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[/] [xucpu/] [trunk/] [target/] [Xilinx/] [1k/] [simulation.wcfg] - Blame information for rev 41

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      clock
      clock
   
   
      label
      clock
      clock
      uc_clock
   
   
      label
      clock
      clock
      dp_clock
   
   
      clka
      clka
   
   
      clka
      clka
   
   
      clka
      clka
   
   
      clka
      clka
   
   
      label
      clka
      clka
      mem_clka
   
   
      reset
      reset
   
   
      clk_valid
      clk_valid
   
   
      switch_in[7:0]
      switch_in[7:0]
   
   
      pushb_in[4:0]
      pushb_in[4:0]
   
   
      led_out[7:0]
      led_out[7:0]
   
   
      pc[14:0]
      pc[14:0]
   
   
      reg_a[3:0]
      reg_a[3:0]
   
   
      reg_b[3:0]
      reg_b[3:0]
   
   
      op_sel[3:0]
      op_sel[3:0]
   
   
      data_in[15:0]
      data_in[15:0]
   
   
      memw
      memw
   
   
      memr
      memr
   
   
      [3]
      addra[3]
   
   
      doa[31:0]
      doa[31:0]
   
   
      wea[3:0]
      wea[3:0]
   


Line No.	Rev	Author	Line
1	4	lcdsgmtr
2
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22
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24			`clock`
25			`clock`
26
27
28			`label`
29			`clock`
30			`clock`
31			`uc_clock`
32
33
34			`label`
35			`clock`
36			`clock`
37			`dp_clock`
38
39
40			`clka`
41			`clka`
42
43
44			`clka`
45			`clka`
46
47
48			`clka`
49			`clka`
50
51
52			`clka`
53			`clka`
54
55
56			`label`
57			`clka`
58			`clka`
59			`mem_clka`
60
61
62			`reset`
63			`reset`
64
65
66			`clk_valid`
67			`clk_valid`
68
69
70			`switch_in[7:0]`
71			`switch_in[7:0]`
72
73
74			`pushb_in[4:0]`
75			`pushb_in[4:0]`
76
77
78			`led_out[7:0]`
79			`led_out[7:0]`
80
81
82			`pc[14:0]`
83			`pc[14:0]`
84
85
86			`reg_a[3:0]`
87			`reg_a[3:0]`
88
89
90			`reg_b[3:0]`
91			`reg_b[3:0]`
92
93
94			`op_sel[3:0]`
95			`op_sel[3:0]`
96
97
98			`data_in[15:0]`
99			`data_in[15:0]`
100
101
102			`memw`
103			`memw`
104
105
106			`memr`
107			`memr`
108
109
110			`[3]`
111			`addra[3]`
112
113
114			`doa[31:0]`
115			`doa[31:0]`
116
117
118			`wea[3:0]`
119			`wea[3:0]`
120
121

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[/] [xucpu/] [trunk/] [target/] [Xilinx/] [1k/] [simulation.wcfg] - Blame information for rev 41