URL https://opencores.org/ocsvn/xucpu/xucpu/trunk

Subversion Repositories xucpu

[/] [xucpu/] [trunk/] [target/] [Xilinx/] [1k/] [startup_sim.wcfg] - Blame information for rev 41

Details | Compare with Previous | View Log




   
   
   
      
         
            
            
            
            
            
            
            
            
            
            
            
            
            
            
            
            
         
      
   
   
   
      clock
      clock
   
   
      reset
      reset
   
   
      rst
      rst
   
   
      clk_out
      clk_out
   
   
      pc_out[14:0]
      pc_out[14:0]
   
   
      q[14:0]
      q[14:0]
   
   
      address_reg_2[9:0]
      address_reg_2[9:0]
   
   
      label
      q2[15:0]
      q2[15:0]
      INSTRUCTION
   
   
      label
      q[15:0]
      q[15:0]
      IR_Q
   
   
      label
      q[15:0]
      q[15:0]
      DR_Q
   
   
      curr_state
      curr_state
   
   
      pc_src[2:0]
      pc_src[2:0]
   
   
      ld_pc
      ld_pc
   
   
      ld_ir
      ld_ir
   
   
      ld_dp
      ld_dp
   
   
      operation[3:0]
      operation[3:0]
   
   
      reg_addr_a[3:0]
      reg_addr_a[3:0]
   
   
      reg_addr_b[3:0]
      reg_addr_b[3:0]
   
   
      reg_src[2:0]
      reg_src[2:0]
   
   
      y[15:0]
      y[15:0]
   
   
      d[15:0]
      d[15:0]
   
   
      reg_wr
      reg_wr
   
   
      [0]
      reg[0]
   
   
      [1]
      reg[1]
   
   
      [2]
      reg[2]
   
   
      [3]
      reg[3]
   
   
      Memory
      label
      128 128 255
      230 230 230
   
   
      data_address[14:0]
      data_address[14:0]
   
   
      databus_write[15:0]
      databus_write[15:0]
   
   
      mem_wr
      mem_wr
   
   
      bus_sel[2:0]
      bus_sel[2:0]
   
   
      gpio_1
      gpio_1
   
   
      ena
      ena
   
   
      we
      we
   
   
      port_out[7:0]
      port_out[7:0]
   


Line No.	Rev	Author	Line
1	4	lcdsgmtr
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29			`clock`
30			`clock`
31
32
33			`reset`
34			`reset`
35
36
37			`rst`
38			`rst`
39
40
41			`clk_out`
42			`clk_out`
43
44
45			`pc_out[14:0]`
46			`pc_out[14:0]`
47
48
49			`q[14:0]`
50			`q[14:0]`
51
52
53			`address_reg_2[9:0]`
54			`address_reg_2[9:0]`
55
56
57			`label`
58			`q2[15:0]`
59			`q2[15:0]`
60			`INSTRUCTION`
61
62
63			`label`
64			`q[15:0]`
65			`q[15:0]`
66			`IR_Q`
67
68
69			`label`
70			`q[15:0]`
71			`q[15:0]`
72			`DR_Q`
73
74
75			`curr_state`
76			`curr_state`
77
78
79			`pc_src[2:0]`
80			`pc_src[2:0]`
81
82
83			`ld_pc`
84			`ld_pc`
85
86
87			`ld_ir`
88			`ld_ir`
89
90
91			`ld_dp`
92			`ld_dp`
93
94
95			`operation[3:0]`
96			`operation[3:0]`
97
98
99			`reg_addr_a[3:0]`
100			`reg_addr_a[3:0]`
101
102
103			`reg_addr_b[3:0]`
104			`reg_addr_b[3:0]`
105
106
107			`reg_src[2:0]`
108			`reg_src[2:0]`
109
110
111			`y[15:0]`
112			`y[15:0]`
113
114
115			`d[15:0]`
116			`d[15:0]`
117
118
119			`reg_wr`
120			`reg_wr`
121
122
123			`[0]`
124			`reg[0]`
125
126
127			`[1]`
128			`reg[1]`
129
130
131			`[2]`
132			`reg[2]`
133
134
135			`[3]`
136			`reg[3]`
137
138
139			`Memory`
140			`label`
141			`128 128 255`
142			`230 230 230`
143
144
145			`data_address[14:0]`
146			`data_address[14:0]`
147
148
149			`databus_write[15:0]`
150			`databus_write[15:0]`
151
152
153			`mem_wr`
154			`mem_wr`
155
156
157			`bus_sel[2:0]`
158			`bus_sel[2:0]`
159
160
161			`gpio_1`
162			`gpio_1`
163
164
165			`ena`
166			`ena`
167
168
169			`we`
170			`we`
171
172
173			`port_out[7:0]`
174			`port_out[7:0]`
175
176

Browse

Tools

Subversion Repositories xucpu

[/] [xucpu/] [trunk/] [target/] [Xilinx/] [1k/] [startup_sim.wcfg] - Blame information for rev 41