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[/] [xucpu/] [trunk/] [target/] [Xilinx/] [1k/] [startup_sim_pr.wcfg] - Blame information for rev 41

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      clock
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      clock
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      reset
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      reset
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      clk_out
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      clk_out
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      rst
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      rst
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      y[14:0]
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      y[14:0]
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      ld_pc
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      ld_pc
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      ld_ir
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      ld_ir
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      ld_dp
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      ld_dp
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      q[14:0]
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      q[14:0]
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      a2[9:0]
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      a2[9:0]
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      q2[15:0]
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      q2[15:0]
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      q[15:0]
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      q[15:0]
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      q[15:0]
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      q[15:0]
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      operation[3:0]
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      operation[3:0]
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      reg_addr_a[3:0]
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      reg_addr_a[3:0]
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      reg_addr_b[3:0]
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      reg_addr_b[3:0]
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      reg_wr
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      reg_wr
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      reg_src[2:0]
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      reg_src[2:0]
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      d[15:0]
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      d[15:0]
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      q1[15:0]
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      q1[15:0]
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      label
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      q2[15:0]
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      q2[15:0]
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      q2[15:0]
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      zero
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      zero
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      Memory
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      label
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      128 128 255
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      230 230 230
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      mem_wr
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      mem_wr
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      data_address[14:0]
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      data_address[14:0]
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      databus_write[15:0]
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      databus_write[15:0]
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      led_out[7:0]
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      led_out[7:0]
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      gpio_1
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      gpio_1
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