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/*******************************************************************************************/
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/** **/
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/** COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
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/** **/
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/** alu math module Rev 0.0 07/29/2011 **/
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/** **/
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/*******************************************************************************************/
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module alu_math (adder_c, adder_hc, adder_out, adder_ov, alua_in, alub_in, aluop_reg,
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carry_bit, carry_daa, daa_op, word_op);
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input carry_bit; /* carry flag */
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input carry_daa; /* carry for daa */
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input daa_op; /* daa operation */
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input word_op; /* word operation */
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input [15:0] alua_in; /* alu a input */
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input [15:0] alub_in; /* alu b input */
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input [`AOP_IDX:0] aluop_reg; /* alu operation control subset */
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output adder_c; /* alu math carry result */
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output adder_hc; /* alu math half-carry result */
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output adder_ov; /* alu math overflow result */
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output [15:0] adder_out; /* alu math result */
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/*****************************************************************************************/
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/* */
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/* signal declarations */
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/* */
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/*****************************************************************************************/
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wire adder_c; /* alu math carry out */
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wire adder_hc; /* alu math half-carry out */
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wire [15:8] bsign_ext; /* alu b sign extend */
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wire [15:0] adder_out; /* alu math out */
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reg alu_cin; /* alu math carry in */
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reg adder_ov; /* alu math overflow out */
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reg [4:0] alu0_out; /* alu math nibble 0 */
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reg [4:0] alu1_out; /* alu math nibble 1 */
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reg [4:0] alu2_out; /* alu math nibble 2 */
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reg [4:0] alu3_out; /* alu math nibble 3 */
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/*****************************************************************************************/
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/* */
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/* alu math carry input, sign extend */
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/* */
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/*****************************************************************************************/
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always @ (aluop_reg or carry_bit) begin
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casex (aluop_reg) //synopsys parallel_case
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`AOP_ADC,
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`AOP_BADC,
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`AOP_SBC,
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`AOP_BSBC: alu_cin = carry_bit;
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default: alu_cin = 1'b0;
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endcase
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end
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assign bsign_ext = {alub_in[7], alub_in[7], alub_in[7], alub_in[7],
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alub_in[7], alub_in[7], alub_in[7], alub_in[7]};
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/*****************************************************************************************/
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/* */
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/* alu math function unit */
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/* */
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/*****************************************************************************************/
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always @ (aluop_reg or alua_in or alub_in or alu_cin) begin
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casex (aluop_reg) //synopsys parallel_case
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`AOP_SUB,
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`AOP_BSUB,
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`AOP_SBC,
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`AOP_BSBC: alu0_out = alua_in[3:0] - alub_in[3:0] - alu_cin;
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default: alu0_out = alua_in[3:0] + alub_in[3:0] + alu_cin;
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endcase
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end
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always @ (aluop_reg or alua_in or alub_in or alu0_out) begin
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casex (aluop_reg) //synopsys parallel_case
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`AOP_SUB,
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`AOP_BSUB,
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`AOP_SBC,
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`AOP_BSBC: alu1_out = alua_in[7:4] - alub_in[7:4] - alu0_out[4];
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default: alu1_out = alua_in[7:4] + alub_in[7:4] + alu0_out[4];
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endcase
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end
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always @ (aluop_reg or alua_in or alub_in or alu1_out or bsign_ext) begin
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casex (aluop_reg) //synopsys parallel_case
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`AOP_ADS: alu2_out = alua_in[11:8] + bsign_ext[11:8] + alu1_out[4];
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`AOP_SUB,
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`AOP_BSUB,
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`AOP_SBC,
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`AOP_BSBC: alu2_out = alua_in[11:8] - alub_in[11:8] - alu1_out[4];
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default: alu2_out = alua_in[11:8] + alub_in[11:8] + alu1_out[4];
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endcase
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end
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always @ (aluop_reg or alua_in or alub_in or alu2_out or bsign_ext) begin
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casex (aluop_reg) //synopsys parallel_case
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`AOP_ADS: alu3_out = alua_in[15:12] + bsign_ext[15:12] + alu2_out[4];
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`AOP_SUB,
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`AOP_BSUB,
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`AOP_SBC,
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`AOP_BSBC: alu3_out = alua_in[15:12] - alub_in[15:12] - alu2_out[4];
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default: alu3_out = alua_in[15:12] + alub_in[15:12] + alu2_out[4];
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endcase
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end
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assign adder_out = {alu3_out[3:0], alu2_out[3:0], alu1_out[3:0], alu0_out[3:0]};
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/*****************************************************************************************/
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/* */
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/* alu math flag generation */
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/* */
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/*****************************************************************************************/
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assign adder_c = (word_op) ? alu3_out[4] :
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(daa_op) ? carry_daa : alu1_out[4];
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assign adder_hc = (word_op) ? alu2_out[4] : alu0_out[4];
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always @ (aluop_reg or alua_in or alub_in or alu3_out or alu1_out or bsign_ext) begin
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casex (aluop_reg) //synopsys parallel_case
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`AOP_ADC,
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`AOP_ADD: adder_ov = (!alu3_out[3] && alua_in[15] && alub_in[15]) ||
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( alu3_out[3] && !alua_in[15] && !alub_in[15]);
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`AOP_BADC,
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`AOP_BADD,
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`AOP_BDEC: adder_ov = (!alu1_out[3] && alua_in[7] && alub_in[7]) ||
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( alu1_out[3] && !alua_in[7] && !alub_in[7]);
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`AOP_SBC,
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`AOP_SUB: adder_ov = (!alu3_out[3] && alua_in[15] && !alub_in[15]) ||
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( alu3_out[3] && !alua_in[15] && alub_in[15]);
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`AOP_BSBC,
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`AOP_BSUB: adder_ov = (!alu1_out[3] && alua_in[7] && !alub_in[7]) ||
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( alu1_out[3] && !alua_in[7] && alub_in[7]);
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default: adder_ov = 1'b0;
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endcase
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end
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endmodule
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