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[/] [y80e/] [trunk/] [rtl/] [machine.v] - Blame information for rev 12

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1 12 bsa
/*******************************************************************************************/
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/**                                                                                       **/
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/** COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED          **/
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/**                                                                                       **/
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/** state machine module                                              Rev 0.0  07/01/2011 **/
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/**                                                                                       **/
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/*******************************************************************************************/
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module machine (ld_ctrl, state_reg, wait_st, clkc, dmar_reg, intr_reg, ld_inta, ld_wait,
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                resetb, state_nxt, wait_req);
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  input         clkc;          /* main cpu clock                                           */
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  input         dmar_reg;      /* latched dma request                                      */
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  input         intr_reg;      /* latched interrupt request                                */
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  input         ld_inta;       /* load interrupt request                                   */
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  input         ld_wait;       /* load wait request                                        */
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  input         resetb;        /* internal reset                                           */
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  input         wait_req;      /* wait request                                             */
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  input   [`STATE_IDX:0] state_nxt;   /* next processor state                              */
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  output        ld_ctrl;       /* load control register                                    */
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  output        wait_st;       /* wait state identifier                                    */
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  output  [`STATE_IDX:0] state_reg;   /* current processor state                           */
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  /*****************************************************************************************/
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  /*                                                                                       */
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  /* signal declarations                                                                   */
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  /*                                                                                       */
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  /*****************************************************************************************/
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  wire         ld_ctrl;                                    /* advance state                */
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  reg          wait_st;                                    /* wait state - inhibit op      */
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  reg  [`STATE_IDX:0] state_reg;                           /* current processor state      */
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  /*****************************************************************************************/
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  /*                                                                                       */
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  /* processor state machine                                                               */
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  /*                                                                                       */
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  /*****************************************************************************************/
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  assign ld_ctrl = !ld_wait || !wait_req;
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  always @ (posedge clkc or negedge resetb) begin
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    if (!resetb) wait_st   <= 1'b0;
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    else         wait_st   <= !ld_ctrl;
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    end
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  always @ (posedge clkc or negedge resetb) begin
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    if      (!resetb) state_reg <= `sRST;
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    else if (ld_ctrl) state_reg <= (ld_inta && dmar_reg) ? `sDMA1 :
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                                   (ld_inta && intr_reg) ? `sINTA : state_nxt;
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    end
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  endmodule
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