URL https://opencores.org/ocsvn/y80e/y80e/trunk

Subversion Repositories y80e

[/] [y80e/] [trunk/] [rtl/] [top_levl.v] - Blame information for rev 8

Go to most recent revision | Details | Compare with Previous | View Log


/*******************************************************************************************/
/**                                                                                       **/
/** ORIGINAL COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
/** COPYRIGHT (C) 2012, SERGEY BELYASHOV                                                  **/
/**                                                                                       **/
/** Y80e processor test bench                                         Rev 0.0  06/18/2012 **/
/**                                                                                       **/
/*******************************************************************************************/
`timescale 1ns / 10ps                                      /* set time scale               */
`include "version.v"                                       /* select version               */
`include "hierarchy.v"                                     /* include sources              */
 
module top_levl;
 
  wire        DMA_ACK;                                     /* dma acknowledge              */
  wire        HALT_TRAN;                                   /* halt transaction             */
  wire        IACK_TRAN;                                   /* int ack transaction          */
  wire        IO_READ;                                     /* i/o read/write status        */
  wire        IO_STROBE;                                   /* i/o strobe                   */
  wire        IO_TRAN;                                     /* i/o transaction              */
  wire        IVEC_RD;                                     /* int vector read strobe       */
  wire        MEM_RD;                                      /* mem read strobe              */
  wire        MEM_TRAN;                                    /* mem transaction              */
  wire        MEM_WR;                                      /* mem write strobe             */
  wire        RETI_TRAN;                                   /* reti transaction             */
  wire        T1;                                          /* first clock of transaction   */
  wire  [7:0] IO_DATA_OUT;                                 /* i/o data output bus          */
  wire  [7:0] MEM_DATA_OUT;                                /* mem data output bus          */
  wire [15:0] IO_ADDR;                                     /* i/o address bus              */
  wire [15:0] MEM_ADDR;                                    /* mem address bus              */
 
  reg         CLEARB;                                      /* master (test) reset          */
  reg         CLKC;                                        /* clock                        */
  reg         DMA_REQ;                                     /* dma request                  */
  reg         INT_REQ;                                     /* interrupt request            */
  reg         NMI_REQ;                                     /* non-maskable interrupt req   */
  reg         RESETB;                                      /* internal (user) reset        */
  reg         WAIT_REQ;                                    /* wait request                 */
  reg   [7:0] IO_DATA_IN;                                  /* i/o data input bus           */
  reg   [7:0] IVEC_DATA_IN;                                /* vector input bus             */
  reg   [7:0] MEM_DATA_IN;                                 /* mem data input bus           */
 
  /*****************************************************************************************/
  /*                                                                                       */
  /* testbench internal variables                                                          */
  /*                                                                                       */
  /*****************************************************************************************/
  reg         CLR_INT;                                     /* deassert interrupt           */
  reg         CLR_NMI;                                     /* deassert nmi                 */
  reg         DISABLE_BREQ;                                /* bus req generator control    */
  reg         DISABLE_INT;                                 /* interrupt generator control  */
  reg         DISABLE_WAIT;                                /* wait generator control       */
  reg         INT_TYPE;                                    /* int type during bus req      */
  reg         PAT_DONE;                                    /* pattern done flag            */
  reg         TRIG_INT;                                    /* assert interrupt             */
  reg         TRIG_NMI;                                    /* assert nmi                   */
  reg   [3:0] PAT_CNT;                                     /* counter to track patterns    */
  reg  [15:0] CMP_ERR_L;                                   /* error counter                */
 
  reg         wait_dly;                                    /* wait request state machine   */
  reg   [5:0] breq_mach;                                   /* bus request state machine    */
 
  reg         TREF0, TREF1, TREF2, TREF3, TREF4;           /* timing generator             */
  reg         TREF5, TREF6, TREF7, TREF8, TREF9;
 
  /*****************************************************************************************/
  /*                                                                                       */
  /* read memory and write data compare memory                                             */
  /*                                                                                       */
  /*****************************************************************************************/
  reg   [7:0] rdmem [0:65535];
  reg   [7:0] wrmem [0:65535];
 
  wire  [7:0] wr_data = (MEM_TRAN) ? wrmem[MEM_ADDR] :
                        (IO_TRAN)  ? wrmem[IO_ADDR]  : 8'hxx;
 
  wire  [7:0] rd_data   = rdmem[MEM_ADDR];
  wire  [7:0] iord_data = rdmem[IO_ADDR];
 
  always @ (posedge TREF6) begin
    IO_DATA_IN   = (IO_TRAN && IO_READ && IO_STROBE && !WAIT_REQ) ? iord_data : 8'hxx;
    MEM_DATA_IN  = (MEM_TRAN && MEM_RD && !WAIT_REQ) ? rd_data : 8'hxx;
    end
 
  always @ (posedge TREF6) begin
    IVEC_DATA_IN = (IACK_TRAN && IVEC_RD && !WAIT_REQ) ? rd_data : 8'hxx;
    end
 
  always @ (posedge TREF0) begin
    IO_DATA_IN   = 8'hxx;
    MEM_DATA_IN  = 8'hxx;
    IVEC_DATA_IN = 8'hxx;
    end
 
  /*****************************************************************************************/
  /*                                                                                       */
  /* instantiate the design                                                                */
  /*                                                                                       */
  /*****************************************************************************************/
  y80_top Y80 ( .dma_ack(DMA_ACK), .halt_tran(HALT_TRAN), .iack_tran(IACK_TRAN),
                .io_addr_out(IO_ADDR), .io_data_out(IO_DATA_OUT), .io_read(IO_READ),
                .io_strobe(IO_STROBE), .io_tran(IO_TRAN), .ivec_rd(IVEC_RD),
                .mem_addr_out(MEM_ADDR), .mem_data_out(MEM_DATA_OUT), .mem_rd(MEM_RD),
                .mem_tran(MEM_TRAN), .mem_wr(MEM_WR), .reti_tran(RETI_TRAN), .t1(T1),
                .clearb(CLEARB), .clkc(CLKC), .dma_req(DMA_REQ), .int_req(INT_REQ),
                .io_data_in(IO_DATA_IN), .ivec_data_in(IVEC_DATA_IN),
                .mem_data_in(MEM_DATA_IN), .nmi_req(NMI_REQ), .resetb(RESETB),
                .wait_req(WAIT_REQ) );
 
  /*****************************************************************************************/
  /*                                                                                       */
  /* timing generator                                                                      */
  /*                                                                                       */
  /*****************************************************************************************/
  initial begin
    TREF0 = 1;
    CLKC  = 1;
    end
 
  always begin
    #10 TREF0 <= 1'b0;
        TREF1 <= 1'b1;
    #10 TREF1 <= 1'b0;
        TREF2 <= 1'b1;
    #10 TREF2 <= 1'b0;
        TREF3 <= 1'b1;
    #10 TREF3 <= 1'b0;
        TREF4 <= 1'b1;
    #10 TREF4 <= 1'b0;
        TREF5 <= 1'b1;
    #10 TREF5 <= 1'b0;
        TREF6 <= 1'b1;
    #10 TREF6 <= 1'b0;
        TREF7 <= 1'b1;
    #10 TREF7 <= 1'b0;
        TREF8 <= 1'b1;
    #10 TREF8 <= 1'b0;
        TREF9 <= 1'b1;
    #10 TREF9 <= 1'b0;
        TREF0 <= 1'b1;
    end
 
  always @ (posedge TREF3) CLKC = 0;
  always @ (posedge TREF8) CLKC = 1;
 
  /*****************************************************************************************/
  /*                                                                                       */
  /* initialize input signals                                                              */
  /*                                                                                       */
  /*****************************************************************************************/
  initial begin
    CLEARB    = 1;
    DMA_REQ   = 0;
    INT_REQ   = 0;
    NMI_REQ   = 0;
    RESETB    = 1;
    WAIT_REQ  = 0;
    end
 
  /*****************************************************************************************/
  /*                                                                                       */
  /* initialize testbench variables                                                        */
  /*                                                                                       */
  /*****************************************************************************************/
  initial begin
    breq_mach    = 6'b000000;
    CMP_ERR_L    = 16'h0000;
    CLR_INT      = 0;
    CLR_NMI      = 0;
    DISABLE_BREQ = 1;
    DISABLE_INT  = 1;
    DISABLE_WAIT = 1;
    INT_TYPE     = 0;
    PAT_DONE     = 0;
    TRIG_INT     = 0;
    TRIG_NMI     = 0;
    end
 
  /*****************************************************************************************/
  /*                                                                                       */
  /* reset and clear task                                                                  */
  /*                                                                                       */
  /*****************************************************************************************/
  task resettask;
    begin
      wait(TREF6);
      RESETB   = 0;
      wait(TREF0);
      wait(TREF6);
      wait(TREF0);
      wait(TREF6);
      RESETB   = 1;
      CLR_INT  = 1;
      CLR_NMI  = 1;
      wait(TREF0);
      PAT_DONE = 0;
      end
    endtask
 
  task cleartask;
    begin
      wait(TREF6);
      CLEARB   = 0;
      RESETB   = 0;
      wait(TREF0);
      wait(TREF6);
      wait(TREF0);
      wait(TREF6);
      CLEARB   = 1;
      RESETB   = 1;
      CLR_INT  = 1;
      CLR_NMI  = 1;
      wait(TREF0);
      PAT_DONE = 0;
      end
    endtask
 
  /*****************************************************************************************/
  /*                                                                                       */
  /* error log                                                                             */
  /*                                                                                       */
  /*****************************************************************************************/
  always @ (posedge TREF4) begin
    if (MEM_WR)                CMP_ERR_L = CMP_ERR_L + (MEM_DATA_OUT != wr_data);
    if (!IO_READ && IO_STROBE) CMP_ERR_L = CMP_ERR_L + (IO_DATA_OUT  != wr_data);
    end
 
  /*****************************************************************************************/
  /*                                                                                       */
  /* end-of-pattern detect                                                                 */
  /*                                                                                       */
  /*****************************************************************************************/
  always @ (posedge TREF4) begin
    PAT_DONE  = (MEM_ADDR[15:0] == 16'h00c3);
    end
 
  /*****************************************************************************************/
  /*                                                                                       */
  /* interrupt/nmi request generator                                                       */
  /*                                                                                       */
  /*****************************************************************************************/
  always @ (posedge TREF4) begin
    TRIG_INT = !((MEM_ADDR[15:13] == 3'b110) && (MEM_ADDR[8:0] == 9'h0ff)) ||
                 DISABLE_INT || |breq_mach;
    TRIG_NMI = !((MEM_ADDR[15:13] == 3'b110) && (MEM_ADDR[8:0] == 9'h1ff)) ||
                 DISABLE_INT || |breq_mach;
    CLR_INT  = (MEM_ADDR[15:13] == 3'b111);
    CLR_NMI  = (MEM_ADDR[15:13] == 3'b111);
    if (T1) INT_TYPE = MEM_ADDR[8];
    end
 
  always @ (negedge TRIG_NMI) begin
    NMI_REQ = 1;
    end
 
  always @ (posedge CLR_NMI) begin
    NMI_REQ = 0;
    end
 
  always @ (negedge TRIG_INT) begin
    INT_REQ = 1;
    end
 
  always @ (posedge CLR_INT) begin
    wait(TREF0);
    wait(TREF4);
    wait(TREF0);
    wait(TREF4);
    INT_REQ = 0;
    end
 
  /*****************************************************************************************/
  /*                                                                                       */
  /* interrupt request generator (during Halt)                                             */
  /*                                                                                       */
  /*****************************************************************************************/
  integer j;
 
  always @ (posedge HALT_TRAN) begin
    for (j=0; j < 10; j=j+1) begin
      wait (TREF6);
      wait (TREF0);
      end
    wait (TREF6);
    INT_REQ = HALT_TRAN && !INT_TYPE;
    NMI_REQ = HALT_TRAN &&  INT_TYPE;
    wait (TREF0);
    for (j=0; j < 12; j=j+1) begin
      wait (TREF6);
      wait (TREF0);
      end
    INT_REQ = 0;
    NMI_REQ = 0;
    wait (TREF6);
    wait (TREF0);
    wait (TREF6);
    NMI_REQ = HALT_TRAN &&  INT_TYPE;
    wait (TREF0);
    wait (TREF6);
    wait (TREF0);
    NMI_REQ = 0;
    end
 
  /*****************************************************************************************/
  /*                                                                                       */
  /* wait request generator                                                                */
  /*                                                                                       */
  /*****************************************************************************************/
  always @ (posedge CLKC) begin
    wait_dly <= T1;
    end
 
  always @ (posedge TREF6) WAIT_REQ = !DISABLE_WAIT && (T1 || wait_dly);
  always @ (posedge TREF9) WAIT_REQ = 1'b0;
 
  /*****************************************************************************************/
  /*                                                                                       */
  /* bus request generator                                                                 */
  /*                                                                                       */
  /*****************************************************************************************/
  always @ (posedge CLKC) begin
    breq_mach <= (DISABLE_BREQ) ? 6'b000000 :
                 (T1)           ? 6'b000001 : {breq_mach[4:0], wait_dly};
    end
 
  always @ (posedge TREF6) DMA_REQ = !DISABLE_BREQ &&
                                     (T1 || |breq_mach[2:0] || (HALT_TRAN && |breq_mach));
 
  /*****************************************************************************************/
  /*                                                                                       */
  /* run the test patterns                                                                 */
  /*                                                                                       */
  /*****************************************************************************************/
  initial begin
    $readmemh("setup_hl.vm", rdmem);
    cleartask;
    wait (PAT_DONE);
 
    DISABLE_INT = 0;                                       /* interrupt generator on       */
 
    resettask;
    CMP_ERR_L = 16'h0000;
    PAT_CNT   = 5'h1;
    $readmemh("blank_xx.vm", rdmem);
    $readmemh("blank_xx.vm", wrmem);
    $readmemh("int_ops.vm",  rdmem);
    $readmemh("int_opsd.vm", wrmem);
    wait (PAT_DONE);
 
    DISABLE_INT  = 1;                                      /* interrupt generator off      */
 
    resettask;
    CMP_ERR_L = 16'h0000;
    PAT_CNT   = 5'h2;
    $readmemh("blank_xx.vm", rdmem);
    $readmemh("blank_xx.vm", wrmem);
    $readmemh("alu_ops.vm", rdmem);
    $readmemh("alu_opsd.vm", wrmem);
    wait (PAT_DONE);
 
    resettask;
    CMP_ERR_L = 16'h0000;
    PAT_CNT   = 5'h3;
    $readmemh("blank_xx.vm", rdmem);
    $readmemh("blank_xx.vm", wrmem);
    $readmemh("dat_mov.vm", rdmem);
    $readmemh("dat_movd.vm", wrmem);
    wait (PAT_DONE);
 
    resettask;
    CMP_ERR_L = 16'h0000;
    PAT_CNT   = 5'h4;
    $readmemh("blank_xx.vm", rdmem);
    $readmemh("blank_xx.vm", wrmem);
    $readmemh("bit_ops.vm", rdmem);
    $readmemh("bit_opsd.vm", wrmem);
    wait (PAT_DONE);
 
    resettask;
    CMP_ERR_L = 16'h0000;
    PAT_CNT   = 5'h5;
    $readmemh("blank_xx.vm", rdmem);
    $readmemh("blank_xx.vm", wrmem);
    $readmemh("jmp_ops.vm", rdmem);
    $readmemh("jmp_opsd.vm", wrmem);
    wait (PAT_DONE);
 
    resettask;
    CMP_ERR_L = 16'h0000;
    PAT_CNT   = 5'h6;
    $readmemh("blank_xx.vm", rdmem);
    $readmemh("blank_xx.vm", wrmem);
    $readmemh("io_ops.vm", rdmem);
    $readmemh("io_opsd.vm", wrmem);
    wait (PAT_DONE);
 
    resettask;
    CMP_ERR_L = 16'h0000;
    PAT_CNT   = 5'h7;
    $readmemh("blank_xx.vm", rdmem);
    $readmemh("blank_xx.vm", wrmem);
    $readmemh("180_ops.vm", rdmem);
    $readmemh("180_opsd.vm", wrmem);
    wait (PAT_DONE);
 
    resettask;
    CMP_ERR_L = 16'h0000;
    PAT_CNT   = 5'h8;
    $readmemh("blank_xx.vm", rdmem);
    $readmemh("blank_xx.vm", wrmem);
    $readmemh("ez8_ops.vm", rdmem);
    $readmemh("ez8_opsd.vm", wrmem);
    wait (PAT_DONE);
 
    DISABLE_INT  = 0;                                      /* interrupt generator on       */
    DISABLE_WAIT = 0;                                      /* wait generator on            */
 
    resettask;
    CMP_ERR_L = 16'h0000;
    PAT_CNT   = 5'h1;
    $readmemh("blank_xx.vm", rdmem);
    $readmemh("blank_xx.vm", wrmem);
    $readmemh("int_ops.vm", rdmem);
    $readmemh("int_opsd.vm", wrmem);
    wait (PAT_DONE);
 
    DISABLE_INT  = 1;                                      /* interrupt generator off      */
 
    resettask;
    CMP_ERR_L = 16'h0000;
    PAT_CNT   = 5'h2;
    $readmemh("blank_xx.vm", rdmem);
    $readmemh("blank_xx.vm", wrmem);
    $readmemh("alu_ops.vm", rdmem);
    $readmemh("alu_opsd.vm", wrmem);
    wait (PAT_DONE);
 
    resettask;
    CMP_ERR_L = 16'h0000;
    PAT_CNT   = 5'h3;
    $readmemh("blank_xx.vm", rdmem);
    $readmemh("blank_xx.vm", wrmem);
    $readmemh("dat_mov.vm", rdmem);
    $readmemh("dat_movd.vm", wrmem);
    wait (PAT_DONE);
 
    resettask;
    CMP_ERR_L = 16'h0000;
    PAT_CNT   = 5'h4;
    $readmemh("blank_xx.vm", rdmem);
    $readmemh("blank_xx.vm", wrmem);
    $readmemh("bit_ops.vm", rdmem);
    $readmemh("bit_opsd.vm", wrmem);
    wait (PAT_DONE);
 
    resettask;
    CMP_ERR_L = 16'h0000;
    PAT_CNT   = 5'h5;
    $readmemh("blank_xx.vm", rdmem);
    $readmemh("blank_xx.vm", wrmem);
    $readmemh("jmp_ops.vm", rdmem);
    $readmemh("jmp_opsd.vm", wrmem);
    wait (PAT_DONE);
 
    resettask;
    CMP_ERR_L = 16'h0000;
    PAT_CNT   = 5'h6;
    $readmemh("blank_xx.vm", rdmem);
    $readmemh("blank_xx.vm", wrmem);
    $readmemh("io_ops.vm", rdmem);
    $readmemh("io_opsd.vm", wrmem);
    wait (PAT_DONE);
 
    resettask;
    CMP_ERR_L = 16'h0000;
    PAT_CNT   = 5'h7;
    $readmemh("blank_xx.vm", rdmem);
    $readmemh("blank_xx.vm", wrmem);
    $readmemh("180_ops.vm", rdmem);
    $readmemh("180_opsd.vm", wrmem);
    wait (PAT_DONE);
 
    resettask;
    CMP_ERR_L = 16'h0000;
    PAT_CNT   = 5'h8;
    $readmemh("blank_xx.vm", rdmem);
    $readmemh("blank_xx.vm", wrmem);
    $readmemh("ez8_ops.vm", rdmem);
    $readmemh("ez8_opsd.vm", wrmem);
    wait (PAT_DONE);
 
    DISABLE_INT  = 0;                                      /* interrupt generator on       */
    DISABLE_BREQ = 0;                                      /* bus req generator on         */
    DISABLE_WAIT = 1;                                      /* wait generator off           */
 
    resettask;
    CMP_ERR_L = 16'h0000;
    PAT_CNT   = 5'h1;
    $readmemh("blank_xx.vm", rdmem);
    $readmemh("blank_xx.vm", wrmem);
    $readmemh("int_ops.vm", rdmem);
    $readmemh("int_opss.vm", wrmem);
    wait (PAT_DONE);
 
    DISABLE_INT  = 1;                                      /* interrupt generator off      */
 
    resettask;
    CMP_ERR_L = 16'h0000;
    PAT_CNT   = 5'h2;
    $readmemh("blank_xx.vm", rdmem);
    $readmemh("blank_xx.vm", wrmem);
    $readmemh("alu_ops.vm", rdmem);
    $readmemh("alu_opsd.vm", wrmem);
    wait (PAT_DONE);
 
    resettask;
    CMP_ERR_L = 16'h0000;
    PAT_CNT   = 5'h3;
    $readmemh("blank_xx.vm", rdmem);
    $readmemh("blank_xx.vm", wrmem);
    $readmemh("dat_mov.vm", rdmem);
    $readmemh("dat_movd.vm", wrmem);
    wait (PAT_DONE);
 
    resettask;
    CMP_ERR_L = 16'h0000;
    PAT_CNT   = 5'h4;
    $readmemh("blank_xx.vm", rdmem);
    $readmemh("blank_xx.vm", wrmem);
    $readmemh("bit_ops.vm", rdmem);
    $readmemh("bit_opsd.vm", wrmem);
    wait (PAT_DONE);
 
    resettask;
    CMP_ERR_L = 16'h0000;
    PAT_CNT   = 5'h5;
    $readmemh("blank_xx.vm", rdmem);
    $readmemh("blank_xx.vm", wrmem);
    $readmemh("jmp_ops.vm", rdmem);
    $readmemh("jmp_opsd.vm", wrmem);
    wait (PAT_DONE);
 
    resettask;
    CMP_ERR_L = 16'h0000;
    PAT_CNT   = 5'h6;
    $readmemh("blank_xx.vm", rdmem);
    $readmemh("blank_xx.vm", wrmem);
    $readmemh("io_ops.vm", rdmem);
    $readmemh("io_opsd.vm", wrmem);
    wait (PAT_DONE);
 
    resettask;
    CMP_ERR_L = 16'h0000;
    PAT_CNT   = 5'h7;
    $readmemh("blank_xx.vm", rdmem);
    $readmemh("blank_xx.vm", wrmem);
    $readmemh("180_ops.vm", rdmem);
    $readmemh("180_opsd.vm", wrmem);
    wait (PAT_DONE);
 
    resettask;
    CMP_ERR_L = 16'h0000;
    PAT_CNT   = 5'h8;
    $readmemh("blank_xx.vm", rdmem);
    $readmemh("blank_xx.vm", wrmem);
    $readmemh("ez8_ops.vm", rdmem);
    $readmemh("ez8_opsd.vm", wrmem);
    wait (PAT_DONE);
 
    $stop;
    end
 
  endmodule
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Line No.	Rev	Author	Line
1	6	bsa	`/*******************************************************************************************/`
2			`/ /`
3			`/ ORIGINAL COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED /`
4			`/ COPYRIGHT (C) 2012, SERGEY BELYASHOV /`
5			`/ /`
6	8	bsa	`/ Y80e processor test bench Rev 0.0 06/18/2012 /`
7	6	bsa	`/ /`
8			`/*******************************************************************************************/`
9			`timescale 1ns / 10ps /* set time scale */
10			`include "version.v" /* select version */
11			`include "hierarchy.v" /* include sources */
12
13			`module top_levl;`
14
15			`wire DMA_ACK; /* dma acknowledge */`
16			`wire HALT_TRAN; /* halt transaction */`
17			`wire IACK_TRAN; /* int ack transaction */`
18			`wire IO_READ; /* i/o read/write status */`
19			`wire IO_STROBE; /* i/o strobe */`
20			`wire IO_TRAN; /* i/o transaction */`
21			`wire IVEC_RD; /* int vector read strobe */`
22			`wire MEM_RD; /* mem read strobe */`
23			`wire MEM_TRAN; /* mem transaction */`
24			`wire MEM_WR; /* mem write strobe */`
25			`wire RETI_TRAN; /* reti transaction */`
26			`wire T1; /* first clock of transaction */`
27			`wire [7:0] IO_DATA_OUT; /* i/o data output bus */`
28			`wire [7:0] MEM_DATA_OUT; /* mem data output bus */`
29			`wire [15:0] IO_ADDR; /* i/o address bus */`
30			`wire [15:0] MEM_ADDR; /* mem address bus */`
31
32			`reg CLEARB; /* master (test) reset */`
33			`reg CLKC; /* clock */`
34			`reg DMA_REQ; /* dma request */`
35			`reg INT_REQ; /* interrupt request */`
36			`reg NMI_REQ; /* non-maskable interrupt req */`
37			`reg RESETB; /* internal (user) reset */`
38			`reg WAIT_REQ; /* wait request */`
39			`reg [7:0] IO_DATA_IN; /* i/o data input bus */`
40			`reg [7:0] IVEC_DATA_IN; /* vector input bus */`
41			`reg [7:0] MEM_DATA_IN; /* mem data input bus */`
42
43			`/*****************************************************************************************/`
44			`/* */`
45			`/* testbench internal variables */`
46			`/* */`
47			`/*****************************************************************************************/`
48			`reg CLR_INT; /* deassert interrupt */`
49			`reg CLR_NMI; /* deassert nmi */`
50			`reg DISABLE_BREQ; /* bus req generator control */`
51			`reg DISABLE_INT; /* interrupt generator control */`
52			`reg DISABLE_WAIT; /* wait generator control */`
53			`reg INT_TYPE; /* int type during bus req */`
54			`reg PAT_DONE; /* pattern done flag */`
55			`reg TRIG_INT; /* assert interrupt */`
56			`reg TRIG_NMI; /* assert nmi */`
57	8	bsa	`reg [3:0] PAT_CNT; /* counter to track patterns */`
58	6	bsa	`reg [15:0] CMP_ERR_L; /* error counter */`
59
60			`reg wait_dly; /* wait request state machine */`
61			`reg [5:0] breq_mach; /* bus request state machine */`
62
63			`reg TREF0, TREF1, TREF2, TREF3, TREF4; /* timing generator */`
64			`reg TREF5, TREF6, TREF7, TREF8, TREF9;`
65
66			`/*****************************************************************************************/`
67			`/* */`
68			`/* read memory and write data compare memory */`
69			`/* */`
70			`/*****************************************************************************************/`
71			`reg [7:0] rdmem [0:65535];`
72			`reg [7:0] wrmem [0:65535];`
73
74			`wire [7:0] wr_data = (MEM_TRAN) ? wrmem[MEM_ADDR] :`
75			`(IO_TRAN) ? wrmem[IO_ADDR] : 8'hxx;`
76
77			`wire [7:0] rd_data = rdmem[MEM_ADDR];`
78			`wire [7:0] iord_data = rdmem[IO_ADDR];`
79
80			`always @ (posedge TREF6) begin`
81			`IO_DATA_IN = (IO_TRAN && IO_READ && IO_STROBE && !WAIT_REQ) ? iord_data : 8'hxx;`
82			`MEM_DATA_IN = (MEM_TRAN && MEM_RD && !WAIT_REQ) ? rd_data : 8'hxx;`
83			`end`
84
85			`always @ (posedge TREF6) begin`
86			`IVEC_DATA_IN = (IACK_TRAN && IVEC_RD && !WAIT_REQ) ? rd_data : 8'hxx;`
87			`end`
88
89			`always @ (posedge TREF0) begin`
90			`IO_DATA_IN = 8'hxx;`
91			`MEM_DATA_IN = 8'hxx;`
92			`IVEC_DATA_IN = 8'hxx;`
93			`end`
94
95			`/*****************************************************************************************/`
96			`/* */`
97			`/* instantiate the design */`
98			`/* */`
99			`/*****************************************************************************************/`
100			`y80_top Y80 ( .dma_ack(DMA_ACK), .halt_tran(HALT_TRAN), .iack_tran(IACK_TRAN),`
101			`.io_addr_out(IO_ADDR), .io_data_out(IO_DATA_OUT), .io_read(IO_READ),`
102			`.io_strobe(IO_STROBE), .io_tran(IO_TRAN), .ivec_rd(IVEC_RD),`
103			`.mem_addr_out(MEM_ADDR), .mem_data_out(MEM_DATA_OUT), .mem_rd(MEM_RD),`
104			`.mem_tran(MEM_TRAN), .mem_wr(MEM_WR), .reti_tran(RETI_TRAN), .t1(T1),`
105			`.clearb(CLEARB), .clkc(CLKC), .dma_req(DMA_REQ), .int_req(INT_REQ),`
106			`.io_data_in(IO_DATA_IN), .ivec_data_in(IVEC_DATA_IN),`
107			`.mem_data_in(MEM_DATA_IN), .nmi_req(NMI_REQ), .resetb(RESETB),`
108			`.wait_req(WAIT_REQ) );`
109
110			`/*****************************************************************************************/`
111			`/* */`
112			`/* timing generator */`
113			`/* */`
114			`/*****************************************************************************************/`
115			`initial begin`
116			`TREF0 = 1;`
117			`CLKC = 1;`
118			`end`
119
120			`always begin`
121			`#10 TREF0 <= 1'b0;`
122			`TREF1 <= 1'b1;`
123			`#10 TREF1 <= 1'b0;`
124			`TREF2 <= 1'b1;`
125			`#10 TREF2 <= 1'b0;`
126			`TREF3 <= 1'b1;`
127			`#10 TREF3 <= 1'b0;`
128			`TREF4 <= 1'b1;`
129			`#10 TREF4 <= 1'b0;`
130			`TREF5 <= 1'b1;`
131			`#10 TREF5 <= 1'b0;`
132			`TREF6 <= 1'b1;`
133			`#10 TREF6 <= 1'b0;`
134			`TREF7 <= 1'b1;`
135			`#10 TREF7 <= 1'b0;`
136			`TREF8 <= 1'b1;`
137			`#10 TREF8 <= 1'b0;`
138			`TREF9 <= 1'b1;`
139			`#10 TREF9 <= 1'b0;`
140			`TREF0 <= 1'b1;`
141			`end`
142
143			`always @ (posedge TREF3) CLKC = 0;`
144			`always @ (posedge TREF8) CLKC = 1;`
145
146			`/*****************************************************************************************/`
147			`/* */`
148			`/* initialize input signals */`
149			`/* */`
150			`/*****************************************************************************************/`
151			`initial begin`
152			`CLEARB = 1;`
153			`DMA_REQ = 0;`
154			`INT_REQ = 0;`
155			`NMI_REQ = 0;`
156			`RESETB = 1;`
157			`WAIT_REQ = 0;`
158			`end`
159
160			`/*****************************************************************************************/`
161			`/* */`
162			`/* initialize testbench variables */`
163			`/* */`
164			`/*****************************************************************************************/`
165			`initial begin`
166			`breq_mach = 6'b000000;`
167			`CMP_ERR_L = 16'h0000;`
168			`CLR_INT = 0;`
169			`CLR_NMI = 0;`
170			`DISABLE_BREQ = 1;`
171			`DISABLE_INT = 1;`
172			`DISABLE_WAIT = 1;`
173			`INT_TYPE = 0;`
174			`PAT_DONE = 0;`
175			`TRIG_INT = 0;`
176			`TRIG_NMI = 0;`
177			`end`
178
179			`/*****************************************************************************************/`
180			`/* */`
181			`/* reset and clear task */`
182			`/* */`
183			`/*****************************************************************************************/`
184			`task resettask;`
185			`begin`
186			`wait(TREF6);`
187			`RESETB = 0;`
188			`wait(TREF0);`
189			`wait(TREF6);`
190			`wait(TREF0);`
191			`wait(TREF6);`
192			`RESETB = 1;`
193			`CLR_INT = 1;`
194			`CLR_NMI = 1;`
195			`wait(TREF0);`
196			`PAT_DONE = 0;`
197			`end`
198			`endtask`
199
200			`task cleartask;`
201			`begin`
202			`wait(TREF6);`
203			`CLEARB = 0;`
204			`RESETB = 0;`
205			`wait(TREF0);`
206			`wait(TREF6);`
207			`wait(TREF0);`
208			`wait(TREF6);`
209			`CLEARB = 1;`
210			`RESETB = 1;`
211			`CLR_INT = 1;`
212			`CLR_NMI = 1;`
213			`wait(TREF0);`
214			`PAT_DONE = 0;`
215			`end`
216			`endtask`
217
218			`/*****************************************************************************************/`
219			`/* */`
220			`/* error log */`
221			`/* */`
222			`/*****************************************************************************************/`
223			`always @ (posedge TREF4) begin`
224			`if (MEM_WR) CMP_ERR_L = CMP_ERR_L + (MEM_DATA_OUT != wr_data);`
225			`if (!IO_READ && IO_STROBE) CMP_ERR_L = CMP_ERR_L + (IO_DATA_OUT != wr_data);`
226			`end`
227
228			`/*****************************************************************************************/`
229			`/* */`
230			`/* end-of-pattern detect */`
231			`/* */`
232			`/*****************************************************************************************/`
233			`always @ (posedge TREF4) begin`
234			`PAT_DONE = (MEM_ADDR[15:0] == 16'h00c3);`
235			`end`
236
237			`/*****************************************************************************************/`
238			`/* */`
239			`/* interrupt/nmi request generator */`
240			`/* */`
241			`/*****************************************************************************************/`
242			`always @ (posedge TREF4) begin`
243			`TRIG_INT = !((MEM_ADDR[15:13] == 3'b110) && (MEM_ADDR[8:0] == 9'h0ff)) \|\|`
244			`DISABLE_INT \|\| \|breq_mach;`
245			`TRIG_NMI = !((MEM_ADDR[15:13] == 3'b110) && (MEM_ADDR[8:0] == 9'h1ff)) \|\|`
246			`DISABLE_INT \|\| \|breq_mach;`
247			`CLR_INT = (MEM_ADDR[15:13] == 3'b111);`
248			`CLR_NMI = (MEM_ADDR[15:13] == 3'b111);`
249			`if (T1) INT_TYPE = MEM_ADDR[8];`
250			`end`
251
252			`always @ (negedge TRIG_NMI) begin`
253			`NMI_REQ = 1;`
254			`end`
255
256			`always @ (posedge CLR_NMI) begin`
257			`NMI_REQ = 0;`
258			`end`
259
260			`always @ (negedge TRIG_INT) begin`
261			`INT_REQ = 1;`
262			`end`
263
264			`always @ (posedge CLR_INT) begin`
265			`wait(TREF0);`
266			`wait(TREF4);`
267			`wait(TREF0);`
268			`wait(TREF4);`
269			`INT_REQ = 0;`
270			`end`
271
272			`/*****************************************************************************************/`
273			`/* */`
274			`/* interrupt request generator (during Halt) */`
275			`/* */`
276			`/*****************************************************************************************/`
277			`integer j;`
278
279			`always @ (posedge HALT_TRAN) begin`
280			`for (j=0; j < 10; j=j+1) begin`
281			`wait (TREF6);`
282			`wait (TREF0);`
283			`end`
284			`wait (TREF6);`
285			`INT_REQ = HALT_TRAN && !INT_TYPE;`
286			`NMI_REQ = HALT_TRAN && INT_TYPE;`
287			`wait (TREF0);`
288			`for (j=0; j < 12; j=j+1) begin`
289			`wait (TREF6);`
290			`wait (TREF0);`
291			`end`
292			`INT_REQ = 0;`
293			`NMI_REQ = 0;`
294			`wait (TREF6);`
295			`wait (TREF0);`
296			`wait (TREF6);`
297			`NMI_REQ = HALT_TRAN && INT_TYPE;`
298			`wait (TREF0);`
299			`wait (TREF6);`
300			`wait (TREF0);`
301			`NMI_REQ = 0;`
302			`end`
303
304			`/*****************************************************************************************/`
305			`/* */`
306			`/* wait request generator */`
307			`/* */`
308			`/*****************************************************************************************/`
309			`always @ (posedge CLKC) begin`
310			`wait_dly <= T1;`
311			`end`
312
313			`always @ (posedge TREF6) WAIT_REQ = !DISABLE_WAIT && (T1 \|\| wait_dly);`
314			`always @ (posedge TREF9) WAIT_REQ = 1'b0;`
315
316			`/*****************************************************************************************/`
317			`/* */`
318			`/* bus request generator */`
319			`/* */`
320			`/*****************************************************************************************/`
321			`always @ (posedge CLKC) begin`
322			`breq_mach <= (DISABLE_BREQ) ? 6'b000000 :`
323			`(T1) ? 6'b000001 : {breq_mach[4:0], wait_dly};`
324			`end`
325
326			`always @ (posedge TREF6) DMA_REQ = !DISABLE_BREQ &&`
327			`(T1 \|\| \|breq_mach[2:0] \|\| (HALT_TRAN && \|breq_mach));`
328
329			`/*****************************************************************************************/`
330			`/* */`
331			`/* run the test patterns */`
332			`/* */`
333			`/*****************************************************************************************/`
334			`initial begin`
335			`$readmemh("setup_hl.vm", rdmem);`
336			`cleartask;`
337			`wait (PAT_DONE);`
338
339			`DISABLE_INT = 0; /* interrupt generator on */`
340
341			`resettask;`
342			`CMP_ERR_L = 16'h0000;`
343	8	bsa	`PAT_CNT = 5'h1;`
344	6	bsa	`$readmemh("blank_xx.vm", rdmem);`
345			`$readmemh("blank_xx.vm", wrmem);`
346			`$readmemh("int_ops.vm", rdmem);`
347			`$readmemh("int_opsd.vm", wrmem);`
348			`wait (PAT_DONE);`
349
350			`DISABLE_INT = 1; /* interrupt generator off */`
351
352			`resettask;`
353			`CMP_ERR_L = 16'h0000;`
354	8	bsa	`PAT_CNT = 5'h2;`
355	6	bsa	`$readmemh("blank_xx.vm", rdmem);`
356			`$readmemh("blank_xx.vm", wrmem);`
357			`$readmemh("alu_ops.vm", rdmem);`
358			`$readmemh("alu_opsd.vm", wrmem);`
359			`wait (PAT_DONE);`
360
361			`resettask;`
362			`CMP_ERR_L = 16'h0000;`
363	8	bsa	`PAT_CNT = 5'h3;`
364	6	bsa	`$readmemh("blank_xx.vm", rdmem);`
365			`$readmemh("blank_xx.vm", wrmem);`
366			`$readmemh("dat_mov.vm", rdmem);`
367			`$readmemh("dat_movd.vm", wrmem);`
368			`wait (PAT_DONE);`
369
370			`resettask;`
371			`CMP_ERR_L = 16'h0000;`
372	8	bsa	`PAT_CNT = 5'h4;`
373	6	bsa	`$readmemh("blank_xx.vm", rdmem);`
374			`$readmemh("blank_xx.vm", wrmem);`
375			`$readmemh("bit_ops.vm", rdmem);`
376			`$readmemh("bit_opsd.vm", wrmem);`
377			`wait (PAT_DONE);`
378
379			`resettask;`
380			`CMP_ERR_L = 16'h0000;`
381	8	bsa	`PAT_CNT = 5'h5;`
382	6	bsa	`$readmemh("blank_xx.vm", rdmem);`
383			`$readmemh("blank_xx.vm", wrmem);`
384			`$readmemh("jmp_ops.vm", rdmem);`
385			`$readmemh("jmp_opsd.vm", wrmem);`
386			`wait (PAT_DONE);`
387
388			`resettask;`
389			`CMP_ERR_L = 16'h0000;`
390	8	bsa	`PAT_CNT = 5'h6;`
391	6	bsa	`$readmemh("blank_xx.vm", rdmem);`
392			`$readmemh("blank_xx.vm", wrmem);`
393			`$readmemh("io_ops.vm", rdmem);`
394			`$readmemh("io_opsd.vm", wrmem);`
395			`wait (PAT_DONE);`
396
397			`resettask;`
398			`CMP_ERR_L = 16'h0000;`
399	8	bsa	`PAT_CNT = 5'h7;`
400	6	bsa	`$readmemh("blank_xx.vm", rdmem);`
401			`$readmemh("blank_xx.vm", wrmem);`
402			`$readmemh("180_ops.vm", rdmem);`
403			`$readmemh("180_opsd.vm", wrmem);`
404			`wait (PAT_DONE);`
405
406	8	bsa	`resettask;`
407			`CMP_ERR_L = 16'h0000;`
408			`PAT_CNT = 5'h8;`
409			`$readmemh("blank_xx.vm", rdmem);`
410			`$readmemh("blank_xx.vm", wrmem);`
411			`$readmemh("ez8_ops.vm", rdmem);`
412			`$readmemh("ez8_opsd.vm", wrmem);`
413			`wait (PAT_DONE);`
414
415	6	bsa	`DISABLE_INT = 0; /* interrupt generator on */`
416			`DISABLE_WAIT = 0; /* wait generator on */`
417
418			`resettask;`
419			`CMP_ERR_L = 16'h0000;`
420	8	bsa	`PAT_CNT = 5'h1;`
421	6	bsa	`$readmemh("blank_xx.vm", rdmem);`
422			`$readmemh("blank_xx.vm", wrmem);`
423			`$readmemh("int_ops.vm", rdmem);`
424			`$readmemh("int_opsd.vm", wrmem);`
425			`wait (PAT_DONE);`
426
427			`DISABLE_INT = 1; /* interrupt generator off */`
428
429			`resettask;`
430			`CMP_ERR_L = 16'h0000;`
431	8	bsa	`PAT_CNT = 5'h2;`
432	6	bsa	`$readmemh("blank_xx.vm", rdmem);`
433			`$readmemh("blank_xx.vm", wrmem);`
434			`$readmemh("alu_ops.vm", rdmem);`
435			`$readmemh("alu_opsd.vm", wrmem);`
436			`wait (PAT_DONE);`
437
438			`resettask;`
439			`CMP_ERR_L = 16'h0000;`
440	8	bsa	`PAT_CNT = 5'h3;`
441	6	bsa	`$readmemh("blank_xx.vm", rdmem);`
442			`$readmemh("blank_xx.vm", wrmem);`
443			`$readmemh("dat_mov.vm", rdmem);`
444			`$readmemh("dat_movd.vm", wrmem);`
445			`wait (PAT_DONE);`
446
447			`resettask;`
448			`CMP_ERR_L = 16'h0000;`
449	8	bsa	`PAT_CNT = 5'h4;`
450	6	bsa	`$readmemh("blank_xx.vm", rdmem);`
451			`$readmemh("blank_xx.vm", wrmem);`
452			`$readmemh("bit_ops.vm", rdmem);`
453			`$readmemh("bit_opsd.vm", wrmem);`
454			`wait (PAT_DONE);`
455
456			`resettask;`
457			`CMP_ERR_L = 16'h0000;`
458	8	bsa	`PAT_CNT = 5'h5;`
459	6	bsa	`$readmemh("blank_xx.vm", rdmem);`
460			`$readmemh("blank_xx.vm", wrmem);`
461			`$readmemh("jmp_ops.vm", rdmem);`
462			`$readmemh("jmp_opsd.vm", wrmem);`
463			`wait (PAT_DONE);`
464
465			`resettask;`
466			`CMP_ERR_L = 16'h0000;`
467	8	bsa	`PAT_CNT = 5'h6;`
468	6	bsa	`$readmemh("blank_xx.vm", rdmem);`
469			`$readmemh("blank_xx.vm", wrmem);`
470			`$readmemh("io_ops.vm", rdmem);`
471			`$readmemh("io_opsd.vm", wrmem);`
472			`wait (PAT_DONE);`
473
474			`resettask;`
475			`CMP_ERR_L = 16'h0000;`
476	8	bsa	`PAT_CNT = 5'h7;`
477	6	bsa	`$readmemh("blank_xx.vm", rdmem);`
478			`$readmemh("blank_xx.vm", wrmem);`
479			`$readmemh("180_ops.vm", rdmem);`
480			`$readmemh("180_opsd.vm", wrmem);`
481			`wait (PAT_DONE);`
482
483	8	bsa	`resettask;`
484			`CMP_ERR_L = 16'h0000;`
485			`PAT_CNT = 5'h8;`
486			`$readmemh("blank_xx.vm", rdmem);`
487			`$readmemh("blank_xx.vm", wrmem);`
488			`$readmemh("ez8_ops.vm", rdmem);`
489			`$readmemh("ez8_opsd.vm", wrmem);`
490			`wait (PAT_DONE);`
491
492	6	bsa	`DISABLE_INT = 0; /* interrupt generator on */`
493			`DISABLE_BREQ = 0; /* bus req generator on */`
494			`DISABLE_WAIT = 1; /* wait generator off */`
495
496			`resettask;`
497			`CMP_ERR_L = 16'h0000;`
498	8	bsa	`PAT_CNT = 5'h1;`
499	6	bsa	`$readmemh("blank_xx.vm", rdmem);`
500			`$readmemh("blank_xx.vm", wrmem);`

Browse

Tools

Subversion Repositories y80e

[/] [y80e/] [trunk/] [rtl/] [top_levl.v] - Blame information for rev 8