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# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2013 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II 64-Bit
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# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
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# Date created = 21:16:13 September 09, 2014
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# ZMachine_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY "Cyclone II"
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set_global_assignment -name DEVICE EP2C5T144C8
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set_global_assignment -name TOP_LEVEL_ENTITY ZMachine
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:16:13 SEPTEMBER 09, 2014"
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set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
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set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
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set_global_assignment -name VERILOG_FILE ZMachine.v
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name BDF_FILE ZMachine.bdf
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set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
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set_location_assignment PIN_142 -to address[16]
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set_location_assignment PIN_141 -to address[15]
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set_location_assignment PIN_48 -to address[14]
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set_location_assignment PIN_53 -to address[13]
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set_location_assignment PIN_139 -to address[12]
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set_location_assignment PIN_58 -to address[11]
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set_location_assignment PIN_60 -to address[10]
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set_location_assignment PIN_57 -to address[9]
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set_location_assignment PIN_55 -to address[8]
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set_location_assignment PIN_137 -to address[7]
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set_location_assignment PIN_136 -to address[6]
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set_location_assignment PIN_135 -to address[5]
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set_location_assignment PIN_134 -to address[4]
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set_location_assignment PIN_133 -to address[3]
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set_location_assignment PIN_132 -to address[2]
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set_location_assignment PIN_129 -to address[1]
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set_location_assignment PIN_126 -to address[0]
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set_location_assignment PIN_64 -to data[7]
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set_location_assignment PIN_65 -to data[6]
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set_location_assignment PIN_67 -to data[5]
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set_location_assignment PIN_69 -to data[4]
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set_location_assignment PIN_70 -to data[3]
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set_location_assignment PIN_121 -to data[2]
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set_location_assignment PIN_122 -to data[1]
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set_location_assignment PIN_125 -to data[0]
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set_location_assignment PIN_17 -to osc_clk
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set_location_assignment PIN_52 -to WE
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set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA OFF
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set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF
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set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
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set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
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set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
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set_location_assignment PIN_43 -to PE
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set_location_assignment PIN_63 -to ramCS
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set_location_assignment PIN_120 -to romCS
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set_global_assignment -name SDC_FILE zmachine.sdc
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set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE AREA
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set_global_assignment -name SMART_RECOMPILE ON
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set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
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set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION ALWAYS
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set_location_assignment PIN_3 -to led0
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set_location_assignment PIN_7 -to led1
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set_location_assignment PIN_9 -to led2
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set_location_assignment PIN_143 -to A18
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set_location_assignment PIN_118 -to A17
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set_location_assignment PIN_119 -to romOE
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set_location_assignment PIN_51 -to ramCE2
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set_location_assignment PIN_59 -to ramOE
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set_location_assignment PIN_41 -to lcdCS
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set_location_assignment PIN_40 -to lcdReset
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set_location_assignment PIN_42 -to lcdRS
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set_location_assignment PIN_44 -to lcdRD
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set_location_assignment PIN_45 -to nadcCS
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set_location_assignment PIN_47 -to adcDout
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to adcDout
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set_global_assignment -name QIP_FILE altpll0.qip
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set_location_assignment PIN_144 -to reset
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to reset
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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