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[/] [z80control/] [trunk/] [CII_Starter_USB_API_v1/] [HW/] [Multi_Sdram/] [Sdram_Controller.v] - Blame information for rev 12

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//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors.  Please refer to the applicable
//agreement for further details.
 
module Sdram_Controller(
                //      HOST
        REF_CLK,
        RESET_N,
        ADDR,
                WR,
                RD,
                LENGTH,
                ACT,
                DONE,
        DATAIN,
        DATAOUT,
                IN_REQ,
                OUT_VALID,
        DM,
                //      SDRAM
        SA,
        BA,
        CS_N,
        CKE,
        RAS_N,
        CAS_N,
        WE_N,
        DQ,
        DQM,
                SDR_CLK
        );
 
 
`include        "Sdram_Params.h"
input                           REF_CLK;                //System Clock
input                           RESET_N;                //System Reset
input   [`ASIZE-1:0]            ADDR;                   //Address for controller requests
input                                                   WR;                                             //Write Request
input                                                   RD;                                             //Read Request
input   [7:0]                                    LENGTH;                                 //Request Data length
output                                                  ACT;                                    //SDRAM ACT
output                                                  DONE;                                   //Write/Read Done
input   [`DSIZE-1:0]            DATAIN;                 //Data input
output  [`DSIZE-1:0]            DATAOUT;                //Data output
input   [`DSIZE/8-1:0]          DM;                     //Data mask input
output  [11:0]                  SA;                     //SDRAM address output
output  [1:0]                   BA;                     //SDRAM bank address
output  [1:0]                   CS_N;                   //SDRAM Chip Selects
output                          CKE;                    //SDRAM clock enable
output                          RAS_N;                  //SDRAM Row address Strobe
output                          CAS_N;                  //SDRAM Column address Strobe
output                          WE_N;                   //SDRAM write enable
inout   [`DSIZE-1:0]            DQ;                     //SDRAM data bus
output  [`DSIZE/8-1:0]          DQM;                    //SDRAM data mask lines
output                                                  OUT_VALID;                              //Output data valid
output                                                  IN_REQ;                                 //Input data request
output                                                  SDR_CLK;                                //SDRAM Clock
 
reg     [`DSIZE/8-1:0]          DQM;                    //SDRAM data mask lines
reg     [11:0]                  SA;                     //SDRAM address output
reg     [1:0]                   BA;                     //SDRAM bank address
reg     [1:0]                   CS_N;                   //SDRAM Chip Selects
reg                             CKE;                    //SDRAM clock enable
reg                             RAS_N;                  //SDRAM Row address Strobe
reg                             CAS_N;                  //SDRAM Column address Strobe
reg                             WE_N;                   //SDRAM write enable
reg                                                             OUT_VALID;                              //Output data valid
reg                                                             IN_REQ;                                 //Input data request                    
reg     [8:0]                                    ST;
reg             [1:0]                                    CMD;
reg                                                     DONE;                                   //Write/Read Done
reg                                                             Pre_RD;
reg                                                             Pre_WR;
reg                                                             PM_STOP;
reg                                                             PM_DONE;
reg                                                             Read;
reg                                                             Write;
reg                                                             Pre_DONE;
reg                                                             mDONE;                                   //SDRAM Internal Done
 
reg     [`DSIZE-1:0]            DATAOUT;                 //Data output
reg     [`DSIZE-1:0]            mDATAOUT;                 //Data output
wire    [`DSIZE-1:0]            DQOUT;
wire    [`DSIZE/8-1:0]          IDQM;                    //SDRAM data mask lines
 
wire    [11:0]                  ISA;                     //SDRAM address output
wire    [1:0]                   IBA;                     //SDRAM bank address
wire    [1:0]                   ICS_N;                   //SDRAM Chip Selects
wire                            ICKE;                    //SDRAM clock enable
wire                            IRAS_N;                  //SDRAM Row address Strobe
wire                            ICAS_N;                  //SDRAM Column address Strobe
wire                            IWE_N;                   //SDRAM write enable
wire                            CMDACK;                 //Controller command acknowledgement
 
wire    [`ASIZE-1:0]            saddr;
wire                            load_mode;
wire                            nop;
wire                            reada;
wire                            writea;
wire                            refresh;
wire                            precharge;
wire                            oe;
wire                                                    ref_ack;
wire                                                    ref_req;
wire                                                    init_req;
wire                                                    cm_ack;
wire                            CLK;
 
PLL1 sdram_pll1 (
                                .inclk0(REF_CLK),
                                .c0(CLK),
                                .c2(SDR_CLK)
                                );
 
control_interface control1 (
                .CLK(CLK),
                .RESET_N(RESET_N),
                .CMD(CMD),
                .ADDR(ADDR),
                .REF_ACK(ref_ack),
                .CM_ACK(cm_ack),
                .NOP(nop),
                .READA(reada),
                .WRITEA(writea),
                .REFRESH(refresh),
                .PRECHARGE(precharge),
                .LOAD_MODE(load_mode),
                .SADDR(saddr),
                .REF_REQ(ref_req),
                                .INIT_REQ(init_req),
                .CMD_ACK(CMDACK)
                );
 
command command1(
                .CLK(CLK),
                .RESET_N(RESET_N),
                .SADDR(saddr),
                .NOP(nop),
                .READA(reada),
                .WRITEA(writea),
                .REFRESH(refresh),
                                .LOAD_MODE(load_mode),
                .PRECHARGE(precharge),
                .REF_REQ(ref_req),
                                .INIT_REQ(init_req),
                .REF_ACK(ref_ack),
                .CM_ACK(cm_ack),
                .OE(oe),
                                .PM_STOP(PM_STOP),
                                .PM_DONE(PM_DONE),
                .SA(ISA),
                .BA(IBA),
                .CS_N(ICS_N),
                .CKE(ICKE),
                .RAS_N(IRAS_N),
                .CAS_N(ICAS_N),
                .WE_N(IWE_N)
                );
 
sdr_data_path data_path1(
                .CLK(CLK),
                .RESET_N(RESET_N),
                .DATAIN(DATAIN),
                .DM(DM),
                .DQOUT(DQOUT),
                .DQM(IDQM)
                );
 
always @(posedge CLK)
begin
        SA      <= (ST==SC_CL+LENGTH)                   ?       12'h200 :       ISA;
    BA      <= IBA;
    CS_N    <= ICS_N;
    CKE     <= ICKE;
    RAS_N   <= (ST==SC_CL+LENGTH)                       ?       1'b0    :       IRAS_N;
    CAS_N   <= (ST==SC_CL+LENGTH)                       ?       1'b1    :       ICAS_N;
    WE_N    <= (ST==SC_CL+LENGTH)                       ?       1'b0    :       IWE_N;
        PM_STOP <= (ST==SC_CL+LENGTH)                   ?       1'b1    :       1'b0;
        PM_DONE <= (ST==SC_CL+SC_RCD+LENGTH+2)  ?       1'b1    :       1'b0;
        DQM             <= ( ACT && (ST>=SC_CL) )       ?       (       ((ST==SC_CL+LENGTH) && Write)?  2'b11   :       2'b00   )       :       2'b11   ;
        mDATAOUT<= DQ;
end
 
assign  DQ = oe ? DQOUT : `DSIZE'hzzzz;
assign  ACT     =       Read | Write;
 
always@(posedge CLK or negedge RESET_N)
begin
        if(RESET_N==0)
        begin
                CMD                     <=  0;
                mDONE           <=  0;
                ST                      <=  0;
                Pre_RD          <=  0;
                Pre_WR          <=  0;
                Read            <=      0;
                Write           <=      0;
                OUT_VALID       <=      0;
                IN_REQ          <=      0;
        end
        else
        begin
                Pre_RD  <=      RD;
                Pre_WR  <=      WR;
                case(ST)
                0:       begin
                                if({Pre_RD,RD}==2'b01)
                                begin
                                        Read    <=      1;
                                        Write   <=      0;
                                        CMD             <=      2'b01;
                                        ST              <=      1;
                                end
                                else if({Pre_WR,WR}==2'b01)
                                begin
                                        Read    <=      0;
                                        Write   <=      1;
                                        CMD             <=      2'b10;
                                        ST              <=      1;
                                end
                        end
                1:      begin
                                if(CMDACK==1)
                                begin
                                        CMD<=2'b00;
                                        ST<=2;
                                end
                        end
                default:        ST<=ST+1;
                endcase
 
                if(ST==SC_CL+SC_RCD+2)
                mDONE   <=      1;
                else if(ST==SC_CL+SC_RCD+LENGTH+2)
                ST              <=      0;
 
                if(Read)
                begin
                        if(ST==SC_CL+SC_RCD+2)
                        OUT_VALID       <=      1;
                        else if(ST==SC_CL+SC_RCD+LENGTH+2)
                        begin
                                OUT_VALID       <=      0;
                                Read            <=      0;
                        end
                end
 
                if(Write)
                begin
                        if(ST==SC_CL-1)
                        IN_REQ  <=      1;
                        else if(ST==SC_CL+LENGTH-1)
                        begin
                                IN_REQ  <=      0;
                                Write   <=      0;
                        end
                end
 
                if(!WR && !RD)
                mDONE<=0;
 
        end
end
 
always@(posedge REF_CLK or negedge RESET_N)
begin
        if(!RESET_N)
        begin
                DONE    <=      0;
                Pre_DONE<=      0;
                DATAOUT <=      0;
        end
        else
        begin
                Pre_DONE        <=      mDONE;
                if({Pre_DONE,mDONE}==2'b01)
                DONE    <=      1;
                if(!WR && !RD)
                DONE    <=      0;
                if(RD)
                DATAOUT <=      mDATAOUT;
        end
end
 
endmodule

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[/] [z80control/] [trunk/] [CII_Starter_USB_API_v1/] [HW/] [Multi_Sdram/] [Sdram_Controller.v] - Blame information for rev 12

Line No.	Rev	Author	Line
1	12	tylerapohl	`//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your`
2			`//use of Altera Corporation's design tools, logic functions and other`
3			`//software and tools, and its AMPP partner logic functions, and any`
4			`//output files any of the foregoing (including device programming or`
5			`//simulation files), and any associated documentation or information are`
6			`//expressly subject to the terms and conditions of the Altera Program`
7			`//License Subscription Agreement or other applicable license agreement,`
8			`//including, without limitation, that your use is for the sole purpose`
9			`//of programming logic devices manufactured by Altera and sold by Altera`
10			`//or its authorized distributors. Please refer to the applicable`
11			`//agreement for further details.`
12
13			`module Sdram_Controller(`
14			`// HOST`
15			`REF_CLK,`
16			`RESET_N,`
17			`ADDR,`
18			`WR,`
19			`RD,`
20			`LENGTH,`
21			`ACT,`
22			`DONE,`
23			`DATAIN,`
24			`DATAOUT,`
25			`IN_REQ,`
26			`OUT_VALID,`
27			`DM,`
28			`// SDRAM`
29			`SA,`
30			`BA,`
31			`CS_N,`
32			`CKE,`
33			`RAS_N,`
34			`CAS_N,`
35			`WE_N,`
36			`DQ,`
37			`DQM,`
38			`SDR_CLK`
39			`);`
40
41
42			`include "Sdram_Params.h"
43			`input REF_CLK; //System Clock`
44			`input RESET_N; //System Reset`
45			input [`ASIZE-1:0] ADDR; //Address for controller requests
46			`input WR; //Write Request`
47			`input RD; //Read Request`
48			`input [7:0] LENGTH; //Request Data length`
49			`output ACT; //SDRAM ACT`
50			`output DONE; //Write/Read Done`
51			input [`DSIZE-1:0] DATAIN; //Data input
52			output [`DSIZE-1:0] DATAOUT; //Data output
53			input [`DSIZE/8-1:0] DM; //Data mask input
54			`output [11:0] SA; //SDRAM address output`
55			`output [1:0] BA; //SDRAM bank address`
56			`output [1:0] CS_N; //SDRAM Chip Selects`
57			`output CKE; //SDRAM clock enable`
58			`output RAS_N; //SDRAM Row address Strobe`
59			`output CAS_N; //SDRAM Column address Strobe`
60			`output WE_N; //SDRAM write enable`
61			inout [`DSIZE-1:0] DQ; //SDRAM data bus
62			output [`DSIZE/8-1:0] DQM; //SDRAM data mask lines
63			`output OUT_VALID; //Output data valid`
64			`output IN_REQ; //Input data request`
65			`output SDR_CLK; //SDRAM Clock`
66
67			reg [`DSIZE/8-1:0] DQM; //SDRAM data mask lines
68			`reg [11:0] SA; //SDRAM address output`
69			`reg [1:0] BA; //SDRAM bank address`
70			`reg [1:0] CS_N; //SDRAM Chip Selects`
71			`reg CKE; //SDRAM clock enable`
72			`reg RAS_N; //SDRAM Row address Strobe`
73			`reg CAS_N; //SDRAM Column address Strobe`
74			`reg WE_N; //SDRAM write enable`
75			`reg OUT_VALID; //Output data valid`
76			`reg IN_REQ; //Input data request`
77			`reg [8:0] ST;`
78			`reg [1:0] CMD;`
79			`reg DONE; //Write/Read Done`
80			`reg Pre_RD;`
81			`reg Pre_WR;`
82			`reg PM_STOP;`
83			`reg PM_DONE;`
84			`reg Read;`
85			`reg Write;`
86			`reg Pre_DONE;`
87			`reg mDONE; //SDRAM Internal Done`
88
89			reg [`DSIZE-1:0] DATAOUT; //Data output
90			reg [`DSIZE-1:0] mDATAOUT; //Data output
91			wire [`DSIZE-1:0] DQOUT;
92			wire [`DSIZE/8-1:0] IDQM; //SDRAM data mask lines
93
94			`wire [11:0] ISA; //SDRAM address output`
95			`wire [1:0] IBA; //SDRAM bank address`
96			`wire [1:0] ICS_N; //SDRAM Chip Selects`
97			`wire ICKE; //SDRAM clock enable`
98			`wire IRAS_N; //SDRAM Row address Strobe`
99			`wire ICAS_N; //SDRAM Column address Strobe`
100			`wire IWE_N; //SDRAM write enable`
101			`wire CMDACK; //Controller command acknowledgement`
102
103			wire [`ASIZE-1:0] saddr;
104			`wire load_mode;`
105			`wire nop;`
106			`wire reada;`
107			`wire writea;`
108			`wire refresh;`
109			`wire precharge;`
110			`wire oe;`
111			`wire ref_ack;`
112			`wire ref_req;`
113			`wire init_req;`
114			`wire cm_ack;`
115			`wire CLK;`
116
117			`PLL1 sdram_pll1 (`
118			`.inclk0(REF_CLK),`
119			`.c0(CLK),`
120			`.c2(SDR_CLK)`
121			`);`
122
123			`control_interface control1 (`
124			`.CLK(CLK),`
125			`.RESET_N(RESET_N),`
126			`.CMD(CMD),`
127			`.ADDR(ADDR),`
128			`.REF_ACK(ref_ack),`
129			`.CM_ACK(cm_ack),`
130			`.NOP(nop),`
131			`.READA(reada),`
132			`.WRITEA(writea),`
133			`.REFRESH(refresh),`
134			`.PRECHARGE(precharge),`
135			`.LOAD_MODE(load_mode),`
136			`.SADDR(saddr),`
137			`.REF_REQ(ref_req),`
138			`.INIT_REQ(init_req),`
139			`.CMD_ACK(CMDACK)`
140			`);`
141
142			`command command1(`
143			`.CLK(CLK),`
144			`.RESET_N(RESET_N),`
145			`.SADDR(saddr),`
146			`.NOP(nop),`
147			`.READA(reada),`
148			`.WRITEA(writea),`
149			`.REFRESH(refresh),`
150			`.LOAD_MODE(load_mode),`
151			`.PRECHARGE(precharge),`
152			`.REF_REQ(ref_req),`
153			`.INIT_REQ(init_req),`
154			`.REF_ACK(ref_ack),`
155			`.CM_ACK(cm_ack),`
156			`.OE(oe),`
157			`.PM_STOP(PM_STOP),`
158			`.PM_DONE(PM_DONE),`
159			`.SA(ISA),`
160			`.BA(IBA),`
161			`.CS_N(ICS_N),`
162			`.CKE(ICKE),`
163			`.RAS_N(IRAS_N),`
164			`.CAS_N(ICAS_N),`
165			`.WE_N(IWE_N)`
166			`);`
167
168			`sdr_data_path data_path1(`
169			`.CLK(CLK),`
170			`.RESET_N(RESET_N),`
171			`.DATAIN(DATAIN),`
172			`.DM(DM),`
173			`.DQOUT(DQOUT),`
174			`.DQM(IDQM)`
175			`);`
176
177			`always @(posedge CLK)`
178			`begin`
179			`SA <= (ST==SC_CL+LENGTH) ? 12'h200 : ISA;`
180			`BA <= IBA;`
181			`CS_N <= ICS_N;`
182			`CKE <= ICKE;`
183			`RAS_N <= (ST==SC_CL+LENGTH) ? 1'b0 : IRAS_N;`
184			`CAS_N <= (ST==SC_CL+LENGTH) ? 1'b1 : ICAS_N;`
185			`WE_N <= (ST==SC_CL+LENGTH) ? 1'b0 : IWE_N;`
186			`PM_STOP <= (ST==SC_CL+LENGTH) ? 1'b1 : 1'b0;`
187			`PM_DONE <= (ST==SC_CL+SC_RCD+LENGTH+2) ? 1'b1 : 1'b0;`
188			`DQM <= ( ACT && (ST>=SC_CL) ) ? ( ((ST==SC_CL+LENGTH) && Write)? 2'b11 : 2'b00 ) : 2'b11 ;`
189			`mDATAOUT<= DQ;`
190			`end`
191
192			assign DQ = oe ? DQOUT : `DSIZE'hzzzz;
193			`assign ACT = Read \| Write;`
194
195			`always@(posedge CLK or negedge RESET_N)`
196			`begin`
197			`if(RESET_N==0)`
198			`begin`
199			`CMD <= 0;`
200			`mDONE <= 0;`
201			`ST <= 0;`
202			`Pre_RD <= 0;`
203			`Pre_WR <= 0;`
204			`Read <= 0;`
205			`Write <= 0;`
206			`OUT_VALID <= 0;`
207			`IN_REQ <= 0;`
208			`end`
209			`else`
210			`begin`
211			`Pre_RD <= RD;`
212			`Pre_WR <= WR;`
213			`case(ST)`
214			`0: begin`
215			`if({Pre_RD,RD}==2'b01)`
216			`begin`
217			`Read <= 1;`
218			`Write <= 0;`
219			`CMD <= 2'b01;`
220			`ST <= 1;`
221			`end`
222			`else if({Pre_WR,WR}==2'b01)`
223			`begin`
224			`Read <= 0;`
225			`Write <= 1;`
226			`CMD <= 2'b10;`
227			`ST <= 1;`
228			`end`
229			`end`
230			`1: begin`
231			`if(CMDACK==1)`
232			`begin`
233			`CMD<=2'b00;`
234			`ST<=2;`
235			`end`
236			`end`
237			`default: ST<=ST+1;`
238			`endcase`
239
240			`if(ST==SC_CL+SC_RCD+2)`
241			`mDONE <= 1;`
242			`else if(ST==SC_CL+SC_RCD+LENGTH+2)`
243			`ST <= 0;`
244
245			`if(Read)`
246			`begin`
247			`if(ST==SC_CL+SC_RCD+2)`
248			`OUT_VALID <= 1;`
249			`else if(ST==SC_CL+SC_RCD+LENGTH+2)`
250			`begin`
251			`OUT_VALID <= 0;`
252			`Read <= 0;`
253			`end`
254			`end`
255
256			`if(Write)`
257			`begin`
258			`if(ST==SC_CL-1)`
259			`IN_REQ <= 1;`
260			`else if(ST==SC_CL+LENGTH-1)`
261			`begin`
262			`IN_REQ <= 0;`
263			`Write <= 0;`
264			`end`
265			`end`
266
267			`if(!WR && !RD)`
268			`mDONE<=0;`
269
270			`end`
271			`end`
272
273			`always@(posedge REF_CLK or negedge RESET_N)`
274			`begin`
275			`if(!RESET_N)`
276			`begin`
277			`DONE <= 0;`
278			`Pre_DONE<= 0;`
279			`DATAOUT <= 0;`
280			`end`
281			`else`
282			`begin`
283			`Pre_DONE <= mDONE;`
284			`if({Pre_DONE,mDONE}==2'b01)`
285			`DONE <= 1;`
286			`if(!WR && !RD)`
287			`DONE <= 0;`
288			`if(RD)`
289			`DATAOUT <= mDATAOUT;`
290			`end`
291			`end`
292
293			`endmodule`