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[/] [z80control/] [trunk/] [CII_Starter_USB_API_v1/] [HW/] [USB_JTAG.v] - Blame information for rev 12

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1 12 tylerapohl 
//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
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//use of Altera Corporation's design tools, logic functions and other
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//software and tools, and its AMPP partner logic functions, and any
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//output files any of the foregoing (including device programming or
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//simulation files), and any associated documentation or information are
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//expressly subject to the terms and conditions of the Altera Program
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//License Subscription Agreement or other applicable license agreement,
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//including, without limitation, that your use is for the sole purpose
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//of programming logic devices manufactured by Altera and sold by Altera
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//or its authorized distributors.  Please refer to the applicable
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//agreement for further details.
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module USB_JTAG (       //      HOST
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                                        iTxD_DATA,oTxD_Done,iTxD_Start,
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                                        oRxD_DATA,oRxD_Ready,iRST_n,iCLK,
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                                        //      JTAG
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                                        TDO,TDI,TCS,TCK );
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input [7:0] iTxD_DATA;
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input iTxD_Start,iRST_n,iCLK;
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output reg [7:0] oRxD_DATA;
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output reg oTxD_Done,oRxD_Ready;
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input TDI,TCS,TCK;
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output TDO;
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wire [7:0] mRxD_DATA;
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wire mTxD_Done,mRxD_Ready;
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reg Pre_TxD_Done,Pre_RxD_Ready;
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reg mTCK;
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////////////    JTAG CLK Sync.  ///////////////
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always@(posedge iCLK)   mTCK<=TCK;
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/////////////////       JTAG Receiver   ///////////////
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JTAG_REC        u0      (mRxD_DATA,mRxD_Ready,TDI,TCS,mTCK);
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//      JTAG Receiver Sync.
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always@(posedge iCLK or negedge iRST_n)
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begin
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        if(!iRST_n)
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        begin
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                oRxD_Ready<=0;
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                Pre_RxD_Ready<=0;
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        end
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        else
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        begin
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                Pre_RxD_Ready<=mRxD_Ready;
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                if({Pre_RxD_Ready,mRxD_Ready}==2'b01 && ~iTxD_Start)
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                begin
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                        oRxD_Ready<=1;
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                        oRxD_DATA<=mRxD_DATA;
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                end
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                else
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                        oRxD_Ready<=0;
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        end
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end
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///////////////////////////////////////////////////
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/////////////   JTAG Transmitter        ///////////////
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JTAG_TRANS      u1      (iTxD_DATA,iTxD_Start,mTxD_Done,TDO,TCK,TCS);
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//      JTAG Transmitter Sync.
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always@(posedge iCLK or negedge iRST_n)
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begin
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        if(!iRST_n)
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        begin
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                oTxD_Done<=0;
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                Pre_TxD_Done<=0;
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        end
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        else
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        begin
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                Pre_TxD_Done<=mTxD_Done;
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                if({Pre_TxD_Done,mTxD_Done}==2'b01)
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                        oTxD_Done<=1;
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                else
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                        oTxD_Done<=0;
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        end
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end
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///////////////////////////////////////////////////
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endmodule
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module JTAG_REC (       //      HOST
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                                        oRxD_DATA,oRxD_Ready,
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                                        //      JTAG
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                                        TDI,TCS,TCK     );
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input TDI,TCS,TCK;
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output reg [7:0] oRxD_DATA;
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output reg oRxD_Ready;
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reg [7:0] rDATA;
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reg [2:0] rCont;
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always@(posedge TCK or posedge TCS)
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begin
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        if(TCS)
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        begin
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                oRxD_Ready<=0;
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                rCont<=0;
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        end
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        else
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        begin
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                rCont<=rCont+1;
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                rDATA<={TDI,rDATA[7:1]};
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                if(rCont==0)
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                begin
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                        oRxD_DATA<={TDI,rDATA[7:1]};
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                        oRxD_Ready<=1;
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                end
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                else
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                        oRxD_Ready<=0;
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        end
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end
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endmodule
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module JTAG_TRANS(      //      HOST
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                                        iTxD_DATA,iTxD_Start,oTxD_Done,
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                                        //      JTAG
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                                        TDO,TCK,TCS     );
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input [7:0] iTxD_DATA;
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input iTxD_Start;
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output reg oTxD_Done;
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input TCK,TCS;
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output reg TDO;
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reg [2:0] rCont;
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always@(posedge TCK or posedge TCS)
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begin
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        if(TCS)
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        begin
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                oTxD_Done<=0;
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                rCont<=0;
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                TDO<=0;
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        end
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        else
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        begin
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                if(iTxD_Start)
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                begin
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                        rCont<=rCont+1;
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                        TDO<=iTxD_DATA[rCont];
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                end
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                else
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                begin
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                        rCont<=0;
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                        TDO<=0;
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                end
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                if(rCont==7)
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                oTxD_Done<=1;
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                else
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                oTxD_Done<=0;
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        end
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end
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endmodule
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