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[/] [z80control/] [trunk/] [CII_Starter_USB_API_v1/] [HW/] [VGA_Controller/] [VGA_OSD_RAM.v] - Blame information for rev 12

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1 12 tylerapohl 
//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
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//use of Altera Corporation's design tools, logic functions and other
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//software and tools, and its AMPP partner logic functions, and any
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//output files any of the foregoing (including device programming or
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//simulation files), and any associated documentation or information are
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//expressly subject to the terms and conditions of the Altera Program
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//License Subscription Agreement or other applicable license agreement,
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//including, without limitation, that your use is for the sole purpose
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//of programming logic devices manufactured by Altera and sold by Altera
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//or its authorized distributors.  Please refer to the applicable
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//agreement for further details.
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module  VGA_OSD_RAM     (       //      Read Out Side
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                                                oRed,
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                                                oGreen,
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                                                oBlue,
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                                                iVGA_ADDR,
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                                                iVGA_X,
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                                                iVGA_Y,
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                                                iVGA_CLK,
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                                                //      Write In Side
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                                                iWR_DATA,
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                                                iWR_ADDR,
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                                                iWR_EN,
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                                                iWR_CLK,
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                                                //      CLUT
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                                                iON_R,
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                                                iON_G,
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                                                iON_B,
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                                                iOFF_R,
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                                                iOFF_G,
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                                                iOFF_B,
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                                                //      Control Signals
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                                                iRST_N  );
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//      Read Out Side
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output  reg     [9:0]    oRed;
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output  reg     [9:0]    oGreen;
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output  reg     [9:0]    oBlue;
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input   [18:0]           iVGA_ADDR;
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input   [9:0]            iVGA_X;
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input   [9:0]            iVGA_Y;
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input                           iVGA_CLK;
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//      Write In Side
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input   [18:0]           iWR_ADDR;
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input                           iWR_DATA;
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input                           iWR_EN;
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input                           iWR_CLK;
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//      CLUT
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input   [9:0]    iON_R;
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input   [9:0]    iON_G;
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input   [9:0]    iON_B;
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input   [9:0]    iOFF_R;
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input   [9:0]    iOFF_G;
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input   [9:0]    iOFF_B;
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//      Control Signals
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input                           iRST_N;
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//      Internal Registers/Wires
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reg             [2:0]            ADDR_d;
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reg             [2:0]            ADDR_dd;
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wire    [7:0]            ROM_DATA;
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wire    [18:0]           mVGA_ADDR;
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parameter       START_X =       60;
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parameter       START_Y =       50;
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parameter       END_X   =       640-60;
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parameter       END_Y   =       480-30;
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assign  mVGA_ADDR       =       iVGA_ADDR-(iVGA_Y*120)-521*50;
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always@(posedge iVGA_CLK or negedge iRST_N)
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begin
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        if(!iRST_N)
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        begin
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                oRed    <=      0;
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                oGreen  <=      0;
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                oBlue   <=      0;
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                ADDR_d  <=      0;
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                ADDR_dd <=      0;
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        end
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        else
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        begin
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                ADDR_d  <=      mVGA_ADDR[2:0];
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                ADDR_dd <=      ~ADDR_d;
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                oRed    <=      ~(iVGA_X>=START_X && iVGA_X<END_X && iVGA_Y>=START_Y && iVGA_Y<END_Y)   ?       iOFF_R  :
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                                        ROM_DATA[ADDR_dd]?      iON_R:iOFF_R;
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                oGreen  <=      ~(iVGA_X>=START_X && iVGA_X<END_X && iVGA_Y>=START_Y && iVGA_Y<END_Y)   ?       iOFF_G  :
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                                        ROM_DATA[ADDR_dd]?      iON_G:iOFF_G;
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                oBlue   <=      ~(iVGA_X>=START_X && iVGA_X<END_X && iVGA_Y>=START_Y && iVGA_Y<END_Y)   ?       iOFF_B  :
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                                        ROM_DATA[ADDR_dd]?      iON_B:iOFF_B;
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        end
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end
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Img_RAM         u0      (       //      Write In Side
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                                        .data(iWR_DATA),
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                                        .wren(iWR_EN),
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                                        .wraddress({iWR_ADDR[18:3],~iWR_ADDR[2:0]}),
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                                        .wrclock(iWR_CLK),
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                                        //      Read Out Side
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                                        .rdaddress(mVGA_ADDR[18:3]),
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                                        .rdclock(iVGA_CLK),
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                                        .q(ROM_DATA));
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endmodule

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