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[/] [z80control/] [trunk/] [DE1/] [rtl/] [VHDL/] [t80/] [DebugSystem.vhd] - Blame information for rev 12

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1 12 tylerapohl
-- Z80, Monitor ROM, 4k RAM and two 16450 UARTs
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-- that can be synthesized and used with
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-- the NoICE debugger that can be found at
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-- http://www.noicedebugger.com/
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity DebugSystem is
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        port(
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                Reset_n         : in std_logic;
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                Clk                     : in std_logic;
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                NMI_n           : in std_logic;
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                RXD0            : in std_logic;
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                CTS0            : in std_logic;
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                DSR0            : in std_logic;
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                RI0                     : in std_logic;
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                DCD0            : in std_logic;
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                RXD1            : in std_logic;
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                CTS1            : in std_logic;
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                DSR1            : in std_logic;
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                RI1                     : in std_logic;
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                DCD1            : in std_logic;
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                TXD0            : out std_logic;
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                RTS0            : out std_logic;
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                DTR0            : out std_logic;
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                TXD1            : out std_logic;
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                RTS1            : out std_logic;
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                DTR1            : out std_logic
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        );
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end DebugSystem;
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architecture struct of DebugSystem is
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        signal M1_n                     : std_logic;
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        signal MREQ_n           : std_logic;
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        signal IORQ_n           : std_logic;
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        signal RD_n                     : std_logic;
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        signal WR_n                     : std_logic;
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        signal RFSH_n           : std_logic;
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        signal HALT_n           : std_logic;
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        signal WAIT_n           : std_logic;
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        signal INT_n            : std_logic;
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        signal RESET_s          : std_logic;
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        signal BUSRQ_n          : std_logic;
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        signal BUSAK_n          : std_logic;
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        signal A                        : std_logic_vector(15 downto 0);
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        signal D                        : std_logic_vector(7 downto 0);
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        signal ROM_D            : std_logic_vector(7 downto 0);
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        signal SRAM_D           : std_logic_vector(7 downto 0);
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        signal UART0_D          : std_logic_vector(7 downto 0);
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        signal UART1_D          : std_logic_vector(7 downto 0);
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        signal CPU_D            : std_logic_vector(7 downto 0);
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        signal Mirror           : std_logic;
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        signal IOWR_n           : std_logic;
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        signal RAMCS_n          : std_logic;
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        signal UART0CS_n        : std_logic;
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        signal UART1CS_n        : std_logic;
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        signal BaudOut0         : std_logic;
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        signal BaudOut1         : std_logic;
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begin
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        Wait_n <= '1';
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        BusRq_n <= '1';
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        INT_n <= '1';
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        process (Reset_n, Clk)
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        begin
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                if Reset_n = '0' then
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                        Reset_s <= '0';
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                        Mirror <= '0';
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                elsif Clk'event and Clk = '1' then
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                        Reset_s <= '1';
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                        if IORQ_n = '0' and A(7 downto 4) = "1111" then
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                                Mirror <= D(0);
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                        end if;
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                end if;
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        end process;
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        IOWR_n <= WR_n or IORQ_n;
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        RAMCS_n <= (not Mirror and not A(15)) or MREQ_n;
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        UART0CS_n <= '0' when IORQ_n = '0' and A(7 downto 3) = "00000" else '1';
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        UART1CS_n <= '0' when IORQ_n = '0' and A(7 downto 3) = "10000" else '1';
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        CPU_D <=
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                SRAM_D when RAMCS_n = '0' else
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                UART0_D when UART0CS_n = '0' else
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                UART1_D when UART1CS_n = '0' else
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                ROM_D;
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        u0 : entity work.T80s
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                        generic map(Mode => 1, T2Write => 1, IOWait => 0)
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                        port map(
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                                RESET_n => RESET_s,
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                                CLK_n => Clk,
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                                WAIT_n => WAIT_n,
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                                INT_n => INT_n,
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                                NMI_n => NMI_n,
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                                BUSRQ_n => BUSRQ_n,
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                                M1_n => M1_n,
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                                MREQ_n => MREQ_n,
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                                IORQ_n => IORQ_n,
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                                RD_n => RD_n,
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                                WR_n => WR_n,
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                                RFSH_n => RFSH_n,
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                                HALT_n => HALT_n,
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                                BUSAK_n => BUSAK_n,
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                                A => A,
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                                DI => CPU_D,
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                                DO => D);
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        u1 : entity work.MonZ80
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                        port map(
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                                Clk => Clk,
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                                A => A(10 downto 0),
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                                D => ROM_D);
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        u2 : entity work.SSRAM
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                        generic map(
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                                AddrWidth => 12)
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                        port map(
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                                Clk => Clk,
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                                CE_n => RAMCS_n,
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                                WE_n => WR_n,
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                                A => A(11 downto 0),
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                                DIn => D,
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                                DOut => SRAM_D);
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        u3 : entity work.T16450
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                        port map(
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                                MR_n => Reset_s,
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                                XIn => Clk,
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                                RClk => BaudOut0,
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                                CS_n => UART0CS_n,
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                                Rd_n => RD_n,
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                                Wr_n => IOWR_n,
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                                A => A(2 downto 0),
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                                D_In => D,
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                                D_Out => UART0_D,
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                                SIn => RXD0,
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                                CTS_n => CTS0,
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                                DSR_n => DSR0,
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                                RI_n => RI0,
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                                DCD_n => DCD0,
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                                SOut => TXD0,
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                                RTS_n => RTS0,
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                                DTR_n => DTR0,
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                                OUT1_n => open,
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                                OUT2_n => open,
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                                BaudOut => BaudOut0,
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                                Intr => open);
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        u4 : entity work.T16450
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                        port map(
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                                MR_n => Reset_s,
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                                XIn => Clk,
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                                RClk => BaudOut1,
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                                CS_n => UART1CS_n,
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                                Rd_n => RD_n,
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                                Wr_n => IOWR_n,
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                                A => A(2 downto 0),
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                                D_In => D,
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                                D_Out => UART1_D,
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                                SIn => RXD1,
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                                CTS_n => CTS1,
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                                DSR_n => DSR1,
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                                RI_n => RI1,
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                                DCD_n => DCD1,
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                                SOut => TXD1,
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                                RTS_n => RTS1,
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                                DTR_n => DTR1,
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                                OUT1_n => open,
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                                OUT2_n => open,
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                                BaudOut => BaudOut1,
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                                Intr => open);
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end;

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