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[/] [z80control/] [trunk/] [DE1/] [rtl/] [VHDL/] [t80/] [SSRAMX.vhd] - Blame information for rev 12

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1 12 tylerapohl
--
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-- Xilinx Block RAM, 8 bit wide and variable size (Min. 512 bytes)
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--
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-- Version : 0247
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--
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-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-- The latest version of this file can be found at:
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--      http://www.opencores.org/cvsweb.shtml/t51/
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--
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-- Limitations :
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--
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-- File history :
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--
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--      0240 : Initial release
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--
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--      0242 : Changed RAMB4_S8 to map by name
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--
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--      0247 : Added RAMB4_S8 component declaration
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity SSRAM is
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        generic(
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                AddrWidth       : integer := 11;
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                DataWidth       : integer := 8
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        );
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        port(
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                Clk                     : in std_logic;
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                CE_n            : in std_logic;
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                WE_n            : in std_logic;
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                A                       : in std_logic_vector(AddrWidth - 1 downto 0);
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                DIn                     : in std_logic_vector(DataWidth - 1 downto 0);
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                DOut            : out std_logic_vector(DataWidth - 1 downto 0)
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        );
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end SSRAM;
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architecture rtl of SSRAM is
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        component RAMB4_S8
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                port(
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                        DO     : out std_logic_vector(7 downto 0);
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                        ADDR   : in std_logic_vector(8 downto 0);
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                        CLK    : in std_ulogic;
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                        DI     : in std_logic_vector(7 downto 0);
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                        EN     : in std_ulogic;
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                        RST    : in std_ulogic;
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                        WE     : in std_ulogic);
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        end component;
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        constant RAMs : integer := (2 ** AddrWidth) / 512;
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        type bRAMOut_a is array(0 to RAMs - 1) of std_logic_vector(7 downto 0);
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        signal bRAMOut : bRAMOut_a;
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        signal biA_r : integer;
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        signal A_r : unsigned(A'left downto 0);
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--      signal A_i : std_logic_vector(8 downto 0);
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        signal WEA : std_logic_vector(RAMs - 1 downto 0);
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begin
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        process (Clk)
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        begin
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                if Clk'event and Clk = '1' then
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                        A_r <= unsigned(A);
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                end if;
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        end process;
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        biA_r <= to_integer(A_r(A'left downto 9));
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--      A_i <= std_logic_vector(A_r(8 downto 0)) when (CE_n nor WE_n) = '1' else A(8 downto 0);
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        bG1: for I in 0 to RAMs - 1 generate
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        begin
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                WEA(I) <= '1' when (CE_n nor WE_n) = '1' and biA_r = I else '0';
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                BSSRAM : RAMB4_S8
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                        port map(
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                                DI => DIn,
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                                EN => '1',
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                                WE => WEA(I),
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                                RST => '0',
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                                CLK => Clk,
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                                ADDR => A,
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                                DO => bRAMOut(I));
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        end generate;
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        process (biA_r, bRAMOut)
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        begin
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                DOut <= bRAMOut(0);
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                for I in 1 to RAMs - 1 loop
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                        if biA_r = I then
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                                DOut <= bRAMOut(I);
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                        end if;
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                end loop;
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        end process;
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end;

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