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tylerapohl |
--===========================================================================--
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--
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-- S Y N T H E Z I A B L E miniUART C O R E
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--
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-- www.OpenCores.Org - January 2000
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-- This core adheres to the GNU public license
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--
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-- Design units : miniUART core for the OCRP-1
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--
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-- File name : miniuart.vhd
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--
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-- Purpose : Implements an miniUART device for communication purposes
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-- between the OR1K processor and the Host computer through
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-- an RS-232 communication protocol.
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--
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-- Library : uart_lib.vhd
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--
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-- Dependencies : IEEE.Std_Logic_1164
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--
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-- Simulator : ModelSim PE/PLUS version 4.7b on a Windows95 PC
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--===========================================================================--
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-------------------------------------------------------------------------------
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-- Revision list
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-- Version Author Date Changes
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--
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-- 0.1 Ovidiu Lupas 15 January 2000 New model
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-- 1.0 Ovidiu Lupas January 2000 Synthesis optimizations
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-- 2.0 Ovidiu Lupas April 2000 Bugs removed - RSBusCtrl
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-- the RSBusCtrl did not process all possible situations
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--
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-- olupas@opencores.org
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-------------------------------------------------------------------------------
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-- Description : The memory consists of a dual-port memory addressed by
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-- two counters (RdCnt & WrCnt). The third counter (StatCnt)
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-- sets the status signals and keeps a track of the data flow.
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-------------------------------------------------------------------------------
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-- Entity for miniUART Unit - 9600 baudrate --
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.UART_Def.all;
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entity miniUART is
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port (
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SysClk : in Std_Logic; -- System Clock
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Reset : in Std_Logic; -- Reset input
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CS_N : in Std_Logic;
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RD_N : in Std_Logic;
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WR_N : in Std_Logic;
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RxD : in Std_Logic;
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TxD : out Std_Logic;
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IntRx_N : out Std_Logic; -- Receive interrupt
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IntTx_N : out Std_Logic; -- Transmit interrupt
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Addr : in Std_Logic_Vector(1 downto 0); --
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DataIn : in Std_Logic_Vector(7 downto 0); --
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DataOut : out Std_Logic_Vector(7 downto 0)); --
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end entity; --================== End of entity ==============================--
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-------------------------------------------------------------------------------
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-- Architecture for miniUART Controller Unit
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-------------------------------------------------------------------------------
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architecture uart of miniUART is
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-----------------------------------------------------------------------------
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-- Signals
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-----------------------------------------------------------------------------
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signal RxData : Std_Logic_Vector(7 downto 0); --
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signal TxData : Std_Logic_Vector(7 downto 0); --
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signal CSReg : Std_Logic_Vector(7 downto 0); -- Ctrl & status register
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-- CSReg detailed
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-----------+--------+--------+--------+--------+--------+--------+--------+
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-- CSReg(7)|CSReg(6)|CSReg(5)|CSReg(4)|CSReg(3)|CSReg(2)|CSReg(1)|CSReg(0)|
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-- Res | Res | Res | Res | UndRun | OvrRun | FErr | OErr |
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-----------+--------+--------+--------+--------+--------+--------+--------+
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signal EnabRx : Std_Logic; -- Enable RX unit
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signal EnabTx : Std_Logic; -- Enable TX unit
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signal DRdy : Std_Logic; -- Receive Data ready
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signal TRegE : Std_Logic; -- Transmit register empty
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signal TBufE : Std_Logic; -- Transmit buffer empty
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signal FErr : Std_Logic; -- Frame error
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signal OErr : Std_Logic; -- Output error
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signal Read : Std_Logic; -- Read receive buffer
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signal Load : Std_Logic; -- Load transmit buffer
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-----------------------------------------------------------------------------
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-- Baud rate Generator
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-----------------------------------------------------------------------------
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component ClkUnit is
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port (
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SysClk : in Std_Logic; -- System Clock
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EnableRX : out Std_Logic; -- Control signal
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EnableTX : out Std_Logic; -- Control signal
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Reset : in Std_Logic); -- Reset input
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end component;
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-----------------------------------------------------------------------------
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-- Receive Unit
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-----------------------------------------------------------------------------
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component RxUnit is
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port (
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Clk : in Std_Logic; -- Clock signal
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Reset : in Std_Logic; -- Reset input
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Enable : in Std_Logic; -- Enable input
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RxD : in Std_Logic; -- RS-232 data input
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RD : in Std_Logic; -- Read data signal
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FErr : out Std_Logic; -- Status signal
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OErr : out Std_Logic; -- Status signal
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DRdy : out Std_Logic; -- Status signal
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DataIn : out Std_Logic_Vector(7 downto 0));
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end component;
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-----------------------------------------------------------------------------
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-- Transmitter Unit
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-----------------------------------------------------------------------------
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component TxUnit is
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port (
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Clk : in Std_Logic; -- Clock signal
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Reset : in Std_Logic; -- Reset input
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Enable : in Std_Logic; -- Enable input
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Load : in Std_Logic; -- Load transmit data
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TxD : out Std_Logic; -- RS-232 data output
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TRegE : out Std_Logic; -- Tx register empty
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TBufE : out Std_Logic; -- Tx buffer empty
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DataO : in Std_Logic_Vector(7 downto 0));
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end component;
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begin
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-----------------------------------------------------------------------------
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-- Instantiation of internal components
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-----------------------------------------------------------------------------
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ClkDiv : ClkUnit port map (SysClk,EnabRX,EnabTX,Reset);
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TxDev : TxUnit port map (SysClk,Reset,EnabTX,Load,TxD,TRegE,TBufE,TxData);
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RxDev : RxUnit port map (SysClk,Reset,EnabRX,RxD,Read,FErr,OErr,DRdy,RxData);
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--IntRx_N <= DRdy;
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--IntTx_N <= TBufE;
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-----------------------------------------------------------------------------
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-- Implements the controller for Rx&Tx units
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-----------------------------------------------------------------------------
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RSBusCtrl : process(SysClk,Reset,Read,Load)
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variable StatM : Std_Logic_Vector(4 downto 0);
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begin
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if Rising_Edge(SysClk) then
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if Reset = '0' then
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StatM := "00000";
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--IntTx_N <= '0';
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--IntRx_N <= '0';
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CSReg <= "11110000";
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else
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StatM(0) := DRdy;
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StatM(1) := FErr;
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StatM(2) := OErr;
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StatM(3) := TBufE;
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StatM(4) := TRegE;
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end if;
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--case StatM is
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--when "00001" =>
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-- IntRx_N <= '1';
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-- CSReg(2) <= '1';
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--when "10001" =>
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-- IntRx_N <= '1';
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-- CSReg(2) <= '1';
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--when "01000" =>
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-- IntTx_N <= '1';
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--when "10000" =>
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-- IntTx_N <= '1';
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-- CSReg(3) <= '1';
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--when others => null;
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--end case;
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IntRx_N <= DRdy;
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IntTx_N <= TRegE;
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--if Read = '1' then
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-- CSReg(2) <= '0';
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-- IntRx_N <= '0';
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--end if;
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--if Load = '1' then
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-- CSReg(3) <= '0';
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-- IntTx_N <= '0';
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--end if;
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end if;
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end process;
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-----------------------------------------------------------------------------
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-- Combinational section
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-----------------------------------------------------------------------------
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process(SysClk)
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begin
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if (CS_N = '0' and RD_N = '0') then
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Read <= '1';
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else Read <= '0';
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end if;
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if (CS_N = '0' and WR_N = '0') then
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Load <= '1';
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else Load <= '0';
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end if;
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if Read = '0' then
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DataOut <= "ZZZZZZZZ";
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elsif (Read = '1' and Addr = "00") then
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DataOut <= RxData;
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elsif (Read = '1' and Addr = "01") then
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DataOut <= CSReg;
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end if;
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if Load = '0' then
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TxData <= "ZZZZZZZZ";
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elsif (Load = '1' and Addr = "00") then
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TxData <= DataIn;
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end if;
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end process;
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end uart; --===================== End of architecture =======================--
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