URL https://opencores.org/ocsvn/etherlab/etherlab/trunk

Subversion Repositories etherlab

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/etherlab/trunk/net/EtherSocket/EtherSocket.csproj

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/etherlab/trunk/net/EtherSocket/doc/Doxyfile

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/etherlab/trunk/net/EtherSocket/doc/EtherSocket.chm Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

/etherlab/trunk/net/EtherSocket/doc/EtherSocket.chm

etherlab/trunk/net/EtherSocket/doc/EtherSocket.chm Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: etherlab/trunk/net/EtherSocket/EtherSocket.suo =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: etherlab/trunk/net/EtherSocket/EtherSocket.suo =================================================================== --- etherlab/trunk/net/EtherSocket/EtherSocket.suo (nonexistent) +++ etherlab/trunk/net/EtherSocket/EtherSocket.suo (revision 2)

etherlab/trunk/net/EtherSocket/EtherSocket.suo Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: etherlab/trunk/net/EtherSocket/src/EtherSocket.cs =================================================================== --- etherlab/trunk/net/EtherSocket/src/EtherSocket.cs (nonexistent) +++ etherlab/trunk/net/EtherSocket/src/EtherSocket.cs (revision 2) @@ -0,0 +1,208 @@ +/****************************************************************************** + * ETHERLAB - FPGA To C# To LABVIEW Bridge * + ****************************************************************************** + * * + * Copyright (C)2012 Mathias Hörtnagl * + * * + * This program is free software: you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation, either version 3 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program. If not, see . * + ******************************************************************************/ +using System; +using System.Collections.Generic; +using System.Threading; + +using PcapDotNet.Core; +using PcapDotNet.Packets; +using PcapDotNet.Packets.Ethernet; + +namespace EtherLab +{ + ///

+ /// A socket for EtherLab communication. + /// + /// + /// Sending + /// + /// To send data, first update any channel's data with . + /// Subsequently call to send the updated EtherLab + /// packet. If isn't invoked at least once, + /// will NOT send the packet, as there is no updated + /// data available. + /// + ///










    +    ///     /**








    +    ///      * Create a new instance of EtherSocket with default








    +    ///      * destination MAC. The first parameter identifies the








    +    ///      * network device to select.








    +    ///      */








    +    ///     EtherSocket es = new EtherSocket(0, "00:1f:16:01:95:a5");








    +    ///








    +    ///     // Update data for channel H and B.








    +    ///     es.update(EChannel.CHANNEL_H, 0x1234);








    +    ///     es.update(EChannel.CHANNEL_B, 0x4321);








    +    ///








    +    ///     // Send the updated packet.








    +    ///     es.send();








    +    ///

+ /// + /// + /// + /// + /// Receiving + /// + /// EtherSocket starts a new Thread automatically for the reception process. + /// Data is read constatntly from the networ device. + /// To read a channel's current data chunk, invoke . + /// + /// NOTE: There is no locking mechanism, to circumvent reading data while + /// new data is read from the network device. + /// + ///










    +    ///     /**








    +    ///      * Create a new instance of EtherSocket with default








    +    ///      * destination MAC. The first parameter identifies the








    +    ///      * network device to select.








    +    ///      */








    +    ///     EtherSocket es = new EtherSocket(0, "00:1f:16:01:95:a5");








    +    ///








    +    ///     ushort data;








    +    ///








    +    ///     // Read data of channel H;








    +    ///     data = es.read(EChannel.CHANNEL_H);








    +    ///

+ /// + /// + ///

+ public sealed class EtherSocket + { + ///

+ /// Packet receiver filter. Capture packages with EtherType = 0x0000 + /// and with a Version 2 field only. + ///

+ private const String RCV_FILTER + = "(ether[12:2] = 0x0000) and (ether[14] = 0x02)"; + + private LivePacketDevice device; + private PacketCommunicator com; + private PacketBuilder builder; + private EtherLabLayer sendLayer; + private EtherLabLayer receiveLayer; + private Thread receiverThread; + + ///

+ /// Creates a new EtherSocket with "00:0a:35:00:00:00" as a default + /// destination MAC. + ///

+ /// The integer ID of the network device. + /// The source MAC address. + public EtherSocket(int deviceId, String srcMAC) + : this(deviceId, srcMAC, "00:0a:35:00:00:00") + { + } + + ///

+ /// Creates a new EtherSocket. + ///

+ /// The integer ID of the network device. + /// The source MAC address. + /// The destination MAC address. + public EtherSocket(int deviceId, String srcMAC, String dstMAC) + { + IList allDevices = LivePacketDevice.AllLocalMachine; + + if ( (allDevices.Count == 0) || (allDevices.Count < deviceId) ) + { + return; + } + + device = allDevices[deviceId]; + com = device.Open(56, PacketDeviceOpenAttributes.Promiscuous, 1000); + + // Filter packages. + using (BerkeleyPacketFilter filter = com.CreateFilter(RCV_FILTER)) + { + com.SetFilter(filter); + } + + EthernetLayer ethernetLayer = new EthernetLayer + { + Source = new MacAddress(srcMAC), + Destination = new MacAddress(dstMAC) + }; + + sendLayer = new EtherLabLayer(); + + builder = new PacketBuilder(ethernetLayer, sendLayer); + + // Start receiver thread. + receiverThread = new Thread(this.receive); + receiverThread.Start(); + } + + ///

+ /// Update channel data and set channel flag. Call send() to send + /// the updated data in a new packet. + ///

+ /// The channel to be updated. + /// The new data for that channel. + public void update(EChannel channel, ushort channelData) + { + sendLayer.update(channel, channelData); + } + + ///

+ /// Sends the current EtherLab packet and resets the channel + /// flags to 0. A packet is sent only if at least one channel + /// flag is set. + ///

+ public void send() + { + if (sendLayer.pendingSendData()) + { + com.SendPacket(builder.Build(DateTime.Now)); + sendLayer.reset(); + } + } + + ///

+ /// Receive a single packet. Packet data can be read with . + ///

+ private void receive() + { + com.ReceivePackets(0, PacketHandler); + } + + ///

+ /// Packet reception callback. + ///

+ /// The received packet. + private void PacketHandler(Packet packet) + { + EtherLabDatagram etherLabPacket + = new EtherLabDatagram(packet.Buffer, EthernetDatagram.HeaderLength, 18); + + receiveLayer = (EtherLabLayer) etherLabPacket.ExtractLayer(); + } + + ///

+ /// Read data for a channel from current received packet. If no packet + /// is available yet, this function returns 0. + ///

+ /// The channel to be read from. + /// The current channel data. + public ushort read(EChannel channel) + { + return (receiveLayer != null) ? receiveLayer.read(channel) : ushort.MinValue; + } + } +} \ No newline at end of file Index: etherlab/trunk/net/EtherSocket/src/etherlab/EChannel.cs =================================================================== --- etherlab/trunk/net/EtherSocket/src/etherlab/EChannel.cs (nonexistent) +++ etherlab/trunk/net/EtherSocket/src/etherlab/EChannel.cs (revision 2) @@ -0,0 +1,42 @@ +/****************************************************************************** + * ETHERLAB - FPGA To C# To LABVIEW Bridge * + ****************************************************************************** + * * + * Copyright (C)2012 Mathias Hörtnagl * + * * + * This program is free software: you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation, either version 3 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program. If not, see . * + ******************************************************************************/ +using System; +using System.Collections.Generic; +using System.Linq; +using System.Text; + +namespace EtherLab +{ + ///

+ /// Available channels A to H. + ///

+ [Flags] + public enum EChannel : int + { + CHANNEL_A = 0, + CHANNEL_B = 1, + CHANNEL_C = 2, + CHANNEL_D = 3, + CHANNEL_E = 4, + CHANNEL_F = 5, + CHANNEL_G = 6, + CHANNEL_H = 7 + } +} Index: etherlab/trunk/net/EtherSocket/src/etherlab/EtherLabLayer.cs =================================================================== --- etherlab/trunk/net/EtherSocket/src/etherlab/EtherLabLayer.cs (nonexistent) +++ etherlab/trunk/net/EtherSocket/src/etherlab/EtherLabLayer.cs (revision 2) @@ -0,0 +1,150 @@ +/****************************************************************************** + * ETHERLAB - FPGA To C# To LABVIEW Bridge * + ****************************************************************************** + * * + * Copyright (C)2012 Mathias Hörtnagl * + * * + * This program is free software: you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation, either version 3 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program. If not, see . * + ******************************************************************************/ +using PcapDotNet.Packets; +using PcapDotNet.Packets.Ethernet; + +namespace EtherLab +{ + ///

+ /// Represents the EtherLab layer for Pcap.NET. + ///

+ public sealed class EtherLabLayer : SimpleLayer, IEthernetNextLayer + { + ///

+ /// The version number of the EtherLab protocol. + ///

+ public byte Version { set; get; } + + ///

+ /// The channel number octet. Specifies the virtual channel this + /// package belongs to. + ///

+ public byte Channel { set; get; } + + ///

+ /// The channel data. 8 channels, 16 bit wide each. Data segment is 40 + /// byte wide as we need at least 42 byte of payload for an Ethernet + /// package (remaining 2 bytes are EtherLab header). + ///

+ public byte[] Data { get; set; } + + ///

+ /// The default MAC Address value when this layer is the Ethernet payload. + /// null means there is no default value. + ///

+ public MacAddress? PreviousLayerDefaultDestination + { + get { return EthernetDatagram.BroadcastAddress; } + } + + ///

+ /// The Ethernet Type the Ethernet layer should write when this layer is the Ethernet payload. + ///

+ public EthernetType PreviousLayerEtherType + { + get { return EthernetType.None; } + } + + ///

+ /// The number of bytes this layer will take. + ///

+ public override int Length + { + get { return EtherLabDatagram.HeaderLength + 16; } + } + + ///

+ /// Two EtherLabLayers are always equal. I could not find reasonable + /// comparison parameters. + ///

+ /// An EtherLabLayer instance. + /// True if the other instance is not null and an instance of EtherLabLayer. + public override bool Equals(Layer other) + { + return other != null && other.GetType() == GetType(); + } + + ///

+ /// Constructor for a default EtherLab package. + /// Version 1. + ///

+ public EtherLabLayer() + { + Version = 1; + Channel = 0; + Data = new byte[16]; + } + + ///

+ /// Writes the layer to the buffer. + /// This method ignores the payload length, and the previous and next layers. + ///

+ /// The buffer to write the layer to. + /// The offset in the buffer to start writing the layer at. + protected sealed override void Write(byte[] buffer, int offset) + { + EtherLabDatagram.Write(buffer, offset, Version, Channel, Data); + } + + ///

+ /// Checks, whether there is new data, that has not yet been sent. + ///

+ /// True, if at least one channel holds new data. + public bool pendingSendData() + { + return Channel != 0; + } + + ///

+ /// Update channel data and set channel flag. Upon next send, updated + /// data will be transmitted. + ///

+ /// The channel to be updated. + /// The new data. + public void update(EChannel channel, ushort channelData) + { + int pos = (int)channel; + Channel |= (byte)(1 << pos); + Data.Write(2 * pos, channelData, Endianity.Big); + } + + ///

+ /// Read data for a channel from current received packet. If no packet + /// is available yet, this function returns 0. + ///

+ /// The channel to be read from. + /// The current channel data. + public ushort read(EChannel channel) + { + int pos = (int)channel; + return Data.ReadUShort(2 * pos, Endianity.Big); + } + + ///

+ /// Reset channel flags to zero. Clear the flags after a package has + /// been sent. Only set channel flags trigger an update on hardware + /// level. + ///

+ public void reset() + { + Channel = 0; + } + } +} \ No newline at end of file Index: etherlab/trunk/net/EtherSocket/src/etherlab/EtherLabDatagram.cs =================================================================== --- etherlab/trunk/net/EtherSocket/src/etherlab/EtherLabDatagram.cs (nonexistent) +++ etherlab/trunk/net/EtherSocket/src/etherlab/EtherLabDatagram.cs (revision 2) @@ -0,0 +1,148 @@ +/****************************************************************************** + * ETHERLAB - FPGA To C# To LABVIEW Bridge * + ****************************************************************************** + * * + * Copyright (C)2012 Mathias Hörtnagl * + * * + * This program is free software: you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation, either version 3 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program. If not, see . * + ******************************************************************************/ +using PcapDotNet.Packets; + +namespace EtherLab +{ + ///

+ /// Represents an EtherLab datagram. + /// + /// An EtherLab Datagram sends data for all active channels in one + /// packet whenever send() is called. + /// A packet, whether sent or received, contains at most 8 independent + /// data chunks of 16 bit size each. + /// + ///









    +    /// +-----+----------------+----------------+








    +    /// | Bit | 0-7            | 8-15           |








    +    /// +-----+----------------+----------------+








    +    /// | 0   | Version        | Channels       |








    +    /// +-----+----------------+----------------+








    +    /// | 16  | Channel A Data                  |








    +    /// +-----+---------------------------------+








    +    /// | 32  | Channel B Data                  |








    +    /// +-----+---------------------------------+








    +    /// :     :                                 :








    +    /// +-----+---------------------------------+








    +    /// | 112 | Channel H Data                  |








    +    /// +-----+---------------------------------+








    +    ///

+ /// + /// + /// Channel Field + /// + /// The Channels field is 1 byte wide and can thus hold 8 seperate + /// channels. An active channel is repesented by its flag set to 1. + ///









    +    /// +-----+-------------------------------+








    +    /// | Bit | 8-15                          |








    +    /// +-----+---+---+---+---+---+---+---+---+








    +    /// | 8   | H | G | F | E | D | C | B | A |








    +    /// +-----+---+---+---+---+---+---+---+---+








    +    ///

+ /// Each channel is labeled with an alphabetic letter (A to H). + /// + ///

+ public sealed class EtherLabDatagram : Datagram + { + private static class Offset + { + public const int Version = 0; + public const int Channel = 1; + public const int Data = 2; + } + + ///

+ /// The number of bytes the EtherLab header takes. + ///

+ public const int HeaderLength = 2; + + ///

+ /// The version number of the EtherLab protocol. + ///

+ public byte Version + { + get { return this[Offset.Version]; } + } + + ///

+ /// The channel number octet. Specifies the virtual channel this + /// package belongs to. + ///

+ public byte Channel + { + get { return this[Offset.Channel]; } + } + + ///

+ public byte[] Data + { + get + { + return ReadBytes(Offset.Data, Length - HeaderLength); + } + } + + ///

+ /// Constructor for a new EtherLab Datagram. + ///

+ /// The buffer to write the layer to. + /// The offset in the buffer to start writing the layer at. + /// The datagram length. + internal EtherLabDatagram(byte[] buffer, int offset, int length) + : base(buffer, offset, length) + { + } + + ///

+ /// Creates a Layer that represents the datagram to be used with PacketBuilder. + ///

+ public override ILayer ExtractLayer() + { + return new EtherLabLayer + { + Version = Version, + Channel = Channel, + Data = Data + }; + } + + ///

+ /// Writes the Datagram to the buffer. + ///

+ /// The buffer to write the layer to. + /// The offset in the buffer to start writing the layer at. + /// The EtherLab protocol version. + /// The active channels. + /// The channels' data. + internal static void Write(byte[] buffer, int offset, byte version, byte channel, byte[] data) + { + buffer.Write(offset + Offset.Version, version); + buffer.Write(offset + Offset.Channel, channel); + + for (int i = 0; i < 16; i++) + buffer.Write(offset + Offset.Data + i, data[i]); + } + } +} \ No newline at end of file Index: etherlab/trunk/net/EtherSocket/EtherSocket.sln =================================================================== --- etherlab/trunk/net/EtherSocket/EtherSocket.sln (nonexistent) +++ etherlab/trunk/net/EtherSocket/EtherSocket.sln (revision 2) @@ -0,0 +1,42 @@ + +Microsoft Visual Studio Solution File, Format Version 11.00 +# Visual C# Express 2010 +Project("{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC}") = "EtherSocket", "EtherSocket.csproj", "{6E829278-25B3-41E9-BC3E-BF14E7C7E3D3}" +EndProject +Project("{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC}") = "EtherExamples", "..\EtherExamples\EtherExamples.csproj", "{6852F6B5-2F8B-4FBA-8438-ACF49FFF2A6A}" +EndProject +Global + GlobalSection(SolutionConfigurationPlatforms) = preSolution + Debug|Any CPU = Debug|Any CPU + Debug|Mixed Platforms = Debug|Mixed Platforms + Debug|x86 = Debug|x86 + Release|Any CPU = Release|Any CPU + Release|Mixed Platforms = Release|Mixed Platforms + Release|x86 = Release|x86 + EndGlobalSection + GlobalSection(ProjectConfigurationPlatforms) = postSolution + {6E829278-25B3-41E9-BC3E-BF14E7C7E3D3}.Debug|Any CPU.ActiveCfg = Debug|Any CPU + {6E829278-25B3-41E9-BC3E-BF14E7C7E3D3}.Debug|Any CPU.Build.0 = Debug|Any CPU + {6E829278-25B3-41E9-BC3E-BF14E7C7E3D3}.Debug|Mixed Platforms.ActiveCfg = Debug|Any CPU + {6E829278-25B3-41E9-BC3E-BF14E7C7E3D3}.Debug|Mixed Platforms.Build.0 = Debug|Any CPU + {6E829278-25B3-41E9-BC3E-BF14E7C7E3D3}.Debug|x86.ActiveCfg = Debug|Any CPU + {6E829278-25B3-41E9-BC3E-BF14E7C7E3D3}.Release|Any CPU.ActiveCfg = Release|Any CPU + {6E829278-25B3-41E9-BC3E-BF14E7C7E3D3}.Release|Any CPU.Build.0 = Release|Any CPU + {6E829278-25B3-41E9-BC3E-BF14E7C7E3D3}.Release|Mixed Platforms.ActiveCfg = Release|Any CPU + {6E829278-25B3-41E9-BC3E-BF14E7C7E3D3}.Release|Mixed Platforms.Build.0 = Release|Any CPU + {6E829278-25B3-41E9-BC3E-BF14E7C7E3D3}.Release|x86.ActiveCfg = Release|Any CPU + {6852F6B5-2F8B-4FBA-8438-ACF49FFF2A6A}.Debug|Any CPU.ActiveCfg = Debug|x86 + {6852F6B5-2F8B-4FBA-8438-ACF49FFF2A6A}.Debug|Mixed Platforms.ActiveCfg = Debug|x86 + {6852F6B5-2F8B-4FBA-8438-ACF49FFF2A6A}.Debug|Mixed Platforms.Build.0 = Debug|x86 + {6852F6B5-2F8B-4FBA-8438-ACF49FFF2A6A}.Debug|x86.ActiveCfg = Debug|x86 + {6852F6B5-2F8B-4FBA-8438-ACF49FFF2A6A}.Debug|x86.Build.0 = Debug|x86 + {6852F6B5-2F8B-4FBA-8438-ACF49FFF2A6A}.Release|Any CPU.ActiveCfg = Release|x86 + {6852F6B5-2F8B-4FBA-8438-ACF49FFF2A6A}.Release|Mixed Platforms.ActiveCfg = Release|x86 + {6852F6B5-2F8B-4FBA-8438-ACF49FFF2A6A}.Release|Mixed Platforms.Build.0 = Release|x86 + {6852F6B5-2F8B-4FBA-8438-ACF49FFF2A6A}.Release|x86.ActiveCfg = Release|x86 + {6852F6B5-2F8B-4FBA-8438-ACF49FFF2A6A}.Release|x86.Build.0 = Release|x86 + EndGlobalSection + GlobalSection(SolutionProperties) = preSolution + HideSolutionNode = FALSE + EndGlobalSection +EndGlobal Index: etherlab/trunk/net/EtherSocket/Properties/AssemblyInfo.cs =================================================================== --- etherlab/trunk/net/EtherSocket/Properties/AssemblyInfo.cs (nonexistent) +++ etherlab/trunk/net/EtherSocket/Properties/AssemblyInfo.cs (revision 2) @@ -0,0 +1,38 @@ +using System.Reflection; +using System.Runtime.CompilerServices; +using System.Runtime.InteropServices; +using System.Resources; + +// Allgemeine Informationen über eine Assembly werden über die folgenden +// Attribute gesteuert. Ändern Sie diese Attributwerte, um die Informationen zu ändern, +// die mit einer Assembly verknüpft sind. +[assembly: AssemblyTitle("EtherSocket")] +[assembly: AssemblyDescription("")] +[assembly: AssemblyConfiguration("")] +[assembly: AssemblyCompany("")] +[assembly: AssemblyProduct("EtheSocket")] +[assembly: AssemblyCopyright("Copyright © 2012")] +[assembly: AssemblyTrademark("GNU GPL v3")] +[assembly: AssemblyCulture("")] + +// Durch Festlegen von ComVisible auf "false" werden die Typen in dieser Assembly unsichtbar +// für COM-Komponenten. Wenn Sie auf einen Typ in dieser Assembly von +// COM zugreifen müssen, legen Sie das ComVisible-Attribut für diesen Typ auf "true" fest. +[assembly: ComVisible(true)] + +// Die folgende GUID bestimmt die ID der Typbibliothek, wenn dieses Projekt für COM verfügbar gemacht wird +[assembly: Guid("22fc37be-a1bd-4432-89ee-01094a1fdf27")] + +// Versionsinformationen für eine Assembly bestehen aus den folgenden vier Werten: +// +// Hauptversion +// Nebenversion +// Buildnummer +// Revision +// +// Sie können alle Werte angeben oder die standardmäßigen Build- und Revisionsnummern +// übernehmen, indem Sie "*" eingeben: +// [assembly: AssemblyVersion("1.0.*")] +[assembly: AssemblyVersion("1.0.0.0")] +[assembly: AssemblyFileVersion("1.0.0.0")] +[assembly: NeutralResourcesLanguageAttribute("en-US")] Index: etherlab/trunk/net/EtherSocket/Properties/ethesocket.manifest =================================================================== --- etherlab/trunk/net/EtherSocket/Properties/ethesocket.manifest (nonexistent) +++ etherlab/trunk/net/EtherSocket/Properties/ethesocket.manifest (revision 2) @@ -0,0 +1,22 @@ + + + + + + + + + + + + Index: etherlab/trunk/net/EtherSocket/EtherSocket.csproj.user =================================================================== --- etherlab/trunk/net/EtherSocket/EtherSocket.csproj.user (nonexistent) +++ etherlab/trunk/net/EtherSocket/EtherSocket.csproj.user (revision 2) @@ -0,0 +1,13 @@ + + + + + + + + + + de-DE + false + + \ No newline at end of file Index: etherlab/trunk/net/EtherExamples/app.config =================================================================== --- etherlab/trunk/net/EtherExamples/app.config (nonexistent) +++ etherlab/trunk/net/EtherExamples/app.config (revision 2) @@ -0,0 +1,3 @@ + + + Index: etherlab/trunk/net/EtherExamples/EtherExamples.csproj =================================================================== --- etherlab/trunk/net/EtherExamples/EtherExamples.csproj (nonexistent) +++ etherlab/trunk/net/EtherExamples/EtherExamples.csproj (revision 2) @@ -0,0 +1,66 @@ + + + + Debug + x86 + 8.0.30703 + 2.0 + {6852F6B5-2F8B-4FBA-8438-ACF49FFF2A6A} + Exe + Properties + EtherExamples + EtherExamples + v3.5 + Client + 512 + + + x86 + true + full + false + bin\Debug\ + DEBUG;TRACE + prompt + 4 + + + x86 + pdbonly + true + bin\Release\ + TRACE + prompt + 4 + + + + + + + + + + + + + + + + + {6E829278-25B3-41E9-BC3E-BF14E7C7E3D3} + EtherSocket + + + + + + + + \ No newline at end of file Index: etherlab/trunk/net/EtherExamples/Properties/AssemblyInfo.cs =================================================================== --- etherlab/trunk/net/EtherExamples/Properties/AssemblyInfo.cs (nonexistent) +++ etherlab/trunk/net/EtherExamples/Properties/AssemblyInfo.cs (revision 2) @@ -0,0 +1,36 @@ +using System.Reflection; +using System.Runtime.CompilerServices; +using System.Runtime.InteropServices; + +// Allgemeine Informationen über eine Assembly werden über die folgenden +// Attribute gesteuert. Ändern Sie diese Attributwerte, um die Informationen zu ändern, +// die mit einer Assembly verknüpft sind. +[assembly: AssemblyTitle("EtherExamples")] +[assembly: AssemblyDescription("")] +[assembly: AssemblyConfiguration("")] +[assembly: AssemblyCompany("")] +[assembly: AssemblyProduct("EtherExamples")] +[assembly: AssemblyCopyright("Copyright © 2012")] +[assembly: AssemblyTrademark("")] +[assembly: AssemblyCulture("")] + +// Durch Festlegen von ComVisible auf "false" werden die Typen in dieser Assembly unsichtbar +// für COM-Komponenten. Wenn Sie auf einen Typ in dieser Assembly von +// COM zugreifen müssen, legen Sie das ComVisible-Attribut für diesen Typ auf "true" fest. +[assembly: ComVisible(false)] + +// Die folgende GUID bestimmt die ID der Typbibliothek, wenn dieses Projekt für COM verfügbar gemacht wird +[assembly: Guid("c5aea2f1-9a9d-4d53-aa5e-59c7ebd35bc9")] + +// Versionsinformationen für eine Assembly bestehen aus den folgenden vier Werten: +// +// Hauptversion +// Nebenversion +// Buildnummer +// Revision +// +// Sie können alle Werte angeben oder die standardmäßigen Build- und Revisionsnummern +// übernehmen, indem Sie "*" eingeben: +// [assembly: AssemblyVersion("1.0.*")] +[assembly: AssemblyVersion("1.0.0.0")] +[assembly: AssemblyFileVersion("1.0.0.0")] Index: etherlab/trunk/net/EtherExamples/examples/SequenceLight.cs =================================================================== --- etherlab/trunk/net/EtherExamples/examples/SequenceLight.cs (nonexistent) +++ etherlab/trunk/net/EtherExamples/examples/SequenceLight.cs (revision 2) @@ -0,0 +1,95 @@ +/****************************************************************************** + * ETHERLAB - FPGA To C# To LABVIEW Bridge * + ****************************************************************************** + * * + * Copyright (C)2012 Mathias Hörtnagl * + * * + * This program is free software: you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation, either version 3 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program. If not, see . * + ******************************************************************************/ +using System; +using System.Threading; + +namespace EtherLab.Examples +{ + ///

+ /// Demonstartes sample usage of EtherLab. Controlls a sequence + /// light with an EtherLab connection. + ///

+ class SequenceLight + { + static void Main(string[] args) + { + /** + * Create a new instance of EtherSocket with default + * destination MAC. The first parameter identifies the + * network device to select. + */ + EtherSocket es = new EtherSocket(0, "00:1f:16:01:95:a5"); + + // Indicates, wich LED is on. + byte run = 0x01; + // The current states of the 4 switches. + ushort switches; + + while (true) + { + // Update channel H (LED). + es.update(EChannel.CHANNEL_H, run); + // Send the updated LED data. + es.send(); + + // Read the switch states. + switches = es.read(EChannel.CHANNEL_H); + // If rightmost switch is on, rotate right, else left. + run = set(switches, 0) ? ror(run, 1) : rol(run, 1); + + // Wait, to see the sequence light show happen. + Thread.Sleep(500); + } + } + + ///

+ /// Checks, if bit is set. + ///

+ /// The bit field. + /// The bit to check. + /// True, if bit is set. + public static Boolean set(ushort val, int bit) + { + return (val & (1 << bit)) != 0; + } + + ///

+ /// Bitwise rotate left. + ///

+ /// The bit field. + /// The number of bits to rotate. + /// Left rotated bit field. + public static byte rol(byte val, int sh) + { + return (byte)(val<> (8 - sh)); + } + + ///

+ /// Bitwise rotate right. + ///

+ /// The bit field. + /// The number of bits to rotate. + /// Right rotated bit field. + public static byte ror(byte val, int sh) + { + return (byte)(val >> sh | val << (8 - sh)); + } + } +} \ No newline at end of file Index: etherlab/trunk/xilinx/etherlab.prj =================================================================== --- etherlab/trunk/xilinx/etherlab.prj (nonexistent) +++ etherlab/trunk/xilinx/etherlab.prj (revision 2) @@ -0,0 +1,8 @@ +vhdl work "../vhdl/PCK_CRC32_D4.vhd" +vhdl work "../vhdl/common.vhd" +vhdl work "../vhdl/mac_snd.vhd" +vhdl work "../vhdl/mac_rcv.vhd" +vhdl work "../vhdl/io.vhd" +vhdl work "clock.vhd" +vhdl work "../vhdl/etherlab.vhd" + Index: etherlab/trunk/xilinx/etherlab.ucf =================================================================== --- etherlab/trunk/xilinx/etherlab.ucf (nonexistent) +++ etherlab/trunk/xilinx/etherlab.ucf (revision 2) @@ -0,0 +1,87 @@ +# ==== Primary Clock ==== +NET "clk" LOC = C9 | IOSTANDARD = "LVCMOS33" | TNM_NET = CLK_I; +TIMESPEC TS_CLK_I = PERIOD "clk" 20 ns HIGH 50%; + +NET "clk" CLOCK_DEDICATED_ROUTE = FALSE; +PIN "inst_clock/DCM_SP_INST.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE; + +# ==== Ethernet PHY ==== +NET "E_COL" LOC = "U6" | IOSTANDARD = LVCMOS33; +NET "E_CRS" LOC = "U13" | IOSTANDARD = LVCMOS33; +NET "E_MDC" LOC = "P9" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8; +NET "E_MDIO" LOC = "U5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8; +NET "E_RX_CLK" LOC = "V3" | IOSTANDARD = LVCMOS33 | TNM_NET = "RXCLK_GRP"; +NET "E_RX_DV" LOC = "V2" | IOSTANDARD = LVCMOS33; +NET "E_RXD<0>" LOC = "V8" | IOSTANDARD = LVCMOS33; +NET "E_RXD<1>" LOC = "T11" | IOSTANDARD = LVCMOS33; +NET "E_RXD<2>" LOC = "U11" | IOSTANDARD = LVCMOS33; +NET "E_RXD<3>" LOC = "V14" | IOSTANDARD = LVCMOS33; +NET "E_RX_ER" LOC = "U14" | IOSTANDARD = LVCMOS33; +NET "E_TX_CLK" LOC = "T7" | IOSTANDARD = LVCMOS33 | TNM_NET = "TXCLK_GRP"; +NET "E_TX_EN" LOC = "P15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8; +NET "E_TXD<0>" LOC = "R11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8; +NET "E_TXD<1>" LOC = "T15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8; +NET "E_TXD<2>" LOC = "R5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8; +NET "E_TXD<3>" LOC = "T5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8; +NET "E_TX_ER" LOC = "R6" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8; + +TIMESPEC "TSTXOUT" = FROM "TXCLK_GRP" TO "PADS" 11 ns; +TIMESPEC "TSRXIN" = FROM "PADS" TO "RXCLK_GRP" 10 ns; + +NET "E_TX_CLK" MAXSKEW= 2.0 ns; +NET "E_TX_CLK" PERIOD = 40 ns HIGH 14 ns; +NET "E_TX_CLK" CLOCK_DEDICATED_ROUTE = FALSE; + +NET "E_RX_CLK" MAXSKEW= 2.0 ns; +NET "E_RX_CLK" PERIOD = 40 ns HIGH 14 ns; +NET "E_RX_CLK" CLOCK_DEDICATED_ROUTE = FALSE; + +# ==== DAC/ADC === +NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 ; +NET "SPI_MOSI" LOC = "T4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8; +NET "SPI_SCK" LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8; +NET "DAC_CS" LOC = "N8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8; +NET "DAC_CLR" LOC = "P8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8; + +# == Disable lines === +NET "SF_OE" LOC = "C18" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2; +NET "SF_CE" LOC = "D16" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2; +NET "SF_WE" LOC = "D17" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2; +NET "FPGA_INIT_B" LOC = "T3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4; +NET "SPI_SS_B" LOC = "U3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6; +NET "AD_CONV" LOC = "P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6; +NET "AMP_CS" LOC = "N7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6; + +# ==== 6-pin header J1 - Digital Input ==== +#NET "DI<3>" LOC = "B4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8; +#NET "DI<2>" LOC = "A4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8; +#NET "DI<1>" LOC = "D5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8; +#NET "DI<0>" LOC = "C5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8; + +# ==== 6-pin header J2 - Digital Output ==== +NET "DO<3>" LOC = "A6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8; +NET "DO<2>" LOC = "B6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8; +NET "DO<1>" LOC = "E7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8; +NET "DO<0>" LOC = "F7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8; + +# === LEDs === +NET "LED<7>" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8; +NET "LED<6>" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8; +NET "LED<5>" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8; +NET "LED<4>" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8; +NET "LED<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8; +NET "LED<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8; +NET "LED<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8; +NET "LED<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8; + +# === SWITCHES === +NET "SW<0>" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP; +NET "SW<1>" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP; +NET "SW<2>" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP; +NET "SW<3>" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP; + +# === Buttons === +NET "BTN<3>" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN; +NET "BTN<2>" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN; +NET "BTN<1>" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN; +NET "BTN<0>" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN; \ No newline at end of file Index: etherlab/trunk/xilinx/etherlab.xst =================================================================== --- etherlab/trunk/xilinx/etherlab.xst (nonexistent) +++ etherlab/trunk/xilinx/etherlab.xst (revision 2) @@ -0,0 +1,56 @@ +set -tmpdir "xst/projnav.tmp" +set -xsthdpdir "xst" +run +-ifn etherlab.prj +-ifmt mixed +-ofn etherlab +-ofmt NGC +-p xc3s500e-4-fg320 +-top etherlab +-opt_mode Speed +-opt_level 1 +-iuc NO +-keep_hierarchy No +-netlist_hierarchy As_Optimized +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case Maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style LUT +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract Yes +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-auto_bram_packing NO +-mux_extract Yes +-resource_sharing YES +-async_to_sync NO +-mult_style Auto +-iobuf YES +-max_fanout 500 +-bufg 24 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-use_clock_enable Yes +-use_sync_set Yes +-use_sync_reset Yes +-iob Auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 Index: etherlab/trunk/xilinx/upload.cmds =================================================================== --- etherlab/trunk/xilinx/upload.cmds (nonexistent) +++ etherlab/trunk/xilinx/upload.cmds (revision 2) @@ -0,0 +1,6 @@ +setMode -bs +setCable -p auto +identify +assignFile -p 1 -file etherlab.bit +program -p 1 +quit \ No newline at end of file Index: etherlab/trunk/xilinx/clock.vhd =================================================================== --- etherlab/trunk/xilinx/clock.vhd (nonexistent) +++ etherlab/trunk/xilinx/clock.vhd (revision 2) @@ -0,0 +1,95 @@ +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 13.1 +-- \ \ Application : xaw2vhdl +-- / / Filename : clock.vhd +-- /___/ /\ Timestamp : 02/27/2012 13:36:57 +-- \ \ / \ +-- \___\/\___\ +-- +--Command: xaw2vhdl-st C:\Mathias\smole\etherlab\xilinx\ipcore_dir\.\clock.xaw C:\Mathias\smole\etherlab\xilinx\ipcore_dir\.\clock +--Design Name: clock +--Device: xc3s500e-4fg320 +-- +-- Module clock +-- Generated by Xilinx Architecture Wizard +-- Written for synthesis tool: XST + +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +library UNISIM; +use UNISIM.Vcomponents.ALL; + +entity clock is + port ( CLKIN_IN : in std_logic; + RST_IN : in std_logic; + CLKIN_IBUFG_OUT : out std_logic; + CLK0_OUT : out std_logic; + CLK90_OUT : out std_logic); +end clock; + +architecture BEHAVIORAL of clock is + signal CLKFB_IN : std_logic; + signal CLKIN_IBUFG : std_logic; + signal CLK0_BUF : std_logic; + signal CLK90_BUF : std_logic; + signal GND_BIT : std_logic; +begin + GND_BIT <= '0'; + CLKIN_IBUFG_OUT <= CLKIN_IBUFG; + CLK0_OUT <= CLKFB_IN; + CLKIN_IBUFG_INST : IBUFG + port map (I=>CLKIN_IN, + O=>CLKIN_IBUFG); + + CLK0_BUFG_INST : BUFG + port map (I=>CLK0_BUF, + O=>CLKFB_IN); + + CLK90_BUFG_INST : BUFG + port map (I=>CLK90_BUF, + O=>CLK90_OUT); + + DCM_SP_INST : DCM_SP + generic map( CLK_FEEDBACK => "1X", + CLKDV_DIVIDE => 2.0, + CLKFX_DIVIDE => 1, + CLKFX_MULTIPLY => 4, + CLKIN_DIVIDE_BY_2 => FALSE, + CLKIN_PERIOD => 20.000, + CLKOUT_PHASE_SHIFT => "NONE", + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", + DFS_FREQUENCY_MODE => "LOW", + DLL_FREQUENCY_MODE => "LOW", + DUTY_CYCLE_CORRECTION => TRUE, + FACTORY_JF => x"C080", + PHASE_SHIFT => 0, + STARTUP_WAIT => FALSE) + port map (CLKFB=>CLKFB_IN, + CLKIN=>CLKIN_IBUFG, + DSSEN=>GND_BIT, + PSCLK=>GND_BIT, + PSEN=>GND_BIT, + PSINCDEC=>GND_BIT, + RST=>RST_IN, + CLKDV=>open, + CLKFX=>open, + CLKFX180=>open, + CLK0=>CLK0_BUF, + CLK2X=>open, + CLK2X180=>open, + CLK90=>CLK90_BUF, + CLK180=>open, + CLK270=>open, + LOCKED=>open, + PSDONE=>open, + STATUS=>open); + +end BEHAVIORAL; + + Index: etherlab/trunk/xilinx/etherlab.ut =================================================================== --- etherlab/trunk/xilinx/etherlab.ut (nonexistent) +++ etherlab/trunk/xilinx/etherlab.ut (revision 2) @@ -0,0 +1,22 @@ +-w +-g DebugBitstream:No +-g Binary:no +-g CRC:Enable +-g ConfigRate:1 +-g ProgPin:PullUp +-g DonePin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g DCMShutdown:Disable +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:No +-g DriveDone:No Index: etherlab/trunk/xilinx/Makefile =================================================================== --- etherlab/trunk/xilinx/Makefile (nonexistent) +++ etherlab/trunk/xilinx/Makefile (revision 2) @@ -0,0 +1,47 @@ +#------------------------------------------------------------------------------# +# Xilinx Makefile # +#------------------------------------------------------------------------------# +# Copyright (C) 2012 Mathias Hoertnagl, mathias.hoertnagl@gmail.com # +# # +# This program is free software; you can redistribute it and/or modify it # +# under the terms of the GNU General Public License as published by the Free # +# Software Foundation; either version 3 of the License, or (at your option) # +# any later version. # +# This program is distributed in the hope that it will be useful, but WITHOUT # +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or # +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for # +# more details. # +# You should have received a copy of the GNU General Public License along with # +# this program; if not, see . # +#------------------------------------------------------------------------------# +TOOL_DIR = /cygdrive/c/Xilinx/13.1/ISE_DS/ISE/bin/nt/ + +XST = $(TOOL_DIR)xst.exe +NGDBUILD = $(TOOL_DIR)ngdbuild.exe +MAP = $(TOOL_DIR)map.exe +PAR = $(TOOL_DIR)par.exe +TRCE = $(TOOL_DIR)trce.exe +BITGEN = $(TOOL_DIR)bitgen.exe +IMPACT = $(TOOL_DIR)impact.exe + +upload : etherlab.bit + $(IMPACT) -batch upload.cmds + +build : + -@mkdir xst + -@mkdir xst/projnav.tmp + $(XST) -ifn etherlab.xst -ofn etherlab.syr -intstyle ise + $(NGDBUILD) -intstyle ise -dd ngdbuild -nt timestamp -uc etherlab.ucf \ + -p xc3s500e-fg320-4 etherlab.ngc etherlab.ngd + $(MAP) -intstyle ise -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 \ + -o etherlab_map.ncd etherlab.ngd etherlab.pcf + $(PAR) -w -intstyle ise -ol high -t 1 etherlab_map.ncd etherlab.ncd etherlab.pcf + $(TRCE) -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml etherlab.twx etherlab.ncd \ + -o etherlab.twr etherlab.pcf -ucf etherlab.ucf + $(BITGEN) -intstyle ise -f etherlab.ut etherlab.ncd + +.PHONY: clean +clean : + -@$(RM) *.bgn *.bld *.drc *.cmd_log *.lso *.ncd *.ngc *.ngd *.ngr *.pad \ + *.par *.pcf *.ptwx *.stx *.syr *.twr *.twx *.unroutes *.xpi *.xwbt \ + *.map *.mrp *.xrpt *.csv *.txt *.xml *.html *.log *.ngm *.prm *.cfi *.sig \ No newline at end of file Index: etherlab/trunk/vhdl/PCK_CRC32_D4.vhd =================================================================== --- etherlab/trunk/vhdl/PCK_CRC32_D4.vhd (nonexistent) +++ etherlab/trunk/vhdl/PCK_CRC32_D4.vhd (revision 2) @@ -0,0 +1,86 @@ +-------------------------------------------------------------------------------- +-- Copyright (C) 1999-2008 Easics NV. +-- This source file may be used and distributed without restriction +-- provided that this copyright statement is not removed from the file +-- and that any derivative work contains the original copyright notice +-- and the associated disclaimer. +-- +-- THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS +-- OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED +-- WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. +-- +-- Purpose : synthesizable CRC function +-- * polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32) +-- * data width: 4 +-- +-- Info : tools@easics.be +-- http://www.easics.com +-------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; + +package PCK_CRC32_D4 is + -- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32) + -- data width: 4 + -- convention: the first serial bit is D[3] + function nextCRC32_D4 + (Data: std_logic_vector(3 downto 0); + crc: std_logic_vector(31 downto 0)) + return std_logic_vector; +end PCK_CRC32_D4; + + +package body PCK_CRC32_D4 is + + -- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32) + -- data width: 4 + -- convention: the first serial bit is D[3] + function nextCRC32_D4 + (Data: std_logic_vector(3 downto 0); + crc: std_logic_vector(31 downto 0)) + return std_logic_vector is + + variable d: std_logic_vector(3 downto 0); + variable c: std_logic_vector(31 downto 0); + variable newcrc: std_logic_vector(31 downto 0); + + begin + d := Data; + c := crc; + + newcrc(0) := d(0) xor c(28); + newcrc(1) := d(1) xor d(0) xor c(28) xor c(29); + newcrc(2) := d(2) xor d(1) xor d(0) xor c(28) xor c(29) xor c(30); + newcrc(3) := d(3) xor d(2) xor d(1) xor c(29) xor c(30) xor c(31); + newcrc(4) := d(3) xor d(2) xor d(0) xor c(0) xor c(28) xor c(30) xor c(31); + newcrc(5) := d(3) xor d(1) xor d(0) xor c(1) xor c(28) xor c(29) xor c(31); + newcrc(6) := d(2) xor d(1) xor c(2) xor c(29) xor c(30); + newcrc(7) := d(3) xor d(2) xor d(0) xor c(3) xor c(28) xor c(30) xor c(31); + newcrc(8) := d(3) xor d(1) xor d(0) xor c(4) xor c(28) xor c(29) xor c(31); + newcrc(9) := d(2) xor d(1) xor c(5) xor c(29) xor c(30); + newcrc(10) := d(3) xor d(2) xor d(0) xor c(6) xor c(28) xor c(30) xor c(31); + newcrc(11) := d(3) xor d(1) xor d(0) xor c(7) xor c(28) xor c(29) xor c(31); + newcrc(12) := d(2) xor d(1) xor d(0) xor c(8) xor c(28) xor c(29) xor c(30); + newcrc(13) := d(3) xor d(2) xor d(1) xor c(9) xor c(29) xor c(30) xor c(31); + newcrc(14) := d(3) xor d(2) xor c(10) xor c(30) xor c(31); + newcrc(15) := d(3) xor c(11) xor c(31); + newcrc(16) := d(0) xor c(12) xor c(28); + newcrc(17) := d(1) xor c(13) xor c(29); + newcrc(18) := d(2) xor c(14) xor c(30); + newcrc(19) := d(3) xor c(15) xor c(31); + newcrc(20) := c(16); + newcrc(21) := c(17); + newcrc(22) := d(0) xor c(18) xor c(28); + newcrc(23) := d(1) xor d(0) xor c(19) xor c(28) xor c(29); + newcrc(24) := d(2) xor d(1) xor c(20) xor c(29) xor c(30); + newcrc(25) := d(3) xor d(2) xor c(21) xor c(30) xor c(31); + newcrc(26) := d(3) xor d(0) xor c(22) xor c(28) xor c(31); + newcrc(27) := d(1) xor c(23) xor c(29); + newcrc(28) := d(2) xor c(24) xor c(30); + newcrc(29) := d(3) xor c(25) xor c(31); + newcrc(30) := c(26); + newcrc(31) := c(27); + return newcrc; + end nextCRC32_D4; + +end PCK_CRC32_D4; Index: etherlab/trunk/vhdl/mac_snd.vhd =================================================================== --- etherlab/trunk/vhdl/mac_snd.vhd (nonexistent) +++ etherlab/trunk/vhdl/mac_snd.vhd (revision 2) @@ -0,0 +1,239 @@ +-------------------------------------------------------------------------------- +-- ETHERLAB - FPGA To C# To LABVIEW Bridge -- +-------------------------------------------------------------------------------- +-- REFERENCES -- +-- [1] http://tools.ietf.org/html/rfc2460 -- +-- [2] https://en.wikipedia.org/wiki/Ethernet_frame -- +-- [5] http://outputlogic.com/my-stuff/circuit-cellar-january-2010-crc.pdf -- +-- [6] OPB Ethernet Lite Media Access Controller (v1.01b) -- +-- [7] LAN83C185 - 10/100 Ethernet PHY -- +-- [8] Xilinx UG230 -- +-------------------------------------------------------------------------------- +-- Copyright (C)2012 Mathias H�rtnagl -- +-- -- +-- This program is free software: you can redistribute it and/or modify -- +-- it under the terms of the GNU General Public License as published by -- +-- the Free Software Foundation, either version 3 of the License, or -- +-- (at your option) any later version. -- +-- -- +-- This program is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- +-- GNU General Public License for more details. -- +-- -- +-- You should have received a copy of the GNU General Public License -- +-- along with this program. If not, see . -- +-------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.PCK_CRC32_D4.all; +use work.common.all; + +entity mac_snd is + port( + E_TX_CLK : in std_logic; -- Sender Clock. + E_TX_EN : out std_logic; -- Sender Enable. + E_TXD : out std_logic_vector(3 downto 0); -- Sent Data. + E_TX_ER : out std_logic; -- Sent Data Error. + el_chnl : in std_logic_vector(7 downto 0); -- EtherLab channels. + el_data : in data_t; -- EtherLab data. + en : in std_logic -- User Start Send. + ); +end mac_snd; + +architecture rtl of mac_snd is + + type mem_t is array(0 to 14) of std_logic_vector(7 downto 0); + + signal mem : mem_t := ( + -------------------------------------------------------------------------- + -- Host PC MAC Address -- + -------------------------------------------------------------------------- + -- 0x0 - 0x5 + x"00", x"1f", x"16", x"01", x"95", x"5a", + + -------------------------------------------------------------------------- + -- FPGA MAC Address (Xilinx OUI) -- + -------------------------------------------------------------------------- + -- 0x6 - 0xb + x"00", x"0a", x"35", x"00", x"00", x"00", + + -------------------------------------------------------------------------- + -- EtherType Field: 0x0000 (EtherLab) -- + -------------------------------------------------------------------------- + -- 0xc - 0xd + x"00", x"00", + + -------------------------------------------------------------------------- + -- EtherLab Header -- + -------------------------------------------------------------------------- + -- EtherLab Version. + -- Hardware returns Version 2 packets to distinguish them from Version 1 + -- packets sent by the host who captures in promiscuous mode only. This + -- would cause the host to read it's own Version 1 packets as well. + -- 0xe + x"02" + ); + + attribute RAM_STYLE : string; + attribute RAM_STYLE of mem: signal is "BLOCK"; + + type state_t is ( + Idle, -- Wait for signal en. + Preamble, -- 55 55 55 55 55 55 55 5 + StartOfFrame, -- d + Upper, -- Send upper Nibble. + Lower, -- Send lower Nibble. + Channel, -- Send EtherLab channel. + DataU, DataL, -- Send EtherLab data. + FrameCheck, -- No Frame Check for now. + InterframeGap -- Gap between two cosecutive frames (93 Bit). + ); + + type snd_t is record + s : state_t; + crc : std_logic_vector(31 downto 0); -- CRC32 latch. + c : natural range 0 to 63; + a : natural range 0 to 7; + end record; + + signal s, sin : snd_t := snd_t'(Idle, x"ffffffff", 0, 0); +begin + + snd_nsl : process(s, mem, en, el_chnl, el_data) + begin + + sin <= s; + E_TX_EN <= '0'; + E_TXD <= x"0"; + E_TX_ER <= '0'; + + case s.s is + when Idle => + if en = '1' then + sin.c <= 0; + sin.s <= Preamble; + end if; + + ----------------------------------------------------------------------- + -- Ethernet II - Preamble and Start Of Frame. -- + ----------------------------------------------------------------------- + when Preamble => + E_TXD <= x"5"; + E_TX_EN <= '1'; + if s.c = 14 then + sin.c <= 0; + sin.s <= StartOfFrame; + else + sin.c <= s.c + 1; + end if; + + when StartOfFrame => + E_TXD <= x"d"; + E_TX_EN <= '1'; + sin.crc <= x"ffffffff"; + sin.s <= Upper; + + ----------------------------------------------------------------------- + -- Custom Protocol Transmit. -- + ----------------------------------------------------------------------- + when Upper => + E_TXD <= mem(s.c)(3 downto 0); + E_TX_EN <= '1'; + sin.crc <= nextCRC32_D4(mem(s.c)(3 downto 0), s.crc); + sin.s <= Lower; + + when Lower => + E_TXD <= mem(s.c)(7 downto 4); + E_TX_EN <= '1'; + sin.crc <= nextCRC32_D4(mem(s.c)(7 downto 4), s.crc); + if s.c = 14 then + sin.c <= 0; + sin.s <= Channel; + else + sin.c <= s.c + 1; + sin.s <= Upper; + end if; + + ----------------------------------------------------------------------- + -- EtherLab - Channel Flags. -- + ----------------------------------------------------------------------- + when Channel => + E_TXD <= el_chnl(4*s.c+3 downto 4*s.c); + E_TX_EN <= '1'; + sin.crc <= nextCRC32_D4(el_chnl(4*s.c+3 downto 4*s.c), s.crc); + if s.c = 1 then + sin.c <= 0; + sin.a <= 0; + sin.s <= DataU; + else + sin.c <= s.c + 1; + end if; + + ----------------------------------------------------------------------- + -- EtherLab - Data. 8 channels � 16 bit. -- + ----------------------------------------------------------------------- + when DataU => + E_TXD <= el_data(s.a)(4*s.c+11 downto 4*s.c+8); + E_TX_EN <= '1'; + sin.crc <= nextCRC32_D4(el_data(s.a)(4*s.c+11 downto 4*s.c+8), s.crc); + if s.c = 1 then + sin.c <= 0; + sin.s <= DataL; + else + sin.c <= s.c + 1; + end if; + + when DataL => + E_TXD <= el_data(s.a)(4*s.c+3 downto 4*s.c); + E_TX_EN <= '1'; + sin.crc <= nextCRC32_D4(el_data(s.a)(4*s.c+3 downto 4*s.c), s.crc); + if s.c = 1 then + sin.c <= 0; + if s.a = 7 then + sin.a <= 0; + sin.s <= FrameCheck; + else + sin.a <= s.a + 1; + sin.s <= DataU; + end if; + else + sin.c <= s.c + 1; + end if; + + ----------------------------------------------------------------------- + -- Ethernet II - Frame Check. -- + ----------------------------------------------------------------------- + when FrameCheck => + E_TXD <= not s.crc(4*s.c+3 downto 4*s.c); + E_TX_EN <= '1'; + if s.c = 7 then + sin.c <= 0; + sin.s <= InterframeGap; + else + sin.c <= s.c + 1; + end if; + + ----------------------------------------------------------------------- + -- Ethernet II - Interframe Gap. -- + ----------------------------------------------------------------------- + when InterframeGap => + if s.c = 23 then + sin.c <= 0; + sin.s <= Idle; + else + sin.c <= s.c + 1; + end if; + end case; + end process; + + snd_reg : process(E_TX_CLK) + begin + if rising_edge(E_TX_CLK) then + s <= sin; + end if; + end process; +end rtl; \ No newline at end of file Index: etherlab/trunk/vhdl/etherlab.vhd =================================================================== --- etherlab/trunk/vhdl/etherlab.vhd (nonexistent) +++ etherlab/trunk/vhdl/etherlab.vhd (revision 2) @@ -0,0 +1,213 @@ +-------------------------------------------------------------------------------- +-- ETHERLAB - FPGA To C# To LABVIEW Bridge -- +-------------------------------------------------------------------------------- +-- Copyright (C)2012 Mathias H�rtnagl -- +-- -- +-- This program is free software: you can redistribute it and/or modify -- +-- it under the terms of the GNU General Public License as published by -- +-- the Free Software Foundation, either version 3 of the License, or -- +-- (at your option) any later version. -- +-- -- +-- This program is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- +-- GNU General Public License for more details. -- +-- -- +-- You should have received a copy of the GNU General Public License -- +-- along with this program. If not, see . -- +-------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.common.all; + +entity etherlab is + port( + clk : in std_logic; + + E_COL : in std_logic; -- Collision Detect. + E_CRS : in std_logic; -- Carrier Sense. + E_MDC : out std_logic; + E_MDIO : in std_logic; + E_RX_CLK : in std_logic; -- Receiver Clock. + E_RX_DV : in std_logic; -- Received Data Valid. + E_RXD : in std_logic_vector(3 downto 0); -- Received Nibble. + E_RX_ER : in std_logic; -- Received Data Error. + E_TX_CLK : in std_logic; -- Sender Clock. + E_TX_EN : out std_logic; -- Sender Enable. + E_TXD : out std_logic_vector(3 downto 0); -- Sent Data. + E_TX_ER : out std_logic; -- sent Data Error. + + SPI_MISO : in std_logic; -- Serial data in. + SPI_MOSI : out std_logic; -- Serial data out. + SPI_SCK : out std_logic; -- Serial Interface clock. + DAC_CS : out std_logic; -- D/A Converter chip sel. + DAC_CLR : out std_logic; -- D/A Converter reset. + + SF_OE : out std_logic; -- StrataFlash. + SF_CE : out std_logic; + SF_WE : out std_logic; + FPGA_INIT_B : out std_logic; + AD_CONV : out std_logic; -- A/D Converter chip sel. + SPI_SS_B : out std_logic; + AMP_CS : out std_logic; -- Pre-Amplifier chip sel. + + DI : in std_logic_vector(3 downto 0); -- 6-pin header J1. + DO : out std_logic_vector(3 downto 0); -- 6-pin header J2. + SW : in std_logic_vector(3 downto 0); -- SWITCHES. + BTN : in std_logic_vector(3 downto 0); -- BUTTONS. + LED : out std_logic_vector(7 downto 0) -- LEDs. + ); +end etherlab; + +architecture rtl of etherlab is + + component clock + port( + clkin_in : in std_logic; + rst_in : in std_logic; + clkin_ibufg_out : out std_logic; + clk0_out : out std_logic; + clk90_out : out std_logic + ); + end component; + + component mac_rcv is + port( + E_RX_CLK : in std_logic; -- Receiver Clock. + E_RX_DV : in std_logic; -- Received Data Valid. + E_RXD : in std_logic_vector(3 downto 0); -- Received Nibble. + el_chnl : out std_logic_vector(7 downto 0); -- EtherLab channels. + el_data : out data_t; -- EtherLab channel data. + el_dv : out std_logic; -- EtherLab data valid. + el_ack : in std_logic -- Packet reception ACK. + ); + end component; + + component mac_snd is + port( + E_TX_CLK : in std_logic; -- Sender Clock. + E_TX_EN : out std_logic; -- Sender Enable. + E_TXD : out std_logic_vector(3 downto 0); -- Sent Data. + E_TX_ER : out std_logic; -- Sent Data Error. + el_chnl : in std_logic_vector(7 downto 0); -- EtherLab channels. + el_data : in data_t; -- EtherLab data. + en : in std_logic -- User Start Send. + ); + end component; + + component io is + port( + clk : in std_logic; + clk90 : in std_logic; + -- EtherLab data received. + el_chnl : in std_logic_vector(7 downto 0); + el_data : in data_t; + el_dv : in std_logic; + el_ack : out std_logic; + -- EtherLab data to send. + el_snd_chnl : out std_logic_vector(7 downto 0); + el_snd_data : out data_t; + el_snd_en : out std_logic; + -- DAC/ADC Connections. + SPI_MISO : in std_logic; + SPI_MOSI : out std_logic; + SPI_SCK : out std_logic; + DAC_CS : out std_logic; + DAC_CLR : out std_logic; + AD_CONV : out std_logic; + AMP_CS : out std_logic; + -- Digital lines. + DI : in std_logic_vector(3 downto 0); + DO : out std_logic_vector(3 downto 0); + -- SWITCHES. + SW : in std_logic_vector(3 downto 0); + -- BUTTONS. + BTN : in std_logic_vector(3 downto 0); + -- LEDs. + LED : out std_logic_vector(7 downto 0) + ); + end component; + + signal el_chnl : std_logic_vector(7 downto 0); -- EtherLab channels. + signal el_data : data_t; -- EtherLab data. + signal el_dv : std_logic; -- Received data valid. + signal el_ack : std_logic; -- Packet reception ACK. + + signal el_snd_chnl : std_logic_vector(7 downto 0); -- EtherLab Send channels. + signal el_snd_data : data_t; -- EhterLab Send data. + signal el_snd_en : std_logic; -- Enable sending. + + signal clk90 : std_logic; -- Clock shiftet 90 degree. + signal clk0 : std_logic; +begin + + SF_OE <= '1'; -- Turn off Strata Flash. + SF_WE <= '1'; + SF_CE <= '1'; + FPGA_INIT_B <= '1'; -- Turn off Platform Flash. + SPI_SS_B <= '1'; -- Turn off Serial Flash. + + E_MDC <= '0'; + + inst_clock: clock port map( + clkin_in => clk, + rst_in => '0', + clkin_ibufg_out => open, + clk0_out => clk0, + clk90_out => clk90 + ); + + mac_receive : mac_rcv port map( + E_RX_CLK => E_RX_CLK, + E_RX_DV => E_RX_DV, + E_RXD => E_RXD, + el_chnl => el_chnl, + el_data => el_data, + el_dv => el_dv, + el_ack => el_ack + ); + + mac_send : mac_snd port map( + E_TX_CLK => E_TX_CLK, + E_TX_EN => E_TX_EN, + E_TXD => E_TXD, + E_TX_ER => E_TX_ER, + en => el_snd_en, + el_chnl => el_snd_chnl, + el_data => el_snd_data + ); + + ioio : io port map( + clk => clk0, + clk90 => clk90, + -- EtherLab data received. + el_chnl => el_chnl, + el_data => el_data, + el_dv => el_dv, + el_ack => el_ack, + -- EtherLab data to send. + el_snd_chnl => el_snd_chnl, + el_snd_data => el_snd_data, + el_snd_en => el_snd_en, + -- DAC/ADC Connections. + SPI_MISO => SPI_MISO, + SPI_MOSI => SPI_MOSI, + SPI_SCK => SPI_SCK, + DAC_CS => DAC_CS, + DAC_CLR => DAC_CLR, + AD_CONV => AD_CONV, + AMP_CS => AMP_CS, + -- Digital lines. + DI => DI, + DO => DO, + -- SWITCHES. + SW => SW, + -- BUTTONS. + BTN => BTN, + -- LEDs. + LED => LED + ); +end rtl; \ No newline at end of file Index: etherlab/trunk/vhdl/io.vhd =================================================================== --- etherlab/trunk/vhdl/io.vhd (nonexistent) +++ etherlab/trunk/vhdl/io.vhd (revision 2) @@ -0,0 +1,300 @@ +-------------------------------------------------------------------------------- +-- ETHERLAB - FPGA To C# To LABVIEW Bridge -- +-------------------------------------------------------------------------------- +-- REFERNCES -- +-- [1] LTC2604/LTC2614/LTC2624 Quad 16-Bit Rail-to-Rail DACs -- +-- [2] Xilinx UG230 -- +-- [3] LTC6912 Dual Programmable Gain Amplifiers -- +-- [4] LTC1407/LTC1407A Serial 12-Bit/14-Bit, 3Msps ADCs -- +-------------------------------------------------------------------------------- +-- Copyright (C)2012 Mathias H�rtnagl -- +-- -- +-- This program is free software: you can redistribute it and/or modify -- +-- it under the terms of the GNU General Public License as published by -- +-- the Free Software Foundation, either version 3 of the License, or -- +-- (at your option) any later version. -- +-- -- +-- This program is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- +-- GNU General Public License for more details. -- +-- -- +-- You should have received a copy of the GNU General Public License -- +-- along with this program. If not, see . -- +-------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.common.all; + +entity io is + port( + clk : in std_logic; + clk90 : in std_logic; + -- EtherLab data received. + el_chnl : in std_logic_vector(7 downto 0); + el_data : in data_t; + el_dv : in std_logic; + el_ack : out std_logic; + -- EtherLab data to send. + el_snd_chnl : out std_logic_vector(7 downto 0); + el_snd_data : out data_t; + el_snd_en : out std_logic; + -- DAC/ADC Connections. + SPI_MISO : in std_logic; + SPI_MOSI : out std_logic; + SPI_SCK : out std_logic; + DAC_CS : out std_logic; + DAC_CLR : out std_logic; + AD_CONV : out std_logic; + AMP_CS : out std_logic; + -- Digital lines. + DI : in std_logic_vector(3 downto 0); + DO : out std_logic_vector(3 downto 0); + -- SWITCHES. + SW : in std_logic_vector(3 downto 0); + -- BUTTONS. + BTN : in std_logic_vector(3 downto 0); + -- LEDs. + LED : out std_logic_vector(7 downto 0) + ); +end io; + +architecture rtl of io is + + ----------------------------------------------------------------------------- + -- SETTING: -- + -- + FREQ: Clock frequency. Usually 50 MHz. -- + -- + PULSE_WIDTH: Time between two EtherLab transmissions. -- + ----------------------------------------------------------------------------- + constant FREQ : natural := 50; -- [MHz] Frequency. + constant PULSE_WIDTH : natural := 100; -- [msec] Time between two sends. + + constant CYCLES_PER_MSEC : natural := 1000000/FREQ; + + type state_t is (Idle, Ready, AnalogOut, Send); + + type reg_t is record + s : state_t; + chnl : std_logic_vector(7 downto 0); -- Channel latch. + ao : std_logic_vector(23 downto 4); -- Analog out register. + do : std_logic_vector(3 downto 0); -- Digital out register. + led : std_logic_vector(7 downto 0); -- LED register. + c : natural range 0 to 23; + end record; + + type snd_state_t is (Idle, Pulse, Transmit); + + type snd_t is record + s : snd_state_t; + d : data_t; -- EtherLab data struct. + q : natural range 0 to CYCLES_PER_MSEC-1; -- Milliseconds counter. + p : natural range 0 to PULSE_WIDTH-1; -- Pulse counter. + end record; + + signal r, rin : reg_t := reg_t'(Idle, x"00", x"00000", x"0", x"00", 0); + signal s, sin : snd_t := snd_t'(Idle, (others => (others => '0')), 0,0); +begin + + snd : process(s, SW, BTN) + begin + + sin <= s; + + el_snd_en <= '0'; -- Turn off Ethernet packet sending. + + case s.s is + + when Idle => + if s.q = (CYCLES_PER_MSEC-1) then + sin.q <= 0; + if s.p = (PULSE_WIDTH-1) then + sin.p <= 0; + sin.s <= Pulse; + else + sin.p <= s.p + 1; + end if; + else + sin.q <= s.q + 1; + end if; + + when Pulse => + sin.d(CHANNEL_E) <= x"000" & DI; -- Sample digital input. + sin.d(CHANNEL_G) <= x"000" & BTN; -- Sample buttons. + sin.d(CHANNEL_H) <= x"000" & SW; -- Sample switches. + sin.s <= Transmit; + + when Transmit => + el_snd_en <= '1'; -- Send Ethernet packet. + sin.s <= Idle; + + end case; + end process; + + el_snd_chnl <= "11010000"; + el_snd_data <= s.d; + + + nsl : process(r, el_chnl, el_data, el_dv, clk90, SPI_MISO) + + -- DAC Commands and Addresses. + constant CMD_UP : std_logic_vector(3 downto 0) := "0011"; + constant ADR_OA : std_logic_vector(3 downto 0) := "0000"; + constant ADR_OB : std_logic_vector(3 downto 0) := "0001"; + constant ADR_OC : std_logic_vector(3 downto 0) := "0010"; + constant ADR_OD : std_logic_vector(3 downto 0) := "0011"; + begin + + rin <= r; + + SPI_MOSI <= r.ao(23); -- Send always the MSBit of the data register. + SPI_SCK <= '0'; -- Pull down SPI clock. + DAC_CLR <= '1'; -- Disable D/A Converter. + DAC_CS <= '1'; + AD_CONV <= '0'; -- Disable A/D Converter. + AMP_CS <= '1'; -- Disable Pre Amplifier. + + el_ack <= '0'; -- Ethernet receiver data ready ACK. + + case r.s is + when Idle => + if el_dv = '1' then + rin.chnl <= el_chnl; + rin.s <= Ready; + end if; + + -- IMPROVE: Merge Ready and AnalogOut states. + when Ready => + -------------------------------------------------------------------- + -- LED Control -- + -------------------------------------------------------------------- + if isSet(r.chnl, CHANNEL_H) then + rin.led <= el_data(CHANNEL_H)(7 downto 0); + rin.chnl(CHANNEL_H) <= '0'; + end if; + -------------------------------------------------------------------- + -- Digital Out Control -- + -------------------------------------------------------------------- + if isSet(r.chnl, CHANNEL_G) then + rin.do <= el_data(CHANNEL_G)(3 downto 0); + rin.chnl(CHANNEL_G) <= '0'; + end if; + -------------------------------------------------------------------- + -- Analog Out Control -- + -------------------------------------------------------------------- + if r.chnl(3 downto 0) /= x"0" then + rin.s <= AnalogOut; + else + rin.s <= Idle; + end if; + + ----------------------------------------------------------------------- + -- Analog Out Control -- + ----------------------------------------------------------------------- + -- Send data to DAC. Since all DACs are controlled via a singe serial + -- interface, the setting of new data follows the following precedence: + -- A > B > C > D. Thus if data is ready for analog output A, it will be + -- sent first. Next is analog output B, then C and finally D. + when AnalogOut => + if isSet(r.chnl, CHANNEL_A) then + rin.ao <= CMD_UP & ADR_OA & el_data(CHANNEL_A)(11 downto 0); + rin.chnl(CHANNEL_A) <= '0'; -- Clear channel flag. + rin.s <= Send; + elsif isSet(r.chnl, CHANNEL_B) then + rin.ao <= CMD_UP & ADR_OB & el_data(CHANNEL_B)(11 downto 0); + rin.chnl(CHANNEL_B) <= '0'; + rin.s <= Send; + elsif isSet(r.chnl, CHANNEL_C) then + rin.ao <= CMD_UP & ADR_OC & el_data(CHANNEL_C)(11 downto 0); + rin.chnl(CHANNEL_C) <= '0'; + rin.s <= Send; + elsif isSet(r.chnl, CHANNEL_D) then + rin.ao <= CMD_UP & ADR_OD & el_data(CHANNEL_D)(11 downto 0); + rin.chnl(CHANNEL_D) <= '0'; + rin.s <= Send; + else + rin.s <= Idle; -- All flags are cleared and DACs are updated. + end if; + + -- To send data at maximum speed, we send clk90, wich is the clock + -- signal phase shifted by 90 degree. This is necessary to meet the + -- timing constraints t1 and t2 defined in [1]. + when Send => + DAC_CS <= '0'; + SPI_SCK <= clk90; + rin.ao <= r.ao(22 downto 4) & '0'; + if r.c = 23 then + rin.c <= 0; + rin.s <= AnalogOut; + else + rin.c <= r.c + 1; + rin.s <= Send; + end if; + + ----------------------------------------------------------------------- + -- TODO: Analog In Control -- + ----------------------------------------------------------------------- + -- Pulse the ADC and capture the data from the last pulse. + -- when Pulse => + -- AD_CONV <= '1'; + -- SPI_SCK <= clk90; + -- rin.c <= 0; + -- rin.d(CHANNEL_E) <= x"000" & DI; -- Sample digital input. + -- rin.d(CHANNEL_G) <= x"000" & BTN; -- Sample buttons. + -- rin.d(CHANNEL_H) <= x"000" & SW; -- Sample switches. + -- rin.s <= Transmit; --Wait0; + + -- when Wait0 => + -- SPI_SCK <= clk90; + -- if r.c = 1 then + -- rin.c <= 0; + -- rin.s <= Receive0; + -- else + -- rin.c <= r.c + 1; + -- end if; + + -- when Receive0 => + -- SPI_SCK <= clk90; + -- rin.d(CHANNEL_A) <= r.d(CHANNEL_A)(15 downto 1) & SPI_MISO; + -- if r.c = 13 then + -- rin.c <= 0; + -- rin.s <= Wait1; + -- else + -- rin.c <= r.c + 1; + -- end if; + + -- when Wait1 => + -- SPI_SCK <= clk90; + -- if r.c = 1 then + -- rin.c <= 0; + -- rin.s <= Receive1; + -- else + -- rin.c <= r.c + 1; + -- end if; + + -- when Receive1 => + -- SPI_SCK <= clk90; + -- rin.d(CHANNEL_B) <= r.d(CHANNEL_B)(15 downto 1) & SPI_MISO; + -- if r.c = 13 then + -- rin.c <= 0; + -- rin.s <= Transmit; + -- else + -- rin.c <= r.c + 1; + -- end if; + + end case; + end process; + + DO <= r.do; + LED <= r.led; + + reg : process(clk) + begin + if rising_edge(clk) then + r <= rin; + s <= sin; + end if; + end process; +end rtl; \ No newline at end of file Index: etherlab/trunk/vhdl/common.vhd =================================================================== --- etherlab/trunk/vhdl/common.vhd (nonexistent) +++ etherlab/trunk/vhdl/common.vhd (revision 2) @@ -0,0 +1,50 @@ +-------------------------------------------------------------------------------- +-- EtherLab Common Package -- +-------------------------------------------------------------------------------- +-- Copyright (C)2012 Mathias H�rtnagl -- +-- -- +-- This program is free software: you can redistribute it and/or modify -- +-- it under the terms of the GNU General Public License as published by -- +-- the Free Software Foundation, either version 3 of the License, or -- +-- (at your option) any later version. -- +-- -- +-- This program is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- +-- GNU General Public License for more details. -- +-- -- +-- You should have received a copy of the GNU General Public License -- +-- along with this program. If not, see . -- +-------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package common is + + -- Array for channel data. + type data_t is array(7 downto 0) of std_logic_vector(15 downto 0); + + -- Channel constants. + constant CHANNEL_A : natural range 0 to 7 := 0; + constant CHANNEL_B : natural range 0 to 7 := 1; + constant CHANNEL_C : natural range 0 to 7 := 2; + constant CHANNEL_D : natural range 0 to 7 := 3; + constant CHANNEL_E : natural range 0 to 7 := 4; + constant CHANNEL_F : natural range 0 to 7 := 5; + constant CHANNEL_G : natural range 0 to 7 := 6; + constant CHANNEL_H : natural range 0 to 7 := 7; + + -- Check, if channel flag is set. + function isSet(el_chnl : std_logic_vector; channel : natural) return boolean; +end common; + +package body common is + + -- Check, if channel flag is set. + function isSet(el_chnl : std_logic_vector; channel : natural) + return boolean is + begin + return (el_chnl(channel) = '1'); + end; +end common; \ No newline at end of file Index: etherlab/trunk/vhdl/mac_rcv.vhd =================================================================== --- etherlab/trunk/vhdl/mac_rcv.vhd (nonexistent) +++ etherlab/trunk/vhdl/mac_rcv.vhd (revision 2) @@ -0,0 +1,199 @@ +-------------------------------------------------------------------------------- +-- ETHERLAB - FPGA To C# To LABVIEW Bridge -- +-------------------------------------------------------------------------------- +-- REFERENCES -- +-- [1] http://tools.ietf.org/html/rfc2460 -- +-- [2] https://en.wikipedia.org/wiki/Ethernet_frame -- +-- [5] http://outputlogic.com/my-stuff/circuit-cellar-january-2010-crc.pdf -- +-- [6] OPB Ethernet Lite Media Access Controller (v1.01b) -- +-- [7] LAN83C185 - 10/100 Ethernet PHY -- +-- [8] Xilinx UG230 -- +-------------------------------------------------------------------------------- +-- Copyright (C)2012 Mathias H�rtnagl -- +-- -- +-- This program is free software: you can redistribute it and/or modify -- +-- it under the terms of the GNU General Public License as published by -- +-- the Free Software Foundation, either version 3 of the License, or -- +-- (at your option) any later version. -- +-- -- +-- This program is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- +-- GNU General Public License for more details. -- +-- -- +-- You should have received a copy of the GNU General Public License -- +-- along with this program. If not, see . -- +-------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.common.all; + +entity mac_rcv is + port( + E_RX_CLK : in std_logic; -- Receiver Clock. + E_RX_DV : in std_logic; -- Received Data Valid. + E_RXD : in std_logic_vector(3 downto 0); -- Received Nibble. + el_chnl : out std_logic_vector(7 downto 0); -- EtherLab channels. + el_data : out data_t; -- EtherLab channel data. + el_dv : out std_logic; -- EtherLab data valid. + el_ack : in std_logic -- Packet reception ACK. + ); +end mac_rcv; + +architecture rtl of mac_rcv is + + type state_t is ( + Preamble, StartOfFrame, -- 7 Bytes 0x55, 1 Byte 0x5d. + MACS, -- 12 Byte MAC addresses. + EtherTypeCheck, -- Next Protocol EtherLab? + Version, -- EtherLab - Version. + Channel, -- EtherLab - Channel. + DataU, DataL, -- EtherLab - Channel data. + Notify -- Inform other hardware components. + ); + + type rcv_t is record + s : state_t; + chnl : std_logic_vector(7 downto 0); -- EtherLab channel field. + d : data_t; -- Channel data. + c : natural range 0 to 23; + a : natural range 0 to 7; + end record; + + signal r, rin : rcv_t + := rcv_t'(Preamble, x"00", (others => (others => '0')), 0, 0); +begin + + rcv_nsl : process(r, E_RX_DV, E_RXD, el_ack) + begin + + rin <= r; + el_dv <= '0'; + + if E_RX_DV = '1' then + case r.s is + + -------------------------------------------------------------------- + -- Ethernet II - Preamble and Start Of Frame. -- + -------------------------------------------------------------------- + when Preamble => + if E_RXD = x"5" then + if r.c = 14 then + rin.c <= 0; + rin.s <= StartOfFrame; + else + rin.c <= r.c + 1; + end if; + else + rin.c <= 0; + end if; + + when StartOfFrame => + if E_RXD = x"d" then + rin.s <= MACS; + else + rin.s <= Preamble; + end if; + + -------------------------------------------------------------------- + -- Ethernet II - 12 Byte MAC addresses. -- + -------------------------------------------------------------------- + when MACS => + if r.c = 23 then + rin.c <= 0; + rin.s <= EtherTypeCheck; + else + rin.c <= r.c + 1; + end if; + + -------------------------------------------------------------------- + -- Ethernet II - Next Layer EtherLab? -- + -------------------------------------------------------------------- + when EtherTypeCheck => + if E_RXD = x"0" then + if r.c = 3 then + rin.c <= 0; + rin.s <= Version; + else + rin.c <= r.c + 1; + end if; + else + rin.c <= 0; + rin.s <= Preamble; + end if; + + -------------------------------------------------------------------- + -- EtherLab - Version -- + -------------------------------------------------------------------- + when Version => + if r.c = 1 then + rin.c <= 0; + rin.s <= Channel; + else + rin.c <= r.c + 1; + end if; + + -------------------------------------------------------------------- + -- EtherLab - Channel Flags. -- + -------------------------------------------------------------------- + when Channel => + rin.chnl(7 downto 0) <= E_RXD & r.chnl(7 downto 4); + if r.c = 1 then + rin.c <= 0; + rin.a <= 0; + rin.s <= DataU; + else + rin.c <= r.c + 1; + end if; + + -------------------------------------------------------------------- + -- EtherLab - Data. 8 channels � 16 bit. -- + -------------------------------------------------------------------- + when DataU => + rin.d(r.a)(15 downto 8) <= E_RXD & r.d(r.a)(15 downto 12); + if r.c = 1 then + rin.c <= 0; + rin.s <= DataL; + else + rin.c <= r.c + 1; + end if; + + when DataL => + rin.d(r.a)(7 downto 0) <= E_RXD & r.d(r.a)(7 downto 4); + if r.c = 1 then + rin.c <= 0; + if r.a = 7 then + rin.a <= 0; + rin.s <= Notify; + else + rin.a <= r.a + 1; + rin.s <= DataU; + end if; + else + rin.c <= r.c + 1; + end if; + + -------------------------------------------------------------------- + -- Notification -- + -------------------------------------------------------------------- + when Notify => + el_dv <= '1'; + rin.s <= Preamble; + + end case; + end if; + end process; + + snd_reg : process(E_RX_CLK) + begin + if rising_edge(E_RX_CLK) then + r <= rin; + end if; + end process; + + el_chnl <= r.chnl; + el_data <= r.d; +end rtl; \ No newline at end of file Index: etherlab/trunk/lab/src/EtherLab.lvproj =================================================================== --- etherlab/trunk/lab/src/EtherLab.lvproj (nonexistent) +++ etherlab/trunk/lab/src/EtherLab.lvproj (revision 2) @@ -0,0 +1,19 @@ + + + + true + true + false + 0 + Mein Computer/VI-Server + Mein Computer/VI-Server + true + true + false + + + + + + + Index: etherlab/trunk/lab/src/Receive/Read_Bool.vi =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: etherlab/trunk/lab/src/Receive/Read_Bool.vi =================================================================== --- etherlab/trunk/lab/src/Receive/Read_Bool.vi (nonexistent) +++ etherlab/trunk/lab/src/Receive/Read_Bool.vi (revision 2)

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etherlab/trunk/lab/src/EtherLab.mnu Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: etherlab/trunk/lab/src/EtherLab.lvlps =================================================================== --- etherlab/trunk/lab/src/EtherLab.lvlps (nonexistent) +++ etherlab/trunk/lab/src/EtherLab.lvlps (revision 2) @@ -0,0 +1,3 @@ +[Projektfenster_Daten] +ProjectExplorer.ClassicPosition[String] = "249,228,649,749" + Index: etherlab/trunk/lab/src/EtherLab.aliases =================================================================== --- etherlab/trunk/lab/src/EtherLab.aliases (nonexistent) +++ etherlab/trunk/lab/src/EtherLab.aliases (revision 2) @@ -0,0 +1,3 @@ +[Mein Computer] +Mein Computer = "192.168.178.30" + Index: etherlab/trunk/lab/src/Send/Update.vi =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: etherlab/trunk/lab/src/Send/Update.vi =================================================================== --- etherlab/trunk/lab/src/Send/Update.vi (nonexistent) +++ etherlab/trunk/lab/src/Send/Update.vi (revision 2)

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etherlab/trunk/lab/src/Send/Update_Short.vi Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: etherlab/trunk/lab/src/EtherLab.lvlib =================================================================== --- etherlab/trunk/lab/src/EtherLab.lvlib (nonexistent) +++ etherlab/trunk/lab/src/EtherLab.lvlib (revision 2) @@ -0,0 +1,30 @@ + + + EtherLab.mnu + + #1#!!!!!!!)!"1!&!!!-!%!!!@````]!!!!"!!%!!!(]!!!*Q(C=\>8"<2MR%!813:!!O;K$1#V-#WJ",5Q,OPKI&K9&N;!7JA7VI";=JQVBZ"4F%#-ZG/O26X_ZZ$/87%>M\6P%FXB^VL\_NHV=@X<^39O0^N(_<8NZOEH@@=^_CM?,3)VK63LD->8LS%=_]J'0@/1N<XH,7^\SFJ?]Z#5P?=F,HP+5JTTF+5`Z>MB$(P+1)YX*RU2DU$(![)Q3YW.YBG>YBM@8'*\B':\B'2Z>9HC':XC':XD=&M-T0--T0-.DK%USWS(H'2\$2`-U4`-U4`/9-JKH!>JE<?!W#%;UC_WE?:KH?:R']T20]T20]\A=T>-]T>-]T?/7<66[UTQ//9^BIHC+JXC+JXA-(=640-640-6DOCC?YCG)-G%:(#(+4;6$_6)]R?.8&%`R&%`R&)^,WR/K<75?GM=BZUG?Z%G?Z%E?1U4S*%`S*%`S'$;3*XG3*XG3RV320-G40!G3*D6^J-(3D;F4#J,(T\:<=HN+P5FS/S,7ZIWV+7.NNFC<+.<GC0819TX-7!]JVO,(7N29CR6L%7,^=<(1M4#R*IFV][.DX(X?V&6>V&G>V&%>V&\N(L@_Z9\X_TVONVN=L^?Y8#ZR0J`D>$L&]8C-Q_%1_`U_>LP>WWPAO_0NB@$TP@4C`%`KH@[8`A@PRPA=PYZLD8Y![_ML^!!!!!! + EtherLab + 1.0.0.0 + + 1 + + + + + + + + 1 + + + + + + 1 + + + + + + + Index: etherlab/trunk/lab/src/EtherSocket.vi =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: etherlab/trunk/lab/src/EtherSocket.vi =================================================================== --- etherlab/trunk/lab/src/EtherSocket.vi (nonexistent) +++ etherlab/trunk/lab/src/EtherSocket.vi (revision 2)

etherlab/trunk/lab/src/EtherSocket.vi Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: etherlab/trunk/lab/examples/UDP Sender.vi =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: etherlab/trunk/lab/examples/UDP Sender.vi =================================================================== --- etherlab/trunk/lab/examples/UDP Sender.vi (nonexistent) +++ etherlab/trunk/lab/examples/UDP Sender.vi (revision 2)

etherlab/trunk/lab/examples/UDP Sender.vi Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property

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