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/trunk/rtl/vhdl/testbench1.vhd
0,0 → 1,144
--===========================================================================--
--
-- CPU11 Microprocessor Test Bench 1
-- Print out "Hello World" on the (non existant) Uart
--
--
-- John Kent 21st October 2002
--
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
 
entity my_testbench is
end my_testbench;
 
-------------------------------------------------------------------------------
-- Architecture for memio Controller Unit
-------------------------------------------------------------------------------
architecture behavior of my_testbench is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal uart_irq : Std_Logic;
signal timer_irq : std_logic;
 
-- CPU Interface signals
signal SysClk : Std_Logic;
signal cpu_reset : Std_Logic;
signal cpu_rw : Std_Logic;
signal cpu_vma : Std_Logic;
signal cpu_addr : Std_Logic_Vector(15 downto 0);
signal cpu_data_in : Std_Logic_Vector(7 downto 0);
signal cpu_data_out: Std_Logic_Vector(7 downto 0);
signal cpu_alu : Std_Logic_Vector(15 downto 0);
signal cpu_cc : Std_Logic_Vector(7 downto 0);
 
constant width : integer := 8;
constant memsize : integer := 64;
 
type rom_array is array(0 to memsize-1) of std_logic_vector(width-1 downto 0);
 
constant rom_data : rom_array :=
(
"11001110", "11111111", "11101000", -- E000 - CE E028 RESET LDX #MSG
"10000110", "00010001", -- E003 - 86 11 LDAA #$11
"10110111", "10000000", "00000100", -- E005 - B7 8004 STAA UARTCR
"10110110", "10000000", "00000100", -- E008 - B6 8004 POLL1 LDAA UARTCR
"10000101", "00000010", -- E00B - 85 02 BITA #TXBE
-- "00100111", "11111001", -- E00D - 27 F9 BEQ POLL1
"00100110", "11111001", -- E00D - 26 F9 BNE POLL1
"10100110", "00000000", -- E00F - A6 00 LDAA 0,X
"00100111", "00000110", -- E011 - 27 06 BEQ POLL2
"00001000", -- E013 - 08 INX
"10110111", "10000000", "00000101", -- E014 - B7 8005 STA UARTDR
"00100110", "11101111", -- E017 - 26 EF BNE POLL1
"00001000", "10000000", "00000100", -- E019 - B6 8004 POLL2 LDAA UARTCR
"10000101", "00000001", -- E01C - 85 01 BITA #RXBF
"00100111", "11111001", -- E01E - 27 F9 BEQ POLL2
-- "00100110", "11111001", -- E01E - 26 F9 BEQ POLL2
"10110110", "10000000", "00000101", -- E020 - B6 8005 LDAA UARTDR
"00100000", "11100000", "00000000", -- E023 - 7E E000 JMP RESET
"00000000", "00000000", -- E026 - 00 00 fcb $00,$00
"01001000", "01100101", "01101100", -- E028 - 48 65 6c MSG FCC "Hel"
"01101100", "01101111", "00100000", -- E02B - 6c 6f 20 FCC "lo "
"01010111", "01101111", "01110010", -- E02E - 57 6f 72 FCC "Wor"
"01101100", "01100100", -- E031 - 6c 64 FCC "ld"
"00001010", "00001101", "00000000", -- E033 - 0a 0d 00 FCB LF,CR,NULL
"00000000", "00000000", -- E036 - 00 00 fcb null,null
"11100000", "00000000", -- E038 - E0 00 fdb $E000 ; Timer irq
"11100000", "00000000", -- E03A - E0 00 fdb $E000 ; Ext IRQ
"11100000", "00000000", -- E03C - E0 00 fcb $E000 ; SWI
"11100000", "00000000" -- E03E - E0 00 fdb $E000 ; Reset
);
 
component cpu11
port (
clk: in std_logic;
rst: in std_logic;
rw: out std_logic; -- Asynchronous memory interface
vma: out std_logic;
address: out std_logic_vector(15 downto 0);
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
irq: in std_logic;
xirq: in std_logic;
test_alu: out std_logic_vector(15 downto 0);
test_cc: out std_logic_vector(7 downto 0)
);
end component;
 
 
begin
cpu : cpu11 port map (
clk => SysClk,
rst => cpu_reset,
rw => cpu_rw,
vma => cpu_vma,
address => cpu_addr(15 downto 0),
data_in => cpu_data_in,
data_out => cpu_data_out,
irq => uart_irq,
xirq => timer_irq,
test_alu => cpu_alu,
test_cc => cpu_cc
);
 
-- *** Test Bench - User Defined Section ***
tb : PROCESS
variable count : integer;
BEGIN
 
cpu_reset <= '0';
SysClk <= '0';
uart_irq <= '0';
timer_irq <= '0';
 
for count in 0 to 256 loop
SysClk <= '0';
if count = 0 then
cpu_reset <= '1';
elsif count = 1 then
cpu_reset <= '0';
end if;
wait for 100 ns;
SysClk <= '1';
wait for 100 ns;
end loop;
 
wait; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***
 
 
rom : PROCESS( cpu_addr )
begin
cpu_data_in <= rom_data(conv_integer(cpu_addr(5 downto 0)));
end process;
 
end behavior; --===================== End of architecture =======================--
 
/trunk/rtl/vhdl/timer.vhd
0,0 → 1,254
--===========================================================================--
--
-- S Y N T H E Z I A B L E timer - simple timer/counter unit
--
-- www.OpenCores.Org - September 2003
-- This core adheres to the GNU public license
--
-- File name : timer.vhd
--
-- Entity name : timer
--
-- Purpose : Simple 9 bit timer
--
-- Dependencies : ieee.std_logic_1164
-- ieee.std_logic_unsigned
--
-- Uses : Nothing
--
-- Author : John Kent - dilbert57@opencores.org
--
-------------------------------------------------------------------------------
-- Revision list
--
-- Version 0.1 - 6 Sept 2002 - John Kent
-- converted to a single timer
-- made syncronous with system clock
--
-- Version 1.0 - 7 September 2003
-- Released to open cores
--
-------------------------------------------------------------------------------
--
-- Register Addressing
-- addr=0 rw=1 down count
-- addr=0 rw=0 preset count
-- addr=1 rw=1 status
-- addr=0 rw=0 control
--
-- Control register
-- b0 = counter enable
-- b1 = mode (0 = counter, 1 = timer)
-- b7 = interrupt enable
--
-- Status register
-- b6 = timer output
-- b7 = interrupt flag
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity timer is
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
irq : out std_logic;
timer_in : in std_logic;
timer_out : out std_logic
);
end;
 
architecture timer_arch of timer is
signal timer_ctrl : std_logic_vector(7 downto 0);
signal timer_stat : std_logic_vector(7 downto 0);
signal timer_reg : std_logic_vector(7 downto 0);
signal timer_count : std_logic_vector(7 downto 0);
signal timer_int : std_logic; -- Timer interrupt
signal timer_term : std_logic; -- Timer terminal count
signal timer_tog : std_logic; -- Timer output
--
-- control/status register bits
--
constant T_enab : integer := 0; -- 0=disable, 1=enabled
constant T_mode : integer := 1; -- 0=counter, 1=timer
constant T_out : integer := 6; -- 0=disabled, 1=enabled
constant T_irq : integer := 7; -- 0=disabled, 1-enabled
 
begin
 
--------------------------------
--
-- write control registers
-- doesn't do anything yet
--
--------------------------------
timer_write : process( clk, rst, cs, rw, addr, data_in,
timer_reg, timer_ctrl, timer_count )
begin
if clk'event and clk = '0' then
if rst = '1' then
timer_reg <= "00000000";
timer_ctrl <= "00000000";
elsif cs = '1' and rw = '0' then
if addr='0' then
timer_reg <= data_in;
timer_ctrl <= timer_ctrl;
timer_term <= '0';
else
timer_reg <= timer_reg;
timer_ctrl <= data_in;
timer_term <= timer_term;
end if;
else
timer_ctrl <= timer_ctrl;
timer_reg <= timer_reg;
if (timer_ctrl(T_enab) = '1') then
if (timer_count = "00000000" ) then
timer_term <= '1';
elsif timer_ctrl(T_mode) = '0' then
timer_term <= '0'; -- counter mode, reset on non zero
else
timer_term <= timer_term; -- timer mode, keep as is
end if;
else
timer_term <= timer_term;
end if;
end if;
end if;
end process;
 
--
-- timer data output mux
--
timer_read : process( addr, timer_count, timer_stat )
begin
if addr='0' then
data_out <= timer_count;
else
data_out <= timer_stat;
end if;
end process;
 
--------------------------------
--
-- counters
--
--------------------------------
 
my_counter: process( clk, rst, timer_ctrl, timer_count, timer_in )
variable timer_tmp : std_logic;
begin
if clk'event and clk='0' then
if rst = '1' then
timer_count <= "00000000";
timer_tmp := '0';
else
if timer_ctrl( T_enab ) = '1' then
if timer_in = '0' and timer_tmp = '1' then
timer_tmp := '0';
if timer_count = "00000000" then
timer_count <= timer_reg;
else
timer_count <= timer_count - 1;
end if;
elsif timer_in = '1' and timer_tmp = '0' then
timer_tmp := '1';
timer_count <= timer_count;
else
timer_tmp := timer_tmp;
timer_count <= timer_count;
end if;
else
timer_tmp := timer_tmp;
timer_count <= timer_count;
end if; -- timer_ctrl
end if; -- rst
end if; -- clk
end process;
 
--
-- read timer strobe to reset interrupts
--
timer_interrupt : process( Clk, rst, cs, rw, addr,
timer_term, timer_int, timer_count, timer_ctrl )
begin
if clk'event and clk = '0' then
if rst = '1' then
timer_int <= '0';
elsif cs = '1' and rw = '1' then
if addr = '0' then
timer_int <= '0'; -- reset interrupt on read count
else
timer_int <= timer_int;
end if;
else
if timer_term = '1' then
timer_int <= '1';
else
timer_int <= timer_int;
end if;
end if;
end if;
 
if timer_ctrl( T_irq ) = '1' then
irq <= timer_int;
else
irq <= '0';
end if;
end process;
 
--
-- timer status register
--
timer_status : process( timer_ctrl, timer_int, timer_tog )
begin
timer_stat(5 downto 0) <= timer_ctrl(5 downto 0);
timer_stat(T_out) <= timer_tog;
timer_stat(T_irq) <= timer_int;
end process;
 
--
-- timer output
--
timer_output : process( Clk, rst, timer_term, timer_ctrl, timer_tog )
variable timer_tmp : std_logic; -- tracks change in terminal count
begin
if clk'event and clk='0' then
if rst = '1' then
timer_tog <= '0';
timer_tmp := '0';
elsif timer_ctrl(T_mode) = '0' then -- free running ?
if (timer_term = '1') and (timer_tmp = '0') then
timer_tmp := '1';
timer_tog <= not timer_tog;
elsif (timer_term = '0') and (timer_tmp = '1') then
timer_tmp := '0';
timer_tog <= timer_tog;
else
timer_tmp := timer_tmp;
timer_tog <= timer_tog;
end if;
else -- one shot timer mode, follow terminal count
if (timer_term = '1') and (timer_tmp = '0') then
timer_tmp := '1';
timer_tog <= '1';
elsif (timer_term = '0') and (timer_tmp = '1') then
timer_tmp := '0';
timer_tog <= '0';
else
timer_tmp := timer_tmp;
timer_tog <= timer_tog;
end if;
end if;
end if;
timer_out <= timer_tog and timer_ctrl(T_out);
end process;
 
end timer_arch;
/trunk/rtl/vhdl/testbench2.vhd
0,0 → 1,139
--===========================================================================--
--
-- CPU11 Microprocessor Test Bench 2
--
-- Subroutine test code.
--
-- John Kent 21st October 2002
--
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
 
entity my_testbench is
end my_testbench;
 
-------------------------------------------------------------------------------
-- Architecture for memio Controller Unit
-------------------------------------------------------------------------------
architecture behavior of my_testbench is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal uart_irq : Std_Logic;
signal timer_irq : std_logic;
 
-- Sequencer Interface signals
signal SysClk : Std_Logic;
signal cpu_reset : Std_Logic;
signal cpu_rw : std_logic;
signal cpu_vma : std_logic;
signal cpu_addr : Std_Logic_Vector(15 downto 0);
signal cpu_data_in : Std_Logic_Vector(7 downto 0);
signal cpu_data_out: Std_Logic_Vector(7 downto 0);
 
constant width : integer := 8;
constant memsize : integer := 64;
 
type rom_array is array(0 to memsize-1) of std_logic_vector(width-1 downto 0);
 
constant rom_data : rom_array :=
(
"10001110", "11111111", "11011101", -- FFC0 - 8E FFDD RESET LDS #$FFDD
"11001110", "00010010", "00110100", -- FFC3 - CE 1234 LDX #$1234
"10001101", "00000100", -- FFC6 - 8D 04 BSR SAVGET
"00100111", "11110110", -- FFC8 - 27 F6 REENT BEQ RESET
"00100000", "11111110", -- FFCA - 20 FF BRA *
"11111111", "11111111", "11110000", -- FFCC - FF FFF0 SAVGET STX $FFF0
"11111110", "11111111", "11011001", -- FFCF - FE FFD9 LDX $FFD9
"00110111", -- FFD2 - 37 PSHB
"11100110", "00000001", -- FFD3 - E6 01 LDAB 1,X
"11100001", "00000011", -- FFD5 - E1 03 CMPB 3,X
"00110011", -- FFD7 - 33 PULB
"00111001", -- FFD8 - 39 RTS
"11111111", "11100000", -- FFD9 - FF E0 FDB $FFE0
"01010101", -- FFDB - 55 FCB $55
"11111111", "11001000", -- FFDC - FFC8 FDB REENT
"00100000", "11100000", -- FFDE - 20 E0 BRA RESET
"00000000", "00000000", -- FFE0 - 00 00 fcb $00,$00
"00000000", "00000000", -- FFE2 - 00 00 fcb $00,$00
"00000000", "00000000", -- FFE4 - 00 00 fcb $00,$00
"00000000", "00000000", -- FFE6 - 00 00 fcb $00,$00
"01001000", "01100101", "01101100", -- FFE8 - 48 65 6c MSG FCC "Hel"
"01101100", "01101111", "00100000", -- FFEB - 6c 6f 20 FCC "lo "
"01010111", "01101111", "01110010", -- FFEE - 57 6f 72 FCC "Wor"
"01101100", "01100100", -- FFF1 - 6c 64 FCC "ld"
"00001010", "00001101", "00000000", -- FFF3 - 0a 0d 00 FCB LF,CR,NULL
"00000000", "00000000", -- FFF6 - 00 00 fcb null,null
"11111111", "11000000", -- FFF8 - FF C0 fdb $FFC0 ; Timer irq
"11111111", "11000000", -- FFFA - FF C0 fdb $FFC0 ; Ext IRQ
"11111111", "11000000", -- FFFC - FF C0 fcb $FFC0 ; SWI
"11111111", "11000000" -- FFFE - FF C0 fdb $FFC0 ; Reset
);
 
component cpu11
port (
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
address: out std_logic_vector(15 downto 0);
vma: out std_logic;
rw: out std_logic; -- Asynchronous memory interface
rst: in std_logic;
clk: in std_logic;
irq: in std_logic;
xirq: in std_logic
);
end component;
 
 
begin
cpu : cpu11 port map (
data_in => cpu_data_in,
data_out => cpu_data_out,
address => cpu_addr(15 downto 0),
vma => cpu_vma,
rw => cpu_rw,
rst => cpu_reset,
clk => SysClk,
irq => uart_irq,
xirq => timer_irq
);
 
-- *** Test Bench - User Defined Section ***
tb : PROCESS
variable count : integer;
BEGIN
 
cpu_reset <= '0';
SysClk <= '0';
uart_irq <= '0';
timer_irq <= '0';
 
for count in 0 to 256 loop
SysClk <= '0';
if count = 0 then
cpu_reset <= '1';
elsif count = 1 then
cpu_reset <= '0';
end if;
wait for 100 ns;
SysClk <= '1';
wait for 100 ns;
end loop;
 
wait; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***
 
 
rom : PROCESS( cpu_addr )
begin
cpu_data_in <= rom_data(conv_integer(cpu_addr(5 downto 0)));
end process;
 
end behavior; --===================== End of architecture =======================--
 
/trunk/rtl/vhdl/system11.ucf
0,0 → 1,283
#### UCF file created by Project Navigator
#### UCF file created by Project Navigator
#
NET "reset_n" LOC = "p57" ;
NET "sysclk" LOC = "p77" ;
#
# For B5-Compact-Flash:
# Connector A
#
#NET "pin2" LOC = "P3" ; #J1-2
#NET "pin3" LOC = "P4" ; #J1-3
#NET "cf_intrq" LOC = "P5" ; #J1-4
NET "cf_wr_n" LOC = "P6" ; #J1-5
NET "cf_rd_n" LOC = "P7" ; #J1-6
NET "cf_cs1_n" LOC = "P8" ; #J1-7
NET "cf_d<15>" LOC = "P9" ; #J1-8
NET "cf_d<14>" LOC = "P10" ; #J1-9
NET "cf_d<13>" LOC = "P11" ; #J1-10
NET "cf_d<12>" LOC = "P15" ; #J1-11
NET "cf_d<11>" LOC = "P16" ; #J1-12
#NET "cf_present" LOC = "P17" ; #J1-13
NET "cf_d<3>" LOC = "P18" ; #J1-14
NET "cf_d<4>" LOC = "P20" ; #J1-15
NET "cf_d<5>" LOC = "P21" ; #J1-16
NET "cf_d<6>" LOC = "P22" ; #J1-17
NET "cf_d<7>" LOC = "P23" ; #J1-18
NET "cf_cs0_n" LOC = "P24" ; #J1-19
#
# For B5-Compact-Flash:
# Connector B
#
NET "cf_a<2>" LOC = "P33" ; #J2-6
NET "cf_a<1>" LOC = "P34" ; #J2-7
NET "cf_a<0>" LOC = "P35" ; #J2-8
NET "cf_d<0>" LOC = "P36" ; #J2-9
NET "cf_d<1>" LOC = "P40" ; #J2-10
NET "cf_d<2>" LOC = "P41" ; #J2-11
NET "cf_cs16_n" LOC = "P42" ; #J2-12
NET "cf_d<10>" LOC = "P43" ; #J2-13
NET "cf_d<9>" LOC = "P44" ; #J2-14
NET "cf_d<8>" LOC = "P45" ; #J2-15
#NET "cf_pdiag" LOC = "P46" ; #J2-16
#NET "cf_dase" LOC = "P47" ; #J2-17
#NET "cf_iordy" LOC = "P48" ; #J2-18
NET "cf_rst_n" LOC = "P49" ; #J2-19
#
# I/O Port
# Connector C
#
NET "porta<0>" LOC = "p55" ; #pin 3
NET "porta<1>" LOC = "p56" ; #pin 4
NET "porta<2>" LOC = "p58" ; #pin 5
NET "porta<3>" LOC = "p59" ; #pin 6
NET "porta<4>" LOC = "p60" ; #pin 7
NET "porta<5>" LOC = "p61" ; #pin 8
NET "porta<6>" LOC = "p62" ; #pin 8
NET "porta<7>" LOC = "p63" ; #pin 10
NET "portb<0>" LOC = "p64" ; #pin 11
NET "portb<1>" LOC = "p68" ; #pin 12
NET "portb<2>" LOC = "p69" ; #pin 13
NET "portb<3>" LOC = "p70" ; #pin 14
NET "portb<4>" LOC = "p71" ; #pin 15
NET "portb<5>" LOC = "p73" ; #pin 16
NET "portb<6>" LOC = "p74" ; #pin 17
NET "portb<7>" LOC = "p75" ; #pin 18
NET "timer_out" LOC = "p81" ; #pin 19
#
# For B3-FPGA-CPU-IO
# Connector D
#
#NET "aux_clock" LOC = "p80" ; #pin 2
#NET "buzzer" LOC = "p82" ; #pin 3
NET "led" LOC = "p82" ; #pin 3
#NET "mouse_clock" LOC = "p83" ; #pin 4
#NET "mouse_data" LOC = "p84" ; #pin 5
NET "cts_n" LOC = "p86" ; #pin 6
NET "rts_n" LOC = "p87" ; #pin 7
NET "txbit" LOC = "p88" ; #pin 8
NET "rxbit" LOC = "p89" ; #pin 9
#NET "kb_clock" LOC = "p93" ; #pin 10
#NET "kb_data" LOC = "p94" ; #pin 11
#NET "v_drive" LOC = "p95" ; #pin 12
#NET "h_drive" LOC = "p96" ; #pin 13
#NET "blue_lo" LOC = "p97" ; #pin 14
#NET "blue_hi" LOC = "p98" ; #pin 15
#NET "green_lo" LOC = "p99" ; #pin 16
#NET "green_hi" LOC = "p100"; #pin 17
#NET "red_lo" LOC = "p101"; #pin 18
#NET "red_hi" LOC = "p102"; #pin 19
#
# For modified B3-SRAM
# Connector E
#
NET "ram_addr<0>" LOC = "p108"; #J1.2
NET "ram_addr<1>" LOC = "p109"; #J1.3
NET "ram_addr<2>" LOC = "p110"; #J1.4
NET "ram_addr<3>" LOC = "p111"; #J1.5
NET "ram_addr<4>" LOC = "p112"; #J1.6
NET "ram_addr<5>" LOC = "p113"; #J1.7
NET "ram_addr<6>" LOC = "p114"; #J1.8
NET "ram_addr<7>" LOC = "p115"; #J1.9
NET "ram_csn" LOC = "p116"; #J1.10
NET "ram_addr<8>" LOC = "p120"; #J1.11
NET "ram_addr<9>" LOC = "p121"; #J1.12
NET "ram_addr<10>" LOC = "p122"; #J1.13
NET "ram_addr<11>" LOC = "p123"; #J1.14
NET "ram_addr<12>" LOC = "p125"; #J1.15
NET "ram_addr<13>" LOC = "p126"; #J1.16
NET "ram_addr<14>" LOC = "p127"; #J1.17
NET "ram_addr<15>" LOC = "p129"; #J1.18
NET "ram_addr<16>" LOC = "p132"; #J1.19
#
# For modified B3-SRAM
# Connector F
#
NET "ram_data<0>" LOC = "p133"; #J2.2
NET "ram_data<1>" LOC = "p134"; #J2.3
NET "ram_data<2>" LOC = "p135"; #J2.4
NET "ram_data<3>" LOC = "p136"; #J2.5
NET "ram_data<4>" LOC = "p138"; #J2.6
NET "ram_data<5>" LOC = "p139"; #J2.7
NET "ram_data<6>" LOC = "p140"; #J2.8
NET "ram_data<7>" LOC = "p141"; #J2.9
NET "ram_data<8>" LOC = "p145"; #J2.10
NET "ram_data<9>" LOC = "p146"; #J2.11
NET "ram_data<10>" LOC = "p147"; #J2.12
NET "ram_data<11>" LOC = "p148"; #J2.13
NET "ram_data<12>" LOC = "p149"; #J2.14
NET "ram_data<13>" LOC = "p150"; #J2.15
NET "ram_data<14>" LOC = "p151"; #J2.16
NET "ram_data<15>" LOC = "p152"; #J2.17
NET "ram_wrun" LOC = "p153"; #J2.18
NET "ram_wrln" LOC = "p154"; #J2.19
#
# Connector G
#
#NET "pin2" LOC = "p182"; #pin 2 (clk input)
NET "test_alu<0>" LOC = "p160"; #pin 3
NET "test_alu<1>" LOC = "p161"; #pin 4
NET "test_alu<2>" LOC = "p162"; #pin 5
NET "test_alu<3>" LOC = "p163"; #pin 6
NET "test_alu<4>" LOC = "p164"; #pin 7
NET "test_alu<5>" LOC = "p165"; #pin 8
NET "test_alu<6>" LOC = "p166"; #pin 9
NET "test_alu<7>" LOC = "p167"; #pin 10
NET "test_alu<8>" LOC = "p168"; #pin 11
NET "test_alu<9>" LOC = "p169"; #pin 12
NET "test_alu<10>" LOC = "p173"; #pin 13
NET "test_alu<11>" LOC = "p174"; #pin 14
NET "test_alu<12>" LOC = "p175"; #pin 15
NET "test_alu<13>" LOC = "p176"; #pin 16
NET "test_alu<14>" LOC = "p178"; #pin 17
NET "test_alu<15>" LOC = "p179"; #pin 18
#NET "pin19" LOC = "p180"; #pin 19
#
# Connector H
#
#NET "pin2" LOC = "p185"; #pin 2 (clk input)
#NET "pin3" LOC = "p181"; #pin 3
#NET "uart_csn" LOC = "p187"; #pin 4
#NET "test_rw" LOC = "p188"; #pin 5
#NET "test_d0" LOC = "p189"; #pin 6
#NET "test_d1" LOC = "p191"; #pin 7
#NET "pin8" LOC = "p192"; #pin 8
#NET "pin9" LOC = "p193"; #pin 9
#NET "pin10" LOC = "p194"; #pin 10
NET "test_cc<0>" LOC = "p198"; #pin 11
NET "test_cc<1>" LOC = "p199"; #pin 12
NET "test_cc<2>" LOC = "p200"; #pin 13
NET "test_cc<3>" LOC = "p201"; #pin 14
NET "test_cc<4>" LOC = "p202"; #pin 15
NET "test_cc<5>" LOC = "p203"; #pin 16
NET "test_cc<6>" LOC = "p204"; #pin 17
NET "test_cc<7>" LOC = "p205"; #pin 18
#NET "pin19" LOC = "p206"; #pin 19
#
# Timing groups
#
INST "ram_addr<0>" TNM = "ram_addr";
INST "ram_addr<1>" TNM = "ram_addr";
INST "ram_addr<2>" TNM = "ram_addr";
INST "ram_addr<3>" TNM = "ram_addr";
INST "ram_addr<4>" TNM = "ram_addr";
INST "ram_addr<5>" TNM = "ram_addr";
INST "ram_addr<6>" TNM = "ram_addr";
INST "ram_addr<7>" TNM = "ram_addr";
INST "ram_addr<8>" TNM = "ram_addr";
INST "ram_addr<9>" TNM = "ram_addr";
INST "ram_addr<10>" TNM = "ram_addr";
INST "ram_addr<11>" TNM = "ram_addr";
INST "ram_addr<12>" TNM = "ram_addr";
INST "ram_addr<13>" TNM = "ram_addr";
INST "ram_addr<14>" TNM = "ram_addr";
INST "ram_addr<15>" TNM = "ram_addr";
INST "ram_addr<16>" TNM = "ram_addr";
INST "ram_data<0>" TNM = "ram_data";
INST "ram_data<1>" TNM = "ram_data";
INST "ram_data<2>" TNM = "ram_data";
INST "ram_data<3>" TNM = "ram_data";
INST "ram_data<4>" TNM = "ram_data";
INST "ram_data<5>" TNM = "ram_data";
INST "ram_data<6>" TNM = "ram_data";
INST "ram_data<7>" TNM = "ram_data";
INST "ram_data<8>" TNM = "ram_data";
INST "ram_data<9>" TNM = "ram_data";
INST "ram_data<10>" TNM = "ram_data";
INST "ram_data<11>" TNM = "ram_data";
INST "ram_data<12>" TNM = "ram_data";
INST "ram_data<13>" TNM = "ram_data";
INST "ram_data<14>" TNM = "ram_data";
INST "ram_data<15>" TNM = "ram_data";
INST "ram_wrln" TNM = "ram_wr";
INST "ram_wrun" TNM = "ram_wr";
INST "ram_csn" TNM = "ram_cs";
INST "test_alu<0>" TNM = "test_alu";
INST "test_alu<1>" TNM = "test_alu";
INST "test_alu<2>" TNM = "test_alu";
INST "test_alu<3>" TNM = "test_alu";
INST "test_alu<4>" TNM = "test_alu";
INST "test_alu<5>" TNM = "test_alu";
INST "test_alu<6>" TNM = "test_alu";
INST "test_alu<7>" TNM = "test_alu";
INST "test_alu<8>" TNM = "test_alu";
INST "test_alu<9>" TNM = "test_alu";
INST "test_alu<10>" TNM = "test_alu";
INST "test_alu<11>" TNM = "test_alu";
INST "test_alu<12>" TNM = "test_alu";
INST "test_alu<13>" TNM = "test_alu";
INST "test_alu<14>" TNM = "test_alu";
INST "test_alu<15>" TNM = "test_alu";
INST "test_cc<0>" TNM = "test_cc";
INST "test_cc<1>" TNM = "test_cc";
INST "test_cc<2>" TNM = "test_cc";
INST "test_cc<3>" TNM = "test_cc";
INST "test_cc<4>" TNM = "test_cc";
INST "test_cc<5>" TNM = "test_cc";
INST "test_cc<6>" TNM = "test_cc";
INST "test_cc<7>" TNM = "test_cc";
TIMEGRP "ram_cs" OFFSET = OUT 35 ns AFTER "sysclk";
TIMEGRP "ram_wr" OFFSET = OUT 35 ns AFTER "sysclk";
TIMEGRP "ram_addr" OFFSET = OUT 35 ns AFTER "sysclk";
TIMEGRP "ram_data" OFFSET = OUT 35 ns AFTER "sysclk";
TIMEGRP "ram_data" OFFSET = IN 15 ns BEFORE "sysclk";
TIMEGRP "test_alu" OFFSET = OUT 90 ns AFTER "sysclk";
TIMEGRP "test_cc" OFFSET = OUT 90 ns AFTER "sysclk";
NET "sysclk" TNM_NET = "sysclk";
TIMESPEC "TS_sysclk" = PERIOD "sysclk" 100 ns LOW 50 %;
NET "ram_addr<0>" FAST;
NET "ram_addr<1>" FAST;
NET "ram_addr<2>" FAST;
NET "ram_addr<3>" FAST;
NET "ram_addr<4>" FAST;
NET "ram_addr<5>" FAST;
NET "ram_addr<6>" FAST;
NET "ram_addr<7>" FAST;
NET "ram_addr<8>" FAST;
NET "ram_addr<9>" FAST;
NET "ram_addr<10>" FAST;
NET "ram_addr<11>" FAST;
NET "ram_addr<12>" FAST;
NET "ram_addr<13>" FAST;
NET "ram_addr<14>" FAST;
NET "ram_addr<15>" FAST;
NET "ram_addr<16>" FAST;
NET "ram_csn" FAST;
NET "ram_data<0>" FAST;
NET "ram_data<1>" FAST;
NET "ram_data<2>" FAST;
NET "ram_data<3>" FAST;
NET "ram_data<4>" FAST;
NET "ram_data<5>" FAST;
NET "ram_data<6>" FAST;
NET "ram_data<7>" FAST;
NET "ram_data<8>" FAST;
NET "ram_data<9>" FAST;
NET "ram_data<10>" FAST;
NET "ram_data<11>" FAST;
NET "ram_data<12>" FAST;
NET "ram_data<13>" FAST;
NET "ram_data<14>" FAST;
NET "ram_data<15>" FAST;
NET "ram_wrln" FAST;
NET "ram_wrun" FAST;
/trunk/rtl/vhdl/testbench3.vhd
0,0 → 1,141
--===========================================================================--
--
-- CPU11 Microprocessor Test Bench 3
--
-- 16 bit compare test (CPX)
--
-- John Kent 21st October 2002
--
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
 
entity my_testbench is
end my_testbench;
 
-------------------------------------------------------------------------------
-- Architecture for memio Controller Unit
-------------------------------------------------------------------------------
architecture behavior of my_testbench is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal uart_irq : Std_Logic;
signal timer_irq : std_logic;
 
-- Sequencer Interface signals
signal SysClk : Std_Logic;
signal cpu_reset : Std_Logic;
signal cpu_rw : std_logic;
signal cpu_vma : std_logic;
signal cpu_addr : Std_Logic_Vector(15 downto 0);
signal cpu_data_in : Std_Logic_Vector(7 downto 0);
signal cpu_data_out: Std_Logic_Vector(7 downto 0);
 
constant width : integer := 8;
constant memsize : integer := 64;
 
type rom_array is array(0 to memsize-1) of std_logic_vector(width-1 downto 0);
 
constant rom_data : rom_array :=
(
"10001110", "11111111", "11011101", -- FFC0 - 8E FFDD RESET LDS #$FFDD
"11111110", "11111111", "11001110", -- FFC3 - FE FFCE LDX BEGA
"00001000", -- FFC6 - 08 LOOP INX
"10111100", "11111111", "11010000", -- FFC7 - BC FFD0 CPX ENDA
"00100011", "11111010", -- FFCA - 23 FA REENT BLS LOOP
"00100000", "11110010", -- FFCC - 20 F2 BRA RESET
"00010010", "00110100", -- FFCE - 12 34 FDB $1234
"00010010", "00110110", -- FFD0 - 12 36 FDB $1236
-- the rest is junk
"00110111", -- FFD2 - 37 PSHB
"11100110", "00000001", -- FFD3 - E6 01 LDAB 1,X
"11100001", "00000011", -- FFD5 - E1 03 CMPB 3,X
"00110011", -- FFD7 - 33 PULB
"00111001", -- FFD8 - 39 RTS
"11111111", "11100000", -- FFD9 - FF E0 FDB $FFE0
"01010101", -- FFDB - 55 FCB $55
"11111111", "11001000", -- FFDC - FFC8 FDB REENT
"00100000", "11100000", -- FFDE - 20 E0 BRA RESET
"00000000", "00000000", -- FFE0 - 00 00 fcb $00,$00
"00000000", "00000000", -- FFE2 - 00 00 fcb $00,$00
"00000000", "00000000", -- FFE4 - 00 00 fcb $00,$00
"00000000", "00000000", -- FFE6 - 00 00 fcb $00,$00
"01001000", "01100101", "01101100", -- FFE8 - 48 65 6c MSG FCC "Hel"
"01101100", "01101111", "00100000", -- FFEB - 6c 6f 20 FCC "lo "
"01010111", "01101111", "01110010", -- FFEE - 57 6f 72 FCC "Wor"
"01101100", "01100100", -- FFF1 - 6c 64 FCC "ld"
"00001010", "00001101", "00000000", -- FFF3 - 0a 0d 00 FCB LF,CR,NULL
"00000000", "00000000", -- FFF6 - 00 00 fcb null,null
"11111111", "11000000", -- FFF8 - FF C0 fdb $FFC0 ; Timer irq
"11111111", "11000000", -- FFFA - FF C0 fdb $FFC0 ; Ext IRQ
"11111111", "11000000", -- FFFC - FF C0 fcb $FFC0 ; SWI
"11111111", "11000000" -- FFFE - FF C0 fdb $FFC0 ; Reset
);
 
component cpu11
port (
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
address: out std_logic_vector(15 downto 0);
vma: out std_logic;
rw: out std_logic; -- Asynchronous memory interface
rst: in std_logic;
clk: in std_logic;
irq: in std_logic;
xirq: in std_logic
);
end component;
 
 
begin
cpu : cpu11 port map (
data_in => cpu_data_in,
data_out => cpu_data_out,
address => cpu_addr(15 downto 0),
vma => cpu_vma,
rw => cpu_rw,
rst => cpu_reset,
clk => SysClk,
irq => uart_irq,
xirq => timer_irq
);
 
-- *** Test Bench - User Defined Section ***
tb : PROCESS
variable count : integer;
BEGIN
 
cpu_reset <= '0';
SysClk <= '0';
uart_irq <= '0';
timer_irq <= '0';
 
for count in 0 to 256 loop
SysClk <= '0';
if count = 0 then
cpu_reset <= '1';
elsif count = 1 then
cpu_reset <= '0';
end if;
wait for 100 ns;
SysClk <= '1';
wait for 100 ns;
end loop;
 
wait; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***
 
 
rom : PROCESS( cpu_addr )
begin
cpu_data_in <= rom_data(conv_integer(cpu_addr(5 downto 0)));
end process;
 
end behavior; --===================== End of architecture =======================--
 
/trunk/rtl/vhdl/System11.vhd
0,0 → 1,555
--===========================================================================--
--
-- S Y N T H E Z I A B L E System11 - System on a Chip
--
-- www.OpenCores.Org - September 2003
-- This core adheres to the GNU public license
--
-- File name : system11.vhd
--
-- Entity name : system11
--
-- Purpose : SWTBUG Monitor modified for the 68HC11
-- ROM sits at $E000
-- Assumes an 6850 ACIA sits at $8004
-- Assumes RAM at $A000 - $BFFF for Flex 2
-- 1024 byte x 8 bit
-- Modified stack to allow for Y register
-- This SOC does not include any 68HC11
-- on chip peripherals
--
-- Dependencies : ieee.std_logic_1164
-- ieee.std_logic_arith
-- ieee.std_logic_unsigned
--
-- Uses : cpu11 (cpu11.vhd) CPU core
-- boot_rom (swtbug11.vhd) Monitor ROM
-- dat_ram (datram.vhd) Dynamic Address Translation
-- miniuart (miniUART.vhd) UART
-- clkunit (clkunit.vhd)
-- rxunit (rxunit.vhd)
-- txunit (txunit.vhd)
-- ioport (ioport.vhd) parallel i/o port
-- timer (timer.vhd) small counter timer
--
-------------------------------------------------------------------------------
-- Revision list
-- Version Author Date Changes
-- 1.0 John Kent 6 September 2003 Initial release to open corse
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
 
entity System11 is
port(
SysClk : in Std_Logic; -- System Clock input
Reset_n : in Std_logic; -- Master Reset input (active low)
LED : out std_logic; -- Diagnostic LED Flasher
 
-- Memory Interface signals
ram_csn : out Std_Logic;
ram_wrln : out Std_Logic;
ram_wrun : out Std_Logic;
ram_addr : out Std_Logic_Vector(16 downto 0);
ram_data : inout Std_Logic_Vector(15 downto 0);
 
-- Stuff on the peripheral board
-- aux_clock : in Std_Logic; -- FPGA-CPU-IO clock
 
-- PS/2 Mouse interface
-- mouse_clock : in Std_Logic;
-- mouse_data : in Std_Logic;
 
-- Uart Interface
rxbit : in Std_Logic;
txbit : out Std_Logic;
rts_n : out Std_Logic;
cts_n : in Std_Logic;
 
-- CRTC output signals
-- v_drive : out Std_Logic;
-- h_drive : out Std_Logic;
-- blue_lo : out std_logic;
-- blue_hi : out std_logic;
-- green_lo : out std_logic;
-- green_hi : out std_logic;
-- red_lo : out std_logic;
-- red_hi : out std_logic;
-- buzzer : out std_logic;
 
-- I/O Ports
PortA : inout std_logic_vector(7 downto 0);
PortB : inout std_logic_vector(7 downto 0);
-- PortC : inout std_logic_vector(7 downto 0);
-- PortD : inout std_logic_vector(7 downto 0);
 
-- Timer I/O
timer_out : out std_logic;
 
-- Compact Flash B5-CF Module
cf_rst_n : out std_logic;
cf_cs0_n : out std_logic;
cf_cs1_n : out std_logic;
cf_rd_n : out std_logic;
cf_wr_n : out std_logic;
cf_cs16_n : out std_logic;
cf_a : out std_logic_vector(2 downto 0);
cf_d : inout std_logic_vector(15 downto 0);
-- cf_intrq : in std_logic;
-- cf_iordy : in std_logic;
-- cf_dase : in std_logic;
-- cf_pdiag : in std_logic;
-- cf_present : in std_logic;
 
-- test signals
test_alu : out std_logic_vector(15 downto 0);
test_cc : out std_logic_vector(7 downto 0)
);
end;
 
-------------------------------------------------------------------------------
-- Architecture for memio Controller Unit
-------------------------------------------------------------------------------
architecture my_computer of System11 is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
-- CPU Interface signals
signal cpu_reset : Std_Logic;
signal cpu_clk : Std_Logic;
signal cpu_rw : std_logic;
signal cpu_vma : std_logic;
signal cpu_irq : std_logic;
signal cpu_xirq : std_logic;
signal cpu_addr : Std_Logic_Vector(15 downto 0);
signal cpu_data_in : Std_Logic_Vector(7 downto 0);
signal cpu_data_out: Std_Logic_Vector(7 downto 0);
 
-- BOOT ROM
signal rom_data_out : Std_Logic_Vector(7 downto 0);
 
-- UART Interface signals
signal uart_data_out : Std_Logic_Vector(7 downto 0);
signal uart_cs : Std_Logic;
signal uart_irq : Std_Logic;
 
-- timer
signal timer_data_out : std_logic_vector(7 downto 0);
signal timer_cs : std_logic;
signal timer_irq : std_logic;
 
-- i/o port
signal ioport_data_out : std_logic_vector(7 downto 0);
signal ioport_cs : std_logic;
 
-- RAM
signal ram_cs : std_logic; -- memory chip select
signal ram_wrl : std_logic; -- memory write lower
signal ram_wru : std_logic; -- memory write upper
signal ram_data_out : std_logic_vector(7 downto 0);
 
-- compact flash port
signal cf_cs : std_logic;
signal cf_rd : std_logic;
signal cf_wr : std_logic;
signal cf_data_out : std_logic_vector(7 downto 0);
 
-- Dynamic Address Translation RAM
signal dat_cs : std_logic;
signal dat_data_out: std_logic_vector(7 downto 0);
 
-- Flashing Led test signals
signal countL : std_logic_vector(23 downto 0);
 
 
-----------------------------------------------------------------
--
-- Open Cores Mini UART
--
-----------------------------------------------------------------
 
component miniUART
port (
SysClk : in Std_Logic; -- System Clock
rst : in Std_Logic; -- Reset input
cs : in Std_Logic;
rw : in Std_Logic;
RxD : in Std_Logic;
TxD : out Std_Logic;
CTS_n : in Std_Logic;
RTS_n : out Std_Logic;
Irq : out Std_logic;
Addr : in Std_Logic;
DataIn : in Std_Logic_Vector(7 downto 0); --
DataOut : out Std_Logic_Vector(7 downto 0)); --
end component;
 
--------------------------------------
--
-- Three port parallel I/O
--
---------------------------------------
 
component ioport
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector(1 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
porta_io : inout std_logic_vector(7 downto 0);
portb_io : inout std_logic_vector(7 downto 0)
);
end component;
 
----------------------------------------
--
-- Timer module
--
----------------------------------------
 
component timer
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
irq : out std_logic;
timer_in : in std_logic;
timer_out : out std_logic
);
end component;
 
component cpu11
port (
clk: in std_logic;
rst: in std_logic;
rw: out std_logic; -- Asynchronous memory interface
vma: out std_logic;
address: out std_logic_vector(15 downto 0);
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
irq: in std_logic;
xirq: in std_logic;
test_alu: out std_logic_vector(15 downto 0);
test_cc: out std_logic_vector(7 downto 0)
);
end component;
 
component dat_ram
port (
clk: in std_logic;
rst: in std_logic;
cs: in std_logic;
rw: in std_logic;
addr_lo: in std_logic_vector(3 downto 0);
addr_hi: in std_logic_vector(3 downto 0);
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0)
);
end component;
 
component boot_rom
port (
addr : in Std_Logic_Vector(9 downto 0); -- 1K byte boot rom
data : out Std_Logic_Vector(7 downto 0)
);
end component;
 
-- component BUFG is
-- port (
-- i: in std_logic;
-- o: out std_logic
-- );
-- end component;
 
begin
-----------------------------------------------------------------------------
-- Instantiation of internal components
-----------------------------------------------------------------------------
 
my_uart : miniUART port map (
SysClk => SysClk,
rst => cpu_reset,
cs => uart_cs,
rw => cpu_rw,
RxD => rxbit,
TxD => txbit,
CTS_n => cts_n,
RTS_n => rts_n,
Irq => uart_irq,
Addr => cpu_addr(0),
Datain => cpu_data_out,
DataOut => uart_data_out
);
 
my_ioport : ioport port map (
clk => SysClk,
rst => cpu_reset,
cs => ioport_cs,
rw => cpu_rw,
addr => cpu_addr(1 downto 0),
data_in => cpu_data_out,
data_out => ioport_data_out,
porta_io => porta,
portb_io => portb
);
 
my_timer : timer port map (
clk => SysClk,
rst => cpu_reset,
cs => timer_cs,
rw => cpu_rw,
addr => cpu_addr(0),
data_in => cpu_data_out,
data_out => timer_data_out,
irq => timer_irq,
timer_in => CountL(5),
timer_out => timer_out
);
 
my_cpu : cpu11 port map (
clk => SysClk,
rst => cpu_reset,
rw => cpu_rw,
vma => cpu_vma,
address => cpu_addr(15 downto 0),
data_in => cpu_data_in,
data_out => cpu_data_out,
irq => cpu_irq,
xirq => cpu_xirq,
test_alu => test_alu,
test_cc => test_cc
);
 
 
my_dat : dat_ram port map (
clk => SysClk,
rst => cpu_reset,
cs => dat_cs,
rw => cpu_rw,
addr_hi => cpu_addr(15 downto 12),
addr_lo => cpu_addr(3 downto 0),
data_in => cpu_data_out,
data_out => dat_data_out(7 downto 0)
);
 
rom : boot_rom port map (
addr => cpu_addr(9 downto 0),
data => rom_data_out
);
 
-- clk_buffer : BUFG port map(
-- i => e_clk,
-- o => cpu_clk
-- );
----------------------------------------------------------------------
--
-- Processes to read and write memory based on bus signals
--
----------------------------------------------------------------------
 
my_decoder: process(
cpu_addr, cpu_vma,
rom_data_out, ram_data_out,
ioport_data_out, timer_data_out, uart_data_out, cf_data_out )
begin
case cpu_addr(15 downto 13) is
--
-- ROM & DAT Space $E000 - $FFFF
--
when "111" => -- $E000 - $FFFF
cpu_data_in <= rom_data_out;
dat_cs <= cpu_vma;
ram_cs <= '0';
uart_cs <= '0';
cf_cs <= '0';
timer_cs <= '0';
ioport_cs <= '0';
--
-- I/O Space at $8000 - $9FFF
--
when "100" => -- $8000 - $9FFF
dat_cs <= '0';
ram_cs <= '0';
case cpu_addr(6 downto 4) is
--
-- UART $8004
--
when "000" => -- $8000 - $800F
cpu_data_in <= uart_data_out;
uart_cs <= cpu_vma;
cf_cs <= '0';
timer_cs <= '0';
ioport_cs <= '0';
--
-- Compact Flash $8010
--
when "001" => -- $8010 - $801F
cpu_data_in <= cf_data_out;
uart_cs <= '0';
cf_cs <= cpu_vma;
timer_cs <= '0';
ioport_cs <= '0';
--
-- Timer $8020
--
when "010" => -- $8020 - $802F
cpu_data_in <= timer_data_out;
uart_cs <= '0';
cf_cs <= '0';
timer_cs <= cpu_vma;
ioport_cs <= '0';
--
-- I/O Port $8030
--
when "011" => -- $8030 - $803F
cpu_data_in <= ioport_data_out;
uart_cs <= '0';
cf_cs <= '0';
timer_cs <= '0';
ioport_cs <= cpu_vma;
--
-- Empty
--
when others => -- $8040 to $9FFF
cpu_data_in <= "00000000";
uart_cs <= '0';
cf_cs <= '0';
timer_cs <= '0';
ioport_cs <= '0';
end case;
--
-- The rest is all RAM
--
when others =>
cpu_data_in <= ram_data_out;
ram_cs <= cpu_vma;
dat_cs <= '0';
uart_cs <= '0';
cf_cs <= '0';
timer_cs <= '0';
ioport_cs <= '0';
end case;
end process;
 
----------------------------------------------------------------------
--
-- Processes to read and write external RAM
--
----------------------------------------------------------------------
 
my_ram: process( SysClk, Reset_n,
cpu_addr, cpu_rw, cpu_data_out,
ram_cs, ram_wrl, ram_wru,
ram_data, dat_data_out )
begin
ram_csn <= not( ram_cs and Reset_n );
ram_wrl <= (not dat_data_out(5)) and (not cpu_rw) and SysClk;
ram_wrln <= not ram_wrl;
ram_wru <= dat_data_out(5) and (not cpu_rw) and SysClk;
ram_wrun <= not ram_wru;
ram_addr(16 downto 12) <= dat_data_out(4 downto 0);
ram_addr(11 downto 0) <= cpu_addr(11 downto 0);
 
if ram_wrl = '1' then
ram_data(7 downto 0) <= cpu_data_out;
else
ram_data(7 downto 0) <= "ZZZZZZZZ";
end if;
 
if ram_wru = '1' then
ram_data(15 downto 8) <= cpu_data_out;
else
ram_data(15 downto 8) <= "ZZZZZZZZ";
end if;
 
if dat_data_out(5) = '1' then
ram_data_out <= ram_data(15 downto 8);
else
ram_data_out <= ram_data(7 downto 0);
end if;
end process;
 
 
--
-- B5-CF Compact Flash Control
--
b5_cf: process( Reset_n,
cpu_addr, cpu_rw, cpu_data_out,
cf_cs, cf_rd, cf_wr, cf_d )
begin
cf_rst_n <= Reset_n;
cf_cs0_n <= not( cf_cs ) or cpu_addr(3);
cf_cs1_n <= not( cf_cs and cpu_addr(3));
cf_cs16_n <= '1';
cf_wr <= cf_cs and (not cpu_rw);
cf_rd <= cf_cs and cpu_rw;
cf_wr_n <= not cf_wr;
cf_rd_n <= not cf_rd;
cf_a <= cpu_addr(2 downto 0);
if cf_wr = '1' then
cf_d(7 downto 0) <= cpu_data_out;
else
cf_d(7 downto 0) <= "ZZZZZZZZ";
end if;
cf_data_out <= cf_d(7 downto 0);
cf_d(15 downto 8) <= "ZZZZZZZZ";
end process;
 
--
-- tie together interrupts
--
interrupts : process( Reset_n, timer_irq, uart_irq )
begin
cpu_reset <= not Reset_n; -- CPU reset is active high
cpu_irq <= uart_irq;
cpu_xirq <= timer_irq;
end process;
 
--
--
--clock_gen : process( SysClk, e_clk )
--begin
-- if SysClk'event and SysClk='0' then
-- e_clk <= not e_clk;
-- end if;
--end process;
 
--
-- flash led to indicate code is working
--
increment: process (SysClk, CountL )
begin
if(SysClk'event and SysClk = '0') then
countL <= countL + 1;
end if;
LED <= countL(21);
end process;
 
 
 
--
-- CRTC output signals
--
-- v_drive <= '0';
-- h_drive <= '0';
-- blue_lo <= '0';
-- blue_hi <= '0';
-- green_lo <= '0';
-- green_hi <= '0';
-- red_lo <= '0';
-- red_hi <= '0';
-- buzzer <= '0';
end my_computer; --===================== End of architecture =======================--
 
/trunk/rtl/vhdl/datram.vhd
0,0 → 1,200
--===========================================================================--
--
-- S Y N T H E Z I A B L E datram - Dynamic Address Translation core
--
-- www.OpenCores.Org - September 2003
-- This core adheres to the GNU public license
--
-- File name : datram.vhd
--
-- Entity name : dat_ram
--
-- Purpose : Maps address bits A12 to A15 of an 8 bit
-- Microprocessor to access 1Mbyte of RAM
-- The 8 data output pins form addresses
-- PA12 to PA19. 16 x 4K pages are selected
-- by writing the high order physical address
-- of memory into the 16 registers.
-- Low order CPU addres bits A11 .. A0
-- connect directly through to the Phyical
-- address bits PA11 .. PA0
-- Register 0 is for A15..A12 = "0000"
-- Register 1 is for A15..A12 = "0001"
-- Register 2 is for A15..A12 = "0010"
-- Register 15 is for A15..A12 = "1111"
-- Registers are pre-initialised to select
-- the bottom 64K of physical address space
--
-- Dependencies : ieee.std_logic_1164
-- ieee.std_logic_unsigned
--
-- Uses : Nothing
--
-------------------------------------------------------------------------------
-- Revision list
--
-- Revision 0.1 - 10 November 2002 - John Kent
--
-- Revision 1.0 - 7 September - John Kent
-- Initial release to open cores
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity dat_ram is
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr_hi : in std_logic_vector(3 downto 0);
addr_lo : in std_logic_vector(3 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0));
end;
 
architecture datram_arch of dat_ram is
signal dat_reg0 : std_logic_vector(7 downto 0);
signal dat_reg1 : std_logic_vector(7 downto 0);
signal dat_reg2 : std_logic_vector(7 downto 0);
signal dat_reg3 : std_logic_vector(7 downto 0);
signal dat_reg4 : std_logic_vector(7 downto 0);
signal dat_reg5 : std_logic_vector(7 downto 0);
signal dat_reg6 : std_logic_vector(7 downto 0);
signal dat_reg7 : std_logic_vector(7 downto 0);
signal dat_reg8 : std_logic_vector(7 downto 0);
signal dat_reg9 : std_logic_vector(7 downto 0);
signal dat_reg10 : std_logic_vector(7 downto 0);
signal dat_reg11 : std_logic_vector(7 downto 0);
signal dat_reg12 : std_logic_vector(7 downto 0);
signal dat_reg13 : std_logic_vector(7 downto 0);
signal dat_reg14 : std_logic_vector(7 downto 0);
signal dat_reg15 : std_logic_vector(7 downto 0);
 
begin
 
 
--------------------------------
--
-- read I/O port
--
--------------------------------
 
 
---------------------------------
--
-- Write DAT RAM
--
---------------------------------
 
dat_write : process( clk, rst, addr_lo, cs, rw, data_in )
begin
if clk'event and clk = '0' then
if rst = '1' then
dat_reg0 <= "00000000";
dat_reg1 <= "00000001";
dat_reg2 <= "00000010";
dat_reg3 <= "00000011";
dat_reg4 <= "00000100";
dat_reg5 <= "00000101";
dat_reg6 <= "00000110";
dat_reg7 <= "00000111";
dat_reg8 <= "00001000";
dat_reg9 <= "00001001";
dat_reg10 <= "00001010";
dat_reg11 <= "00001011";
dat_reg12 <= "00001100";
dat_reg13 <= "00001101";
dat_reg14 <= "00001110";
dat_reg15 <= "00001111";
else
if cs = '1' and rw = '0' then
case addr_lo is
when "0000" =>
dat_reg0 <= data_in;
when "0001" =>
dat_reg1 <= data_in;
when "0010" =>
dat_reg2 <= data_in;
when "0011" =>
dat_reg3 <= data_in;
when "0100" =>
dat_reg4 <= data_in;
when "0101" =>
dat_reg5 <= data_in;
when "0110" =>
dat_reg6 <= data_in;
when "0111" =>
dat_reg7 <= data_in;
when "1000" =>
dat_reg8 <= data_in;
when "1001" =>
dat_reg9 <= data_in;
when "1010" =>
dat_reg10 <= data_in;
when "1011" =>
dat_reg11 <= data_in;
when "1100" =>
dat_reg12 <= data_in;
when "1101" =>
dat_reg13 <= data_in;
when "1110" =>
dat_reg14 <= data_in;
when "1111" =>
dat_reg15 <= data_in;
when others =>
null;
end case;
end if;
end if;
end if;
end process;
 
dat_read : process( addr_hi,
dat_reg0, dat_reg1, dat_reg2, dat_reg3,
dat_reg4, dat_reg5, dat_reg6, dat_reg7,
dat_reg8, dat_reg9, dat_reg10, dat_reg11,
dat_reg12, dat_reg13, dat_reg14, dat_reg15 )
begin
case addr_hi is
when "0000" =>
data_out <= dat_reg0;
when "0001" =>
data_out <= dat_reg1;
when "0010" =>
data_out <= dat_reg2;
when "0011" =>
data_out <= dat_reg3;
when "0100" =>
data_out <= dat_reg4;
when "0101" =>
data_out <= dat_reg5;
when "0110" =>
data_out <= dat_reg6;
when "0111" =>
data_out <= dat_reg7;
when "1000" =>
data_out <= dat_reg8;
when "1001" =>
data_out <= dat_reg9;
when "1010" =>
data_out <= dat_reg10;
when "1011" =>
data_out <= dat_reg11;
when "1100" =>
data_out <= dat_reg12;
when "1101" =>
data_out <= dat_reg13;
when "1110" =>
data_out <= dat_reg14;
when "1111" =>
data_out <= dat_reg15;
when others =>
null;
end case;
end process;
 
end datram_arch;
/trunk/rtl/vhdl/miniUART.vhd
0,0 → 1,250
--===========================================================================--
--
-- S Y N T H E Z I A B L E miniUART C O R E
--
-- www.OpenCores.Org - January 2000
-- This core adheres to the GNU public license
--
-- Design units : miniUART core for the OCRP-1
--
-- File name : miniuart.vhd
--
-- Purpose : Implements an miniUART device for communication purposes
-- between the OR1K processor and the Host computer through
-- an RS-232 communication protocol.
--
-- Library : uart_lib.vhd
--
-- Dependencies : IEEE.Std_Logic_1164
--
-- Simulator : ModelSim PE/PLUS version 4.7b on a Windows95 PC
--===========================================================================--
-------------------------------------------------------------------------------
-- Revision list
-- Version Author Date Changes
--
-- 0.1 Ovidiu Lupas 15 January 2000 New model
-- 1.0 Ovidiu Lupas January 2000 Synthesis optimizations
-- 2.0 Ovidiu Lupas April 2000 Bugs removed - RSBusCtrl
-- the RSBusCtrl did not process all possible situations
--
-- olupas@opencores.org
--
-- 3.0 John Kent October 2002 Changed Status bits to match mc6805
-- Added CTS, RTS, Baud rate control & Software Reset
-------------------------------------------------------------------------------
-- Entity for miniUART Unit - 9600 baudrate --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity miniUART is
port (
SysClk : in Std_Logic; -- System Clock
rst : in Std_Logic; -- Reset input (active high)
cs : in Std_Logic;
rw : in Std_Logic;
RxD : in Std_Logic;
TxD : out Std_Logic;
CTS_n : in Std_Logic;
RTS_n : out Std_Logic;
Irq : out Std_Logic; -- interrupt
Addr : in Std_Logic; -- Register Select
DataIn : in Std_Logic_Vector(7 downto 0); --
DataOut : out Std_Logic_Vector(7 downto 0)); --
end entity; --================== End of entity ==============================--
-------------------------------------------------------------------------------
-- Architecture for miniUART Controller Unit
-------------------------------------------------------------------------------
architecture uart of miniUART is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal RxData : Std_Logic_Vector(7 downto 0); --
signal TxData : Std_Logic_Vector(7 downto 0); --
signal StatReg : Std_Logic_Vector(7 downto 0); -- status register
signal CtrlReg : Std_Logic_Vector(7 downto 0); -- control register
-- StatReg detailed
-----------+--------+--------+--------+--------+--------+--------+--------+
-- Int | PErr | ORErr | FErr | CTS | DCD | TBufE | DRdy |
-----------+--------+--------+--------+--------+--------+--------+--------+
signal EnabRx : Std_Logic; -- Enable RX unit
signal EnabTx : Std_Logic; -- Enable TX unit
signal DRdy : Std_Logic; -- Receive Data ready
signal TBufE : Std_Logic; -- Transmit buffer empty
signal FErr : Std_Logic; -- Frame error
signal OErr : Std_Logic; -- Output error
signal Read : Std_Logic; -- Read receive buffer
signal Load : Std_Logic; -- Load transmit buffer
signal Int : Std_Logic; -- Interrupt bit
signal Reset : Std_Logic; -- Reset (Software & Hardware)
-----------------------------------------------------------------------------
-- Baud rate Generator
-----------------------------------------------------------------------------
component ClkUnit is
port (
Clk : in Std_Logic; -- System Clock
Reset : in Std_Logic; -- Reset input
EnableRX : out Std_Logic; -- Control signal
EnableTX : out Std_Logic; -- Control signal
BaudRate : in Std_Logic_Vector(1 downto 0));
end component;
-----------------------------------------------------------------------------
-- Receive Unit
-----------------------------------------------------------------------------
component RxUnit is
port (
Clk : in Std_Logic; -- Clock signal
Reset : in Std_Logic; -- Reset input
Enable : in Std_Logic; -- Enable input
RxD : in Std_Logic; -- RS-232 data input
ReadD : in Std_Logic; -- Read data signal
FRErr : out Std_Logic; -- Status signal
ORErr : out Std_Logic; -- Status signal
DARdy : out Std_Logic; -- Status signal
DataI : out Std_Logic_Vector(7 downto 0));
end component;
-----------------------------------------------------------------------------
-- Transmitter Unit
-----------------------------------------------------------------------------
component TxUnit is
port (
Clk : in Std_Logic; -- Clock signal
Reset : in Std_Logic; -- Reset input
Enable : in Std_Logic; -- Enable input
LoadD : in Std_Logic; -- Load transmit data
TxD : out Std_Logic; -- RS-232 data output
TBE : out Std_Logic; -- Tx buffer empty
DataO : in Std_Logic_Vector(7 downto 0));
end component;
begin
-----------------------------------------------------------------------------
-- Instantiation of internal components
-----------------------------------------------------------------------------
 
ClkDiv : ClkUnit port map (
Clk => SysClk,
EnableRx => EnabRX,
EnableTx => EnabTX,
BaudRate => CtrlReg(1 downto 0),
Reset => Reset);
TxDev : TxUnit port map (
Clk => SysClk,
Reset => Reset,
Enable => EnabTX,
LoadD => Load,
TxD => TxD,
TBE => TBufE,
DataO => TxData);
 
RxDev : RxUnit port map (
Clk => SysClk,
Reset => Reset,
Enable => EnabRX,
RxD => RxD,
ReadD => Read,
FRErr => FErr,
ORErr => OErr,
DARdy => DRdy,
DataI => RxData);
 
-----------------------------------------------------------------------------
-- Implements the controller for Rx&Tx units
-----------------------------------------------------------------------------
RSBusCtrl : process(SysClk, Reset, DRdy, TBufE, FErr, OErr, Int, CtrlReg)
variable StatM : Std_Logic_Vector(7 downto 0);
begin
if SysClk'event and SysClk='0' then
if Reset = '1' then
StatM := "00000000";
Int <= '0';
else
StatM(0) := DRdy;
StatM(1) := TBufE;
StatM(2) := '0'; -- DCD
StatM(3) := CTS_n;
StatM(4) := FErr;
StatM(5) := OErr;
StatM(6) := '0'; -- Parrity error
StatM(7) := Int;
Int <= (CtrlReg(7) and DRdy) or
((not CtrlReg(6)) and CtrlReg(5) and TBufE);
end if;
 
RTS_n <= CtrlReg(6) and not CtrlReg(5);
Irq <= Int;
StatReg <= StatM;
end if;
end process;
 
-----------------------------------------------------------------------------
-- Combinational section
-----------------------------------------------------------------------------
 
control_strobe: process(SysClk, Reset, cs, rw, Addr, DataIn, CtrlReg )
begin
if SysClk'event and SysClk='0' then
if (reset = '1') then
CtrlReg <= "00000000";
Load <= '0';
Read <= '0';
else
if cs = '1' then
if Addr = '1' then
CtrlReg <= CtrlReg;
if rw = '0' then -- write data register
Load <= '1';
Read <= '0';
else -- read Data Register
Load <= '0';
Read <= '1';
end if; -- rw
else -- read Status Register
Load <= '0';
Read <= '0';
if rw = '0' then -- write data register
CtrlReg <= DataIn;
else -- read Data Register
CtrlReg <= CtrlReg;
end if; -- rw
end if; -- Addr
else -- not selected
Load <= '0';
Read <= '0';
CtrlReg <= CtrlReg;
end if; -- cs
end if; -- reset
end if; -- SysClk
end process;
 
---------------------------------------------------------------
--
-- set data output mux
--
--------------------------------------------------------------
 
data_port: process(Addr, StatReg, RxData, DataIn )
begin
TxData <= DataIn;
if Addr = '1' then
DataOut <= RxData; -- read data register
else
DataOut <= StatReg; -- read status register
end if; -- Addr
end process;
 
---------------------------------------------------------------
--
-- reset may be hardware or software
--
---------------------------------------------------------------
 
uart_reset: process(CtrlReg, rst )
begin
Reset <= (CtrlReg(1) and CtrlReg(0)) or rst;
end process;
 
end uart; --===================== End of architecture =======================--
 
/trunk/rtl/vhdl/clkunit.vhd
0,0 → 1,129
--===========================================================================--
--
-- S Y N T H E Z I A B L E miniUART C O R E
--
-- www.OpenCores.Org - January 2000
-- This core adheres to the GNU public license
 
-- Design units : miniUART core for the OCRP-1
--
-- File name : clkUnit.vhd
--
-- Purpose : Implements an miniUART device for communication purposes
-- between the OR1K processor and the Host computer through
-- an RS-232 communication protocol.
--
-- Library : uart_lib.vhd
--
-- Dependencies : IEEE.Std_Logic_1164
--
--===========================================================================--
-------------------------------------------------------------------------------
-- Revision list
-- Version Author Date Changes
--
-- 0.1 Ovidiu Lupas 15 January 2000 New model
-- olupas@opencores.org
-- 0.2 John Kent ?? October 2002 Added programmable baud rate
-- 0.3 John Kent 15 December 2002 Fixed TX counter
-------------------------------------------------------------------------------
-- Description : Generates the Baud clock and enable signals for RX & TX
-- units.
-------------------------------------------------------------------------------
-- Entity for Baud rate generator Unit - 9600 baudrate --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
-------------------------------------------------------------------------------
-- Baud rate generator
-------------------------------------------------------------------------------
entity ClkUnit is
port (
Clk : in Std_Logic; -- System Clock
Reset : in Std_Logic; -- Reset input
EnableRx : out Std_Logic; -- Control signal
EnableTx : out Std_Logic; -- Control signal
BaudRate : in Std_Logic_Vector(1 downto 0));
end entity; --================== End of entity ==============================--
-------------------------------------------------------------------------------
-- Architecture for Baud rate generator Unit
-------------------------------------------------------------------------------
architecture Behaviour of ClkUnit is
signal tmpEnRx : std_logic;
 
begin
-----------------------------------------------------------------------------
-- Divides the system clock of 40 MHz div 260 gives 153 KHz for 9600bps
-- 48 MHz div 156 gives 300 KHz for 19.2Kbps
-- 24 MHz div 156 gives 153 KHz for 9600bps
-- 4.9152MHz div 32 gives 153KHz for 9600bps
-----------------------------------------------------------------------------
DivClk : process(Clk,Reset,tmpEnRx, BaudRate)
variable Count : unsigned(7 downto 0);
constant CntOne : Unsigned(7 downto 0):="00000001";
begin
if Clk'event and Clk = '0' then
if Reset = '1' then
Count := "00000000";
tmpEnRx <= '0';
else
if Count = "00000000" then
tmpEnRx <= '1';
case BaudRate is
when "00" => -- divide by 1 ((1*2)-1) (fast)
Count := "00000001";
when "01" => -- divide by 16 ((16*2)-1) (9600 Baud)
Count := "00011111";
when "10" => -- divide by 64 ((64*2)-1) (2400 Baud)
Count := "01111111";
when others =>
-- when "11" => -- reset
Count := "00000000";
null;
end case;
else
tmpEnRx <= '0';
Count := Count - CntOne;
end if;
end if;
end if;
EnableRx <= tmpEnRx;
end process;
 
-----------------------------------------------------------------------------
-- Provides the EnableTX signal, at 9.6 KHz
-- Divide by 16
-- Except it wasn't ... it counted up to "10010" (18)
-----------------------------------------------------------------------------
DivClk16 : process(Clk,Reset,tmpEnRX)
variable Cnt16 : unsigned(4 downto 0);
constant CntOne : Unsigned(4 downto 0):="00001";
begin
if Clk'event and Clk = '0' then
if Reset = '1' then
Cnt16 := "00000";
EnableTX <= '0';
else
case Cnt16 is
when "00000" =>
if tmpEnRx = '1' then
Cnt16 := "01111";
EnableTx <='1';
else
Cnt16 := Cnt16;
EnableTx <='0';
end if;
when others =>
if tmpEnRx = '1' then
Cnt16 := Cnt16 - CntOne;
else
Cnt16 := Cnt16;
end if;
EnableTX <= '0';
end case;
end if;
end if;
end process;
end Behaviour; --==================== End of architecture ===================--
/trunk/rtl/vhdl/cpu11.vhd
0,0 → 1,4770
--===========================================================================--
--
-- S Y N T H E Z I A B L E cpu11 - HC11 compatible CPU core
--
-- www.OpenCores.Org - September 2003
-- This core adheres to the GNU public license
--
-- File name : cpu11.vhd
--
-- Entity name : cpu11
--
-- Purpose : HC11 instruction set compatible CPU core
--
-- Dependencies : ieee.std_logic_1164
-- ieee.std_logic_unsigned
--
-- Uses : Nothing
--
-- Author : John Kent - dilbert57@opencores.org
--
-------------------------------------------------------------------------------
-- Revision list
--
-- Version 0.1 - 13 November 2002 - John Kent
-- revamped 6801 CPU into 68HC11 CPU.
-- Added Y index register
-- Added Y indexing prebyte
-- Added CMPD with prebyte
-- Added bit operators
-- Updated stack operations
--
-- Version 0.3 - 15 December 2002 - John Kent
-- implemented FDIV
-- implemented IDIV
--
-- Version 1.0 - 7 September 2003 - John Kent
-- Released to Open Cores
-- Basic 6800 instructions working
-- but not Divide and bit operations.
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity cpu11 is
port (
clk: in std_logic;
rst: in std_logic;
rw: out std_logic;
vma: out std_logic;
address: out std_logic_vector(15 downto 0);
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
irq: in std_logic;
xirq: in std_logic;
test_alu: out std_logic_vector(15 downto 0);
test_cc: out std_logic_vector(7 downto 0)
);
end;
 
architecture CPU_ARCH of cpu11 is
 
constant SBIT : integer := 7;
constant XBIT : integer := 6;
constant HBIT : integer := 5;
constant IBIT : integer := 4;
constant NBIT : integer := 3;
constant ZBIT : integer := 2;
constant VBIT : integer := 1;
constant CBIT : integer := 0;
 
type state_type is (reset_state, fetch_state, decode_state,
extended_state, indexed_state, direct_state, direct16_state, immediate16_state,
write8_state, write16_state,
execute_state, halt_state, spin_state,
exchange1_state, exchange2_state,
mul_state, mulea_state, muld_state, mul0_state,
idiv_state,
div1_state, div2_state, div3_state, div4_state, div5_state,
jmp_state, jsr_state, jsr1_state,
branch_state, bsr_state, bsr1_state,
bitmask_state, brset_state, brclr_state, bset_state, bclr_state,
rts_hi_state, rts_lo_state,
int_pcl_state, int_pch_state,
int_ixl_state, int_ixh_state,
int_iyl_state, int_iyh_state,
int_cc_state, int_acca_state, int_accb_state,
int_wai_state, int_maski_state, int_maskx_state,
rti_state, rti_cc_state, rti_acca_state, rti_accb_state,
rti_ixl_state, rti_ixh_state,
rti_iyl_state, rti_iyh_state,
rti_pcl_state, rti_pch_state,
pula_state, psha_state, pulb_state, pshb_state,
pulx_lo_state, pulx_hi_state, pshx_lo_state, pshx_hi_state,
vect_lo_state, vect_hi_state );
type addr_type is (idle_ad, fetch_ad, read_ad, write_ad, push_ad, pull_ad, int_hi_ad, int_lo_ad );
type dout_type is ( acca_dout, accb_dout, cc_dout,
ix_lo_dout, ix_hi_dout, iy_lo_dout, iy_hi_dout,
md_lo_dout, md_hi_dout, pc_lo_dout, pc_hi_dout );
type op_type is (reset_op, fetch_op, latch_op );
type pre_type is (reset_pre, fetch_pre, latch_pre );
type acca_type is (reset_acca, load_acca, load_hi_acca, pull_acca, latch_acca );
type accb_type is (reset_accb, load_accb, pull_accb, latch_accb );
type cc_type is (reset_cc, load_cc, pull_cc, latch_cc );
type ix_type is (reset_ix, load_ix, pull_lo_ix, pull_hi_ix, latch_ix );
type iy_type is (reset_iy, load_iy, pull_lo_iy, pull_hi_iy, latch_iy );
type sp_type is (reset_sp, latch_sp, load_sp );
type pc_type is (reset_pc, latch_pc, load_pc, pull_lo_pc, pull_hi_pc );
type md_type is (reset_md, latch_md, load_md, fetch_first_md, fetch_next_md, shiftl_md );
type ea_type is (reset_ea, latch_ea, load_ea, fetch_first_ea, fetch_next_ea );
type iv_type is (reset_iv, latch_iv, swi_iv, xirq_iv, irq_iv );
type count_type is (reset_count, latch_count, inc_count );
type left_type is (acca_left, accb_left, accd_left, md_left, ix_left, iy_left, pc_left, sp_left, ea_left );
type right_type is (md_right, zero_right, one_right, accb_right, pre_right, ea_right, sexea_right );
type alu_type is (alu_add8, alu_sub8, alu_add16, alu_sub16, alu_adc, alu_sbc,
alu_and, alu_ora, alu_eor,
alu_tst, alu_inc, alu_dec, alu_clr, alu_neg, alu_com,
alu_inc16, alu_dec16,
alu_lsr16, alu_lsl16,
alu_ror8, alu_rol8, alu_rol16,
alu_asr8, alu_asl8, alu_lsr8,
alu_sei, alu_cli, alu_sec, alu_clc, alu_sev, alu_clv,
alu_sex, alu_clx, alu_tpa, alu_tap,
alu_ld8, alu_st8, alu_ld16, alu_st16, alu_nop, alu_daa,
alu_bset, alu_bclr );
 
signal op_code: std_logic_vector(7 downto 0);
signal pre_byte: std_logic_vector(7 downto 0);
signal acca: std_logic_vector(7 downto 0);
signal accb: std_logic_vector(7 downto 0);
signal cc: std_logic_vector(7 downto 0);
signal cc_out: std_logic_vector(7 downto 0);
signal xreg: std_logic_vector(15 downto 0);
signal yreg: std_logic_vector(15 downto 0);
signal sp: std_logic_vector(15 downto 0);
signal ea: std_logic_vector(15 downto 0);
signal pc: std_logic_vector(15 downto 0);
signal md: std_logic_vector(15 downto 0);
signal left: std_logic_vector(15 downto 0);
signal right: std_logic_vector(15 downto 0);
signal out_alu: std_logic_vector(15 downto 0);
signal iv: std_logic_vector(1 downto 0);
signal ea_bit: std_logic;
signal count: std_logic_vector(4 downto 0);
 
signal state: state_type;
signal next_state: state_type;
signal pc_ctrl: pc_type;
signal ea_ctrl: ea_type;
signal op_ctrl: op_type;
signal pre_ctrl: pre_type;
signal md_ctrl: md_type;
signal acca_ctrl: acca_type;
signal accb_ctrl: accb_type;
signal ix_ctrl: ix_type;
signal iy_ctrl: iy_type;
signal cc_ctrl: cc_type;
signal sp_ctrl: sp_type;
signal iv_ctrl: iv_type;
signal left_ctrl: left_type;
signal right_ctrl: right_type;
signal alu_ctrl: alu_type;
signal addr_ctrl: addr_type;
signal dout_ctrl: dout_type;
signal count_ctrl: count_type;
 
 
begin
 
--------------------------------
--
-- Accumulator A
--
--------------------------------
acca_reg : process( clk, acca_ctrl, out_alu, acca, data_in )
begin
if clk'event and clk = '0' then
case acca_ctrl is
when reset_acca =>
acca <= "00000000";
when load_acca =>
acca <= out_alu(7 downto 0);
when load_hi_acca =>
acca <= out_alu(15 downto 8);
when pull_acca =>
acca <= data_in;
when others =>
-- when latch_acca =>
acca <= acca;
end case;
end if;
end process;
 
--------------------------------
--
-- Accumulator B
--
--------------------------------
accb_reg : process( clk, accb_ctrl, out_alu, accb, data_in )
begin
if clk'event and clk = '0' then
case accb_ctrl is
when reset_accb =>
accb <= "00000000";
when load_accb =>
accb <= out_alu(7 downto 0);
when pull_accb =>
accb <= data_in;
when others =>
-- when latch_accb =>
accb <= accb;
end case;
end if;
end process;
 
----------------------------------
--
-- Condition Codes
--
----------------------------------
 
cc_reg: process( clk, cc_ctrl, cc_out, cc, data_in )
begin
if clk'event and clk = '0' then
case cc_ctrl is
when reset_cc =>
cc <= "11000000";
when load_cc =>
cc <= cc_out;
when pull_cc =>
cc <= data_in;
when others =>
-- when latch_cc =>
cc <= cc;
end case;
end if;
end process;
 
--------------------------------
--
-- X Index register
--
--------------------------------
ix_reg : process( clk, ix_ctrl, out_alu, xreg, data_in )
begin
if clk'event and clk = '0' then
case ix_ctrl is
when reset_ix =>
xreg <= "0000000000000000";
when load_ix =>
xreg <= out_alu(15 downto 0);
when pull_hi_ix =>
xreg(15 downto 8) <= data_in;
when pull_lo_ix =>
xreg(7 downto 0) <= data_in;
when others =>
-- when latch_ix =>
xreg <= xreg;
end case;
end if;
end process;
 
--------------------------------
--
-- Y Index register
--
--------------------------------
iy_reg : process( clk, iy_ctrl, out_alu, yreg, data_in )
begin
if clk'event and clk = '0' then
case iy_ctrl is
when reset_iy =>
yreg <= "0000000000000000";
when load_iy =>
yreg <= out_alu(15 downto 0);
when pull_hi_iy =>
yreg(15 downto 8) <= data_in;
when pull_lo_iy =>
yreg(7 downto 0) <= data_in;
when others =>
-- when latch_iy =>
yreg <= yreg;
end case;
end if;
end process;
 
--------------------------------
--
-- stack pointer
--
--------------------------------
sp_reg : process( clk, sp_ctrl, out_alu )
begin
if clk'event and clk = '0' then
case sp_ctrl is
when reset_sp =>
sp <= "0000000000000000";
when load_sp =>
sp <= out_alu(15 downto 0);
when others =>
-- when latch_sp =>
sp <= sp;
end case;
end if;
end process;
 
----------------------------------
--
-- Program Counter Control
--
----------------------------------
 
pc_reg: process( clk, pc_ctrl, pc, out_alu, data_in )
begin
if clk'event and clk = '0' then
case pc_ctrl is
when reset_pc =>
pc <= "0000000000000000";
when load_pc =>
pc <= out_alu(15 downto 0);
when pull_lo_pc =>
pc(7 downto 0) <= data_in;
when pull_hi_pc =>
pc(15 downto 8) <= data_in;
when others =>
-- when latch_pc =>
pc <= pc;
end case;
end if;
end process;
 
----------------------------------
--
-- Effective Address Control
--
----------------------------------
 
ea_reg: process( clk, ea_ctrl, ea, out_alu, data_in )
begin
 
if clk'event and clk = '0' then
case ea_ctrl is
when reset_ea =>
ea <= "0000000000000000";
when fetch_first_ea =>
ea(7 downto 0) <= data_in;
ea(15 downto 8) <= "00000000";
when fetch_next_ea =>
ea(15 downto 8) <= ea(7 downto 0);
ea(7 downto 0) <= data_in;
when load_ea =>
ea <= out_alu(15 downto 0);
when others =>
-- when latch_ea =>
ea <= ea;
end case;
end if;
end process;
 
--------------------------------
--
-- Memory Data
--
--------------------------------
md_reg : process( clk, md_ctrl, out_alu, data_in, md )
begin
if clk'event and clk = '0' then
case md_ctrl is
when reset_md =>
md <= "0000000000000000";
when load_md =>
md <= out_alu(15 downto 0);
when fetch_first_md =>
md(15 downto 8) <= "00000000";
md(7 downto 0) <= data_in;
when fetch_next_md =>
md(15 downto 8) <= md(7 downto 0);
md(7 downto 0) <= data_in;
when shiftl_md =>
md(15 downto 1) <= md(14 downto 0);
md(0) <= '0';
when others =>
-- when latch_md =>
md <= md;
end case;
end if;
end process;
 
----------------------------------
--
-- interrupt vector
--
----------------------------------
 
iv_reg: process( clk, iv_ctrl )
begin
if clk'event and clk = '0' then
case iv_ctrl is
when reset_iv =>
iv <= "11";
when xirq_iv =>
iv <= "10";
when swi_iv =>
iv <= "01";
when irq_iv =>
iv <= "00";
when others =>
iv <= iv;
end case;
end if;
end process;
 
----------------------------------
--
-- op code register
--
----------------------------------
 
op_reg: process( clk, data_in, op_ctrl, op_code )
begin
if clk'event and clk = '0' then
case op_ctrl is
when reset_op =>
op_code <= "00000001";
when fetch_op =>
op_code <= data_in;
when others =>
-- when latch_op =>
op_code <= op_code;
end case;
end if;
end process;
 
----------------------------------
--
-- pre byte register
--
----------------------------------
 
pre_reg: process( clk, pre_ctrl, data_in, pre_byte )
begin
if clk'event and clk = '0' then
case pre_ctrl is
when reset_pre =>
pre_byte <= "00000000";
when fetch_pre =>
pre_byte <= data_in;
when others =>
-- when latch_op =>
pre_byte <= pre_byte;
end case;
end if;
end process;
 
----------------------------------
--
-- counter
--
----------------------------------
 
count_reg: process( clk, count_ctrl, count )
begin
if clk'event and clk = '0' then
case count_ctrl is
when reset_count =>
count <= "00000";
when inc_count =>
count <= count + "00001";
when others =>
-- when latch_count =>
count <= count;
end case;
end if;
end process;
 
----------------------------------
--
-- Address output multiplexer
--
----------------------------------
 
addr_mux: process( clk, addr_ctrl, pc, ea, sp, iv )
begin
case addr_ctrl is
when idle_ad =>
address <= "1111111111111111";
vma <= '0';
rw <= '1';
when fetch_ad =>
address <= pc;
vma <= '1';
rw <= '1';
when read_ad =>
address <= ea;
vma <= '1';
rw <= '1';
when write_ad =>
address <= ea;
vma <= '1';
rw <= '0';
when push_ad =>
address <= sp;
vma <= '1';
rw <= '0';
when pull_ad =>
address <= sp;
vma <= '1';
rw <= '1';
when int_hi_ad =>
address <= "1111111111111" & iv & "0";
vma <= '1';
rw <= '1';
when int_lo_ad =>
address <= "1111111111111" & iv & "1";
vma <= '1';
rw <= '1';
when others =>
address <= "1111111111111111";
vma <= '0';
rw <= '1';
end case;
end process;
 
--------------------------------
--
-- Data Bus output
--
--------------------------------
dout_mux : process( clk, dout_ctrl, md, acca, accb, xreg, yreg, pc, cc )
begin
case dout_ctrl is
when acca_dout => -- accumulator a
data_out <= acca;
when accb_dout => -- accumulator b
data_out <= accb;
when cc_dout => -- condition codes
data_out <= cc;
when ix_lo_dout => -- X index reg
data_out <= xreg(7 downto 0);
when ix_hi_dout => -- X index reg
data_out <= xreg(15 downto 8);
when iy_lo_dout => -- Y index reg
data_out <= yreg(7 downto 0);
when iy_hi_dout => -- Y index reg
data_out <= yreg(15 downto 8);
when md_lo_dout => -- memory data (ALU)
data_out <= md(7 downto 0);
when md_hi_dout => -- memory data (ALU)
data_out <= md(15 downto 8);
when pc_lo_dout => -- low order pc
data_out <= pc(7 downto 0);
when pc_hi_dout => -- high order pc
data_out <= pc(15 downto 8);
when others =>
data_out <= "00000000";
end case;
end process;
 
----------------------------------
--
-- ea bit mutiplexer (used by multiply)
--
----------------------------------
 
ea_bit_mux: process( count, ea )
begin
case count(3 downto 0) is
when "0000" =>
ea_bit <= ea(0);
when "0001" =>
ea_bit <= ea(1);
when "0010" =>
ea_bit <= ea(2);
when "0011" =>
ea_bit <= ea(3);
when "0100" =>
ea_bit <= ea(4);
when "0101" =>
ea_bit <= ea(5);
when "0110" =>
ea_bit <= ea(6);
when "0111" =>
ea_bit <= ea(7);
when "1000" =>
ea_bit <= ea(8);
when "1001" =>
ea_bit <= ea(9);
when "1010" =>
ea_bit <= ea(10);
when "1011" =>
ea_bit <= ea(11);
when "1100" =>
ea_bit <= ea(12);
when "1101" =>
ea_bit <= ea(13);
when "1110" =>
ea_bit <= ea(14);
when "1111" =>
ea_bit <= ea(15);
when others =>
null;
end case;
end process;
 
----------------------------------
--
-- Left Mux
--
----------------------------------
 
left_mux: process( left_ctrl, acca, accb, xreg, yreg, sp, pc, ea, md )
begin
case left_ctrl is
when acca_left =>
left(15 downto 8) <= "00000000";
left(7 downto 0) <= acca;
when accb_left =>
left(15 downto 8) <= "00000000";
left(7 downto 0) <= accb;
when accd_left =>
left(15 downto 8) <= acca;
left(7 downto 0) <= accb;
when md_left =>
left <= md;
when ix_left =>
left <= xreg;
when iy_left =>
left <= yreg;
when sp_left =>
left <= sp;
when pc_left =>
left <= pc;
when others =>
-- when ea_left =>
left <= ea;
end case;
end process;
 
----------------------------------
--
-- Right Mux
--
----------------------------------
 
right_mux: process( right_ctrl, data_in, md, accb, pre_byte, ea )
begin
case right_ctrl is
when zero_right =>
right <= "0000000000000000";
when one_right =>
right <= "0000000000000001";
when accb_right =>
right <= "00000000" & accb; -- for abx / aby instructions
when pre_right =>
right <= "00000000" & pre_byte; -- prebyte register doubles as bit mask
when ea_right =>
right <= ea;
when sexea_right =>
if ea(7) = '0' then
right <= "00000000" & ea(7 downto 0);
else
right <= "11111111" & ea(7 downto 0);
end if;
when others =>
-- when md_right =>
right <= md;
end case;
end process;
 
----------------------------------
--
-- Arithmetic Logic Unit
--
----------------------------------
 
alu_logic: process( alu_ctrl, cc, left, right, out_alu, cc_out )
variable valid_lo, valid_hi : boolean;
variable carry_in : std_logic;
variable daa_reg : std_logic_vector(7 downto 0);
begin
 
case alu_ctrl is
when alu_adc | alu_sbc |
alu_rol8 | alu_ror8 | alu_rol16 =>
carry_in := cc(CBIT);
when others =>
carry_in := '0';
end case;
 
valid_lo := left(3 downto 0) <= 9;
valid_hi := left(7 downto 4) <= 9;
 
if (cc(CBIT) = '0') then
if( cc(HBIT) = '1' ) then
if valid_hi then
daa_reg := "00000110";
else
daa_reg := "01100110";
end if;
else
if valid_lo then
if valid_hi then
daa_reg := "00000000";
else
daa_reg := "01100000";
end if;
else
if( left(7 downto 4) <= 8 ) then
daa_reg := "00000110";
else
daa_reg := "01100110";
end if;
end if;
end if;
else
if ( cc(HBIT) = '1' )then
daa_reg := "01100110";
else
if valid_lo then
daa_reg := "01100000";
else
daa_reg := "01100110";
end if;
end if;
end if;
 
case alu_ctrl is
when alu_add8 | alu_adc | alu_inc |
alu_add16 | alu_inc16 =>
out_alu <= left + right + ("000000000000000" & carry_in);
when alu_sub8 | alu_sbc | alu_dec |
alu_sub16 | alu_dec16 =>
out_alu <= left - right - ("000000000000000" & carry_in);
when alu_and =>
out_alu <= left and right; -- and/bit
when alu_bclr =>
out_alu <= left and (not right); -- bclr
when alu_ora | alu_bset =>
out_alu <= left or right; -- or
when alu_eor =>
out_alu <= left xor right; -- eor/xor
when alu_lsl16 | alu_asl8 | alu_rol8 | alu_rol16 =>
out_alu <= left(14 downto 0) & carry_in; -- rol8/rol16/asl8/lsl16
when alu_lsr16 | alu_lsr8 =>
out_alu <= carry_in & left(15 downto 1); -- lsr
when alu_ror8 =>
out_alu <= "00000000" & carry_in & left(7 downto 1); -- ror
when alu_asr8 =>
out_alu <= "00000000" & left(7) & left(7 downto 1); -- asr
when alu_neg =>
out_alu <= right - left; -- neg (right=0)
when alu_com =>
out_alu <= not left;
when alu_clr | alu_ld8 | alu_ld16 =>
out_alu <= right; -- clr, ld
when alu_st8 | alu_st16 =>
out_alu <= left;
when alu_daa =>
out_alu <= left + ("00000000" & daa_reg);
when alu_tpa =>
out_alu <= "00000000" & cc;
when others =>
out_alu <= left; -- nop
end case;
 
--
-- carry bit
--
case alu_ctrl is
when alu_add8 | alu_adc =>
cc_out(CBIT) <= (left(7) and right(7)) or
(left(7) and not out_alu(7)) or
(right(7) and not out_alu(7));
when alu_sub8 | alu_sbc =>
cc_out(CBIT) <= ((not left(7)) and right(7)) or
((not left(7)) and out_alu(7)) or
(right(7) and out_alu(7));
when alu_add16 =>
cc_out(CBIT) <= (left(15) and right(15)) or
(left(15) and not out_alu(15)) or
(right(15) and not out_alu(15));
when alu_sub16 =>
cc_out(CBIT) <= ((not left(15)) and right(15)) or
((not left(15)) and out_alu(15)) or
(right(15) and out_alu(15));
when alu_ror8 | alu_lsr16 | alu_lsr8 | alu_asr8 =>
cc_out(CBIT) <= left(0);
when alu_rol8 | alu_asl8 =>
cc_out(CBIT) <= left(7);
when alu_lsl16 | alu_rol16 =>
cc_out(CBIT) <= left(15);
when alu_com =>
cc_out(CBIT) <= '1';
when alu_neg | alu_clr =>
cc_out(CBIT) <= out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0);
when alu_daa =>
if ( daa_reg(7 downto 4) = "0110" ) then
cc_out(CBIT) <= '1';
else
cc_out(CBIT) <= '0';
end if;
when alu_sec =>
cc_out(CBIT) <= '1';
when alu_clc =>
cc_out(CBIT) <= '0';
when alu_tap =>
cc_out(CBIT) <= left(CBIT);
when others => -- carry is not affected by cpx
cc_out(CBIT) <= cc(CBIT);
end case;
--
-- Zero flag
--
case alu_ctrl is
when alu_add8 | alu_sub8 |
alu_adc | alu_sbc |
alu_and | alu_ora | alu_eor |
alu_inc | alu_dec |
alu_neg | alu_com | alu_clr |
alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 |
alu_ld8 | alu_st8 |
alu_bset | alu_bclr =>
cc_out(ZBIT) <= not( out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0) );
when alu_add16 | alu_sub16 |
alu_lsl16 | alu_lsr16 |
alu_inc16 | alu_dec16 |
alu_ld16 | alu_st16 =>
cc_out(ZBIT) <= not( out_alu(15) or out_alu(14) or out_alu(13) or out_alu(12) or
out_alu(11) or out_alu(10) or out_alu(9) or out_alu(8) or
out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0) );
when alu_tap =>
cc_out(ZBIT) <= left(ZBIT);
when others =>
cc_out(ZBIT) <= cc(ZBIT);
end case;
 
--
-- negative flag
--
case alu_ctrl is
when alu_add8 | alu_sub8 |
alu_adc | alu_sbc |
alu_and | alu_ora | alu_eor |
alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 |
alu_inc | alu_dec | alu_neg | alu_com | alu_clr |
alu_ld8 | alu_st8 |
alu_bset | alu_bclr =>
cc_out(NBIT) <= out_alu(7);
when alu_add16 | alu_sub16 |
alu_lsl16 | alu_lsr16 |
alu_ld16 | alu_st16 =>
cc_out(NBIT) <= out_alu(15);
when alu_tap =>
cc_out(NBIT) <= left(NBIT);
when others =>
cc_out(NBIT) <= cc(NBIT);
end case;
 
--
-- Interrupt mask flag
--
case alu_ctrl is
when alu_sei =>
cc_out(IBIT) <= '1'; -- set interrupt mask
when alu_cli =>
cc_out(IBIT) <= '0'; -- clear interrupt mask
when alu_tap =>
cc_out(IBIT) <= left(IBIT);
when others =>
cc_out(IBIT) <= cc(IBIT); -- interrupt mask
end case;
 
--
-- Half Carry flag
--
case alu_ctrl is
when alu_add8 | alu_adc =>
cc_out(HBIT) <= (left(3) and right(3)) or
(right(3) and not out_alu(3)) or
(left(3) and not out_alu(3));
when alu_tap =>
cc_out(HBIT) <= left(HBIT);
when others =>
cc_out(HBIT) <= cc(HBIT);
end case;
 
--
-- Overflow flag
--
case alu_ctrl is
when alu_add8 | alu_adc =>
cc_out(VBIT) <= (left(7) and right(7) and (not out_alu(7))) or
((not left(7)) and (not right(7)) and out_alu(7));
when alu_sub8 | alu_sbc =>
cc_out(VBIT) <= (left(7) and (not right(7)) and (not out_alu(7))) or
((not left(7)) and right(7) and out_alu(7));
when alu_add16 =>
cc_out(VBIT) <= (left(15) and right(15) and (not out_alu(15))) or
((not left(15)) and (not right(15)) and out_alu(15));
when alu_sub16 =>
cc_out(VBIT) <= (left(15) and (not right(15)) and (not out_alu(15))) or
((not left(15)) and right(15) and out_alu(15));
when alu_inc =>
cc_out(VBIT) <= ((not left(7)) and left(6) and left(5) and left(4) and
left(3) and left(2) and left(1) and left(0));
when alu_dec | alu_neg =>
cc_out(VBIT) <= (left(7) and (not left(6)) and (not left(5)) and (not left(4)) and
(not left(3)) and (not left(2)) and (not left(1)) and (not left(0)));
when alu_asr8 =>
cc_out(VBIT) <= left(0) xor left(7);
when alu_lsr8 | alu_lsr16 =>
cc_out(VBIT) <= left(0);
when alu_ror8 =>
cc_out(VBIT) <= left(0) xor cc(CBIT);
when alu_lsl16 =>
cc_out(VBIT) <= left(15) xor left(14);
when alu_rol8 | alu_asl8 =>
cc_out(VBIT) <= left(7) xor left(6);
when alu_tap =>
cc_out(VBIT) <= left(VBIT);
when alu_and | alu_ora | alu_eor | alu_com |
alu_st8 | alu_st16 | alu_ld8 | alu_ld16 |
alu_bset | alu_bclr |
alu_clv =>
cc_out(VBIT) <= '0';
when alu_sev =>
cc_out(VBIT) <= '1';
when others =>
cc_out(VBIT) <= cc(VBIT);
end case;
 
case alu_ctrl is
when alu_sex =>
cc_out(XBIT) <= '1'; -- set interrupt mask
when alu_clx =>
cc_out(XBIT) <= '0'; -- clear interrupt mask
when alu_tap =>
cc_out(XBIT) <= cc(XBIT) and left(XBIT);
when others =>
cc_out(XBIT) <= cc(XBIT) and left(XBIT);
end case;
 
case alu_ctrl is
when alu_tap =>
cc_out(SBIT) <= left(SBIT);
when others =>
cc_out(SBIT) <= cc(SBIT);
end case;
 
test_alu <= out_alu;
test_cc <= cc_out;
end process;
 
 
------------------------------------
--
-- state sequencer
--
------------------------------------
state_logic: process( state, op_code, pre_byte, cc, ea, md, irq, xirq, ea_bit, count )
begin
case state is
when reset_state => -- released from reset
-- reset the registers
op_ctrl <= reset_op;
pre_ctrl <= reset_pre;
acca_ctrl <= reset_acca;
accb_ctrl <= reset_accb;
ix_ctrl <= reset_ix;
iy_ctrl <= reset_iy;
sp_ctrl <= reset_sp;
pc_ctrl <= reset_pc;
ea_ctrl <= reset_ea;
md_ctrl <= reset_md;
iv_ctrl <= reset_iv;
sp_ctrl <= reset_sp;
count_ctrl <= reset_count;
-- idle the ALU
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= reset_cc;
-- idle the bus
dout_ctrl <= md_lo_dout;
addr_ctrl <= idle_ad;
next_state <= vect_hi_state;
 
--
-- Jump via interrupt vector
-- iv holds interrupt type
-- fetch PC hi from vector location
--
when vect_hi_state =>
-- default the registers
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
ea_ctrl <= latch_ea;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
-- idle the ALU
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- fetch pc low interrupt vector
pc_ctrl <= pull_hi_pc;
addr_ctrl <= int_hi_ad;
dout_ctrl <= pc_hi_dout;
next_state <= vect_lo_state;
--
-- jump via interrupt vector
-- iv holds vector type
-- fetch PC lo from vector location
--
when vect_lo_state =>
-- default the registers
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
ea_ctrl <= latch_ea;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
-- idle the ALU
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- fetch the vector low byte
pc_ctrl <= pull_lo_pc;
addr_ctrl <= int_lo_ad;
dout_ctrl <= pc_lo_dout;
next_state <= fetch_state;
 
--
-- Here to fetch an instruction
-- PC points to opcode
-- Should service interrupt requests at this point
-- either from the timer
-- or from the external input.
--
when fetch_state =>
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
-- fetch the op code
op_ctrl <= fetch_op;
pre_ctrl <= fetch_pre;
ea_ctrl <= reset_ea;
addr_ctrl <= fetch_ad;
dout_ctrl <= md_lo_dout;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
-- service non maskable interrupts
if (xirq = '1') and (cc(XBIT) = '0') then
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
pc_ctrl <= latch_pc;
next_state <= int_pcl_state;
-- service maskable interrupts
else
--
-- IRQ is level sensitive
--
if (irq = '1') and (cc(IBIT) = '0') then
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
pc_ctrl <= latch_pc;
next_state <= int_pcl_state;
else
-- Advance the PC to fetch next instruction byte
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
next_state <= decode_state;
end if;
end if;
--
-- Here to decode instruction
-- and fetch next byte of intruction
-- whether it be necessary or not
--
when decode_state =>
-- fetch first byte of address or immediate data
addr_ctrl <= fetch_ad;
dout_ctrl <= md_lo_dout;
pre_ctrl <= latch_pre;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
case op_code(7 downto 4) is
when "0000" =>
md_ctrl <= reset_md;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
op_ctrl <= latch_op;
case op_code(3 downto 0) is
when "0000" => -- test -- spin PC
left_ctrl <= accd_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ea_ctrl <= reset_ea;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
next_state <= spin_state;
when "0001" => -- nop
left_ctrl <= accd_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ea_ctrl <= reset_ea;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
next_state <= fetch_state;
when "0010" => -- idiv
-- transfer IX to ea
left_ctrl <= ix_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
ea_ctrl <= load_ea;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
next_state <= idiv_state;
when "0011" => -- fdiv
left_ctrl <= ix_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
ea_ctrl <= load_ea;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= reset_ix;
iy_ctrl <= latch_iy;
next_state <= div1_state;
when "0100" => -- lsrd
left_ctrl <= accd_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_lsr16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
ea_ctrl <= reset_ea;
next_state <= fetch_state;
when "0101" => -- lsld
left_ctrl <= accd_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_lsl16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
ea_ctrl <= reset_ea;
next_state <= fetch_state;
when "0110" => -- tap
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_tap;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
ea_ctrl <= reset_ea;
next_state <= fetch_state;
when "0111" => -- tpa
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_tpa;
cc_ctrl <= latch_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
ea_ctrl <= reset_ea;
next_state <= fetch_state;
when "1000" => -- inx
if pre_byte = "00011000" then
left_ctrl <= iy_left;
ix_ctrl <= latch_ix;
iy_ctrl <= load_iy;
else
left_ctrl <= ix_left;
ix_ctrl <= load_ix;
iy_ctrl <= latch_iy;
end if;
ea_ctrl <= reset_ea;
right_ctrl <= one_right;
alu_ctrl <= alu_inc16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
next_state <= fetch_state;
when "1001" => -- dex
if pre_byte = "00011000" then
left_ctrl <= iy_left;
ix_ctrl <= latch_ix;
iy_ctrl <= load_iy;
else
left_ctrl <= ix_left;
ix_ctrl <= load_ix;
iy_ctrl <= latch_iy;
end if;
ea_ctrl <= reset_ea;
right_ctrl <= one_right;
alu_ctrl <= alu_dec16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= load_ix;
next_state <= fetch_state;
when "1010" => -- clv
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_clv;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
ea_ctrl <= reset_ea;
next_state <= fetch_state;
when "1011" => -- sev
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_sev;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
ea_ctrl <= reset_ea;
next_state <= fetch_state;
when "1100" => -- clc
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_clc;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
ea_ctrl <= reset_ea;
next_state <= fetch_state;
when "1101" => -- sec
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_sec;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
ea_ctrl <= reset_ea;
next_state <= fetch_state;
when "1110" => -- cli
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_cli;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
ea_ctrl <= reset_ea;
next_state <= fetch_state;
when "1111" => -- sei
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_sei;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
ea_ctrl <= reset_ea;
next_state <= fetch_state;
when others =>
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
ea_ctrl <= reset_ea;
next_state <= fetch_state;
end case;
-- acca / accb inherent instructions
when "0001" =>
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
case op_code(3 downto 0) is
when "0000" => -- sba
op_ctrl <= latch_op;
left_ctrl <= acca_left;
right_ctrl <= accb_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= latch_pc;
next_state <= fetch_state;
when "0001" => -- cba
op_ctrl <= latch_op;
left_ctrl <= acca_left;
right_ctrl <= accb_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= latch_pc;
next_state <= fetch_state;
when "0010" => -- brset direct
op_ctrl <= latch_op;
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= load_pc;
next_state <= direct_state;
when "0011" => -- brclr direct
op_ctrl <= latch_op;
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= load_pc;
next_state <= direct_state;
when "0100" => -- bset direct
op_ctrl <= latch_op;
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= load_pc;
next_state <= direct_state;
when "0101" => -- bclr direct
op_ctrl <= latch_op;
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= load_pc;
next_state <= direct_state;
when "0110" => -- tab
op_ctrl <= latch_op;
left_ctrl <= acca_left;
right_ctrl <= accb_right;
alu_ctrl <= alu_st8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
pc_ctrl <= latch_pc;
next_state <= fetch_state;
when "0111" => -- tba
op_ctrl <= latch_op;
left_ctrl <= acca_left;
right_ctrl <= accb_right;
alu_ctrl <= alu_ld8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= latch_pc;
next_state <= fetch_state;
when "1000" => -- indexed y prebyte
op_ctrl <= fetch_op;
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= load_pc;
next_state <= decode_state;
when "1001" => -- daa
op_ctrl <= latch_op;
left_ctrl <= acca_left;
right_ctrl <= accb_right;
alu_ctrl <= alu_daa;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= latch_pc;
next_state <= fetch_state;
when "1010" => -- CPD & CPY ff,X prebyte
op_ctrl <= fetch_op;
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= load_pc;
next_state <= decode_state;
when "1011" => -- aba
op_ctrl <= latch_op;
left_ctrl <= acca_left;
right_ctrl <= accb_right;
alu_ctrl <= alu_add8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= latch_pc;
next_state <= fetch_state;
when "1100" => -- bset indexed
op_ctrl <= latch_op;
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= load_pc;
next_state <= indexed_state;
when "1101" => -- bclr indexed
op_ctrl <= latch_op;
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= load_pc;
next_state <= indexed_state;
when "1110" => -- brset indexed
op_ctrl <= latch_op;
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= load_pc;
next_state <= indexed_state;
when "1111" => -- brclr indexed
op_ctrl <= latch_op;
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= load_pc;
next_state <= indexed_state;
when others =>
op_ctrl <= latch_op;
left_ctrl <= acca_left;
right_ctrl <= accb_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= latch_pc;
next_state <= fetch_state;
end case;
when "0010" => -- branch conditional
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
case op_code(3 downto 0) is
when "0000" => -- bra
next_state <= branch_state;
when "0001" => -- brn
next_state <= fetch_state;
when "0010" => -- bhi
if (cc(CBIT) or cc(ZBIT)) = '0' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "0011" => -- bls
if (cc(CBIT) or cc(ZBIT)) = '1' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "0100" => -- bcc/bhs
if cc(CBIT) = '0' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "0101" => -- bcs/blo
if cc(CBIT) = '1' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "0110" => -- bne
if cc(ZBIT) = '0' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "0111" => -- beq
if cc(ZBIT) = '1' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "1000" => -- bvc
if cc(VBIT) = '0' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "1001" => -- bvs
if cc(VBIT) = '1' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "1010" => -- bpl
if cc(NBIT) = '0' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "1011" => -- bmi
if cc(NBIT) = '1' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "1100" => -- bge
if (cc(NBIT) xor cc(VBIT)) = '0' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "1101" => -- blt
if (cc(NBIT) xor cc(VBIT)) = '1' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "1110" => -- bgt
if (cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '0' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "1111" => -- ble
if (cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '1' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when others =>
next_state <= fetch_state;
end case;
--
-- Single byte stack operators
-- Do not advance PC
--
when "0011" =>
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= latch_pc;
case op_code(3 downto 0) is
when "0000" => -- tsx / tsy
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
if pre_byte = "00011000" then
ix_ctrl <= latch_ix;
iy_ctrl <= load_iy;
else
ix_ctrl <= load_ix;
iy_ctrl <= latch_iy;
end if;
next_state <= fetch_state;
when "0001" => -- ins
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= load_sp;
next_state <= fetch_state;
when "0010" => -- pula
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= load_sp;
next_state <= pula_state;
when "0011" => -- pulb
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= load_sp;
next_state <= pulb_state;
when "0100" => -- des
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= load_sp;
next_state <= fetch_state;
when "0101" => -- txs / tys
if pre_byte = "00011000" then
left_ctrl <= iy_left;
else
left_ctrl <= ix_left;
end if;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= load_sp;
next_state <= fetch_state;
when "0110" => -- psha
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
next_state <= psha_state;
when "0111" => -- pshb
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
next_state <= pshb_state;
when "1000" => -- pulx
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= load_sp;
next_state <= pulx_hi_state;
when "1001" => -- rts
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= load_sp;
next_state <= rts_hi_state;
when "1010" => -- abx / aby
if pre_byte = "00011000" then
left_ctrl <= iy_left;
ix_ctrl <= latch_ix;
iy_ctrl <= load_iy;
else
left_ctrl <= ix_left;
ix_ctrl <= load_ix;
iy_ctrl <= latch_iy;
end if;
right_ctrl <= accb_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
next_state <= fetch_state;
when "1011" => -- rti
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= load_sp;
next_state <= rti_cc_state;
when "1100" => -- pshx
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
next_state <= pshx_lo_state;
when "1101" => -- mul
left_ctrl <= acca_left;
right_ctrl <= accb_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
next_state <= mul_state;
when "1110" => -- wai
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
next_state <= int_pcl_state;
when "1111" => -- swi
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
next_state <= int_pcl_state;
when others =>
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
next_state <= fetch_state;
end case;
--
-- Accumulator A Single operand
-- source = Acc A dest = Acc A
-- Do not advance PC
--
when "0100" => -- acca single op
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
op_ctrl <= latch_op;
accb_ctrl <= latch_accb;
pc_ctrl <= latch_pc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
left_ctrl <= acca_left;
case op_code(3 downto 0) is
when "0000" => -- neg
right_ctrl <= zero_right;
alu_ctrl <= alu_neg;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "0011" => -- com
right_ctrl <= zero_right;
alu_ctrl <= alu_com;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "0100" => -- lsr
right_ctrl <= zero_right;
alu_ctrl <= alu_lsr8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "0110" => -- ror
right_ctrl <= zero_right;
alu_ctrl <= alu_ror8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "0111" => -- asr
right_ctrl <= zero_right;
alu_ctrl <= alu_asr8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1000" => -- asl
right_ctrl <= zero_right;
alu_ctrl <= alu_asl8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1001" => -- rol
right_ctrl <= zero_right;
alu_ctrl <= alu_rol8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1010" => -- dec
right_ctrl <= one_right;
alu_ctrl <= alu_dec;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1011" => -- undefined
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
acca_ctrl <= latch_acca;
cc_ctrl <= latch_cc;
when "1100" => -- inc
right_ctrl <= one_right;
alu_ctrl <= alu_inc;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1101" => -- tst
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
acca_ctrl <= latch_acca;
cc_ctrl <= load_cc;
when "1110" => -- jmp
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
acca_ctrl <= latch_acca;
cc_ctrl <= latch_cc;
when "1111" => -- clr
right_ctrl <= zero_right;
alu_ctrl <= alu_ld8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when others =>
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
acca_ctrl <= latch_acca;
cc_ctrl <= latch_cc;
end case;
next_state <= fetch_state;
--
-- single operand acc b
-- Do not advance PC
--
when "0101" =>
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
pc_ctrl <= latch_pc;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
left_ctrl <= accb_left;
case op_code(3 downto 0) is
when "0000" => -- neg
right_ctrl <= zero_right;
alu_ctrl <= alu_neg;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "0011" => -- com
right_ctrl <= zero_right;
alu_ctrl <= alu_com;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "0100" => -- lsr
right_ctrl <= zero_right;
alu_ctrl <= alu_lsr8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "0110" => -- ror
right_ctrl <= zero_right;
alu_ctrl <= alu_ror8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "0111" => -- asr
right_ctrl <= zero_right;
alu_ctrl <= alu_asr8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1000" => -- asl
right_ctrl <= zero_right;
alu_ctrl <= alu_asl8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1001" => -- rol
right_ctrl <= zero_right;
alu_ctrl <= alu_rol8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1010" => -- dec
right_ctrl <= one_right;
alu_ctrl <= alu_dec;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1011" => -- undefined
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
when "1100" => -- inc
right_ctrl <= one_right;
alu_ctrl <= alu_inc;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1101" => -- tst
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
accb_ctrl <= latch_accb;
cc_ctrl <= load_cc;
when "1110" => -- jmp
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
when "1111" => -- clr
right_ctrl <= zero_right;
alu_ctrl <= alu_ld8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when others =>
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
end case;
next_state <= fetch_state;
--
-- Single operand indexed
-- Two byte instruction so advance PC
-- EA should hold index offset
--
when "0110" => -- indexed single op
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
next_state <= indexed_state;
--
-- Single operand extended addressing
-- three byte instruction so advance the PC
-- Low order EA holds high order address
--
when "0111" => -- extended single op
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
next_state <= extended_state;
 
when "1000" => -- acca immediate
ea_ctrl <= fetch_first_ea;
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
cc_ctrl <= latch_cc;
case op_code(3 downto 0) is
when "0011" | -- subd #
"1100" | -- cpx / cpy #
"1110" => -- lds #
-- increment the pc
md_ctrl <= fetch_first_md;
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
pc_ctrl <= load_pc;
next_state <= immediate16_state;
when "1101" => -- bsr
-- increment the pc
md_ctrl <= fetch_first_md;
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
pc_ctrl <= load_pc;
next_state <= bsr_state;
when "1111" => -- egdx /egdy
-- idle pc
left_ctrl <= accd_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
pc_ctrl <= latch_pc;
md_ctrl <= load_md;
next_state <= exchange1_state;
when others =>
md_ctrl <= fetch_first_md;
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
pc_ctrl <= load_pc;
next_state <= execute_state;
end case;
 
when "1001" => -- acca direct
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
case op_code(3 downto 0) is
when "0111" | -- staa direct
"1111" => -- sts direct
next_state <= execute_state;
when "1101" => -- jsr direct
next_state <= jsr_state;
when others =>
next_state <= direct_state;
end case;
 
when "1010" => -- acca indexed
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
next_state <= indexed_state;
 
when "1011" => -- acca extended
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
next_state <= extended_state;
 
when "1100" => -- accb immediate
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
case op_code(3 downto 0) is
when "0011" | -- addd #
"1100" | -- ldd #
"1110" => -- ldx #
op_ctrl <= latch_op;
next_state <= immediate16_state;
when "1101" => -- indexed Y pre-byte $CD
op_ctrl <= fetch_op;
next_state <= decode_state;
when others =>
op_ctrl <= latch_op;
next_state <= execute_state;
end case;
 
when "1101" => -- accb direct
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
case op_code(3 downto 0) is
when "0111" | -- stab direct
"1101" | -- std direct
"1111" => -- stx / sty direct
next_state <= execute_state;
when others =>
next_state <= direct_state;
end case;
 
when "1110" => -- accb indexed
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
next_state <= indexed_state;
 
when "1111" => -- accb extended
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
next_state <= extended_state;
 
when others =>
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
op_ctrl <= latch_op;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
-- idle the pc
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
pc_ctrl <= latch_pc;
next_state <= fetch_state;
end case;
 
when immediate16_state =>
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
pre_ctrl <= latch_pre;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
ea_ctrl <= latch_ea;
-- increment pc
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
-- fetch next immediate byte
md_ctrl <= fetch_next_md;
addr_ctrl <= fetch_ad;
dout_ctrl <= md_lo_dout;
next_state <= execute_state;
--
-- ea holds 8 bit index offet
-- calculate the effective memory address
-- using the alu
--
when indexed_state =>
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
-- calculate effective address from index reg
-- index offest is not sign extended
if (pre_byte = "00011000") or (pre_byte = "11001101") then
left_ctrl <= iy_left;
else
left_ctrl <= ix_left;
end if;
right_ctrl <= ea_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ea_ctrl <= load_ea;
-- idle the bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
-- work out next state
case op_code(7 downto 4) is
when "0110" => -- single op indexed
case op_code(3 downto 0) is
when "1011" => -- undefined
next_state <= fetch_state;
when "1110" => -- jmp
next_state <= jmp_state;
when others =>
next_state <= direct_state;
end case;
when "1010" => -- acca indexed
case op_code(3 downto 0) is
when "0111" | -- staa
"1111" => -- sts
next_state <= execute_state;
when "1101" => -- jsr
next_state <= jsr_state;
when others =>
next_state <= direct_state;
end case;
when "1110" => -- accb indexed
case op_code(3 downto 0) is
when "0111" | -- stab
"1101" | -- std
"1111" => -- stx / sty
next_state <= execute_state;
when others =>
next_state <= direct_state;
end case;
when others =>
next_state <= fetch_state;
end case;
--
-- ea holds the low byte of the absolute address
-- Move ea low byte into ea high byte
-- load new ea low byte to for absolute 16 bit address
-- advance the program counter
--
when extended_state => -- fetch ea low byte
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
-- increment pc
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
-- fetch next effective address bytes
ea_ctrl <= fetch_next_ea;
addr_ctrl <= fetch_ad;
dout_ctrl <= md_lo_dout;
-- work out the next state
case op_code(7 downto 4) is
when "0111" => -- single op extended
case op_code(3 downto 0) is
when "1011" => -- undefined
next_state <= fetch_state;
when "1110" => -- jmp
next_state <= jmp_state;
when others =>
next_state <= direct_state;
end case;
when "1011" => -- acca extended
case op_code(3 downto 0) is
when "0111" | -- staa extended
"1111" => -- sts
next_state <= execute_state;
when "1101" => -- jsr
next_state <= jsr_state;
when others =>
next_state <= direct_state;
end case;
when "1111" => -- accb extended
case op_code(3 downto 0) is
when "0111" | -- stab extended
"1101" | -- std
"1111" => -- stx / sty
next_state <= execute_state;
when others =>
next_state <= direct_state;
end case;
when others =>
next_state <= fetch_state;
end case;
--
-- here if ea holds low byte (direct page)
-- can enter here from extended addressing
-- read memory location
-- note that reads may be 8 or 16 bits
--
when direct_state => -- read data
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
-- read first data byte from ea
md_ctrl <= fetch_first_md;
addr_ctrl <= read_ad;
dout_ctrl <= md_lo_dout;
case op_code(7 downto 4) is
when "0001" => -- bset / bclr / brset / brclr
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ea_ctrl <= latch_ea;
pc_ctrl <= load_pc;
next_state <= bitmask_state;
when "0110" | "0111" => -- single operand
left_ctrl <= ea_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ea_ctrl <= latch_ea;
pc_ctrl <= latch_pc;
next_state <= execute_state;
when "1001" | "1010" | "1011" => -- acca
pc_ctrl <= latch_pc;
case op_code(3 downto 0) is
when "0011" | -- subd / cpd
"1110" | -- lds
"1100" => -- cpx / cpy
-- increment the effective address in case of 16 bit load
left_ctrl <= ea_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ea_ctrl <= load_ea;
next_state <= direct16_state;
when others =>
left_ctrl <= ea_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ea_ctrl <= latch_ea;
next_state <= execute_state;
end case;
when "1101" | "1110" | "1111" => -- accb
pc_ctrl <= latch_pc;
case op_code(3 downto 0) is
when "0011" | -- addd
"1100" | -- ldd
"1110" => -- ldx / ldy
-- increment the effective address in case of 16 bit load
left_ctrl <= ea_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ea_ctrl <= load_ea;
next_state <= direct16_state;
when others =>
left_ctrl <= ea_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ea_ctrl <= latch_ea;
next_state <= execute_state;
end case;
when others =>
left_ctrl <= ea_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ea_ctrl <= latch_ea;
pc_ctrl <= latch_pc;
next_state <= fetch_state;
end case;
 
when direct16_state => -- read second data byte from ea
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
-- idle the effective address
left_ctrl <= ea_left;
right_ctrl <= one_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ea_ctrl <= latch_ea;
-- read the low byte of the 16 bit data
md_ctrl <= fetch_next_md;
addr_ctrl <= read_ad;
dout_ctrl <= md_lo_dout;
next_state <= execute_state;
 
--
-- exchange registers
-- at this point md holds accd
-- transfer X or Y to accd
--
when exchange1_state => -- md holds accd
-- default
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
md_ctrl <= latch_md;
-- transfer x or y to accd
if pre_byte = "00011000" then
left_ctrl <= iy_left;
else
left_ctrl <= ix_left;
end if;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
-- idle the address bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= exchange2_state;
 
--
-- exchange registers
-- at this point md holds accd
-- accd holds either X or Y
-- now transfer md to X or Y
--
when exchange2_state => -- md holds accd
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
md_ctrl <= latch_md;
-- transfer md to x or y
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
if pre_byte = "00011000" then
ix_ctrl <= latch_ix;
iy_ctrl <= load_iy;
else
ix_ctrl <= load_ix;
iy_ctrl <= latch_iy;
end if;
-- idle the address bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= fetch_state;
 
when bitmask_state => -- fetch bit mask from next op
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
ea_ctrl <= latch_ea;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
-- addvance the pc
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
-- read the bit mask into the pre byte register
pre_ctrl <= fetch_pre;
addr_ctrl <= fetch_ad;
dout_ctrl <= md_lo_dout;
case op_code is
when "00010010" | "00011110" => -- brset
next_state <= brset_state;
when "00010011" | "00011111" => -- brclr
next_state <= brclr_state;
when "00010100" | "00011100" => -- bset
next_state <= bset_state;
when "00010101" | "00011101" => -- bclr
next_state <= bclr_state;
when others =>
next_state <= fetch_state;
end case;
 
when brclr_state => -- fetch the branch offset
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
-- advance the pc
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
-- fetch the branch offset
addr_ctrl <= fetch_ad;
ea_ctrl <= fetch_first_ea;
dout_ctrl <= md_lo_dout;
if (pre_byte and md(7 downto 0) ) = "00000000" then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
 
when brset_state => -- fetch the branch offset
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
-- advance the pc
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
-- fetch the branch offset
addr_ctrl <= fetch_ad;
ea_ctrl <= fetch_first_ea;
dout_ctrl <= md_lo_dout;
if (pre_byte and md(7 downto 0) ) = "00000000" then
next_state <= fetch_state;
else
next_state <= branch_state;
end if;
 
when bclr_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
pc_ctrl <= latch_pc;
-- mask bit
left_ctrl <= md_left;
right_ctrl <= pre_right;
alu_ctrl <= alu_bclr;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
-- idle bus
addr_ctrl <= idle_ad;
ea_ctrl <= latch_ea;
dout_ctrl <= md_lo_dout;
next_state <= write8_state;
 
when bset_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
pc_ctrl <= latch_pc;
-- mask bit
left_ctrl <= md_left;
right_ctrl <= pre_right;
alu_ctrl <= alu_bset;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
-- idle bus
addr_ctrl <= idle_ad;
ea_ctrl <= latch_ea;
dout_ctrl <= md_lo_dout;
next_state <= write8_state;
 
when jmp_state =>
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- load PC with effective address
left_ctrl <= pc_left;
right_ctrl <= ea_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
-- idle the bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= fetch_state;
 
when jsr_state => -- JSR
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write pc low
addr_ctrl <= push_ad;
dout_ctrl <= pc_lo_dout;
next_state <= jsr1_state;
 
when jsr1_state => -- JSR
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write pc hi
addr_ctrl <= push_ad;
dout_ctrl <= pc_hi_dout;
next_state <= jmp_state;
 
when branch_state => -- Bcc
-- default registers
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- calculate signed branch
left_ctrl <= pc_left;
right_ctrl <= sexea_right; -- right must be sign extended effective address
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
pc_ctrl <= load_pc;
-- idle the bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= fetch_state;
 
when bsr_state => -- BSR
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write pc low
addr_ctrl <= push_ad;
dout_ctrl <= pc_lo_dout;
next_state <= bsr1_state;
 
when bsr1_state => -- BSR
-- default registers
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write pc hi
addr_ctrl <= push_ad;
dout_ctrl <= pc_hi_dout;
next_state <= branch_state;
 
when rts_hi_state => -- RTS
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- increment the sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- read pc hi
pc_ctrl <= pull_hi_pc;
addr_ctrl <= pull_ad;
dout_ctrl <= pc_hi_dout;
next_state <= rts_lo_state;
 
when rts_lo_state => -- RTS1
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- idle the ALU
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- read pc low
pc_ctrl <= pull_lo_pc;
addr_ctrl <= pull_ad;
dout_ctrl <= pc_lo_dout;
next_state <= fetch_state;
 
when mul_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- move acca to md
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= mulea_state;
 
when mulea_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
md_ctrl <= latch_md;
-- move accb to ea
left_ctrl <= accb_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
ea_ctrl <= load_ea;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= muld_state;
 
when muld_state =>
-- default
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
md_ctrl <= latch_md;
-- clear accd
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_ld8;
cc_ctrl <= latch_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= mul0_state;
 
when mul0_state =>
-- default
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
count_ctrl <= inc_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- if ea bit(count) set, add accd to md
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
if ea_bit = '1' then
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
else
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
end if;
md_ctrl <= shiftl_md;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
if count = "0111" then
next_state <= fetch_state;
else
next_state <= mul0_state;
end if;
 
--
-- Integer division
-- ACCD = numerator
-- EA = denominator
-- IX = quotient
--
-- For integer divide, re-arrange registers
-- IX = ACCD = dividend low word
-- ACCD = 0 = dividend
--
when idiv_state =>
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
md_ctrl <= latch_md;
-- transfer ACCD to IX
left_ctrl <= accd_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
ix_ctrl <= load_ix; --- quotient / dividend
acca_ctrl <= reset_acca;
accb_ctrl <= reset_accb;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= div1_state;
 
 
--
-- Common integer divide
-- ACCD = Dividend high word
-- IX = Dividend low word / Quotient
-- EA = Divisor
-- MD = Temp for subtraction
--
-- Test for divide
-- MD = ACCD - EA
--
when div1_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
count_ctrl <= latch_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- subtract denominator from numerator
left_ctrl <= accd_left;
right_ctrl <= ea_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
md_ctrl <= load_md; -- md = temporary result
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= div2_state;
 
--
-- shift carry into quotient
-- IX = IX << 1 + Carry
-- next state dependant on carry from previous state
--
when div2_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
count_ctrl <= inc_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
md_ctrl <= load_md;
-- rotate carry into quotient
left_ctrl <= ix_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_rol16;
cc_ctrl <= load_cc;
ix_ctrl <= load_ix;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
if cc(CBIT) = '1' then
next_state <= div3_state;
else
next_state <= div4_state;
end if;
 
--
-- hear if Carry Set from subtract
-- ACCD = ACCD << 1 + Carry
--
when div3_state =>
-- default
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
count_ctrl <= latch_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
md_ctrl <= latch_md;
-- shift numerator left
left_ctrl <= accd_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_rol16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
if count = "10000" then
next_state <= div5_state;
else
next_state <= div1_state;
end if;
--
-- hear if Carry Clear from subtract
-- ACCD = MD << 1 + Carry
--
when div4_state =>
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
count_ctrl <= latch_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
md_ctrl <= latch_md;
-- numerator = Subtraction rotated left
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_rol16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
if count = "10000" then
next_state <= div5_state;
else
next_state <= div1_state;
end if;
 
--
-- invert quotient in IX
-- IX = COM( IX )
--
when div5_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
count_ctrl <= latch_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
md_ctrl <= latch_md;
-- complement quotient
left_ctrl <= ix_left;
right_ctrl <= ea_right;
alu_ctrl <= alu_com;
cc_ctrl <= load_cc;
ix_ctrl <= load_ix;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= fetch_state;
 
--
-- Spin the Program counter
--
when spin_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
count_ctrl <= latch_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
md_ctrl <= latch_md;
-- complement quotient
left_ctrl <= pc_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
pc_ctrl <= load_pc;
cc_ctrl <= latch_cc;
-- idle bus
addr_ctrl <= fetch_ad;
dout_ctrl <= md_lo_dout;
next_state <= spin_state;
 
 
when execute_state => -- execute
-- default
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
count_ctrl <= reset_count;
case op_code(7 downto 4) is
when "0001" => -- bit operators come here
case op_code(3 downto 0) is
when "0100" | "1100" => -- bset
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
ea_ctrl <= latch_ea;
-- OR bit
left_ctrl <= md_left;
right_ctrl <= pre_right;
alu_ctrl <= alu_bset;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= write8_state;
when "0101" | "1101" => -- bclr
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
ea_ctrl <= latch_ea;
-- AND bit
left_ctrl <= md_left;
right_ctrl <= pre_right;
alu_ctrl <= alu_bclr;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= write8_state;
when others =>
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
ea_ctrl <= latch_ea;
-- idle ALU
left_ctrl <= md_left;
right_ctrl <= pre_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= fetch_state;
end case;
when "0000" | -- inherent operators
"0010" | -- branch conditional
"0011" | -- stack operators
"0100" | -- acca single operand
"0101" => -- accb single operand
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
ea_ctrl <= latch_ea;
-- idle ALU
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= fetch_state;
 
when "0110" | -- indexed single op
"0111" => -- extended single op
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
ea_ctrl <= latch_ea;
-- idle the bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
case op_code(3 downto 0) is
when "0000" => -- neg
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_neg;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "0011" => -- com
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_com;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "0100" => -- lsr
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_lsr8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "0110" => -- ror
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_ror8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "0111" => -- asr
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_asr8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "1000" => -- asl
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_asl8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "1001" => -- rol
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_rol8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "1010" => -- dec
left_ctrl <= md_left;
right_ctrl <= one_right;
alu_ctrl <= alu_dec;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "1011" => -- undefined
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1100" => -- inc
left_ctrl <= md_left;
right_ctrl <= one_right;
alu_ctrl <= alu_inc;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "1101" => -- tst
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
cc_ctrl <= load_cc;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1110" => -- jmp
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1111" => -- clr
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_ld8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when others =>
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= fetch_state;
end case;
 
when "1000" | -- acca immediate
"1001" | -- acca direct
"1010" | -- acca indexed
"1011" => -- acca extended
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
ea_ctrl <= latch_ea;
-- idle the bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
case op_code(3 downto 0) is
when "0000" => -- suba
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0001" => -- cmpa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0010" => -- sbca
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sbc;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0011" => -- subd / cmpd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
if (pre_byte = "00011010") or (pre_byte = "11001101") then
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
else
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
end if;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0100" => -- anda
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0101" => -- bita
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0110" => -- ldaa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0111" => -- staa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= load_md;
next_state <= write8_state;
when "1000" => -- eora
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_eor;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1001" => -- adca
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_adc;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1010" => -- oraa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ora;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1011" => -- adda
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1100" => -- cpx / cpy
if (pre_byte = "00011000") or (pre_byte = "00011010") then
left_ctrl <= iy_left;
else
left_ctrl <= ix_left;
end if;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1101" => -- bsr / jsr
left_ctrl <= pc_left;
right_ctrl <= md_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1110" => -- lds
left_ctrl <= sp_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= load_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1111" => -- sts
left_ctrl <= sp_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= load_md;
next_state <= write16_state;
when others =>
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
end case;
when "1100" | -- accb immediate
"1101" | -- accb direct
"1110" | -- accb indexed
"1111" => -- accb extended
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
ea_ctrl <= latch_ea;
-- idle the bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
case op_code(3 downto 0) is
when "0000" => -- subb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0001" => -- cmpb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0010" => -- sbcb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sbc;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0011" => -- addd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0100" => -- andb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0101" => -- bitb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0110" => -- ldab
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "0111" => -- stab
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= load_md;
next_state <= write8_state;
when "1000" => -- eorb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_eor;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1001" => -- adcb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_adc;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1010" => -- orab
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ora;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1011" => -- addb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1100" => -- ldd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1101" => -- std
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= load_md;
next_state <= write16_state;
when "1110" => -- ldx / ldy
if pre_byte = "00011000" then
left_ctrl <= iy_left;
ix_ctrl <= latch_ix;
iy_ctrl <= load_iy;
else
left_ctrl <= ix_left;
ix_ctrl <= load_ix;
iy_ctrl <= latch_iy;
end if;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1111" => -- stx / sty
if pre_byte = "00011000" then
left_ctrl <= iy_left;
else
left_ctrl <= ix_left;
end if;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= load_md;
next_state <= write16_state;
when others =>
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
next_state <= fetch_state;
end case;
when others =>
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
ea_ctrl <= latch_ea;
-- idle the bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= fetch_state;
end case;
--
-- 16 bit Write state
-- write high byte of ALU output.
-- EA hold address of memory to write to
-- Advance the effective address in ALU
--
when write16_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
-- increment the effective address
left_ctrl <= ea_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ea_ctrl <= load_ea;
-- write the ALU hi byte to ea
addr_ctrl <= write_ad;
dout_ctrl <= md_hi_dout;
next_state <= write8_state;
--
-- 8 bit write
-- Write low 8 bits of ALU output
--
when write8_state =>
-- default registers
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- idle the ALU
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- write ALU low byte output
addr_ctrl <= write_ad;
dout_ctrl <= md_lo_dout;
next_state <= fetch_state;
 
when psha_state =>
-- default registers
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write acca
addr_ctrl <= push_ad;
dout_ctrl <= acca_dout;
next_state <= fetch_state;
 
when pula_state =>
-- default registers
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- idle sp
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
-- read acca
acca_ctrl <= pull_acca;
addr_ctrl <= pull_ad;
dout_ctrl <= acca_dout;
next_state <= fetch_state;
 
when pshb_state =>
-- default registers
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write accb
addr_ctrl <= push_ad;
dout_ctrl <= accb_dout;
next_state <= fetch_state;
 
when pulb_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- idle sp
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
-- read accb
accb_ctrl <= pull_accb;
addr_ctrl <= pull_ad;
dout_ctrl <= accb_dout;
next_state <= fetch_state;
 
when pshx_lo_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write ix low
addr_ctrl <= push_ad;
if pre_byte = "00011000" then
dout_ctrl <= iy_lo_dout;
else
dout_ctrl <= ix_lo_dout;
end if;
next_state <= pshx_hi_state;
 
when pshx_hi_state =>
-- default registers
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write ix / iy hi
addr_ctrl <= push_ad;
if pre_byte = "00011000" then
dout_ctrl <= iy_hi_dout;
else
dout_ctrl <= ix_hi_dout;
end if;
next_state <= fetch_state;
 
when pulx_hi_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- pull ix hi
if pre_byte = "00011000" then
ix_ctrl <= latch_ix;
iy_ctrl <= pull_hi_iy;
dout_ctrl <= iy_hi_dout;
else
ix_ctrl <= pull_hi_ix;
iy_ctrl <= latch_iy;
dout_ctrl <= ix_hi_dout;
end if;
addr_ctrl <= pull_ad;
next_state <= pulx_lo_state;
 
when pulx_lo_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- idle sp
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
-- read ix low
if pre_byte = "00011000" then
ix_ctrl <= latch_ix;
iy_ctrl <= pull_lo_iy;
dout_ctrl <= iy_lo_dout;
else
ix_ctrl <= pull_lo_ix;
iy_ctrl <= latch_iy;
dout_ctrl <= ix_lo_dout;
end if;
addr_ctrl <= pull_ad;
next_state <= fetch_state;
 
--
-- return from interrupt
-- enter here from bogus interrupts
--
when rti_state =>
-- default registers
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- idle address bus
cc_ctrl <= latch_cc;
addr_ctrl <= idle_ad;
dout_ctrl <= cc_dout;
next_state <= rti_cc_state;
 
when rti_cc_state =>
-- default registers
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read cc
cc_ctrl <= pull_cc;
addr_ctrl <= pull_ad;
dout_ctrl <= cc_dout;
next_state <= rti_accb_state;
 
when rti_accb_state =>
-- default registers
acca_ctrl <= latch_acca;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- read accb
accb_ctrl <= pull_accb;
addr_ctrl <= pull_ad;
dout_ctrl <= accb_dout;
next_state <= rti_acca_state;
 
when rti_acca_state =>
-- default registers
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- read acca
acca_ctrl <= pull_acca;
addr_ctrl <= pull_ad;
dout_ctrl <= acca_dout;
next_state <= rti_ixh_state;
 
when rti_ixh_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- read ix hi
ix_ctrl <= pull_hi_ix;
addr_ctrl <= pull_ad;
dout_ctrl <= ix_hi_dout;
next_state <= rti_ixl_state;
 
when rti_ixl_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- read ix low
ix_ctrl <= pull_lo_ix;
addr_ctrl <= pull_ad;
dout_ctrl <= ix_lo_dout;
next_state <= rti_iyh_state;
 
when rti_iyh_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- read iy hi
iy_ctrl <= pull_hi_iy;
addr_ctrl <= pull_ad;
dout_ctrl <= iy_hi_dout;
next_state <= rti_iyl_state;
 
when rti_iyl_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- read iy low
iy_ctrl <= pull_lo_iy;
addr_ctrl <= pull_ad;
dout_ctrl <= iy_lo_dout;
next_state <= rti_pch_state;
 
when rti_pch_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- pull pc hi
pc_ctrl <= pull_hi_pc;
addr_ctrl <= pull_ad;
dout_ctrl <= pc_hi_dout;
next_state <= rti_pcl_state;
 
when rti_pcl_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- idle sp
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
-- pull pc low
pc_ctrl <= pull_lo_pc;
addr_ctrl <= pull_ad;
dout_ctrl <= pc_lo_dout;
next_state <= fetch_state;
 
--
-- here on interrupt
-- iv register hold interrupt type
--
when int_pcl_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write pc low
addr_ctrl <= push_ad;
dout_ctrl <= pc_lo_dout;
next_state <= int_pch_state;
 
when int_pch_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write pc hi
addr_ctrl <= push_ad;
dout_ctrl <= pc_hi_dout;
next_state <= int_iyl_state;
 
when int_iyl_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write iy low
addr_ctrl <= push_ad;
dout_ctrl <= iy_lo_dout;
next_state <= int_iyh_state;
 
when int_iyh_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write iy hi
addr_ctrl <= push_ad;
dout_ctrl <= iy_hi_dout;
next_state <= int_ixl_state;
 
when int_ixl_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write ix low
addr_ctrl <= push_ad;
dout_ctrl <= ix_lo_dout;
next_state <= int_ixh_state;
 
when int_ixh_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write ix hi
addr_ctrl <= push_ad;
dout_ctrl <= ix_hi_dout;
next_state <= int_acca_state;
 
when int_acca_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write acca
addr_ctrl <= push_ad;
dout_ctrl <= acca_dout;
next_state <= int_accb_state;
 
 
when int_accb_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write accb
addr_ctrl <= push_ad;
dout_ctrl <= accb_dout;
next_state <= int_cc_state;
 
when int_cc_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write cc
addr_ctrl <= push_ad;
dout_ctrl <= cc_dout;
--
-- XIRQ is level sensitive
--
if (xirq = '1') and (cc(XBIT) = '0') then
iv_ctrl <= xirq_iv;
next_state <= int_maskx_state;
else
--
-- IRQ is level sensitive
--
if (irq = '1') and (cc(IBIT) = '0') then
iv_ctrl <= irq_iv;
next_state <= int_maski_state;
else
case op_code is
when "00111110" => -- WAI (wait for interrupt)
iv_ctrl <= latch_iv;
next_state <= int_wai_state;
when "00111111" => -- SWI (Software interrupt)
iv_ctrl <= swi_iv;
next_state <= vect_hi_state;
when others => -- bogus interrupt (return)
iv_ctrl <= latch_iv;
next_state <= rti_state;
end case;
end if;
end if;
 
when int_wai_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
count_ctrl <= reset_count;
md_ctrl <= latch_md;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- enable interrupts
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_cli;
cc_ctrl <= load_cc;
sp_ctrl <= latch_sp;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= cc_dout;
--
-- XIRQ is level sensitive
--
if (xirq = '1') and (cc(XBIT) = '0') then
iv_ctrl <= xirq_iv;
next_state <= int_maskx_state;
else
--
-- IRQ is level sensitive
--
if (irq = '1') and (cc(IBIT) = '0') then
iv_ctrl <= irq_iv;
next_state <= int_maski_state;
else
iv_ctrl <= latch_iv;
next_state <= int_wai_state;
end if;
end if;
 
when int_maskx_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- Mask IRQ
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_sex;
cc_ctrl <= load_cc;
sp_ctrl <= latch_sp;
-- idle bus cycle
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= vect_hi_state;
 
when int_maski_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- Mask IRQ
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_sei;
cc_ctrl <= load_cc;
sp_ctrl <= latch_sp;
-- idle bus cycle
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= vect_hi_state;
 
when others => -- halt on undefine states
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
count_ctrl <= reset_count;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
ea_ctrl <= latch_ea;
-- do nothing in ALU
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- idle bus cycle
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= halt_state;
end case;
end process;
 
--------------------------------
--
-- state machine
--
--------------------------------
 
change_state: process( clk, rst, state )
begin
if clk'event and clk = '0' then
if rst = '1' then
state <= reset_state;
else
state <= next_state;
end if;
end if;
end process;
-- output
end;
/trunk/rtl/vhdl/rxunit.vhd
0,0 → 1,149
--===========================================================================--
--
-- S Y N T H E Z I A B L E miniUART C O R E
--
-- www.OpenCores.Org - January 2000
-- This core adheres to the GNU public license
--
-- Design units : miniUART core for the OCRP-1
--
-- File name : RxUnit.vhd
--
-- Purpose : Implements an miniUART device for communication purposes
-- between the OR1K processor and the Host computer through
-- an RS-232 communication protocol.
--
-- Library : uart_lib.vhd
--
-- Dependencies : IEEE.Std_Logic_1164
--
--===========================================================================--
-------------------------------------------------------------------------------
-- Revision list
-- Version Author Date Changes
--
-- 0.1 Ovidiu Lupas 15 January 2000 New model
-- 2.0 Ovidiu Lupas 17 April 2000 samples counter cleared for bit 0
-- olupas@opencores.org
-------------------------------------------------------------------------------
-- Description : Implements the receive unit of the miniUART core. Samples
-- 16 times the RxD line and retain the value in the middle of
-- the time interval.
-------------------------------------------------------------------------------
-- Entity for Receive Unit - 9600 baudrate --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
-------------------------------------------------------------------------------
-- Receive unit
-------------------------------------------------------------------------------
entity RxUnit is
port (
Clk : in Std_Logic; -- system clock signal
Reset : in Std_Logic; -- Reset input
Enable : in Std_Logic; -- Enable input
RxD : in Std_Logic; -- RS-232 data input
ReadD : in Std_Logic; -- Read data signal
FRErr : out Std_Logic; -- Status signal
ORErr : out Std_Logic; -- Status signal
DARdy : out Std_Logic; -- Status signal
DataI : out Std_Logic_Vector(7 downto 0));
end entity; --================== End of entity ==============================--
-------------------------------------------------------------------------------
-- Architecture for receive Unit
-------------------------------------------------------------------------------
architecture Behaviour of RxUnit is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal Start : Std_Logic; -- Syncro signal
signal tmpRxD : Std_Logic; -- RxD buffer
signal tmpDRdy : Std_Logic; -- Data ready buffer
signal outErr : Std_Logic; --
signal frameErr : Std_Logic; --
signal BitCnt : Unsigned(3 downto 0); --
signal SampleCnt : Unsigned(3 downto 0); -- samples on one bit counter
signal ShtReg : Std_Logic_Vector(7 downto 0); --
signal DOut : Std_Logic_Vector(7 downto 0); --
 
begin
---------------------------------------------------------------------
-- Receiver process
---------------------------------------------------------------------
RcvProc : process(Clk,Reset,Enable,RxD)
constant CntOne : Unsigned(3 downto 0):="0001";
begin
if Clk'event and Clk='0' then
if Reset = '1' then
BitCnt <= "0000";
SampleCnt <= "0000";
Start <= '0';
tmpDRdy <= '0';
frameErr <= '0';
outErr <= '0';
 
ShtReg <= "00000000"; --
DOut <= "00000000"; --
else
if ReadD = '1' then
tmpDRdy <= '0'; -- Data was read
end if;
 
if Enable = '1' then
if Start = '0' then
if RxD = '0' then -- Start bit,
SampleCnt <= SampleCnt + CntOne;
Start <= '1';
end if;
else
if SampleCnt = "1000" then -- reads the RxD line
tmpRxD <= RxD;
SampleCnt <= SampleCnt + CntOne;
elsif SampleCnt = "1111" then
case BitCnt is
when "0000" =>
if tmpRxD = '1' then -- Start Bit
Start <= '0';
else
BitCnt <= BitCnt + CntOne;
end if;
SampleCnt <= SampleCnt + CntOne;
when "1001" =>
if tmpRxD = '0' then -- stop bit expected
frameErr <= '1';
else
frameErr <= '0';
end if;
 
if tmpDRdy = '1' then --
outErr <= '1';
else
outErr <= '0';
end if;
 
tmpDRdy <= '1';
DOut <= ShtReg;
BitCnt <= "0000";
Start <= '0';
when others =>
BitCnt <= BitCnt + CntOne;
SampleCnt <= SampleCnt + CntOne;
ShtReg <= tmpRxD & ShtReg(7 downto 1);
end case;
else
SampleCnt <= SampleCnt + CntOne;
end if;
end if;
end if;
end if;
end if;
end process;
 
DARdy <= tmpDRdy;
DataI <= DOut;
FRErr <= frameErr;
ORErr <= outErr;
 
end Behaviour; --==================== End of architecture ====================--
/trunk/rtl/vhdl/txunit.vhd
0,0 → 1,112
--===========================================================================--
--
-- S Y N T H E Z I A B L E miniUART C O R E
--
-- www.OpenCores.Org - January 2000
-- This core adheres to the GNU public license
--
-- Design units : miniUART core for the OCRP-1
--
-- File name : TxUnit.vhd
--
-- Purpose : Implements an miniUART device for communication purposes
-- between the OR1K processor and the Host computer through
-- an RS-232 communication protocol.
--
-- Library : uart_lib.vhd
--
-- Dependencies : IEEE.Std_Logic_1164
--
--===========================================================================--
-------------------------------------------------------------------------------
-- Revision list
-- Version Author Date Changes
--
-- 0.1 Ovidiu Lupas 15 January 2000 New model
-- 2.0 Ovidiu Lupas 17 April 2000 unnecessary variable removed
-- olupas@opencores.org
-- 3.0 John Kent September 2002 Did some changes ...cant remember what
-------------------------------------------------------------------------------
-- Description :
-------------------------------------------------------------------------------
-- Entity for the Tx Unit --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
-------------------------------------------------------------------------------
-- Transmitter unit
-------------------------------------------------------------------------------
entity TxUnit is
port (
Clk : in Std_Logic; -- Clock signal
Reset : in Std_Logic; -- Reset input
Enable : in Std_Logic; -- Enable input
LoadD : in Std_Logic; -- Load transmit data
TxD : out Std_Logic; -- RS-232 data output
TBE : out Std_Logic; -- Tx buffer empty
DataO : in Std_Logic_Vector(7 downto 0));
end entity; --================== End of entity ==============================--
-------------------------------------------------------------------------------
-- Architecture for TxUnit
-------------------------------------------------------------------------------
architecture Behaviour of TxUnit is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal TBuff : Std_Logic_Vector(7 downto 0); -- transmit buffer
signal TReg : Std_Logic_Vector(7 downto 0); -- transmit register
signal BitCnt : Unsigned(3 downto 0); -- bit counter
signal tmpTRegE : Std_Logic; --
signal tmpTBufE : Std_Logic; --
begin
-----------------------------------------------------------------------------
-- Implements the Tx unit
-----------------------------------------------------------------------------
process(Clk,Reset,Enable,LoadD,DataO,TBuff,TReg,tmpTRegE,tmpTBufE)
constant CntOne : Unsigned(3 downto 0):="0001";
begin
if Clk'event and Clk = '0' then
if Reset = '1' then
tmpTRegE <= '1';
tmpTBufE <= '1';
TxD <= '1';
BitCnt <= "0000";
elsif LoadD = '1' then
TBuff <= DataO;
tmpTBufE <= '0';
elsif Enable = '1' then
if ( tmpTBufE = '0') and (tmpTRegE = '1') then
TReg <= TBuff;
tmpTRegE <= '0';
tmpTBufE <= '1';
end if;
 
if tmpTRegE = '0' then
case BitCnt is
when "0000" =>
TxD <= '0';
BitCnt <= BitCnt + CntOne;
when "0001" | "0010" | "0011" |
"0100" | "0101" | "0110" |
"0111" | "1000" =>
TxD <= TReg(0);
TReg <= '1' & TReg(7 downto 1);
BitCnt <= BitCnt + CntOne;
when "1001" =>
TxD <= '1'; -- 2 stop bits
BitCnt <= BitCnt + CntOne;
when "1010" =>
TxD <= '1';
BitCnt <= "0000";
tmpTRegE <= '1';
when others => null;
end case;
end if;
end if;
end if;
end process;
 
TBE <= tmpTBufE;
end Behaviour; --=================== End of architecture ====================--
/trunk/rtl/vhdl/ioport.vhd
0,0 → 1,194
--===========================================================================--
--
-- S Y N T H E Z I A B L E ioport - Dual 8 Bit parallel i/o port
--
-- www.OpenCores.Org - September 2003
-- This core adheres to the GNU public license
--
-- File name : ioport.vhd
--
-- Entity name : ioport
--
-- Purpose : Dual 8 bit parallel I/O port with
-- Data Direction Registers
-- cs + 0 - porta data
-- cs + 1 - portb data
-- cs + 3 - porta direction
-- cs + 4 - portb direction
--
-- Dependencies : ieee.std_logic_1164
-- ieee.std_logic_unsigned
--
-- Uses : Nothing
--
-- Author : John Kent - dilbert57@opencores.org
--
-------------------------------------------------------------------------------
-- Revision list
--
-- Revision 0.1 - 11 Oct 2002 - John Kent
-- used a loop counter for data direction & read port signals
--
-- Revision 0.2 - 5 Sept 2003 - John Kent
-- Reduced to 2 x 8 bit ports
--
-- Revision 1.0 - 7 September - John Kent
-- Initial release to open cores
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity ioport is
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector(1 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
porta_io : inout std_logic_vector(7 downto 0);
portb_io : inout std_logic_vector(7 downto 0)
);
end;
 
architecture ioport_arch of ioport is
signal porta_ddr : std_logic_vector(7 downto 0);
signal portb_ddr : std_logic_vector(7 downto 0);
signal porta_data : std_logic_vector(7 downto 0);
signal portb_data : std_logic_vector(7 downto 0);
 
begin
 
 
--------------------------------
--
-- read I/O port
--
--------------------------------
 
ioport_read : process( addr,
porta_ddr, portb_ddr,
porta_data, portb_data,
porta_io, portb_io )
variable count : integer;
begin
case addr is
when "00" =>
for count in 0 to 7 loop
if porta_ddr(count) = '1' then
data_out(count) <= porta_data(count);
else
data_out(count) <= porta_io(count);
end if;
end loop;
 
when "01" =>
for count in 0 to 7 loop
if portb_ddr(count) = '1' then
data_out(count) <= portb_data(count);
else
data_out(count) <= portb_io(count);
end if;
end loop;
 
when "10" =>
data_out <= porta_ddr;
when "11" =>
data_out <= portb_ddr;
when others =>
data_out <= "00000000";
end case;
end process;
 
---------------------------------
--
-- Write I/O ports
--
---------------------------------
 
ioport_write : process( clk, rst, addr, cs, rw, data_in,
porta_data, portb_data,
porta_ddr, portb_ddr )
begin
if clk'event and clk = '0' then
if rst = '1' then
porta_data <= "00000000";
portb_data <= "00000000";
porta_ddr <= "00000000";
portb_ddr <= "00000000";
elsif cs = '1' and rw = '0' then
case addr is
when "00" =>
porta_data <= data_in;
portb_data <= portb_data;
porta_ddr <= porta_ddr;
portb_ddr <= portb_ddr;
when "01" =>
porta_data <= porta_data;
portb_data <= data_in;
porta_ddr <= porta_ddr;
portb_ddr <= portb_ddr;
when "10" =>
porta_data <= porta_data;
portb_data <= portb_data;
porta_ddr <= data_in;
portb_ddr <= portb_ddr;
when "11" =>
porta_data <= porta_data;
portb_data <= portb_data;
porta_ddr <= porta_ddr;
portb_ddr <= data_in;
when others =>
porta_data <= porta_data;
portb_data <= portb_data;
porta_ddr <= porta_ddr;
portb_ddr <= portb_ddr;
end case;
else
porta_data <= porta_data;
portb_data <= portb_data;
porta_ddr <= porta_ddr;
portb_ddr <= portb_ddr;
end if;
end if;
end process;
 
---------------------------------
--
-- direction control port a
--
---------------------------------
porta_direction : process ( porta_data, porta_ddr )
variable count : integer;
begin
for count in 0 to 7 loop
if porta_ddr(count) = '1' then
porta_io(count) <= porta_data(count);
else
porta_io(count) <= 'Z';
end if;
end loop;
end process;
---------------------------------
--
-- direction control port b
--
---------------------------------
portb_direction : process ( portb_data, portb_ddr )
variable count : integer;
begin
for count in 0 to 7 loop
if portb_ddr(count) = '1' then
portb_io(count) <= portb_data(count);
else
portb_io(count) <= 'Z';
end if;
end loop;
end process;
---------------------------------
 
end ioport_arch;
/trunk/rtl/vhdl/swtbug11.vhd
0,0 → 1,1083
--===========================================================================--
--
-- S Y N T H E Z I A B L E SWTBUG11 monitor ROM
--
-- www.OpenCores.Org - September 2003
-- This core adheres to the GNU public license
--
-- File name : swtbug11.vhd
--
-- Entity name : boot_rom
--
-- Purpose : SWTBUG Monitor modified for the 68HC11
-- ROM sits at $E000
-- Assumes an 6850 ACIA sits at $8004
-- Assumes RAM at $A000 - $BFFF for Flex 2
-- 1024 byte x 8 bit
-- Modified stack to allow for Y register
--
-- Dependencies : ieee.std_logic_1164
-- ieee.std_logic_arith
-- ieee.std_logic_unsigned
--
-- Author : John Kent - dilbert57@opencores.org
--
--===========================================================================--
-------------------------------------------------------------------------------
-- Revision list
-- Version Author Date Changes
-- 1.0 John Kent 6 September 2003 Initial release to open corse
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
library work;
-- use work.memory.all;
 
entity boot_rom is
port (
addr : in std_logic_vector(9 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity boot_rom;
 
architecture basic of boot_rom is
constant width : integer := 8;
constant memsize : integer := 1024;
 
type rom_array is array(0 to memsize-1) of std_logic_vector(width-1 downto 0);
 
constant rom_data : rom_array :=
(
"11111110",
"10100000",
"00000000",
"01101110",
"00000000",
"10001101",
"01000000",
"01101110",
"00000000",
"00010000",
"00010110",
"00000100",
"10111101",
"11100011",
"00110100",
"10001101",
"01100111",
"10000001",
"01010011",
"00100110",
"11111010",
"10001101",
"01100001",
"10000001",
"00111001",
"00100111",
"00101001",
"10000001",
"00110001",
"00100110",
"11110000",
"01111111",
"10100000",
"00001111",
"10001101",
"00110001",
"10000000",
"00000010",
"10110111",
"10100000",
"01000111",
"10001101",
"00011100",
"10001101",
"00101000",
"01111010",
"10100000",
"01000111",
"00100111",
"00001001",
"10100111",
"00000000",
"10100001",
"00000000",
"00100110",
"00001000",
"00001000",
"00100000",
"11110000",
"01111100",
"10100000",
"00001111",
"00100111",
"11001111",
"10000110",
"00111111",
"10001101",
"00110001",
"01111110",
"11100010",
"11010100",
"10001101",
"00001100",
"10110111",
"10100000",
"00001101",
"10001101",
"00000111",
"10110111",
"10100000",
"00001110",
"11111110",
"10100000",
"00001101",
"00111001",
"10001101",
"01010011",
"01001000",
"01001000",
"01001000",
"01001000",
"00010110",
"10001101",
"01001100",
"00011011",
"00010110",
"11111011",
"10100000",
"00001111",
"11110111",
"10100000",
"00001111",
"00111001",
"01000100",
"01000100",
"01000100",
"01000100",
"10000100",
"00001111",
"10001011",
"00110000",
"10000001",
"00111001",
"00100011",
"00000010",
"10001011",
"00000111",
"01111110",
"11100001",
"11010001",
"01111110",
"11100001",
"10101100",
"10001101",
"11111000",
"00001000",
"10100110",
"00000000",
"10000001",
"00000100",
"00100110",
"11110111",
"00111001",
"01111110",
"11100001",
"01001010",
"10001101",
"10111101",
"11001110",
"11100001",
"10011101",
"10001101",
"11101111",
"11001110",
"10100000",
"00001101",
"10001101",
"00110100",
"11111110",
"10100000",
"00001101",
"10001101",
"00110001",
"10001101",
"00110001",
"10001101",
"11011011",
"10000001",
"00100000",
"00100111",
"11111010",
"10000001",
"00001101",
"00100111",
"11100000",
"10000001",
"01011110",
"00100000",
"00101100",
"00000001",
"10001101",
"11001100",
"10000000",
"00110000",
"00101011",
"01001100",
"10000001",
"00001001",
"00101111",
"00001010",
"10000001",
"00010001",
"00101011",
"01000100",
"10000001",
"00010110",
"00101110",
"01000000",
"10000000",
"00000111",
"00111001",
"10100110",
"00000000",
"10001101",
"10100100",
"10100110",
"00000000",
"00001000",
"00100000",
"10100011",
"10001101",
"11110101",
"10001101",
"11110011",
"10000110",
"00100000",
"00100000",
"10100101",
"10001110",
"10100000",
"01000000",
"00100000",
"00101100",
"00100110",
"00000111",
"00001001",
"00001001",
"11111111",
"10100000",
"00001101",
"00100000",
"10101100",
"11111111",
"10100000",
"00001101",
"00100000",
"00000010",
"00100000",
"01101101",
"10000001",
"00110000",
"00100101",
"10100001",
"10000001",
"01000110",
"00100010",
"10011101",
"10001101",
"10111101",
"10111101",
"11100000",
"01010111",
"00001001",
"10100111",
"00000000",
"10100001",
"00000000",
"00100111",
"10010001",
"01111110",
"11100000",
"01000000",
"10111110",
"10100000",
"00001000",
"00100000",
"01001001",
"10111111",
"10100000",
"00001000",
"10000110",
"11111111",
"10111101",
"11100011",
"00001000",
"11001110",
"10000000",
"00000100",
"10111101",
"11100010",
"10000100",
"10100110",
"00000000",
"10100001",
"00000010",
"00100000",
"00000010",
"00100000",
"00011001",
"00100110",
"00111001",
"10000110",
"00000011",
"10100111",
"00000000",
"10000110",
"00010001",
"10100111",
"00000000",
"00100000",
"00101111",
"00000001",
"10111111",
"10100000",
"00001000",
"00110000",
"01101101",
"00000110",
"00100110",
"00000010",
"01101010",
"00000101",
"01101010",
"00000110",
"11001110",
"11100001",
"10011101",
"10111101",
"11100000",
"01111110",
"11111110",
"10100000",
"00001000",
"00001000",
"10001101",
"10001110",
"10001101",
"10001100",
"10001101",
"10001010",
"01111110",
"11100011",
"01011111",
"00000001",
"11001110",
"10100000",
"00001000",
"10111101",
"11100000",
"11001000",
"11111110",
"10100000",
"00010010",
"10001100",
"11100001",
"00100011",
"00100111",
"00011001",
"10001110",
"10100000",
"01000000",
"11001110",
"10000000",
"00000100",
"11111111",
"10100000",
"00001010",
"01111111",
"10100000",
"00001100",
"10001101",
"01110011",
"00100111",
"00000011",
"10111101",
"11100010",
"01111101",
"10111101",
"11100011",
"01010011",
"10111101",
"11100011",
"01000111",
"11001110",
"11100001",
"10011100",
"10111101",
"11100000",
"01111110",
"10001101",
"00111001",
"11001110",
"11100011",
"11010001",
"10100001",
"00000000",
"00100110",
"00000111",
"10111101",
"11100000",
"11001100",
"11101110",
"00000001",
"01101110",
"00000000",
"00001000",
"00001000",
"00001000",
"10001100",
"11100011",
"11111000",
"00100110",
"11101101",
"00100000",
"10111111",
"11111110",
"10100000",
"00010010",
"01101110",
"00000000",
"01010011",
"00111001",
"00000100",
"00001101",
"00001010",
"00010101",
"00000000",
"00000000",
"00000000",
"01010011",
"00110001",
"00000100",
"00010011",
"00001101",
"00001010",
"00010101",
"00000000",
"00000000",
"00000000",
"00100100",
"00000100",
"00100000",
"01001100",
"11111110",
"10100000",
"00000110",
"01101110",
"00000000",
"00100000",
"01000000",
"10111101",
"11100000",
"01000111",
"11111111",
"10100000",
"00000100",
"10111101",
"11100000",
"01000111",
"10111101",
"11100000",
"01010101",
"00010110",
"10100110",
"00000000",
"11111111",
"10100000",
"00001101",
"00010001",
"00100111",
"00000010",
"00100000",
"00100001",
"11001110",
"11100001",
"10011101",
"10111101",
"11100000",
"01111110",
"11001110",
"10100000",
"00001101",
"00100000",
"00010000",
"00111011",
"00100000",
"00111010",
"11111111",
"10100000",
"00010000",
"11111110",
"10100000",
"00001010",
"00110111",
"11100110",
"00000001",
"11100001",
"00000011",
"00110011",
"00111001",
"10111101",
"11100000",
"11001000",
"11111110",
"10100000",
"00001101",
"10111100",
"10100000",
"00000100",
"00100111",
"10011110",
"00001000",
"00100000",
"11001101",
"10001101",
"00000110",
"10000100",
"01111111",
"00111001",
"00110001",
"00110001",
"00110001",
"00110111",
"10001101",
"11011010",
"00100110",
"00101000",
"10000110",
"00010101",
"10100111",
"00000000",
"10100110",
"00000000",
"01000111",
"00100100",
"11111011",
"10100110",
"00000001",
"11110110",
"10100000",
"00001100",
"00100111",
"00000111",
"00100000",
"00010001",
"00110111",
"10001101",
"11000011",
"00100110",
"00101110",
"11000110",
"00010001",
"11100111",
"00000000",
"11100110",
"00000000",
"01010111",
"01010111",
"00100100",
"11111010",
"10100111",
"00000001",
"00110011",
"11111110",
"10100000",
"00010000",
"00111001",
"10100110",
"00000000",
"00101011",
"11111100",
"10001101",
"00111010",
"11000110",
"00000100",
"11100111",
"00000010",
"01011000",
"10001101",
"00101010",
"00001101",
"01101001",
"00000000",
"01000110",
"01011010",
"00100110",
"11110111",
"10001101",
"00100001",
"11110110",
"10100000",
"00001100",
"00100111",
"00010011",
"00100000",
"11011110",
"10001101",
"00100011",
"11000110",
"00001010",
"01101010",
"00000000",
"10001101",
"00010110",
"10001101",
"00010000",
"10100111",
"00000000",
"00001101",
"01000110",
"01011010",
"00100110",
"11110111",
"11100110",
"00000010",
"01011000",
"00101010",
"11001000",
"10001101",
"00000010",
"00100000",
"11000100",
"01101101",
"00000010",
"00101010",
"11111100",
"01101100",
"00000010",
"01101010",
"00000010",
"00111001",
"01101111",
"00000010",
"10001101",
"11110111",
"00100000",
"11110001",
"10001101",
"10000011",
"00010110",
"01111111",
"10100000",
"00001011",
"11111110",
"10100000",
"00001010",
"10001101",
"00010000",
"10001101",
"00000111",
"11001110",
"11100011",
"11101111",
"00010111",
"01111110",
"11100001",
"01110110",
"10000110",
"00110100",
"10100111",
"00000011",
"10100111",
"00000010",
"00111001",
"01101100",
"00000000",
"10000110",
"00000111",
"10100111",
"00000001",
"01101100",
"00000000",
"10100111",
"00000010",
"00111001",
"01111111",
"10000000",
"00010100",
"10001101",
"00101110",
"11000110",
"00001011",
"10001101",
"00100101",
"11100110",
"00000100",
"11000101",
"00000001",
"00100110",
"11111010",
"01101111",
"00000110",
"10001101",
"00011101",
"11000110",
"10011100",
"10001101",
"00010111",
"11001110",
"00100100",
"00000000",
"11000101",
"00000010",
"00100111",
"00000110",
"10110110",
"10000000",
"00011011",
"10100111",
"00000000",
"00001000",
"11110110",
"10000000",
"00011000",
"11000101",
"00000001",
"00100110",
"11101111",
"01111110",
"00100100",
"00000000",
"11100111",
"00000100",
"10001101",
"00000000",
"00111001",
"11001110",
"11111111",
"11111111",
"00001001",
"10001100",
"10000000",
"00010100",
"00100110",
"11111010",
"00111001",
"11001110",
"11100000",
"00001001",
"10111101",
"11100000",
"01111110",
"10001101",
"11110001",
"10111101",
"11100011",
"01000111",
"00100000",
"01011000",
"11001110",
"11100001",
"00100011",
"10111100",
"10100000",
"00010010",
"00100111",
"00011010",
"00001000",
"10001101",
"00110010",
"10111101",
"11100000",
"01000111",
"11111111",
"10100000",
"00010100",
"10100110",
"00000000",
"10110111",
"10100000",
"00010110",
"10000110",
"00111111",
"10100111",
"00000000",
"11001110",
"11100001",
"00100011",
"10001101",
"00011110",
"01111110",
"11100001",
"01101011",
"11111110",
"10100000",
"00010100",
"10110110",
"10100000",
"00010110",
"10100111",
"00000000",
"11001110",
"11100001",
"00100100",
"00100000",
"11011010",
"10110111",
"10100000",
"01000001",
"11111110",
"10100000",
"00010010",
"10001100",
"11100001",
"00100011",
"00100111",
"00000110",
"11001110",
"11100001",
"00100100",
"11111111",
"10100000",
"00010010",
"00111001",
"10001101",
"01011010",
"00100000",
"00001111",
"11001110",
"10100000",
"01001001",
"11111111",
"10100000",
"00000100",
"00001001",
"10001101",
"01010010",
"11001110",
"11100001",
"10010000",
"10111101",
"11100000",
"01111110",
"10001101",
"00100100",
"10001101",
"10010001",
"01111110",
"11100001",
"01010010",
"01110011",
"10100000",
"00001100",
"10000110",
"00010001",
"11000110",
"00100000",
"10001101",
"00011010",
"10111101",
"11100001",
"11011001",
"00100111",
"00000100",
"10000110",
"00111100",
"10100111",
"00000011",
"00111001",
"10000110",
"00010011",
"11000110",
"00010000",
"00100000",
"00001010",
"10000110",
"00010010",
"11000110",
"00000100",
"00100000",
"00000100",
"10000110",
"00010100",
"11000110",
"00001000",
"10111101",
"11100000",
"01110101",
"10111101",
"11100001",
"11010110",
"00100000",
"00010110",
"10111101",
"11100000",
"11001000",
"10111101",
"11100000",
"11001000",
"10111101",
"11100000",
"11001000",
"01111110",
"11100001",
"01000100",
"11100111",
"00000000",
"10001101",
"00000010",
"10000110",
"00000110",
"10100111",
"00000001",
"11100111",
"00000000",
"00111001",
"11111110",
"10100000",
"00000010",
"11111111",
"10100000",
"01000100",
"10001101",
"11001111",
"10110110",
"10100000",
"00000101",
"10110000",
"10100000",
"01000101",
"11110110",
"10100000",
"00000100",
"11110010",
"10100000",
"01000100",
"00100110",
"00000100",
"10000001",
"00010000",
"00100101",
"00000010",
"10000110",
"00001111",
"10001011",
"00000100",
"10110111",
"10100000",
"01000111",
"10000000",
"00000011",
"10110111",
"10100000",
"01000110",
"11001110",
"11100001",
"10010011",
"10111101",
"11100000",
"01111110",
"01011111",
"11001110",
"10100000",
"01000111",
"10001101",
"00100100",
"11001110",
"10100000",
"01000100",
"10001101",
"00011111",
"10001101",
"00011101",
"11111110",
"10100000",
"01000100",
"10001101",
"00011000",
"01111010",
"10100000",
"01000110",
"00100110",
"11111001",
"11111111",
"10100000",
"01000100",
"01010011",
"00110111",
"00110000",
"10001101",
"00001011",
"00110011",
"11111110",
"10100000",
"01000100",
"00001001",
"10111100",
"10100000",
"00000100",
"00100110",
"10110011",
"00111001",
"11101011",
"00000000",
"01111110",
"11100000",
"10111111",
"01000111",
"11100001",
"11010000",
"01011010",
"11000000",
"00000000",
"01001101",
"11100000",
"10001000",
"01000110",
"11100001",
"10101110",
"01010010",
"11100001",
"00110000",
"01001010",
"11100000",
"00000101",
"01000011",
"11100010",
"11001100",
"01000100",
"11100010",
"10001111",
"01000010",
"11100010",
"11011001",
"01001111",
"11100010",
"01101001",
"01010000",
"11100011",
"00011010",
"01001100",
"11100000",
"00001100",
"01000101",
"11100011",
"00011110",
"11100000",
"00000000",
"11100001",
"10001011",
"11100001",
"10100111",
"11100000",
"11010000"
);
begin
data <= rom_data(conv_integer(addr));
end architecture basic;
 
/trunk/rtl/vhdl/System11.npl
0,0 → 1,36
JDF E
// Created by ISE ver 1.0
PROJECT System11
DESIGN system11 Normal
DEVKIT xc2s300e-6pq208
DEVFAM spartan2e
FLOW XST VHDL
STIMULUS testbench1.vhd Normal
STIMULUS testbench2.vhd Normal
STIMULUS testbench3.vhd Normal
MODULE ioport.vhd
MODSTYLE ioport Normal
MODULE cpu11.vhd
MODSTYLE cpu11 Normal
MODULE rxunit.vhd
MODSTYLE rxunit Normal
MODULE swtbug11.vhd
MODSTYLE boot_rom Normal
MODULE txunit.vhd
MODSTYLE txunit Normal
MODULE datram.vhd
MODSTYLE dat_ram Normal
MODULE timer.vhd
MODSTYLE timer Normal
MODULE System11.vhd
MODSTYLE system11 Normal
MODULE clkunit.vhd
MODSTYLE clkunit Normal
MODULE miniUART.vhd
MODSTYLE miniuart Normal
 
[Normal]
p_impactConfigMode=xstvhd, SPARTAN2E, VHDL.t_impactProgrammingTool, 1062755889, Slave Serial
 
[STRATEGY-LIST]
Normal=True, 1062754578
/trunk/sw/SWTBUG11.s19
0,0 → 1,35
S123E000FEA0006E008D406E00101604BDE3348D67815326FA8D6181392729813126F07F90
S123E020A00F8D318002B7A0478D1C8D287AA0472709A700A10026080820F07CA00F27CFB1
S123E040863F8D317EE2D48D0CB7A00D8D07B7A00EFEA00D398D5348484848168D4C1B160B
S123E060FBA00FF7A00F3944444444840F8B30813923028B077EE1D17EE1AC8DF808A600D6
S123E080810426F7397EE14A8DBDCEE19D8DEFCEA00D8D34FEA00D8D318D318DDB81202753
S123E0A0FA810D27E0815E202C018DCC80302B4C81092F0A81112B4481162E40800739A6F2
S123E0C0008DA4A6000820A38DF58DF3862020A58EA040202C26070909FFA00D20ACFFA01D
S123E0E00D2002206D813025A18146229D8DBDBDE05709A700A10027917EE040BEA00820F8
S123E10049BFA00886FFBDE308CE8004BDE284A600A1022002201926398603A7008611A738
S123E12000202F01BFA008306D0626026A056A06CEE19DBDE07EFEA008088D8E8D8C8D8A1A
S123E1407EE35F01CEA008BDE0C8FEA0128CE12327198EA040CE8004FFA00A7FA00C8D730B
S123E1602703BDE27DBDE353BDE347CEE19CBDE07E8D39CEE3D1A1002607BDE0CCEE016E39
S123E180000808088CE3F826ED20BFFEA0126E005339040D0A15000000533104130D0A1569
S123E1A00000002404204CFEA0066E002040BDE047FFA004BDE047BDE05516A600FFA00D90
S123E1C01127022021CEE19DBDE07ECEA00D20103B203AFFA010FEA00A37E601E103333954
S123E1E0BDE0C8FEA00DBCA004279E0820CD8D06847F39313131378DDA26288615A700A6BB
S123E200004724FBA601F6A00C27072011378DC3262EC611E700E600575724FAA70133FEC8
S123E220A01039A6002BFC8D3AC604E702588D2A0D6900465A26F78D21F6A00C271320DEE0
S123E2408D23C60A6A008D168D10A7000D465A26F7E602582AC88D0220C46D022AFC6C0277
S123E2606A02396F028DF720F18D83167FA00BFEA00A8D108D07CEE3EF177EE1768634A7D9
S123E28003A702396C008607A7016C00A702397F80148D2EC60B8D25E604C50126FA6F0610
S123E2A08D1DC69C8D17CE2400C5022706B6801BA70008F68018C50126EF7E2400E7048D41
S123E2C00039CEFFFF098C801426FA39CEE009BDE07E8DF1BDE3472058CEE123BCA012279D
S123E2E01A088D32BDE047FFA014A600B7A016863FA700CEE1238D1E7EE16BFEA014B6A0D4
S123E30016A700CEE12420DAB7A041FEA0128CE1232706CEE124FFA012398D5A200FCEA029
S123E32049FFA004098D52CEE190BDE07E8D248D917EE15273A00C8611C6208D1ABDE1D971
S123E3402704863CA703398613C610200A8612C60420048614C608BDE075BDE1D62016BDE9
S123E360E0C8BDE0C8BDE0C87EE144E7008D028606A701E70039FEA002FFA0448DCFB6A085
S123E38005B0A045F6A004F2A044260481102502860F8B04B7A0478003B7A046CEE193BDAC
S123E3A0E07E5FCEA0478D24CEA0448D1F8D1DFEA0448D187AA04626F9FFA0445337308DFE
S123E3C00B33FEA04409BCA00426B339EB007EE0BF47E1D05AC0004DE08846E1AE52E13097
S11BE3E04AE00543E2CC44E28F42E2D94FE26950E31A4CE00C45E31EEA
S10BE3F8E000E18BE1A7E0D095
S105A048E0D062
S9030000FC
/trunk/sw/SwtBug11.txt
0,0 → 1,669
NAM SWTBUG
* VERSION 1.00
 
OPT l
****************************************************
*REPLACEMENT FOR MIKBUG ROM
*FOR SWTPC 6800 COMPUTER SYSTEM
*COPYRIGHT 1977
*SOUTHWEST TECHNICAL PROD. CORP.
*AUGUST, 1977
****************************************************
*
* Revised for the 68HC11
* 15 December 2002
* John E. Kent
*
ORG $A000
IRQ RMB 2 IRQ POINTER
BEGA RMB 2 BEGINNING ADDR PNCH
ENDA RMB 2 ENDING ADDR PNCH
NMI RMB 2 NMI INTERRUPT VECTOR
SP RMB 1 S HIGH
RMB 1 S LOW
PORADD RMB 2 PORT ADDRESS
PORECH RMB 1 ECHO ON/OFF FLAG
XHI RMB 1 XREG HIGH
XLOW RMB 1 XREG LOW
CKSM RMB 1 CHECKSUM
XTEMP RMB 2 X-REG TEMP STGE
SWIJMP RMB 2 SWI JUMP VECTOR
TW EQU $A044 TEMPORARY STORAGE
TEMP EQU $A046 TEMPORARY STORAGE
BYTECT EQU $A047 BYTECT AND MCONT TEMP.
CTLPOR EQU $8004 CONTROL PORT ADDRESS
PROM EQU $C000 JUMP TO PROM ADDRESS
BKPT RMB 2 BREAKPOINT ADDRESS
BKLST RMB 1 BREAKPOINT DATA
*
* Two more bytes added to the stack
* for the IY register
*
ORG $A040
STACK RMB 1 SWTBUG STACK
*
ORG $E000
*
*I/O INTERRUPT SEQUENCE
IRQV LDX IRQ
JMP 0,X
*
*JUMP TO USER PROGRAM
JUMP BSR BADDR
JMP 0,X
*
CURSOR FCB $10,$16,4 CT-1024 CURSOR CONTROL
*
*ASCII LOADING ROUTINE
LOAD JSR RDON READER ON, DIS ECHO, GET P#
LOAD3 BSR INCH
CMPA #'S
BNE LOAD3 1ST CHAR NOT S
BSR INCH READ CHAR
CMPA #'9
BEQ LOAD21
CMPA #'1
BNE LOAD3 2ND CHAR NOT 1
CLR CKSM ZERO CHECKSUM
BSR BYTE READ BYTE
SUBA #2
STAA BYTECT BYTE COUNT
*BUILD ADDRESS
BSR BADDR
*STORE DATA
LOAD11 BSR BYTE
DEC BYTECT
BEQ LOAD15 ZERO BYTE COUNT
STAA 0,X STORE DATA
CMPA 0,X DATA STORED?
BNE LOAD19
INX
BRA LOAD11
LOAD15 INC CKSM
BEQ LOAD3
LOAD19 LDAA #'?
BSR OUTCH
LOAD21 JMP RDOFF1
*
*BUILD ADDRESS
BADDR BSR BYTE READ 2 FRAMES
STAA XHI
BSR BYTE
STAA XLOW
LDX XHI LOAD IXR WITH NUMBER
RTS
*
*INPUT BYTE (TWO FRAMES)
BYTE BSR INHEX GET HEX CHAR
BYTE1 ASLA
ASLA
ASLA
ASLA
TAB
BSR INHEX
ABA
TAB
ADDB CKSM
STAB CKSM
RTS
*
OUTHL LSRA OUT HEX LEFT BCD DIGIT
LSRA
LSRA
LSRA
OUTHR ANDA #$F OUT HEX RIGHT BCD DIGIT
ADDA #$30
CMPA #$39
BLS OUTCH
ADDA #$7
*
*OUTPUT ONE CHAR
OUTCH JMP OUTEEE
INCH JMP INEEE
*
*PRINT DATA POINTED TO BY X REG
PDATA2 BSR OUTCH
INX
PDATA1 LDAA 0,X
CMPA #4
BNE PDATA2
RTS STOP ON HEX 04
*
C1 JMP SWTCTL
*
*MEMORY EXAMINE AND CHANGE
CHANGE BSR BADDR
CHA51 LDX #MCL
BSR PDATA1 C/R L/F
LDX #XHI
BSR OUT4HS PRINT ADDRESS
LDX XHI
BSR OUT2HS PRINT OLD DATA
BSR OUTS OUTPUT SPACE
ANOTH BSR INCH INPUT CHAR
CMPA #$20
BEQ ANOTH
CMPA #$D
BEQ C1
CMPA #'^ UP ARROW?
BRA AL3 BRANCH FOR ADJUSTMENT
NOP
*
*INPUT HEX CHARACTER
INHEX BSR INCH
INHEX1 SUBA #$30
BMI C3
CMPA #$9
BLE IN1HG
CMPA #$11
BMI C3 NOT HEX
CMPA #$16
BGT C3 NOT HEX
SUBA #7
IN1HG RTS
*
OUT2H LDAA 0,X OUTPUT 2 HEX CHAR
OUT2HA BSR OUTHL OUT LEFT HEX CHAR
LDAA 0,X
INX
BRA OUTHR OUTPUT RIGHT HEX CHAR
*
OUT4HS BSR OUT2H OUTPUT 4 HEX CHAR + SPACE
OUT2HS BSR OUT2H OUTPUT 2 HEX CHAR + SPACE
*
OUTS LDAA #$20 SPACE
BRA OUTCH (BSR & TRS)
*
*ENTER POWER ON SEQUENCE
START LDS #STACK
BRA AL1 BRANCH FOR ADDRESS COMPATIBIL
*
********************************************
*PART OF MEMORY EXAMINE AND CHANGE
AL3 BNE SK1
DEX
DEX
STX XHI
BRA CHA51
SK1 STX XHI
BRA AL4
*
EOE3 BRA CONTRL BRANCH FOR MIKBUG EQUIV. CONT
*
AL4 CMPA #$30
BCS CHA51
CMPA #$46
BHI CHA51
BSR INHEX1
JSR BYTE1
DEX
STAA 0,X CHANGE MEMORY
CMPA 0,X
BEQ CHA51 DID CHANGE
JMP LOAD19 DIDN'T CHANGE
C3 LDS SP
BRA SWTCTL
**************************************************
*
*CONTINUE POWER UP SEQUENCE
AL1 STS SP INIT TARGET STACK PTR.
LDAA #$FF
JSR SWISET
*CONFIGURE FOR PIA AND SEE IF OK
LDX #CTLPOR
JSR PIAINI INIT PIA
LDAA 0,X
CMPA 2,X
BRA AL2
*
BRA PRINT BRA FOR BILOAD
*
AL2 BNE CONTRL
*
*INITIALIZE AS ACIA
LDAA #3 ACIA MASTER RESET
STAA 0,X
LDAA #$11
STAA 0,X
BRA CONTRL
*
*ENTER FROM SOFTWARE INTERRUPT
SF0 NOP
SFE1 STS SP SAVE TARGETS STACK POINTER
*DECREMENT P COUNTER
TSX
TST 6,X
BNE *+4
DEC 5,X
DEC 6,X
*PRINT CONTENTS OF STACK.
PRINT LDX #MCL
JSR PDATA1
LDX SP
INX
BSR OUT2HS COND CODES
BSR OUT2HS ACC B
BSR OUT2HS ACC A
JMP PATCH1
NOP
* BSR OUT4HS IXR
* BSR OUT4HS PGM COUNTER
PATCH2 LDX #SP
JSR OUT4HS STACK POINTER
SWTCTL LDX SWIJMP
CPX #SF0
BEQ CONTR1
*
CONTRL LDS #STACK SET CONTRL STACK POINTER
LDX #CTLPOR RESET TO CONTROL PORT
STX PORADD
CLR PORECH TURN ECHO ON
BSR SAVGET GET PORT # AND TYPE
BEQ POF1
JSR PIAECH SET PIA ECHO ON IF MP-C INTER
POF1 JSR PNCHOF TURN PUNCH OFF
JSR RDOFF TURN READER OFF
CONTR1 LDX #MCLOFF
JSR PDATA1 PRINT DATA STRING
BSR INEEE READ COMMAND CHARACTER
*
*COMMAND LOOKUP ROUTINE
LOOK LDX #TABLE
OVER CMPA 0,X
BNE SK3
JSR OUTS SKIP SPACE
LDX 1,X
JMP 0,X
SK3 INX
INX
INX
CPX #TABEND+3
BNE OVER
SWTL1 BRA SWTCTL
*
*SOFTWARE INTERRUPT ENTRY POINT
SFE LDX SWIJMP JUMP TO VECTORED SOFTWARE INT
JMP 0,X
*
S9 FCB 'S,'9,4 END OF TAPE
*
***************************************************
MTAPE1 FCB $D,$A,$15,0,0,0,'S,'1,4 PUNCH FORMAT
*
MCLOFF FCB $13 READER OFF
MCL FCB $D,$A,$15,0,0,0,'$,4
*
EIA5 BRA BILD BINARY LOADER INPUT
***************************************************
*
*
*NMI SEQUENCE
NMIV LDX NMI GET NMI VECTOR
JMP 0,X
*
INEEE BRA INEEE1
*
*BYTE SEARCH ROUTINE
SEARCH JSR BADDR GET TOP ADDRESS
STX ENDA
JSR BADDR GET BOTTOM ADDRESS
JSR BYTE GET BYTE TO SEARCH FOR
TAB
OVE LDAA 0,X
STX XHI
CBA
BEQ PNT
BRA INCR1
PNT LDX #MCL
JSR PDATA1
LDX #XHI
BRA SKP0
***************************************************
*
*GO TO USER PROGRAM ROUTINE
GOTO RTI
OUTEEE BRA OUTEE1
*
*
*
*SAVE IXR AND LOAD IXR WITH CORRECT
*PORT NUMBER AND TEST FOR TYPE
SAVGET STX XTEMP STORE INDEX REGISTER
GETPT1 LDX PORADD
ISACIA PSHB
LDAB 1,X
CMPB 3,X
PULB
RTS
***************************************************
*
*CONTINUATION OF SEARCH ROUTINE
SKP0 JSR OUT4HS
LDX XHI
INCR1 CPX ENDA
BEQ SWTL1
INX
BRA OVE
*
INEEE1 BSR INCH8 INPUT 8 BIT CHARACTER
ANDA #%01111111 GET RID OF PARITY BIT
RTS
*
BILD INS FIX UP STACK WHEN USING
INS BINARY LOADER ON SWTPC TAPES
INS
*
*INPUT ONE CHAR INTO ACC B
INCH8 PSHB SAVE ACC B
BSR SAVGET SAVE IXR, GET PORT# AND TYPE
BNE IN1 INPUT FROM PIA IF NOT
LDAA #$15 RECONFIG FOR 8 BIT, 1 SB
STAA 0,X
ACIAIN LDAA 0,X
ASRA
BCC ACIAIN NOT READY
LDAA 1,X LOAD CHAR
LDAB PORECH
BEQ ACIOUT ECHO
BRA RES DON'T ECHO
*
*OUTPUT ONE CHARACTER
OUTEE1 PSHB SAVE ACC B
BSR SAVGET
BNE IOUT
*
ACIOUT LDAB #$11
STAB 0,X
ACIOU1 LDAB 0,X
ASRB
ASRB
BCC ACIOU1 ACIA NOT READY
STAA 1,X OUTPUT CHARACTER
RES PULB RESTORE ACC B
LDX XTEMP
RTS
*
*PIA INPUT ROUTINE
IN1 LDAA 0,X LOOK FOR START BIT
BMI IN1
BSR DDL DELAY HALF BIT TIME
LDAB #4 SET DEL FOR FULL BIT TIME
STAB 2,X
ASLB SET UP CNTR WITH 8
IN3 BSR DEL WAIT ONE CHAR TIME
SEC
ROL 0,X
RORA
DECB
BNE IN3
BSR DEL WAIT FOR STOP BIT
LDAB PORECH IS ECHO DESIRED?
BEQ IOUT2 ECHO
BRA RES RESTORE IXR,ACCB
*PIA OUTPUT ROUTINE
IOUT BSR DDL1 DELAY ONE HALF BIT TIME
LDAB #$A SET UP COUNTER
DEC 0,X SET START BIT
BSR DE START TIMER
OUT1 BSR DEL DELAY ONE BIT TIME
STAA 0,X PUT OUT ONE DATA BIT
SEC
RORA SHIFT IN NEXT BIT
DECB DECREMENT COUNTER
BNE OUT1 TEST FOR 0
IOUT2 LDAB 2,X TEST FOR STOP BITS
ASLB SHIFT BIT TO SIGN
BPL RES BRA FOR 1 STOP BIT
BSR DEL DELAY FOR STOP BITS
BRA RES
DEL TST 2,X IS TIME UP
BPL DEL
DE INC 2,X RESET TIMER
DEC 2,X
RTS
*
DDL CLR 2,X HALF BIT DELAY
DDL1 BSR DE
BRA DEL
*
*
*OPTIONAL PORT ROUTINE
OPTL BSR INEEE1
TAB
CLR PORADD+1 SET I/O ADDRESS FOR $8000
LDX PORADD
BSR PIAINI INITIALIZE PIA
BSR PIAECH SET ECHO
LDX #TABLE1 P, L OR E
TBA
JMP OVER LOOK AT TABLE FOR E, L OR P
*
PIAECH LDAA #$34 SET DDR
STAA 3,X
STAA 2,X
NOOPT RTS
*
*PIA INITIALIZATION ROUTINE
PIAINI INC 0,X SET DDR
LDAA #$7
STAA 1,X
INC 0,X
STAA 2,X
RTS
*
*MINIFLOPPY DISK BOOT
DISK CLR $8014
BSR DELAY
LDAB #$0B
BSR RETT2
LOOP1 LDAB 4,X
BITB #1
BNE LOOP1
CLR 6,X
BSR RETURN
LDAB #$9C
BSR RETT2
LDX #$2400
LOOP2 BITB #2
BEQ LOOP3
LDAA $801B
STAA 0,X
INX
LOOP3 LDAB $8018
BITB #1
BNE LOOP2
JMP $2400
RETT2 STAB 4,X
RETURN BSR RETT1
RETT1 RTS
*
*GENERAL PURPOSE DELAY LOOP
DELAY LDX #$FFFF
DELAY1 DEX
CPX #$8014 STOP AT 8014
DUM BNE DELAY1
RTS
*
*
*CLRAR SCREEN FOR CT-1024 TYPE TERMINALS
CLEAR LDX #CURSOR
JSR PDATA1
BSR DELAY1 DELAY
RDOFF1 JSR RDOFF
BRA C4
*
*BREAKPOINT ENTERING ROUTINE
BREAK LDX #SF0
CPX SWIJMP BREAKPOINTS ALREADY IN USE?
BEQ INUSE
INX
BREAK0 BSR STO1
JSR BADDR
STX BKPT
LDAA 0,X
STAA BKLST
LDAA #$3F
STAA 0,X
LDX #SF0
BSR STO1
JMP CONTR1
INUSE LDX BKPT
LDAA BKLST
STAA 0,X
LDX #SFE1
BRA BREAK0
*
SWISET STAA STACK+1 FIX POWER UP INTERRUPT
LDX SWIJMP
CPX #SF0
BEQ STORTN
STO LDX #SFE1
STO1 STX SWIJMP
STORTN RTS
*
PUNCH1 BSR PUNCH
BRA POFC4
*
*FORMAT END OF TAPE WITH PGM. CTR. AND S9
PNCHS9 LDX #$A049
STX ENDA
DEX
BSR PUNCH2
LDX #S9
PDAT JSR PDATA1
POFC4 BSR PNCHOF
BSR DELAY
C4 JMP CONTRL
*
RDON COM PORECH DISABLE ECHO FOR ACIA
LDAA #$11 RON CHAR.
LDAB #$20 STROBE CHAR
BSR STROBE
JSR ISACIA CHECK TO SEE IF PIA
BEQ RTNN
LDAA #$3C DISABLE PIA ECHO IF PIA
STAA 3,X
RTNN RTS
*
RDOFF LDAA #$13 TURN READER OFF
LDAB #$10
BRA STROBE
*
PNCHON LDAA #$12
LDAB #4
BRA STROBE
*
PNCHOF LDAA #$14
LDAB #$8
*
*PIA STROBING ROUTINE FOR PUNCH/READ ON/OFF
STROBE JSR OUTCH
JSR GETPT1
* BEQ RTN1
BRA RTN1
*
* New code for stack dump
*
PATCH1 JSR OUT4HS IXR
JSR OUT4HS IYR
JSR OUT4HS PGM COUNTER
JMP PATCH2
* LDAA #2
* ORAB #1
* BSR STR2
* BSR STR1
* LDAA #2
* LDAB #1
STAB 0,X
BSR STR2
STR1 LDAA #6
STR2 STAA 1,X
STAB 0,X
RTN1 RTS
*
*PUNCH FROM BEGINNING ADDRESS (BEGA) THRU
*ENDING ADDRESS (ENDA)
PUNCH LDX BEGA
PUNCH2 STX TW
BSR PNCHON
PUN11 LDAA ENDA+1
SUBA TW+1
LDAB ENDA
SBCB TW
BNE PUN22
CMPA #16
BCS PUN23
PUN22 LDAA #15
PUN23 ADDA #4
STAA BYTECT
SUBA #3
STAA TEMP
*PUNCH C/R L/F NULLS S1
LDX #MTAPE1
JSR PDATA1
CLRB
*PUNCH FRAME COUNT
LDX #BYTECT
BSR PUNT2 PUNCH 2 HEX CHARACTERS
*PUNCH ADDRESS
LDX #TW
BSR PUNT2
BSR PUNT2
*PUNCH DATA
LDX TW
PUN32 BSR PUNT2 PUNCH ONE BYTE
DEC TEMP
BNE PUN32
STX TW
COMB
PSHB
TSX
BSR PUNT2 PUNCH CHECKSUM
PULB RESTORE STACK
LDX TW
DEX
CPX ENDA
BNE PUN11
RTN5 RTS
*
*PUNCH 2 HEX CHAR, UPDATE CHECKSUM
PUNT2 ADDB 0,X
JMP OUT2H OUTPUT 2 HEX CHAR AND RTS
*
*COMMAND TABLE
TABLE FCB 'G GOTO
FDB GOTO
FCB 'Z GOTO PROM
FDB PROM
FCB 'M MEMORY EXAM AND CHANGE
FDB CHANGE
FCB 'F BYTE SEARCH
FDB SEARCH
FCB 'R REGISTER DUMP
FDB PRINT
FCB 'J JUMP
FDB JUMP
FCB 'C CLEAR SCREEN
FDB CLEAR
FCB 'D DISK BOOT
FDB DISK
FCB 'B BREAKPOINT
FDB BREAK
FCB 'O OPTIONAL PORT
FDB OPTL
TABLE1 FCB 'P ASCII PUNCH
FDB PUNCH1
FCB 'L ASCII LOAD
FDB LOAD
TABEND FCB 'E END OF TAPE
FDB PNCHS9
*
ORG $E3F8
FDB IRQV IRQ VECTOR
FDB SFE SOFTWARE INTERRUPT
FDB NMIV NMI VECTOR
FDB START RESTART VECTOR
*
ORG $A048
FDB START
END

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