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/aes3rx/trunk/temp-test-bench/rx-test.vhd
0,0 → 1,222
 
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:17:15 10/10/2008
-- Design Name: receiver
-- Module Name: C:/Xilinx92i/projects/citac/tb_rx.vhd
-- Project Name: citac
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: receiver
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.numeric_std.ALL;
use ieee.math_real.all; -- for UNIFORM, TRUNC
 
ENTITY tb_rx_vhd IS
END tb_rx_vhd;
 
ARCHITECTURE behavior OF tb_rx_vhd IS
 
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT aes3rx
generic (
reg_width : integer := 5
);
port (
clk : in std_logic; -- master clock
aes3 : in std_logic; -- input
reset : in std_logic; -- synchronous reset
--ch_a : out std_logic_vector(27 downto 0) := (others => '0'); -- channel A output register
--ch_b : out std_logic_vector(27 downto 0) := (others => '0'); -- channel B output register
--ch_a_w: out std_logic := '0'; -- channel A reg has new data (active high for one clk period)
--ch_b_w: out std_logic := '0'; -- channel B reg has new data (active high for one clk period)
sdata : out std_logic := '0';
sclk : out std_logic := '0';
bsync : out std_logic := '0'; -- block start (active high for one clk period)
fsync : out std_logic := '0';
active: out std_logic := '0' -- receiver has valid data on its outputs
);
end component;
--Inputs
SIGNAL CLK_50MHZ : std_logic := '0';
SIGNAL RX : std_logic := '0';
 
--Outputs
-- SIGNAL active : std_logic;
-- SIGNAL sdata : std_logic;
-- SIGNAL sclk : std_logic;
-- SIGNAL fsync : std_logic;
-- signal bsync : std_logic;
constant PERIOD : time := 20ns;
constant DUTY_CYCLE : real := 0.5;
constant OFFSET : time := 100 ns;
type INT_ARRAY is array (integer range <>) of integer;
shared variable vals : INT_ARRAY(0 to 191);
shared variable S : time := 81.4 ns;-- 160 ns;
shared variable M : time := 162.7 ns; -- 340 ns;
shared variable L : time := 244.1 ns; -- 480 ns;
procedure vector2aes(vector : in std_logic_vector (23 downto 0); signal aes : inout std_logic) is
begin
for i in 0 to 23 loop
if vector(i) = '0' then
aes <= not aes;
wait for M;
elsif vector(i) = '1' then
aes <= not aes;
wait for S;
aes <= not aes;
wait for S;
end if;
end loop;
end procedure;
procedure generate_block(pcm_data : in INT_ARRAY(0 to 191); signal aes : inout std_logic; signal curr_val : out std_logic_vector(23 downto 0)) is
begin
-- Z preamble
aes <= not aes;
wait for L;
aes <= not aes;
wait for S;
aes <= not aes;
wait for S;
aes <= not aes;
wait for L;
 
vector2aes(conv_std_logic_vector(pcm_data(0), 24), aes);
curr_val <= conv_std_logic_vector(pcm_data(0), 24);
 
aes <= not aes; -- 1.5
wait for M;
aes <= not aes; -- 1.5
wait for M;
aes <= not aes; -- 1.5
wait for M;
aes <= not aes; -- 1.5
wait for M;
for i in 1 to 191 loop
if i mod 2 /= 0 then --B subframe
--Y preamble
aes <= not aes; -- 1.5
wait for L;
aes <= not aes; -- 1.5
wait for M;
aes <= not aes; -- 3
wait for S;
aes <= not aes; -- 3.5
wait for M;
else --A subframe
--X preamble
aes <= not aes; -- 1.5
wait for L;
aes <= not aes;
wait for L;
aes <= not aes;
wait for S;
aes <= not aes;
wait for S;
end if;
curr_val <= conv_std_logic_vector(pcm_data(i), 24);
 
vector2aes(conv_std_logic_vector(pcm_data(i), 24), aes);
 
aes <= not aes; -- 1.5
wait for M;
aes <= not aes; -- 1.5
wait for M;
aes <= not aes; -- 1.5
wait for M;
aes <= not aes; -- 1.5
wait for M;
end loop;
end procedure;
shared variable seed1 : positive;
shared variable seed2 : positive;
shared variable rand : real;
signal curr_val : std_logic_vector(23 downto 0);
 
BEGIN
 
-- Instantiate the Unit Under Test (UUT)
uut: aes3rx PORT MAP(
clk => CLK_50MHZ,
aes3 => RX,
reset => '0'
--bsync => bsync
--bsync => bsync
);
PROCESS -- clock process for CLK_50MHZ
BEGIN
WAIT for OFFSET;
CLOCK_LOOP : LOOP
CLK_50MHZ <= '0';
WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE));
CLK_50MHZ <= '1';
WAIT FOR (PERIOD * DUTY_CYCLE);
END LOOP CLOCK_LOOP;
END PROCESS;
 
tb : PROCESS
BEGIN
wait for 100 ns;
for i in 0 to 191 loop
if i = 0 then
vals(i) := 0;
else
vals(i) := 1;
end if;
end loop;
generate_block(vals, RX, curr_val);
for i in 0 to 191 loop
if i = 0 then
vals(i) := 0;
else
vals(i) := vals(i-1) + 10000;
end if;
end loop;
generate_block(vals, RX, curr_val);
-- Wait 100 ns for global reset to finish
wait for 100 ns;
wait; -- will wait forever
END PROCESS;
 
END;
/aes3rx/trunk/aes3rx.vhd
0,0 → 1,221
----------------------------------------------------------------------------------
-- Company: Czech Television
-- Engineer: Petr Nohavica
--
-- Create Date: 09:02:45 05/09/2009
-- Module Name: aes3rx - Behavioral
-- Project Name: AES3 minimalistic receiver
-- Target Devices: Spartan 3
-- Tool versions: ISE 10.1
--
-- Revision:
-- Revision 0.01 - File Created
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity aes3rx is
generic (
reg_width : integer := 5
);
port (
clk : in std_logic; -- master clock
aes3 : in std_logic; -- input
reset : in std_logic; -- synchronous reset
--ch_a : out std_logic_vector(27 downto 0) := (others => '0'); -- channel A output register
--ch_b : out std_logic_vector(27 downto 0) := (others => '0'); -- channel B output register
--ch_a_w: out std_logic := '0'; -- channel A reg has new data (active high for one clk period)
--ch_b_w: out std_logic := '0'; -- channel B reg has new data (active high for one clk period)
sdata : out std_logic := '0';
sclk : out std_logic := '0';
bsync : out std_logic := '0'; -- block start (active high for one clk period)
fsync : out std_logic := '0';
active: out std_logic := '0' -- receiver has valid data on its outputs
);
end aes3rx;
 
architecture Behavioral of aes3rx is
constant X_PREAMBLE : std_logic_vector(7 downto 0) := "01000111";
constant Y_PREAMBLE : std_logic_vector(7 downto 0) := "00100111";
constant Z_PREAMBLE : std_logic_vector(7 downto 0) := "00010111";
signal aes3_sync : std_logic_vector(3 downto 0) := (others => '0'); -- input shift reg for double sampling, change detection and input delaying
signal change : std_logic := '0'; -- signal signifying a change on the input
signal aes3_clk : std_logic := '0'; -- recovered clock signal (actually a stream of pulses on supposed clock edges for implementation on single edge driven FFs)
signal decoder_shift : std_logic_vector(7 downto 0) := (others => '0');
signal align_counter : std_logic := '0';
signal clk_counter : std_logic_vector(reg_width - 1 downto 0) := (others => '0'); -- counter for aes3 clock regeneration
signal dur_counter : std_logic_vector(reg_width + 1 downto 0) := (others => '0'); -- counts durration (in clk periods) of current input invariant state (i.e. from "edge to edge")
signal upd_timer : std_logic_vector(5 downto 0) := (others => '0'); -- timer counting input changes
signal reg_reset : std_logic := '0'; -- resets reg_shortest on upd_timer overflow
signal reg_shortest : std_logic_vector(reg_width - 1 downto 0) := (others => '1'); -- stores durration of shortest measured input invariant state
signal reg_shortest_ref : std_logic_vector(reg_width - 1 downto 0) := (others => '1'); -- copied from reg_shortest on update counter overflows, serves as reference for aes3 clock regeneration
signal sdata_int : std_logic := '0';
signal bsync_int : std_logic := '0';
signal fsync_int : std_logic := '0';
signal sync_ok : std_logic := '0';
signal active_int : std_logic := '0';
signal timeout : std_logic := '1';
begin
 
------------------------------------------
-- input_shift_reg_proc
-- Carries out input double sampling in
-- order to avoid metastable states on FFs
-- and creation of delayed signals for
-- change detector (1 clk period) and
-- decoder (2 clk periods)
------------------------------------------
input_shift_reg_proc: process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
aes3_sync <= (others => '0');
else
aes3_sync <= aes3 & aes3_sync(3 downto 1); -- synthetizes shift reg
end if;
end if;
end process;
------------------------------------------
-- change_detect_proc
-- Detects edge on sampled input in the
-- way of comparsion of delayed input
-- and current state on XOR gate
------------------------------------------
change_detect_proc: process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
change <= '0';
else
change <= '0';
if aes3_sync(2) /= aes3_sync(1) then
change <= '1';
end if;
end if;
end if;
end process;
shortest_pulse_dur_cnt_proc: process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
reg_shortest <= (others => '1');
dur_counter <= (others => '0');
else
if change = '1' then
timeout <= '0';
if dur_counter < reg_shortest then
reg_shortest <= dur_counter(reg_width - 1 downto 0);
end if;
dur_counter <= (others => '0');
elsif dur_counter = 2**(reg_width + 2) - 1 then
timeout <= '1';
else
dur_counter <= dur_counter + 1;
end if;
if reg_reset = '1' then
reg_shortest <= (others => '1');
end if;
end if;
end if;
end process;
register_update_timer_proc: process (clk)
begin
if clk'event and clk = '1' then
reg_reset <= '0';
if reset = '1' then
reg_shortest_ref <= (others => '1');
upd_timer <= (others => '0');
else
if change = '1' then
if upd_timer = 63 then
reg_shortest_ref <= reg_shortest;
reg_reset <= '1';
end if;
upd_timer <= upd_timer + 1;
end if;
end if;
end if;
end process;
 
aes3_clk_regen_proc: process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
clk_counter <= (others => '0');
aes3_clk <= '0';
else
clk_counter <= clk_counter - 1;
aes3_clk <= '0';
if change = '1' then
clk_counter <= '0' & reg_shortest_ref(reg_width - 1 downto 1);
elsif clk_counter = 0 then
clk_counter <= reg_shortest_ref;
aes3_clk <= '1';
end if;
end if;
end if;
end process;
decoder_shift_reg_proc: process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
decoder_shift <= (others => '0');
elsif aes3_clk = '1' then
decoder_shift <= aes3_sync(0) & decoder_shift(7 downto 1);
end if;
end if;
end process;
decoder_proc: process (clk)
begin
if clk'event and clk = '1' then
if timeout = '1' then
sync_ok <= '0';
end if;
if aes3_clk = '1' then
align_counter <= not align_counter;
if decoder_shift = X_PREAMBLE or decoder_shift = not X_PREAMBLE then
fsync_int <= '1';
bsync_int <= '0';
sync_ok <= '1';
align_counter <= '0';
elsif decoder_shift = Y_PREAMBLE or decoder_shift = not Y_PREAMBLE then
fsync_int <= '0';
bsync_int <= '0';
sync_ok <= '1';
align_counter <= '0';
elsif decoder_shift = Z_PREAMBLE or decoder_shift = not Z_PREAMBLE then
fsync_int <= '1';
bsync_int <= '1';
sync_ok <= '1';
align_counter <= '0';
end if;
if align_counter = '1' then
if decoder_shift(1) = decoder_shift(0) then
sdata_int <= '0';
else
sdata_int <= '1';
end if;
end if;
end if;
end if;
end process;
active_int <= sync_ok and not timeout;
sclk <= align_counter and active_int;
sdata <= sdata_int and active_int;
fsync <= fsync_int and active_int;
bsync <= bsync_int and active_int;
active <= active_int;
end Behavioral;
 

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