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/trunk/src/rofactor.vhd
0,0 → 1,119
--------------------------------------------------------------------------------------------------- |
-- |
-- Title : rofactor |
-- Design : cfft |
-- Author : ZHAO Ming |
-- email : sradio@opencores.org |
-- |
--------------------------------------------------------------------------------------------------- |
-- |
-- File : rofactor.vhd |
-- Generated : Thu Oct 3 00:12:16 2002 |
-- |
--------------------------------------------------------------------------------------------------- |
-- |
-- Description : Generate FFT rotation factor |
-- |
--------------------------------------------------------------------------------------------------- |
-- |
-- Revisions : 0 |
-- Revision Number : 1 |
-- Version : 1.1.0 |
-- Date : Oct 17 2002 |
-- Modifier : ZHAO Ming |
-- Desccription : Data width configurable |
-- |
--------------------------------------------------------------------------------------------------- |
-- |
-- Revisions : 0 |
-- Revision Number : 2 |
-- Version : 1.2.0 |
-- Date : Oct 18 2002 |
-- Modifier : ZHAO Ming |
-- Desccription : Data width configurable |
-- |
--------------------------------------------------------------------------------------------------- |
|
|
library IEEE; |
use IEEE.STD_LOGIC_1164.all; |
use ieee.std_logic_arith.all; |
use ieee.std_logic_unsigned.all; |
use ieee.std_logic_signed.all; |
|
entity rofactor is |
generic ( |
POINT : Natural; |
STAGE : Natural |
); |
port( |
clk : in STD_LOGIC; |
rst : in STD_LOGIC; |
start : in STD_LOGIC; |
inv : in std_logic; |
-- step : in STD_LOGIC_VECTOR(2 downto 0); |
angle : out STD_LOGIC_VECTOR(2*STAGE-1 downto 0) |
); |
end rofactor; |
|
|
architecture rofactor of rofactor is |
signal counter : std_logic_vector( STAGE*2-1 downto 0 ):=( others=>'0' ); |
signal inc,iinc,phase : std_logic_vector( STAGE*2-1 downto 0 ):=( others=>'0' ); |
signal mask : std_logic_vector( STAGE*2-1 downto 0 ):=( others=>'0' ); |
begin |
angle<=phase; |
|
count:process( clk,rst ) |
begin |
if rst='1' then |
counter<=( others=>'0' ); |
inc<=( others=>'0' ); |
mask<=( others=>'0' ); |
elsif clk'event and clk='1' then |
if start='1' then |
counter<=( others=>'0' ); |
mask<=( others=>'0' ); |
-- state<="000"; |
if inv='1' then |
inc<=CONV_STD_LOGIC_VECTOR(1,STAGE*2); |
else |
inc<=CONV_STD_LOGIC_VECTOR(-1,STAGE*2); |
end if; |
else |
counter<=unsigned(counter)+1; |
if signed(counter)=-1 then |
inc<=inc(STAGE*2-3 downto 0 )&"00"; |
mask<="11"&mask( STAGE*2-1 downto 2 ); |
-- if state/="100" then |
-- state<=state+1; |
-- end if; |
end if; |
end if; |
end if; |
end process count; |
|
output : process( clk, rst ) |
begin |
if rst='1' then |
phase<=( others=>'0' ); |
iinc<=( others=>'0' ); |
elsif clk'event and clk='1' then |
if start='1' then |
iinc<=( others=>'0' ); |
phase<=( others=>'0' ); |
else |
if unsigned(counter( 1 downto 0 ))=3 then |
phase<=( others=>'0' ); |
else |
phase<=unsigned(phase)+unsigned(iinc); |
end if; |
if signed(counter or mask)=-1 then |
iinc<=(others=>'0'); |
elsif unsigned(counter( 1 downto 0 ))=3 then |
iinc<=unsigned(iinc)+unsigned(inc); |
end if; |
end if; |
end if; |
end process output; |
end rofactor; |
/trunk/src/cfft.vhd
0,0 → 1,335
--------------------------------------------------------------------------------------------------- |
-- |
-- Title : cfft |
-- Design : cfft |
-- Author : ZHAO Ming |
-- email : sradio@opencores.org |
-- |
--------------------------------------------------------------------------------------------------- |
-- |
-- File : cfft.vhd |
-- Generated : Thu Oct 3 03:03:58 2002 |
-- |
--------------------------------------------------------------------------------------------------- |
-- |
-- Description : 4-based 1024 point FFT input 12 bit Output 14 bit with |
-- limit and overfall processing internal |
-- |
-- The gain is 0.0287 for FFT and 29.4 for IFFT |
-- |
-- The output is 4-based reversed ordered, it means |
-- a0a1a2a3a4a5a6a7a8a9 => a8a9a6a7a4a5aa2a3a0a1 |
-- |
-- |
--------------------------------------------------------------------------------------------------- |
|
|
--------------------------------------------------------------------------------------------------- |
-- |
-- port : |
-- clk : main clk -- I have test 90M with Xilinx virtex600E |
-- rst : globe reset -- '1' for reset |
-- start : start fft -- one clock '1' before data input |
-- inv : '0' for fft and '1' for ifft, it is sampled when start is '1' |
-- Iin,Qin : data input-- following start immediately, input data |
-- -- power should not be too big |
-- inputbusy : if it change to '0' then next fft is enable |
-- outdataen : when it is '1', the valid data is output |
-- Iout,Qout : fft data output when outdataen is '1' |
-- |
--------------------------------------------------------------------------------------------------- |
-- |
-- Revisions : 0 |
-- Revision Number : 1 |
-- Version : 1.1.0 |
-- Date : Oct 17 2002 |
-- Modifier : ZHAO Ming |
-- Desccription : Data width configurable |
-- |
--------------------------------------------------------------------------------------------------- |
-- |
-- Revisions : 0 |
-- Revision Number : 2 |
-- Version : 1.2.0 |
-- Date : Oct 18 2002 |
-- Modifier : ZHAO Ming |
-- Desccription : Point configurable |
-- FFT Gain IFFT GAIN |
-- 256 0.0698 17.9 |
-- 1024 0.0287 29.4 |
-- 4096 0.0118 48.2742 |
-- |
-- |
--------------------------------------------------------------------------------------------------- |
|
library IEEE; |
use IEEE.STD_LOGIC_1164.all; |
use IEEE.STD_LOGIC_ARITH.all; |
|
entity cfft is |
generic ( |
WIDTH : Natural; |
POINT : Natural; |
STAGE : Natural -- STAGE=log4(POINT) |
); |
port( |
clk : in STD_LOGIC; |
rst : in STD_LOGIC; |
start : in STD_LOGIC; |
inv : in std_logic; |
Iin : in STD_LOGIC_VECTOR(WIDTH-1 downto 0); |
Qin : in STD_LOGIC_VECTOR(WIDTH-1 downto 0); |
inputbusy : out STD_LOGIC; |
outdataen : out STD_LOGIC; |
Iout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0); |
Qout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0) |
); |
end cfft; |
|
|
architecture cfft of cfft is |
|
component address |
generic ( |
WIDTH : Natural; |
POINT : Natural; |
STAGE : Natural |
); |
port( |
clk : in STD_LOGIC; |
rst : in STD_LOGIC; |
start : in STD_LOGIC; |
Iin : in std_logic_vector( WIDTH-1 downto 0 ); |
Qin : in std_logic_vector( WIDTH-1 downto 0 ); |
fftI : in std_logic_vector( WIDTH-1 downto 0 ); |
fftQ : in std_logic_vector( WIDTH-1 downto 0 ); |
wdataI : out std_logic_vector( WIDTH-1 downto 0 ); |
wdataQ : out std_logic_vector( WIDTH-1 downto 0 ); |
raddr : out STD_LOGIC_VECTOR(2*STAGE-1 downto 0); |
waddr : out STD_LOGIC_VECTOR(2*STAGE-1 downto 0); |
wen : out std_logic; |
factorstart : out STD_LOGIC; |
cfft4start : out STD_LOGIC; |
outdataen : out std_logic; |
inputbusy : out std_logic |
); |
end component; |
|
component blockdram |
generic( |
depth: integer; |
Dwidth: integer; |
Awidth: integer |
); |
port( |
addra: IN std_logic_VECTOR(Awidth-1 downto 0); |
clka: IN std_logic; |
addrb: IN std_logic_VECTOR(Awidth-1 downto 0); |
clkb: IN std_logic; |
dia: IN std_logic_VECTOR(Dwidth-1 downto 0); |
wea: IN std_logic; |
dob: OUT std_logic_VECTOR(Dwidth-1 downto 0)); |
end component; |
|
component cfft4 |
generic ( |
WIDTH : Natural |
); |
port( |
clk : in STD_LOGIC; |
rst : in STD_LOGIC; |
start : in STD_LOGIC; |
inv : in std_logic; |
I : in STD_LOGIC_VECTOR(WIDTH-1 downto 0); |
Q : in STD_LOGIC_VECTOR(WIDTH-1 downto 0); |
Iout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0); |
Qout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0) |
); |
end component; |
|
component div4limit |
generic ( |
WIDTH : Natural |
); |
port( |
clk : in std_logic; |
D : in STD_LOGIC_VECTOR(WIDTH+3 downto 0); |
Q : out STD_LOGIC_VECTOR(WIDTH-1 downto 0) |
); |
end component; |
|
component mulfactor |
generic ( |
WIDTH : Natural; |
STAGE : Natural |
); |
port( |
clk : in STD_LOGIC; |
rst : in STD_LOGIC; |
angle : in signed(2*STAGE-1 downto 0); |
I : in signed(WIDTH+1 downto 0); |
Q : in signed(WIDTH+1 downto 0); |
Iout : out signed(WIDTH+3 downto 0); |
Qout : out signed(WIDTH+3 downto 0) |
); |
end component; |
|
component rofactor |
generic ( |
POINT : Natural; |
STAGE : Natural |
); |
port( |
clk : in STD_LOGIC; |
rst : in STD_LOGIC; |
start : in STD_LOGIC; |
inv : in std_logic; |
angle : out STD_LOGIC_VECTOR(2*STAGE-1 downto 0) |
); |
end component; |
signal wea,cfft4start,factorstart:std_logic:='0'; |
signal wdataI,wdataQ,fftI,fftQ,Iramout,Qramout:std_logic_vector(WIDTH-1 downto 0):=(others=>'0'); |
signal waddr,raddr:std_logic_vector( 2*STAGE-1 downto 0):=(others=>'0'); |
signal Icfft4out,Qcfft4out:std_logic_vector( WIDTH+1 downto 0):=(others=>'0'); |
signal angle:std_logic_vector( 2*STAGE-1 downto 0 ):=( others=>'0'); |
signal Imulout,Qmulout:signed( WIDTH+3 downto 0):=(others=>'0'); |
signal inv_reg:std_logic:='0'; |
|
begin |
|
Aaddress:address |
generic map ( |
WIDTH=>WIDTH, |
POINT=>POINT, |
STAGE=>STAGE |
) |
port map ( |
clk=>clk, |
rst=>rst, |
start=>start, |
Iin=>Iin, |
Qin=>Qin, |
fftI=>fftI, |
fftQ=>fftQ, |
wdataI=>wdataI, |
wdataQ=>wdataQ, |
raddr=>raddr, |
waddr=>waddr, |
wen=>wea, |
factorstart=>factorstart, |
cfft4start=>cfft4start, |
outdataen=>outdataen, |
inputbusy=>inputbusy |
); |
|
Iram:blockdram |
generic map ( |
depth=>POINT, |
Dwidth=>WIDTH, |
Awidth=>2*STAGE |
) |
port map ( |
addra=>waddr, |
clka=>clk, |
addrb=>raddr, |
clkb=>clk, |
dia=>wdataI, |
wea=>wea, |
dob=>Iramout |
); |
|
Qram:blockdram |
generic map ( |
depth=>POINT, |
Dwidth=>WIDTH, |
Awidth=>2*STAGE |
) |
port map ( |
addra=>waddr, |
clka=>clk, |
addrb=>raddr, |
clkb=>clk, |
dia=>wdataQ, |
wea=>wea, |
dob=>Qramout |
); |
|
acfft4:cfft4 |
generic map ( |
WIDTH=>WIDTH |
) |
port map ( |
clk=>clk, |
rst=>rst, |
start=>cfft4start, |
inv=>inv_reg, |
I=>Iramout, |
Q=>Qramout, |
Iout=>Icfft4out, |
Qout=>Qcfft4out |
); |
|
Iout<=Icfft4out; |
Qout<=Qcfft4out; |
|
Ilimit:div4limit |
generic map ( |
WIDTH=>WIDTH |
) |
port map ( |
clk=>clk, |
D=>std_logic_vector(Imulout), |
Q=>fftI |
); |
Qlimit:div4limit |
generic map ( |
WIDTH=>WIDTH |
) |
port map ( |
clk=>clk, |
D=>std_logic_vector(Qmulout), |
Q=>fftQ |
); |
|
amulfactor:mulfactor |
generic map ( |
WIDTH=>WIDTH, |
STAGE=>STAGE |
) |
port map ( |
clk=>clk, |
rst=>rst, |
angle=>signed(angle), |
I=>signed(Icfft4out), |
Q=>signed(Qcfft4out), |
Iout=>Imulout, |
Qout=>Qmulout |
); |
|
arofactor:rofactor |
generic map ( |
POINT=>POINT, |
STAGE=>STAGE |
) |
port map ( |
clk=>clk, |
rst=>rst, |
start=>factorstart, |
inv=>inv_reg, |
angle=>angle |
); |
|
process( clk, rst ) |
begin |
if rst='1' then |
inv_reg<='0'; |
elsif clk'event and clk='1' then |
if start='1' then |
inv_reg<=inv; |
end if; |
end if; |
end process; |
|
|
|
end cfft; |
/trunk/src/p2r_CordicPipe.vhd
0,0 → 1,170
-- |
-- file: p2r_CordicPipe.vhd |
-- author: Richard Herveille |
-- rev. 1.0 initial release |
-- |
|
-- |
-- This file is come from WWW.OPENCORES.ORG |
|
--------------------------------------------------------------------------------------------------- |
-- |
-- Title : p2r_CordicPipe |
-- Design : cfft |
-- |
--------------------------------------------------------------------------------------------------- |
-- |
-- File : p2r_CordicPipe.vhd |
-- |
--------------------------------------------------------------------------------------------------- |
-- |
-- Description : Cordic arith pilepline |
-- |
--------------------------------------------------------------------------------------------------- |
-- |
-- Revisions : 0 |
-- Revision Number : 1 |
-- Version : 1 |
-- Date : Oct 17 2002 |
-- Modifier : ZHAO Ming <sradio@opencores.org> |
-- Desccription : Data width configurable |
-- |
--------------------------------------------------------------------------------------------------- |
|
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
|
entity p2r_CordicPipe is |
generic( |
WIDTH : natural := 16; |
PIPEID : natural := 1 |
); |
port( |
clk : in std_logic; |
ena : in std_logic; |
|
Xi : in signed(WIDTH -1 downto 0); |
Yi : in signed(WIDTH -1 downto 0); |
Zi : in signed(19 downto 0); |
|
Xo : out signed(WIDTH -1 downto 0); |
Yo : out signed(WIDTH -1 downto 0); |
Zo : out signed(19 downto 0) |
); |
end entity p2r_CordicPipe; |
|
architecture dataflow of p2r_CordicPipe is |
|
-- |
-- functions |
-- |
|
-- Function CATAN (constante arc-tangent). |
-- This is a lookup table containing pre-calculated arc-tangents. |
-- 'n' is the number of the pipe, returned is a 20bit arc-tangent value. |
-- The numbers are calculated as follows: Z(n) = atan(1/2^n) |
-- examples: |
-- 20bit values => 2^20 = 2pi(rad) |
-- 1(rad) = 2^20/2pi = 166886.053.... |
-- n:0, atan(1/1) = 0.7853...(rad) |
-- 0.7853... * 166886.053... = 131072(dec) = 20000(hex) |
-- n:1, atan(1/2) = 0.4636...(rad) |
-- 0.4636... * 166886.053... = 77376.32(dec) = 12E40(hex) |
-- n:2, atan(1/4) = 0.2449...(rad) |
-- 0.2449... * 166886.053... = 40883.52(dec) = 9FB3(hex) |
-- n:3, atan(1/8) = 0.1243...(rad) |
-- 0.1243... * 166886.053... = 20753.11(dec) = 5111(hex) |
-- |
function CATAN(n :natural) return integer is |
variable result :integer; |
begin |
case n is |
when 0 => result := 16#020000#; |
when 1 => result := 16#012E40#; |
when 2 => result := 16#09FB4#; |
when 3 => result := 16#05111#; |
when 4 => result := 16#028B1#; |
when 5 => result := 16#0145D#; |
when 6 => result := 16#0A2F#; |
when 7 => result := 16#0518#; |
when 8 => result := 16#028C#; |
when 9 => result := 16#0146#; |
when 10 => result := 16#0A3#; |
when 11 => result := 16#051#; |
when 12 => result := 16#029#; |
when 13 => result := 16#014#; |
when 14 => result := 16#0A#; |
when 15 => result := 16#05#; |
when 16 => result := 16#03#; |
when 17 => result := 16#01#; |
when others => result := 16#0#; |
end case; |
return result; |
end CATAN; |
|
-- function Delta is actually an arithmatic shift right |
-- This strange construction is needed for compatibility with Xilinx WebPack |
function Delta(Arg : signed; Cnt : natural) return signed is |
variable tmp : signed(Arg'range); |
constant lo : integer := Arg'high -cnt +1; |
begin |
for n in Arg'high downto lo loop |
tmp(n) := Arg(Arg'high); |
end loop; |
for n in Arg'high -cnt downto 0 loop |
tmp(n) := Arg(n +cnt); |
end loop; |
return tmp; |
end function Delta; |
|
function AddSub(dataa, datab : in signed; add_sub : in std_logic) return signed is |
begin |
if (add_sub = '1') then |
return dataa + datab; |
else |
return dataa - datab; |
end if; |
end; |
|
-- |
-- ARCHITECTURE BODY |
-- |
signal dX, Xresult : signed(WIDTH -1 downto 0); |
signal dY, Yresult : signed(WIDTH -1 downto 0); |
signal atan, Zresult : signed(19 downto 0); |
|
signal Zneg, Zpos : std_logic; |
|
begin |
|
dX <= Delta(Xi, PIPEID); |
dY <= Delta(Yi, PIPEID); |
atan <= conv_signed( catan(PIPEID), 20); |
|
-- generate adder structures |
Zneg <= Zi(19); |
Zpos <= not Zi(19); |
|
-- xadd |
Xresult <= AddSub(Xi, dY, Zneg); |
|
-- yadd |
Yresult <= AddSub(Yi, dX, Zpos); |
|
-- zadd |
Zresult <= AddSub(Zi, atan, Zneg); |
|
gen_regs: process(clk) |
begin |
if(clk'event and clk='1') then |
if (ena = '1') then |
Xo <= Xresult; |
Yo <= Yresult; |
Zo <= Zresult; |
end if; |
end if; |
end process; |
|
end architecture dataflow; |
/trunk/src/address.vhd
0,0 → 1,305
--------------------------------------------------------------------------------------------------- |
-- |
-- Title : address |
-- Design : cfft |
-- Author : ZHAO Ming |
-- email : sradio@opencores.org |
-- |
--------------------------------------------------------------------------------------------------- |
-- |
-- File : address.vhd |
-- Generated : Thu Oct 3 01:44:47 2002 |
-- |
--------------------------------------------------------------------------------------------------- |
-- |
-- Description : Generate RAM read write address and start finish control signal |
-- |
--------------------------------------------------------------------------------------------------- |
-- |
-- Revisions : 0 |
-- Revision Number : 1 |
-- Version : 1.1.0 |
-- Date : Oct 17 2002 |
-- Modifier : ZHAO Ming |
-- Desccription : Data width configurable |
-- |
--------------------------------------------------------------------------------------------------- |
-- |
-- Revisions : 0 |
-- Revision Number : 2 |
-- Version : 1.2.0 |
-- Date : Oct 18 2002 |
-- Modifier : ZHAO Ming |
-- Desccription : Data width configurable |
-- |
--------------------------------------------------------------------------------------------------- |
-- |
-- Revisions : 1 |
-- Revision Number : 2 |
-- Version : 1.2.1 |
-- Date : Oct 19 2002 |
-- Modifier : ZHAO Ming |
-- Desccription : modified fuction counter2address for syn |
-- add rmask1,rmask2,wmask1,wmask2 signal |
-- |
--------------------------------------------------------------------------------------------------- |
|
|
library IEEE; |
use IEEE.STD_LOGIC_1164.all; |
use IEEE.STD_LOGIC_ARITH.all; |
use IEEE.std_logic_unsigned.all; |
use IEEE.std_logic_signed.all; |
|
entity address is |
generic ( |
WIDTH : Natural; |
POINT : Natural; |
STAGE : Natural |
); |
port( |
clk : in STD_LOGIC; |
rst : in STD_LOGIC; |
start : in STD_LOGIC; |
Iin : in std_logic_vector( WIDTH-1 downto 0 ); |
Qin : in std_logic_vector( WIDTH-1 downto 0 ); |
fftI : in std_logic_vector( WIDTH-1 downto 0 ); |
fftQ : in std_logic_vector( WIDTH-1 downto 0 ); |
wdataI : out std_logic_vector( WIDTH-1 downto 0 ); |
wdataQ : out std_logic_vector( WIDTH-1 downto 0 ); |
raddr : out STD_LOGIC_VECTOR(STAGE*2-1 downto 0); |
waddr : out STD_LOGIC_VECTOR(STAGE*2-1 downto 0); |
wen : out std_logic; |
factorstart : out STD_LOGIC; |
cfft4start : out STD_LOGIC; |
outdataen : out std_logic; |
inputbusy : out std_logic |
); |
end address; |
|
|
architecture address of address is |
|
|
-- function counter2addr(counter : std_logic_vector; state:std_logic_vector) return std_logic_vector is |
-- variable result :std_logic_vector(counter'range); |
-- variable istate : Natural; |
-- begin |
-- istate:=CONV_INTEGER(unsigned(state)); |
-- if istate=0 then |
-- result := counter( 1 downto 0 )&counter( counter'high downto 2 ); |
-- elsif istate=(counter'high-1)/2 then |
-- result := counter; |
-- elsif istate<(counter'high-1)/2 then |
-- result := counter( counter'high downto counter'high-istate*2+1 )&counter( 1 downto 0 )&counter( counter'high-istate*2 downto 2 ); |
-- else |
-- result := counter; |
-- end if; |
-- return result; |
-- end counter2addr; |
|
function counter2addr( |
counter : std_logic_vector; |
mask1:std_logic_vector; |
mask2:std_logic_vector |
) return std_logic_vector is |
variable result :std_logic_vector(counter'range); |
begin |
for n in mask1'range loop |
if mask1(n)='1' then |
result( 2*n+1 downto 2*n ):=counter( 1 downto 0 ); |
elsif mask2(n)='1' and n/=STAGE-1 then |
result( 2*n+1 downto 2*n ):=counter( 2*n+3 downto 2*n+2 ); |
else |
result( 2*n+1 downto 2*n ):=counter( 2*n+1 downto 2*n ); |
end if; |
end loop; |
return result; |
end counter2addr; |
|
|
signal rstate,wstate,state:std_logic_vector( 3 downto 0 ); |
signal rmask1,rmask2,wmask1,wmask2:std_logic_vector( STAGE-1 downto 0 ); |
signal counter,wcounter,rcounter:std_logic_vector( STAGE*2-1 downto 0 ); |
signal outcounter:std_logic_vector( STAGE*2 downto 0 ); |
|
constant FFTDELAY:integer:=12+2*STAGE; |
constant FACTORDELAY:integer:=6; |
constant OUTDELAY:integer:=7; |
|
|
|
begin |
outdataen<=outcounter(STAGE*2); |
|
count:process( clk, rst ) |
begin |
if rst='1' then |
counter<=( others=>'0' ); |
state<=CONV_STD_LOGIC_VECTOR( STAGE+1,4); |
elsif clk'event and clk='1' then |
if start='1' then |
counter<=( others=>'0' ); |
state<=(others=>'0'); |
elsif unsigned(state)/=STAGE+1 then |
counter<=unsigned(counter)+1; |
if signed(counter)=-1 then |
state<=unsigned(state)+1; |
end if; |
end if; |
end if; |
end process count; |
|
readaddr:process( clk,rst ) |
begin |
if rst='1' then |
raddr<=( others=>'0' ); |
rcounter<=( others=>'0' ); |
rstate<=( others=>'0' ); |
rmask1<=( others=>'0' ); |
rmask2<=( others=>'0' ); |
elsif clk'event and clk='1' then |
if unsigned(state)=0 and signed(counter)=-1 then |
rmask1(STAGE-1)<='1'; |
rmask1(STAGE-2 downto 0)<=(others=>'0'); |
rmask2(STAGE-1)<='0'; |
rmask2(STAGE-2 downto 0)<=(others=>'1'); |
elsif signed(counter)=-1 then |
rmask1<='0'&rmask1( STAGE-1 downto 1 ); |
rmask2<='0'&rmask2( STAGE-1 downto 1 ); |
end if; |
if unsigned(state)/=STAGE+1 and signed(counter)=-1 then |
rcounter<=( others=>'0' ); |
rstate<=state; |
else |
rcounter<=unsigned(rcounter)+1; |
end if; |
raddr<=counter2addr( rcounter, rmask1, rmask2 ); |
-- modified for point configurable |
-- case rstate is |
-- when "000" => |
-- raddr<=rcounter( 1 downto 0 )&rcounter( 9 downto 2); |
-- when "001" => |
-- raddr<=rcounter( 9 downto 8 )&rcounter( 1 downto 0 )&rcounter( 7 downto 2); |
-- when "010" => |
-- raddr<=rcounter( 9 downto 6 )&rcounter( 1 downto 0 )&rcounter( 5 downto 2); |
-- when "011" => |
-- raddr<=rcounter( 9 downto 4 )&rcounter( 1 downto 0 )&rcounter( 3 downto 2); |
-- when "100" => |
-- raddr<=rcounter( 9 downto 2 )&rcounter( 1 downto 0 ); |
-- when others => |
-- raddr<=( others=> '0' ); |
-- end case; |
end if; |
end process readaddr; |
|
writeaddr:process( clk,rst ) |
begin |
if rst='1' then |
waddr<=( others=>'0' ); |
wcounter<=( others=>'0' ); |
wstate<=( others=>'0' ); |
wmask1<=( others=>'0' ); |
wmask2<=( others=>'0' ); |
elsif clk'event and clk='1' then |
if unsigned(state)=0 then |
waddr<=counter; |
else |
if UNSIGNED(rstate)=0 and unsigned(rcounter)=FFTDELAY-1 then |
wmask1(STAGE-1)<='1'; |
wmask1(STAGE-2 downto 0)<=(others=>'0'); |
wmask2(STAGE-1)<='0'; |
wmask2(STAGE-2 downto 0)<=(others=>'1'); |
elsif unsigned(rcounter)=FFTDELAY-1 then |
wmask1<='0'&wmask1( STAGE-1 downto 1 ); |
wmask2<='0'&wmask2( STAGE-1 downto 1 ); |
end if; |
if UNSIGNED(rstate)<STAGE and unsigned(rcounter)=FFTDELAY-1 then |
wcounter<=( others=>'0' ); |
wstate<=rstate; |
else |
wcounter<=unsigned(wcounter)+1; |
end if; |
waddr<=counter2addr( wcounter, wmask1, wmask2 ); |
-- modified for point configurable |
-- case wstate is |
-- when "000" => |
-- waddr<=wcounter( 1 downto 0 )&wcounter( 9 downto 2); |
-- when "001" => |
-- waddr<=wcounter( 9 downto 8 )&wcounter( 1 downto 0 )&wcounter( 7 downto 2); |
-- when "010" => |
-- waddr<=wcounter( 9 downto 6 )&wcounter( 1 downto 0 )&wcounter( 5 downto 2); |
-- when "011" => |
-- waddr<=wcounter( 9 downto 4 )&wcounter( 1 downto 0 )&wcounter( 3 downto 2); |
-- when others => |
-- waddr<=( others=> '0' ); |
-- end case; |
end if; |
end if; |
end process writeaddr; |
|
writeen : process( clk, rst ) |
begin |
if rst='1' then |
wen<='0'; |
elsif clk'event and clk='1' then |
if unsigned(state)=0 then |
wen<='1'; |
elsif unsigned(state)=1 and unsigned(counter)=0 then |
wen<='0'; |
elsif unsigned(rstate)=0 and unsigned(rcounter)=FFTDELAY then |
wen<='1'; |
elsif unsigned(rstate)=STAGE-1 and unsigned(rcounter)=FFTDELAY then |
wen<='0'; |
end if; |
end if; |
end process writeen; |
|
otherstart : process( clk, rst ) |
begin |
if rst='1' then |
factorstart<='0'; |
cfft4start<='0'; |
outcounter<=(others=>'0'); |
inputbusy<='0'; |
elsif clk'event and clk='1' then |
if start='1' then |
inputbusy<='1'; |
elsif unsigned(state)=STAGE and unsigned(counter)=FFTDELAY then |
inputbusy<='0'; |
end if; |
if unsigned(state)=1 and unsigned(counter)=0 then |
cfft4start<='1'; |
else |
cfft4start<='0'; |
end if; |
if unsigned(rstate)=0 and unsigned(rcounter)=FACTORDELAY then |
factorstart<='1'; |
else |
factorstart<='0'; |
end if; |
if unsigned(state)=STAGE and unsigned(rcounter)=OUTDELAY then |
outcounter<=CONV_STD_LOGIC_VECTOR(POINT,2*STAGE+1); |
elsif outcounter(STAGE*2)='1' then |
outcounter<=unsigned(outcounter)+1; |
end if; |
end if; |
end process otherstart; |
|
datasel : process( clk,rst ) |
begin |
if rst='1' then |
wdataI<=( others=>'0' ); |
wdataQ<=( others=>'0' ); |
elsif clk'event and clk='1' then |
if unsigned(state)=0 then |
wdataI<=Iin; |
wdataQ<=Qin; |
else |
wdataI<=fftI; |
wdataQ<=fftQ; |
end if; |
end if; |
end process datasel; |
|
end address; |
/trunk/src/div4limit.vhd
0,0 → 1,63
--------------------------------------------------------------------------------------------------- |
-- |
-- Title : div4limit |
-- Design : cfft |
-- Author : ZHAO Ming |
-- email : sradio@opencores.org |
-- |
--------------------------------------------------------------------------------------------------- |
-- |
-- File : div4limit.vhd |
-- Generated : Tue Jul 16 10:39:17 2002 |
-- |
--------------------------------------------------------------------------------------------------- |
-- |
-- Description : Div 4 Limit to 12 bit |
-- |
--------------------------------------------------------------------------------------------------- |
-- |
-- Revisions : 0 |
-- Revision Number : 1 |
-- Version : 1 |
-- Date : Oct 17 2002 |
-- Modifier : ZHAO Ming |
-- Desccription : Data width configurable |
-- |
--------------------------------------------------------------------------------------------------- |
|
library IEEE; |
use IEEE.STD_LOGIC_1164.all; |
use IEEE.STD_LOGIC_UNSIGNED.all; |
|
entity div4limit is |
generic ( |
WIDTH : Natural |
); |
port( |
clk : in std_logic; |
D : in STD_LOGIC_VECTOR(WIDTH+3 downto 0); |
Q : out STD_LOGIC_VECTOR(WIDTH-1 downto 0) |
); |
end div4limit; |
|
architecture div4limit of div4limit is |
begin |
|
process( clk ) |
variable Temp_D:std_logic_vector( WIDTH+1 downto 0 ); |
begin |
if clk'event and clk='1' then |
Temp_D:=D( WIDTH+3 downto 2 )+D(1); |
if Temp_D(WIDTH+1)='1' and Temp_D(WIDTH downto WIDTH-1)/="11" then |
Temp_D(WIDTH+1 downto WIDTH-1):="111"; |
Temp_D(WIDTH-2 downto 1):=( others=>'0' ); |
Temp_D(0):='1'; |
elsif Temp_D(WIDTH+1)='0' and Temp_D(WIDTH downto WIDTH-1)/="00" then |
Temp_D(WIDTH+1 downto WIDTH-1):="000"; |
Temp_D(WIDTH-2 downto 0):=( others=>'1' ); |
end if; |
Q<=Temp_D(WIDTH-1 downto 0 ); |
end if; |
end process; |
|
end div4limit; |
/trunk/src/cfft4.vhd
0,0 → 1,128
--------------------------------------------------------------------------------------------------- |
-- |
-- Title : cfft4 |
-- Design : cfft |
-- Author : ZHAO Ming |
-- email : sradio@opencores.org |
-- |
--------------------------------------------------------------------------------------------------- |
-- |
-- File : cfft4.vhd |
-- Generated : Wed Oct 2 15:49:06 2002 |
-- |
--------------------------------------------------------------------------------------------------- |
-- |
-- Description : 4 point fft |
-- |
--------------------------------------------------------------------------------------------------- |
-- |
-- Revisions : 0 |
-- Revision Number : 1 |
-- Version : 1.1.0 |
-- Date : Oct 17 2002 |
-- Modifier : ZHAO Ming |
-- Desccription : Data width configurable |
-- |
--------------------------------------------------------------------------------------------------- |
|
library IEEE; |
use IEEE.STD_LOGIC_1164.all; |
use IEEE.STD_LOGIC_ARITH.all; |
use IEEE.STD_LOGIC_SIGNED.all; |
|
|
entity cfft4 is |
generic ( |
WIDTH : Natural |
); |
port( |
clk : in STD_LOGIC; |
rst : in STD_LOGIC; |
start : in STD_LOGIC; |
inv : in std_logic; |
I : in STD_LOGIC_VECTOR(WIDTH-1 downto 0); |
Q : in STD_LOGIC_VECTOR(WIDTH-1 downto 0); |
Iout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0); |
Qout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0) |
); |
end cfft4; |
|
|
architecture cfft4 of cfft4 is |
type RegAtype is array (3 downto 0) of std_logic_vector(WIDTH-1 downto 0); |
type RegBtype is array (3 downto 0) of std_logic_vector(WIDTH downto 0); |
|
signal counter : std_logic_vector( 1 downto 0 ):="00"; |
signal RegAI,RegAQ : RegAtype; |
signal RegBI,RegBQ : RegBtype; |
begin |
|
|
count:process( clk,rst ) |
begin |
if rst='1' then |
counter<="00"; |
elsif clk'event and clk='1' then |
if start='1' then |
counter<="00"; |
else |
counter<=counter+1; |
end if; |
end if; |
end process count; |
|
|
------------------------------------------------------------------------- |
--0 rA(0)<=A0 rB(1)<=rA(0)-rA(2) rB(2)<=rA(1)+rA(3) B3<=rB(1)-rB(3)-- |
--1 rA(1)<=A1 rB(3)<=(-j)*(rA(1)-rA(3)) B0<=rB(0)+rB(2)-- |
--2 rA(2)<=A2 B1<=rB(1)+rB(3)-- |
--3 rA(3)<=A3 rB(0)<=rA(0)+rA(2) B2<=rB(0)-rB(2)-- |
------------------------------------------------------------------------- |
calculate:process( clk ) |
begin |
if clk'event and clk='1' then |
case counter is |
--0 rA(0)<=A0 rB(1)<=rA(0)-rA(2) rB(2)<=rA(1)+rA(3) B3<=rB(1)-rB(3)-- |
when "00" => |
RegAI(0)<=I; |
RegAQ(0)<=Q; |
RegBI(1)<=SXT(RegAI(0),WIDTH+1)-SXT(RegAI(2),WIDTH+1); |
RegBQ(1)<=SXT(RegAQ(0),WIDTH+1)-SXT(RegAQ(2),WIDTH+1); |
RegBI(2)<=SXT(RegAI(1),WIDTH+1)+SXT(RegAI(3),WIDTH+1); |
RegBQ(2)<=SXT(RegAQ(1),WIDTH+1)+SXT(RegAQ(3),WIDTH+1); |
Iout<=SXT(RegBI(1),WIDTH+2)-SXT(RegBI(3),WIDTH+2); |
Qout<=SXT(RegBQ(1),WIDTH+2)-SXT(RegBQ(3),WIDTH+2); |
--1 rA(1)<=A1 rB(3)<=(-j)*(rA(1)-rA(3)) B0<=rB(0)+rB(2)-- |
when "01" => |
RegAI(1)<=I; |
RegAQ(1)<=Q; |
if inv='0' then |
-- for fft *(-j) |
RegBI(3)<=SXT(RegAQ(1),WIDTH+1)-SXT(RegAQ(3),WIDTH+1); |
RegBQ(3)<=SXT(RegAI(3),WIDTH+1)-SXT(RegAI(1),WIDTH+1); |
else |
-- for fft *(j) |
RegBI(3)<=SXT(RegAQ(3),WIDTH+1)-SXT(RegAQ(1),WIDTH+1); |
RegBQ(3)<=SXT(RegAI(1),WIDTH+1)-SXT(RegAI(3),WIDTH+1); |
end if; |
Iout<=SXT(RegBI(0),WIDTH+2)+SXT(RegBI(2),WIDTH+2); |
Qout<=SXT(RegBQ(0),WIDTH+2)+SXT(RegBQ(2),WIDTH+2); |
--2 rA(2)<=A2 B1<=rB(1)+rB(3)-- |
when "10" => |
RegAI(2)<=I; |
RegAQ(2)<=Q; |
Iout<=SXT(RegBI(1),WIDTH+2)+SXT(RegBI(3),WIDTH+2); |
Qout<=SXT(RegBQ(1),WIDTH+2)+SXT(RegBQ(3),WIDTH+2); |
--3 rA(3)<=A3 rB(0)<=rA(0)+rA(2) B2<=rB(0)-rB(2)-- |
when "11" => |
RegAI(3)<=I; |
RegAQ(3)<=Q; |
RegBI(0)<=SXT(RegAI(0),WIDTH+1)+SXT(RegAI(2),WIDTH+1); |
RegBQ(0)<=SXT(RegAQ(0),WIDTH+1)+SXT(RegAQ(2),WIDTH+1); |
Iout<=SXT(RegBI(0),WIDTH+2)-SXT(RegBI(2),WIDTH+2); |
Qout<=SXT(RegBQ(0),WIDTH+2)-SXT(RegBQ(2),WIDTH+2); |
when others => null; |
end case; |
end if; |
end process calculate; |
end cfft4; |
/trunk/src/p2r_cordic.vhd
0,0 → 1,131
-- |
-- VHDL implementation of cordic algorithm |
-- |
-- File: p2r_cordic.vhd |
-- author: Richard Herveille |
-- rev. 1.0 initial release |
-- |
|
-- |
-- |
-- This file is come from www.opencores.org |
-- |
-- It has been modified by zhaom to enable 20 bit phase input |
-- |
--------------------------------------------------------------------------------------------------- |
-- |
-- Title : p2r_cordic |
-- Design : cfft |
-- |
--------------------------------------------------------------------------------------------------- |
-- |
-- File : p2r_cordic.vhd |
-- |
--------------------------------------------------------------------------------------------------- |
-- |
-- Description : Cordic arith pilepline |
-- |
--------------------------------------------------------------------------------------------------- |
-- |
-- Revisions : 0 |
-- Revision Number : 1 |
-- Version : 1 |
-- Date : Oct 17 2002 |
-- Modifier : ZHAO Ming <sradio@opencores.org> |
-- Desccription : Data width configurable |
-- |
--------------------------------------------------------------------------------------------------- |
|
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
|
entity p2r_cordic is |
generic( |
PIPELINE : integer := 15; |
WIDTH : integer := 16); |
port( |
clk : in std_logic; |
ena : in std_logic; |
|
Xi : in signed(WIDTH -1 downto 0); |
Yi : in signed(WIDTH -1 downto 0) := (others => '0'); |
Zi : in signed(19 downto 0); |
|
Xo : out signed(WIDTH -1 downto 0); |
Yo : out signed(WIDTH -1 downto 0) |
); |
end entity p2r_Cordic; |
|
|
architecture dataflow of p2r_cordic is |
|
-- |
-- TYPE defenitions |
-- |
type XYVector is array(PIPELINE downto 0) of signed(WIDTH -1 downto 0); |
type ZVector is array(PIPELINE downto 0) of signed(19 downto 0); |
|
-- |
-- COMPONENT declarations |
-- |
component p2r_CordicPipe |
generic( |
WIDTH : natural := 16; |
PIPEID : natural := 1 |
); |
port( |
clk : in std_logic; |
ena : in std_logic; |
|
Xi : in signed(WIDTH -1 downto 0); |
Yi : in signed(WIDTH -1 downto 0); |
Zi : in signed(19 downto 0); |
|
Xo : out signed(WIDTH -1 downto 0); |
Yo : out signed(WIDTH -1 downto 0); |
Zo : out signed(19 downto 0) |
); |
end component p2r_CordicPipe; |
|
-- |
-- SIGNALS |
-- |
signal X, Y : XYVector; |
signal Z : ZVector; |
|
-- |
-- ACHITECTURE BODY |
-- |
begin |
-- fill first nodes |
|
-- fill X |
X(0) <= Xi; |
|
-- fill Y |
Y(0) <= Yi; |
|
-- fill Z |
Z(0)(19 downto 0) <= Zi; -- modified by zhaom |
--Z(0)(3 downto 0) <= (others => '0'); -- modified by zhaom |
|
-- |
-- generate pipeline |
-- |
gen_pipe: |
for n in 1 to PIPELINE generate |
Pipe: p2r_CordicPipe |
generic map(WIDTH => WIDTH, PIPEID => n -1) |
port map ( clk, ena, X(n-1), Y(n-1), Z(n-1), X(n), Y(n), Z(n) ); |
end generate gen_pipe; |
|
-- |
-- assign outputs |
-- |
Xo <= X(PIPELINE); |
Yo <= Y(PIPELINE); |
end dataflow; |
|
|
/trunk/src/mulfactor.vhd
0,0 → 1,126
--------------------------------------------------------------------------------------------------- |
-- |
-- Title : mulfactor |
-- Design : cfft |
-- Author : ZHAO Ming |
-- email : sradio@opencores.org |
-- |
--------------------------------------------------------------------------------------------------- |
-- |
-- File : mulfactor.vhd |
-- Generated : Thu Oct 3 00:37:40 2002 |
-- |
--------------------------------------------------------------------------------------------------- |
-- |
-- Description : 360 degee complex rotation |
-- |
--------------------------------------------------------------------------------------------------- |
-- |
-- Revisions : 0 |
-- Revision Number : 1 |
-- Version : 1.1.0 |
-- Date : Oct 17 2002 |
-- Modifier : ZHAO Ming |
-- Desccription : Data width configurable |
-- |
--------------------------------------------------------------------------------------------------- |
-- |
-- Revisions : 0 |
-- Revision Number : 2 |
-- Version : 1.2.1 |
-- Date : Oct 18 2002 |
-- Modifier : ZHAO Ming |
-- Desccription : Point configurable |
-- |
--------------------------------------------------------------------------------------------------- |
|
|
library IEEE; |
use IEEE.STD_LOGIC_1164.all; |
use IEEE.STD_LOGIC_ARITH.all; |
use IEEE.STD_LOGIC_SIGNED.all; |
|
entity mulfactor is |
generic ( |
WIDTH : Natural; |
STAGE : Natural |
); |
port( |
clk : in STD_LOGIC; |
rst : in STD_LOGIC; |
angle : in signed(2*STAGE-1 downto 0); |
I : in signed(WIDTH+1 downto 0); |
Q : in signed(WIDTH+1 downto 0); |
Iout : out signed(WIDTH+3 downto 0); |
Qout : out signed(WIDTH+3 downto 0) |
); |
end mulfactor; |
|
|
architecture mulfactor of mulfactor is |
signal phase : signed( 2*STAGE-3 downto 0 ); |
signal Xi,Yi : signed( WIDTH+1 downto 0 ); |
component sc_corproc |
generic( |
WIDTH : Natural; |
STAGE : Natural |
); |
port( |
clk : in std_logic; |
ena : in std_logic; |
Xin : in signed(WIDTH+1 downto 0); |
Yin : in signed(WIDTH+1 downto 0); |
Ain : in signed(2*STAGE-3 downto 0 ); |
|
sin : out signed(WIDTH+3 downto 0); |
cos : out signed(WIDTH+3 downto 0)); |
end component; |
|
begin |
|
u1: sc_corproc |
generic map( |
WIDTH=>WIDTH, |
STAGE=>STAGE |
) |
port map ( |
clk=>clk, |
ena=>'1', |
Xin=>Xi, |
Yin=>Yi, |
Ain=>phase, |
|
sin=>Qout, |
cos=>Iout |
); |
|
process( clk, rst ) |
variable temp : std_logic_vector( 1 downto 0 ); |
begin |
if rst='1' then |
phase<=( others=>'0' ); |
Xi<=( others=>'0' ); |
Yi<=( others=>'0' ); |
elsif clk'event and clk='1' then |
phase<=angle( 2*STAGE-3 downto 0 ); |
temp:=std_logic_vector(angle( 2*STAGE-1 downto 2*STAGE-2 )); |
case temp is |
when "00" => |
Xi<=I; |
Yi<=Q; |
when "01" => |
Xi<=0-Q; |
Yi<=I; |
when "10" => |
Xi<=0-I; |
Yi<=0-Q; |
when "11" => |
Xi<=Q; |
Yi<=0-I; |
when others=> |
null; |
end case; |
end if; |
end process; |
|
end mulfactor; |
/trunk/src/sc_corproc.vhd
0,0 → 1,100
-- |
-- This file is come from www.opencores.org |
-- |
-- It has been modified by ZHAO Ming for 20 bit complex rotation |
-- |
|
--------------------------------------------------------------------------------------------------- |
-- |
-- Title : sc_corproc |
-- Design : cfft |
-- Author : ZHAO Ming |
-- email : sradio@opencores.org |
-- |
--------------------------------------------------------------------------------------------------- |
-- |
-- File : sc_corproc.vhd |
-- Generated : Tue Jul 16 10:39:17 2002 |
-- |
--------------------------------------------------------------------------------------------------- |
-- |
-- Description : complex rotation |
-- |
--------------------------------------------------------------------------------------------------- |
-- |
-- Revisions : 0 |
-- Revision Number : 1 |
-- Version : 1.1.0 |
-- Date : Oct 17 2002 |
-- Modifier : ZHAO Ming |
-- Desccription : Data width configurable |
-- |
--------------------------------------------------------------------------------------------------- |
-- |
-- Revisions : 0 |
-- Revision Number : 2 |
-- Version : 1.2.0 |
-- Date : Oct 18 2002 |
-- Modifier : ZHAO Ming |
-- Desccription : Data width configurable |
-- |
--------------------------------------------------------------------------------------------------- |
|
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
use ieee.std_logic_signed.all; |
|
entity sc_corproc is |
generic ( |
WIDTH : Natural; |
STAGE : Natural |
); |
port( |
clk : in std_logic; |
ena : in std_logic; |
Xin : in signed(WIDTH+1 downto 0); |
Yin : in signed(WIDTH+1 downto 0); |
Ain : in signed(2*STAGE-3 downto 0 ); |
|
sin : out signed(WIDTH+3 downto 0); |
cos : out signed(WIDTH+3 downto 0) |
); |
end entity sc_corproc; |
|
architecture dataflow of sc_corproc is |
constant PipeLength : natural := 2*STAGE+2; |
|
component p2r_cordic is |
generic( |
PIPELINE : integer := 15; |
WIDTH : integer := 16); |
port( |
clk : in std_logic; |
ena : in std_logic; |
|
Xi : in signed(WIDTH -1 downto 0); |
Yi : in signed(WIDTH -1 downto 0) := (others => '0'); |
Zi : in signed(19 downto 0); |
|
Xo : out signed(WIDTH -1 downto 0); |
Yo : out signed(WIDTH -1 downto 0) |
); |
end component p2r_cordic; |
signal phase:signed( 19 downto 0 ); |
signal Xi,Yi:signed( WIDTH+7 downto 0 ); |
signal Xo,Yo:signed( WIDTH+7 downto 0 ); |
signal zeros:signed( 19-STAGE*2 downto 0 ); |
begin |
Xi<= Xin(WIDTH+1)&Xin&"00000"; |
Yi<= Yin(WIDTH+1)&Yin&"00000"; |
zeros<=(others=>'0'); |
phase<="00"&Ain&zeros; |
cos<=Xo(WIDTH+7)&Xo( WIDTH+7 downto 5 ); |
sin<=Yo(WIDTH+7)&Yo( WIDTH+7 downto 5 ); |
|
u1: p2r_cordic |
generic map(PIPELINE => PipeLength, WIDTH => WIDTH+8) |
port map(clk => clk, ena => ena, Xi => Xi, Yi=>Yi,Zi => phase, Xo => Xo, Yo => Yo); |
end architecture dataflow; |
/trunk/src/blockdram.vhd
0,0 → 1,68
--------------------------------------------------------------------------------------------------- |
-- |
-- Title : blockram |
-- Design : cfft |
-- Author : MENG Lin |
-- email : |
-- |
--------------------------------------------------------------------------------------------------- |
-- |
-- File : blockram.vhd |
-- Generated : unknown |
-- |
--------------------------------------------------------------------------------------------------- |
-- |
-- Description : Dual port ram |
-- |
--------------------------------------------------------------------------------------------------- |
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
use ieee.std_logic_unsigned.all; |
library synplify; |
use synplify.attributes.all; |
|
entity blockdram is |
generic( |
depth: integer; |
Dwidth: integer; |
Awidth: integer |
); |
port( |
addra: IN std_logic_VECTOR(Awidth-1 downto 0); |
clka: IN std_logic; |
addrb: IN std_logic_VECTOR(Awidth-1 downto 0); |
clkb: IN std_logic; |
dia: IN std_logic_VECTOR(Dwidth-1 downto 0); |
wea: IN std_logic; |
dob: OUT std_logic_VECTOR(Dwidth-1 downto 0)); |
end blockdram; |
|
architecture arch_blockdram of blockdram is |
|
type ram_memtype is array (depth-1 downto 0) of std_logic_vector |
(Dwidth-1 downto 0); |
signal mem : ram_memtype := (others => (others => '0')); |
attribute syn_ramstyle of mem : signal is "block_ram"; |
|
signal addrb_reg: std_logic_vector(Awidth-1 downto 0); |
|
begin |
wr: process( clka ) |
begin |
if rising_edge(clka) then |
if wea = '1' then |
mem(conv_integer(addra)) <= dia; |
end if; |
end if; |
end process wr; |
|
rd: process( clkb ) |
begin |
if rising_edge(clkb) then |
addrb_reg <= addrb; |
end if; |
end process rd; |
dob <= mem(conv_integer(addrb_reg)); |
end arch_blockdram; |
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