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/fft_fir_filter/trunk/bench/fft_filter2_tb.vhd
0,0 → 1,277
---------------------------------------------------------------------
---- ----
---- FFT-based FIR Filter IP core ----
---- ----
---- Authors: Anatoliy Sergienko, Volodya Lepeha ----
---- Company: Unicore Systems http://unicore.co.ua ----
---- ----
---- Downloaded from: http://www.opencores.org ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2006-2010 Unicore Systems LTD ----
---- www.unicore.co.ua ----
---- o.uzenkov@unicore.co.ua ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED "AS IS" ----
---- AND ANY EXPRESSED OR IMPLIED WARRANTIES, ----
---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ----
---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ----
---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ----
---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ----
---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ----
---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ----
---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ----
---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ----
---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ----
---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ----
---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ----
---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
--
-- File : fft_filter2_TB.vhd
-- Generated : 08.08.05, 13:25
---------------------------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.math_real.all;
use IEEE.std_logic_arith.all;
 
 
entity fft_filter2_tb is
generic(
iwidth : INTEGER := 16;
owidth : INTEGER := 18;
wwidth : INTEGER := 16;
n : INTEGER := 10;
v2 : INTEGER := 1;
reall : INTEGER := 1;
filtre:std_logic_vector(1 downto 0):="01");
end fft_filter2_tb;
 
architecture TB_ARCHITECTURE of fft_filter2_tb is
constant tc:time:=12.5 ns; -- clock period =1/Fclk
constant fs:real:=2500.0 ; --sampling frequency Fs in kHz
constant nd:natural:=32; -- Fclk=nd*Fs, nd>29
constant df:real:=5.0;--19.5*4.0; -- step of frequency in kHz to show the freq. characteristic
constant f00:real:=00.0; -- init frequency in kHz
constant magn:real:=30000.0; -- input signal magnitude
constant Fl1:real:=100.0; -- low pass band
constant Fh1:real:=200.0; -- high pass band
constant Fl2:real:=100.0; -- low pass band
constant Fh2:real:=200.0; -- high pass band
component fft_filter2
generic(
iwidth : INTEGER := 8;
owidth : INTEGER := 8;
wwidth : INTEGER := 8;
n : INTEGER := 7;
v2 : INTEGER := 1;
reall : INTEGER := 0 );
port(
CLK : in std_logic;
RST : in std_logic;
CE : in std_logic;
START : in std_logic;
DATAE : in std_logic;
FILTER : in std_logic_vector(1 downto 0);
L1 : in std_logic_vector((n-1) downto 0);
H1 : in std_logic_vector((n-1) downto 0);
L2 : in std_logic_vector((n-1) downto 0);
H2 : in std_logic_vector((n-1) downto 0);
DATAIRE : in std_logic_vector((iwidth-1) downto 0);
DATAIIM : in std_logic_vector((iwidth-1) downto 0);
READY : out std_logic;
DATAORE : out std_logic_vector((owidth-1) downto 0);
DATAOIM : out std_logic_vector((owidth-1) downto 0);
SPRDY: out STD_LOGIC;
WESP: out STD_LOGIC;
SPRE: out STD_LOGIC_VECTOR (owidth-1 downto 0);
SPIM: out STD_LOGIC_VECTOR (owidth-1 downto 0);
FREQ:out STD_LOGIC_VECTOR (n-1 downto 0);
SPEXP:out STD_LOGIC_VECTOR (3 downto 0) ) ;
end component;
signal CLK : std_logic:='1';
signal RST : std_logic:='1';
signal CE : std_logic;
signal START : std_logic;
signal DATAE,rdyd : std_logic;
signal FILTER : std_logic_vector(1 downto 0);
signal L1 : std_logic_vector((n-1) downto 0);
signal H1 : std_logic_vector((n-1) downto 0);
signal L2 : std_logic_vector((n-1) downto 0);
signal H2 : std_logic_vector((n-1) downto 0);
signal DATAIRE : std_logic_vector((iwidth-1) downto 0);
signal DATAIIM : std_logic_vector((iwidth-1) downto 0);
-- signal READY : std_logic;
signal DATAORE : std_logic_vector((owidth-1) downto 0);
signal DATAOIM : std_logic_vector((owidth-1) downto 0);
signal clk_ce : std_logic := '1';
signal DATA_IN,DATA_OUT,DATA_IN1,DATA_OUT1 : STD_LOGIC_VECTOR(15 downto 0) := x"0000";
signal rs,rc,f0,res,reslog,f1,frequ:real:=0.0;
signal p,p1,p2,p3,p4,ENA,RDY : std_logic:='0';
signal cnt,ct2:natural;
signal ssc,scc,coun,freque:integer;
constant a1:std_logic_vector((iwidth-1) downto 0):=
CONV_STD_LOGIC_VECTOR(integer(0.99 * magn),iwidth);
constant a0:std_logic_vector((iwidth-1) downto 0):=(others=>'0');
constant nn:real:=real(2**n);
begin
FILTER<=filtre; --01 prosto filter, 10 filter+differenc-r
CE<='1'; -- bez zamedlenija
l1<=conv_std_logic_vector(integer(1.0*Fl1*nn/fs),n);
h1<=conv_std_logic_vector(integer(1.0*Fh1*nn/fs),n);
l2<=conv_std_logic_vector(integer(1.0*Fl2*nn/fs),n);
h2<=conv_std_logic_vector(integer(1.0*Fh2*nn/fs),n);
rst <= '1','0' after 103 ns;
clk <= not clk after 0.5*tc; --Generator sinchroserii
start<='0', '1' after 104 ns,'0' after 104 ns + 2*tc;
QUANT:process(rst,CLK)
begin
if rst='1' then cnt<=0;
elsif rising_edge(CLK) then
if cnt= nd-1 then
cnt<=0; ENA<='1' ;
else
cnt<=cnt+1;ENA<='0' ;
end if;
end if;
end process;
-- Unit Under Test port map
UUT : fft_filter2
generic map (
iwidth => iwidth,
owidth => owidth,
wwidth => wwidth,
n => n,
v2 => v2,
reall => reall
)
port map (CLK,RST,CE,
START => START,
DATAE => ENA,
FILTER => FILTER,
L1 => L1,
H1 => H1,
L2 => L2,
H2 => H2,
DATAIRE => DATA_In,
DATAIIM => DATA_in1,
READY => RDY,
DATAORE =>DATAORE,
DATAOIM =>DATAOIM
);
DATA_Out<=DATAORE(owidth-1 downto owidth-iwidth);
DATA_Out1<=DATAOIM(owidth-1 downto owidth-iwidth);
EPOCH:process begin
--wait for 1500*tc*nd;
loop
p <= '0'; wait for (1024*nd-1)*tc;-- 0.25*1000 us; p <= '1'; wait for 4*12.5 ns;
p<='1'; wait for tc;
end loop;
end process;
SINE_GEN:process(clk,rst)
variable i : real;
variable j : integer;
begin
if rst = '1' then
ct2<=0;
rs <= 0.0;
i := 0.0; j := 0;
f0 <= f00;
rdyd<='0';
elsif clk = '1' and clk'event then
rdyd<=rdy;
if RDY='1' and rdyd='0' then
if ct2=1 then
ct2<=0;
f0 <= f0 + df; f1 <= f0*2.5;
else
ct2<= ct2+1; -- counter of even/odd FFT
end if;
end if;
-- if p = '1' then f0 <= f0 + df; f1 <= f0*2.5; end if;
rc <= cos(f0 * 2.0 * math_pi * i/Fs); --0.0;----
rs <= sin(f0 * 2.0 * math_pi * i/Fs);
if ENA='1' then i:=i+1.0; end if;
end if;
end process;
data_in1 <=(CONV_STD_LOGIC_VECTOR(integer(rs * magn),16));--others=>'0');-- ----
data_in <= CONV_STD_LOGIC_VECTOR(integer(rc * magn),16); -- when p = '1' else x"0000";
-- data_in <= CONV_STD_LOGIC_VECTOR(integer(0.9 * magn),16); -- when p = '1' else x"0000";
-- data_in<=a0, a1 after 0.01 us, a0 after 14 us, a1 after 30 us,a0 after 35 us,
-- a1 after 70 us, a0 after 74 us, a1 after 91 us,a0 after 105 us,
-- a1 after 120 us, a0 after 123 us, a1 after 141 us,a0 after 155 us;
-- p1 <= transport p after 10 us;
process(clk,rst)
variable couni : integer := 0;
variable ss,sc,sm0,r,rsum : real;
begin
if rst = '1' then
reslog <= -100.0;
res<=0.0;
elsif clk = '1' and clk'event then
if RDY='1' and rdyd='0'and ct2=1 then
coun <= 0;
rsum:=0.0;
end if;
if coun /= 32 and ENA='1' then
coun <= coun + 1;
end if;
if ENA='1' then
if coun >= 0 and coun < 30 then
ss := real(conv_integer(signed(data_out)))/magn;
sc := real(conv_integer(signed(data_out1)))/magn;
sm0 := ss*ss + sc*sc + 0.00000000000001; --; --
r := 20.0 * log10(sqrt(sm0));
rsum := rsum + sm0;
end if;
if coun = 31 then
res<= sqrt(rsum/30.0) ;
reslog <= 20.0 * log10(sqrt(rsum/30.0));
freque<=integer(f0-df);
end if;
end if;
end if;
end process;
ssc <= (conv_integer(signed(data_out)));
scc <= (conv_integer(signed(data_out1)));
end TB_ARCHITECTURE;
 
/fft_fir_filter/trunk/rtl/fftdpath.vhd
0,0 → 1,312
---------------------------------------------------------------------
---- ----
---- FFT Filter IP core ----
---- ----
---- Authors: Anatoliy Sergienko, Volodya Lepeha ----
---- Company: Unicore Systems http://unicore.co.ua ----
---- ----
---- Downloaded from: http://www.opencores.org ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2006-2010 Unicore Systems LTD ----
---- www.unicore.co.ua ----
---- o.uzenkov@unicore.co.ua ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED "AS IS" ----
---- AND ANY EXPRESSED OR IMPLIED WARRANTIES, ----
---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ----
---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ----
---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ----
---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ----
---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ----
---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ----
---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ----
---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ----
---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ----
---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ----
---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ----
---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- AUTHORS Volodymir Lepekha,
-- Anatoli Sergyienko.
--HISTORY :07.2005 mode added:
-- 00 - multiply by window
-- 01 - butterfly
-- 10 - restore for real FFT
-- only for Virtex2 and later
--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
 
entity FFTDPATH is
generic ( ifft: integer:=0;
width: integer :=8 ; -- word width =8...24
Wwdth: integer:=7; -- coefficient width =7...15
V2:integer
);
port (
CLK: in STD_LOGIC;
RST: in STD_LOGIC;
CE: in STD_LOGIC;
ODDC: in STD_LOGIC; --
DIV2: in STD_LOGIC; --Scaling factor
ZWR: in STD_LOGIC;
ZWI: in STD_LOGIC;
SIGNRE: in STD_LOGIC;
MODE: in STD_LOGIC_VECTOR (1 downto 0);
REDI: in STD_LOGIC_VECTOR (width downto 0);
IMDI: in STD_LOGIC_VECTOR (width downto 0);
WF: in STD_LOGIC_VECTOR (wwdth-1 downto 0);
REDO: out STD_LOGIC_VECTOR (width downto 0);
IMDO: out STD_LOGIC_VECTOR (width downto 0)
);
end FFTDPATH;
 
 
architecture FFTDPATH_s of FFTDPATH is
constant zeros: STD_LOGIC_VECTOR (width-wwdth downto 0):=
CONV_STD_LOGIC_VECTOR(0,width-wwdth+1);
signal ar,ai,ar3,ai3: STD_LOGIC_VECTOR (width-1 downto 0);
signal br1,bi1,br,bi,br2,bi2: STD_LOGIC_VECTOR (width-1 downto 0);
signal renorm,imnorm,br4,bi4: STD_LOGIC_VECTOR (width-1 downto 0);
signal ard,aid: STD_LOGIC_VECTOR (3 downto 0);
signal wr,wr1: STD_LOGIC_VECTOR (wwdth-1 downto 0);
signal prodrb,prodib: STD_LOGIC_VECTOR (width+wwdth downto 0);
signal prodr1,prodi1: STD_LOGIC_VECTOR (width+wwdth-2 downto wwdth-2);
signal prodr2,prodi2: STD_LOGIC_VECTOR (width+wwdth-1 downto wwdth-2);
signal prodr,prodi,prodrd,prodid: STD_LOGIC_VECTOR (width downto 0);
signal cr,ci: STD_LOGIC_VECTOR (width downto 0);
signal dr,di: STD_LOGIC_VECTOR (width+2 downto 0);
signal zwri,zwii,zwr1,zwi1,zwr2,zwi2,signrei,signre1,signre2: STD_LOGIC;
begin
SHIFT:process(REDI,IMDI,DIV2)
begin
if DIV2='1' then
renorm <= REDI (width downto 1);
imnorm <= IMDI (width downto 1);
else
renorm <= REDI(width-1 downto 0);
imnorm <= IMDI(width-1 downto 0);
end if;
end process;
RDELAY:process(CLK,RST)
begin
if RST = '1' then
wr <= (others =>'0');
wr1 <= (others =>'0');
ar <= (others =>'0');
br <= (others =>'0');
br1<= (others =>'0');
br2 <= (others =>'0');
ar3 <= (others =>'0');
br4 <= (others =>'0');
ai <= (others =>'0');
bi <= (others =>'0');
bi1<= (others =>'0');
bi2 <= (others =>'0');
ai3 <= (others =>'0');
bi4 <= (others =>'0');
elsif CLK = '1' and CLK'event then
if CE = '1' then
wr<=WF;
wr1<=wr;
br2<=br1;
bi2<=bi1;
if ODDC='0' then
ar<= renorm;
ar3<=ar;
br4<=br2;
ai<= imnorm;
ai3<=ai;
bi4<=bi2;
else
br<= renorm;
br1<=br;
bi<= imnorm;
bi1<=bi;
end if;
end if;
end if;
end process;
TTDELAY:process(CLK,RST)
begin
if RST='1' then
zwri<='0';
zwii<='0';
zwr1<='0';
zwi1<='0';
zwr2<='0';
zwi2<='0';
signrei<='0';
signre1<='0';
signre2<='0';
elsif CLK='1' and CLK'event then
if CE='1' then
zwri<=ZWR;
zwii<=ZWI;
zwr1<=zwri;
zwi1<=zwii;
zwr2<=zwr1;
zwi2<=zwi1;
signrei<=SIGNRE;
signre1<=signrei;
signre2<=signre1;
end if;
end if;
end process;
BLCK:if v2=1 generate
MPU_U: process(CLK,RST)
variable prodr,prodi:STD_LOGIC_VECTOR(width+wwdth-2 downto 0);
variable minusre,minusim:STD_LOGIC;
begin
if RST = '1' then
prodrb <= (others =>'0');
prodr2 <= (others =>'0');
prodib <= (others =>'0');
prodi2 <= (others =>'0');
elsif CLK = '1' and CLK'event then
if CE = '1' then
prodrb <= signed('0'& wr) * signed(ar);
prodib <= signed('0'& wr) * signed(ai);
prodr2<=prodrb(width+wwdth-1 downto wwdth-2);
prodi2<=prodib(width+wwdth-1 downto wwdth-2);
end if;
end if;
end process;
end generate;
prodr<=prodr2( width+wwdth-1 downto wwdth-1);
prodi<=prodi2( width+wwdth-1 downto wwdth-1);
RPRODD: process(CLK,RST)
begin
if RST='1' then
prodrd<=(others=>'0');
prodid<=(others=>'0');
elsif CLK='1' and CLK'event then
if CE ='1' then
if signre1='1' then
prodrd<= - signed(prodr);
prodid<= - signed(prodi);
else
prodrd<=prodr;
prodid<=prodi;
end if;
end if;
end if;
end process;
FFTINST:if IFFT=0 generate
ACPROD:process(RST,CLK)
begin
if RST='1' then
cr<=(others=>'0');
ci<=(others=>'0');
elsif CLK='1' and CLK'event then
if CE ='1' and ODDC='0' then
if zwi2='1' then
cr <= ar3&'0';
ci <= ai3&'0';
elsif zwr2='1' then
cr <= ai3&'0';
ci <= - signed(ar3&'0');
else
cr<= signed(prodrd)+signed(prodi);
ci<= signed(prodid)-signed(prodr);
end if;
end if;
end if;
end process;
end generate;
IFFTINST:if IFFT=1 generate
ACPROD:process(RST,CLK)
begin
if RST='1' then
cr<=(others=>'0');
ci<=(others=>'0');
elsif CLK='1' and CLK'event then
if CE ='1' and ODDC='0' then
if zwi2='1' then
cr <= ar3&'0';
ci <= ai3&'0';
elsif zwr2='1' then
cr <= 0- signed(ai3&'0');
ci <= ar3&'0';
else-- if signre2='1' then
-- cr<= 0- signed(prodrd)-signed(prodi);
-- ci<= 0- signed(prodid)+signed(prodr);
-- else
cr<= signed(prodrd)-signed(prodi);
ci<= signed(prodid)+signed(prodr);
-- end if;
end if;
end if;
end if;
end process;
end generate;
ABUTTERF:process(CLK,RST)
begin
if RST='1' then
dr<=(others=>'0');
di<=(others=>'0');
elsif CLK='1' and CLK'event then
if CE ='1' then
case MODE is
when "00" => dr<=prodr&"01";
di<=prodI&"01" ;
when "01" => --butterfly
if ODDC='1' then --addition with rounding
dr<=signed(br4&"01")+signed( cr(width)&cr&'1');
di<=signed(bi4&"01")+signed( ci(width)&ci&'1');
else
dr<=signed(br4&"01")-signed( cr(width)&cr&'1');
di<=signed(bi4&"01")-signed( ci(width)&ci&'1');
end if;
when others=> -- Wosstanowlenie
if ODDC='1' then --addition with rounding
dr<=signed(br4&"01")+signed( cr(width)&cr&'1');
di<=signed(bi4&"01")-signed( ci(width)&ci&'1');
else
dr<=signed(bi4&"01")+signed( ci(width)&ci&'1');
di<=signed( cr(width)&cr&'1')- signed(br4&"01");
end if;
end case ;
end if;
end if;
end process;
REDO<= dr(width+2 downto 2) ;
IMDO<= di(width+2 downto 2);
end FFTDPATH_s;
/fft_fir_filter/trunk/rtl/fft_filtr2.vhd
0,0 → 1,304
---------------------------------------------------------------------
---- ----
---- FFT Filter IP core ----
---- ----
---- Authors: Anatoliy Sergienko, Volodya Lepeha ----
---- Company: Unicore Systems http://unicore.co.ua ----
---- ----
---- Downloaded from: http://www.opencores.org ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2006-2010 Unicore Systems LTD ----
---- www.unicore.co.ua ----
---- o.uzenkov@unicore.co.ua ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED "AS IS" ----
---- AND ANY EXPRESSED OR IMPLIED WARRANTIES, ----
---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ----
---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ----
---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ----
---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ----
---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ----
---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ----
---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ----
---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ----
---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ----
---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ----
---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ----
---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-- DESCRIPTION:
--
-- FUNCTION FFT filter for FFT length of
-- N= 64, 128, 256, 512, 1024, 2048 points,
-- N= 2**n,
-- ifft=0 forward FFT, =1 inverse FFT
-- rams=1 - single data RAM, =2 dual data RAM
-- input data width: iwidth = 8,...,16 bit signed
-- output data width: owidth = 8,...,16 bit signed
-- coefficient width : wwidth = 8,...,16 bit
-- Synthesable for Virtex2, Spartan3 FPGAs.
--
-- FILES: FFT_Filtr2.VHD -- this file
-- ALFFT_Core_slip.vhd - Slipping FFT with windowing
-- FFTDPATH.vhd - data path of the FFT butterfly
-- CONTROL.vhd - control unit of FFT processor
-- ROM_COS.vhd - coefficient ROM
-- RAM2X_2.vhd - dual data RAM block
-- ALFFT_Core_sli.vhd - file of IFFT processor
-- FFTDPATHi.vhd - data path of the IFFT butterfly
-- CONTROL_i.vhd - control unit of IFFT processor
-- ROM_COSi.vhd - coefficient ROM
-- RAM1X_2.vhd - data RAM block
-- DENORM.vhd -- denormalizer unit
-- When redesign data RAM blocks
-- the Core will fit another FPGA families
--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~--
 
library IEEE;
use IEEE.std_logic_1164.all;
Use IEEE.std_logic_arith.all;
 
entity FFT_FILTER2 is
generic (
iwidth: INTEGER:=8 ; -- input data width =8...16
owidth: INTEGER:=8 ; -- output data width =8...16
wwidth: INTEGER:=8; -- coefficient width =8...16
n:INTEGER:=7 ; -- 6,7,8,9,10,11 - transform length factor
v2:INTEGER:=1 ; -- 1 - Virtex2
reall:INTEGER:= 1 --wch. mass: 0 -complex 1 - 2 realnych
);
port (
CLK: in STD_LOGIC;
RST: in STD_LOGIC;
 
 
 
FILTER: in STD_LOGIC_VECTOR (1 downto 0); --0 -ne filtruet 1 - filtruet 2-+diff 3 +2diff
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
);
end FFT_FILTER2;
 
architecture ALFFT_CoreS of FFT_Filter2 is
component ALFFT_Core is
generic ( ifft: INTEGER:=0; -- 0- forward FFT
rams:INTEGER:=2; -- 1,2
iwidth: INTEGER:=8 ; -- input data width =8...16
owidth: INTEGER:=8 ; -- output data width =8...16
wwidth: INTEGER:=8; -- coefficient width =8...16
n:INTEGER:=7 ;
v2:INTEGER:=1 ; -- 1 - Virtex2
slip:INTEGER:= 2; -- 2 -- skolzassij s perekrytiem 2
wnd:INTEGER:= 1 ; -- umnozaecca na okno 1 ,0 -bez umnozenija
reall:INTEGER:= 0 --wch. mass: 0 -complex 1 - 2 realnych
); --4,5, 6,7,8,9,10,11 - transform length factor
port (
CLK: in STD_LOGIC;
RST: in STD_LOGIC;
CE: in STD_LOGIC;
START: in STD_LOGIC;
DATAE: in STD_LOGIC;
DATAIRE: in STD_LOGIC_VECTOR (iwidth-1 downto 0);
DATAIIM: in STD_LOGIC_VECTOR (iwidth-1 downto 0);
FFTRDY: out STD_LOGIC;
READY: out STD_LOGIC;
WERES: out STD_LOGIC;
ADDRRES: out STD_LOGIC_VECTOR (n-1 downto 0);
DATAORE: out STD_LOGIC_VECTOR (owidth-1 downto 0);
DATAOIM: out STD_LOGIC_VECTOR (owidth-1 downto 0);
EXP: out STD_LOGIC_VECTOR (3 downto 0)
);
end component;
component ALFFT_Corei is
generic (width: INTEGER:=8 ; -- output data width =8...16
wwidth: INTEGER:=8; -- coefficient width =8...16
n:INTEGER:=7 ;
v2:INTEGER:=1 ; -- 1 - Virtex2
reall:INTEGER:= 0 --wch. mass: 0 -complex 1 - 2 realnych
); --4,5, 6,7,8,9,10,11 - transform length factor
port (
CLK: in STD_LOGIC;
RST: in STD_LOGIC;
CE: in STD_LOGIC;
START: in STD_LOGIC;
FILTER: in STD_LOGIC_VECTOR (1 downto 0); --0 -ne filtruet 1 - filtruet 2-+diff 3 +2diff
L1:in STD_LOGIC_VECTOR (n-1 downto 0); -- tsastoty filtrow
H1:in STD_LOGIC_VECTOR (n-1 downto 0); -- tsastoty filtrow
L2:in STD_LOGIC_VECTOR (n-1 downto 0);
H2:in STD_LOGIC_VECTOR (n-1 downto 0);
DATAE: in STD_LOGIC;
DATAIRE: in STD_LOGIC_VECTOR (width-1 downto 0);
DATAIIM: in STD_LOGIC_VECTOR (width-1 downto 0);
FFTRDY: out STD_LOGIC;
READY: out STD_LOGIC;
WERES: out STD_LOGIC;
ADDRRES: inout STD_LOGIC_VECTOR (n-1 downto 0);
DATAORE: out STD_LOGIC_VECTOR (width-1 downto 0);
DATAOIM: out STD_LOGIC_VECTOR (width-1 downto 0);
EXP: out STD_LOGIC_VECTOR (3 downto 0)
);
end component ;
component DENORM is
generic (width: integer :=8 ; -- word width =8...24
n:INTEGER:=7 ;
reall:INTEGER:= 0 ;
v2:INTEGER:=1 );-- 1 - Virtex2
port (
CLK: in STD_LOGIC;
RST: in STD_LOGIC;
CE: in STD_LOGIC;
DATAE: in STD_LOGIC;
START: in STD_LOGIC; --
INIT: in STD_LOGIC; --
WERES: in STD_LOGIC;
SPRDY: in STD_LOGIC;
ADDRRES: in STD_LOGIC_VECTOR (n-1 downto 0);
EXPI: in STD_LOGIC_VECTOR (3 downto 0);
EXPF: in STD_LOGIC_VECTOR (3 downto 0);
REDI: in STD_LOGIC_VECTOR (width-1 downto 0);
IMDI: in STD_LOGIC_VECTOR (width-1 downto 0);
RDY: out STD_LOGIC;
REDO: out STD_LOGIC_VECTOR (width-1 downto 0);
IMDO: out STD_LOGIC_VECTOR (width-1 downto 0)
);
end component;
signal REDI: STD_LOGIC_VECTOR (owidth-1 downto 0);
signal IMDI: STD_LOGIC_VECTOR (owidth-1 downto 0);
signal REDO: STD_LOGIC_VECTOR (owidth-1 downto 0);
signal IMDO: STD_LOGIC_VECTOR (owidth-1 downto 0);
signal INITOVERF: STD_LOGIC;
signal WEspi: STD_LOGIC;
signal sprdyi: STD_LOGIC;
signal WEres: STD_LOGIC;
signal fftrdy,ifftrdy: STD_LOGIC; -- 0 -fromDIRE,DIIM, 1 - DMRE,DMIM
signal EVEN: STD_LOGIC; --0- 0th bank 1- 1st bank -for DIRE,DIIM
signal ADDRW: STD_LOGIC_VECTOR (n - 1 downto 0);
signal MODE: STD_LOGIC_VECTOR (1 downto 0);
signal SPREi,SPIMi,DRE,DIM:STD_LOGIC_VECTOR (owidth-1 downto 0);
signal EXPF,EXPI:STD_LOGIC_VECTOR (3 downto 0);
signal addrres,address: STD_LOGIC_VECTOR (n-1 downto 0);
signal DIRE,DIIM: STD_LOGIC_VECTOR (iwidth-1 downto 0);
constant vcc:STD_LOGIC:='1';
signal sno1,sno2,sno3:integer;
begin
DIRE<=DATAIRE;-- & zeros;
DIIM<=DATAIIM;-- & zeros;
FFT_F: ALFFT_Core
generic map (ifft=>0, -- 0- forward FFT
rams=>2, -- 1,2
iwidth=>iwidth, -- input data width =8...16
owidth=>owidth, -- output data width =8...16
wwidth=>wwidth, -- coefficient width =8...16
n=>n,
v2=>v2, -- 1 - Virtex2
slip=> 2, -- 2 -- skolzassij s perekrytiem 2
wnd=> 1, -- umnozaecca na okno 1 ,0 -bez umnozenija
reall=>reall --wch. mass: 0 -complex 1 - 2 realnych
) --4,5, 6,7,8,9,10,11 - transform length factor
port map (CLK,RST,CE,
START=>START,
DATAE=>DATAE,
DATAIRE=>DIRE,
DATAIIM=>DIIM,
FFTRDY=>fftrdy,
READY=>sprdyi,
WERES=>wespi,
ADDRRES=>address,
DATAORE=>SPREi,
DATAOIM=>SPIMi,
EXP=>expf
);
WESP<=wespi; -- spectr data output
SPRDY<=sprdyi;
SPRE<=SPREi;
SPIM<=SPIMi;
SPEXP<=expf;
FREQ<=address;
FFT_I: ALFFT_Corei
generic map (width=>owidth, -- output data width =8...16
wwidth=>wwidth, -- coefficient width =8...16
n=>n,
v2=>v2, -- 1 - Virtex2
reall=>reall --wch. mass: 0 -complex 1 - 2 realnych
) --4,5, 6,7,8,9,10,11 - transform length factor
port map(CLK,RST,CE,
START=>sprdyi,
FILTER=>FILTER, --0 -ne filtruet 1 - filtruet 2-+diff 3 +2diff
L1=>L1, -- tsastoty filtrow
H1=>H1, -- tsastoty filtrow
L2=>L2,
H2=>H2,
DATAE=>wespi,
DATAIRE=>SPREi,
DATAIIM=>SPIMi,
FFTRDY=>open,
READY=>ifftrdy,
WERES=>weres,
ADDRRES=>addrres,
DATAORE=>DRE,
DATAOIM=>DIM,
EXP=>EXPi
);
U_OUT: DENORM
generic map(width=>owidth, -- word width =8...24
n=>n,
reall=>reall,
v2=>v2)
port map(CLK,RST,CE,
DATAE=>DATAE,
START=>start,
INIT=> ifftrdy,
WERES=>weres,
ADDRRES=>addrres,
SPRDY=>SPRDYi,
EXPI=>expi,
EXPF=>expf,
REDI=>DRE,
IMDI=>DIM,
RDY=>READY,
REDO=>REDO,
IMDO=>IMDO
);
DATAORE<=REDO ;
DATAOIM<=IMDO ;
end ALFFT_CoreS;
/fft_fir_filter/trunk/rtl/rom_cos.vhd
0,0 → 1,426
---------------------------------------------------------------------
---- ----
---- FFT Filter IP core ----
---- ----
---- Authors: Anatoliy Sergienko, Volodya Lepeha ----
---- Company: Unicore Systems http://unicore.co.ua ----
---- ----
---- Downloaded from: http://www.opencores.org ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2006-2010 Unicore Systems LTD ----
---- www.unicore.co.ua ----
---- o.uzenkov@unicore.co.ua ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED "AS IS" ----
---- AND ANY EXPRESSED OR IMPLIED WARRANTIES, ----
---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ----
---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ----
---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ----
---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ----
---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ----
---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ----
---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ----
---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ----
---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ----
---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ----
---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ----
---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
 
entity ROM_COS is
generic(n: integer; --- FFT factor= 6,7,8,9,10,11
wwdth: integer:=15;-- output word width =8...15 , cos>0
wnd:integer);
port ( SELW:in STD_LOGIC;
ADDRROM :in std_logic_vector(n-2 downto 0);
COS : out std_logic_vector(wwdth-1 downto 0)
);
end ROM_COS ;
-----------
architecture DISTR of ROM_COS is
 
type ARR512 is array (0 to 511) of STD_LOGIC_VECTOR(15 downto 0);
constant hann:arr512:=(
X"0001",X"0002",X"0003",X"0005",X"0008",X"000C",X"0010",X"0014", X"0019",X"001F",X"0026",X"002D",X"0035",X"003D",X"0046",X"004F",
X"005A",X"0064",X"0070",X"007C",X"0088",X"0096",X"00A3",X"00B2",X"00C1",X"00D1",X"00E1",X"00F2",X"0103",X"0115",X"0128",X"013B",
X"014F",X"0164",X"0179",X"018F",X"01A5",X"01BC",X"01D3",X"01EB",X"0204",X"021E",X"0237",X"0252",X"026D",X"0289",X"02A5",X"02C2",
X"02DF",X"02FD",X"031C",X"033B",X"035B",X"037C",X"039D",X"03BE",X"03E0",X"0403",X"0426",X"044A",X"046F",X"0494",X"04B9",X"04E0",
X"0506",X"052E",X"0556",X"057E",X"05A7",X"05D1",X"05FB",X"0625",X"0651",X"067D",X"06A9",X"06D6",X"0703",X"0731",X"0760",X"078F",
X"07BF",X"07EF",X"0820",X"0851",X"0883",X"08B5",X"08E8",X"091B",X"094F",X"0984",X"09B9",X"09EE",X"0A24",X"0A5B",X"0A92",X"0ACA",
X"0B02",X"0B3A",X"0B73",X"0BAD",X"0BE7",X"0C22",X"0C5D",X"0C99",X"0CD5",X"0D11",X"0D4E",X"0D8C",X"0DCA",X"0E09",X"0E48",X"0E87",
X"0EC7",X"0F08",X"0F49",X"0F8A",X"0FCC",X"100E",X"1051",X"1094",X"10D8",X"111C",X"1161",X"11A6",X"11EC",X"1232",X"1278",X"12BF",
X"1306",X"134E",X"1396",X"13DF",X"1428",X"1471",X"14BB",X"1505",X"1550",X"159B",X"15E7",X"1633",X"167F",X"16CC",X"1719",X"1766",
X"17B4",X"1802",X"1851",X"18A0",X"18F0",X"193F",X"1990",X"19E0",X"1A31",X"1A82",X"1AD4",X"1B26",X"1B78",X"1BCB",X"1C1E",X"1C72",
X"1CC5",X"1D19",X"1D6E",X"1DC3",X"1E18",X"1E6D",X"1EC3",X"1F19",X"1F6F",X"1FC6",X"201D",X"2074",X"20CC",X"2124",X"217C",X"21D5",
X"222D",X"2286",X"22E0",X"233A",X"2393",X"23EE",X"2448",X"24A3",X"24FE",X"2559",X"25B5",X"2610",X"266C",X"26C9",X"2725",X"2782",
X"27DF",X"283C",X"289A",X"28F7",X"2955",X"29B3",X"2A12",X"2A70",X"2ACF",X"2B2E",X"2B8D",X"2BEC",X"2C4C",X"2CAC",X"2D0C",X"2D6C",
X"2DCC",X"2E2D",X"2E8D",X"2EEE",X"2F4F",X"2FB0",X"3011",X"3073",X"30D4",X"3136",X"3198",X"31FA",X"325C",X"32BE",X"3321",X"3383",
X"33E6",X"3449",X"34AC",X"350F",X"3572",X"35D5",X"3638",X"369C",X"36FF",X"3763",X"37C6",X"382A",X"388E",X"38F2",X"3956",X"39BA",
X"3A1E",X"3A82",X"3AE6",X"3B4A",X"3BAF",X"3C13",X"3C77",X"3CDC",X"3D40",X"3DA4",X"3E09",X"3E6D",X"3ED2",X"3F36",X"3F9B",X"3FFF",
X"4064",X"40C9",X"412D",X"4192",X"41F6",X"425B",X"42BF",X"4323",X"4388",X"43EC",X"4450",X"44B5",X"4519",X"457D",X"45E1",X"4645",
X"46A9",X"470D",X"4771",X"47D5",X"4839",X"489C",X"4900",X"4963",X"49C7",X"4A2A",X"4A8D",X"4AF0",X"4B53",X"4BB6",X"4C19",X"4C7C",
X"4CDE",X"4D41",X"4DA3",X"4E05",X"4E67",X"4EC9",X"4F2B",X"4F8C",X"4FEE",X"504F",X"50B0",X"5111",X"5172",X"51D2",X"5233",X"5293",
X"52F3",X"5353",X"53B3",X"5413",X"5472",X"54D1",X"5530",X"558F",X"55ED",X"564C",X"56AA",X"5708",X"5765",X"57C3",X"5820",X"587D",
X"58DA",X"5936",X"5993",X"59EF",X"5A4A",X"5AA6",X"5B01",X"5B5C",X"5BB7",X"5C11",X"5C6C",X"5CC5",X"5D1F",X"5D79",X"5DD2",X"5E2A",
X"5E83",X"5EDB",X"5F33",X"5F8B",X"5FE2",X"6039",X"6090",X"60E6",X"613C",X"6192",X"61E7",X"623C",X"6291",X"62E6",X"633A",X"638D",
X"63E1",X"6434",X"6487",X"64D9",X"652B",X"657D",X"65CE",X"661F",X"666F",X"66C0",X"670F",X"675F",X"67AE",X"67FD",X"684B",X"6899",
X"68E6",X"6933",X"6980",X"69CC",X"6A18",X"6A64",X"6AAF",X"6AFA",X"6B44",X"6B8E",X"6BD7",X"6C20",X"6C69",X"6CB1",X"6CF9",X"6D40",
X"6D87",X"6DCD",X"6E13",X"6E59",X"6E9E",X"6EE3",X"6F27",X"6F6B",X"6FAE",X"6FF1",X"7033",X"7075",X"70B6",X"70F7",X"7138",X"7178",
X"71B7",X"71F6",X"7235",X"7273",X"72B1",X"72EE",X"732A",X"7366",X"73A2",X"73DD",X"7418",X"7452",X"748C",X"74C5",X"74FD",X"7535",
X"756D",X"75A4",X"75DB",X"7611",X"7646",X"767B",X"76B0",X"76E4",X"7717",X"774A",X"777C",X"77AE",X"77DF",X"7810",X"7840",X"7870",
X"789F",X"78CE",X"78FC",X"7929",X"7956",X"7982",X"79AE",X"79DA",X"7A04",X"7A2E",X"7A58",X"7A81",X"7AA9",X"7AD1",X"7AF9",X"7B1F",
X"7B46",X"7B6B",X"7B90",X"7BB5",X"7BD9",X"7BFC",X"7C1F",X"7C41",X"7C62",X"7C83",X"7CA4",X"7CC4",X"7CE3",X"7D02",X"7D20",X"7D3D",
X"7D5A",X"7D76",X"7D92",X"7DAD",X"7DC8",X"7DE1",X"7DFB",X"7E14",X"7E2C",X"7E43",X"7E5A",X"7E70",X"7E86",X"7E9B",X"7EB0",X"7EC4",
X"7ED7",X"7EEA",X"7EFC",X"7F0D",X"7F1E",X"7F2E",X"7F3E",X"7F4D",X"7F5C",X"7F69",X"7F77",X"7F83",X"7F8F",X"7F9B",X"7FA5",X"7FB0",
X"7FB9",X"7FC2",X"7FCA",X"7FD2",X"7FD9",X"7FE0",X"7FE6",X"7FEB",X"7FEF",X"7FF3",X"7FF7",X"7FFA",X"7FFC",X"7FFD",X"7FFE",X"7FFF");
 
--signal hanns:STD_LOGIC_VECTOR(wwdth-1 downto 0);
signal addrful:STD_LOGIC_VECTOR(8 downto 0);
signal wind:std_logic_vector(wwdth-1 downto 0);
constant nulls: STD_LOGIC_VECTOR(10-n downto 0):=(others=>'0');
 
 
signal ADDR :std_logic_vector(n-3 downto 0);
type ROM16_16 is array(0 to 15 ) of std_logic_vector(15 downto 0);
type ROM128_8 is array(0 to 127 ) of std_logic_vector(7 downto 0);
constant ROM0000:ROM16_16:= (
X"7FFF",X"7F61",X"7D89",X"7A7C",X"7641",X"70E2",X"6A6D",X"62F1",
X"5A82",X"5133",X"471C",X"3C56", X"30FB",X"2528",X"18F9",X"0C8C");
constant ROM1000:ROM16_16:= (
X"7FD8",X"7E9C",X"7C29",X"7884",X"73B5",X"6DC9",X"66CF",X"5ED7",
X"55F5",X"4C3F",X"41CE",X"36BA",X"2B1F",X"1F1A",X"12C8",X"0648");
constant ROM0100:ROM16_16:= (
X"7FF5",X"7F09",X"7CE3",X"7989",X"7504",X"6F5E",X"68A6",X"60EB",
X"5842",X"4EBF",X"447A",X"398C",X"2E11",X"2223",X"15E2",X"096A");
constant ROM1100:ROM16_16:= (
X"7FA6",X"7E1D",X"7B5C",X"776B",X"7254",X"6C23",X"64E8",X"5CB3",
X"539B",X"49B4",X"3F17",X"33DF",X"2826",X"1C0B",X"0FAB",X"0324");
constant ROM0010:ROM16_16:= (
X"7FFD",X"7F37",X"7D39",X"7A05",X"75A5",X"7022",X"698B",X"61F0",
X"5964",X"4FFB",X"45CD",X"3AF2",X"2F87",X"23A6",X"176E",X"0AFB");
constant ROM1010:ROM16_16:= (
X"7FC1",X"7E5F",X"7BC5",X"77FA",X"7307",X"6CF8",X"65DD",X"5DC7",
X"54C9",X"4AFB",X"4073",X"354D",X"29A3",X"1D93",X"113A",X"04B6");
constant ROM0110:ROM16_16:= (
X"7FE9",X"7ED5",X"7C88",X"7909",X"745F",X"6E96",X"67BC",X"5FE3",
X"571D",X"4D81",X"4325",X"3824",X"2C99",X"209F",X"1455",X"07D9");
constant ROM1110:ROM16_16:= (
X"7F86",X"7DD5",X"7AEE",X"76D8",X"719D",X"6B4A",X"63EE",X"5B9C",
X"5268",X"4869",X"3DB8",X"326E",X"26A8",X"1A82",X"0E1C",X"0192");
constant ROM0001:ROM16_16:= (
X"7FFE",X"7F4D",X"7D62",X"7A41",X"75F3",X"7083",X"69FD",X"6271",
X"59F3",X"5097",X"4675",X"3BA5",X"3041",X"2467",X"1833",X"0BC4");
constant ROM0011:ROM16_16:= (
X"7FF9",X"7F21",X"7D0E",X"79C8",X"7555",X"6FC1",X"6919",X"616E",
X"58D3",X"4F5D",X"4524",X"3A40",X"2ECC",X"22E5",X"16A8",X"0A33");
constant ROM0101:ROM16_16:= (
X"7FF0",X"7EEF",X"7CB6",X"794A",X"74B2",X"6EFB",X"6832",X"6068",
X"57B0",X"4E20",X"43D0",X"38D9",X"2D55",X"2161",X"151C",X"08A2");
constant ROM0111:ROM16_16:= (
X"7FE1",X"7EB9",X"7C59",X"78C7",X"740A",X"6E30",X"6746",X"5F5D",
X"568A",X"4CE0",X"427A",X"376F",X"2BDC",X"1FDD",X"138F",X"0711");
constant ROM1001:ROM16_16:= (
X"7FCD",X"7E7E",X"7BF8",X"783F",X"735E",X"6D61",X"6656",X"5E4F",
X"5560",X"4B9D",X"4121",X"3604",X"2A61",X"1E57",X"1201",X"057F");
constant ROM1011:ROM16_16:= (
X"7FB4",X"7E3E",X"7B91",X"77B3",X"72AE",X"6C8E",X"6563",X"5D3E",
X"5432",X"4A58",X"3FC5",X"3496",X"28E5",X"1CCF",X"1072",X"03ED");
constant ROM1101:ROM16_16:= (
X"7F97",X"7DFA",X"7B26",X"7722",X"71F9",X"6BB7",X"646C",X"5C28",
X"5302",X"490F",X"3E68",X"3326",X"2767",X"1B47",X"0EE3",X"025B");
constant ROM1111:ROM16_16:= (
X"7F74",X"7DB0",X"7AB6",X"768D",X"7140",X"6ADC",X"6370",X"5B0F",
X"51CE",X"47C3",X"3D07",X"31B5",X"25E8",X"19BE",X"0D54",X"00C9");
constant ROMINCR:ROM128_8:= (
X"00",X"01",X"02",X"04",X"05",X"06",X"07",X"09",
X"0a",X"0b",X"0d",X"0e",X"0f",X"10",X"11",X"12",
X"13",X"15",X"16",X"17",X"19",X"1a",X"1b",X"1c",
X"1d",X"1e",X"1f",X"21",X"22",X"23",X"24",X"25",
X"27",X"28",X"29",X"2a",X"2b",X"2c",X"2d",X"2e",
X"2f",X"30",X"32",X"33",X"34",X"35",X"36",X"37",
X"38",X"39",X"3a",X"3b",X"3c",X"3d",X"3e",X"3f",
X"40",X"41",X"42",X"43",X"44",X"45",X"45",X"46",
X"47",X"48",X"49",X"4a",X"4b",X"4c",X"4d",X"4d",
X"4e",X"4f",X"4f",X"50",X"51",X"52",X"53",X"53",
X"54",X"55",X"55",X"56",X"56",X"57",X"58",X"58",
X"58",X"59",X"59",X"5a",X"5b",X"5b",X"5c",X"5d",
X"5d",X"5d",X"5e",X"5f",X"5f",X"5f",X"5f",X"60",
X"60",X"60",X"61",X"61",X"62",X"62",X"62",X"62",
X"63",X"63",X"63",X"63",X"64",X"64",X"64",X"64",
X"64",X"64",X"64",X"64",X"64",X"64",X"64",X"64");
signal MUX:std_logic_vector(wwdth-1 downto 0);
signal MUXi:std_logic_vector(15 downto 0);
signal AD: std_logic_vector(1 downto 0);
begin
ADDR<=ADDRROM(n-3 downto 0);
N16: if n=4 generate
AD<=ADDR;
with AD select
MUXi<=X"7FFF" when "00",
X"7641" when "01" ,
X"5A82" when "10" ,
X"30FB" when others;
MUX<=MUXi(14 downto 15- wwdth);
end generate;
N32: if n=5 generate
process (ADDR) is
variable B:std_logic_vector(15 downto 0);
begin
B:=ROM0000(conv_integer(ADDR&'0'));
MUX<=B(14 downto 15- wwdth);
end process;
end generate;
N64: if n=6 generate
process (ADDR) is
variable B:std_logic_vector(15 downto 0);
begin
B:=ROM0000(conv_integer(ADDR));
MUX<=B(14 downto 15- wwdth);
end process;
end generate;
N128: if n=7 generate
process (ADDR) is
variable B0,B1:std_logic_vector(15 downto 0);
begin
B0:=ROM0000(conv_integer(ADDR(4 downto 1)));
B1:=ROM1000(conv_integer(ADDR(4 downto 1)));
case ADDR(0) is
when '0' => MUX<=B0(14 downto 15- wwdth);
when '1' => MUX<=B1(14 downto 15- wwdth);
when others => null ;
end case;
end process;
end generate;
N256: if n=8 generate
process (ADDR) is
variable B00:std_logic_vector(15 downto 0);
variable B01:std_logic_vector(15 downto 0);
variable B10:std_logic_vector(15 downto 0);
variable B11:std_logic_vector(15 downto 0);
variable sel:std_logic_vector(1 downto 0);
begin
B00:=ROM0000(conv_integer(ADDR(5 downto 2)));
B01:=ROM0100(conv_integer(ADDR(5 downto 2)));
B10:=ROM1000(conv_integer(ADDR(5 downto 2)));
B11:=ROM1100(conv_integer(ADDR(5 downto 2)));
sel:=ADDR(1 downto 0) ;
case sel is
when "00" => MUX<=B00(14 downto 15- wwdth);
when "01" => MUX<=B01(14 downto 15- wwdth);
when "10" => MUX<=B10(14 downto 15- wwdth);
when "11" => MUX<=B11(14 downto 15- wwdth);
when others => null ;
end case;
end process;
end generate;
N512: if n=9 generate
process (ADDR) is
variable B000,B001:std_logic_vector(15 downto 0);
variable B010,B011:std_logic_vector(15 downto 0);
variable B100,B101:std_logic_vector(15 downto 0);
variable B110,B111:std_logic_vector(15 downto 0);
variable sel:std_logic_vector(2 downto 0);
begin
B000:=ROM0000(conv_integer(ADDR(6 downto 3)));
B001:=ROM0010(conv_integer(ADDR(6 downto 3)));
B010:=ROM0100(conv_integer(ADDR(6 downto 3)));
B011:=ROM0110(conv_integer(ADDR(6 downto 3)));
B100:=ROM1000(conv_integer(ADDR(6 downto 3)));
B101:=ROM1010(conv_integer(ADDR(6 downto 3)));
B110:=ROM1100(conv_integer(ADDR(6 downto 3)));
B111:=ROM1110(conv_integer(ADDR(6 downto 3)));
sel:=ADDR(2 downto 0) ;
case sel is
when "000" =>MUX<=B000(14 downto 15- wwdth);
when "001" =>MUX<=B001(14 downto 15- wwdth);
when "010" =>MUX<=B010(14 downto 15- wwdth);
when "011" =>MUX<=B011(14 downto 15- wwdth);
when "100" =>MUX<=B100(14 downto 15- wwdth);
when "101" =>MUX<=B101(14 downto 15- wwdth);
when "110" =>MUX<=B110(14 downto 15- wwdth);
when "111" =>MUX<=B111(14 downto 15- wwdth);
when others => null ;
end case;
end process;
end generate;
N1024: if n=10 generate
process (ADDR) is
variable B0000:std_logic_vector(15 downto 0);
variable B0001:std_logic_vector(15 downto 0);
variable B0010:std_logic_vector(15 downto 0);
variable B0011:std_logic_vector(15 downto 0);
variable B0100,B0101,B0110,B0111:std_logic_vector(15 downto 0);
variable B1000,B1001,B1010,B1011:std_logic_vector(15 downto 0);
variable B1100,B1101,B1110,B1111:std_logic_vector(15 downto 0);
variable sel:std_logic_vector(3 downto 0);
begin
B0000:=ROM0000(conv_integer(ADDR(7 downto 4)));
B0001:=ROM0001(conv_integer(ADDR(7 downto 4)));
B0010:=ROM0010(conv_integer(ADDR(7 downto 4)));
B0011:=ROM0011(conv_integer(ADDR(7 downto 4)));
B0100:=ROM0100(conv_integer(ADDR(7 downto 4)));
B0101:=ROM0101(conv_integer(ADDR(7 downto 4)));
B0110:=ROM0110(conv_integer(ADDR(7 downto 4)));
B0111:=ROM0111(conv_integer(ADDR(7 downto 4)));
B1000:=ROM1000(conv_integer(ADDR(7 downto 4)));
B1001:=ROM1001(conv_integer(ADDR(7 downto 4)));
B1010:=ROM1010(conv_integer(ADDR(7 downto 4)));
B1011:=ROM1011(conv_integer(ADDR(7 downto 4)));
B1100:=ROM1100(conv_integer(ADDR(7 downto 4)));
B1101:=ROM1101(conv_integer(ADDR(7 downto 4)));
B1110:=ROM1110(conv_integer(ADDR(7 downto 4)));
B1111:=ROM1111(conv_integer(ADDR(7 downto 4)));
sel:=ADDR(3 downto 0) ;
case sel is
when "0000" =>MUX<=B0000(14 downto 15- wwdth);
when "0001" =>MUX<=B0001(14 downto 15- wwdth);
when "0010" =>MUX<=B0010(14 downto 15- wwdth);
when "0011" =>MUX<=B0011(14 downto 15- wwdth);
when "0100" =>MUX<=B0100(14 downto 15- wwdth);
when "0101" =>MUX<=B0101(14 downto 15- wwdth);
when "0110" =>MUX<=B0110(14 downto 15- wwdth);
when "0111" =>MUX<=B0111(14 downto 15- wwdth);
when "1000" =>MUX<=B1000(14 downto 15- wwdth);
when "1001" =>MUX<=B1001(14 downto 15- wwdth);
when "1010" =>MUX<=B1010(14 downto 15- wwdth);
when "1011" =>MUX<=B1011(14 downto 15- wwdth);
when "1100" =>MUX<=B1100(14 downto 15- wwdth);
when "1101" =>MUX<=B1101(14 downto 15- wwdth);
when "1110" =>MUX<=B1110(14 downto 15- wwdth);
when "1111" =>MUX<=B1111(14 downto 15- wwdth);
when others => null ;
end case;
end process;
end generate;
N2048: if n=11 generate
process (ADDR) is
variable B0000:std_logic_vector(15 downto 0);
variable B0001:std_logic_vector(15 downto 0);
variable B0010:std_logic_vector(15 downto 0);
variable B0011:std_logic_vector(15 downto 0);
variable B0100,B0101,B0110,B0111:std_logic_vector(15 downto 0);
variable B1000,B1001,B1010,B1011:std_logic_vector(15 downto 0);
variable B1100,B1101,B1110,B1111:std_logic_vector(15 downto 0);
variable MUXI:std_logic_vector(wwdth-1 downto 0);
variable INCI:std_logic_vector(wwdth-8 downto 0);
variable INC:std_logic_vector(7 downto 0);
variable sel:std_logic_vector(3 downto 0);
begin
INC:=ROMINCR(conv_integer(ADDR(8 downto 2)));
INCI:=INC( 7 downto 15- wwdth);
B0000:=ROM0000(conv_integer(ADDR(8 downto 5)));
B0001:=ROM0001(conv_integer(ADDR(8 downto 5)));
B0010:=ROM0010(conv_integer(ADDR(8 downto 5)));
B0011:=ROM0011(conv_integer(ADDR(8 downto 5)));
B0100:=ROM0100(conv_integer(ADDR(8 downto 5)));
B0101:=ROM0101(conv_integer(ADDR(8 downto 5)));
B0110:=ROM0110(conv_integer(ADDR(8 downto 5)));
B0111:=ROM0111(conv_integer(ADDR(8 downto 5)));
B1000:=ROM1000(conv_integer(ADDR(8 downto 5)));
B1001:=ROM1001(conv_integer(ADDR(8 downto 5)));
B1010:=ROM1010(conv_integer(ADDR(8 downto 5)));
B1011:=ROM1011(conv_integer(ADDR(8 downto 5)));
B1100:=ROM1100(conv_integer(ADDR(8 downto 5)));
B1101:=ROM1101(conv_integer(ADDR(8 downto 5)));
B1110:=ROM1110(conv_integer(ADDR(8 downto 5)));
B1111:=ROM1111(conv_integer(ADDR(8 downto 5)));
sel:=ADDR(4 downto 1) ;
case sel is
when "0000" =>MUXI:=B0000(14 downto 15- wwdth);
when "0001" =>MUXI:=B0001(14 downto 15- wwdth);
when "0010" =>MUXI:=B0010(14 downto 15- wwdth);
when "0011" =>MUXI:=B0011(14 downto 15- wwdth);
when "0100" =>MUXI:=B0100(14 downto 15- wwdth);
when "0101" =>MUXI:=B0101(14 downto 15- wwdth);
when "0110" =>MUXI:=B0110(14 downto 15- wwdth);
when "0111" =>MUXI:=B0111(14 downto 15- wwdth);
when "1000" =>MUXI:=B1000(14 downto 15- wwdth);
when "1001" =>MUXI:=B1001(14 downto 15- wwdth);
when "1010" =>MUXI:=B1010(14 downto 15- wwdth);
when "1011" =>MUXI:=B1011(14 downto 15- wwdth);
when "1100" =>MUXI:=B1100(14 downto 15- wwdth);
when "1101" =>MUXI:=B1101(14 downto 15- wwdth);
when "1110" =>MUXI:=B1110(14 downto 15- wwdth);
when "1111" =>MUXI:=B1111(14 downto 15- wwdth);
when others => null ;
end case;
if ADDR(0)='1' then
MUX<=CONV_STD_LOGIC_VECTOR((unsigned(MUXI)-unsigned(INCi)),wwdth);
else
MUX<=MUXI;
end if;
end process;
end generate;
process(ADDRROM,addrful)
variable windi: STD_LOGIC_VECTOR(15 downto 0);
begin
addrful<=ADDRROM(n-3 downto 0)&nulls;
if ADDRROM(n-2)='0' then
windi:=hann(conv_integer(addrful));
wind<=windi(14 downto 15-wwdth);
else
--wind(wwdth-1)<='0' ;
wind(wwdth-1 downto 0)<=(others=>'1');
end if;
end process;
COS<=MUX when SELW='0'
else wind when wnd=1 else (others=>'1');
end DISTR;
 
/fft_fir_filter/trunk/rtl/denorm.vhd
0,0 → 1,320
 
---------------------------------------------------------------------
---- ----
---- FFT Filter IP core ----
---- ----
---- Authors: Anatoliy Sergienko, Volodya Lepeha ----
---- Company: Unicore Systems http://unicore.co.ua ----
---- ----
---- Downloaded from: http://www.opencores.org ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2006-2010 Unicore Systems LTD ----
---- www.unicore.co.ua ----
---- o.uzenkov@unicore.co.ua ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED "AS IS" ----
---- AND ANY EXPRESSED OR IMPLIED WARRANTIES, ----
---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ----
---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ----
---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ----
---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ----
---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ----
---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ----
---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ----
---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ----
---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ----
---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ----
---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ----
---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-- Data is shifted right and then written when is address is
-- betweenn 0100..0 and 1011..1
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
 
entity DENORM is
generic (width: integer :=8 ; -- word width =8...24
n:INTEGER:=7 ;
satur:INTEGER:=1 ; --1 - usilenie s ogranicheniem
reall:INTEGER:= 0 ;
v2:INTEGER:=1 );-- 1 - Virtex2
port (
CLK: in STD_LOGIC;
RST: in STD_LOGIC;
CE: in STD_LOGIC;
DATAE: in STD_LOGIC;
START: in STD_LOGIC; --
INIT: in STD_LOGIC; --
WERES: in STD_LOGIC;
SPRDY: in STD_LOGIC;
ADDRRES: in STD_LOGIC_VECTOR (n-1 downto 0);
EXPI: in STD_LOGIC_VECTOR (3 downto 0);
EXPF: in STD_LOGIC_VECTOR (3 downto 0);
REDI: in STD_LOGIC_VECTOR (width-1 downto 0);
IMDI: in STD_LOGIC_VECTOR (width-1 downto 0);
RDY: out STD_LOGIC;
REDO: out STD_LOGIC_VECTOR (width-1 downto 0);
IMDO: out STD_LOGIC_VECTOR (width-1 downto 0)
);
end DENORM;
 
 
architecture FFTDPATH_s of DENORM is
component RAMB16_S36_S36 is
port (DIA : in STD_LOGIC_VECTOR (31 downto 0);
DIB : in STD_LOGIC_VECTOR (31 downto 0);
DIPA : in STD_LOGIC_VECTOR (3 downto 0);
DIPB : in STD_LOGIC_VECTOR (3 downto 0);
ENA : in STD_ULOGIC;
ENB : in STD_ULOGIC;
WEA : in STD_ULOGIC;
WEB : in STD_ULOGIC;
SSRA : in STD_ULOGIC;
SSRB : in STD_ULOGIC;
CLKA : in STD_ULOGIC;
CLKB : in STD_ULOGIC;
ADDRA : in STD_LOGIC_VECTOR (8 downto 0);
ADDRB : in STD_LOGIC_VECTOR (8 downto 0);
DOA : out STD_LOGIC_VECTOR (31 downto 0);
DOB : out STD_LOGIC_VECTOR (31 downto 0);
DOPA : out STD_LOGIC_VECTOR (3 downto 0);
DOPB : out STD_LOGIC_VECTOR (3 downto 0)
);
end component;
component RAMB16_S18_S18 is
port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
DIPA : in STD_LOGIC_VECTOR (1 downto 0);
DIPB : in STD_LOGIC_VECTOR (1 downto 0);
ENA : in STD_ULOGIC;
ENB : in STD_ULOGIC;
WEA : in STD_ULOGIC;
WEB : in STD_ULOGIC;
SSRA : in STD_ULOGIC;
SSRB : in STD_ULOGIC;
CLKA : in STD_ULOGIC;
CLKB : in STD_ULOGIC;
ADDRA : in STD_LOGIC_VECTOR (9 downto 0);
ADDRB : in STD_LOGIC_VECTOR (9 downto 0);
DOA : out STD_LOGIC_VECTOR (15 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0);
DOPA : out STD_LOGIC_VECTOR (1 downto 0);
DOPB : out STD_LOGIC_VECTOR (1 downto 0)
);
end component;
constant nulls:std_logic_vector(31 downto 0):=X"00000000";
constant ones:std_logic_vector(n-1 downto 0):=(others=>'1');
constant plus1:std_logic_vector(17 downto 0):="011111111111111111";
constant minus1:std_logic_vector(17 downto 0):="100000000000000000";
constant gnd:STD_LOGIC:='0';
constant endaddrr:std_logic_vector(9 downto 0):=nulls(9-n downto 0)&ones;
constant endaddr:STD_LOGIC_VECTOR (9 downto 0):=
conv_std_logic_vector((2**n-10),10);
signal exp,expfi:std_logic_vector(3 downto 0);
signal DRES,DIMS:std_logic_vector(17 downto 0);
signal DRESS,DIMSS:std_logic_vector(18 downto 0);
signal DRE0,DIM0,DIMou,REDOi,REDOii,IMDOi,IMDOii:std_logic_vector(17 downto 0);
signal DRE0i,DIM0i,DRESi,DIMSi:std_logic_vector(31 downto 0);
signal D32,D32o:std_logic_vector(31 downto 0);
signal D4,D4o:std_logic_vector(3 downto 0);
signal ADDR:std_logic_vector(n-1 downto 0);
signal ADDRW,addrr:std_logic_vector(9 downto 0);
signal WEM,an:STD_LOGIC;
begin
RC:process(CLK,RST)
variable exi:STD_LOGIC_VECTOR(4 downto 0);
begin
if RST='1' then
exp<="0000";
expfi<="0000";
elsif rising_edge(CLK) then
if SPRDY='1' then
if reall=1 then
expfi<=EXPF;
else
expfi<=EXPF+2;
end if;
end if;
exi:='0'&EXPI+ EXPFi; --common exponent
--if exi(4)='1' then
-- exi:="00000";
-- end if;
if INIT='1' then
EXP<=exi(3 downto 0);
end if;
end if;
end process;
DRE0i<=SXT(REDI,32) ;
DIM0i<=SXT(IMDI,32);
DRESi <= SHL(DRE0i,exp);
DIMSi <= SHL(DIM0i,exp);
DRESs<=DRESi(20+n downto n+2);
DIMSs<=DIMSi(20+n downto n+2);
SAT:if satur=1 generate
DRES<= plus1 when DRESS(18)='0' and DRESS(17)='1' else
minus1 when DRESS(18)='1' and DRESS(17)='0' else
DRESS(17 downto 0);
DIMS<= plus1 when DIMSS(18)='0' and DIMSS(17)='1' else
minus1 when DIMSS(18)='1' and DIMSS(17)='0' else
DIMSS(17 downto 0);
end generate;
NSAT:if satur=0 generate
DRES<= DRESS(17 downto 0);
DIMS<=DIMSS(17 downto 0);
end generate;
D32<=DIMS(13 downto 0)&DRES;
D4<=DIMS(17 downto 14);
ADDR<=ADDRRES;
ADR:process(addr) begin
ADDRW<=(others=>'0');
ADDRW(n-1)<=an;
ADDRW(n-2)<=not ADDR(n-2);-- not ADDR(n-2);
ADDRW(n-3 downto 0)<= ADDR(n-3 downto 0);
end process;
WEM<=WERES when (ADDR(n-1) xor ADDR(n-2))='1' else '0';
--WEM<=WERES when ADDR(n-1)='0' else '0';
CTO:process(CLK,RST)
variable ea: std_logic_vector(9 downto 0);
begin
if reall=0 then
ea:=endaddr;--"0000000000";
else
ea:=endaddrr;
end if;
if RST='1' then
RDY<='0';
an<='0';
addrr<=ea;
elsif rising_edge(CLK) then
if start ='1' then
an<='1';
addrr<=ea;--0000000000";
elsif DATAE='1' then
if addrr(n-1 downto 0)=nulls(n-1 downto 0) then--ones(n-1 downto 0) then
addrr<=endaddrr;
RDY<='1';
else
RDY<='0';
addrr<=addrr-1; --adres tshtenija dla wydachi resultata
end if;
end if;
if init='1' then
an<=not an;
end if;
end if;
end process;
RAM_V2_9: if V2=1 and n<=9 generate
U_RAM512: RAMB16_S36_S36
port map (DIA=>D32,
DIB =>nulls,
DIPA =>D4,
DIPB =>nulls(3 downto 0),
ENA =>CE,
ENB =>CE,
WEA =>WEM,
WEB =>gnd,
SSRA =>gnd,
SSRB =>gnd,
CLKA =>CLK,
CLKB =>CLK,
ADDRA =>ADDRW(8 downto 0),
ADDRB =>ADDRR(8 downto 0),
DOA =>open,
DOB =>D32o,
DOPA =>open,
DOPB =>d4o );
REDO<= D32o(17 downto 18-width) ;
DIMou<= D4o & D32o(31 downto 18);
IMDO<= DIMOu(17 downto 18-width) ;
end generate;
RAM_V2_10: if V2=1 and n=10 generate
U_RAM1024_0: RAMB16_S18_S18
port map (DIA=>DRES(15 downto 0),
DIB =>nulls(15 downto 0),
DIPA =>DRES(17 downto 16),
DIPB =>nulls(1 downto 0),
ENA =>CE,
ENB =>CE,
WEA =>WEM,
WEB =>gnd,
SSRA =>gnd,
SSRB =>gnd,
CLKA =>CLK,
CLKB =>CLK,
ADDRA =>ADDRW,
ADDRB =>ADDRR,
DOA =>open,
DOB =>REDOi(15 downto 0),
DOPA =>open,
DOPB =>REDOi(17 downto 16));
U_RAM1024_1: RAMB16_S18_S18
port map (DIA=>DIMS(15 downto 0),
DIB =>nulls(15 downto 0),
DIPA =>DIMS(17 downto 16),
DIPB =>nulls(1 downto 0),
ENA =>CE,
ENB =>CE,
WEA =>WEM,
WEB =>gnd,
SSRA =>gnd,
SSRB =>gnd,
CLKA =>CLK,
CLKB =>CLK,
ADDRA =>ADDRW,
ADDRB =>ADDRR,
DOA =>open,
DOB =>IMDOi(15 downto 0),
DOPA =>open,
DOPB =>IMDOi(17 downto 16));
REDO<= REDOi(17 downto 18-width) ;
IMDO<= IMDOi(17 downto 18-width) ;
end generate;
end FFTDPATH_s;
/fft_fir_filter/trunk/rtl/control_slip.vhd
0,0 → 1,591
---------------------------------------------------------------------
---- ----
---- FFT Filter IP core ----
---- ----
---- Authors: Anatoliy Sergienko, Volodya Lepeha ----
---- Company: Unicore Systems http://unicore.co.ua ----
---- ----
---- Downloaded from: http://www.opencores.org ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2006-2010 Unicore Systems LTD ----
---- www.unicore.co.ua ----
---- o.uzenkov@unicore.co.ua ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED "AS IS" ----
---- AND ANY EXPRESSED OR IMPLIED WARRANTIES, ----
---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ----
---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ----
---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ----
---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ----
---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ----
---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ----
---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ----
---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ----
---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ----
---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ----
---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ----
---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
 
entity CONTROL is
generic ( ifft:INTEGER:=0;
rams:INTEGER:=2;
n:INTEGER:=8; -- 6,7,8,9,10,11
slip:INTEGER;
reall:INTEGER:= 0 --wch. mass: 0 -complex 1 - 2 realnych
);
port (
CLK: in STD_LOGIC;
RST: in STD_LOGIC;
CE: in STD_LOGIC;
START: in STD_LOGIC;
DATAE: in STD_LOGIC;
OVERF: in STD_LOGIC;
FFTRDY: out STD_LOGIC;
READY: out STD_LOGIC;
WE: out STD_LOGIC;
WEI: out STD_LOGIC;
WEM: out STD_LOGIC;
WERES: out STD_LOGIC;
--HRES: out STD_LOGIC;
INITOVERF: out STD_LOGIC;
-- SEL: out STD_LOGIC; -- 0 -fromDIRE,DIIM, 1 - DMRE,DMIM
ODDC: out STD_LOGIC;
EVEN: out STD_LOGIC; --0- 0th bank 1- 1st bank -for DIRE,DIIM
DIV2: out STD_LOGIC;
ZWR: out STD_LOGIC;
ZWI: out STD_LOGIC;
SELW: out STD_LOGIC; --0 -twiddle 1 - window
SIGNRE: out STD_LOGIC;
MODE: out STD_LOGIC_VECTOR (1 downto 0);
EXP: out STD_LOGIC_VECTOR (3 downto 0);
ADDRR: out STD_LOGIC_VECTOR (n - 1 downto 0); -- data reading address
ADDRWIN: out STD_LOGIC_VECTOR (n - 1 downto 0);--input data writing address
ADDRWM: out STD_LOGIC_VECTOR (n - 1 downto 0) ;--working data writing address
ADDRRES: out STD_LOGIC_VECTOR (n - 1 downto 0);--result address
ADDRROM :out STD_LOGIC_VECTOR(n- 2 downto 0)
);
end CONTROL;
 
 
 
architecture CONTROL_slip of CONTROL is
constant NN: INTEGER:=2**n;
constant lat: INTEGER:=7; --latency
constant lat2: INTEGER:=7; --latency in butterflies
constant one:INTEGER:=2**(n-1);
constant onehalf:INTEGER:=2**(n-2);
signal strt,iarrdy,iarrdy1,go,god,god2,DATAED: STD_LOGIC;
signal fftfly,infly,resfly: STD_LOGIC; --FFT run flag,input flag,result fag
signal resrdy, resrdy2,idatardy: STD_LOGIC; --FFT result ready flag
signal fftend,FFTRDYi: STD_LOGIC; --FFT end flag
signal enditera:STD_LOGIC; --end of iteration
signal incbfly: STD_LOGIC; -- +1 to reading data address
signal incbflyw: STD_LOGIC; -- +1 to writing data address
signal startitera: STD_LOGIC; -- iteration start
signal startiterad1: STD_LOGIC; -- iteration start
signal startiterad0: STD_LOGIC; -- iteration start
signal ODDCi: STD_LOGIC; -- 1 when odd clock cycle
signal startiterad2: STD_LOGIC; --delayed iteration start
signal wefft: STD_LOGIC; --we fft data
signal addrwid, addrwidi :STD_LOGIC_VECTOR(n-1 downto 0); --I. data writing address
signal invaddr:STD_LOGIC_VECTOR(n-1 downto 0);--inverse writing address
signal itera:STD_LOGIC_VECTOR(n-1 downto 0); --iteration number
signal ADDRRi: STD_LOGIC_VECTOR (n-1 downto 0); --data reading address
signal ADDRwosst,addrrwin: STD_LOGIC_VECTOR (n-1 downto 0); --data reading address
signal ADDRWi: STD_LOGIC_VECTOR (n-1 downto 0); --data writimg address
signal addres0,addres1: STD_LOGIC_VECTOR (n-1 downto 0);
signal resnum,resnumi:STD_LOGIC_VECTOR (n-1 downto 0);
signal ADDRWwin,ADDRwwini,ADDRwnd: STD_LOGIC_VECTOR (n-1 downto 0); --data writimg address
signal ADDRF: STD_LOGIC_VECTOR (n-2 downto 0); --data writing address
signal bflies: STD_LOGIC_VECTOR (n downto 0); --butterfly counter
signal startiterad: STD_LOGIC_VECTOR (lat downto 1);
signal incaddrf:STD_LOGIC_VECTOR(n-2 downto 0); -- increment to the factor address
signal EXPi: STD_LOGIC_VECTOR (3 downto 0);
signal ADDRROMi :STD_LOGIC_VECTOR (n-2 downto 0);
signal WERESULTi,wed: STD_LOGIC;
signal irdy:STD_LOGIC_VECTOR (1 downto 0);
signal ird,winend,wewin: STD_LOGIC;
signal inflyd,resflyd:STD_LOGIC_VECTOR (15 downto 0);
signal fwd,fwdd,resend,resfld,wereswosst:STD_LOGIC;
constant nulls:STD_LOGIC_VECTOR (n-2 downto 0):=(others=>'0');
begin
CTIDATA:process(CLK,RST) -- data counter for input
begin
if RST='1' then
addrwidi<=(others=>'0');
addrwid<=(others=>'0');
irdy<="00";
ird<='0';
idatardy<= '0';
elsif CLK='1' and CLK'event then
if CE='1' then
if START='1' then -- or FFTRDYi='1'
addrwidi<= (others=>'0');
elsif DATAE='1' then --(strt='1' ) and or go='1' or god2='1'
irdy<="00";
if UNSIGNED(addrwidi)=NN-1 then
addrwidi<= (others=>'0');
irdy<="10";
else
addrwidi<=UNSIGNED(addrwidi)+1;
end if;
if UNSIGNED(addrwidi)=NN-1 then
irdy<="10";
elsif UNSIGNED(addrwidi)=NN/2-1 then
irdy<="01";
end if;
end if;
end if;
ird<= irdy(0)or irdy(1);
idatardy<= (irdy(0)or irdy(1)) and not ird;
end if;
end process;
CTRIDAT_W:process(CLK,RST,addrwwini) -- data counter for reading/writing to multiply by window
begin
if RST='1' then
addrrwin<=(others=>'0');
addrwnd<=(others=>'0');
addrwwini<=(others=>'0');
wewin<='0';
winend<='0';
EVEN<='1';
fwd<='1';
fwdd<='1';
winend<='0'; -- koniec umnozenia na okno
elsif CLK='1' and CLK'event then
if CE='1' then
EVEN<=not infly;
fwdd<=fwd;
inflyd<=inflyd(14 downto 0)& infly;
winend<='0';
if iarrdy='1' then -- or FFTRDYi='1'
fwd<='1';
addrrwin<= irdy(0)& nulls ;
addrwwini<=(others=>'0');
addrwnd<=(others=>'0');
elsif infly='1' then
addrrwin<=UNSIGNED(addrrwin)+1;
if UNSIGNED(addrrwin(n-2 downto 0))= nn/2-2 then
fwd<='0';
end if;
if fwd='1' then
addrwnd<=UNSIGNED(addrwnd)+1;--address okna
elsif fwdd='0' then
addrwnd<=UNSIGNED(addrwnd)-1;
end if;
if UNSIGNED(addrwnd)= nn-3 and fwd='0' then ---4
winend<='1'; --konec umnozenia na okno
end if;
end if;
if wewin='1' then -- inflyd(4)='1'
addrwwini<=UNSIGNED(addrwwini)+1;
end if;
wewin<=inflyd(3); --(4)
end if;
end if;
for i in 0 to n-1 loop
addrwwin(i)<=addrwwini(n-i-1); --addrwwini(i);-- --2-th inverse writing address
end loop;
end process;
CTLAT:process(RST,CLK) --delay on 1 LUT
begin
if RST='1' then
startiterad1<='0';
startiterad2<='0';
elsif CLK='1' and CLK'event then
if CE='1' then
startiterad1<=startitera;
startiterad2<=startiterad0;
end if;
end if;
end process;
CTLATS:process(RST,CLK) --delay on 1 LUT
begin
if CLK='1' and CLK'event then
if CE='1' then
startiterad<=startiterad(lat-1 downto 1)&startitera;
end if;
end if;
end process;
startiterad0<= startiterad(lat);
TODDC:process(CLK,RST) --odd cycle for FFT
begin
if RST='1' then
ODDCi<='0';
elsif CLK='1' and CLK'event then
if CE='1' then
if startitera='1' or FFTend='1' or resend='1' then
ODDCi<='0';
elsif fftfly='1' or resfly='1' then
ODDCi<= not ODDCi;
end if;
end if;
end if;
end process;
ODDC<= ODDCi;
CTRADDR:process(CLK,RST,ADDRRi) --FFT read counter
variable sum:STD_LOGIC_VECTOR (n downto 0);
variable inc:STD_LOGIC;
begin
if RST='1' then
incbfly<='0';
ADDRRi<=( others=>'0');
elsif CLK='1' and CLK'event then
if CE='1' then
if startitera='1' then
ADDRRi<=( others=>'0');
elsif fftfly='1' then
sum:=UNSIGNED('0'&ADDRRi)+UNSIGNED(itera);
inc:= sum(n);
ADDRRi<=UNSIGNED(sum(n-1 downto 0))+inc;
incbfly<=inc;
end if;
end if;
end if;
end process;
CTWADDR:process(CLK,RST,ADDRWi) --FFT write counter
variable sum:STD_LOGIC_VECTOR (n downto 0);
variable inc:STD_LOGIC;
begin
if RST='1' then
ADDRWi<=( others=>'0');
elsif CLK='1' and CLK'event then
if CE='1' then
if startiterad2='1' then
ADDRWi<=( others=>'0');
elsif fftfly='1' then
sum:=UNSIGNED('0'&ADDRWi)+UNSIGNED(itera);
inc:= sum(n);
ADDRWi<=UNSIGNED(sum(n-1 downto 0))+inc;
end if;
end if;
end if;
end process;
LINCADDRF:process(itera)
begin
for i in 0 to n-2 loop
incaddrf(i)<=itera(n-1-i);
end loop;
end process;
CTADDRF: process(CLK,RST) --iteration counter
begin
if RST='1' then
ADDRF<=( others=>'0');
elsif CLK='1' and CLK'event then
if CE='1' then
if startiterad1='1' then
ADDRF<=( others=>'0');
elsif fftfly='1' and incbfly = '1' then
ADDRF<=UNSIGNED(ADDRF)+UNSIGNED(incaddrf);
end if;
end if;
end if;
end process;
FADDRROM:process(CLK,RST)
begin
if RST='1' then
SIGNRE<='0';
ZWR<='0';
ZWI<='0';
ADDRROMi<=( others=>'0');
elsif CLK='1' and CLK'event then
if CE='1' then
if UNSIGNED(ADDRF)=onehalf then
ZWR<='1';
else
ZWR<='0';
end if;
if UNSIGNED(ADDRF)=0 or resfly='1' then
ZWI<='1';
else
ZWI<='0';
end if;
if ODDCi='1' then --cosine address
if ADDRF(n-2)='0' then
ADDRROMi<='0'&ADDRF(n-3 downto 0);
SIGNRE<='0';
else
ADDRROMi<=onehalf-UNSIGNED('0'&ADDRF(n-3 downto 0));
SIGNRE<='1';
end if;
else -- sine address
if ADDRF(n-2)='0' then
ADDRROMi<=onehalf -UNSIGNED('0'&ADDRF(n-3 downto 0));
else
ADDRROMi<='0'&ADDRF(n-3 downto 0);
end if;
end if;
end if;
end if;
end process;
CTBFLIES:process(CLK,RST,bflies) --butterfly counter
begin
if RST='1' then
wefft<='0';
enditera<='0';
bflies<=( others=>'0');
WERESULTi<='0';
FFTRDYi<='0';
elsif CLK='1' and CLK'event then
if CE='1' then
if startiterad2='1' then
wefft<='1';
if itera(n-1)='1'then
WERESULTi<='1';
end if;
end if;
if startitera='1' then
bflies<=( others=>'0');
elsif fftfly='1'
then
bflies<=UNSIGNED(bflies)+1;
end if;
if idatardy ='1' and go ='0' then
FFTRDYi<='1';
elsif UNSIGNED(bflies)=nn + lat2 and enditera='0' then
enditera<='1';
wefft<='0';
WERESULTi<='0';
if itera(n-1)='1' then
FFTRDYi<='1';
end if;
else
enditera<='0';
FFTRDYi<='0';
end if;
end if;
end if;
end process;
TIARRDY:process(CLK,RST) --1st input data ready
begin
if RST='1' then
iarrdy<='0';
iarrdy1<='0';
go<='0';
god<='0';
god2<='0';
elsif CLK='1' and CLK'event then
if CE='1' then
if START='1' then
iarrdy<='0';
iarrdy1<='0';
go<='0';
elsif idatardy='1' then
iarrdy<='1';
go<='1';
god<='0';
if go='0'
then
iarrdy1<='1';
end if;
else
god2<=god;
iarrdy<='0';
iarrdy1<='0';
if FFTRDYi='1' then
god<='1' ;
end if;
end if;
end if;
end if;
end process;
CTITERA:process(CLK,RST) --iteration counter
begin
if RST='1' then
itera<=CONV_STD_LOGIC_VECTOR(1,n);
elsif CLK='1' and CLK'event then
if CE='1' then
if FFTRDYi='1' then
itera<=CONV_STD_LOGIC_VECTOR(1,n);
elsif enditera='1' then
itera<=itera(n-2 downto 0)&'0';
end if;
end if;
end if;
end process;
CTWOSST:process(CLK,RST) -- data counters for wosstanowlenija
begin
if RST='1' then
addres0<=(others=>'0');
addres1<=(others=>'0');
resnumi<=(others=>'0');
resend<='0';
resfld<='0';
-- WERESwosst<='0';
elsif CLK='1' and CLK'event then
resend<='0';
if CE='1' then
resflyd<=resflyd(14 downto 0)& resfly;
resfld<=resflyd(6);
if fftend='1' then -- or FFTRDYi='1'
addres0<= (others=>'0');
addres1<= (others=>'0'); -- conv_std_logic_vector(NN,n+1);
resnumi<=(others=>'0');
elsif resfly='1' then
if oddci='1' then
addres0<=UNSIGNED(addres0)+1;
addres1<=UNSIGNED(addres1)-1;
end if;
if resfld='1' and resfly='1' then
resnumi<=UNSIGNED(resnumi)+1;
end if;
if UNSIGNED(resnumi)=nn-2 then ---1
resend<='1';
end if;
end if;
end if;
end if;
end process;
WERESwosst<=resfld and resfly;
addrwosst<=addres0 when oddci='1' else addres1(n-1 downto 0);
resnum<=resnumi(0)&resnumi(n-1 downto 1);
resrdy2<=resflyd(6) and not resfld;
TTFFTFLY:process(CLK,RST,enditera) --triggers of the FFT running
begin
if RST='1' then
infly<='0';
resfly<='0';
fftfly<='0';
resrdy<='0';
fftend<='0';
MODE<="00";
elsif CLK='1' and CLK'event then
if CE='1' then
if idatardy='1'then --iarrdy1='1'or FFTRDYi='1' then
infly<='1';
MODE<="00";
elsif winend='1' then
infly<='0';
fftfly<='1';
MODE<="01";
elsif FFTend='1' then
fftfly<='0';
if reall=1 then
resfly<='1';
MODE<="10";
end if;
elsif resend='1' then
resfly<='0';
MODE<="00";
end if;
resrdy<= startiterad0 and itera(n-1);
end if;
end if;
fftend<= (enditera and itera(n-1)) ;
end process;
REXP: process(CLK,RST) --exponent counter
begin
if RST='1' then
EXPi<=( others=>'0');
DIV2<='0';
elsif CLK='1' and CLK'event then
if CE='1' then
if winend='1' then
EXPi<=( 0 =>OVERF, others=>'0');
DIV2<= OVERF;
elsif enditera='1' or (fftend='1' and reall=1) then
if OVERF = '1' then
EXPi<=UNSIGNED(EXPi)+1;
DIV2<='1';
else
DIV2<='0';
end if;
elsif resend ='1' then
DIV2<='0';
end if;
end if;
end if;
end process;
WEI<=DATAE;
WEd<=DATAE;
ADDRWIN<=addrwidi;
FFTRDY<= FFTRDYi after 3 ns;
startitera<= (enditera and not FFTRDYi) or winend; -- idatardy;--
WEM<=wewin when infly='1'
else(wefft and fftfly); -- and not itera(n-1)
WERES<= WERESULTi when reall=0 else WERESwosst after 1 ns;
ADDRRES<= ADDRWi when fftfly='1' and reall=0 else resnum ;
ADDRR<=addrwosst when resfly='1' else
addrrwin when infly='1' else
ADDRRi ;
ADDRWM<=addrwwin when infly='1'
else ADDRWi;
SELW<= not (FFTfly or resfly);
INITOVERF<=startitera;-- and START;
ADDRROM<= addrwnd(n-2 downto 0) when infly='1'
else ADDRROMi(n-2 downto 0) when fftfly='1'
else (others=>'0');-- when oddci='1' else '1'&nulls(n-3 downto 0);
READY<=resrdy2 when reall=1 else resrdy after 3 ns;
EXP<=EXPi;
end CONTROL_slip;
/fft_fir_filter/trunk/rtl/control_i.vhd
0,0 → 1,720
---------------------------------------------------------------------
---- ----
---- FFT Filter IP core ----
---- ----
---- Authors: Anatoliy Sergienko, Volodya Lepeha ----
---- Company: Unicore Systems http://unicore.co.ua ----
---- ----
---- Downloaded from: http://www.opencores.org ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2006-2010 Unicore Systems LTD ----
---- www.unicore.co.ua ----
---- o.uzenkov@unicore.co.ua ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED "AS IS" ----
---- AND ANY EXPRESSED OR IMPLIED WARRANTIES, ----
---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ----
---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ----
---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ----
---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ----
---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ----
---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ----
---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ----
---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ----
---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ----
---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ----
---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ----
---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
 
entity CONTROLi is
generic (n:INTEGER; -- 6,7,8,9,10,11
reall:INTEGER:= 0 --wch. mass: 0 -complex 1 - 2 realnych
);
port (
CLK: in STD_LOGIC;
RST: in STD_LOGIC;
CE: in STD_LOGIC;
START: in STD_LOGIC;
DATAE: in STD_LOGIC;
OVERF: in STD_LOGIC;
FILTER: in STD_LOGIC_VECTOR (1 downto 0); --0 -ne filtruet 1 - filtruet 2-+diff 3 +2diff
L1:in STD_LOGIC_VECTOR (n-1 downto 0); -- tsastoty filtrow
H1:in STD_LOGIC_VECTOR (n-1 downto 0); -- tsastoty filtrow
L2:in STD_LOGIC_VECTOR (n-1 downto 0);
H2:in STD_LOGIC_VECTOR (n-1 downto 0);
FFTRDY: out STD_LOGIC;
READY: out STD_LOGIC;
WEI: out STD_LOGIC;
WEM: out STD_LOGIC;
WERES: out STD_LOGIC;
ODDC: out STD_LOGIC;
EVEN: out STD_LOGIC; --0- 0th bank 1- 1st bank -for DIRE,DIIM
DIV2: out STD_LOGIC;
ZWR: out STD_LOGIC;
ZWI: out STD_LOGIC;
SIGNRE: out STD_LOGIC;
INITOVERF: out STD_LOGIC;
RESRAM: out STD_LOGIC;
SEL: out STD_LOGIC; -- 0 -fromDIRE,DIIM, 1 - DMRE,DMIM
SELW: out STD_LOGIC_vector(1 downto 0); --0 -twiddle 1 - window
MODE: out STD_LOGIC_VECTOR (1 downto 0);
EXP: out STD_LOGIC_VECTOR (3 downto 0);
ADDRR: out STD_LOGIC_VECTOR (n downto 0);
ADDRWM: out STD_LOGIC_VECTOR (n downto 0) ;
ADDRRES: out STD_LOGIC_VECTOR (n - 1 downto 0);
ADDRROM :out STD_LOGIC_VECTOR(n- 2 downto 0)
);
end CONTROLi;
 
 
 
architecture CONTROL_slip of CONTROLi is
constant NN: INTEGER:=2**n;
constant lat: INTEGER:=6;--7; --latency
constant lat2: INTEGER:=7; --latency in butterflies
constant one:INTEGER:=2**(n-1);
constant onehalf:INTEGER:=2**(n-2);
signal startd,strt,iarrdy,iarrdy1,go,god,god2,DATAED: STD_LOGIC;
signal fftfly,filt1fly,filt2fly,filt3fly,resfly: STD_LOGIC; --FFT run flag,input flag,result fag
signal resrdy, idatardy: STD_LOGIC; --FFT result ready flag
signal fftend,FFTRDYi: STD_LOGIC; --FFT end flag
signal enditera:STD_LOGIC; --end of iteration
signal incbfly: STD_LOGIC; -- +1 to reading data address
signal incbflyw: STD_LOGIC; -- +1 to writing data address
signal startitera: STD_LOGIC; -- iteration start
signal startiterad1: STD_LOGIC; -- iteration start
signal startiterad0: STD_LOGIC; -- iteration start
signal ODDCi: STD_LOGIC; -- 1 when odd clock cycle
signal startiterad2: STD_LOGIC; --delayed iteration start
signal wefft: STD_LOGIC; --we fft data
signal addrwid, addrwidi :STD_LOGIC_VECTOR(n-1 downto 0); --I. data writing address
signal invaddr:STD_LOGIC_VECTOR(n-1 downto 0);--inverse writing address
signal itera:STD_LOGIC_VECTOR(n-1 downto 0); --iteration number
signal ADDRRi: STD_LOGIC_VECTOR (n-1 downto 0); --data reading address
signal ADDRwosstw: STD_LOGIC_VECTOR (n-1 downto 0); --data reading address
signal ADDRWi: STD_LOGIC_VECTOR (n-1 downto 0); --data writimg address
signal addres0,addres1: STD_LOGIC_VECTOR (n-1 downto 0);
signal resnum:STD_LOGIC_VECTOR (n-1 downto 0);
signal resnumi:STD_LOGIC_VECTOR (n downto 0);
signal ADDRwf,addrwfi,addrrf,addrrfi,ctt,addrfilt: STD_LOGIC_VECTOR (n-1 downto 0); --data writimg address
signal addrfilt1,addrfilt2: STD_LOGIC_VECTOR (4 downto 0);
signal ADDRF: STD_LOGIC_VECTOR (n-2 downto 0); --data writing address
signal bflies: STD_LOGIC_VECTOR (n downto 0); --butterfly counter
signal startiterad: STD_LOGIC_VECTOR (15 downto 0);
signal incaddrf:STD_LOGIC_VECTOR(n-2 downto 0); -- increment to the factor address
signal EXPi: STD_LOGIC_VECTOR (3 downto 0);
signal ADDRROMi,addrROMF :STD_LOGIC_VECTOR (n-2 downto 0);
signal WERESULTi,wed,filtd: STD_LOGIC;
signal irdy:STD_LOGIC_VECTOR (1 downto 0);
signal ird,winend,wefilt,outp: STD_LOGIC;
signal filt1flyd,filt2flyd,filt3flyd,resflyd:STD_LOGIC_VECTOR (15 downto 0);
signal fwd,fwdd,resend,wereswosst:STD_LOGIC;
signal filt1end,filt2end,filt3end:std_logic;
constant nulls:STD_LOGIC_VECTOR (n-1 downto 0):=(others=>'0');
constant ones:STD_LOGIC_VECTOR (n-1 downto 0):=(others=>'1');
constant oneh:STD_LOGIC_VECTOR (n downto 0):=
conv_std_logic_vector((nn),n+1);
constant nullsaf:STD_LOGIC_VECTOR (n-6 downto 0):=(others=>'0');
begin
CTRFILT1:process(CLK,RST,addrwfi,oddci) -- data counter for reading/writing to multiply by window
variable addrwfii: STD_LOGIC_VECTOR (n-1 downto 0);
begin
if RST='1' then
addrwfi<=(others=>'0');
ctt<=(others=>'0');
addrfilt1<=(others=>'0');
addrfilt2<=(others=>'0');
addrrfi<=(others=>'0');
wefilt<='0';
filt1end<='0'; -- koniec umnozenia na okno
EVEN<='0';
startd<='0';
filtd<='0';
addrROMF<=(others=>'0');
elsif CLK='1' and CLK'event then
if CE='1' then
filtd<=filt2fly or filt3fly;
EVEN<=filt1fly;
filt1flyd<=filt1flyd(14 downto 0)& filt1fly ;
filt2flyd<=filt2flyd(14 downto 0)& filt2fly;
filt3flyd<=filt3flyd(14 downto 0)& filt3fly;
filt1end<='0';
filt2end<='0';
filt3end<='0';
startd<=START;
if (START='0' and startd='1')
or (filt1end='1' and FILTER="10")
or (filt2end='1' and FILTER="11") then -- or FFTRDYi='1'
addrwfi<=(others=>'0');
ctt<=(others=>'0');
if L1=nulls then
addrfilt1<="01000";
else
addrfilt1<="00000";
end if;
if L2=nulls then
addrfilt2<="01000";
else
addrfilt2<="00000";
end if;
addrrfi<=(others=>'0');
wefilt<='0';
elsif filt1fly='1' then
if ODDCi='1' then
ctt<=ctt+1;
if ctt>=L1-5 and addrfilt1<8 then
addrfilt1<=addrfilt1+1;
end if;
if ctt>=H1-3 and addrfilt1<16 then
addrfilt1<=addrfilt1+1;
end if;
if ctt>=L2-5 and addrfilt2<8 then
addrfilt2<=addrfilt2+1;
end if;
if ctt>=H2-3 and addrfilt2<16 then
addrfilt2<=addrfilt2+1;
end if;
end if;
if wefilt='1' then
addrwfi<=addrwfi+1;--address zapisi
end if;
if filt1flyd(2)='1' then
wefilt<='1';
end if;
if addrwf= nn-1 then
filt1end<='1'; --konec umnozenia na okno
end if;
if addrwf= nn-1 or filt1end='1' then
wefilt<='0';
end if;
elsif (filt2fly or filt3fly)='1' then --filtd='1'---------differenciator
addrrfi<=addrrfi+1;
if wefilt='1' then
addrwfi<=addrwfi+1;--address zapisi
end if;
if (filt2flyd(3)='1')--and filt2fly='1')
or (filt3flyd(3)='1')--and filt3fly='1')
then
wefilt<='1';
end if;
if addrwfi= nn-1 then
if filt2fly='1' then
filt2end<='1'; --konec umnozenia na okno
wefilt<='0';
elsif filt3fly='1' then
filt3end<='1';
wefilt<='0';
end if;
end if;
end if;
addrROMF<=addrrfi(n-1 downto 1);
end if;
end if;
addrwfii:= addrwfi(0)&addrwfi(n-1 downto 1);
if (filt1fly='1' and reall=0)
or (filt2fly='1' and reall=0)
or (filt3fly='1' and reall=0 ) then
for i in 0 to n-1 loop
addrwf(i)<=addrwfii(n-i-1); --2-th inverse writing address
end loop;
else
addrwf<=addrwfi;
end if;
end process;
addrrf<=addrrfi ;--when oddci='0'
-- else not addrrfi;
addrfilt<=nullsaf & addrfilt1 when oddci='0' --'1'
else nullsaf & addrfilt2 ;
CTLAT:process(RST,CLK) --delay on 1 LUT
begin
if RST='1' then
startiterad1<='0';
startiterad2<='0';
elsif CLK='1' and CLK'event then
if CE='1' then
startiterad1<=startitera;
startiterad2<=startiterad0;
end if;
end if;
end process;
CTLATS:process(RST,CLK) --delay on 1 LUT
begin
if CLK='1' and CLK'event then
if CE='1' then
startiterad<=startiterad(14 downto 0)&startitera;
end if;
end if;
end process;
startiterad0<= startiterad(lat);
TODDC:process(CLK,RST) --odd cycle for FFT
begin
if RST='1' then
ODDCi<='0';
elsif CLK='1' and CLK'event then
if CE='1' then
if (START='0' and startd='1') or filt1end='1' or filt2end='1'or filt3end='1'
or startitera='1' or FFTend='1' or resend='1' then
ODDCi<='0';
else -- fftfly='1' or resfly='1' then
ODDCi<= not ODDCi;
end if;
end if;
end if;
end process;
ODDC<= ODDCi;
CTRADDR:process(CLK,RST,addrri) --FFT read counter
variable sum:STD_LOGIC_VECTOR (n downto 0);
variable inc:STD_LOGIC;
begin
if RST='1' then
incbfly<='0';
ADDRRi<=( others=>'0');
elsif CLK='1' and CLK'event then
if CE='1' then
if startitera='1' then
ADDRRi<=( others=>'0');
elsif fftfly='1' then
sum:='0'&ADDRRi+itera;
inc:= sum(n);
ADDRRi<=sum(n-1 downto 0)+inc;
incbfly<=inc;
end if;
end if;
end if;
end process;
CTWADDR:process(CLK,RST,ADDRWi) --FFT write counter
variable sum:STD_LOGIC_VECTOR (n downto 0);
variable inc:STD_LOGIC;
begin
if RST='1' then
ADDRWi<=( others=>'0');
elsif CLK='1' and CLK'event then
if CE='1' then
if startiterad2='1' then
ADDRWi<=( others=>'0');
elsif fftfly='1' then
sum:='0'&ADDRWi+itera;
inc:= sum(n);
ADDRWi<=sum(n-1 downto 0)+inc;
end if;
end if;
end if;
end process;
LINCADDRF:process(itera)
begin
for i in 0 to n-2 loop
incaddrf(i)<=itera(n-1-i);
end loop;
end process;
CTADDRF: process(CLK,RST) --iteration counter
begin
if RST='1' then
ADDRF<=( others=>'0');
elsif CLK='1' and CLK'event then
if CE='1' then
if startiterad1='1' then
ADDRF<=( others=>'0');
elsif fftfly='1' and incbfly = '1' then
ADDRF<=ADDRF+incaddrf;
end if;
end if;
end if;
end process;
FADDRROM:process(CLK,RST)
begin
if RST='1' then
SIGNRE<='0';
ZWR<='0';
ZWI<='0';
ADDRROMi<=( others=>'0');
elsif CLK='1' and CLK'event then
if CE='1' then
if ADDRF=onehalf then
ZWR<='1';
else
ZWR<='0';
end if;
if ADDRF=0 or resfly='1' then
ZWI<='1';
else
ZWI<='0';
end if;
if ODDCi='1' then --cosine address
if ADDRF(n-2)='0' then
ADDRROMi<='0'&ADDRF(n-3 downto 0);
SIGNRE<='0';
else
ADDRROMi<=onehalf-('0'&ADDRF(n-3 downto 0));
SIGNRE<='1';
end if;
else -- sine address
if ADDRF(n-2)='0' then
ADDRROMi<=onehalf -('0'&ADDRF(n-3 downto 0));
else
ADDRROMi<='0'&ADDRF(n-3 downto 0);
end if;
end if;
end if;
end if;
end process;
CTBFLIES:process(CLK,RST,bflies) --butterfly counter
begin
if RST='1' then
wefft<='0';
enditera<='0';
bflies<=( others=>'0');
WERESULTi<='0';
FFTRDYi<='0';
resrdy<='0';
elsif CLK='1' and CLK'event then
if CE='1' then
resrdy<= startitera and itera(n-2);
if startiterad2='1' then
wefft<='1';
if itera(n-1)='1'then
WERESULTi<='1';
end if;
end if;
if startitera='1' then
bflies<=( others=>'0');
elsif fftfly='1'
then
bflies<=bflies+1;
end if;
if idatardy ='1' and go ='0' then
FFTRDYi<='1';
elsif bflies=nn + lat2 and enditera='0' then
enditera<='1';
wefft<='0';
WERESULTi<='0';
if itera(n-1)='1' then
FFTRDYi<='1';
end if;
else
enditera<='0';
FFTRDYi<='0';
end if;
end if;
end if;
end process;
TIARRDY:process(CLK,RST) --1st input data ready
begin
if RST='1' then
iarrdy<='0';
iarrdy1<='0';
go<='0';
god<='0';
god2<='0';
elsif CLK='1' and CLK'event then
if CE='1' then
if START='1' then
iarrdy<='0';
iarrdy1<='0';
go<='0';
elsif idatardy='1' then
iarrdy<='1';
go<='1';
god<='0';
if go='0'
then
iarrdy1<='1';
end if;
else
god2<=god;
iarrdy<='0';
iarrdy1<='0';
if FFTRDYi='1' then
god<='1' ;
end if;
end if;
end if;
end if;
end process;
CTITERA:process(CLK,RST) --iteration counter
begin
if RST='1' then
itera<=CONV_STD_LOGIC_VECTOR(1,n);
elsif CLK='1' and CLK'event then
if CE='1' then
if FFTRDYi='1' then
itera<=CONV_STD_LOGIC_VECTOR(1,n);
elsif enditera='1' then
itera<=itera(n-2 downto 0)&'0';
end if;
end if;
end if;
end process;
CTWOSST:process(CLK,RST,addres0,addres1,oddci) -- data counters for wosstanowlenija
variable addrw:STD_LOGIC_VECTOR(n-1 downto 0);
begin
if RST='1' then
addres0<=(others=>'0');
addres1<=(others=>'0');
resnumi<=(others=>'0');
resend<='0';
-- WERESwosst<='0';
RESRAM<='0';
elsif CLK='1' and CLK'event then
if CE='1' then
resend<='0';
resflyd<=resflyd(14 downto 0)& resfly;
if (FILTER=0 and reall=1 and START='0' and startd = '1')
or (FILTER=1 and filt1end='1'and reall=1)
or (FILTER=2 and filt2end='1'and reall=1)
or (FILTER=3 and filt3end='1'and reall=1)
then
RESRAM<='0';
addres0<= (others=>'0');
addres1<= (others=>'0');
resnumi<=(others=>'0');
elsif resfly='1' then
if oddci='1' and resflyd(7)='1' then --'1'
addres0<=UNSIGNED(addres0)+1;
addres1<=UNSIGNED(addres1)-1;
end if;
resnumi<=UNSIGNED(resnumi)+1;
if resnumi=oneh then
RESRAM<='1';
end if;
end if;
if UNSIGNED(addres0)=nn/2 then
resend<='1';
end if;
if (resflyd(7) and resfly)='0' then
RESRAM<='0';
end if;
end if;
end if;
if oddci='0' then
addrw:= addres0;
else
addrw:= addres1;
end if;
--2-ja inversija
if reall=1 then
for i in 0 to n-1 loop
addrwosstw(i)<=addrw(n-i-1); --2-th inverse writing address
end loop;
else
addrwosstw<=addrw;
end if;
end process;
WERESwosst<=resflyd(7) and resfly;
resnum<=resnumi(n-1 downto 0);
TTFFTFLY:process(CLK,RST,enditera) --triggers of the FFT running
begin
if RST='1' then
filt1fly<='0';
filt2fly<='0';
filt3fly<='0';
resfly<='0';
fftfly<='0';
fftend<='0';
MODE<="00";
elsif CLK='1' and CLK'event then
if CE='1' then
if START='0' and startd = '1'then--
if FILTER=0 then
if reall=0 then
MODE<="01";
fftfly<='1';
else
resfly<='1';
MODE<="10";
end if;
else
filt1fly<='1';
MODE<="00";
end if;
elsif filt1end='1' then
filt1fly<='0';
if FILTER=1 then
if reall=0 then
MODE<="01";
fftfly<='1';
else
resfly<='1';
MODE<="10";
end if;
else
filt2fly<='1';
MODE<="11";
end if;
elsif filt2end='1' then
filt2fly<='0';
if FILTER=2 then
if reall=0 then
MODE<="01";
fftfly<='1';
else
MODE<="10";
resfly<='1';
end if;
else
filt3fly<='1';
MODE<="11";
end if;
elsif filt3end='1' then
filt3fly<='0';
if reall=0 then
MODE<="01";
fftfly<='1';
else
MODE<="10";
resfly<='1';
end if;
elsif resend='1' then
resfly<='0';
fftfly<='1';
MODE<="01";
elsif FFTend='1' then
fftfly<='0';
end if;
end if;
end if;
fftend<= (enditera and itera(n-1)) ;
end process;
REXP: process(CLK,RST) --exponent counter
begin
if RST='1' then
EXPi<=( others=>'0');
DIV2<='0';
elsif CLK='1' and CLK'event then
if CE='1' then
if ((FILTER=0 and start='0' and startd='1')
or (FILTER=1 and filt1end='1')
or (FILTER=2 and filt2end='1')
or (FILTER=3 and filt3end='1')) then
EXPi<=( 0 =>OVERF, others=>'0');
DIV2<= overf;
elsif startitera='1' and (fftfly='1' or resfly='1')then
if OVERF = '1' then
EXPi<=UNSIGNED(EXPi)+1;
DIV2<='1';
else
DIV2<='0';
end if;
elsif FFTRDYi='1' then
DIV2<='0';
end if;
end if;
end if;
end process;
--WEI<=DATAE;
WEd<=DATAE;
FFTRDY<= FFTRDYi after 3 ns;
startitera<= '1' when (enditera='1' and FFTRDYi='0')
or (filt1end='1' and FILTER=1 and reall=0)
or (filt2end='1' and FILTER=2 and reall=0 )
or (filt3end='1' and FILTER=3 and reall=0)
or (resend='1' and reall=1)
else '0';
WEM<=wefilt when filt1fly='1' or filt2fly='1'or filt3fly='1'
else wefft when fftfly='1'
else WERESwosst ;
WERES<= WERESULTi after 1 ns;
ADDRRES<= ADDRWi when fftfly='1' and itera(n-1)='1' else (others=>'0');
ADDRR<='1'& resnum when resfly='1'
else '1'& addrrf when filt2fly='1' or filt3fly='1'
else '0'& ADDRRi ;
ADDRWM<= '0'&addrwf when filt1fly='1'and FILTER=1 and reall=0
else '1'&addrwf when filt3fly='1' or filt2fly='1' or filt1fly='1'
else '0'&addrwosstw when resfly='1'
else '0'& ADDRWi;
SEL<='1' when (FILTER="00" and reall=0 and fftfly ='1' and itera(0)='1')
or(FILTER="00" and reall=1 and resfly ='1')
or(FILTER/="00" and filt1fly='1')
else '0';
SELW<= "01" when filt1fly='1' else
"10" when (Filt2fly or filt3fly)='1' else
"00";
INITOVERF<=startitera;-- and START;
ADDRROM<= addrfilt(n-2 downto 0) when filt1fly='1'
else addrROMF when filt2fly='1' or filt3fly='1'
else ADDRROMi(n-2 downto 0) when fftfly='1'
else (others=>'0');-- when oddci='1' else '1'&nulls(n-3 downto 0);
READY<=resrdy after 3 ns;
EXP<=EXPi;
end CONTROL_slip;
/fft_fir_filter/trunk/rtl/fftdpathi.vhd
0,0 → 1,296
---------------------------------------------------------------------
---- ----
---- FFT Filter IP core ----
---- ----
---- Authors: Anatoliy Sergienko, Volodya Lepeha ----
---- Company: Unicore Systems http://unicore.co.ua ----
---- ----
---- Downloaded from: http://www.opencores.org ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2006-2010 Unicore Systems LTD ----
---- www.unicore.co.ua ----
---- o.uzenkov@unicore.co.ua ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED "AS IS" ----
---- AND ANY EXPRESSED OR IMPLIED WARRANTIES, ----
---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ----
---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ----
---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ----
---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ----
---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ----
---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ----
---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ----
---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ----
---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ----
---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ----
---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ----
---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
 
-- AUTHORS Volodymir Lepekha,
-- Anatoli Sergyienko.
--HISTORY :07.2005 mode added:
-- 00 - multiply by window
-- 01 - butterfly
-- 10 - restore for real FFT
-- only for Virtex2 and later
--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
 
entity FFTDPATHI is
generic (width: integer :=8 ; -- word width =8...24
Wwdth: integer:=7; -- coefficient width =7...15
reall:integer;
V2:integer
);
port (
CLK: in STD_LOGIC;
RST: in STD_LOGIC;
CE: in STD_LOGIC;
ODDC: in STD_LOGIC; --
DIV2: in STD_LOGIC; --Scaling factor
ZWR: in STD_LOGIC;
ZWI: in STD_LOGIC;
SIGNRE: in STD_LOGIC;
MODE: in STD_LOGIC_VECTOR (1 downto 0);--00-umnozenie na okno, 01-FFT,10-wosstanowlenie
REDI: in STD_LOGIC_VECTOR (width downto 0);
IMDI: in STD_LOGIC_VECTOR (width downto 0);
WF: in STD_LOGIC_VECTOR (wwdth-1 downto 0);
REDO: out STD_LOGIC_VECTOR (width downto 0);
IMDO: out STD_LOGIC_VECTOR (width downto 0)
);
end FFTDPATHI;
 
 
architecture FFTDPATH_s of FFTDPATHI is
constant zeros: STD_LOGIC_VECTOR (width-wwdth downto 0):=
CONV_STD_LOGIC_VECTOR(0,width-wwdth+1);
signal ar,ai,ar3,ai3: STD_LOGIC_VECTOR (width-1 downto 0);
signal br1,bi1,br,bi,br2,bi2: STD_LOGIC_VECTOR (width-1 downto 0);
signal renorm,imnorm,br4,bi4: STD_LOGIC_VECTOR (width-1 downto 0);
signal ard,aid: STD_LOGIC_VECTOR (3 downto 0);
signal wr,wr1: STD_LOGIC_VECTOR (wwdth-1 downto 0);
signal prodrb,prodib: STD_LOGIC_VECTOR (width+wwdth downto 0);
signal prodr1,prodi1: STD_LOGIC_VECTOR (width+wwdth-2 downto wwdth-2);
signal prodr2,prodi2: STD_LOGIC_VECTOR (width+wwdth-1 downto wwdth-2);
signal prodr,prodi,prodrd,prodid: STD_LOGIC_VECTOR (width downto 0);
signal cr,ci: STD_LOGIC_VECTOR (width downto 0);
signal dr,di: STD_LOGIC_VECTOR (width+2 downto 0);
signal zwri,zwii,zwr1,zwi1,zwr2,zwi2,signrei,signre1,signre2: STD_LOGIC;
begin
SHIFT:process(REDI,IMDI,DIV2)
begin
if DIV2='1' then
renorm <= REDI (width downto 1);
imnorm <= IMDI (width downto 1);
else
renorm <= REDI(width-1 downto 0);
imnorm <= IMDI(width-1 downto 0);
end if;
end process;
RDELAY:process(CLK,RST)
begin
if RST = '1' then
wr <= (others =>'0');
wr1 <= (others =>'0');
ar <= (others =>'0');
br <= (others =>'0');
br1<= (others =>'0');
br2 <= (others =>'0');
ar3 <= (others =>'0');
br4 <= (others =>'0');
ai <= (others =>'0');
bi <= (others =>'0');
bi1<= (others =>'0');
bi2 <= (others =>'0');
ai3 <= (others =>'0');
bi4 <= (others =>'0');
elsif CLK = '1' and CLK'event then
if CE = '1' then
wr<=WF;
wr1<=wr;
br2<=br1;
bi2<=bi1;
if ODDC='0' or mode="00" or mode="11" then
ar<= renorm;
ar3<=ar;
br4<=br2;
ai<= imnorm;
ai3<=ai;
bi4<=bi2;
else
br<= renorm;
br1<=br;
bi<= imnorm;
bi1<=bi;
end if;
end if;
end if;
end process;
TTDELAY:process(CLK,RST)
begin
if RST='1' then
zwri<='0';
zwii<='0';
zwr1<='0';
zwi1<='0';
zwr2<='0';
zwi2<='0';
signrei<='0';
signre1<='0';
signre2<='0';
elsif CLK='1' and CLK'event then
if CE='1' then
zwri<=ZWR;
zwii<=ZWI;
zwr1<=zwri;
zwi1<=zwii;
zwr2<=zwr1;
zwi2<=zwi1;
signrei<=SIGNRE;
signre1<=signrei;
signre2<=signre1;
end if;
end if;
end process;
BLCK:if v2=1 generate
MPU_U: process(CLK,RST)
variable prodr,prodi:STD_LOGIC_VECTOR(width+wwdth-2 downto 0);
variable minusre,minusim:STD_LOGIC;
begin
if RST = '1' then
prodrb <= (others =>'0');
prodr2 <= (others =>'0');
prodib <= (others =>'0');
prodi2 <= (others =>'0');
elsif CLK = '1' and CLK'event then
if CE = '1' then
prodrb <= signed('0'& wr) * signed(ar);
prodib <= signed('0'& wr) * signed(ai);
prodr2<=prodrb(width+wwdth-1 downto wwdth-2);
prodi2<=prodib(width+wwdth-1 downto wwdth-2);
end if;
end if;
end process;
end generate;
prodr<=prodr2( width+wwdth-1 downto wwdth-1);
prodi<=prodi2( width+wwdth-1 downto wwdth-1);
RPRODD: process(CLK,RST)
begin
if RST='1' then
prodrd<=(others=>'0');
prodid<=(others=>'0');
elsif CLK='1' and CLK'event then
if CE ='1' then
if signre1='1' then
prodrd<= - signed(prodr);
prodid<= - signed(prodi);
else
prodrd<=prodr;
prodid<=prodi;
end if;
end if;
end if;
end process;
ACPROD:process(RST,CLK)
begin
if RST='1' then
cr<=(others=>'0');
ci<=(others=>'0');
elsif CLK='1' and CLK'event then
if CE ='1' and ODDC='0' then
if zwi2='1' then
cr <= ar3&'0';
ci <= ai3&'0';
elsif zwr2='1' then
cr <= 0- signed(ai3&'0');
ci <= ar3&'0';
else-- if signre2='1' then
-- cr<= 0- signed(prodrd)-signed(prodi);
-- ci<= 0- signed(prodid)+signed(prodr);
-- else
cr<= signed(prodrd)-signed(prodi);
ci<= signed(prodid)+signed(prodr);
-- end if;
end if;
end if;
end if;
end process;
ABUTTERF:process(CLK,RST)
begin
if RST='1' then
dr<=(others=>'0');
di<=(others=>'0');
elsif CLK='1' and CLK'event then
if CE ='1' then
case MODE is
when "00" => dr<=prodr&"01";
di<=prodI&"01" ;
when "11" => -- *jW
if ODDC='0' and reall=0 then
dr<=0-signed(prodi&"01"); --posle n/2
di<=prodr&"01" ;
else
dr<=prodi&"01";
di<=0-signed(prodr&"00") ; -- do n/2
end if;
when "01" => --butterfly
if ODDC='1' then --addition with rounding
dr<=signed(br4&"01")+signed( cr(width)&cr&'1');
di<=signed(bi4&"01")+signed( ci(width)&ci&'1');
else
dr<=signed(br4&"01")-signed( cr(width)&cr&'1');
di<=signed(bi4&"01")-signed( ci(width)&ci&'1');
end if;
when others=> -- Wosstanowlenie
if ODDC='1' then --addition with rounding
dr<=signed(br4&"01")-signed( ci(width)&ci&'1');
di<=signed(bi4&"01")+signed( cr(width)&cr&'1');
else
dr<=signed(br4&"01")+signed( ci(width)&ci&'1');
di<=signed( cr(width)&cr&'1')- signed(bi4&"01");
end if;
end case ;
end if;
end if;
end process;
REDO<= dr(width+2 downto 2) ;
IMDO<= di(width+2 downto 2);
end FFTDPATH_s;
/fft_fir_filter/trunk/rtl/ram1x_2.vhd
0,0 → 1,459
---------------------------------------------------------------------
---- ----
---- FFT Filter IP core ----
---- ----
---- Authors: Anatoliy Sergienko, Volodya Lepeha ----
---- Company: Unicore Systems http://unicore.co.ua ----
---- ----
---- Downloaded from: http://www.opencores.org ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2006-2010 Unicore Systems LTD ----
---- www.unicore.co.ua ----
---- o.uzenkov@unicore.co.ua ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED "AS IS" ----
---- AND ANY EXPRESSED OR IMPLIED WARRANTIES, ----
---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ----
---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ----
---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ----
---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ----
---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ----
---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ----
---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ----
---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ----
---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ----
---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ----
---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ----
---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
 
entity RAM1X_2 is
generic(width : INTEGER;
n:INTEGER; -- 6,7,8,9,10,11
v2:INTEGER:=1);
port (
CLK: in STD_LOGIC;
RST: in STD_LOGIC;
CE: in STD_LOGIC;
WE: in STD_LOGIC;
INITOVERF: in STD_LOGIC;
ADDRW: in STD_LOGIC_VECTOR (n downto 0);
ADDRR: in STD_LOGIC_VECTOR (n downto 0);
SEL: in STD_LOGIC; -- 0 -fromDIRE,DIIM, 1 - DMRE,DMIM
RESRAM: in STD_LOGIC;
DIRE: in STD_LOGIC_VECTOR (width-1 downto 0);
DIIM: in STD_LOGIC_VECTOR (width-1 downto 0);
DMRE: in STD_LOGIC_VECTOR (width-1 downto 0);
DMIM: in STD_LOGIC_VECTOR (width-1 downto 0);
OVERF:out STD_LOGIC;
DORE: out STD_LOGIC_VECTOR (width-1 downto 0);
DOIM: out STD_LOGIC_VECTOR (width-1 downto 0)
);
end RAM1X_2;
 
 
architecture RAM1X of RAM1X_2 is
component RAMB4_S1_S1 is
port (
CLKA,CLKB: in STD_LOGIC;
RSTA,RSTB: in STD_LOGIC;
ENA, ENB: in STD_LOGIC;
WEA, WEB: in STD_LOGIC;
ADDRA,ADDRB: in STD_LOGIC_VECTOR (11 downto 0);
DIA,DIB: in STD_LOGIC;
DOA,DOB: out STD_LOGIC );
end component;
component RAMB4_S2_S2 is
port (
CLKA, CLKB,RSTA,RSTB,ENA,ENB,WEA,WEB: in STD_LOGIC;
ADDRA,ADDRB: in STD_LOGIC_VECTOR (10 downto 0);
DIA,DIB: in STD_LOGIC_VECTOR (1 downto 0);
DOA,DOB: out STD_LOGIC_VECTOR (1 downto 0)
);
end component;
component RAMB4_S4_S4 is
port (
CLKA, CLKB,RSTA,RSTB,ENA,ENB,WEA,WEB: in STD_LOGIC;
ADDRA,ADDRB: in STD_LOGIC_VECTOR (9 downto 0);
DIA,DIB: in STD_LOGIC_VECTOR (3 downto 0);
DOA,DOB: out STD_LOGIC_VECTOR (3 downto 0)
);
end component;
component RAMB4_S8_S8 is
port (
CLKA, CLKB,RSTA,RSTB,ENA,ENB,WEA,WEB: in STD_LOGIC;
ADDRA,ADDRB: in STD_LOGIC_VECTOR (8 downto 0);
DIA,DIB: in STD_LOGIC_VECTOR (7 downto 0);
DOA,DOB: out STD_LOGIC_VECTOR (7 downto 0)
);
end component;
component RAMB4_S16_S16 is
port (
CLKA,CLKB,RSTA,RSTB,ENA,ENB,WEA,WEB: in STD_LOGIC;
ADDRA,ADDRB: in STD_LOGIC_VECTOR (7 downto 0);
DIA,DIB : in STD_LOGIC_VECTOR (15 downto 0);
DOA,DOB: out STD_LOGIC_VECTOR (15 downto 0)
);
end component;
component RAMB16_S18_S18 is
port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
DIPA : in STD_LOGIC_VECTOR (1 downto 0);
DIPB : in STD_LOGIC_VECTOR (1 downto 0);
ENA : in STD_ULOGIC;
ENB : in STD_ULOGIC;
WEA : in STD_ULOGIC;
WEB : in STD_ULOGIC;
SSRA : in STD_ULOGIC;
SSRB : in STD_ULOGIC;
CLKA : in STD_ULOGIC;
CLKB : in STD_ULOGIC;
ADDRA : in STD_LOGIC_VECTOR (9 downto 0);
ADDRB : in STD_LOGIC_VECTOR (9 downto 0);
DOA : out STD_LOGIC_VECTOR (15 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0);
DOPA : out STD_LOGIC_VECTOR (1 downto 0);
DOPB : out STD_LOGIC_VECTOR (1 downto 0)
);
end component;
--constant zeros: STD_LOGIC_VECTOR (width-iwidth-1 downto 0):=(others=>'0');
signal EN,A10 : STD_LOGIC;
signal DIREi,DIIMi: STD_LOGIC_VECTOR (width-1 downto 0);
signal ADDRA8,ADDRB8: STD_LOGIC_VECTOR (7 downto 0);
signal ADDRA9,ADDRB9: STD_LOGIC_VECTOR (8 downto 0);
signal ADDRA10,ADDRB10: STD_LOGIC_VECTOR (9 downto 0);
signal ADDRA11,ADDRB11: STD_LOGIC_VECTOR (10 downto 0);
signal ADDRA12,ADDRB12: STD_LOGIC_VECTOR (11 downto 0);
signal WE0,WE1,WEB,over:STD_LOGIC;
Signal DIAR,DIB,DOA,DOBR,DOBR0,DOBR1: STD_LOGIC_VECTOR (17 downto 0);
Signal DIAI,DOBI,DOBI0,DOBI1: STD_LOGIC_VECTOR (17 downto 0);
begin
--Writing at ADDRW address
-- Reading at ADDRR address
EN <= '1';
DIB<=(others=>'0');
RDI:process(CLK,RST)
begin
if RST='1' then
DIREi<=(others=>'0');
DIIMi<=(others=>'0');
elsif CLK='1' and CLK'event then
if CE='1' then
DIREi<=DIRE;
DIIMi<=DIIM;
end if;
end if;
end process;
-- DIREi<=DIRE;
-- DIIMi<=DIIM;
-- Virtex:if V2=0 generate
-- ZEROD: for i in width to 15 generate
-- DIAR(i)<='0';
-- DIAI(i)<='0';
-- end generate;
--
-- DIB<=(others=>'0');
-- WEB<='0';
--
-- RAMD256: if n=4 or n=5 or n=6 or n=7 or n=8 generate
-- EMPTYA4:if n=4 generate
-- ADDRA8(7 downto 4) <= "0000";
-- ADDRB8(7 downto 4) <= "0000";
-- end generate;
--
-- EMPTYA5:if n=5 generate
-- ADDRA8(7 downto 5) <= "000";
-- ADDRB8(7 downto 5) <= "000";
-- end generate;
--
-- EMPTYA6:if n=6 generate
-- ADDRA8(6) <= '0';
-- ADDRB8(6) <= '0';
-- ADDRA8(7) <= '0';
-- ADDRB8(7) <= '0';
-- end generate;
-- EMPTYA7:if n=7 generate
-- ADDRA8(7) <= '0';
-- ADDRB8(7) <= '0';
-- end generate;
--
-- ADDRA8(n-1 downto 0)<=ADDRW(n-1 downto 0);
-- ADDRB8(n-1 downto 0)<=ADDRR(n-1 downto 0);
--
--
-- RAM256_R: RAMB4_S16_S16
-- port map(CLKA => CLK,CLKB => CLK,RSTA => RST,RSTB => RST,
-- ENA => EN,ENB => EN,
-- WEA =>WE,WEB => WEB,
-- DOA => DOA, DOB => DOBR,
-- ADDRA => ADDRA8, ADDRB => ADDRB8,
-- DIA => DIAR, DIB => DIB);
--
-- RAM256_I: RAMB4_S16_S16
-- port map(CLKA => CLK,CLKB => CLK,RSTA => RST,RSTB => RST,
-- ENA => EN,ENB => EN,
-- WEA =>WE,WEB => WEB,
-- DOA => DOA, DOB => DOBI,
-- ADDRA => ADDRA8, ADDRB => ADDRB8,
-- DIA => DIAI, DIB => DIB);
-- end generate;
--
-- RAMD512: if n=9 generate
--
-- ADDRA9(n-1 downto 0)<=ADDRW(n-1 downto 0);
-- ADDRB9(n-1 downto 0)<=ADDRR(n-1 downto 0);
--
-- RAMD9:for i in 0 to 1 generate
--
-- RAM512_R: RAMB4_S8_S8
-- port map(CLKA => CLK,CLKB => CLK,RSTA => RST,RSTB => RST,
-- ENA => EN,ENB => EN,
-- WEA =>WE,WEB => WEB,
-- DOA => DOA(8*i+7 downto 8*i), DOB => DOBR(8*i+7 downto 8*i),
-- ADDRA => ADDRA9, ADDRB => ADDRB9,
-- DIA => DIAR(8*i+7 downto 8*i), DIB => DIB(8*i+7 downto 8*i));
--
-- RAM512_I: RAMB4_S8_S8
-- port map(CLKA => CLK,CLKB => CLK,RSTA => RST,RSTB => RST,
-- ENA => EN,ENB => EN,
-- WEA =>WE,WEB => WEB,
-- DOA => DOA(8*i+7 downto 8*i), DOB => DOBI(8*i+7 downto 8*i),
-- ADDRA => ADDRA9, ADDRB => ADDRB9,
-- DIA => DIAI(8*i+7 downto 8*i), DIB => DIB(8*i+7 downto 8*i));
--
-- end generate;
--
-- end generate;
--
-- RAMD1024: if n=10 generate
--
-- ADDRA10(n-1 downto 0)<=ADDRW(n-1 downto 0);
-- ADDRB10(n-1 downto 0)<=ADDRR(n-1 downto 0);
--
-- RAMD10:for i in 0 to 3 generate
--
-- RAM1024_R: RAMB4_S4_S4
-- port map(CLKA => CLK,CLKB => CLK,RSTA => RST,RSTB => RST,
-- ENA => EN,ENB => EN,
-- WEA =>WE,WEB => WEB,
-- DOA => DOA(4*i+3 downto 4*i), DOB => DOBR(4*i+3 downto 4*i),
-- ADDRA => ADDRA10, ADDRB => ADDRB10,
-- DIA => DIAR(4*i+3 downto 4*i), DIB => DIB(4*i+3 downto 4*i));
--
-- RAM1024_I: RAMB4_S4_S4
-- port map(CLKA => CLK,CLKB => CLK,RSTA => RST,RSTB => RST,
-- ENA => EN,ENB => EN,
-- WEA =>WE,WEB => WEB,
-- DOA => DOA(4*i+3 downto 4*i), DOB => DOBI(4*i+3 downto 4*i),
-- ADDRA => ADDRA10, ADDRB => ADDRB10,
-- DIA => DIAI(4*i+3 downto 4*i), DIB => DIB(4*i+3 downto 4*i));
--
-- end generate;
-- end generate;
--
-- RAMD2048: if n=11 generate
--
-- ADDRA11(n-1 downto 0)<=ADDRW(n-1 downto 0);
-- ADDRB11(n-1 downto 0)<=ADDRR(n-1 downto 0);
-- RAMD11:for i in 0 to 7 generate
--
-- RAM2048_R: RAMB4_S2_S2
-- port map(CLKA => CLK,CLKB => CLK,RSTA => RST,RSTB => RST,
-- ENA => EN,ENB => EN,
-- WEA =>WE,WEB => WEB,
-- DOA => DOA(2*i+1 downto 2*i), DOB => DOBR(2*i+1 downto 2*i),
-- ADDRA => ADDRA11, ADDRB => ADDRB11,
-- DIA => DIAR(2*i+1 downto 2*i), DIB => DIB(2*i+1 downto 2*i));
--
-- RAM2048_I: RAMB4_S2_S2
-- port map(CLKA => CLK,CLKB => CLK,RSTA => RST,RSTB => RST,
-- ENA => EN,ENB => EN,
-- WEA =>WE,WEB => WEB,
-- DOA => DOA(2*i+1 downto 2*i), DOB => DOBI(2*i+1 downto 2*i),
-- ADDRA => ADDRA11, ADDRB => ADDRB11,
-- DIA => DIAI(2*i+1 downto 2*i), DIB => DIB(2*i+1 downto 2*i));
--
-- end generate;
-- end generate;
-- end generate;
RAMD512v2: if n<=9 and v2=1 generate
DIB<=(others=>'0');
WEB<='0';
ADDRB10(n downto 0)<=ADDRR(n downto 0);
DIAR( width-1 downto 0)<= DMRE;
DIAI( width-1 downto 0)<=DMIM;
ADDRA10(n downto 0)<=ADDRW(n downto 0);
ADDRA10(9 downto n+1)<=(others=>'0');
ADDRB10(n downto 0)<=ADDRR(n downto 0);
ADDRB10(9 downto n+1)<=(others=>'0');
-- Working RAMs
RAM1024_R: RAMB16_S18_S18 --Re -part
port map (
CLKA => CLK, CLKB => CLK,SSRA => RST,SSRB => RESRAM,
WEA => WE, WEB => WEB,ENA => EN,ENB => EN,
DIPA => DIAR(17 downto 16),
DIPB => DIB(17 downto 16),
DIA => DIAR(15 downto 0),
DIB => DIB(15 downto 0),
ADDRA => ADDRA10,
ADDRB => ADDRB10,
DOPA => open,--DOA2(17 downto 16),
DOPB => DOBR(17 downto 16),
DOA => open,--DOA2(15 downto 0),
DOB => DOBR(15 downto 0));
RAM1024_I: RAMB16_S18_S18
port map (
CLKA => CLK, CLKB => CLK,SSRA => RST,SSRB => RESRAM,
WEA => WE, WEB => WEB,ENA => EN,ENB => EN,
DIPA => DIAI(17 downto 16),
DIPB => DIB(17 downto 16),
DIA => DIAI(15 downto 0),
DIB => DIB(15 downto 0),
ADDRA => ADDRA10, ADDRB => ADDRB10,
DOPA => open,--DOA2(17 downto 16),
DOPB => DOBI(17 downto 16),
DOA => open,--DOA2(15 downto 0),
DOB => DOBI(15 downto 0));
end generate;
RAMD1024v2: if n=10 and v2=1 generate
DIB<=(others=>'0');
WEB<='0';
ADDRB10<=ADDRR(n-1 downto 0);
ADDRA10<=ADDRW(n-1 downto 0);
DIAR( width-1 downto 0)<= DMRE;
DIAI( width-1 downto 0)<=DMIM;
WE0<=WE when ADDRW(n)='0' else '0';
WE1<=WE when ADDRW(n)='1' else '0';
-- Working RAMs
RAM1024_R0: RAMB16_S18_S18 --Re -part
port map (
CLKA => CLK, CLKB => CLK,SSRA => RST,SSRB => RESRAM,
WEA => WE0, WEB => WEB,ENA => EN,ENB => EN,
DIPA => DIAR(17 downto 16),
DIPB => DIB(17 downto 16),
DIA => DIAR(15 downto 0),
DIB => DIB(15 downto 0),
ADDRA => ADDRA10,
ADDRB => ADDRB10,
DOPA => open,--DOA2(17 downto 16),
DOPB => DOBR0(17 downto 16),
DOA => open,--DOA2(15 downto 0),
DOB => DOBR0(15 downto 0));
RAM1024_I0: RAMB16_S18_S18
port map (
CLKA => CLK, CLKB => CLK,SSRA => RST,SSRB => RESRAM,
WEA => WE0, WEB => WEB,ENA => EN,ENB => EN,
DIPA => DIAI(17 downto 16),
DIPB => DIB(17 downto 16),
DIA => DIAI(15 downto 0),
DIB => DIB(15 downto 0),
ADDRA => ADDRA10, ADDRB => ADDRB10,
DOPA => open,--DOA2(17 downto 16),
DOPB => DOBI0(17 downto 16),
DOA => open,--DOA2(15 downto 0),
DOB => DOBI0(15 downto 0));
RAM1024_R1: RAMB16_S18_S18 --Re -part
port map (
CLKA => CLK, CLKB => CLK,SSRA => RST,SSRB => RESRAM,
WEA => WE1, WEB => WEB,ENA => EN,ENB => EN,
DIPA => DIAR(17 downto 16),
DIPB => DIB(17 downto 16),
DIA => DIAR(15 downto 0),
DIB => DIB(15 downto 0),
ADDRA => ADDRA10,
ADDRB => ADDRB10,
DOPA => open,--DOA2(17 downto 16),
DOPB => DOBR1(17 downto 16),
DOA => open,--DOA2(15 downto 0),
DOB => DOBR1(15 downto 0));
RAM1024_I1: RAMB16_S18_S18
port map (
CLKA => CLK, CLKB => CLK,SSRA => RST,SSRB => RESRAM,
WEA => WE1, WEB => WEB,ENA => EN,ENB => EN,
DIPA => DIAI(17 downto 16),
DIPB => DIB(17 downto 16),
DIA => DIAI(15 downto 0),
DIB => DIB(15 downto 0),
ADDRA => ADDRA10, ADDRB => ADDRB10,
DOPA => open,--DOA2(17 downto 16),
DOPB => DOBI1(17 downto 16),
DOA => open,--DOA2(15 downto 0),
DOB => DOBI1(15 downto 0));
TA:process(CLK,RST)begin
if RST='1' then
A10<='0';
elsif rising_edge(CLK) then
A10<=ADDRR(n);
end if;
end process;
DOBR<=DOBR0 when A10='0' else DOBR1;
DOBI<=DOBI0 when A10='0' else DOBI1;
end generate;
TOVERFR:process(CLK,RST,DIAR,DIAI)
begin
over<= (DIAI( width-1) xor DIAI( width-2)) or (DIAI( width-1) xor DIAI( width-3))
or (DIAR( width-1) xor DIAR( width-2)) or (DIAR( width-1) xor DIAR( width-3));
if RST='1' then
OVERF<='0';
elsif CLK='1' and CLK'event then
if CE='1' then
if INITOVERF='1' then
OVERF<='0';
elsif over='1' and WE='1' then
OVERF<='1';
end if;
end if;
end if;
end process;
DORE<=DOBR(width-1 downto 0)when SEL='0' else DIREi;
DOIM<=DOBI(width-1 downto 0)when SEL='0' else DIIMi;
end RAM1X;
/fft_fir_filter/trunk/rtl/ram2x_2.vhd
0,0 → 1,233
---------------------------------------------------------------------
---- ----
---- FFT Filter IP core ----
---- ----
---- Authors: Anatoliy Sergienko, Volodya Lepeha ----
---- Company: Unicore Systems http://unicore.co.ua ----
---- ----
---- Downloaded from: http://www.opencores.org ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2006-2010 Unicore Systems LTD ----
---- www.unicore.co.ua ----
---- o.uzenkov@unicore.co.ua ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED "AS IS" ----
---- AND ANY EXPRESSED OR IMPLIED WARRANTIES, ----
---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ----
---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ----
---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ----
---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ----
---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ----
---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ----
---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ----
---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ----
---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ----
---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ----
---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ----
---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
 
entity RAM2X2 is
generic( iwidth : INTEGER:=16;
width : INTEGER:=16;
n:INTEGER:=8; -- 6,7,8,9,10,11
v2:INTEGER);
port (
CLK: in STD_LOGIC;
RST: in STD_LOGIC;
CE: in STD_LOGIC;
WEI: in STD_LOGIC; -- for input data
WEM: in STD_LOGIC; -- for intermediate data
INITOVERF:in STD_LOGIC;
ADDRWIN: in STD_LOGIC_VECTOR (n - 1 downto 0);
ADDRWM: in STD_LOGIC_VECTOR (n - 1 downto 0);
ADDRR: in STD_LOGIC_VECTOR (n - 1 downto 0);
EVEN: in STD_LOGIC; --0- 1th bank is read 1- 0tht bank -is read
DIRE: in STD_LOGIC_VECTOR (iwidth-1 downto 0);
DIIM: in STD_LOGIC_VECTOR (iwidth-1 downto 0);
DMRE: in STD_LOGIC_VECTOR (width-1 downto 0);
DMIM: in STD_LOGIC_VECTOR (width-1 downto 0);
OVERF:out STD_LOGIC;
DORE: out STD_LOGIC_VECTOR (width-1 downto 0);
DOIM: out STD_LOGIC_VECTOR (width-1 downto 0)
);
end RAM2X2 ;
 
 
architecture RAM2X_2 of RAM2X2 is
component RAMB16_S18_S18 is
port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
DIPA : in STD_LOGIC_VECTOR (1 downto 0);
DIPB : in STD_LOGIC_VECTOR (1 downto 0);
ENA : in STD_ULOGIC;
ENB : in STD_ULOGIC;
WEA : in STD_ULOGIC;
WEB : in STD_ULOGIC;
SSRA : in STD_ULOGIC;
SSRB : in STD_ULOGIC;
CLKA : in STD_ULOGIC;
CLKB : in STD_ULOGIC;
ADDRA : in STD_LOGIC_VECTOR (9 downto 0);
ADDRB : in STD_LOGIC_VECTOR (9 downto 0);
DOA : out STD_LOGIC_VECTOR (15 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0);
DOPA : out STD_LOGIC_VECTOR (1 downto 0);
DOPB : out STD_LOGIC_VECTOR (1 downto 0)
);
end component ;
signal EN : STD_LOGIC;
signal ADDRA100,ADDRA101,ADDRB10: STD_LOGIC_VECTOR (9 downto 0);
signal DIREi,DIIMi: STD_LOGIC_VECTOR (width-1 downto 0);
Signal DIAR,DIAMR,DIB,DOA,DOBR0,DOBR1: STD_LOGIC_VECTOR (17 downto 0);
Signal DIAI,DIAMI,DOBI0,DOBI1: STD_LOGIC_VECTOR (17 downto 0);
signal WEA0,WEA1,WEB, WEIi,OVER:STD_LOGIC;
constant nulls:STD_LOGIC_VECTOR (17 downto 0):=(others=>'0');
begin
--Writing at ADDRW address
-- Reading at ADDRR address
EN <= '1';
RDI:process(CLK,RST) --wchodnoj registr
begin
if RST='1' then
WEIi<='0';
DIREi<=(others=>'0');
DIIMi<=(others=>'0');
elsif CLK='1' and CLK'event then
if CE='1' then
WEIi<=WEI;
DIREi<=SXT(DIRE,width);--&nulls(width-iwidth-1 downto 0);
DIIMi<=SXT(DIIM,width);--&nulls(width-iwidth-1 downto 0);
end if;
end if;
end process;
DIAR( width-1 downto 0)<= DIREi;
DIAI( width-1 downto 0)<=DIIMi;
DIAMR( width-1 downto 0)<= DMRE;
DIAMI( width-1 downto 0)<=DMIM;
ZEROD: for i in width to 17 generate
DIAR(i)<='0';
DIAI(i)<='0';
DIAMR(i)<='0';
DIAMI(i)<='0';
end generate;
DIB<=(others=>'0');
WEB<='0';
ADDRA100(n-1 downto 0)<=ADDRWIN(n-1 downto 0);
ADDRA100(9 downto n)<=(others=>'0');
ADDRA101(n-1 downto 0)<=ADDRWM(n-1 downto 0);
ADDRA101(9 downto n)<=(others=>'0');
ADDRB10(n-1 downto 0)<=ADDRR(n-1 downto 0);
ADDRB10(9 downto n)<=(others=>'0');
RAMD1024v2: if n<=10 and v2=1 generate
ADDRB10(n-1 downto 0)<=ADDRR(n-1 downto 0);
-- input RAM
RAM1024I_R: RAMB16_S18_S18 --RE- part
port map (
CLKA => CLK, CLKB => CLK,SSRA => RST,SSRB => RST,
WEA => WEI, WEB => WEB,ENA => EN,ENB => EN,
DIPA => DIAR(17 downto 16),
DIPB => DIB(17 downto 16),
DIA => DIAR(15 downto 0),
DIB => DIB(15 downto 0),
ADDRA => ADDRA100, ADDRB => ADDRB10,
DOPA => open,--DOA2(17 downto 16),
DOPB => DOBR0(17 downto 16),
DOA => open,--DOA2(15 downto 0),
DOB => DOBR0(15 downto 0));
RAM1024I_I: RAMB16_S18_S18
port map (
CLKA => CLK, CLKB => CLK,SSRA => RST,SSRB => RST,
WEA => WEI, WEB => WEB,ENA => EN,ENB => EN,
DIPA => DIAI(17 downto 16),
DIPB => DIB(17 downto 16),
DIA => DIAI(15 downto 0),
DIB => DIB(15 downto 0),
ADDRA => ADDRA100, ADDRB => ADDRB10,
DOPA => open,--DOA2(17 downto 16),
DOPB => DOBI0(17 downto 16),
DOA => open,--DOA2(15 downto 0),
DOB => DOBI0(15 downto 0));
-- Working RAMs
RAM1024_R: RAMB16_S18_S18 --Re -part
port map (
CLKA => CLK, CLKB => CLK,SSRA => RST,SSRB => RST,
WEA => WEM, WEB => WEB,ENA => EN,ENB => EN,
DIPA => DIAMR(17 downto 16),
DIPB => DIB(17 downto 16),
DIA => DIAMR(15 downto 0),
DIB => DIB(15 downto 0),
ADDRA => ADDRA101, ADDRB => ADDRB10,
DOPA => open,--DOA2(17 downto 16),
DOPB => DOBR1(17 downto 16),
DOA => open,--DOA2(15 downto 0),
DOB => DOBR1(15 downto 0));
RAM1024_I: RAMB16_S18_S18
port map (
CLKA => CLK, CLKB => CLK,SSRA => RST,SSRB => RST,
WEA => WEM, WEB => WEB,ENA => EN,ENB => EN,
DIPA => DIAMI(17 downto 16),
DIPB => DIB(17 downto 16),
DIA => DIAMI(15 downto 0),
DIB => DIB(15 downto 0),
ADDRA => ADDRA101, ADDRB => ADDRB10,
DOPA => open,--DOA2(17 downto 16),
DOPB => DOBI1(17 downto 16),
DOA => open,--DOA2(15 downto 0),
DOB => DOBI1(15 downto 0));
end generate;
TOVERFR:process(CLK,RST,DMRE,DMIM)
begin
OVER<= (DIAMR( width-1) xor DIAMR( width-2)) or (DIAMR( width-1) xor DIAMR( width-3))
or (DIAMI( width-1) xor DIAMI( width-2)) or (DIAMI( width-1) xor DIAMI( width-3));
if RST='1' then
OVERF<='0';
elsif CLK='1' and CLK'event then
if CE='1' then
if INITOVERF='1' then
OVERF<='0';
elsif over='1' and WEM='1' then
OVERF<='1';
end if;
end if;
end if;
end process;
DORE<=DOBR0(width-1 downto 0) when EVEN='0' else DOBR1(width-1 downto 0);
DOIM<=DOBI0(width-1 downto 0) when EVEN='0' else DOBI1(width-1 downto 0);
end RAM2X_2;
/fft_fir_filter/trunk/rtl/rom_cosi.vhd
0,0 → 1,400
---------------------------------------------------------------------
---- ----
---- FFT Filter IP core ----
---- ----
---- Authors: Anatoliy Sergienko, Volodya Lepeha ----
---- Company: Unicore Systems http://unicore.co.ua ----
---- ----
---- Downloaded from: http://www.opencores.org ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2006-2010 Unicore Systems LTD ----
---- www.unicore.co.ua ----
---- o.uzenkov@unicore.co.ua ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED "AS IS" ----
---- AND ANY EXPRESSED OR IMPLIED WARRANTIES, ----
---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ----
---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ----
---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ----
---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ----
---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ----
---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ----
---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ----
---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ----
---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ----
---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ----
---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ----
---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
 
entity ROM_COSI is
generic(n: integer; --- FFT factor= 6,7,8,9,10,11
wwdth: integer:=15;-- output word width =8...15 , cos>0
wnd:integer);
port ( SELW:in STD_LOGIC_vector(1 downto 0);
ADDRROM :in std_logic_vector(n-2 downto 0);
COS : out std_logic_vector(wwdth-1 downto 0)
);
end ROM_COSI ;
-----------
architecture DISTR of ROM_COSI is
type ARR17 is array (0 to 31) of STD_LOGIC_VECTOR(15 downto 0);
constant black:arr17:=(
X"0000",X"0685",X"1268",X"2665",X"3fff",X"5999",X"6d96",X"797a",
X"7fff",X"797a",X"6d96",X"5999",X"3fff",X"2665",X"1268",X"0685",
X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",
X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",X"0000");
--signal hanns:STD_LOGIC_VECTOR(wwdth-1 downto 0);
signal addrful:STD_LOGIC_VECTOR(8 downto 0);
signal wind:std_logic_vector(wwdth-1 downto 0);
constant nulls: STD_LOGIC_VECTOR(wwdth-1 downto 0):=(others=>'0');
signal ADDR :std_logic_vector(n-3 downto 0);
type ROM16_16 is array(0 to 15 ) of std_logic_vector(15 downto 0);
type ROM128_8 is array(0 to 127 ) of std_logic_vector(7 downto 0);
constant ROM0000:ROM16_16:= (
X"7FFF",X"7F61",X"7D89",X"7A7C",X"7641",X"70E2",X"6A6D",X"62F1",
X"5A82",X"5133",X"471C",X"3C56", X"30FB",X"2528",X"18F9",X"0C8C");
constant ROM1000:ROM16_16:= (
X"7FD8",X"7E9C",X"7C29",X"7884",X"73B5",X"6DC9",X"66CF",X"5ED7",
X"55F5",X"4C3F",X"41CE",X"36BA",X"2B1F",X"1F1A",X"12C8",X"0648");
constant ROM0100:ROM16_16:= (
X"7FF5",X"7F09",X"7CE3",X"7989",X"7504",X"6F5E",X"68A6",X"60EB",
X"5842",X"4EBF",X"447A",X"398C",X"2E11",X"2223",X"15E2",X"096A");
constant ROM1100:ROM16_16:= (
X"7FA6",X"7E1D",X"7B5C",X"776B",X"7254",X"6C23",X"64E8",X"5CB3",
X"539B",X"49B4",X"3F17",X"33DF",X"2826",X"1C0B",X"0FAB",X"0324");
constant ROM0010:ROM16_16:= (
X"7FFD",X"7F37",X"7D39",X"7A05",X"75A5",X"7022",X"698B",X"61F0",
X"5964",X"4FFB",X"45CD",X"3AF2",X"2F87",X"23A6",X"176E",X"0AFB");
constant ROM1010:ROM16_16:= (
X"7FC1",X"7E5F",X"7BC5",X"77FA",X"7307",X"6CF8",X"65DD",X"5DC7",
X"54C9",X"4AFB",X"4073",X"354D",X"29A3",X"1D93",X"113A",X"04B6");
constant ROM0110:ROM16_16:= (
X"7FE9",X"7ED5",X"7C88",X"7909",X"745F",X"6E96",X"67BC",X"5FE3",
X"571D",X"4D81",X"4325",X"3824",X"2C99",X"209F",X"1455",X"07D9");
constant ROM1110:ROM16_16:= (
X"7F86",X"7DD5",X"7AEE",X"76D8",X"719D",X"6B4A",X"63EE",X"5B9C",
X"5268",X"4869",X"3DB8",X"326E",X"26A8",X"1A82",X"0E1C",X"0192");
constant ROM0001:ROM16_16:= (
X"7FFE",X"7F4D",X"7D62",X"7A41",X"75F3",X"7083",X"69FD",X"6271",
X"59F3",X"5097",X"4675",X"3BA5",X"3041",X"2467",X"1833",X"0BC4");
constant ROM0011:ROM16_16:= (
X"7FF9",X"7F21",X"7D0E",X"79C8",X"7555",X"6FC1",X"6919",X"616E",
X"58D3",X"4F5D",X"4524",X"3A40",X"2ECC",X"22E5",X"16A8",X"0A33");
constant ROM0101:ROM16_16:= (
X"7FF0",X"7EEF",X"7CB6",X"794A",X"74B2",X"6EFB",X"6832",X"6068",
X"57B0",X"4E20",X"43D0",X"38D9",X"2D55",X"2161",X"151C",X"08A2");
constant ROM0111:ROM16_16:= (
X"7FE1",X"7EB9",X"7C59",X"78C7",X"740A",X"6E30",X"6746",X"5F5D",
X"568A",X"4CE0",X"427A",X"376F",X"2BDC",X"1FDD",X"138F",X"0711");
constant ROM1001:ROM16_16:= (
X"7FCD",X"7E7E",X"7BF8",X"783F",X"735E",X"6D61",X"6656",X"5E4F",
X"5560",X"4B9D",X"4121",X"3604",X"2A61",X"1E57",X"1201",X"057F");
constant ROM1011:ROM16_16:= (
X"7FB4",X"7E3E",X"7B91",X"77B3",X"72AE",X"6C8E",X"6563",X"5D3E",
X"5432",X"4A58",X"3FC5",X"3496",X"28E5",X"1CCF",X"1072",X"03ED");
constant ROM1101:ROM16_16:= (
X"7F97",X"7DFA",X"7B26",X"7722",X"71F9",X"6BB7",X"646C",X"5C28",
X"5302",X"490F",X"3E68",X"3326",X"2767",X"1B47",X"0EE3",X"025B");
constant ROM1111:ROM16_16:= (
X"7F74",X"7DB0",X"7AB6",X"768D",X"7140",X"6ADC",X"6370",X"5B0F",
X"51CE",X"47C3",X"3D07",X"31B5",X"25E8",X"19BE",X"0D54",X"00C9");
constant ROMINCR:ROM128_8:= (
X"00",X"01",X"02",X"04",X"05",X"06",X"07",X"09",
X"0a",X"0b",X"0d",X"0e",X"0f",X"10",X"11",X"12",
X"13",X"15",X"16",X"17",X"19",X"1a",X"1b",X"1c",
X"1d",X"1e",X"1f",X"21",X"22",X"23",X"24",X"25",
X"27",X"28",X"29",X"2a",X"2b",X"2c",X"2d",X"2e",
X"2f",X"30",X"32",X"33",X"34",X"35",X"36",X"37",
X"38",X"39",X"3a",X"3b",X"3c",X"3d",X"3e",X"3f",
X"40",X"41",X"42",X"43",X"44",X"45",X"45",X"46",
X"47",X"48",X"49",X"4a",X"4b",X"4c",X"4d",X"4d",
X"4e",X"4f",X"4f",X"50",X"51",X"52",X"53",X"53",
X"54",X"55",X"55",X"56",X"56",X"57",X"58",X"58",
X"58",X"59",X"59",X"5a",X"5b",X"5b",X"5c",X"5d",
X"5d",X"5d",X"5e",X"5f",X"5f",X"5f",X"5f",X"60",
X"60",X"60",X"61",X"61",X"62",X"62",X"62",X"62",
X"63",X"63",X"63",X"63",X"64",X"64",X"64",X"64",
X"64",X"64",X"64",X"64",X"64",X"64",X"64",X"64");
signal MUX:std_logic_vector(wwdth-1 downto 0);
signal MUXi:std_logic_vector(15 downto 0);
signal AD: std_logic_vector(1 downto 0);
begin
ADDR<=ADDRROM(n-3 downto 0);
N16: if n=4 generate
AD<=ADDR;
with AD select
MUXi<=X"7FFF" when "00",
X"7641" when "01" ,
X"5A82" when "10" ,
X"30FB" when others;
MUX<=MUXi(14 downto 15- wwdth);
end generate;
N32: if n=5 generate
process (ADDR) is
variable B:std_logic_vector(15 downto 0);
begin
B:=ROM0000(conv_integer(ADDR&'0'));
MUX<=B(14 downto 15- wwdth);
end process;
end generate;
N64: if n=6 generate
process (ADDR) is
variable B:std_logic_vector(15 downto 0);
begin
B:=ROM0000(conv_integer(ADDR));
MUX<=B(14 downto 15- wwdth);
end process;
end generate;
N128: if n=7 generate
process (ADDR) is
variable B0,B1:std_logic_vector(15 downto 0);
begin
B0:=ROM0000(conv_integer(ADDR(4 downto 1)));
B1:=ROM1000(conv_integer(ADDR(4 downto 1)));
case ADDR(0) is
when '0' => MUX<=B0(14 downto 15- wwdth);
when '1' => MUX<=B1(14 downto 15- wwdth);
when others => null ;
end case;
end process;
end generate;
N256: if n=8 generate
process (ADDR) is
variable B00:std_logic_vector(15 downto 0);
variable B01:std_logic_vector(15 downto 0);
variable B10:std_logic_vector(15 downto 0);
variable B11:std_logic_vector(15 downto 0);
variable sel:std_logic_vector(1 downto 0);
begin
B00:=ROM0000(conv_integer(ADDR(5 downto 2)));
B01:=ROM0100(conv_integer(ADDR(5 downto 2)));
B10:=ROM1000(conv_integer(ADDR(5 downto 2)));
B11:=ROM1100(conv_integer(ADDR(5 downto 2)));
sel:=ADDR(1 downto 0) ;
case sel is
when "00" => MUX<=B00(14 downto 15- wwdth);
when "01" => MUX<=B01(14 downto 15- wwdth);
when "10" => MUX<=B10(14 downto 15- wwdth);
when "11" => MUX<=B11(14 downto 15- wwdth);
when others => null ;
end case;
end process;
end generate;
N512: if n=9 generate
process (ADDR) is
variable B000,B001:std_logic_vector(15 downto 0);
variable B010,B011:std_logic_vector(15 downto 0);
variable B100,B101:std_logic_vector(15 downto 0);
variable B110,B111:std_logic_vector(15 downto 0);
variable sel:std_logic_vector(2 downto 0);
begin
B000:=ROM0000(conv_integer(ADDR(6 downto 3)));
B001:=ROM0010(conv_integer(ADDR(6 downto 3)));
B010:=ROM0100(conv_integer(ADDR(6 downto 3)));
B011:=ROM0110(conv_integer(ADDR(6 downto 3)));
B100:=ROM1000(conv_integer(ADDR(6 downto 3)));
B101:=ROM1010(conv_integer(ADDR(6 downto 3)));
B110:=ROM1100(conv_integer(ADDR(6 downto 3)));
B111:=ROM1110(conv_integer(ADDR(6 downto 3)));
sel:=ADDR(2 downto 0) ;
case sel is
when "000" =>MUX<=B000(14 downto 15- wwdth);
when "001" =>MUX<=B001(14 downto 15- wwdth);
when "010" =>MUX<=B010(14 downto 15- wwdth);
when "011" =>MUX<=B011(14 downto 15- wwdth);
when "100" =>MUX<=B100(14 downto 15- wwdth);
when "101" =>MUX<=B101(14 downto 15- wwdth);
when "110" =>MUX<=B110(14 downto 15- wwdth);
when "111" =>MUX<=B111(14 downto 15- wwdth);
when others => null ;
end case;
end process;
end generate;
N1024: if n=10 generate
process (ADDR) is
variable B0000:std_logic_vector(15 downto 0);
variable B0001:std_logic_vector(15 downto 0);
variable B0010:std_logic_vector(15 downto 0);
variable B0011:std_logic_vector(15 downto 0);
variable B0100,B0101,B0110,B0111:std_logic_vector(15 downto 0);
variable B1000,B1001,B1010,B1011:std_logic_vector(15 downto 0);
variable B1100,B1101,B1110,B1111:std_logic_vector(15 downto 0);
variable sel:std_logic_vector(3 downto 0);
begin
B0000:=ROM0000(conv_integer(ADDR(7 downto 4)));
B0001:=ROM0001(conv_integer(ADDR(7 downto 4)));
B0010:=ROM0010(conv_integer(ADDR(7 downto 4)));
B0011:=ROM0011(conv_integer(ADDR(7 downto 4)));
B0100:=ROM0100(conv_integer(ADDR(7 downto 4)));
B0101:=ROM0101(conv_integer(ADDR(7 downto 4)));
B0110:=ROM0110(conv_integer(ADDR(7 downto 4)));
B0111:=ROM0111(conv_integer(ADDR(7 downto 4)));
B1000:=ROM1000(conv_integer(ADDR(7 downto 4)));
B1001:=ROM1001(conv_integer(ADDR(7 downto 4)));
B1010:=ROM1010(conv_integer(ADDR(7 downto 4)));
B1011:=ROM1011(conv_integer(ADDR(7 downto 4)));
B1100:=ROM1100(conv_integer(ADDR(7 downto 4)));
B1101:=ROM1101(conv_integer(ADDR(7 downto 4)));
B1110:=ROM1110(conv_integer(ADDR(7 downto 4)));
B1111:=ROM1111(conv_integer(ADDR(7 downto 4)));
sel:=ADDR(3 downto 0) ;
case sel is
when "0000" =>MUX<=B0000(14 downto 15- wwdth);
when "0001" =>MUX<=B0001(14 downto 15- wwdth);
when "0010" =>MUX<=B0010(14 downto 15- wwdth);
when "0011" =>MUX<=B0011(14 downto 15- wwdth);
when "0100" =>MUX<=B0100(14 downto 15- wwdth);
when "0101" =>MUX<=B0101(14 downto 15- wwdth);
when "0110" =>MUX<=B0110(14 downto 15- wwdth);
when "0111" =>MUX<=B0111(14 downto 15- wwdth);
when "1000" =>MUX<=B1000(14 downto 15- wwdth);
when "1001" =>MUX<=B1001(14 downto 15- wwdth);
when "1010" =>MUX<=B1010(14 downto 15- wwdth);
when "1011" =>MUX<=B1011(14 downto 15- wwdth);
when "1100" =>MUX<=B1100(14 downto 15- wwdth);
when "1101" =>MUX<=B1101(14 downto 15- wwdth);
when "1110" =>MUX<=B1110(14 downto 15- wwdth);
when "1111" =>MUX<=B1111(14 downto 15- wwdth);
when others => null ;
end case;
end process;
end generate;
N2048: if n=11 generate
process (ADDR) is
variable B0000:std_logic_vector(15 downto 0);
variable B0001:std_logic_vector(15 downto 0);
variable B0010:std_logic_vector(15 downto 0);
variable B0011:std_logic_vector(15 downto 0);
variable B0100,B0101,B0110,B0111:std_logic_vector(15 downto 0);
variable B1000,B1001,B1010,B1011:std_logic_vector(15 downto 0);
variable B1100,B1101,B1110,B1111:std_logic_vector(15 downto 0);
variable MUXI:std_logic_vector(wwdth-1 downto 0);
variable INCI:std_logic_vector(wwdth-8 downto 0);
variable INC:std_logic_vector(7 downto 0);
variable sel:std_logic_vector(3 downto 0);
begin
INC:=ROMINCR(conv_integer(ADDR(8 downto 2)));
INCI:=INC( 7 downto 15- wwdth);
B0000:=ROM0000(conv_integer(ADDR(8 downto 5)));
B0001:=ROM0001(conv_integer(ADDR(8 downto 5)));
B0010:=ROM0010(conv_integer(ADDR(8 downto 5)));
B0011:=ROM0011(conv_integer(ADDR(8 downto 5)));
B0100:=ROM0100(conv_integer(ADDR(8 downto 5)));
B0101:=ROM0101(conv_integer(ADDR(8 downto 5)));
B0110:=ROM0110(conv_integer(ADDR(8 downto 5)));
B0111:=ROM0111(conv_integer(ADDR(8 downto 5)));
B1000:=ROM1000(conv_integer(ADDR(8 downto 5)));
B1001:=ROM1001(conv_integer(ADDR(8 downto 5)));
B1010:=ROM1010(conv_integer(ADDR(8 downto 5)));
B1011:=ROM1011(conv_integer(ADDR(8 downto 5)));
B1100:=ROM1100(conv_integer(ADDR(8 downto 5)));
B1101:=ROM1101(conv_integer(ADDR(8 downto 5)));
B1110:=ROM1110(conv_integer(ADDR(8 downto 5)));
B1111:=ROM1111(conv_integer(ADDR(8 downto 5)));
sel:=ADDR(4 downto 1) ;
case sel is
when "0000" =>MUXI:=B0000(14 downto 15- wwdth);
when "0001" =>MUXI:=B0001(14 downto 15- wwdth);
when "0010" =>MUXI:=B0010(14 downto 15- wwdth);
when "0011" =>MUXI:=B0011(14 downto 15- wwdth);
when "0100" =>MUXI:=B0100(14 downto 15- wwdth);
when "0101" =>MUXI:=B0101(14 downto 15- wwdth);
when "0110" =>MUXI:=B0110(14 downto 15- wwdth);
when "0111" =>MUXI:=B0111(14 downto 15- wwdth);
when "1000" =>MUXI:=B1000(14 downto 15- wwdth);
when "1001" =>MUXI:=B1001(14 downto 15- wwdth);
when "1010" =>MUXI:=B1010(14 downto 15- wwdth);
when "1011" =>MUXI:=B1011(14 downto 15- wwdth);
when "1100" =>MUXI:=B1100(14 downto 15- wwdth);
when "1101" =>MUXI:=B1101(14 downto 15- wwdth);
when "1110" =>MUXI:=B1110(14 downto 15- wwdth);
when "1111" =>MUXI:=B1111(14 downto 15- wwdth);
when others => null ;
end case;
if ADDR(0)='1' then
MUX<=CONV_STD_LOGIC_VECTOR((unsigned(MUXI)-unsigned(INCi)),wwdth);
else
MUX<=MUXI;
end if;
end process;
end generate;
process(ADDRROM,addrful)
variable windi: STD_LOGIC_VECTOR(15 downto 0);
begin
--addrful<=ADDRROM(n-3 downto 0);
if wnd=1 then
windi:=black(conv_integer(addrrom(4 downto 0)));
wind<=windi(14 downto 15-wwdth);
else
--wind(wwdth-1)<='0' ;
wind(wwdth-1 downto 0)<=(others=>'1');
end if;
end process;
COS<=MUX when SELW="00"
else wind when SELW="01"
else addrrom & nulls(wwdth-n downto 0) when SELW="10"
else (others=>'1');
end DISTR;
 
/fft_fir_filter/trunk/rtl/alfft_core_sli.vhd
0,0 → 1,340
---------------------------------------------------------------------
---- ----
---- FFT Filter IP core ----
---- ----
---- Authors: Anatoliy Sergienko, Volodya Lepeha ----
---- Company: Unicore Systems http://unicore.co.ua ----
---- ----
---- Downloaded from: http://www.opencores.org ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2006-2010 Unicore Systems LTD ----
---- www.unicore.co.ua ----
---- o.uzenkov@unicore.co.ua ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED "AS IS" ----
---- AND ANY EXPRESSED OR IMPLIED WARRANTIES, ----
---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ----
---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ----
---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ----
---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ----
---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ----
---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ----
---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ----
---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ----
---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ----
---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ----
---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ----
---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-- DESCRIPTION:
--
-- FUNCTION Fast Fourier Transform of
-- N=16, 32, 64, 128, 256, 512, 1024, 2048 points,
-- N= 2**n,
-- ifft=0 forward FFT, =1 inverse FFT
-- rams=1 - single data RAM, =2 dual data RAM
-- input data width: iwidth = 8,...,16 bit signed
-- output data width: owidth = 8,...,16 bit signed
-- coefficient width : wwidth = 8,...,16 bit
-- Synthesable for Virtex, SpartanII FPGAs.
--
-- FILES: ALFFT_Core_sli.vhd -this file
-- FFTDPATHi.vhd - data path of the FFT butterfly
-- CONTROL_i.vhd - control unit
-- ROM_COSi.vhd - coefficient ROM
-- RAMX_2.vhd - data RAM block
-- When redesign data RAM blocks
-- the Core will fit another FPGA families
--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~--
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
 
entity ALFFT_Corei is
generic (width: INTEGER:=8 ; -- output data width =8...16
wwidth: INTEGER:=8; -- coefficient width =8...16
n:INTEGER:=7 ;
v2:INTEGER:=1 ; -- 1 - Virtex2
reall:INTEGER:= 0 --wch. mass: 0 -complex 1 - 2 realnych
); --4,5, 6,7,8,9,10,11 - transform length factor
port (
CLK: in STD_LOGIC;
RST: in STD_LOGIC;
CE: in STD_LOGIC;
START: in STD_LOGIC;
FILTER: in STD_LOGIC_VECTOR (1 downto 0); --0 -ne filtruet 1 - filtruet 2-+diff 3 +2diff
L1:in STD_LOGIC_VECTOR (n-1 downto 0); -- tsastoty filtrow
H1:in STD_LOGIC_VECTOR (n-1 downto 0); -- tsastoty filtrow
L2:in STD_LOGIC_VECTOR (n-1 downto 0);
H2:in STD_LOGIC_VECTOR (n-1 downto 0);
DATAE: in STD_LOGIC;
DATAIRE: in STD_LOGIC_VECTOR (width-1 downto 0);
DATAIIM: in STD_LOGIC_VECTOR (width-1 downto 0);
FFTRDY: out STD_LOGIC;
READY: out STD_LOGIC;
WERES: out STD_LOGIC;
ADDRRES: inout STD_LOGIC_VECTOR (n-1 downto 0);
DATAORE: out STD_LOGIC_VECTOR (width-1 downto 0);
DATAOIM: out STD_LOGIC_VECTOR (width-1 downto 0);
EXP: out STD_LOGIC_VECTOR (3 downto 0)
);
end ALFFT_Corei;
 
architecture ALFFT_CoreS of ALFFT_Corei is
component FFTDPATHI is
generic (width: integer :=8 ; -- word width =8...16
wwdth: integer:=7; -- coefficient width =7...15
reall:integer;
V2:integer
);
port (
CLK: in STD_LOGIC;
RST: in STD_LOGIC;
CE: in STD_LOGIC;
ODDC: in STD_LOGIC; --Odd cycle
DIV2: in STD_LOGIC; --Scaling factor
ZWR: in STD_LOGIC;
ZWI: in STD_LOGIC;
SIGNRE: in STD_LOGIC;
MODE: in STD_LOGIC_VECTOR (1 downto 0);
REDI: in STD_LOGIC_VECTOR (width downto 0);
IMDI: in STD_LOGIC_VECTOR (width downto 0);
WF: in STD_LOGIC_VECTOR (wwdth-1 downto 0);
REDO: out STD_LOGIC_VECTOR (width downto 0);
IMDO: out STD_LOGIC_VECTOR (width downto 0)
);
end component;
component ROM_COSi is
generic(n: integer; --- FFT factor= 6,7,8,9,10,11
wwdth: integer:=15;-- output word width =8...15 , cos>0
wnd: integer);
port ( SELW:in STD_LOGIC_vector(1 downto 0);
ADDRROM :in std_logic_vector(n-2 downto 0);
COS : out std_logic_vector(wwdth-1 downto 0)
);
end component ;
component CONTROLi is
generic (n:INTEGER; -- 6,7,8,9,10,11
reall:INTEGER:= 0 --wch. mass: 0 -complex 1 - 2 realnych
);
port (
CLK: in STD_LOGIC;
RST: in STD_LOGIC;
CE: in STD_LOGIC;
START: in STD_LOGIC;
DATAE: in STD_LOGIC;
OVERF: in STD_LOGIC;
FILTER: in STD_LOGIC_VECTOR (1 downto 0); --0 -ne filtruet 1 - filtruet 2-+diff 3 +2diff
L1:in STD_LOGIC_VECTOR (n-1 downto 0); -- tsastoty filtrow
H1:in STD_LOGIC_VECTOR (n-1 downto 0); -- tsastoty filtrow
L2:in STD_LOGIC_VECTOR (n-1 downto 0);
H2:in STD_LOGIC_VECTOR (n-1 downto 0);
FFTRDY: out STD_LOGIC;
READY: out STD_LOGIC;
WEI: out STD_LOGIC;
WEM: out STD_LOGIC;
WERES: out STD_LOGIC;
ODDC: out STD_LOGIC;
EVEN: out STD_LOGIC; --0- 0th bank 1- 1st bank -for DIRE,DIIM
DIV2: out STD_LOGIC;
ZWR: out STD_LOGIC;
ZWI: out STD_LOGIC;
RESRAM: out STD_LOGIC;
SIGNRE: out STD_LOGIC;
INITOVERF: out STD_LOGIC;
SEL: out STD_LOGIC; -- 0 -fromDIRE,DIIM, 1 - DMRE,DMIM
SELW: out STD_LOGIC_vector(1 downto 0); --0 -twiddle 1 - window
MODE: out STD_LOGIC_VECTOR (1 downto 0);
EXP: out STD_LOGIC_VECTOR (3 downto 0);
ADDRR: out STD_LOGIC_VECTOR (n downto 0);
ADDRWM: out STD_LOGIC_VECTOR (n downto 0) ;
ADDRRES: out STD_LOGIC_VECTOR (n - 1 downto 0);
ADDRROM :out STD_LOGIC_VECTOR(n- 2 downto 0)
);
end component ;
component RAM1X_2 is
generic(width : INTEGER;
n:INTEGER; -- 6,7,8,9,10,11
v2:INTEGER:=1);
port (
CLK: in STD_LOGIC;
RST: in STD_LOGIC;
CE: in STD_LOGIC;
WE: in STD_LOGIC;
INITOVERF: in STD_LOGIC;
ADDRW: in STD_LOGIC_VECTOR (n downto 0);
ADDRR: in STD_LOGIC_VECTOR (n downto 0);
SEL: in STD_LOGIC; -- 0 -fromDIRE,DIIM, 1 - DMRE,DMIM
RESRAM: in STD_LOGIC;
DIRE: in STD_LOGIC_VECTOR (width-1 downto 0);
DIIM: in STD_LOGIC_VECTOR (width-1 downto 0);
DMRE: in STD_LOGIC_VECTOR (width-1 downto 0);
DMIM: in STD_LOGIC_VECTOR (width-1 downto 0);
OVERF:out STD_LOGIC;
DORE: out STD_LOGIC_VECTOR (width-1 downto 0);
DOIM: out STD_LOGIC_VECTOR (width-1 downto 0)
);
end component;
--constant zeros: STD_LOGIC_VECTOR (owidth-iwidth-1 downto 0):=(others=>'0');
signal ODDC: STD_LOGIC; --Odd cycle
signal DIV2: STD_LOGIC; --Scaling factor
signal ZWR: STD_LOGIC;
signal ZWI: STD_LOGIC;
signal SIGNRE: STD_LOGIC;
signal REDI: STD_LOGIC_VECTOR (width-1 downto 0);
signal IMDI: STD_LOGIC_VECTOR (width-1 downto 0);
signal WF: STD_LOGIC_VECTOR (wwidth-2 downto 0);
signal REDO: STD_LOGIC_VECTOR (width-1 downto 0);
signal IMDO: STD_LOGIC_VECTOR (width-1 downto 0);
signal OVERF: STD_LOGIC;
signal INITOVERF: STD_LOGIC;
signal WEI: STD_LOGIC;
signal WEM: STD_LOGIC;
signal SEL: STD_LOGIC; -- 0 -fromDIRE,DIIM, 1 - DMRE,DMIM
signal SELW:STD_LOGIC_vector(1 downto 0);
signal EVEN: STD_LOGIC; --0- 0th bank 1- 1st bank -for DIRE,DIIM
signal ADDRW: STD_LOGIC_VECTOR (n - 1 downto 0);
signal ADDRR: STD_LOGIC_VECTOR (n downto 0);
signal ADDRWM: STD_LOGIC_VECTOR (n downto 0) ;
signal ADDRROM : STD_LOGIC_VECTOR(n- 2 downto 0);
signal MODE: STD_LOGIC_VECTOR (1 downto 0);
signal sn11,sn12:integer;
signal RESRAM: STD_LOGIC;
 
signal DIRE,DIIM: STD_LOGIC_VECTOR (width-1 downto 0);
begin
DIRE<=DATAIRE;-- & zeros;
DIIM<=DATAIIM;-- & zeros;
U_PATH: FFTDPATHI
generic map(width=>width-1, -- word width =7...15
wwdth=>wwidth-1, -- coefficient width =7...15
reall=>reall,
V2=>v2
)
port map(
CLK=> CLK,
RST=> RST,
CE=> CE,
MODE=>mode,
ODDC=>ODDC, --Odd cycle
DIV2=> DIV2, --Scaling factor
ZWR=> ZWR,
ZWI=> ZWI,
SIGNRE=>SIGNRE,
REDI=>REDI,
IMDI=> IMDI,
WF=> WF,
REDO=>REDO,
IMDO=>IMDO
);
U_ROM:ROM_COSi
generic map(n=>n, --- FFT factor= 6,7,8,9,10,11
wwdth=>wwidth-1, -- output word width =8...15 , cos>0
wnd=>1 --okno blackmana
)
port map (
SELW=>selw,
ADDRROM =>ADDRROM,
COS =>WF);
-- CNTR_SLIP2: if slip=2 generate
U_CNTRL: CONTROLi
generic map(n=>n , -- 6,7,8,9,10,11
reall=>reall
)
port map(
CLK=>CLK ,
RST=> RST,
CE=>CE ,
filter=>filter, --0 -ne filtruet 1 - filtruet 2-+diff 3 +2diff
L1=>L1, -- tsastoty filtrow
H1=>H1,
L2=>L2,
H2=>H2,
START=>START ,
DATAE=> DATAE,
OVERF=> OVERF,
FFTRDY=> FFTRDY,
READY=> READY,
-- WEI=> WEI,
WEM=> WEM,
RESRAM=>RESRAM,
INITOVERF=>INITOVERF,
WERES=>WERES,
SEL=>SEL , -- 0 -fromDIRE,DIIM, 1 - DMRE,DMIM
ODDC=>ODDC,
MODE=>mode,
EVEN=> EVEN, --0- 0th bank 1- 1st bank -for DIRE,DIIM
DIV2=> DIV2,
ZWR=> ZWR,
ZWI=> ZWI,
SELW=>selw,
SIGNRE=>SIGNRE ,
EXP=>EXP,
ADDRR=> ADDRR,
ADDRWM=> ADDRWM,
ADDRRES=>ADDRRES,
ADDRROM =>ADDRROM
);
U_RAM: RAM1X_2
generic map(
width =>width,
n=>n -- 6,7,8,9,10,11
,v2=>v2
)
port map(
CLK=>CLK ,
RST=> RST,
CE=> CE,
WE=> WEM, -- for input data
ADDRW=> ADDRWM,
ADDRR=> ADDRR,
SEL=>SEL,
DIRE=>DIRE,
RESRAM=>RESRAM,
DIIM=> DIIM,
DMRE=> REDO,
DMIM=> IMDO,
OVERF=> OVERF ,
INITOVERF=>INITOVERF,
DORE=>REDI,
DOIM=> IMDI
);
DATAORE<=REDO ;
DATAOIM<=IMDO ;
sn11<=conv_integer(signed(redo));--when addrres(n-1)='0' else 0;
sn12<=conv_integer(signed(imdo));
end ALFFT_CoreS;
/fft_fir_filter/trunk/rtl/alfft_core_slip.vhd
0,0 → 1,431
---------------------------------------------------------------------
---- ----
---- FFT Filter IP core ----
---- ----
---- Authors: Anatoliy Sergienko, Volodya Lepeha ----
---- Company: Unicore Systems http://unicore.co.ua ----
---- ----
---- Downloaded from: http://www.opencores.org ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2006-2010 Unicore Systems LTD ----
---- www.unicore.co.ua ----
---- o.uzenkov@unicore.co.ua ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED "AS IS" ----
---- AND ANY EXPRESSED OR IMPLIED WARRANTIES, ----
---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ----
---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ----
---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ----
---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ----
---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ----
---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ----
---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ----
---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ----
---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ----
---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ----
---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ----
---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-- DESCRIPTION:
--
-- FUNCTION Fast Fourier Transform of
-- N=16, 32, 64, 128, 256, 512, 1024, 2048 points,
-- N= 2**n,
-- ifft=0 forward FFT,
-- rams=1 - single data RAM, =2 dual data RAM
-- input data width: iwidth = 8,...,16 bit signed
-- output data width: owidth = 8,...,16 bit signed
-- coefficient width : wwidth = 8,...,16 bit
-- Synthesable for Virtex, SpartanII FPGAs.
-- Slipping transform with windowing
-- FILES: ALFFT_Core_slip.vhd -this file
-- FFTDPATH.vhd - data path of the FFT butterfly
-- CONTROL.vhd - control unit
-- ROM_COS.vhd - coefficient ROM
-- RAM2X_2.vhd - dual data RAM block
-- When redesign data RAM blocks
-- the Core will fit another FPGA families
--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~--
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
 
entity ALFFT_Core is
generic ( ifft: INTEGER:=0; -- 0- forward FFT
rams:INTEGER:=2; -- 1,2
iwidth: INTEGER:=8 ; -- input data width =8...16
owidth: INTEGER:=8 ; -- output data width =8...16
wwidth: INTEGER:=8; -- coefficient width =8...16
n:INTEGER:=7 ;
v2:INTEGER:=1 ; -- 1 - Virtex2
slip:INTEGER:= 2; -- 2 -- skolzassij s perekrytiem 2
wnd:INTEGER:= 1 ; -- umnozaecca na okno 1 ,0 -bez umnozenija
reall:INTEGER:= 0 --wch. mass: 0 -complex 1 - 2 realnych
); --4,5, 6,7,8,9,10,11 - transform length factor
port (
CLK: in STD_LOGIC;
RST: in STD_LOGIC;
CE: in STD_LOGIC;
START: in STD_LOGIC;
DATAE: in STD_LOGIC;
DATAIRE: in STD_LOGIC_VECTOR (iwidth-1 downto 0);
DATAIIM: in STD_LOGIC_VECTOR (iwidth-1 downto 0);
FFTRDY: out STD_LOGIC;
READY: out STD_LOGIC;
WERES: out STD_LOGIC;
ADDRRES: out STD_LOGIC_VECTOR (n-1 downto 0);
DATAORE: out STD_LOGIC_VECTOR (owidth-1 downto 0);
DATAOIM: out STD_LOGIC_VECTOR (owidth-1 downto 0);
EXP: out STD_LOGIC_VECTOR (3 downto 0)
);
end ALFFT_Core;
 
architecture ALFFT_CoreS of ALFFT_Core is
component FFTDPATH is
generic ( ifft: integer:=0;
width: integer :=8 ; -- word width =8...16
wwdth: integer:=7; -- coefficient width =7...15
V2:integer
);
port (
CLK: in STD_LOGIC;
RST: in STD_LOGIC;
CE: in STD_LOGIC;
ODDC: in STD_LOGIC; --Odd cycle
DIV2: in STD_LOGIC; --Scaling factor
ZWR: in STD_LOGIC;
ZWI: in STD_LOGIC;
SIGNRE: in STD_LOGIC;
MODE: in STD_LOGIC_VECTOR (1 downto 0);
REDI: in STD_LOGIC_VECTOR (width downto 0);
IMDI: in STD_LOGIC_VECTOR (width downto 0);
WF: in STD_LOGIC_VECTOR (wwdth-1 downto 0);
REDO: out STD_LOGIC_VECTOR (width downto 0);
IMDO: out STD_LOGIC_VECTOR (width downto 0)
);
end component;
component ROM_COS is
generic(n: integer; --- FFT factor= 6,7,8,9,10,11
wwdth: integer:=15;-- output word width =8...15 , cos>0
wnd: integer);
port ( SELW:in STD_LOGIC;
ADDRROM :in std_logic_vector(n-2 downto 0);
COS : out std_logic_vector(wwdth-1 downto 0)
);
end component ;
component RAM2X is
generic( iwidth : INTEGER;
width : INTEGER;
n:INTEGER); -- 6,7,8,9,10,11
port (
CLK: in STD_LOGIC;
RST: in STD_LOGIC;
CE: in STD_LOGIC;
WEI: in STD_LOGIC; -- for input data
WEM: in STD_LOGIC; -- for intermediate data
INITOVERF: in STD_LOGIC;
ADDRWIN: in STD_LOGIC_VECTOR (n - 1 downto 0);
ADDRWM: in STD_LOGIC_VECTOR (n - 1 downto 0);
ADDRR: in STD_LOGIC_VECTOR (n - 1 downto 0);
EVEN: in STD_LOGIC; --0- 0th bank 1- 1st bank -for DIRE,DIIM
DIRE: in STD_LOGIC_VECTOR (iwidth-1 downto 0);
DIIM: in STD_LOGIC_VECTOR (iwidth-1 downto 0);
DMRE: in STD_LOGIC_VECTOR (width-1 downto 0);
DMIM: in STD_LOGIC_VECTOR (width-1 downto 0);
OVERF:out STD_LOGIC;
DORE: out STD_LOGIC_VECTOR (width-1 downto 0);
DOIM: out STD_LOGIC_VECTOR (width-1 downto 0)
);
end component ;
component RAM2X2 is
generic( iwidth : INTEGER:=16;
width : INTEGER:=16;
n:INTEGER:=8; -- 6,7,8,9,10,11
v2:INTEGER);
port (
CLK: in STD_LOGIC;
RST: in STD_LOGIC;
CE: in STD_LOGIC;
WEI: in STD_LOGIC; -- for input data
WEM: in STD_LOGIC; -- for intermediate data
INITOVERF: in STD_LOGIC;
ADDRWIN: in STD_LOGIC_VECTOR (n - 1 downto 0);
ADDRWM: in STD_LOGIC_VECTOR (n - 1 downto 0);
ADDRR: in STD_LOGIC_VECTOR (n - 1 downto 0);
EVEN: in STD_LOGIC; --0- 1th bank is read 1- 0tht bank -is read
DIRE: in STD_LOGIC_VECTOR (iwidth-1 downto 0);
DIIM: in STD_LOGIC_VECTOR (iwidth-1 downto 0);
DMRE: in STD_LOGIC_VECTOR (width-1 downto 0);
DMIM: in STD_LOGIC_VECTOR (width-1 downto 0);
OVERF:out STD_LOGIC;
DORE: out STD_LOGIC_VECTOR (width-1 downto 0);
DOIM: out STD_LOGIC_VECTOR (width-1 downto 0)
);
end component;
component CONTROL is
generic ( ifft:INTEGER;--:=0;
rams:INTEGER;--:=1;
n:INTEGER; -- 6,7,8,9,10,11
slip:INTEGER;
reall:INTEGER:= 0 --wch. mass: 0 -complex 1 - 2 realnych
);
port (
CLK: in STD_LOGIC;
RST: in STD_LOGIC;
CE: in STD_LOGIC;
START: in STD_LOGIC;
DATAE: in STD_LOGIC;
OVERF: in STD_LOGIC;
FFTRDY: out STD_LOGIC;
READY: out STD_LOGIC;
WE: out STD_LOGIC;
WEI: out STD_LOGIC;
WEM: out STD_LOGIC;
WERES: out STD_LOGIC;
SEL: out STD_LOGIC; -- 0 -fromDIRE,DIIM, 1 - DMRE,DMIM
ODDC: out STD_LOGIC;
EVEN: out STD_LOGIC; --0- 0th bank 1- 1st bank -for DIRE,DIIM
DIV2: out STD_LOGIC;
ZWR: out STD_LOGIC;
ZWI: out STD_LOGIC;
SIGNRE: out STD_LOGIC;
INITOVERF: out STD_LOGIC;
SELW: out STD_LOGIC; --0 -twiddle 1 - window
MODE: out STD_LOGIC_VECTOR (1 downto 0);
EXP: out STD_LOGIC_VECTOR (3 downto 0);
ADDRW: out STD_LOGIC_VECTOR (n - 1 downto 0);
ADDRR: out STD_LOGIC_VECTOR (n - 1 downto 0);
ADDRWIN: out STD_LOGIC_VECTOR (n - 1 downto 0);
ADDRWM: out STD_LOGIC_VECTOR (n - 1 downto 0) ;
ADDRRES: out STD_LOGIC_VECTOR (n - 1 downto 0);
ADDRROM :out STD_LOGIC_VECTOR(n- 2 downto 0)
);
end component ;
--constant zeros: STD_LOGIC_VECTOR (owidth-iwidth-1 downto 0):=(others=>'0');
signal ODDC: STD_LOGIC; --Odd cycle
signal DIV2: STD_LOGIC; --Scaling factor
signal ZWR: STD_LOGIC;
signal ZWI: STD_LOGIC;
signal SIGNRE: STD_LOGIC;
signal REDI: STD_LOGIC_VECTOR (owidth-1 downto 0);
signal IMDI: STD_LOGIC_VECTOR (owidth-1 downto 0);
signal WF: STD_LOGIC_VECTOR (wwidth-2 downto 0);
signal REDO: STD_LOGIC_VECTOR (owidth-1 downto 0);
signal IMDO: STD_LOGIC_VECTOR (owidth-1 downto 0);
signal OVERF: STD_LOGIC;
signal INITOVERF: STD_LOGIC;
signal WE: STD_LOGIC;
signal WEI: STD_LOGIC;
signal WEM: STD_LOGIC;
signal SEL,SELW: STD_LOGIC; -- 0 -fromDIRE,DIIM, 1 - DMRE,DMIM
signal EVEN: STD_LOGIC; --0- 0th bank 1- 1st bank -for DIRE,DIIM
signal ADDRW: STD_LOGIC_VECTOR (n - 1 downto 0);
signal ADDRR: STD_LOGIC_VECTOR (n - 1 downto 0);
signal ADDRWIN: STD_LOGIC_VECTOR (n - 1 downto 0);
signal ADDRWM: STD_LOGIC_VECTOR (n - 1 downto 0) ;
signal ADDRROM : STD_LOGIC_VECTOR(n- 2 downto 0);
signal MODE: STD_LOGIC_VECTOR (1 downto 0);
signal DIRE,DIIM: STD_LOGIC_VECTOR (iwidth-1 downto 0);
signal sn01,sn02:integer;
begin
DIRE<=DATAIRE;-- & zeros;
DIIM<=DATAIIM;-- & zeros;
U_PATH: FFTDPATH
generic map( ifft=>ifft,
width=>owidth-1, -- word width =7...15
wwdth=>wwidth-1, -- coefficient width =7...15
V2=>v2
)
port map(
CLK=> CLK,
RST=> RST,
CE=> CE,
MODE=>mode,
ODDC=>ODDC, --Odd cycle
DIV2=> DIV2, --Scaling factor
ZWR=> ZWR,
ZWI=> ZWI,
SIGNRE=>SIGNRE,
REDI=>REDI,
IMDI=> IMDI,
WF=> WF,
REDO=>REDO,
IMDO=>IMDO
);
U_ROM:ROM_COS
generic map(n=>n, --- FFT factor= 6,7,8,9,10,11
wwdth=>wwidth-1, -- output word width =8...15 , cos>0
wnd=>wnd)
port map (
SELW=>selw,
ADDRROM =>ADDRROM,
COS =>WF);
-- CNTRL_SLIP0:if slip=0 generate
-- U_CNTRL:entity CONTROL(CONTROL)
-- generic map( ifft=>ifft,
-- rams=>rams,
-- n=>n , -- 6,7,8,9,10,11
-- slip=>slip
-- )
-- port map(
-- CLK=>CLK ,
-- RST=> RST,
-- CE=>CE ,
-- START=>START ,
-- DATAE=> DATAE,
-- OVERF=> OVERF,
-- FFTRDY=> FFTRDY,
-- READY=> READY,
-- WE=> WE,
-- WEI=> WEI,
-- WEM=> WEM,
-- INITOVERF=>INITOVERF,
-- WERES=>WERES,
-- SEL=>SEL , -- 0 -fromDIRE,DIIM, 1 - DMRE,DMIM
-- ODDC=>ODDC,
-- EVEN=> EVEN, --0- 0th bank 1- 1st bank -for DIRE,DIIM
-- DIV2=> DIV2,
-- ZWR=> ZWR,
-- ZWI=> ZWI,
-- SIGNRE=>SIGNRE ,
-- EXP=>EXP,
-- ADDRW=> ADDRW,
-- ADDRR=> ADDRR,
-- ADDRWIN=>ADDRWIN,
-- ADDRWM=> ADDRWM,
-- ADDRRES=>ADDRRES,
-- ADDRROM =>ADDRROM
-- );
-- end generate;
-- CNTR_SLIP2: if slip=2 generate
U_CNTRL:entity CONTROL(CONTROL_SLIP)
generic map( ifft=>ifft,
rams=>rams,
n=>n , -- 6,7,8,9,10,11
slip=>slip,
reall=>reall
)
port map(
CLK=>CLK ,
RST=> RST,
CE=>CE ,
START=>START ,
DATAE=> DATAE,
OVERF=> OVERF,
FFTRDY=> FFTRDY,
READY=> READY,
WE=> WE,
WEI=> WEI,
WEM=> WEM,
INITOVERF=>INITOVERF,
WERES=>WERES,
-- SEL=>SEL , -- 0 -fromDIRE,DIIM, 1 - DMRE,DMIM
ODDC=>ODDC,
MODE=>mode,
EVEN=> EVEN, --0- 0th bank 1- 1st bank -for DIRE,DIIM
DIV2=> DIV2,
ZWR=> ZWR,
ZWI=> ZWI,
SELW=>selw,
SIGNRE=>SIGNRE ,
EXP=>EXP,
ADDRR=> ADDRR,
ADDRWIN=>ADDRWIN,
ADDRWM=> ADDRWM,
ADDRRES=>ADDRRES,
ADDRROM =>ADDRROM
);
-- end generate;
-- RAM2: if rams=2 and slip=0 generate
-- U_RAM: RAM2X
-- generic map( iwidth=>iwidth,
-- width =>owidth,
-- n=>n -- 6,7,8,9,10,11
-- -- ,v2=>v2
-- )
-- port map(
-- CLK=>CLK ,
-- RST=> RST,
-- CE=> CE,
-- WEI=> WEI, -- for input data
-- WEM=> WEM, -- for intermediate data
-- ADDRWIN=> ADDRWIN,
-- ADDRWM=> ADDRWM,
-- ADDRR=> ADDRR,
-- EVEN=>EVEN , --0- 0th bank 1- 1st bank -for DIRE,DIIM
-- DIRE=>DIRE,
-- DIIM=> DIIM,
-- DMRE=> REDO,
-- DMIM=> IMDO,
-- OVERF=> OVERF ,
-- INITOVERF=>INITOVERF,
-- DORE=>REDI,
-- DOIM=> IMDI
-- );
--
-- end generate;
RAM2s: if rams=2 and slip=2 generate
U_RAM: RAM2X2
generic map( iwidth=>iwidth,
width =>owidth,
n=>n -- 6,7,8,9,10,11
,v2=>v2
)
port map(
CLK=>CLK ,
RST=> RST,
CE=> CE,
WEI=> WEI, -- for input data
WEM=> WEM, -- for intermediate data
ADDRWIN=> ADDRWIN,
ADDRWM=> ADDRWM,
ADDRR=> ADDRR,
EVEN=>EVEN , --0- 0th bank (Input) 1- 1st bank -for DIRE,DIIM
DIRE=>DIRE,
DIIM=> DIIM,
DMRE=> REDO,
DMIM=> IMDO,
OVERF=> OVERF ,
INITOVERF=>INITOVERF,
DORE=>REDI,
DOIM=> IMDI
);
end generate;
DATAORE<=REDO ;
DATAOIM<=IMDO ;
sn01<=conv_integer(signed(redo));
sn02<=conv_integer(signed(imdo));
end ALFFT_CoreS;
/fft_fir_filter/trunk/rtl/ramb16_s18_s18.vhd
0,0 → 1,122
---------------------------------------------------------------------
---- ----
---- FFT Filter IP core ----
---- ----
---- Authors: Anatoliy Sergienko, Volodya Lepeha ----
---- Company: Unicore Systems http://unicore.co.ua ----
---- ----
---- Downloaded from: http://www.opencores.org ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2006-2010 Unicore Systems LTD ----
---- www.unicore.co.ua ----
---- o.uzenkov@unicore.co.ua ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED "AS IS" ----
---- AND ANY EXPRESSED OR IMPLIED WARRANTIES, ----
---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ----
---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ----
---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ----
---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ----
---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ----
---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ----
---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ----
---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ----
---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ----
---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ----
---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ----
---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- File: RAMB4_S18_S18.vhd
-- created by Design Wizard: 12/13/99 08:52:59
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
 
entity RAMB16_S18_S18 is
port (DIA : in STD_LOGIC_VECTOR (15 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
DIPA : in STD_LOGIC_VECTOR (1 downto 0);
DIPB : in STD_LOGIC_VECTOR (1 downto 0);
ENA : in STD_ULOGIC;
ENB : in STD_ULOGIC;
WEA : in STD_ULOGIC;
WEB : in STD_ULOGIC;
SSRA : in STD_ULOGIC;
SSRB : in STD_ULOGIC;
CLKA : in STD_ULOGIC;
CLKB : in STD_ULOGIC;
ADDRA : in STD_LOGIC_VECTOR (9 downto 0);
ADDRB : in STD_LOGIC_VECTOR (9 downto 0);
DOA : out STD_LOGIC_VECTOR (15 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0);
DOPA : out STD_LOGIC_VECTOR (1 downto 0);
DOPB : out STD_LOGIC_VECTOR (1 downto 0)
);
end RAMB16_S18_S18;
 
architecture BEH of RAMB16_S18_S18 is
type mem is array (0 to 1023) of std_logic_vector (17 downto 0);
signal adra,adrb:std_logic_vector (9 downto 0):=(others=>'0');
signal data_a,data_b:std_logic_vector (17 downto 0);
signal wea_1,web_1: STD_LOGIC;
begin
process(clka,ssra,clkb,ssrb,adra,adrb,wea,web,dia,dib)
variable ram: mem:=(others=>"000000000000000000") ;
variable ia,ib: integer;
variable a,b:std_logic_vector (17 downto 0);
begin
ia:= conv_integer(To_X01(adra));
a:= ram(ia);
dopa<=a(17 downto 16);
doa <= a(15 downto 0);
if wea_1 = '1' then
ram(ia) :=data_a;
end if;
ib:= conv_integer(To_X01(adrb));
b:= ram(ib);
dopb<=b(17 downto 16);
dob <= b(15 downto 0);
if web_1 = '1' then
ram(ib) := data_b;
end if;
if ssra = '1' then
dopa<="00";
doa <= X"0000";
adra <= "0000000000";
wea_1 <= '0';
elsif clka = '1' and clka'event then
data_a <= dipa&dia;
adra(9 downto 0) <= addra;
wea_1 <= wea;
end if;
if ssrb = '1' then
dopb<="00";
dob <= X"0000";
adrb <= "0000000000";
web_1 <= '0';
elsif clkb = '1' and clkb'event then
data_b <= dipb&dib;
adrb(9 downto 0) <= addrb;
web_1 <= web;
end if;
end process;
end BEH;
/fft_fir_filter/trunk/rtl/ramb16_s36_s36.vhd
0,0 → 1,122
---------------------------------------------------------------------
---- ----
---- FFT Filter IP core ----
---- ----
---- Authors: Anatoliy Sergienko, Volodya Lepeha ----
---- Company: Unicore Systems http://unicore.co.ua ----
---- ----
---- Downloaded from: http://www.opencores.org ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2006-2010 Unicore Systems LTD ----
---- www.unicore.co.ua ----
---- o.uzenkov@unicore.co.ua ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED "AS IS" ----
---- AND ANY EXPRESSED OR IMPLIED WARRANTIES, ----
---- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ----
---- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ----
---- AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ----
---- IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ----
---- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ----
---- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ----
---- OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ----
---- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ----
---- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ----
---- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ----
---- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ----
---- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- File: RAMB4_S36_S36.vhd
-- created by Design Wizard: 08/13/05 08:52:59
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
 
entity RAMB16_S36_S36 is
port (DIA : in STD_LOGIC_VECTOR (31 downto 0);
DIB : in STD_LOGIC_VECTOR (31 downto 0);
DIPA : in STD_LOGIC_VECTOR (3 downto 0);
DIPB : in STD_LOGIC_VECTOR (3 downto 0);
ENA : in STD_ULOGIC;
ENB : in STD_ULOGIC;
WEA : in STD_ULOGIC;
WEB : in STD_ULOGIC;
SSRA : in STD_ULOGIC;
SSRB : in STD_ULOGIC;
CLKA : in STD_ULOGIC;
CLKB : in STD_ULOGIC;
ADDRA : in STD_LOGIC_VECTOR (8 downto 0);
ADDRB : in STD_LOGIC_VECTOR (8 downto 0);
DOA : out STD_LOGIC_VECTOR (31 downto 0);
DOB : out STD_LOGIC_VECTOR (31 downto 0);
DOPA : out STD_LOGIC_VECTOR (3 downto 0);
DOPB : out STD_LOGIC_VECTOR (3 downto 0)
);
end RAMB16_S36_S36;
 
architecture BEH of RAMB16_S36_S36 is
type mem is array (0 to 511) of std_logic_vector (35 downto 0);
signal adra,adrb:std_logic_vector (8 downto 0):=(others=>'0');
signal data_a,data_b:std_logic_vector (35 downto 0);
signal wea_1,web_1: STD_LOGIC;
begin
process(clka,ssra,clkb,ssrb,adra,adrb,wea,web,dia,dib)
variable ram: mem:=(others=>X"000000000") ;
variable ia,ib: integer;
variable a,b:std_logic_vector (35 downto 0);
begin
if ssra = '1' then
dopa<="0000";
doa <= X"00000000";
adra <= "000000000";
wea_1 <= '0';
elsif clka = '1' and clka'event then
data_a <= dipa&dia;
adra(8 downto 0) <= addra;
wea_1 <= wea;
end if;
if ssrb = '1' then
dopb<="0000";
dob <= X"00000000";
adrb <= "000000000";
web_1 <= '0';
elsif clkb = '1' and clkb'event then
data_b <= dipb&dib;
adrb(8 downto 0) <= addrb;
web_1 <= web;
end if;
ia:= conv_integer(To_X01(adra));
a:= ram(ia);
dopa<=a(35 downto 32);
doa <= a(31 downto 0);
if wea_1 = '1' then
ram(ia) :=data_a;
end if;
ib:= conv_integer(To_X01(adrb));
b:= ram(ib);
dopb<=b(35 downto 32);
dob <= b(31 downto 0);
if web_1 = '1' then
ram(ib) := data_b;
end if;
end process;
end BEH;
/fft_fir_filter/trunk/doc/fir_filter_um.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/fft_fir_filter/trunk/doc/fir_filter_um.pdf
fft_fir_filter/trunk/doc/fir_filter_um.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property

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