URL
https://opencores.org/ocsvn/hpc-16/hpc-16/trunk
Subversion Repositories hpc-16
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 1 to Rev 2
- ↔ Reverse comparison
Rev 1 → Rev 2
/trunk/impl0/sim_junk/hpc.cr.mti
0,0 → 1,180
D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/cpu_pkg.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/cpu_pkg.vhd |
Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003 |
-- Loading package standard |
-- Loading package std_logic_1164 |
-- Compiling package cpu_pkg |
|
} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/con_pkg.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/con_pkg.vhd |
Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003 |
-- Loading package standard |
-- Loading package std_logic_1164 |
-- Compiling package con_pkg |
|
} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/log.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/log.vhd |
Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003 |
-- Loading package standard |
-- Loading package std_logic_1164 |
-- Compiling entity log |
-- Compiling architecture dataflow of log |
|
} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/dp.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/dp.vhd |
Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003 |
-- Loading package standard |
-- Loading package std_logic_1164 |
-- Loading package std_logic_arith |
-- Loading package dp_pkg |
-- Compiling entity dp |
-- Compiling architecture rtl of dp |
-- Loading package std_logic_unsigned |
-- Loading entity regfile |
-- Loading entity alu |
-- Loading entity shifter |
-- Loading entity flags |
-- Loading entity fcmp |
|
} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/shifter.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/shifter.vhd |
Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003 |
-- Loading package standard |
-- Loading package std_logic_1164 |
-- Loading package std_logic_arith |
-- Loading package std_logic_unsigned |
-- Compiling entity shifter |
-- Compiling architecture dataflow of shifter |
|
} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/dp_pkg.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/dp_pkg.vhd |
Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003 |
-- Loading package standard |
-- Loading package std_logic_1164 |
-- Compiling package dp_pkg |
|
} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/sync.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/sync.vhd |
Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003 |
-- Loading package standard |
-- Loading package std_logic_1164 |
-- Compiling entity sync |
-- Compiling architecture behavioral of sync |
-- Compiling architecture behave2 of sync |
-- Loading entity sync |
|
} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/sim/testbench/ram8x16.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/sim/testbench/ram8x16.vhd |
Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003 |
-- Loading package standard |
-- Loading package std_logic_1164 |
-- Loading package std_logic_arith |
-- Loading package std_logic_unsigned |
-- Compiling entity ram8x16 |
-- Compiling architecture sim of ram8x16 |
|
} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/sim/testbench/test.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/sim/testbench/test.vhd |
Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003 |
-- Loading package standard |
-- Loading package std_logic_1164 |
-- Loading package std_logic_arith |
-- Loading package std_logic_unsigned |
-- Compiling entity test |
-- Compiling architecture sim of test |
-- Loading package textio |
-- Loading package std_logic_textio |
-- Loading entity ramnx16 |
-- Loading package cpu_pkg |
-- Loading entity cpu |
-- Loading entity ram8x16 |
|
} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/sim/testbench/arith.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/sim/testbench/arith.vhd |
Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003 |
-- Loading package standard |
-- Loading package std_logic_1164 |
-- Loading package numeric_std |
-- Loading package vital_timing |
-- Loading package vcomponents |
-- Compiling entity m2_1_mxilinx_arith |
-- Compiling architecture behavioral of m2_1_mxilinx_arith |
-- Loading entity and2b1 |
-- Loading entity or2 |
-- Loading entity and2 |
-- Compiling entity adsu16_mxilinx_arith |
-- Compiling architecture behavioral of adsu16_mxilinx_arith |
-- Loading entity fmap |
-- Loading entity xor3 |
-- Loading package vital_primitives |
-- Loading entity muxcy_l |
-- Loading entity muxcy |
-- Loading entity xorcy |
-- Loading entity muxcy_d |
-- Loading entity xor2 |
-- Loading entity inv |
-- Compiling entity arith |
-- Compiling architecture behavioral of arith |
-- Loading entity adsu16_mxilinx_arith |
-- Loading entity m2_1_mxilinx_arith |
-- Loading entity gnd |
|
} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/con1.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/con1.vhd |
Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003 |
-- Loading package standard |
-- Loading package std_logic_1164 |
-- Loading package con_pkg |
-- Compiling entity con1 |
-- Compiling architecture rtl of con1 |
-- Loading entity sync |
|
} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/alu.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/alu.vhd |
Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003 |
-- Loading package standard |
-- Loading package std_logic_1164 |
-- Compiling entity alu |
-- Compiling architecture struct of alu |
-- Loading package numeric_std |
-- Loading package vital_timing |
-- Loading package vcomponents |
-- Loading entity arith |
-- Loading entity log |
|
} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/flags.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/flags.vhd |
Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003 |
-- Loading package standard |
-- Loading package std_logic_1164 |
-- Compiling entity flags |
-- Compiling architecture behavioral of flags |
|
} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/sim/testbench/ramNx16.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/sim/testbench/ramNx16.vhd |
Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003 |
-- Loading package standard |
-- Loading package std_logic_1164 |
-- Loading package std_logic_arith |
-- Loading package std_logic_unsigned |
-- Loading package textio |
-- Loading package std_logic_textio |
-- Compiling entity ramnx16 |
-- Compiling architecture async of ramnx16 |
|
} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/fcmp.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/fcmp.vhd |
Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003 |
-- Loading package standard |
-- Loading package std_logic_1164 |
-- Compiling entity fcmp |
-- Compiling architecture behavioral of fcmp |
|
} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/regfile.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/regfile.vhd |
Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003 |
-- Loading package standard |
-- Loading package std_logic_1164 |
-- Loading package std_logic_arith |
-- Loading package std_logic_unsigned |
-- Compiling entity regfile |
-- Compiling architecture behavioral of regfile |
|
} {} {}} D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/cpu.vhd {1 {vcom -work work -93 -explicit D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/cpu.vhd |
Model Technology ModelSim XE II vcom 5.7g Compiler 2003.10 Oct 13 2003 |
-- Loading package standard |
-- Loading package std_logic_1164 |
-- Loading package cpu_pkg |
-- Compiling entity cpu |
-- Compiling architecture struct of cpu |
-- Loading package con_pkg |
-- Loading entity con1 |
-- Loading package std_logic_arith |
-- Loading package dp_pkg |
-- Loading entity dp |
|
} {} {}} |
/trunk/impl0/sim_junk/vsim.wlf
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
trunk/impl0/sim_junk/vsim.wlf
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/impl0/sim_junk/transcript
===================================================================
--- trunk/impl0/sim_junk/transcript (nonexistent)
+++ trunk/impl0/sim_junk/transcript (revision 2)
@@ -0,0 +1,201 @@
+# Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl
+# OpenFile "D:/MyOpenCoresProjects/hpc-16/impl0/sim_junk/hpc.mpf"
+# Loading project hpc
+# Compile of arith.vhd was successful.
+# Compile of log.vhd was successful.
+# Compile of alu.vhd was successful.
+# Compile of shifter.vhd was successful.
+# Compile of fcmp.vhd was successful.
+# Compile of flags.vhd was successful.
+# Compile of regfile.vhd was successful.
+# Compile of dp_pkg.vhd was successful.
+# Compile of dp.vhd was successful.
+# Compile of sync.vhd was successful.
+# Compile of con_pkg.vhd was successful.
+# Compile of con1.vhd was successful.
+# Compile of cpu_pkg.vhd was successful.
+# Compile of cpu.vhd was successful.
+# Compile of test.vhd was successful.
+# Compile of ram8x16.vhd was successful.
+# Compile of ramNx16.vhd was successful.
+# 17 compiles, 0 failed with no errors.
+vsim -t 10ps work.test
+# vsim -t 10ps work.test
+# Loading C:/Modeltech_xe_starter/win32xoem/../std.standard
+# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body)
+# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body)
+# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body)
+# Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body)
+# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body)
+# Loading work.cpu_pkg
+# Loading work.test(sim)
+# Loading work.ramnx16(async)
+# Loading work.con_pkg
+# Loading work.dp_pkg
+# Loading work.cpu(struct)
+# Loading work.con1(rtl)
+# Loading work.sync(behave2)
+# Loading work.dp(rtl)
+# Loading work.regfile(behavioral)
+# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.numeric_std(body)
+# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_timing(body)
+# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.vcomponents
+# Loading work.alu(struct)
+# Loading work.arith(behavioral)
+# Loading C:/Modeltech_xe_starter/win32xoem/../ieee.vital_primitives(body)
+# Loading work.adsu16_mxilinx_arith(behavioral)
+# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.fmap(fmap_v)
+# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.xor3(xor3_v)
+# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.muxcy_l(muxcy_l_v)
+# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.muxcy(muxcy_v)
+# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.xorcy(xorcy_v)
+# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.muxcy_d(muxcy_d_v)
+# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.xor2(xor2_v)
+# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.inv(inv_v)
+# Loading work.m2_1_mxilinx_arith(behavioral)
+# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.and2b1(and2b1_v)
+# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.or2(or2_v)
+# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.and2(and2_v)
+# Loading C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/unisim.gnd(gnd_v)
+# Loading work.log(dataflow)
+# Loading work.shifter(dataflow)
+# Loading work.flags(behavioral)
+# Loading work.fcmp(behavioral)
+# Loading work.ram8x16(sim)
+# WARNING: Design size of 1881 statements or 10 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
+# Expect performance to be quite adversely affected.
+view wave
+# .wave
+do D:/MyOpenCoresProjects/hpc-16/impl0/sim_junk/complete_wave_no_ramcs.do
+# ERROR: No objects found matching "/test/ram/line__57/ram_data_upper"
+# Executing ONERROR command at macro D:\MyOpenCoresProjects\hpc-16\impl0\sim_junk\complete_wave_no_ramcs.do line 39
+# ERROR: No objects found matching "/test/ram/line__57/ram_data_lower"
+# Executing ONERROR command at macro D:\MyOpenCoresProjects\hpc-16\impl0\sim_junk\complete_wave_no_ramcs.do line 40
+view variables
+# .variables
+view process
+# .process
+destroy .variables
+destroy .process
+do D:/MyOpenCoresProjects/hpc-16/impl0/sim_junk/complete_wave_no_ramcs.do
+run -all
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 ps Iteration: 0 Instance: /test/cpu/datapath/u1
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 ps Iteration: 0 Instance: /test/cpu/datapath/u1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 ps Iteration: 0 Instance: /test/cpu/datapath/u1
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 ps Iteration: 0 Instance: /test/cpu/datapath/u1
+# ** Error: (vsim-7) Failed to open VHDL file "add2_init_ram.txt" in rb mode.
+# No such file or directory. (errno = ENOENT)
+# Time: 0 ps Iteration: 0 Instance: /test/ram
+# ** Fatal: (vsim-7) Failed to open VHDL file "add2_init_ram.txt" in rb mode.
+# No such file or directory. (errno = ENOENT)
+# Time: 0 ps Iteration: 0 Process: /test/ram/init File: D:/MyOpenCoresProjects/hpc-16/impl0/sim/testbench/ramNx16.vhd
+# Fatal error at D:/MyOpenCoresProjects/hpc-16/impl0/sim/testbench/ramNx16.vhd line 101
+#
+run -all
+# Cannot continue because of fatal error.
+restart
+# WARNING: Design size of 1881 statements or 10 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
+# Expect performance to be quite adversely affected.
+run -all
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 ps Iteration: 0 Instance: /test/cpu/datapath/u1
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 ps Iteration: 0 Instance: /test/cpu/datapath/u1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 ps Iteration: 0 Instance: /test/cpu/datapath/u1
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 ps Iteration: 0 Instance: /test/cpu/datapath/u1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 ps Iteration: 1 Instance: /test/cpu/datapath
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 ps Iteration: 1 Instance: /test/cpu/datapath
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 40 ns Iteration: 1 Instance: /test/cpu/datapath
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 40 ns Iteration: 1 Instance: /test/cpu/datapath
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 80 ns Iteration: 1 Instance: /test/cpu/datapath
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 80 ns Iteration: 1 Instance: /test/cpu/datapath
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 120 ns Iteration: 1 Instance: /test/cpu/datapath
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 120 ns Iteration: 1 Instance: /test/cpu/datapath
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 160 ns Iteration: 1 Instance: /test/cpu/datapath
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 160 ns Iteration: 1 Instance: /test/cpu/datapath
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 200 ns Iteration: 1 Instance: /test/cpu/datapath
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 200 ns Iteration: 1 Instance: /test/cpu/datapath
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 240 ns Iteration: 1 Instance: /test/cpu/datapath
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 240 ns Iteration: 1 Instance: /test/cpu/datapath
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 280 ns Iteration: 1 Instance: /test/cpu/datapath
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 280 ns Iteration: 1 Instance: /test/cpu/datapath
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 320 ns Iteration: 1 Instance: /test/cpu/datapath
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 320 ns Iteration: 1 Instance: /test/cpu/datapath
+# ** Error: simulation completed (not an error)
+# Time: 3 us Iteration: 0 Instance: /test
+restart
+# WARNING: Design size of 1881 statements or 10 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.
+# Expect performance to be quite adversely affected.
+run -all
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 ps Iteration: 0 Instance: /test/cpu/datapath/u1
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 ps Iteration: 0 Instance: /test/cpu/datapath/u1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 ps Iteration: 0 Instance: /test/cpu/datapath/u1
+# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
+# Time: 0 ps Iteration: 0 Instance: /test/cpu/datapath/u1
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 ps Iteration: 1 Instance: /test/cpu/datapath
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 0 ps Iteration: 1 Instance: /test/cpu/datapath
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 40 ns Iteration: 1 Instance: /test/cpu/datapath
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 40 ns Iteration: 1 Instance: /test/cpu/datapath
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 80 ns Iteration: 1 Instance: /test/cpu/datapath
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 80 ns Iteration: 1 Instance: /test/cpu/datapath
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 120 ns Iteration: 1 Instance: /test/cpu/datapath
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 120 ns Iteration: 1 Instance: /test/cpu/datapath
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 160 ns Iteration: 1 Instance: /test/cpu/datapath
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 160 ns Iteration: 1 Instance: /test/cpu/datapath
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 200 ns Iteration: 1 Instance: /test/cpu/datapath
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 200 ns Iteration: 1 Instance: /test/cpu/datapath
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 240 ns Iteration: 1 Instance: /test/cpu/datapath
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 240 ns Iteration: 1 Instance: /test/cpu/datapath
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 280 ns Iteration: 1 Instance: /test/cpu/datapath
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 280 ns Iteration: 1 Instance: /test/cpu/datapath
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 320 ns Iteration: 1 Instance: /test/cpu/datapath
+# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
+# Time: 320 ns Iteration: 1 Instance: /test/cpu/datapath
+# ** Error: simulation completed (not an error)
+# Time: 3 us Iteration: 0 Instance: /test
+destroy .wave
+quit -sim
Index: trunk/impl0/sim_junk/add2_init_ram.txt
===================================================================
--- trunk/impl0/sim_junk/add2_init_ram.txt (nonexistent)
+++ trunk/impl0/sim_junk/add2_init_ram.txt (revision 2)
@@ -0,0 +1,11 @@
+0:0100100100000000
+1:1111111100000000
+2:0100100101100000
+3:1111111100000010
+4:0000100000100000
+5:0000100000110110
+6:0011000100100011
+7:0100100110000000
+8:1111111100000100
+9:0001000000101000
+10:1111100000000000
\ No newline at end of file
Index: trunk/impl0/sim_junk/hpc.mpf
===================================================================
--- trunk/impl0/sim_junk/hpc.mpf (nonexistent)
+++ trunk/impl0/sim_junk/hpc.mpf (revision 2)
@@ -0,0 +1,249 @@
+;
+; Copyright Model Technology, a Mentor Graphics
+; Corporation company 2003, - All rights reserved.
+;
+[Library]
+std = $MODEL_TECH/../std
+ieee = $MODEL_TECH/../ieee
+verilog = $MODEL_TECH/../verilog
+vital2000 = $MODEL_TECH/../vital2000
+std_developerskit = $MODEL_TECH/../std_developerskit
+synopsys = $MODEL_TECH/../synopsys
+modelsim_lib = $MODEL_TECH/../modelsim_lib
+
+
+; VHDL Section
+unisim = $MODEL_TECH/../xilinx/vhdl/unisim
+simprim = $MODEL_TECH/../xilinx/vhdl/simprim
+xilinxcorelib = $MODEL_TECH/../xilinx/vhdl/xilinxcorelib
+aim = $MODEL_TECH/../xilinx/vhdl/aim
+pls = $MODEL_TECH/../xilinx/vhdl/pls
+cpld = $MODEL_TECH/../xilinx/vhdl/cpld
+
+; Verilog Section
+unisims_ver = $MODEL_TECH/../xilinx/verilog/unisims_ver
+uni9000_ver = $MODEL_TECH/../xilinx/verilog/uni9000_ver
+simprims_ver = $MODEL_TECH/../xilinx/verilog/simprims_ver
+xilinxcorelib_ver = $MODEL_TECH/../xilinx/verilog/xilinxcorelib_ver
+aim_ver = $MODEL_TECH/../xilinx/verilog/aim_ver
+cpld_ver = $MODEL_TECH/../xilinx/verilog/cpld_ver
+
+work = work
+[vcom]
+; Turn on VHDL-1993 as the default. Normally is off.
+VHDL93 = 1
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+ Explicit = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = false
+
+; Turn off "loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+; -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+[vlog]
+
+; Turn off "loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Turns on incremental compilation of modules
+; Incremental = 1
+
+[vsim]
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+Resolution = ps
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+UserTimeUnit = default
+
+; Default run length
+RunLength = 100
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 5000
+
+; Directive to license manager:
+; vhdl Immediately reserve a VHDL license
+; vlog Immediately reserve a Verilog license
+; plus Immediately reserve a VHDL and Verilog license
+; nomgc Do not look for Mentor Graphics Licenses
+; nomti Do not look for Model Technology Licenses
+; noqueue Do not wait in the license queue when a license isn't available
+; License = plus
+
+; Stop the simulator after an assertion message
+; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+BreakOnAssertion = 3
+
+; Assertion Message Format
+; %S - Severity Level
+; %R - Report Message
+; %T - Time of assertion
+; %D - Delta
+; %I - Instance or Region pathname (if available)
+; %% - print '%' character
+; AssertionFormat = "** %S: %R\n Timf: %T Iteration: %D%I\n"
+
+; Assertion File - alternate file for storing assertion messages
+; AssertFile = assert.log
+
+; Default radix for all windows and commands...
+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
+DefaultRadix = symbolic
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+;CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format. For VHDL, PathSeparator = /
+; for Verilog, PathSeparator = .
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example, sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Disable assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Default force kind. May be freeze, drive, or deposit
+; or in other terms, fixed, wired or charged.
+; DefaultForceKind = freeze
+
+; If zero, open files when elaborated
+; else open files on first read or write
+; DelayFileOpen = 0
+
+; Control VHDL files opened for write
+; 0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control number of VHDL files open concurrently
+; This number should always be less then the
+; current ulimit setting for max file descriptors
+; 0 = unlimited
+ConcurrentFileLimit = 40
+
+; This controls the number of hierarchical regions displayed as
+; part of a signal name shown in the waveform window. The default
+; value or a value of zero tells VSIM to display the full name.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings from the std_logic_arith, std_logic_unsigned
+; and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from the IEEE numeric_std and numeric_bit
+; packages.
+; NumericStdNoWarnings = 1
+
+; Control the format of a generate statement label. Don't quote it.
+; GenerateFormat = %s__%d
+
+; Specify whether checkpoint files should be compressed.
+; The default is to be compressed.
+; CheckpointCompressMode = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+
+[lmc]
+[Project]
+Project_Version = 5
+Project_DefaultLib = work
+Project_SortMethod = unused
+Project_Files_Count = 17
+Project_File_0 = D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/con_pkg.vhd
+Project_File_P_0 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 1125777840 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn3 1 vhdl_warn4 1 vhdl_warn5 1 ood 0 compile_to work compile_order 10 dont_compile 0 vhdl_use93 1
+Project_File_1 = D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/cpu_pkg.vhd
+Project_File_P_1 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 1125744617 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn3 1 vhdl_warn4 1 vhdl_warn5 1 ood 0 compile_to work compile_order 12 dont_compile 0 vhdl_use93 1
+Project_File_2 = D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/log.vhd
+Project_File_P_2 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 1125744802 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn3 1 vhdl_warn4 1 vhdl_warn5 1 ood 0 compile_to work compile_order 1 dont_compile 0 vhdl_use93 1
+Project_File_3 = D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/dp.vhd
+Project_File_P_3 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 1125744639 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn3 1 vhdl_warn4 1 vhdl_warn5 1 ood 0 compile_to work compile_order 8 dont_compile 0 vhdl_use93 1
+Project_File_4 = D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/shifter.vhd
+Project_File_P_4 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 1125744830 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn3 1 vhdl_warn4 1 vhdl_warn5 1 ood 0 compile_to work compile_order 3 dont_compile 0 vhdl_use93 1
+Project_File_5 = D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/sync.vhd
+Project_File_P_5 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 1125864447 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn3 1 vhdl_warn4 1 vhdl_warn5 1 ood 0 compile_to work compile_order 9 dont_compile 0 vhdl_use93 1
+Project_File_6 = D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/dp_pkg.vhd
+Project_File_P_6 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 1125744735 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn3 1 vhdl_warn4 1 vhdl_warn5 1 ood 0 compile_to work compile_order 7 dont_compile 0 vhdl_use93 1
+Project_File_7 = D:/MyOpenCoresProjects/hpc-16/impl0/sim/testbench/ram8x16.vhd
+Project_File_P_7 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 1125827422 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn3 1 vhdl_warn4 1 vhdl_warn5 1 ood 0 compile_to work compile_order 15 dont_compile 0 vhdl_use93 1
+Project_File_8 = D:/MyOpenCoresProjects/hpc-16/impl0/sim/testbench/arith.vhd
+Project_File_P_8 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 1122463114 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn3 1 vhdl_warn4 1 vhdl_warn5 1 ood 0 compile_to work compile_order 0 dont_compile 0 vhdl_use93 1
+Project_File_9 = D:/MyOpenCoresProjects/hpc-16/impl0/sim/testbench/test.vhd
+Project_File_P_9 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 1125827504 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn3 1 vhdl_warn4 1 vhdl_warn5 1 ood 0 compile_to work compile_order 14 dont_compile 0 vhdl_use93 1
+Project_File_10 = D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/con1.vhd
+Project_File_P_10 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 1125865820 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn3 1 vhdl_warn4 1 vhdl_warn5 1 ood 0 compile_to work compile_order 11 dont_compile 0 vhdl_use93 1
+Project_File_11 = D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/alu.vhd
+Project_File_P_11 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 1125744419 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn3 1 vhdl_warn4 1 vhdl_warn5 1 ood 0 compile_to work compile_order 2 dont_compile 0 vhdl_use93 1
+Project_File_12 = D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/flags.vhd
+Project_File_P_12 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 1125744790 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn3 1 vhdl_warn4 1 vhdl_warn5 1 ood 0 compile_to work compile_order 5 dont_compile 0 vhdl_use93 1
+Project_File_13 = D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/regfile.vhd
+Project_File_P_13 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 1125744817 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn3 1 vhdl_warn4 1 vhdl_warn5 1 ood 0 compile_to work compile_order 6 dont_compile 0 vhdl_use93 1
+Project_File_14 = D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/fcmp.vhd
+Project_File_P_14 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 1125744774 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn3 1 vhdl_warn4 1 vhdl_warn5 1 ood 0 compile_to work compile_order 4 dont_compile 0 vhdl_use93 1
+Project_File_15 = D:/MyOpenCoresProjects/hpc-16/impl0/sim/testbench/ramNx16.vhd
+Project_File_P_15 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 1125827384 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn3 1 vhdl_warn4 1 vhdl_warn5 1 ood 0 compile_to work compile_order 16 dont_compile 0 vhdl_use93 1
+Project_File_16 = D:/MyOpenCoresProjects/hpc-16/impl0/rtl/vhdl/cpu.vhd
+Project_File_P_16 = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 1125744575 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn3 1 vhdl_warn4 1 vhdl_warn5 1 ood 0 compile_to work compile_order 13 dont_compile 0 vhdl_use93 1
+Project_Sim_Count = 1
+Project_Sim_0 = add2
+Project_Sim_P_0 = Generics {} timing default -std_output {} +notimingchecks 0 -L {} selected_du {} -hazards 0 -sdf {} +acc {} ok 1 folder {Top Level} +pulse_r {} -absentisempty 0 -multisource_delay {} OtherArgs {} +pulse_e {} -t 10ps -vital2.2b 0 +plusarg {} -sdfnoerror 0 -coverage 0 additional_dus work.test -noglitch 0 -nofileshare 0 +no_pulse_msg 0 -wlf {} -std_input {} -Lf {} -sdfnowarn 0 -assertfile {}
+Project_Folder_Count = 0
Index: trunk/impl0/sim_junk/complete_wave_no_ramcs.do
===================================================================
--- trunk/impl0/sim_junk/complete_wave_no_ramcs.do (nonexistent)
+++ trunk/impl0/sim_junk/complete_wave_no_ramcs.do (revision 2)
@@ -0,0 +1,58 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -divider {CPU interfacing}
+add wave -noupdate -format Logic -label CLK_I /test/clk_i
+add wave -noupdate -format Logic -label RST_I /test/rst_i
+add wave -noupdate -format Logic -label ACK_I /test/ack_i
+add wave -noupdate -format Logic -label INTR_I /test/intr_i
+add wave -noupdate -format Literal -label SEL_O /test/sel_o
+add wave -noupdate -format Logic -label STB_O /test/stb_o
+add wave -noupdate -format Logic -label CYC_O /test/cyc_o
+add wave -noupdate -format Logic -label WE_O /test/we_o
+add wave -noupdate -format Logic -label INTA_CYC_O /test/inta_cyc_o
+add wave -noupdate -format Logic -label I_CYC_O /test/i_cyc_o
+add wave -noupdate -format Logic -label C_CYC_O /test/c_cyc_o
+add wave -noupdate -format Logic -label D_CYC_O /test/d_cyc_o
+add wave -noupdate -format Literal -label ADR_O -radix hexadecimal /test/adr_o
+add wave -noupdate -format Literal -label DAT_IO -radix hexadecimal /test/dat_io
+add wave -noupdate -divider {CPU internal (DP)}
+add wave -noupdate -format Literal -label GPRs -radix hexadecimal -expand /test/cpu/datapath/u1/regfile_data
+add wave -noupdate -format Literal -label IR -radix hexadecimal /test/cpu/datapath/ir_out
+add wave -noupdate -format Literal -label MDRI -radix hexadecimal /test/cpu/datapath/mdri_out
+add wave -noupdate -format Literal -label TR2 -radix hexadecimal /test/cpu/datapath/tr2_out
+add wave -noupdate -format Literal -label PC -radix hexadecimal /test/cpu/datapath/pc_out
+add wave -noupdate -format Literal -label SP -radix hexadecimal /test/cpu/datapath/sp_out
+add wave -noupdate -format Literal -label FLAGS /test/cpu/datapath/flags_out
+add wave -noupdate -format Literal -label INTR /test/cpu/datapath/intr_out
+add wave -noupdate -format Literal -label MAR -radix hexadecimal /test/cpu/datapath/mar_out
+add wave -noupdate -format Literal -label DFH -radix hexadecimal /test/cpu/datapath/dfh_out
+add wave -noupdate -format Literal -label MDRO -radix hexadecimal /test/cpu/datapath/mdro_out
+add wave -noupdate -divider {CPU Internal (Con)}
+add wave -noupdate -format Logic -label Jcc_OK /test/cpu/control/jcc_ok
+add wave -noupdate -format Logic -label rst_sync /test/cpu/control/rst_sync
+add wave -noupdate -format Logic -label ack_sync /test/cpu/control/ack_sync
+add wave -noupdate -format Logic -label intr_sync /test/cpu/control/intr_sync
+add wave -noupdate -format Literal -label cur_state /test/cpu/control/cur_state
+add wave -noupdate -format Literal -label nxt_state /test/cpu/control/nxt_state
+add wave -noupdate -format Literal -label cur_ic /test/cpu/control/cur_ic
+add wave -noupdate -divider RAM
+add wave -noupdate -format Literal -label RAM_data_upper -radix hexadecimal /test/ram/line__87/ram_data_upper
+add wave -noupdate -format Literal -label RAM_data_lower -radix hexadecimal /test/ram/line__87/ram_data_lower
+add wave -noupdate -divider RAM2
+add wave -noupdate -format Literal -label RAM2_data_upper -radix hexadecimal /test/ram2/write_low/ram_data_upper
+add wave -noupdate -format Literal -label RAM2_data_lower -radix hexadecimal /test/ram2/write_low/ram_data_lower
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {200000 ps} 0}
+WaveRestoreZoom {0 ps} {197600 ps}
+configure wave -namecolwidth 139
+configure wave -valuecolwidth 95
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
Index: trunk/impl0/asm/readme.txt
===================================================================
--- trunk/impl0/asm/readme.txt (nonexistent)
+++ trunk/impl0/asm/readme.txt (revision 2)
@@ -0,0 +1,2 @@
+in this directory, i will put assembly programs.
+correspoinding "_init_ram.txt" will be in /sim directory
\ No newline at end of file
Index: trunk/impl0/rtl/vhdl/con1.vhd
===================================================================
--- trunk/impl0/rtl/vhdl/con1.vhd (nonexistent)
+++ trunk/impl0/rtl/vhdl/con1.vhd (revision 2)
@@ -0,0 +1,2080 @@
+--------------------------------------------------------------
+-- con1.vhd
+--------------------------------------------------------------
+-- project: HPC-16 Microprocessor
+--
+-- usage: control unit of microprocessor
+--
+-- dependency: con_pkg.vhd
+--
+---------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.con_pkg.all;
+
+entity con1 is
+ port(
+ CLK_I : in std_logic;
+ RST_I : in std_logic;
+ ACK_I : in std_logic;
+ INTR_I : in std_logic;
+ --
+ SEL_O : out std_logic_vector(1 downto 0);
+ STB_O : out std_logic;
+ CYC_O : out std_logic;
+ WE_O : out std_logic;
+ INTA_CYC_O : out std_logic;
+ C_CYC_O : out std_logic;
+ I_CYC_O : out std_logic;
+ D_CYC_O : out std_logic;
+ --
+ jcc_ok : in std_logic;
+ int_flag : in std_logic;
+ pc0 : in std_logic;
+ sp0 : in std_logic;
+ mar0 : in std_logic;
+ tr20 : in std_logic;
+ ir_high : in std_logic_vector(7 downto 0);
+ --
+ intr_ce : out std_logic;
+ ir_ce : out std_logic;
+ mdri_ce : out std_logic;
+ mdri_hl_zse_sign : out std_logic;
+ intno_mux_sel : out std_logic_vector(2 downto 0);
+ adin_mux_sel : out std_logic_vector(2 downto 0);
+ rf_adwe : out std_logic;
+ pcin_mux_sel : out std_logic_vector(1 downto 0);
+ pc_pre : out std_logic;
+ pc_ce : out std_logic;
+ spin_mux_sel : out std_logic;
+ sp_pre : out std_logic;
+ sp_ce : out std_logic;
+ dfh_ce : out std_logic;
+ alua_mux_sel : out std_logic_vector(1 downto 0);
+ alub_mux_sel : out std_logic_vector(2 downto 0);
+ aopsel : out std_logic_vector(2 downto 0);
+ sopsel : out std_logic_vector(2 downto 0);
+ sbin_mux_sel : out std_logic;
+ asresult_mux_sel : out std_logic;
+ coszin_mux_sel : out std_logic;
+ flags_rst : out std_logic;
+ flags_ce : out std_logic;
+ flags_cfce : out std_logic;
+ flags_ifce : out std_logic;
+ flags_clc : out std_logic;
+ flags_cmc : out std_logic;
+ flags_stc : out std_logic;
+ flags_cli : out std_logic;
+ flags_sti : out std_logic;
+ marin_mux_sel : out std_logic_vector(1 downto 0);
+ mar_ce : out std_logic;
+ mdroin_mux_sel : out std_logic_vector(2 downto 0);
+ mdro_ce : out std_logic; -- mdro rst are removed
+ mdro_oe : out std_logic
+ );
+end con1;
+architecture rtl of con1 is
+ signal rst_sync : std_logic;
+ signal ack_sync : std_logic;
+ signal intr_sync : std_logic;
+ signal cur_state , nxt_state : state;
+ signal cur_ic : ic;
+ signal asopsel : std_logic_vector(3 downto 0);
+
+ for all : sync use entity work.sync(behave2);
+
+begin
+ rsync : sync
+ port map
+ (
+ d => RST_I, clk => CLK_I, q => rst_sync
+ );
+
+ -- uncomment these line to additional synchronization of ACK_I
+ async : sync
+ port map
+ (
+ d => ACK_I, clk => CLK_I, q => ack_sync
+ );
+ -- and comment line below
+ -- ack_sync <= ACK_I;
+
+ isync : sync
+ port map
+ (
+ d => INTR_I, clk => CLK_I, q => intr_sync
+ );
+
+ process(CLK_I, rst_sync)
+ begin
+ if rst_sync = '1' then
+ cur_state <= reset;
+ elsif rising_edge(CLK_I) then
+ cur_state <= nxt_state;
+ end if;
+ end process;
+
+ decode:
+ cur_ic <= ic_mov_rn_rm when ir_high = mov_rn_rm else
+ ic_mov_sp_rm when ir_high = mov_sp_rm else
+ ic_mov_rn_sp when ir_high = mov_rn_sp else
+ ic_ld_rn_rb when ir_high = ld_rn_rb else
+ ic_ld_rn_rb_disp when ir_high = ld_rn_rb_disp else
+ ic_ld_rn_sp when ir_high = ld_rn_sp else
+ ic_ld_rn_sp_disp when ir_high = ld_rn_sp_disp else
+ ic_st_rn_rb when ir_high = st_rn_rb else
+ ic_st_rn_rb_disp when ir_high = st_rn_rb_disp else
+ ic_st_rn_sp when ir_high = st_rn_sp else
+ ic_st_rn_sp_disp when ir_high = st_rn_sp_disp else
+ ic_lbzx_rn_rb when ir_high = lbzx_rn_rb else
+ ic_lbzx_rn_rb_disp when ir_high = lbzx_rn_rb_disp else
+ ic_lbsx_rn_rb when ir_high = lbsx_rn_rb else
+ ic_lbsx_rn_rb_disp when ir_high = lbsx_rn_rb_disp else
+ ic_sb_rn_rb when ir_high = sb_rn_rb else
+ ic_sb_rn_rb_disp when ir_high = sb_rn_rb_disp else
+ ic_sing_dec when ir_high = sing_dec else
+ ic_sing_inc when ir_high = sing_inc else
+ ic_alur when ir_high(7 downto 3) = alur else
+ ic_shiftr when ir_high(7 downto 3) = shiftr else
+ ic_cmp_cmp when ir_high = cmp_cmp else
+ ic_cmp_tst when ir_high = cmp_tst else
+ ic_li_rn when ir_high = li_rn else
+ ic_li_sp when ir_high = li_sp else
+ ic_alui when ir_high(7 downto 3) = alui else
+ ic_shifti when ir_high(7 downto 3) = shifti else
+ ic_cmpi_cmp when ir_high = cmpi_cmp else
+ ic_cmpi_tst when ir_high = cmpi_tst else
+ ic_alusp_sub when ir_high = alusp_sub else
+ ic_alusp_add when ir_high = alusp_add else
+ ic_stk_pushr when ir_high = stk_pushr else
+ ic_stk_pushf when ir_high = stk_pushf else
+ ic_stk_popr when ir_high = stk_popr else
+ ic_stk_popf when ir_high = stk_popf else
+ ic_acall when ir_high = acall else
+ ic_lcall when ir_high = lcall else
+ ic_scall when ir_high(7 downto 3) = scall else
+ ic_ret when ir_high(7 downto 3) = ret else
+ ic_int when ir_high(7 downto 3) = int else
+ ic_into when ir_high(7 downto 3) = into else
+ ic_iret when ir_high(7 downto 3) = iret else
+ ic_ajmp when ir_high = ajmp else
+ ic_ljmp when ir_high = ljmp else
+ ic_sjmp when ir_high(7 downto 3) = sjmp else
+ ic_jcc when ir_high(7 downto 3) = jcc else
+ ic_fop_clc when ir_high = fop_clc else
+ ic_fop_stc when ir_high = fop_stc else
+ ic_fop_cmc when ir_high = fop_cmc else
+ ic_fop_cli when ir_high = fop_cli else
+ ic_fop_sti when ir_high = fop_sti else
+ ic_nop when ir_high(7 downto 3) = nop else
+ ic_hlt when ir_high(7 downto 3) = hlt else
+ ic_invalid;
+
+ process(cur_state, cur_ic, jcc_ok, int_flag, pc0, sp0, tr20, mar0, ir_high(2 downto 0),
+ ack_sync, intr_sync, rst_sync)
+ begin
+ SEL_O <= "00"; STB_O <= '0'; CYC_O <= '0'; WE_O <= '0'; INTA_CYC_O <= '0';
+ C_CYC_O <= '0'; I_CYC_O <= '0'; D_CYC_O <= '0'; intr_ce <= '0';
+ ir_ce <= '0'; mdri_ce <= '0'; mdri_hl_zse_sign <= '0'; intno_mux_sel <= "000";
+ adin_mux_sel <= "000"; rf_adwe <= '0'; pcin_mux_sel <= "00"; pc_pre <= '0';
+ pc_ce <= '0'; spin_mux_sel <= '0'; sp_pre <= '0'; sp_ce <= '0';
+ alua_mux_sel <= "00"; alub_mux_sel <= "000"; sbin_mux_sel <= '0';
+ asopsel <= "0000"; coszin_mux_sel <= '0'; flags_rst <= '0';
+ flags_ce <= '0'; flags_cfce <= '0'; flags_ifce <= '0';
+ flags_clc <= '0'; flags_cmc <= '0'; flags_stc <= '0';
+ flags_cli <= '0'; flags_sti <= '0'; marin_mux_sel <= "00";
+ mar_ce <= '0'; dfh_ce <= '0'; mdroin_mux_sel <= "000";
+ mdro_ce <= '0'; mdro_oe <= '0';
+
+ case cur_state is
+--//////////////////////////////////////
+ when reset =>
+ pc_pre <= '1'; flags_rst <= '1';
+ if rst_sync = '0' then
+ nxt_state <= fetch0;
+ else
+ nxt_state <= reset;
+ end if;
+--//////////////////////////////////////
+ when fetch0 =>
+ if pc0 = '0' then
+ -- mar = pc
+ marin_mux_sel <= marin_mux_sel_pc;
+ mar_ce <= '1';
+ -- pc += 2
+ alua_mux_sel <= alua_mux_sel_pc;
+ alub_mux_sel <= alub_mux_sel_2;
+ asopsel <= asopsel_add;
+ pcin_mux_sel <= pcin_mux_sel_aluout;
+ pc_ce <= '1';
+ --
+ nxt_state <= fetch1;
+ else
+ nxt_state <= align0;
+ end if;
+--///////////////////////////////////////
+ when fetch1 =>
+ -- read instruction
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; I_CYC_O <= '1';
+ -- prepare ir
+ ir_ce <= '1';
+ --
+ nxt_state <= fetch2;
+--///////////////////////////////////////
+ when fetch2 =>
+ if ack_sync = '1' then
+ -- read end
+ nxt_state <= exec0;
+ else
+ -- continue read & prepare ir
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; I_CYC_O <= '1';
+ ir_ce <= '1';
+ --
+ nxt_state <= fetch2;
+ end if;
+--///////////////////////////////////////
+ when exec0 =>
+ case cur_ic is
+ ----------------------------------------------
+ when ic_mov_rn_rm =>
+ -- rn = tr2
+ adin_mux_sel <= adin_mux_sel_tr2;
+ rf_adwe <= '1';
+ --
+ nxt_state <= int_chk;
+ ----------------------------------------------
+ when ic_mov_sp_rm =>
+ -- sp = (tr2 + 0)
+ alua_mux_sel <= alua_mux_sel_tr2;
+ alub_mux_sel <= alub_mux_sel_0;
+ asopsel <= asopsel_add;
+ spin_mux_sel <= spin_mux_sel_aluout;
+ sp_ce <= '1';
+ --
+ nxt_state <= int_chk;
+ ----------------------------------------------
+ when ic_mov_rn_sp =>
+ -- rn = sp
+ adin_mux_sel <= adin_mux_sel_sp;
+ rf_adwe <= '1';
+ --
+ nxt_state <= int_chk;
+ ----------------------------------------------
+ when ic_ld_rn_rb =>
+ if tr20 = '0' then
+ -- mar = tr2 + 0
+ alua_mux_sel <= alua_mux_sel_tr2;
+ alub_mux_sel <= alub_mux_sel_0;
+ asopsel <= asopsel_add;
+ marin_mux_sel <= marin_mux_sel_aluout;
+ mar_ce <= '1';
+ --
+ nxt_state <= exec1;
+ else
+ nxt_state <= align0;
+ end if;
+ ----------------------------------------------
+ when ic_ld_rn_rb_disp | ic_ld_rn_sp_disp |
+ ic_st_rn_rb_disp | ic_st_rn_sp_disp |
+ ic_lbzx_rn_rb_disp | ic_lbsx_rn_rb_disp |
+ ic_sb_rn_rb_disp | ic_li_rn |
+ ic_li_sp | ic_alui | ic_cmpi_cmp |
+ ic_cmpi_tst | ic_alusp_add | ic_alusp_sub =>
+ -- mar = pc
+ marin_mux_sel <= marin_mux_sel_pc;
+ mar_ce <= '1';
+ -- pc += 2
+ alua_mux_sel <= alua_mux_sel_pc;
+ alub_mux_sel <= alub_mux_sel_2;
+ asopsel <= asopsel_add;
+ pcin_mux_sel <= pcin_mux_sel_aluout;
+ pc_ce <= '1';
+ --
+ nxt_state <= exec1;
+ ----------------------------------------------
+ when ic_ld_rn_sp =>
+ if sp0 = '0' then
+ -- mar = sp
+ marin_mux_sel <= marin_mux_sel_sp;
+ mar_ce <= '1';
+ --
+ nxt_state <= exec1;
+ else
+ -- dfh = sp
+ dfh_ce <= '1';
+ --
+ nxt_state <= stkerr0;
+ end if;
+ ----------------------------------------------
+ when ic_st_rn_rb =>
+ if tr20 = '0' then
+ -- mar = tr2 + 0
+ alua_mux_sel <= alua_mux_sel_tr2;
+ alub_mux_sel <= alub_mux_sel_0;
+ asopsel <= asopsel_add;
+ marin_mux_sel <= marin_mux_sel_aluout;
+ mar_ce <= '1';
+ -- mdro = tr1
+ mdroin_mux_sel <= mdroin_mux_sel_tr1;
+ mdro_ce <= '1';
+ --! mdro_oe <= '1';
+ --
+ nxt_state <= exec1;
+ else
+ nxt_state <= align0;
+ end if;
+ ----------------------------------------------
+ when ic_st_rn_sp =>
+ if sp0 = '0' then
+ -- mar = sp
+ marin_mux_sel <= marin_mux_sel_sp;
+ mar_ce <= '1';
+ -- mdro = tr1
+ mdroin_mux_sel <= mdroin_mux_sel_tr1;
+ mdro_ce <= '1';
+ --! mdro_oe <= '1';
+ --
+ nxt_state <= exec1;
+ else
+ -- dfh = sp
+ dfh_ce <= '1';
+ --
+ nxt_state <= stkerr0;
+ end if;
+ ----------------------------------------------
+ when ic_lbzx_rn_rb | ic_lbsx_rn_rb =>
+ -- mar = tr2 + 0
+ alua_mux_sel <= alua_mux_sel_tr2;
+ alub_mux_sel <= alub_mux_sel_0;
+ asopsel <= asopsel_add;
+ marin_mux_sel <= marin_mux_sel_aluout;
+ mar_ce <= '1';
+ --
+ nxt_state <= exec1;
+ ----------------------------------------------
+ when ic_sb_rn_rb =>
+ -- mar = tr2 + 0
+ alua_mux_sel <= alua_mux_sel_tr2;
+ alub_mux_sel <= alub_mux_sel_0;
+ asopsel <= asopsel_add;
+ marin_mux_sel <= marin_mux_sel_aluout;
+ mar_ce <= '1';
+ --
+ if tr20 = '0' then
+ -- mdro = tr1(7..0) & 0000_0000
+ mdroin_mux_sel <= mdroin_mux_sel_tr1_loweven;
+ else
+ -- mdro = 0000_0000 & tr1(7..0)
+ mdroin_mux_sel <= mdroin_mux_sel_tr1_lowodd;
+ end if;
+ mdro_ce <= '1';
+ --! mdro_oe <= '1';
+ --
+ nxt_state <= exec1;
+ ----------------------------------------------
+ when ic_sing_inc =>
+ -- tr5 = tr1 + 1
+ alua_mux_sel <= alua_mux_sel_tr1;
+ alub_mux_sel <= alub_mux_sel_1;
+ asopsel <= asopsel_add;
+ -- flags updated (except cf, if)
+ coszin_mux_sel <= coszin_mux_sel_asresult;
+ flags_ce <= '1';
+ --
+ nxt_state <= exec1;
+ ----------------------------------------------
+ when ic_sing_dec =>
+ -- tr5 = tr1 - 1
+ alua_mux_sel <= alua_mux_sel_tr1;
+ alub_mux_sel <= alub_mux_sel_1;
+ asopsel <= asopsel_sub;
+ -- flags updated (except cf, if)
+ coszin_mux_sel <= coszin_mux_sel_asresult;
+ flags_ce <= '1';
+ --
+ nxt_state <= exec1;
+ ----------------------------------------------
+ when ic_alur =>
+ -- tr5 = tr1 aluop tr2
+ alua_mux_sel <= alua_mux_sel_tr1;
+ alub_mux_sel <= alub_mux_sel_tr2;
+ case ir_high(2 downto 0) is
+ when a_sub =>
+ asopsel <= asopsel_sub;
+ when a_add =>
+ asopsel <= asopsel_add;
+ when a_sbb =>
+ asopsel <= asopsel_sbb;
+ when a_adc =>
+ asopsel <= asopsel_adc;
+ when a_not =>
+ asopsel <= asopsel_not;
+ when a_and =>
+ asopsel <= asopsel_and;
+ when a_or =>
+ asopsel <= asopsel_or;
+ when a_xor =>
+ asopsel <= asopsel_xor;
+ when others =>
+ asopsel <= (others => '0');
+ end case;
+ -- flags updated (except if)
+ coszin_mux_sel <= coszin_mux_sel_asresult;
+ flags_ce <= '1';
+ flags_cfce <= '1';
+ --
+ nxt_state <= exec1;
+ ----------------------------------------------
+ when ic_shiftr =>
+ -- tr5 = tr1 shiftop tr2
+ sbin_mux_sel <= sbin_mux_sel_tr2;
+ case ir_high(2 downto 0) is
+ when s_sll =>
+ asopsel <= asopsel_sll;
+ when s_slr =>
+ asopsel <= asopsel_slr;
+ when s_sal =>
+ asopsel <= asopsel_sal;
+ when s_sar =>
+ asopsel <= asopsel_sar;
+ when s_rol =>
+ asopsel <= asopsel_rol;
+ when s_ror =>
+ asopsel <= asopsel_ror;
+ when s_rcl =>
+ asopsel <= asopsel_rcl;
+ when s_rcr =>
+ asopsel <= asopsel_rcr;
+ when others =>
+ asopsel <= (others => '0');
+ end case;
+ -- flags updated (except if)
+ coszin_mux_sel <= coszin_mux_sel_asresult;
+ flags_ce <= '1';
+ flags_cfce <= '1';
+ --
+ nxt_state <= exec1;
+ ----------------------------------------------
+ when ic_cmp_cmp =>
+ -- tr5 = tr1 - tr2
+ alua_mux_sel <= alua_mux_sel_tr1;
+ alub_mux_sel <= alub_mux_sel_tr2;
+ asopsel <= asopsel_sub;
+ -- flags updated (except if)
+ coszin_mux_sel <= coszin_mux_sel_asresult;
+ flags_ce <= '1';
+ flags_cfce <= '1';
+ --
+ nxt_state <= int_chk;
+ ----------------------------------------------
+ when ic_cmp_tst =>
+ -- tr5 = tr1 and tr2
+ alua_mux_sel <= alua_mux_sel_tr1;
+ alub_mux_sel <= alub_mux_sel_tr2;
+ asopsel <= asopsel_and;
+ -- flags updated (except if)
+ coszin_mux_sel <= coszin_mux_sel_asresult;
+ flags_ce <= '1';
+ flags_cfce <= '1';
+ --
+ nxt_state <= int_chk;
+ ----------------------------------------------
+ when ic_shifti =>
+ -- tr5 = tr1 shiftop ir(3..0)
+ sbin_mux_sel <= sbin_mux_sel_ir;
+ case ir_high(2 downto 0) is
+ when s_sll =>
+ asopsel <= asopsel_sll;
+ when s_slr =>
+ asopsel <= asopsel_slr;
+ when s_sal =>
+ asopsel <= asopsel_sal;
+ when s_sar =>
+ asopsel <= asopsel_sar;
+ when s_rol =>
+ asopsel <= asopsel_rol;
+ when s_ror =>
+ asopsel <= asopsel_ror;
+ when s_rcl =>
+ asopsel <= asopsel_rcl;
+ when s_rcr =>
+ asopsel <= asopsel_rcr;
+ when others =>
+ asopsel <= (others => '0');
+ end case;
+ -- flags updated (except if)
+ coszin_mux_sel <= coszin_mux_sel_asresult;
+ flags_ce <= '1';
+ flags_cfce <= '1';
+ --
+ nxt_state <= exec1;
+ ----------------------------------------------
+ when ic_stk_pushr =>
+ if sp0 = '0' then
+ --
+ alua_mux_sel <= alua_mux_sel_sp;
+ alub_mux_sel <= alub_mux_sel_2;
+ asopsel <= asopsel_sub;
+ -- sp = old sp - 2
+ spin_mux_sel <= spin_mux_sel_aluout;
+ sp_ce <= '1';
+ -- mar = old sp - 2
+ marin_mux_sel <= marin_mux_sel_aluout;
+ mar_ce <= '1';
+ -- mdro = tr1
+ mdroin_mux_sel <= mdroin_mux_sel_tr1;
+ mdro_ce <= '1';
+ --! mdro_oe <= '1';
+ --
+ nxt_state <= exec1;
+ else
+ -- dfh = sp
+ dfh_ce <= '1';
+ nxt_state <= stkerr0;
+ end if;
+ ----------------------------------------------
+ when ic_stk_pushf =>
+ if sp0 = '0' then
+ --
+ alua_mux_sel <= alua_mux_sel_sp;
+ alub_mux_sel <= alub_mux_sel_2;
+ asopsel <= asopsel_sub;
+ -- sp = old sp - 2
+ spin_mux_sel <= spin_mux_sel_aluout;
+ sp_ce <= '1';
+ -- mar = old sp - 2
+ marin_mux_sel <= marin_mux_sel_aluout;
+ mar_ce <= '1';
+ -- mdro = flags
+ mdroin_mux_sel <= mdroin_mux_sel_flags;
+ mdro_ce <= '1';
+ --! mdro_oe <= '1';
+ --
+ nxt_state <= exec1;
+ else
+ -- dfh = sp
+ dfh_ce <= '1';
+ --
+ nxt_state <= stkerr0;
+ end if;
+ ----------------------------------------------
+ when ic_stk_popr | ic_stk_popf | ic_ret | ic_iret =>
+ if sp0 = '0' then
+ --
+ alua_mux_sel <= alua_mux_sel_sp;
+ alub_mux_sel <= alub_mux_sel_2;
+ asopsel <= asopsel_add;
+ -- sp = old sp + 2
+ spin_mux_sel <= spin_mux_sel_aluout;
+ sp_ce <= '1';
+ -- mar = old sp
+ marin_mux_sel <= marin_mux_sel_sp;
+ mar_ce <= '1';
+ --
+ nxt_state <= exec1;
+ else
+ -- dfh = sp
+ dfh_ce <= '1';
+ --
+ nxt_state <= stkerr0;
+ end if;
+ ---------------------------------------------
+ when ic_acall | ic_lcall | ic_scall =>
+ if sp0 = '0' then
+ alua_mux_sel <= alua_mux_sel_sp;
+ alub_mux_sel <= alub_mux_sel_2;
+ asopsel <= asopsel_sub;
+ -- sp = old sp - 2
+ spin_mux_sel <= spin_mux_sel_aluout;
+ sp_ce <= '1';
+ -- mar = old sp - 2
+ marin_mux_sel <= marin_mux_sel_aluout;
+ mar_ce <= '1';
+ -- mdro = pc
+ mdroin_mux_sel <= mdroin_mux_sel_pc;
+ mdro_ce <= '1';
+ --! mdro_oe <= '1';
+ --
+ nxt_state <= exec1;
+ else
+ -- dfh =sp
+ dfh_ce <= '1';
+ --
+ nxt_state <= stkerr0;
+ end if;
+ ---------------------------------------------
+ when ic_int =>
+ if sp0 = '0' then
+ alua_mux_sel <= alua_mux_sel_sp;
+ alub_mux_sel <= alub_mux_sel_2;
+ asopsel <= asopsel_sub;
+ -- sp = old sp - 2
+ spin_mux_sel <= spin_mux_sel_aluout;
+ sp_ce <= '1';
+ -- mar = old sp - 2
+ marin_mux_sel <= marin_mux_sel_aluout;
+ mar_ce <= '1';
+ -- mdro = flags
+ mdroin_mux_sel <= mdroin_mux_sel_flags;
+ mdro_ce <= '1';
+ --! mdro_oe <= '1';
+ --
+ nxt_state <= exec1;
+ else
+ -- mdro = intno
+ intno_mux_sel <= intno_mux_sel_ir;
+ mdroin_mux_sel <= mdroin_mux_sel_intno;
+ mdro_ce <= '1';
+ --! mdro_oe <= '1';
+ -- dfh =sp
+ dfh_ce <= '1';
+ --
+ nxt_state <= df0;
+ end if;
+ ---------------------------------------------
+ when ic_into =>
+ if sp0 = '0' then
+ if jcc_ok = '0' then
+ alua_mux_sel <= alua_mux_sel_sp;
+ alub_mux_sel <= alub_mux_sel_2;
+ asopsel <= asopsel_sub;
+ -- sp = old sp - 2
+ spin_mux_sel <= spin_mux_sel_aluout;
+ sp_ce <= '1';
+ -- mar = old sp - 2
+ marin_mux_sel <= marin_mux_sel_aluout;
+ mar_ce <= '1';
+ -- mdro = flags
+ mdroin_mux_sel <= mdroin_mux_sel_flags;
+ mdro_ce <= '1';
+ --! mdro_oe <= '1';
+ --
+ nxt_state <= exec1;
+ else
+ nxt_state <= int_chk;
+ end if;
+ else
+ -- mdro = intno
+ intno_mux_sel <= intno_mux_sel_ir;
+ mdroin_mux_sel <= mdroin_mux_sel_intno;
+ mdro_ce <= '1';
+ --! mdro_oe <= '1';
+ -- dfh =sp
+ dfh_ce <= '1';
+ --
+ nxt_state <= df0;
+ end if;
+ ---------------------------------------------
+ when ic_ajmp =>
+ -- pc = tr2
+ alua_mux_sel <= alua_mux_sel_tr2;
+ alub_mux_sel <= alub_mux_sel_0;
+ asopsel <= asopsel_add;
+ pcin_mux_sel <= pcin_mux_sel_aluout;
+ pc_ce <= '1';
+ --
+ nxt_state <= int_chk;
+ --------------------------------------------
+ when ic_ljmp =>
+ -- pc += tr2
+ alua_mux_sel <= alua_mux_sel_pc;
+ alub_mux_sel <= alub_mux_sel_tr2;
+ asopsel <= asopsel_add;
+ pcin_mux_sel <= pcin_mux_sel_aluout;
+ pc_ce <= '1';
+ --
+ nxt_state <= int_chk;
+ ---------------------------------------------
+ when ic_sjmp =>
+ -- pc += tr3
+ alua_mux_sel <= alua_mux_sel_pc;
+ alub_mux_sel <= alub_mux_sel_tr3;
+ asopsel <= asopsel_add;
+ pcin_mux_sel <= pcin_mux_sel_aluout;
+ pc_ce <= '1';
+ --
+ nxt_state <= int_chk;
+ ----------------------------------------------
+ when ic_jcc =>
+ if jcc_ok = '1' then
+ -- pc += tr4
+ alua_mux_sel <= alua_mux_sel_pc;
+ alub_mux_sel <= alub_mux_sel_tr4;
+ asopsel <= asopsel_add;
+ pcin_mux_sel <= pcin_mux_sel_aluout;
+ pc_ce <= '1';
+ --
+ else
+ null;
+ end if;
+ nxt_state <= int_chk;
+ ----------------------------------------------
+ when ic_fop_clc =>
+ flags_clc <= '1';
+ nxt_state <= int_chk;
+ ----------------------------------------------
+ when ic_fop_cmc =>
+ flags_cmc <= '1';
+ nxt_state <= int_chk;
+ ----------------------------------------------
+ when ic_fop_stc =>
+ flags_stc <= '1';
+ nxt_state <= int_chk;
+ ----------------------------------------------
+ when ic_fop_cli =>
+ flags_cli <= '1';
+ nxt_state <= int_chk;
+ ----------------------------------------------
+ when ic_fop_sti =>
+ flags_stc <= '1';
+ nxt_state <= int_chk;
+ ----------------------------------------------
+ when ic_nop =>
+ nxt_state <= int_chk;
+ ----------------------------------------------
+ when ic_hlt =>
+ flags_sti <= '1';
+ nxt_state <= halted;
+ ----------------------------------------------
+ when ic_invalid =>
+ nxt_state <= invalid0;
+ ----------------------------------------------
+ end case;
+--///////////////////////////////////////
+ when exec1 =>
+ case cur_ic is
+ ----------------------------------------------
+ when ic_ld_rn_rb | ic_ld_rn_sp | ic_stk_popr |
+ ic_stk_popf | ic_ret | ic_iret =>
+ -- read data word
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; D_CYC_O <= '1';
+ -- prepare mdri
+ mdri_ce <= '1';
+ --
+ nxt_state <= exec2;
+ ---------------------------------------------
+ when ic_ld_rn_rb_disp | ic_ld_rn_sp_disp |
+ ic_st_rn_rb_disp | ic_st_rn_sp_disp |
+ ic_lbzx_rn_rb_disp | ic_lbsx_rn_rb_disp |
+ ic_sb_rn_rb_disp | ic_li_rn | ic_li_sp |
+ ic_alui | ic_cmpi_cmp | ic_cmpi_tst |
+ ic_alusp_add | ic_alusp_sub =>
+ -- read const word
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; C_CYC_O <= '1';
+ -- prepare mdri
+ mdri_ce <= '1';
+ --
+ nxt_state <= exec2;
+ --------------------------------------------
+ when ic_st_rn_rb | ic_st_rn_sp | ic_stk_pushr |
+ ic_stk_pushf | ic_acall | ic_lcall | ic_scall |
+ ic_int | ic_into =>
+ mdro_oe <= '1';
+ -- write data word
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
+ --
+ nxt_state <= exec2;
+ -------------------------------------------
+ when ic_lbzx_rn_rb | ic_lbsx_rn_rb =>
+ -- read data byte
+ if mar0 = '0' then
+ SEL_O <= "10";
+ else
+ SEL_O <= "01";
+ end if;
+ STB_O <= '1'; CYC_O <= '1'; D_CYC_O <= '1';
+ --
+ mdri_ce <= '1';
+ --
+ nxt_state <= exec2;
+ --------------------------------------------
+ when ic_sb_rn_rb =>
+ mdro_oe <= '1';
+ -- write data byte
+ if mar0 = '0' then
+ SEL_O <= "10";
+ else
+ SEL_O <= "01";
+ end if;
+ STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
+ --
+ nxt_state <= exec2;
+ --------------------------------------------
+ when ic_sing_inc | ic_sing_dec | ic_alur |
+ ic_shiftr | ic_shifti =>
+ -- rn = tr5
+ adin_mux_sel <= adin_mux_sel_tr5;
+ rf_adwe <= '1';
+ --
+ nxt_state <= int_chk;
+ --------------------------------------------
+ when others =>
+ null;
+ end case;
+--///////////////////////////////////////
+ when exec2 =>
+ case cur_ic is
+ ----------------------------------------------
+ when ic_ld_rn_rb | ic_ld_rn_sp =>
+ if ack_sync = '1' then
+ -- rn = mdri
+ adin_mux_sel <= adin_mux_sel_mdri;
+ rf_adwe <= '1';
+ --
+ nxt_state <= int_chk;
+ else
+ -- try reading data word
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; D_CYC_O <= '1';
+ -- prepare mdri
+ mdri_ce <= '1';
+ --
+ nxt_state <= exec2;
+ end if;
+ --------------------------------------------
+ when ic_ld_rn_rb_disp |
+ ic_lbzx_rn_rb_disp | ic_lbsx_rn_rb_disp =>
+ if ack_sync = '1' then
+ -- mar = tr2 + mdri
+ alua_mux_sel <= alua_mux_sel_tr2;
+ alub_mux_sel <= alub_mux_sel_mdri;
+ asopsel <= asopsel_add;
+ marin_mux_sel <= marin_mux_sel_aluout;
+ mar_ce <= '1';
+ --
+ nxt_state <= exec3;
+ else
+ -- try reading const word data
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; C_CYC_O <= '1';
+ -- prepare mdri
+ mdri_ce <= '1';
+ --
+ nxt_state <= exec2;
+ end if;
+ --------------------------------------------
+ when ic_ld_rn_sp_disp =>
+ if ack_sync = '1' then
+ -- mar = sp + mdri
+ alua_mux_sel <= alua_mux_sel_sp;
+ alub_mux_sel <= alub_mux_sel_mdri;
+ asopsel <= asopsel_add;
+ marin_mux_sel <= marin_mux_sel_aluout;
+ mar_ce <= '1';
+ --
+ nxt_state <= exec3;
+ else
+ -- try reading const word data
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; C_CYC_O <= '1';
+ -- prepare mdri
+ mdri_ce <= '1';
+ --
+ nxt_state <= exec2;
+ end if;
+ --------------------------------------------
+ when ic_st_rn_rb_disp =>
+ if ack_sync = '1' then
+ -- mar = tr2 + mdri
+ alua_mux_sel <= alua_mux_sel_tr2;
+ alub_mux_sel <= alub_mux_sel_mdri;
+ asopsel <= asopsel_add;
+ marin_mux_sel <= marin_mux_sel_aluout;
+ mar_ce <= '1';
+ -- mdro = tr1
+ mdroin_mux_sel <= mdroin_mux_sel_tr1;
+ mdro_ce <= '1';
+ --! mdro_oe <= '1';
+ --
+ nxt_state <= exec3;
+ else
+ -- try reading const word data
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; C_CYC_O <= '1';
+ -- prepare mdri
+ mdri_ce <= '1';
+ --
+ nxt_state <= exec2;
+ end if;
+ --------------------------------------------
+ when ic_st_rn_sp_disp =>
+ if ack_sync = '1' then
+ -- mar = sp + mdri
+ alua_mux_sel <= alua_mux_sel_sp;
+ alub_mux_sel <= alub_mux_sel_mdri;
+ asopsel <= asopsel_add;
+ marin_mux_sel <= marin_mux_sel_aluout;
+ mar_ce <= '1';
+ -- mdro = tr1
+ mdroin_mux_sel <= mdroin_mux_sel_tr1;
+ mdro_ce <= '1';
+ --! mdro_oe <= '1';
+ --
+ nxt_state <= exec3;
+ else
+ -- try reading const word data
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; C_CYC_O <= '1';
+ -- prepare mdri
+ mdri_ce <= '1';
+ --
+ nxt_state <= exec2;
+ end if;
+ --------------------------------------------
+ when ic_st_rn_rb | ic_st_rn_sp =>
+ if ack_sync = '1' then
+ nxt_state <= int_chk;
+ else
+ mdro_oe <= '1';
+ -- try write data word
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
+ --
+ nxt_state <= exec2;
+ end if;
+ --------------------------------------------
+ when ic_lbzx_rn_rb =>
+ if ack_sync = '1' then
+ mdri_hl_zse_sign <= '0';
+ if mar0 = '0' then
+ adin_mux_sel <= adin_mux_sel_mdri_high;
+ else
+ adin_mux_sel <= adin_mux_sel_mdri_low;
+ end if;
+ rf_adwe <= '1';
+ --
+ nxt_state <= int_chk;
+ else
+ -- try read byte
+ if mar0 = '0' then
+ SEL_O <= "10";
+ else
+ SEL_O <= "01";
+ end if;
+ STB_O <= '1'; CYC_O <= '1'; D_CYC_O <= '1';
+ --
+ mdri_ce <= '1';
+ --
+ nxt_state <= exec2;
+ end if;
+ --------------------------------------------
+ when ic_lbsx_rn_rb =>
+ if ack_sync = '1' then
+ mdri_hl_zse_sign <= '1';
+ if mar0 = '0' then
+ adin_mux_sel <= adin_mux_sel_mdri_high;
+ else
+ adin_mux_sel <= adin_mux_sel_mdri_low;
+ end if;
+ rf_adwe <= '1';
+ --
+ nxt_state <= int_chk;
+ else
+ -- try read byte
+ if mar0 = '0' then
+ SEL_O <= "10";
+ else
+ SEL_O <= "01";
+ end if;
+ STB_O <= '1'; CYC_O <= '1'; D_CYC_O <= '1';
+ --
+ mdri_ce <= '1';
+ --
+ nxt_state <= exec2;
+ end if;
+ --------------------------------------------
+ when ic_sb_rn_rb =>
+ if ack_sync = '1' then
+ nxt_state <= int_chk;
+ else
+ mdro_oe <= '1';
+ -- try writing byte
+ if mar0 = '0' then
+ SEL_O <= "10";
+ else
+ SEL_O <= "01";
+ end if;
+ STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
+ --
+ nxt_state <= exec2;
+ end if;
+ --------------------------------------------
+ when ic_sb_rn_rb_disp =>
+ if ack_sync = '1' then
+ -- mar = tr2 + mdri
+ alua_mux_sel <= alua_mux_sel_tr2;
+ alub_mux_sel <= alub_mux_sel_mdri;
+ asopsel <= asopsel_add;
+ marin_mux_sel <= marin_mux_sel_aluout;
+ mar_ce <= '1';
+ nxt_state <= exec3;
+ else
+ -- try reading const word data
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; C_CYC_O <= '1';
+ -- prepare mdri
+ mdri_ce <= '1';
+ --
+ nxt_state <= exec2;
+ end if;
+ --------------------------------------------
+ when ic_li_rn =>
+ if ack_sync = '1' then
+ -- rn = mdri
+ adin_mux_sel <= adin_mux_sel_mdri;
+ rf_adwe <= '1';
+ --
+ nxt_state <= int_chk;
+ else
+ -- try reading const word
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; C_CYC_O <= '1';
+ -- prepare mdri
+ mdri_ce <= '1';
+ --
+ nxt_state <= exec2;
+ end if;
+ --------------------------------------------
+ when ic_li_sp =>
+ if ack_sync = '1' then
+ -- sp = mdri
+ spin_mux_sel <= spin_mux_sel_mdri;
+ sp_ce <= '1';
+ --
+ nxt_state <= int_chk;
+ else
+ -- try reading const word
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; C_CYC_O <= '1';
+ -- prepare mdri
+ mdri_ce <= '1';
+ --
+ nxt_state <= exec2;
+ end if;
+ --------------------------------------------
+ when ic_alui =>
+ if ack_sync = '1' then
+ -- tr5 = tr1 aluop mdri
+ alua_mux_sel <= alua_mux_sel_tr1;
+ alub_mux_sel <= alub_mux_sel_mdri;
+ case ir_high(2 downto 0) is
+ when a_sub =>
+ asopsel <= asopsel_sub;
+ when a_add =>
+ asopsel <= asopsel_add;
+ when a_sbb =>
+ asopsel <= asopsel_sbb;
+ when a_adc =>
+ asopsel <= asopsel_adc;
+ when a_and =>
+ asopsel <= asopsel_and;
+ when a_or =>
+ asopsel <= asopsel_or;
+ when a_xor =>
+ asopsel <= asopsel_xor;
+ when others =>
+ asopsel <= (others => '0');
+ end case;
+ -- flags updated (except if)
+ coszin_mux_sel <= coszin_mux_sel_asresult;
+ flags_ce <= '1';
+ flags_cfce <= '1';
+ --
+ nxt_state <= exec3;
+ else
+ -- try reading const word
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; C_CYC_O <= '1';
+ -- prepare mdri
+ mdri_ce <= '1';
+ --
+ nxt_state <= exec2;
+ end if;
+ --------------------------------------------
+ when ic_cmpi_cmp =>
+ if ack_sync = '1' then
+ -- tr5 = tr1 - mdri
+ alua_mux_sel <= alua_mux_sel_tr1;
+ alub_mux_sel <= alub_mux_sel_mdri;
+ asopsel <= asopsel_sub;
+ -- flags updated
+ coszin_mux_sel <= coszin_mux_sel_asresult;
+ flags_ce <= '1';
+ flags_cfce <= '1';
+ --
+ nxt_state <= int_chk;
+ else
+ -- try reading const word
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; C_CYC_O <= '1';
+ -- prepare mdri
+ mdri_ce <= '1';
+ --
+ nxt_state <= exec2;
+ end if;
+ --------------------------------------------
+ when ic_cmpi_tst =>
+ if ack_sync = '1' then
+ -- tr5 = tr1 and mdri
+ alua_mux_sel <= alua_mux_sel_tr1;
+ alub_mux_sel <= alub_mux_sel_mdri;
+ asopsel <= asopsel_and;
+ -- flags updated
+ coszin_mux_sel <= coszin_mux_sel_asresult;
+ flags_ce <= '1';
+ flags_cfce <= '1';
+ --
+ nxt_state <= int_chk;
+ else
+ -- try reading const word
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; C_CYC_O <= '1';
+ -- prepare mdri
+ mdri_ce <= '1';
+ --
+ nxt_state <= exec2;
+ end if;
+ --------------------------------------------
+ when ic_alusp_sub =>
+ if ack_sync = '1' then
+ -- sp = sp - mdri
+ alua_mux_sel <= alua_mux_sel_sp;
+ alub_mux_sel <= alub_mux_sel_mdri;
+ asopsel <= asopsel_sub;
+ spin_mux_sel <= spin_mux_sel_aluout;
+ sp_ce <= '1';
+ --
+ nxt_state <= int_chk;
+ else
+ -- try reading const word
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; C_CYC_O <= '1';
+ -- prepare mdri
+ mdri_ce <= '1';
+ --
+ nxt_state <= exec2;
+ end if;
+ --------------------------------------------
+ when ic_alusp_add =>
+ if ack_sync = '1' then
+ -- sp = sp + mdri
+ alua_mux_sel <= alua_mux_sel_sp;
+ alub_mux_sel <= alub_mux_sel_mdri;
+ asopsel <= asopsel_add;
+ spin_mux_sel <= spin_mux_sel_aluout;
+ sp_ce <= '1';
+ --
+ nxt_state <= int_chk;
+ else
+ -- try reading const word
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; C_CYC_O <= '1';
+ -- prepare mdri
+ mdri_ce <= '1';
+ --
+ nxt_state <= exec2;
+ end if;
+ --------------------------------------------
+ when ic_stk_pushr | ic_stk_pushf =>
+ if ack_sync = '1' then
+ nxt_state <= int_chk;
+ else
+ mdro_oe <= '1';
+ -- try writing data word
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
+ --
+ nxt_state <= exec2;
+ end if;
+ --------------------------------------------
+ when ic_stk_popr =>
+ if ack_sync = '1'then
+ -- rn = mdri
+ adin_mux_sel <= adin_mux_sel_mdri;
+ rf_adwe <= '1';
+ nxt_state <= int_chk;
+ else
+ -- try reading data word
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; D_CYC_O <= '1';
+ --
+ mdri_ce <= '1';
+ --
+ nxt_state <= exec2;
+ end if;
+ --------------------------------------------
+ when ic_stk_popf =>
+ if ack_sync = '1' then
+ -- flags = mdri
+ coszin_mux_sel <= coszin_mux_sel_mdri;
+ flags_ce <= '1';
+ flags_cfce <= '1';
+ flags_ifce <= '1';
+ --
+ nxt_state <= int_chk;
+ else
+ -- try reading word data
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; D_CYC_O <= '1';
+ --
+ mdri_ce <= '1';
+ --
+ nxt_state <= exec2;
+ end if;
+ --------------------------------------------
+ when ic_acall =>
+ if ack_sync = '0' then
+ -- pc = tr2
+ alua_mux_sel <= alua_mux_sel_tr2;
+ alub_mux_sel <= alub_mux_sel_0;
+ asopsel <= asopsel_add;
+ pcin_mux_sel <= pcin_mux_sel_aluout;
+ pc_ce <= '1';
+ --
+ nxt_state <= int_chk;
+ else
+ mdro_oe <= '1';
+ -- try writing data word
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
+ --
+ nxt_state <= exec2;
+ end if;
+ --------------------------------------------
+ when ic_lcall =>
+ if ack_sync = '0' then
+ -- pc += tr2
+ alua_mux_sel <= alua_mux_sel_pc;
+ alub_mux_sel <= alub_mux_sel_tr2;
+ asopsel <= asopsel_add;
+ pcin_mux_sel <= pcin_mux_sel_aluout;
+ pc_ce <= '1';
+ --
+ nxt_state <= int_chk;
+ else
+ mdro_oe <= '1';
+ -- try writing data word
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
+ --
+ nxt_state <= exec2;
+ end if;
+ ------------------------------------------
+ when ic_scall =>
+ if ack_sync = '0' then
+ -- pc += tr2
+ alua_mux_sel <= alua_mux_sel_pc;
+ alub_mux_sel <= alub_mux_sel_tr3;
+ asopsel <= asopsel_add;
+ pcin_mux_sel <= pcin_mux_sel_aluout;
+ pc_ce <= '1';
+ --
+ nxt_state <= int_chk;
+ else
+ mdro_oe <= '1';
+ -- try writing data word
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
+ --
+ nxt_state <= exec2;
+ end if;
+ -----------------------------------------
+ when ic_ret =>
+ if ack_sync = '0' then
+ -- pc = mdri
+ pcin_mux_sel <= pcin_mux_sel_mdri;
+ pc_ce <= '1';
+ --
+ nxt_state <= int_chk;
+ else
+ -- try reading data word
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; D_CYC_O <= '1';
+ --
+ mdri_ce <= '1';
+ --
+ nxt_state <= exec2;
+ end if;
+ -------------------------------------------
+ when ic_int | ic_into =>
+ if ack_sync = '1' then
+ alua_mux_sel <= alua_mux_sel_sp;
+ alub_mux_sel <= alub_mux_sel_2;
+ asopsel <= asopsel_sub;
+ -- mar = old sp -2
+ marin_mux_sel <= marin_mux_sel_aluout;
+ mar_ce <= '1';
+ -- sp = old sp - 2
+ spin_mux_sel <= spin_mux_sel_aluout;
+ sp_ce <= '1';
+ -- mdro = pc
+ mdroin_mux_sel <= mdroin_mux_sel_pc;
+ mdro_ce <= '1';
+ --! mdro_oe <= '1';
+ --
+ nxt_state <= exec3;
+ else
+ mdro_oe <= '1';
+ -- try writing data word
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
+ --
+ nxt_state <= exec2;
+ end if;
+ -----------------------------------------
+ when ic_iret =>
+ if ack = '1' then
+ -- pc = mdri
+ pcin_mux_sel <= pcin_mux_sel_mdri;
+ pc_ce <= '1';
+ -- sp = old sp + 2
+ alua_mux_sel <= alua_mux_sel_sp;
+ alub_mux_sel <= alub_mux_sel_2;
+ asopsel <= asopsel_add;
+ spin_mux_sel <= spin_mux_sel_aluout;
+ -- mar = sp
+ marin_mux_sel <= marin_mux_sel_sp;
+ mar_ce <= '1';
+ --
+ nxt_state <= exec3;
+ else
+ -- try reading data word
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; D_CYC_O <= '1';
+ --
+ mdri_ce <= '1';
+ --
+ nxt_state <= exec2;
+ end if;
+ --------------------------------------------
+ when others =>
+ null;
+ -------------------------------------------
+ end case;
+--///////////////////////////////////////
+ when exec3 =>
+ case cur_ic is
+ ----------------------------------------------
+ when ic_ld_rn_rb_disp | ic_ld_rn_sp_disp =>
+ if mar0 = '0' then
+ -- try reading data word
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; D_CYC_O <= '1';
+ --
+ mdri_ce <= '1';
+ --
+ nxt_state <= exec4;
+ else
+ nxt_state <= align0;
+ end if;
+ ----------------------------------------------
+ when ic_st_rn_rb_disp | ic_st_rn_sp_disp =>
+ if mar0 = '0' then
+ mdro_oe <= '1';
+ -- try writing data word
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
+ --
+ nxt_state <= exec4;
+ else
+ nxt_state <= align0;
+ end if;
+ ----------------------------------------------
+ when ic_lbzx_rn_rb_disp | ic_lbsx_rn_rb_disp =>
+ -- try reading data byte
+ if mar0 = '0' then
+ SEL_O <= "10";
+ else
+ SEL_O <= "01";
+ end if;
+ STB_O <= '1'; CYC_O <= '1'; D_CYC_O <= '1';
+ --
+ mdri_ce <= '1';
+ --
+ nxt_state <= exec4;
+ ----------------------------------------------
+ when ic_sb_rn_rb_disp =>
+ --! mdro_oe <= '1';
+ mdro_ce <= '1';
+ if mar0 = '0' then
+ mdroin_mux_sel <= mdroin_mux_sel_tr1_loweven;
+ else
+ mdroin_mux_sel <= mdroin_mux_sel_tr1_lowodd;
+ end if;
+ nxt_state <= exec4;
+ ----------------------------------------------
+ when ic_alui =>
+ -- rn = tr5
+ adin_mux_sel <= adin_mux_sel_tr5;
+ rf_adwe <= '1';
+ --
+ nxt_state <= int_chk;
+ ----------------------------------------------
+ when ic_int | ic_into =>
+ mdro_oe <= '1';
+ -- try writting word
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
+ --
+ nxt_state <= exec4;
+ ----------------------------------------------
+ when ic_iret =>
+ mdri_ce <= '1';
+ -- try reading word
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; D_CYC_O <= '1';
+ --
+ nxt_state <= exec4;
+ ----------------------------------------------
+ when others =>
+ null;
+ ----------------------------------------------
+ end case;
+--///////////////////////////////////////
+ when exec4 =>
+ case cur_ic is
+ ----------------------------------------------
+ when ic_ld_rn_rb_disp | ic_ld_rn_sp_disp =>
+ if ack_sync = '1' then
+ adin_mux_sel <= adin_mux_sel_mdri;
+ rf_adwe <= '1';
+ --
+ nxt_state <= int_chk;
+ else
+ mdri_ce <= '1';
+ -- read data word
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; D_CYC_O <= '1';
+ --
+ nxt_state <= exec4;
+ end if;
+ ----------------------------------------------
+ when ic_st_rn_rb_disp | ic_st_rn_sp_disp =>
+ if ack_sync = '1' then
+ nxt_state <= int_chk;
+ else
+ mdro_oe <= '1';
+ -- write data word
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
+ --
+ nxt_state <= exec4;
+ end if;
+ ----------------------------------------------
+ when ic_lbzx_rn_rb_disp =>
+ if ack_sync = '1' then
+ mdri_hl_zse_sign <= '0';
+ if mar0 = '0' then
+ adin_mux_sel <= adin_mux_sel_mdri_high;
+ else
+ adin_mux_sel <= adin_mux_sel_mdri_low;
+ end if;
+ rf_adwe <= '1';
+ --
+ nxt_state <= int_chk;
+ else
+ mdri_ce <= '1';
+ if mar0 = '0' then
+ SEL_O <= "10";
+ else
+ SEL_O <= "01";
+ end if;
+ STB_O <= '1'; CYC_O <= '1'; D_CYC_O <= '1';
+ --
+ nxt_state <= exec4;
+ end if;
+ ----------------------------------------------
+ when ic_lbsx_rn_rb_disp =>
+ if ack_sync = '1' then
+ mdri_hl_zse_sign <= '1';
+ if mar0 = '0' then
+ adin_mux_sel <= adin_mux_sel_mdri_high;
+ else
+ adin_mux_sel <= adin_mux_sel_mdri_low;
+ end if;
+ rf_adwe <= '1';
+ --
+ nxt_state <= int_chk;
+ else
+ mdri_ce <= '1';
+ if mar0 = '0' then
+ SEL_O <= "10";
+ else
+ SEL_O <= "01";
+ end if;
+ STB_O <= '1'; CYC_O <= '1'; D_CYC_O <= '1';
+ --
+ nxt_state <= exec4;
+ end if;
+ ----------------------------------------------
+ when ic_sb_rn_rb_disp =>
+ mdro_oe <= '1';
+ -- write byte
+ if mar0 = '0' then
+ SEL_O <= "10";
+ else
+ SEL_O <= "01";
+ end if;
+ STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
+ --
+ nxt_state <= exec5;
+ ----------------------------------------------
+ when ic_int | ic_into =>
+ if ack_sync = '1' then
+ -- pc = ext(ir(3..0))
+ intno_mux_sel <= intno_mux_sel_ir;
+ pcin_mux_sel <= pcin_mux_sel_intno;
+ pc_ce <= '1';
+ --
+ nxt_state <= int_chk;
+ else
+ mdro_oe <= '1';
+ -- write word
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
+ --
+ nxt_state <= exec4;
+ end if;
+ ----------------------------------------------
+ when ic_iret =>
+ if ack_sync = '1' then
+ -- flags = mdri
+ coszin_mux_sel <= coszin_mux_sel_mdri;
+ flags_ce <= '1';
+ flags_cfce <= '1';
+ flags_ifce <= '1';
+ --
+ nxt_state <= int_chk;
+ else
+ mdro_oe <= '1';
+ -- write byte
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
+ --
+ nxt_state <= exec4;
+ end if;
+ ----------------------------------------------
+ when others =>
+ null;
+ ----------------------------------------------
+ end case;
+--///////////////////////////////////////
+ when exec5 =>
+ case cur_ic is
+ when ic_sb_rn_rb_disp =>
+ if ack_sync = '1' then
+ nxt_state <= int_chk;
+ else
+ mdro_oe <= '1';
+ -- write byte
+ if mar0 = '0' then
+ SEL_O <= "10";
+ else
+ SEL_O <= "01";
+ end if;
+ STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
+ --
+ nxt_state <= exec5;
+ end if;
+ when others =>
+ null;
+ end case;
+--///////////////////////////////////////
+ when int_chk =>
+ if int_flag = '1' then
+ if intr_sync = '1' then
+ -- read vector no.
+ SEL_O <= "10"; STB_O <= '1'; CYC_O <= '1'; INTA_CYC_O <= '1';
+ -- prepare intr
+ intr_ce <= '1';
+ --
+ nxt_state <= int0;
+ else
+ nxt_state <= fetch0;
+ end if;
+ else
+ nxt_state <= fetch0;
+ end if;
+--///////////////////////////////////////
+ when int0 =>
+ if ack_sync = '1' then
+ if sp0 = '0' then
+ -- mar = old sp - 2
+ alua_mux_sel <= alua_mux_sel_sp;
+ alub_mux_sel <= alub_mux_sel_2;
+ asopsel <= asopsel_sub;
+ marin_mux_sel <= marin_mux_sel_aluout;
+ mar_ce <= '1';
+ -- sp = old sp - 2
+ spin_mux_sel <= spin_mux_sel_aluout;
+ sp_ce <= '1';
+ -- mdro = flags
+ mdroin_mux_sel <= mdroin_mux_sel_flags;
+ mdro_ce <= '1';
+ --! mdro_oe <= '1';
+ --
+ nxt_state <= int1;
+ else
+ -- mdro = intno
+ intno_mux_sel <= intno_mux_sel_intr;
+ mdroin_mux_sel <= mdroin_mux_sel_intno;
+ mdro_ce <= '1';
+ --! mdro_oe <= '1';
+ -- dfh = sp
+ dfh_ce <= '1';
+ --
+ nxt_state <= df0;
+ end if;
+ else
+ -- try reading vector number
+ SEL_O <= "10"; STB_O <= '1'; CYC_O <= '1'; INTA_CYC_O <= '1';
+ --
+ intr_ce <= '1';
+ --
+ nxt_state <= int0;
+ end if;
+--///////////////////////////////////////
+ when int1 =>
+ -- write flags
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
+ --
+ mdro_oe <= '1';
+ --
+ nxt_state <= int2;
+--///////////////////////////////////////
+ when int2 =>
+ if ack_sync = '1' then
+ alua_mux_sel <= alua_mux_sel_sp;
+ alub_mux_sel <= alub_mux_sel_2;
+ asopsel <= asopsel_sub;
+ -- mar = old sp - 2
+ marin_mux_sel <= marin_mux_sel_aluout;
+ mar_ce <= '1';
+ -- sp = old sp - 2
+ spin_mux_sel <= spin_mux_sel_aluout;
+ sp_ce <= '1';
+ -- mdro = pc
+ mdroin_mux_sel <= mdroin_mux_sel_pc;
+ mdro_ce <= '1';
+ --! mdro_oe <= '1';
+ --
+ nxt_state <= int3;
+ else
+ -- try writing data word (flags)
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
+ --
+ mdro_oe <= '1';
+ --
+ nxt_state <= int2;
+ end if;
+--///////////////////////////////////////
+ when int3 =>
+ -- write pc
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
+ --
+ mdro_oe <= '1';
+ --
+ nxt_state <= int4;
+--///////////////////////////////////////
+ when int4 =>
+ if ack_sync = '1' then
+ intno_mux_sel <= intno_mux_sel_intr;
+ pcin_mux_sel <= pcin_mux_sel_intno;
+ pc_ce <= '1';
+ --
+ nxt_state <= fetch0;
+ else
+ -- writing pc
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
+ --
+ mdro_oe <= '1';
+ --
+ nxt_state <= int4;
+ end if;
+--///////////////////////////////////////
+ when invalid0 =>
+ if sp0= '0' then
+ -- push flag
+ alua_mux_sel <= alua_mux_sel_sp;
+ alub_mux_sel <= alub_mux_sel_2;
+ asopsel <= asopsel_sub;
+ --
+ spin_mux_sel <= spin_mux_sel_aluout;
+ sp_ce <= '1';
+ --
+ marin_mux_sel <= marin_mux_sel_aluout;
+ mar_ce <= '1';
+ --
+ mdroin_mux_sel <= mdroin_mux_sel_flags;
+ mdro_ce <= '1';
+ --! mdro_oe <= '1';
+ --
+ nxt_state <= invalid1;
+ else
+ -- in case of df
+ -- move the vector no to
+ intno_mux_sel <= intno_mux_sel_invalid;
+ mdroin_mux_sel <= mdroin_mux_sel_intno;
+ mdro_ce <= '1';
+ --! mdro_oe <= '1';
+ --
+ dfh_ce <= '1';
+ --
+ nxt_state <= df0;
+ end if;
+--///////////////////////////////////////
+ when invalid1 =>
+ -- write flags
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
+ --
+ mdro_oe <= '1';
+ --
+ nxt_state <= invalid2;
+--///////////////////////////////////////
+ when invalid2 =>
+ if ack_sync = '1' then
+ alua_mux_sel <= alua_mux_sel_sp;
+ alub_mux_sel <= alub_mux_sel_2;
+ asopsel <= asopsel_sub;
+ -- mar = old sp - 2
+ marin_mux_sel <= marin_mux_sel_aluout;
+ mar_ce <= '1';
+ -- sp = old sp - 2
+ spin_mux_sel <= spin_mux_sel_aluout;
+ sp_ce <= '1';
+ -- mdro = pc
+ mdroin_mux_sel <= mdroin_mux_sel_pc;
+ mdro_ce <= '1';
+ --! mdro_oe <= '1';
+ --
+ nxt_state <= invalid3;
+ else
+ -- try writing data word (flags)
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
+ --
+ mdro_oe <= '1';
+ --
+ nxt_state <= invalid2;
+ end if;
+--///////////////////////////////////////
+ when invalid3 =>
+ -- write pc
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
+ --
+ mdro_oe <= '1';
+ --
+ nxt_state <= invalid4;
+--///////////////////////////////////////
+ when invalid4 =>
+ if ack_sync = '1' then
+ intno_mux_sel <= intno_mux_sel_intr;
+ pcin_mux_sel <= pcin_mux_sel_intno;
+ pc_ce <= '1';
+ --
+ nxt_state <= fetch0;
+ else
+ -- writing pc
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
+ --
+ mdro_oe <= '1';
+ --
+ nxt_state <= invalid4;
+ end if;
+--///////////////////////////////////////
+ when align0 =>
+ if sp0= '0' then
+ -- push flag
+ alua_mux_sel <= alua_mux_sel_sp;
+ alub_mux_sel <= alub_mux_sel_2;
+ asopsel <= asopsel_sub;
+ --
+ spin_mux_sel <= spin_mux_sel_aluout;
+ sp_ce <= '1';
+ --
+ marin_mux_sel <= marin_mux_sel_aluout;
+ mar_ce <= '1';
+ --
+ mdroin_mux_sel <= mdroin_mux_sel_flags;
+ mdro_ce <= '1';
+ --! mdro_oe <= '1';
+ --
+ nxt_state <= align1;
+ else
+ -- in case of df
+ -- move the vector no to
+ intno_mux_sel <= intno_mux_sel_align;
+ mdroin_mux_sel <= mdroin_mux_sel_intno;
+ mdro_ce <= '1';
+ --! mdro_oe <= '1';
+ --
+ dfh_ce <= '1';
+ --
+ nxt_state <= df0;
+ end if;
+--///////////////////////////////////////
+ when align1 =>
+ -- write flags
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
+ --
+ mdro_oe <= '1';
+ --
+ nxt_state <= align2;
+--///////////////////////////////////////
+ when align2 =>
+ if ack_sync = '1' then
+ alua_mux_sel <= alua_mux_sel_sp;
+ alub_mux_sel <= alub_mux_sel_2;
+ asopsel <= asopsel_sub;
+ -- mar = old sp - 2
+ marin_mux_sel <= marin_mux_sel_aluout;
+ mar_ce <= '1';
+ -- sp = old sp - 2
+ spin_mux_sel <= spin_mux_sel_aluout;
+ sp_ce <= '1';
+ -- mdro = pc
+ mdroin_mux_sel <= mdroin_mux_sel_pc;
+ mdro_ce <= '1';
+ --! mdro_oe <= '1';
+ --
+ nxt_state <= align3;
+ else
+ -- try writing data word (flags)
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
+ --
+ mdro_oe <= '1';
+ --
+ nxt_state <= align2;
+ end if;
+--///////////////////////////////////////
+ when align3 =>
+ -- write pc
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
+ --
+ mdro_oe <= '1';
+ --
+ nxt_state <= align4;
+--///////////////////////////////////////
+ when align4 =>
+ if ack_sync = '1' then
+ intno_mux_sel <= intno_mux_sel_intr;
+ pcin_mux_sel <= pcin_mux_sel_intno;
+ pc_ce <= '1';
+ --
+ nxt_state <= fetch0;
+ else
+ -- writing pc
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
+ --
+ mdro_oe <= '1';
+ --
+ nxt_state <= align4;
+ end if;
+--///////////////////////////////////////
+ when stkerr0 =>
+ sp_pre <= '1';
+ nxt_state <= stkerr1;
+--//////////////////////////////////////
+ when stkerr1 =>
+ alua_mux_sel <= alua_mux_sel_sp;
+ alub_mux_sel <= alub_mux_sel_2;
+ asopsel <= asopsel_sub;
+ --
+ marin_mux_sel <= marin_mux_sel_aluout;
+ mar_ce <= '1';
+ --
+ spin_mux_sel <= spin_mux_sel_aluout;
+ sp_ce <= '1';
+ --
+ mdroin_mux_sel <= mdroin_mux_sel_dfh;
+ mdro_ce <= '1';
+ --! mdro_oe <= '1';
+ --
+ nxt_state <= stkerr2;
+--///////////////////////////////////////
+ when stkerr2 =>
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
+ mdro_oe <= '1';
+ nxt_state <= stkerr3;
+--///////////////////////////////////////
+ when stkerr3 =>
+ if ack_sync ='1' then
+ alua_mux_sel <= alua_mux_sel_sp;
+ alub_mux_sel <= alub_mux_sel_2;
+ asopsel <= asopsel_sub;
+ --
+ marin_mux_sel <= marin_mux_sel_aluout;
+ mar_ce <= '1';
+ --
+ spin_mux_sel <= spin_mux_sel_aluout;
+ sp_ce <= '1';
+ --
+ mdroin_mux_sel <= mdroin_mux_sel_flags;
+ mdro_ce <= '1';
+ --! mdro_oe <= '1';
+ --
+ nxt_state <= stkerr4;
+ else
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
+ mdro_oe <= '1';
+ nxt_state <= stkerr3;
+ end if;
+--///////////////////////////////////////
+ when stkerr4 =>
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
+ mdro_oe <= '1';
+ nxt_state <= stkerr5;
+--///////////////////////////////////////
+ when stkerr5 =>
+ if ack_sync ='1' then
+ alua_mux_sel <= alua_mux_sel_sp;
+ alub_mux_sel <= alub_mux_sel_2;
+ asopsel <= asopsel_sub;
+ --
+ marin_mux_sel <= marin_mux_sel_aluout;
+ mar_ce <= '1';
+ --
+ spin_mux_sel <= spin_mux_sel_aluout;
+ sp_ce <= '1';
+ --
+ mdroin_mux_sel <= mdroin_mux_sel_pc;
+ mdro_ce <= '1';
+ --! mdro_oe <= '1';
+ --
+ nxt_state <= stkerr6;
+ else
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
+ mdro_oe <= '1';
+ nxt_state <= stkerr5;
+ end if;
+--///////////////////////////////////////
+ when stkerr6 =>
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
+ mdro_oe <= '1';
+ nxt_state <= stkerr7;
+--///////////////////////////////////////
+ when stkerr7 =>
+ if ack_sync = '1' then
+ intno_mux_sel <= intno_mux_sel_df;
+ pcin_mux_sel <= pcin_mux_sel_intno;
+ pc_ce <= '1';
+ --
+ nxt_state <= fetch0;
+ else
+ -- writing pc
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
+ --
+ mdro_oe <= '1';
+ --
+ nxt_state <= stkerr7;
+ end if;
+--///////////////////////////////////////
+ when df0 =>
+ sp_pre <= '1';
+ nxt_state <= df1;
+--//////////////////////////////////////
+ when df1 =>
+ alua_mux_sel <= alua_mux_sel_sp;
+ alub_mux_sel <= alub_mux_sel_2;
+ asopsel <= asopsel_sub;
+ --
+ marin_mux_sel <= marin_mux_sel_aluout;
+ mar_ce <= '1';
+ --
+ spin_mux_sel <= spin_mux_sel_aluout;
+ sp_ce <= '1';
+ --
+ nxt_state <= df2;
+--//////////////////////////////////////
+ when df2 =>
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
+ mdro_oe <= '1';
+ nxt_state <= df3;
+--//////////////////////////////////////
+ when df3 =>
+ if ack_sync ='1' then
+ alua_mux_sel <= alua_mux_sel_sp;
+ alub_mux_sel <= alub_mux_sel_2;
+ asopsel <= asopsel_sub;
+ --
+ marin_mux_sel <= marin_mux_sel_aluout;
+ mar_ce <= '1';
+ --
+ spin_mux_sel <= spin_mux_sel_aluout;
+ sp_ce <= '1';
+ --
+ mdroin_mux_sel <= mdroin_mux_sel_dfh;
+ mdro_ce <= '1';
+ --! mdro_oe <= '1';
+ --
+ nxt_state <= df4;
+ else
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
+ mdro_oe <= '1';
+ nxt_state <= df3;
+ end if;
+--///////////////////////////////////////
+ when df4 =>
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
+ mdro_oe <= '1';
+ nxt_state <= df5;
+--///////////////////////////////////////
+ when df5 =>
+ if ack_sync ='1' then
+ alua_mux_sel <= alua_mux_sel_sp;
+ alub_mux_sel <= alub_mux_sel_2;
+ asopsel <= asopsel_sub;
+ --
+ marin_mux_sel <= marin_mux_sel_aluout;
+ mar_ce <= '1';
+ --
+ spin_mux_sel <= spin_mux_sel_aluout;
+ sp_ce <= '1';
+ --
+ mdroin_mux_sel <= mdroin_mux_sel_flags;
+ mdro_ce <= '1';
+ --! mdro_oe <= '1';
+ --
+ nxt_state <= df6;
+ else
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
+ mdro_oe <= '1';
+ nxt_state <= df5;
+ end if;
+--///////////////////////////////////////
+ when df6 =>
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
+ mdro_oe <= '1';
+ nxt_state <= df7;
+--///////////////////////////////////////
+ when df7 =>
+ if ack_sync ='1' then
+ alua_mux_sel <= alua_mux_sel_sp;
+ alub_mux_sel <= alub_mux_sel_2;
+ asopsel <= asopsel_sub;
+ --
+ marin_mux_sel <= marin_mux_sel_aluout;
+ mar_ce <= '1';
+ --
+ spin_mux_sel <= spin_mux_sel_aluout;
+ sp_ce <= '1';
+ --
+ mdroin_mux_sel <= mdroin_mux_sel_pc;
+ mdro_ce <= '1';
+ --! mdro_oe <= '1';
+ --
+ nxt_state <= df8;
+ else
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
+ mdro_oe <= '1';
+ nxt_state <= df7;
+ end if;
+--///////////////////////////////////////
+ when df8 =>
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
+ mdro_oe <= '1';
+ nxt_state <= df9;
+--///////////////////////////////////////
+ when df9 =>
+ if ack_sync = '1' then
+ intno_mux_sel <= intno_mux_sel_df;
+ pcin_mux_sel <= pcin_mux_sel_intno;
+ pc_ce <= '1';
+ --
+ nxt_state <= fetch0;
+ else
+ -- writing pc
+ SEL_O <= "11"; STB_O <= '1'; CYC_O <= '1'; WE_O <= '1'; D_CYC_O <= '1';
+ --
+ mdro_oe <= '1';
+ --
+ nxt_state <= df9;
+ end if;
+--///////////////////////////////////////
+ when halted =>
+ if intr_sync = '1' then
+ -- read vector no.
+ SEL_O <= "10"; STB_O <= '1'; CYC_O <= '1'; INTA_CYC_O <= '1';
+ -- prepare intr
+ intr_ce <= '1';
+ --
+ nxt_state <= int0;
+ else
+ nxt_state <= halted;
+ end if;
+--//////////////////////////////////////
+ end case;
+ end process;
+ -- since alu & shifter are not used simultanously...
+ aopsel <= asopsel(2 downto 0);
+ sopsel <= asopsel(2 downto 0);
+ asresult_mux_sel <= asopsel(3);
+end rtl;
\ No newline at end of file
Index: trunk/impl0/rtl/vhdl/con_pkg.vhd
===================================================================
--- trunk/impl0/rtl/vhdl/con_pkg.vhd (nonexistent)
+++ trunk/impl0/rtl/vhdl/con_pkg.vhd (revision 2)
@@ -0,0 +1,266 @@
+--------------------------------------------------------------
+-- con_pkg.vhd
+--------------------------------------------------------------
+-- project: HPC-16 Microprocessor
+--
+-- usage: constants, component and type declarations for control unit(fsm)
+--
+-- dependency: sync.vhd
+--
+---------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+
+package con_pkg is
+
+-- intruction catagories
+ constant mov_rn_rm : std_logic_vector(7 downto 0) := b"00000_001";
+ constant mov_sp_rm : std_logic_vector(7 downto 0) := b"00000_010";
+ constant mov_rn_sp : std_logic_vector(7 downto 0) := b"00000_100";
+
+ constant ld_rn_rb : std_logic_vector(7 downto 0) := b"00001_000";
+ constant ld_rn_rb_disp : std_logic_vector(7 downto 0) := b"00001_001";
+ constant ld_rn_sp : std_logic_vector(7 downto 0) := b"00001_010";
+ constant ld_rn_sp_disp : std_logic_vector(7 downto 0) := b"00001_100";
+
+ constant st_rn_rb : std_logic_vector(7 downto 0) := b"00010_000";
+ constant st_rn_rb_disp : std_logic_vector(7 downto 0) := b"00010_001";
+ constant st_rn_sp : std_logic_vector(7 downto 0) := b"00010_010";
+ constant st_rn_sp_disp : std_logic_vector(7 downto 0) := b"00010_100";
+
+ constant lbzx_rn_rb : std_logic_vector(7 downto 0) := b"00011_000";
+ constant lbzx_rn_rb_disp : std_logic_vector(7 downto 0) := b"00011_100";
+ constant lbsx_rn_rb : std_logic_vector(7 downto 0) := b"00011_001";
+ constant lbsx_rn_rb_disp : std_logic_vector(7 downto 0) := b"00011_101";
+
+ constant sb_rn_rb : std_logic_vector(7 downto 0) := b"00100_001";
+ constant sb_rn_rb_disp : std_logic_vector(7 downto 0) := b"00100_010";
+
+ constant sing_dec : std_logic_vector(7 downto 0) := b"00101_000";
+ constant sing_inc : std_logic_vector(7 downto 0) := b"00101_001";
+
+ constant alur : std_logic_vector(4 downto 0) := "00110";
+
+ constant shiftr : std_logic_vector(4 downto 0) := "00111";
+
+ constant cmp_cmp : std_logic_vector(7 downto 0) := b"01000_000";
+ constant cmp_tst : std_logic_vector(7 downto 0) := b"01000_101";
+
+ constant li_rn : std_logic_vector(7 downto 0) := b"01001_001";
+ constant li_sp : std_logic_vector(7 downto 0) := b"01001_010";
+
+ constant alui : std_logic_vector(4 downto 0) := "01010";
+
+ constant shifti : std_logic_vector(4 downto 0) := "01011";
+
+ constant cmpi_cmp : std_logic_vector(7 downto 0) := b"01100_000";
+ constant cmpi_tst : std_logic_vector(7 downto 0) := b"01100_101";
+
+ constant alusp_sub : std_logic_vector(7 downto 0) := b"01101_000";
+ constant alusp_add : std_logic_vector(7 downto 0) := b"01101_001";
+
+ constant stk_pushr : std_logic_vector(7 downto 0) := b"01110_000";
+ constant stk_pushf : std_logic_vector(7 downto 0) := b"01110_001";
+ constant stk_popr : std_logic_vector(7 downto 0) := b"01110_100";
+ constant stk_popf : std_logic_vector(7 downto 0) := b"01110_101";
+
+ constant acall : std_logic_vector(7 downto 0) := b"01111_001";
+
+ constant lcall : std_logic_vector(7 downto 0) := b"01111_010";
+
+ constant scall : std_logic_vector(4 downto 0) := "10000";
+
+ constant ret : std_logic_vector(4 downto 0) := "10001";
+
+ constant int : std_logic_vector(4 downto 0) := "10010";
+
+ constant into : std_logic_vector(4 downto 0) := "10011";
+
+ constant iret : std_logic_vector(4 downto 0) := "10100";
+
+ constant ajmp : std_logic_vector(7 downto 0) := b"10101_001";
+
+ constant ljmp : std_logic_vector(7 downto 0) := b"10101_010";
+
+ constant sjmp : std_logic_vector(4 downto 0) := "10110";
+
+ constant jcc : std_logic_vector(4 downto 0) := "10111";
+
+ constant fop_clc : std_logic_vector(7 downto 0) := b"11000_000";
+ constant fop_stc : std_logic_vector(7 downto 0) := b"11000_001";
+ constant fop_cmc : std_logic_vector(7 downto 0) := b"11000_010";
+ constant fop_cli : std_logic_vector(7 downto 0) := b"11000_100";
+ constant fop_sti : std_logic_vector(7 downto 0) := b"11000_101";
+
+ constant nop : std_logic_vector(4 downto 0) := "11110";
+
+ constant hlt : std_logic_vector(4 downto 0) := "11111";
+
+ -- subop/subtype field
+
+ constant a_sub : std_logic_vector(2 downto 0) := "000";
+ constant a_add : std_logic_vector(2 downto 0) := "001";
+ constant a_sbb : std_logic_vector(2 downto 0) := "010";
+ constant a_adc : std_logic_vector(2 downto 0) := "011";
+ constant a_not : std_logic_vector(2 downto 0) := "100";
+ constant a_and : std_logic_vector(2 downto 0) := "101";
+ constant a_or : std_logic_vector(2 downto 0) := "110";
+ constant a_xor : std_logic_vector(2 downto 0) := "111";
+
+ constant s_sll : std_logic_vector(2 downto 0) := "000";
+ constant s_slr : std_logic_vector(2 downto 0) := "001";
+ constant s_sal : std_logic_vector(2 downto 0) := "010";
+ constant s_sar : std_logic_vector(2 downto 0) := "011";
+ constant s_rol : std_logic_vector(2 downto 0) := "100";
+ constant s_ror : std_logic_vector(2 downto 0) := "101";
+ constant s_rcl : std_logic_vector(2 downto 0) := "110";
+ constant s_rcr : std_logic_vector(2 downto 0) := "111";
+
+ -- alu operations
+ constant asopsel_sub : std_logic_vector(3 downto 0) := "0000";
+ constant asopsel_add : std_logic_vector(3 downto 0) := "0001";
+ constant asopsel_sbb : std_logic_vector(3 downto 0) := "0010";
+ constant asopsel_adc : std_logic_vector(3 downto 0) := "0011";
+ constant asopsel_not : std_logic_vector(3 downto 0) := "0100";
+ constant asopsel_and : std_logic_vector(3 downto 0) := "0101";
+ constant asopsel_or : std_logic_vector(3 downto 0) := "0110";
+ constant asopsel_xor : std_logic_vector(3 downto 0) := "0111";
+
+ -- shifter operations
+ constant asopsel_sll : std_logic_vector(3 downto 0) := "1000";
+ constant asopsel_slr : std_logic_vector(3 downto 0) := "1001";
+ constant asopsel_sal : std_logic_vector(3 downto 0) := "1010";
+ constant asopsel_sar : std_logic_vector(3 downto 0) := "1011";
+ constant asopsel_rol : std_logic_vector(3 downto 0) := "1100";
+ constant asopsel_ror : std_logic_vector(3 downto 0) := "1101";
+ constant asopsel_rcl : std_logic_vector(3 downto 0) := "1110";
+ constant asopsel_rcr : std_logic_vector(3 downto 0) := "1111";
+
+ constant intno_mux_sel_invalid : std_logic_vector(2 downto 0) := "000";
+ constant intno_mux_sel_align : std_logic_vector(2 downto 0) := "001";
+ constant intno_mux_sel_stk : std_logic_vector(2 downto 0) := "010";
+ constant intno_mux_sel_df : std_logic_vector(2 downto 0) := "011";
+ constant intno_mux_sel_ir : std_logic_vector(2 downto 0) := "100";
+ constant intno_mux_sel_intr : std_logic_vector(2 downto 0) := "101";
+
+ constant adin_mux_sel_tr2 : std_logic_vector(2 downto 0) := "000";
+ constant adin_mux_sel_tr5 : std_logic_vector(2 downto 0) := "001";
+ constant adin_mux_sel_sp : std_logic_vector(2 downto 0) := "010";
+ constant adin_mux_sel_mdri : std_logic_vector(2 downto 0) := "011";
+ constant adin_mux_sel_mdri_high : std_logic_vector(2 downto 0) := "100";
+ constant adin_mux_sel_mdri_low : std_logic_vector(2 downto 0) := "101";
+
+ constant pcin_mux_sel_aluout : std_logic_vector(1 downto 0) := "00";
+ constant pcin_mux_sel_intno : std_logic_vector(1 downto 0) := "01";
+ constant pcin_mux_sel_mdri : std_logic_vector(1 downto 0) := "10";
+
+ constant spin_mux_sel_aluout : std_logic := '0';
+ constant spin_mux_sel_mdri : std_logic := '1';
+
+ constant alua_mux_sel_pc : std_logic_vector(1 downto 0) := "00";
+ constant alua_mux_sel_sp : std_logic_vector(1 downto 0) := "01";
+ constant alua_mux_sel_tr1 : std_logic_vector(1 downto 0) := "10";
+ constant alua_mux_sel_tr2 : std_logic_vector(1 downto 0) := "11";
+
+ constant alub_mux_sel_tr2 : std_logic_vector(2 downto 0) := "000";
+ constant alub_mux_sel_2 : std_logic_vector(2 downto 0) := "001";
+ constant alub_mux_sel_1 : std_logic_vector(2 downto 0) := "010";
+ constant alub_mux_sel_0 : std_logic_vector(2 downto 0) := "011";
+ constant alub_mux_sel_tr3 : std_logic_vector(2 downto 0) := "100";
+ constant alub_mux_sel_tr4 : std_logic_vector(2 downto 0) := "101";
+ constant alub_mux_sel_mdri : std_logic_vector(2 downto 0) := "110";
+
+ constant sbin_mux_sel_tr2 : std_logic := '0';
+ constant sbin_mux_sel_ir : std_logic := '1';
+
+ constant coszin_mux_sel_asresult : std_logic := '0';
+ constant coszin_mux_sel_mdri : std_logic := '1';
+
+ constant marin_mux_sel_pc : std_logic_vector(1 downto 0) := "00";
+ constant marin_mux_sel_aluout : std_logic_vector(1 downto 0) := "01";
+ constant marin_mux_sel_sp : std_logic_vector(1 downto 0) := "10";
+
+ constant mdroin_mux_sel_pc : std_logic_vector(2 downto 0) := "000";
+ constant mdroin_mux_sel_tr1 : std_logic_vector(2 downto 0) := "001";
+ constant mdroin_mux_sel_flags : std_logic_vector(2 downto 0) := "010";
+ constant mdroin_mux_sel_dfh : std_logic_vector(2 downto 0) := "011";
+ constant mdroin_mux_sel_intno : std_logic_vector(2 downto 0) := "100";
+ constant mdroin_mux_sel_tr1_loweven : std_logic_vector(2 downto 0) := "101";
+ constant mdroin_mux_sel_tr1_lowodd : std_logic_vector(2 downto 0) := "110";
+
+ type ic is (
+ ic_mov_rn_rm, ic_mov_sp_rm, ic_mov_rn_sp,
+
+ ic_ld_rn_rb, ic_ld_rn_rb_disp, ic_ld_rn_sp, ic_ld_rn_sp_disp,
+
+ ic_st_rn_rb, ic_st_rn_rb_disp, ic_st_rn_sp, ic_st_rn_sp_disp,
+
+ ic_lbzx_rn_rb, ic_lbzx_rn_rb_disp, ic_lbsx_rn_rb, ic_lbsx_rn_rb_disp,
+
+ ic_sb_rn_rb, ic_sb_rn_rb_disp,
+
+ ic_sing_dec, ic_sing_inc,
+
+ ic_alur,
+
+ ic_shiftr,
+
+ ic_cmp_cmp, ic_cmp_tst,
+
+ ic_li_rn, ic_li_sp,
+
+ ic_alui,
+
+ ic_shifti,
+
+ ic_cmpi_cmp, ic_cmpi_tst,
+
+ ic_alusp_sub, ic_alusp_add,
+
+ ic_stk_pushr, ic_stk_pushf, ic_stk_popr, ic_stk_popf,
+
+ ic_acall, ic_lcall, ic_scall,
+
+ ic_ret,
+
+ ic_int,
+
+ ic_into,
+
+ ic_iret,
+
+ ic_ajmp, ic_ljmp, ic_sjmp,
+
+ ic_jcc,
+
+ ic_fop_clc, ic_fop_stc, ic_fop_cmc, ic_fop_cli, ic_fop_sti,
+
+ ic_nop,
+
+ ic_hlt,
+
+ ic_invalid);
+
+ type state is (
+ reset,
+ fetch0, fetch1, fetch2,
+ exec0, exec1, exec2, exec3, exec4, exec5,
+ int_chk,
+ int0, int1, int2, int3, int4,
+ align0, align1, align2, align3, align4,
+ stkerr0, stkerr1, stkerr2, stkerr3, stkerr4, stkerr5, stkerr6, stkerr7,
+ invalid0, invalid1, invalid2, invalid3, invalid4,
+ df0, df1, df2, df3, df4, df5, df6, df7, df8, df9,
+ halted
+ );
+
+ component sync is
+ port
+ (
+ d : in std_logic;
+ clk : in std_logic;
+ q : out std_logic
+ );
+ end component;
+
+end package;
Index: trunk/impl0/rtl/vhdl/alu.vhd
===================================================================
--- trunk/impl0/rtl/vhdl/alu.vhd (nonexistent)
+++ trunk/impl0/rtl/vhdl/alu.vhd (revision 2)
@@ -0,0 +1,119 @@
+--------------------------------------------------------------
+-- alu.vhd
+--------------------------------------------------------------
+-- project: HPC-16 Microprocessor
+--
+-- usage: ALU of microprocessor
+--
+-- dependency: log.vhd, arith.sch
+--
+-- Author: M. Umair Siddiqui (umairsiddiqui@opencores.org)
+---------------------------------------------------------------
+------------------------------------------------------------------------------------
+-- --
+-- Copyright (c) 2005, M. Umair Siddiqui all rights reserved --
+-- --
+-- This file is part of HPC-16. --
+-- --
+-- HPC-16 is free software; you can redistribute it and/or modify --
+-- it under the terms of the GNU Lesser General Public License as published by --
+-- the Free Software Foundation; either version 2.1 of the License, or --
+-- (at your option) any later version. --
+-- --
+-- HPC-16 is distributed in the hope that it will be useful, --
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
+-- GNU Lesser General Public License for more details. --
+-- --
+-- You should have received a copy of the GNU Lesser General Public License --
+-- along with HPC-16; if not, write to the Free Software --
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
+-- --
+------------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+--Opsel_in--|--ALU Operation--
+--000-------|--sub------------
+--001-------|--add------------
+--010-------|--sbb------------
+--011-------|--adc------------
+--100-------|--not------------
+--101-------|--and------------
+--110-------|--or-------------
+--111-------|--xor------------
+
+entity alu is
+ port(
+ a : in std_logic_vector(15 downto 0);
+ b : in std_logic_vector(15 downto 0);
+ opsel : in std_logic_vector(2 downto 0);
+ c_in : in std_logic;
+ result: out std_logic_vector(15 downto 0);
+ c_out: out std_logic;
+ ofl_out: out std_logic
+ );
+end alu;
+
+architecture struct of alu is
+ COMPONENT arith
+ PORT( c_out : OUT STD_LOGIC;
+ ofl_out : OUT STD_LOGIC;
+ s0 : IN STD_LOGIC;
+ c_in : IN STD_LOGIC;
+ s1 : IN STD_LOGIC;
+ a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+ b : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+ result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0));
+ END COMPONENT;
+
+ component log
+ port ( a : in std_logic_vector(15 downto 0);
+ b : in std_logic_vector(15 downto 0);
+ s0 : in std_logic;
+ s1 : in std_logic;
+ result : out std_logic_vector(15 downto 0)
+ );
+ end component;
+
+ signal cout_temp : std_logic;
+ signal ofl_temp : std_logic;
+ signal result_arith : std_logic_vector(15 downto 0);
+ signal result_log : std_logic_vector(15 downto 0);
+ signal result_temp : std_logic_vector(15 downto 0);
+
+begin
+
+ u1 : arith
+ PORT map ( c_out => cout_temp,
+ ofl_out => ofl_temp,
+ s0 => opsel(0),
+ c_in => c_in,
+ s1 => opsel(1),
+ a => a,
+ b => b,
+ result => result_arith
+ );
+
+
+ u2 : log
+ port map ( a => a,
+ b => b,
+ s0 => opsel(0),
+ s1 => opsel(1),
+ result => result_log
+ );
+
+
+ result_temp <= result_arith when opsel(2) = '0' else
+ result_log;
+
+ result <= result_temp;
+
+ c_out <= cout_temp when opsel(2) = '0' else
+ '0';
+
+ ofl_out <= ofl_temp when opsel(2) = '0' else
+ '0';
+
+end struct;
\ No newline at end of file
Index: trunk/impl0/rtl/vhdl/log.vhd
===================================================================
--- trunk/impl0/rtl/vhdl/log.vhd (nonexistent)
+++ trunk/impl0/rtl/vhdl/log.vhd (revision 2)
@@ -0,0 +1,55 @@
+--------------------------------------------------------------
+-- log.vhd
+--------------------------------------------------------------
+-- project: HPC-16 Microprocessor
+--
+-- usage: component of ALU, performs logical operations
+--
+-- dependency: none
+--
+-- Author: M. Umair Siddiqui (umairsiddiqui@opencores.org)
+---------------------------------------------------------------
+------------------------------------------------------------------------------------
+-- --
+-- Copyright (c) 2005, M. Umair Siddiqui all rights reserved --
+-- --
+-- This file is part of HPC-16. --
+-- --
+-- HPC-16 is free software; you can redistribute it and/or modify --
+-- it under the terms of the GNU Lesser General Public License as published by --
+-- the Free Software Foundation; either version 2.1 of the License, or --
+-- (at your option) any later version. --
+-- --
+-- HPC-16 is distributed in the hope that it will be useful, --
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
+-- GNU Lesser General Public License for more details. --
+-- --
+-- You should have received a copy of the GNU Lesser General Public License --
+-- along with HPC-16; if not, write to the Free Software --
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
+-- --
+------------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity log is
+ port ( a : in std_logic_vector(15 downto 0);
+ b : in std_logic_vector(15 downto 0);
+ s0 : in std_logic;
+ s1 : in std_logic;
+ result : out std_logic_vector(15 downto 0)
+ );
+end log;
+
+architecture dataflow of log is
+ signal sel : std_logic_vector(1 downto 0);
+begin
+ sel <= s1 & s0;
+ result <= not a when sel = "00" else
+ a and b when sel = "01" else
+ a or b when sel = "10" else
+ a xor b;
+end dataflow;
Index: trunk/impl0/rtl/vhdl/arith.sch
===================================================================
--- trunk/impl0/rtl/vhdl/arith.sch (nonexistent)
+++ trunk/impl0/rtl/vhdl/arith.sch (revision 2)
@@ -0,0 +1,238 @@
+VERSION 6
+BEGIN SCHEMATIC
+ BEGIN ATTR DeviceFamilyName "spartan3"
+ DELETE all:0
+ EDITNAME all:0
+ EDITTRAIT all:0
+ END ATTR
+ BEGIN NETLIST
+ SIGNAL c_out
+ SIGNAL ofl_out
+ SIGNAL XLXN_14
+ SIGNAL XLXN_15
+ SIGNAL s0
+ SIGNAL XLXN_18
+ SIGNAL zero_i
+ SIGNAL XLXN_24
+ SIGNAL c_in
+ SIGNAL XLXN_29
+ SIGNAL XLXN_30
+ SIGNAL s1
+ SIGNAL a(15:0)
+ SIGNAL b(15:0)
+ SIGNAL XLXN_35
+ SIGNAL result(15:0)
+ PORT Output c_out
+ PORT Output ofl_out
+ PORT Input s0
+ PORT Input c_in
+ PORT Input s1
+ PORT Input a(15:0)
+ PORT Input b(15:0)
+ PORT Output result(15:0)
+ BEGIN BLOCKDEF adsu16
+ TIMESTAMP 2001 2 2 12 35 41
+ LINE N 240 -64 384 -64
+ LINE N 240 -124 240 -64
+ RECTANGLE N 0 -204 64 -180
+ RECTANGLE N 0 -332 64 -308
+ RECTANGLE N 384 -268 448 -244
+ LINE N 128 -448 64 -448
+ LINE N 128 -416 128 -448
+ LINE N 128 -64 48 -64
+ LINE N 128 -96 128 -64
+ LINE N 64 -288 64 -432
+ LINE N 128 -256 64 -288
+ LINE N 64 -224 128 -256
+ LINE N 64 -80 64 -224
+ LINE N 384 -160 64 -80
+ LINE N 384 -336 384 -160
+ LINE N 384 -352 384 -336
+ LINE N 64 -432 384 -352
+ LINE N 336 -128 336 -148
+ LINE N 384 -128 336 -128
+ LINE N 448 -256 384 -256
+ LINE N 448 -128 384 -128
+ LINE N 448 -64 384 -64
+ LINE N 0 -448 64 -448
+ LINE N 0 -192 64 -192
+ LINE N 0 -320 64 -320
+ LINE N 0 -64 64 -64
+ END BLOCKDEF
+ BEGIN BLOCKDEF m2_1
+ TIMESTAMP 2001 2 2 12 39 29
+ LINE N 96 -64 96 -192
+ LINE N 256 -96 96 -64
+ LINE N 256 -160 256 -96
+ LINE N 96 -192 256 -160
+ LINE N 176 -32 96 -32
+ LINE N 176 -80 176 -32
+ LINE N 0 -32 96 -32
+ LINE N 320 -128 256 -128
+ LINE N 0 -96 96 -96
+ LINE N 0 -160 96 -160
+ END BLOCKDEF
+ BEGIN BLOCKDEF gnd
+ TIMESTAMP 2001 2 2 12 37 29
+ LINE N 64 -64 64 -96
+ LINE N 76 -48 52 -48
+ LINE N 68 -32 60 -32
+ LINE N 88 -64 40 -64
+ LINE N 64 -64 64 -80
+ LINE N 64 -128 64 -96
+ END BLOCKDEF
+ BEGIN BLOCKDEF inv
+ TIMESTAMP 2001 2 2 12 38 38
+ LINE N 0 -32 64 -32
+ LINE N 224 -32 160 -32
+ LINE N 64 -64 128 -32
+ LINE N 128 -32 64 0
+ LINE N 64 0 64 -64
+ CIRCLE N 128 -48 160 -16
+ END BLOCKDEF
+ BEGIN BLOCK XLXI_1 adsu16
+ PIN A(15:0) a(15:0)
+ PIN ADD s0
+ PIN B(15:0) b(15:0)
+ PIN CI XLXN_35
+ PIN CO XLXN_14
+ PIN OFL ofl_out
+ PIN S(15:0) result(15:0)
+ END BLOCK
+ BEGIN BLOCK XLXI_2 m2_1
+ PIN D0 XLXN_15
+ PIN D1 XLXN_14
+ PIN S0 s0
+ PIN O c_out
+ END BLOCK
+ BEGIN BLOCK XLXI_10 inv
+ PIN I XLXN_14
+ PIN O XLXN_15
+ END BLOCK
+ BEGIN BLOCK XLXI_3 m2_1
+ PIN D0 XLXN_29
+ PIN D1 XLXN_30
+ PIN S0 s1
+ PIN O XLXN_35
+ END BLOCK
+ BEGIN BLOCK XLXI_11 m2_1
+ PIN D0 XLXN_18
+ PIN D1 zero_i
+ PIN S0 s0
+ PIN O XLXN_29
+ END BLOCK
+ BEGIN BLOCK XLXI_8 inv
+ PIN I zero_i
+ PIN O XLXN_18
+ END BLOCK
+ BEGIN BLOCK XLXI_4 m2_1
+ PIN D0 XLXN_24
+ PIN D1 c_in
+ PIN S0 s0
+ PIN O XLXN_30
+ END BLOCK
+ BEGIN BLOCK XLXI_13 inv
+ PIN I c_in
+ PIN O XLXN_24
+ END BLOCK
+ BEGIN BLOCK XLXI_14 gnd
+ PIN G zero_i
+ END BLOCK
+ END NETLIST
+ BEGIN SHEET 1 3520 2720
+ INSTANCE XLXI_1 1824 1552 R0
+ INSTANCE XLXI_2 2576 1648 R0
+ BEGIN BRANCH c_out
+ WIRE 2896 1520 2960 1520
+ WIRE 2960 1520 3024 1520
+ BEGIN DISPLAY 2960 1520 ATTR Name
+ ALIGNMENT SOFT-BCENTER
+ END DISPLAY
+ END BRANCH
+ BEGIN BRANCH ofl_out
+ WIRE 2272 1424 2336 1424
+ WIRE 2336 1424 2416 1424
+ BEGIN DISPLAY 2336 1424 ATTR Name
+ ALIGNMENT SOFT-BCENTER
+ END DISPLAY
+ END BRANCH
+ INSTANCE XLXI_10 2320 1520 R0
+ BEGIN BRANCH XLXN_14
+ WIRE 2272 1488 2320 1488
+ WIRE 2272 1488 2272 1552
+ WIRE 2272 1552 2576 1552
+ END BRANCH
+ BEGIN BRANCH XLXN_15
+ WIRE 2544 1488 2576 1488
+ END BRANCH
+ BEGIN BRANCH s0
+ WIRE 544 1616 816 1616
+ WIRE 816 1616 1824 1616
+ WIRE 1824 1616 2576 1616
+ WIRE 816 912 944 912
+ WIRE 816 912 816 1232
+ WIRE 816 1232 816 1616
+ WIRE 816 1232 944 1232
+ WIRE 1824 1488 1824 1616
+ BEGIN DISPLAY 816 912 ATTR Name
+ ALIGNMENT SOFT-BCENTER
+ END DISPLAY
+ END BRANCH
+ INSTANCE XLXI_3 1360 1232 R0
+ BEGIN BRANCH XLXN_18
+ WIRE 912 784 944 784
+ END BRANCH
+ INSTANCE XLXI_11 944 944 R0
+ INSTANCE XLXI_8 688 816 R0
+ BEGIN BRANCH zero_i
+ WIRE 592 784 656 784
+ WIRE 656 784 656 848
+ WIRE 656 848 944 848
+ WIRE 656 784 688 784
+ END BRANCH
+ INSTANCE XLXI_4 944 1264 R0
+ INSTANCE XLXI_13 640 1136 R0
+ BEGIN BRANCH XLXN_24
+ WIRE 864 1104 944 1104
+ END BRANCH
+ BEGIN BRANCH c_in
+ WIRE 464 1104 528 1104
+ WIRE 528 1104 640 1104
+ WIRE 528 1104 528 1168
+ WIRE 528 1168 944 1168
+ END BRANCH
+ BEGIN BRANCH XLXN_29
+ WIRE 1264 816 1312 816
+ WIRE 1312 816 1312 1072
+ WIRE 1312 1072 1360 1072
+ END BRANCH
+ BEGIN BRANCH XLXN_30
+ WIRE 1264 1136 1360 1136
+ END BRANCH
+ BEGIN BRANCH s1
+ WIRE 1152 1296 1360 1296
+ WIRE 1360 1200 1360 1296
+ END BRANCH
+ BEGIN BRANCH a(15:0)
+ WIRE 1648 1232 1824 1232
+ END BRANCH
+ BEGIN BRANCH b(15:0)
+ WIRE 1648 1360 1824 1360
+ END BRANCH
+ BEGIN BRANCH XLXN_35
+ WIRE 1680 1104 1824 1104
+ END BRANCH
+ BEGIN BRANCH result(15:0)
+ WIRE 2272 1296 2448 1296
+ END BRANCH
+ INSTANCE XLXI_14 528 912 R0
+ IOMARKER 3024 1520 c_out R0 28
+ IOMARKER 2416 1424 ofl_out R0 28
+ IOMARKER 464 1104 c_in R180 28
+ IOMARKER 1152 1296 s1 R180 28
+ IOMARKER 544 1616 s0 R180 28
+ IOMARKER 1648 1232 a(15:0) R180 28
+ IOMARKER 1648 1360 b(15:0) R180 28
+ IOMARKER 2448 1296 result(15:0) R0 28
+ END SHEET
+END SCHEMATIC
Index: trunk/impl0/rtl/vhdl/dp.vhd
===================================================================
--- trunk/impl0/rtl/vhdl/dp.vhd (nonexistent)
+++ trunk/impl0/rtl/vhdl/dp.vhd (revision 2)
@@ -0,0 +1,663 @@
+--------------------------------------------------------------
+-- dp.vhd
+--------------------------------------------------------------
+-- project: HPC-16 Microprocessor
+--
+-- usage: microprocessor datapath
+--
+-- dependency: dp_pkg.vhd
+--
+-- Author: M. Umair Siddiqui (umairsiddiqui@opencores.org)
+---------------------------------------------------------------
+------------------------------------------------------------------------------------
+-- --
+-- Copyright (c) 2005, M. Umair Siddiqui all rights reserved --
+-- --
+-- This file is part of HPC-16. --
+-- --
+-- HPC-16 is free software; you can redistribute it and/or modify --
+-- it under the terms of the GNU Lesser General Public License as published by --
+-- the Free Software Foundation; either version 2.1 of the License, or --
+-- (at your option) any later version. --
+-- --
+-- HPC-16 is distributed in the hope that it will be useful, --
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
+-- GNU Lesser General Public License for more details. --
+-- --
+-- You should have received a copy of the GNU Lesser General Public License --
+-- along with HPC-16; if not, write to the Free Software --
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
+-- --
+------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use ieee.std_logic_arith.all;
+use work.dp_pkg.all;
+
+entity dp is
+ generic
+ ( pc_preset_value : std_logic_vector(15 downto 0) := X"0000";
+ sp_preset_value : std_logic_vector(15 downto 0) := X"0000"
+ );
+ port
+ (
+ CLK_I : in std_logic;
+ DAT_IO: inout std_logic_vector(15 downto 0);
+ ADR_O : out std_logic_vector(15 downto 0);
+ --
+ jcc_ok : out std_logic;
+ int_flag : out std_logic;
+ pc0 : out std_logic;
+ sp0 : out std_logic;
+ mar0 : out std_logic;
+ tr20 : out std_logic;
+ ir_high : out std_logic_vector(7 downto 0);
+ --
+ intr_ce : in std_logic;
+ ir_ce : in std_logic;
+ mdri_ce : in std_logic;
+ mdri_hl_zse_sign : in std_logic;
+ intno_mux_sel : in std_logic_vector(2 downto 0);
+ adin_mux_sel : in std_logic_vector(2 downto 0);
+ rf_adwe : in std_logic;
+ pcin_mux_sel : in std_logic_vector(1 downto 0);
+ pc_pre : in std_logic;
+ pc_ce : in std_logic;
+ spin_mux_sel : in std_logic;
+ sp_pre : in std_logic;
+ sp_ce : in std_logic;
+ dfh_ce : in std_logic;
+ alua_mux_sel : in std_logic_vector(1 downto 0);
+ alub_mux_sel : in std_logic_vector(2 downto 0);
+ aopsel : in std_logic_vector(2 downto 0);
+ sopsel : in std_logic_vector(2 downto 0);
+ sbin_mux_sel : in std_logic;
+ asresult_mux_sel : std_logic;
+ coszin_mux_sel : in std_logic;
+ flags_rst : in std_logic;
+ flags_ce : in std_logic;
+ flags_cfce : in std_logic;
+ flags_ifce : in std_logic;
+ flags_clc : in std_logic;
+ flags_cmc : in std_logic;
+ flags_stc : in std_logic;
+ flags_cli : in std_logic;
+ flags_sti : in std_logic;
+ marin_mux_sel : in std_logic_vector(1 downto 0);
+ mar_ce : in std_logic;
+ mdroin_mux_sel : in std_logic_vector(2 downto 0);
+ mdro_ce : in std_logic; -- mdro rst removed (11 aug 2005)
+ mdro_oe : in std_logic
+ );
+end dp;
+
+architecture rtl of dp is
+ signal dat_i : std_logic_vector(15 downto 0);
+ --
+ signal ir_out : std_logic_vector(15 downto 0);
+ signal mdri_out : std_logic_vector(15 downto 0);
+ signal rf_aq_out, rf_bq_out : std_logic_vector(15 downto 0);
+ signal tr1_out, tr2_out, tr3_out, tr4_out : std_logic_vector(15 downto 0);
+ signal pcin_mux_out : std_logic_vector(15 downto 0);
+ signal pc_out : std_logic_vector(15 downto 0);
+ signal spin_mux_out : std_logic_vector(15 downto 0);
+ signal sp_out : std_logic_vector(15 downto 0);
+ signal alua_mux_out : std_logic_vector(15 downto 0);
+ signal alub_mux_out : std_logic_vector(15 downto 0);
+ signal alu_result_out : std_logic_vector(15 downto 0);
+ signal alu_c_out, alu_o_out : std_logic;
+ signal sbin_mux_out : std_logic_vector(3 downto 0);
+ signal shifter_result_out : std_logic_vector(15 downto 0);
+ signal shifter_c_out, shifter_o_out : std_logic;
+ signal asresult_mux_result_out : std_logic_vector(15 downto 0);
+ signal asresult_mux_c_out, asresult_mux_o_out,
+ asresult_mux_s_out, asresult_mux_z_out : std_logic;
+ signal tr5_out : std_logic_vector(15 downto 0);
+ signal mdri_highlow_zse_high_out, mdri_highlow_zse_low_out : std_logic_vector(15 downto 0);
+ signal coszin_mux_out : std_logic_vector(3 downto 0);
+ signal flags_in : std_logic_vector(4 downto 0);
+ signal adin_mux_out : std_logic_vector(15 downto 0);
+ signal flags_out : std_logic_vector(4 downto 0);
+ signal intr_out : std_logic_vector(3 downto 0);
+ signal intno_mux_out : std_logic_vector(15 downto 0);
+ signal marin_mux_out : std_logic_vector(15 downto 0);
+ signal mar_out : std_logic_vector(15 downto 0);
+ signal dfh_out : std_logic_vector(15 downto 0);
+ signal mdroin_mux_out : std_logic_vector(15 downto 0);
+ signal mdro_out : std_logic_vector(15 downto 0);
+begin
+ -- internal tristate...(optional)
+ dat_i <= DAT_IO; --when mdro_oe = '0' else
+ --(others => 'Z');
+ --
+ ir : process(CLK_I)
+ -- ir is 16-bit register, connected to data bus. cpu store the instruction
+ -- fetched from memory. The ir's controlled by fsm signal ``ir_ce".
+ begin
+ if rising_edge(CLK_I) then
+ if ir_ce = '1' then
+ ir_out <= DAT_I;
+ end if;
+ end if;
+ end process;
+
+ -- ir outputs goes to different components...
+ -- ir(15..8) goes to fsm for evaluation of current instruction's opcode
+ -- and subop
+ ir_high <= ir_out(15 downto 8);
+
+ mdri : process(CLK_I)
+ -- mdri is another 16-bit register connected to databus. cpu store data and
+ -- immediate const from memory in the this register. it is controlled by
+ -- fsm signal ``mdri_ce"
+ begin
+ if rising_edge(CLK_I) then
+ if mdri_ce = '1' then
+ mdri_out <= DAT_I;
+ end if;
+ end if;
+ end process;
+
+ mdri_highlow_zse : process (mdri_hl_zse_sign, mdri_out)
+ -- while execution of lbzx/lbsx instruction cpu needs to load byte.
+ -- after loading byte data, data is either zero extended or sign extended.
+ -- additionally there is no alignment restriction on byte data, it may either
+ -- present on even address or odd address. byte data on even address appear on
+ -- upper 8 lines of databus and loaded into mdri(15..8) while byte data on odd
+ -- address appear on lower 8 lines of databus and loaded into mdri(7..0).
+ -- so we have to (sign/zero) extend both of them.
+ begin
+ case mdri_hl_zse_sign is
+ when '0' =>
+ mdri_highlow_zse_high_out <= ext(mdri_out(15 downto 8), 16);
+ mdri_highlow_zse_low_out <= ext(mdri_out(7 downto 0), 16);
+ when '1' =>
+ mdri_highlow_zse_high_out <= sxt(mdri_out(15 downto 8), 16);
+ mdri_highlow_zse_low_out <= sxt(mdri_out(7 downto 0), 16);
+ when others =>
+ mdri_highlow_zse_high_out <= (others => '0');
+ mdri_highlow_zse_low_out <= (others => '0');
+ end case;
+ end process;
+
+ u1 : regfile
+ -- register file contain 16-bit, 16 general purpose registers...
+ -- register file has two address inputs (4-bit wide), one connected to aadrin_mux_out,
+ -- another connected to ir(3..0). it's write control is connected to fsm
+ -- signal `rf_adwe'. its data input port (16-bit wide) is connected to adin_mux's output.
+ -- register file has two outputs (16-bit wide): aq, bq
+ -- the data (register contents) can be read asynchronously from register file however,
+ -- data writing is done synchronously.
+ port map(
+ aadr => ir_out(7 downto 4),
+ badr => ir_out(3 downto 0),
+ ad => adin_mux_out,
+ adwe => rf_adwe,
+ clk => CLK_I,
+ aq => rf_aq_out,
+ bq => rf_bq_out
+ );
+
+ -- two 16-bit temporary registers tr1 and tr2 are connected to register file's
+ -- aq and bq output respectively.
+ -- two 16-bit temporary registers tr3 and tr4 are connected to sign extended fields of ir:
+ -- ir(10..0) and (ir(10..8)&ir(3..0)) respectively
+ tr1 : process(CLK_I)
+ begin
+ if rising_edge(CLK_I) then
+ tr1_out <= rf_aq_out;
+ end if;
+ end process;
+
+ tr2 : process(CLK_I)
+ begin
+ if rising_edge(CLK_I) then
+ tr2_out <= rf_bq_out;
+ end if;
+ end process;
+
+ -- tr2(0) goes out of datapath (to fsm) for evalution
+ tr20 <= tr2_out(0);
+
+ tr3 : process(CLK_I)
+ begin
+ if rising_edge(CLK_I) then
+ tr3_out <= sxt(ir_out(10 downto 0), 16);
+ end if;
+ end process;
+
+ tr4 : process(CLK_I)
+ begin
+ if rising_edge(CLK_I) then
+ tr4_out <= sxt(ir_out(10 downto 8) & ir_out(3 downto 0), 16);
+ end if;
+ end process;
+
+
+ alua_mux : process(alua_mux_sel, pc_out, sp_out, tr1_out, tr2_out)
+ -- alua_mux is connected to alu's input port `A' and used to select
+ -- operand `A'. it is controlled by fsm signal alua_mux_sel. it has four
+ -- inputs which are connected to: pc output, sp output, tr1 output and
+ -- tr2 output. all the inputs and output are 16-bit wide.
+ begin
+ case alua_mux_sel is
+ when "00" =>
+ alua_mux_out <= pc_out;
+ when "01" =>
+ alua_mux_out <= sp_out;
+ when "10" =>
+ alua_mux_out <= tr1_out;
+ when "11" =>
+ alua_mux_out <= tr2_out;
+ when others =>
+ alua_mux_out <= (others => '-');
+ end case;
+ end process;
+
+ alub_mux : process(alub_mux_sel, tr2_out, tr3_out, tr4_out, mdri_out)
+ -- alub_mux is connected to alu's input port `B' and used to select
+ -- operand `B'. it is controlled by fsm signal alua_mux_sel. it has 8 inputs,
+ -- which are connected to: tr2 output, constant `2', constant `1', constant `0'
+ -- tr3, tr4, mdri's ouput and rest don't care.
+ -- all the inputs and output are 16-bit wide.
+ begin
+ case alub_mux_sel is
+ when "000" =>
+ alub_mux_out <= tr2_out;
+ when "001" =>
+ alub_mux_out <= X"0002";
+ when "010" =>
+ alub_mux_out <= X"0001";
+ when "011" =>
+ alub_mux_out <= X"0000";
+ when "100" =>
+ alub_mux_out <= tr3_out;
+ when "101" =>
+ alub_mux_out <= tr4_out;
+ when "110" =>
+ alub_mux_out <= mdri_out;
+ when others =>
+ alub_mux_out <= (others => '-');
+ end case;
+ end process;
+
+ u2 : alu
+ -- Alu perform all the arithmetic and logic operations. it has two 16-bit wide data inputs
+ -- `A' and `B', and 1-bit carry input. the alu is controled by fsm signal aopsel(2..0).
+ -- the alu has a 16-bit wide output: result, as well as carry out and overflow out
+ -- signals (1-bit each). the carry out and overflow out signals are used
+ -- to update corresponding status flags in ``flags" register.
+ port map(
+ a => alua_mux_out,
+ b => alub_mux_out,
+ opsel => aopsel(2 downto 0),
+ c_in => flags_out(4),
+ result => alu_result_out,
+ c_out => alu_c_out,
+ ofl_out => alu_o_out
+ );
+
+ sbin_mux : process(sbin_mux_sel, ir_out(3 downto 0), tr2_out(3 downto 0))
+ -- sbin_mux is 4-bit wide 2-1 mux, its output connected to `B' input of
+ -- shifter. one of its input connected to tr2(3..0) while other is connected
+ -- to ir(3..0). this allow us to implement const as well as variable shift operations
+ begin
+ case sbin_mux_sel is
+ when '0' =>
+ sbin_mux_out <= tr2_out(3 downto 0);
+ when '1' =>
+ sbin_mux_out <= ir_out(3 downto 0);
+ when others =>
+ sbin_mux_out <= (others => '-');
+ end case;
+ end process;
+
+ u3 : shifter
+ -- Shifter perform 16-bit data shift and rotate operations. it has a 16-bit data input `A',
+ -- the no. of time shift operation is performed, is determined by 4-bit `B' input. To support
+ -- operations: ``rotate carry left" and ``rotate carry right", there is 1-bit carry input signal.
+ -- like alu, shifter also has a 16-bit wide output: result, as well as carry out and overflow out
+ -- signals (1-bit each). the carry out and overflow out signals are used
+ -- to update corresponding status flags in ``flags" register.
+ port map
+ (
+ a => tr1_out,
+ b => sbin_mux_out,
+ c_in => flags_out(4),
+ opsel => sopsel(2 downto 0),
+ result => shifter_result_out,
+ c_out => shifter_c_out,
+ ofl_out => shifter_o_out
+ );
+
+ asresult_mux : process(asresult_mux_sel, alu_result_out, alu_c_out,
+ alu_o_out, shifter_result_out, shifter_c_out,
+ shifter_o_out)
+ -- The result, carry out, and overflow out signals, are comming out from both shifter
+ -- and alu. The asresult mux, multiplexed these signals
+ begin
+ case asresult_mux_sel is
+ when '0' =>
+ asresult_mux_result_out <= alu_result_out;
+ asresult_mux_c_out <= alu_c_out;
+ asresult_mux_o_out <= alu_o_out;
+ when '1' =>
+ asresult_mux_result_out <= shifter_result_out;
+ asresult_mux_c_out <= shifter_c_out;
+ asresult_mux_o_out <= shifter_o_out;
+ when others =>
+ asresult_mux_result_out <= (others => '-');
+ asresult_mux_c_out <= '-';
+ asresult_mux_o_out <= '-';
+ end case;
+ end process;
+
+ -- from ``asresult_mux_result_out" signal, two more signals are generated:
+ -- ``asresult_mux_s_out" and ``asresult_mux_z_out". these two signal update
+ -- two status flags: sign and zero flags inside flags register, respactively.
+
+ asresult_mux_s_out <= asresult_mux_result_out(15);
+
+ asresult_mux_z_out <= '1' when asresult_mux_result_out = X"0000" else
+ '0';
+
+ tr5: process(CLK_I)
+ -- the multiplexed result, ``asresult_mux_result_out" goes to 16-bit temporary
+ -- register.
+ begin
+ if rising_edge(CLK_I) then
+ tr5_out <= asresult_mux_result_out;
+ end if;
+ end process;
+
+ coszin_mux : process(coszin_mux_sel, mdri_out(4 downto 1), asresult_mux_c_out,
+ asresult_mux_o_out, asresult_mux_s_out, asresult_mux_z_out)
+ -- The PUSHF instruction, push the content of flags register into memory.
+ -- corresponding POPF instruction, pop the content of memory word into flags register.
+ -- therefore a 4-bit wide 2-1 mux is required for four status flags (C, O, S, Z) in
+ -- flags register, to either select mdri(4 downto 1) or flag outputs of asresult mux.
+ begin
+ case coszin_mux_sel is
+ when '0' =>
+ coszin_mux_out <= asresult_mux_c_out & asresult_mux_o_out
+ & asresult_mux_s_out & asresult_mux_z_out;
+ when '1' =>
+ coszin_mux_out <= mdri_out(4 downto 1);
+ when others =>
+ coszin_mux_out <= (others => '-');
+ end case;
+ end process;
+
+ -- flags register contain four status flags: carry, overflow, sign and zero.
+ -- there is also a system flag: int. flags register input consists of
+ -- coszin_mux_out & mdri(0).
+
+ flags_in <= coszin_mux_out & mdri_out(0);
+
+ u4 : flags
+ -- flags register has several control signals: async reset which is control by fsm
+ -- signal ``flags_rst" asserted on cpu reset, load control by fsm's ``flags_ce"
+ -- signal, separate load controls for carry and interrupt flags which are controlled
+ -- by ``flags_cfce" and ``flags_ifce" respectively.
+ -- three control signals ``flags_clc", ``flags_cmc" and ``flags_stc" are provided
+ -- for clearing/complementing/setting carry flag.
+ -- two control signals ``flags_cli" and ``flags_sti" are provided
+ -- for clearing/setting int flag.
+ port map(
+ Flags_in => flags_in,
+ CLK_in => CLK_I,
+ ResetAll_in => flags_rst,
+ CE_in => flags_ce,
+ CFCE_in => flags_cfce,
+ IFCE_in => flags_ifce,
+ CLC_in => flags_clc,
+ CMC_in => flags_cmc,
+ STC_in => flags_stc,
+ STI_in => flags_sti,
+ CLI_in => flags_cli,
+ Flags_out => flags_out
+ );
+
+ -- when hardware interrupt occurs, cpu need to check the status of interrupt flag.
+ -- so this signal goes to fsm
+ int_flag <= flags_out(0);
+
+ adin_mux : process(adin_mux_sel, tr2_out, tr5_out, sp_out, mdri_out,
+ mdri_highlow_zse_high_out, mdri_highlow_zse_low_out)
+ -- the adin_mux is 16-bit wide 8-1 mux connected to regfile ad input. it is
+ -- controlled by fsm's signal ``adin_mux_sel". its input are connected to outputs of
+ -- tr2, tr5, sp, mdri and mdri_highlow_zse. the rest of inputs are donot care.
+ begin
+ case adin_mux_sel is
+ when "000" =>
+ adin_mux_out <= tr2_out;
+ when "001" =>
+ adin_mux_out <= tr5_out;
+ when "010" =>
+ adin_mux_out <= sp_out;
+ when "011" =>
+ adin_mux_out <= mdri_out;
+ when "100" =>
+ adin_mux_out <= mdri_highlow_zse_high_out;
+ when "101" =>
+ adin_mux_out <= mdri_highlow_zse_low_out;
+ when others =>
+ adin_mux_out <= (others => '-');
+ end case;
+ end process;
+
+ u5: fcmp
+ -- A flag comparator (fcmp) is used during execution of jcc and into instruction.
+ -- it has two 4-bit inputs connected to status flags of flags register and
+ -- ir(7..4). it has 1-bit output. It check the status flags according condition
+ -- specified in ir(7..4), if condition holds, the output is asserted.
+ -- this output goes to fsm for evaluation.
+ port map(
+ tttnField_in => ir_out(7 downto 4),
+ flags_in => flags_out(4 downto 1),
+ result_out => jcc_ok
+ );
+
+ intr: process(CLK_I)
+ -- the intr is 4-bit register, connected to data bus(11..8) lines of databus.
+ -- it is controled by fsm's signal ``intr_ce". it is used to store
+ -- interrupt vector no. provided by the interrupting hardware.
+ begin
+ if rising_edge(CLK_I) then
+ if intr_ce = '1' then
+ intr_out <= DAT_I(11 downto 8);
+ end if;
+ end if;
+ end process;
+
+ intno_mux : process(intno_mux_sel, ir_out(3 downto 0), intr_out)
+ -- the intno_mux select the vector no. it is controlled by fsm's intno_mux_sel
+ -- signal. first four inputs are tied to consts declared in ``dp_pkg", which are
+ -- vector numbers of invaild opcode exception, alignment exception,
+ -- stack error exception and double fault respectively.
+ -- the other two are tied to outputs of ir(3..0)and intr.
+ -- the selected vector number is further zero extended and multiplied by 8.
+ variable t1 : std_logic_vector(3 downto 0);
+ variable t2 : std_logic_vector(15 downto 0);
+ begin
+ case intno_mux_sel is
+ when "000" =>
+ t1 := invaild_inst_vec;
+ when "001" =>
+ t1 := align_err_vec;
+ when "010" =>
+ t1 := stack_err_vec;
+ when "011" =>
+ t1 := df_err_vec;
+ when "100" =>
+ t1 := ir_out(3 downto 0);
+ when "101" =>
+ t1 := intr_out;
+ when others =>
+ t1 := (others => '-');
+ end case;
+ t2 := "000000000000" & t1;
+ intno_mux_out <= t2(12 downto 0) & "000";
+ end process;
+
+ pcin_mux : process(pcin_mux_sel, alu_result_out, intno_mux_out, mdri_out)
+ -- the pcin_mux is 16-bit wide mux, connected to pc input.
+ -- it is controlled by fsm's signal ``pcin_mux_sel". one of its input is connected
+ -- alu result output (this allows increament in pc after fetching instruction, place
+ -- effective address calculated during jmp and call), second to intno_mux output
+ -- (for int, into and hardware interrupt) and third to mdri output (for ret and iret
+ -- instructions)
+ begin
+ case pcin_mux_sel is
+ when "00" =>
+ pcin_mux_out <= alu_result_out;
+ when "01" =>
+ pcin_mux_out <= intno_mux_out;
+ when "10" =>
+ pcin_mux_out <= mdri_out;
+ when others =>
+ pcin_mux_out <= (others => '-');
+ end case;
+ end process;
+
+ pc : process(CLK_I, pc_pre)
+ -- the 16-bit pc register contain the address of for the next instruction
+ -- to be executed. it is advanced from one instruction boundry to the next
+ -- in straight line code or it is moved ahead or backwards by a number of instructions
+ -- when executing jmp, jcc, call, ret and iret instructions.
+ -- on cpu reset, the pc preset to ``pc_preset_value".
+ begin
+ if pc_pre = '1' then
+ pc_out <= pc_preset_value;
+ elsif rising_edge(CLK_I) then
+ if pc_ce = '1' then
+ pc_out <= pcin_mux_out;
+ end if;
+ end if;
+ end process;
+
+ -- the pc may contain odd address, specially after ret or iret instruction.
+ -- therefore lsb of pc output goes to fsm input.
+ pc0 <= pc_out(0);
+
+ spin_mux : process(spin_mux_sel, alu_result_out, mdri_out)
+ -- the spin_mux is 16-bit wide 2-1 mux, connected to sp input.
+ -- it is controlled by fsm's signal ``spin_mux_sel". one of its input is connected
+ -- alu result output and other to mdri output.
+ begin
+ case spin_mux_sel is
+ when '0' =>
+ spin_mux_out <= alu_result_out;
+ when '1' =>
+ spin_mux_out <= mdri_out;
+ when others =>
+ spin_mux_out <= (others => '-');
+ end case;
+ end process;
+
+ sp : process(CLK_I, sp_pre)
+ -- sp is 16-bit register, it contain the address of ``top of stack"(TOS).
+ -- when items (only 16-bit) are pushed on stack, cpu decreament the sp,
+ -- and push the item of TOS. when an item is popped off the stack, the
+ -- processor read the items from TOS, then increament the sp register.
+ -- on procedure call, cpu automatically push pc and on return pops the TOS
+ -- into pc. on interrupt/exception cpu automattically push flags and pc while
+ -- on iret, cpu restore pc and flags
+ -- on stack error and double fault, sp preset to ``sp_preset_value"
+ begin
+ if sp_pre = '1' then
+ sp_out <= sp_preset_value;
+ elsif rising_edge(CLK_I) then
+ if sp_ce = '1' then
+ sp_out <= spin_mux_out;
+ end if;
+ end if;
+ end process;
+
+ -- lsb of sp goes to fsm's input, for alignment checking.
+ sp0 <= sp_out(0);
+
+ dfh : process(CLK_I)
+ -- dfh is 16-bit register which used to temporary store the offending sp value,
+ -- during stk err and df. it is controlled by fsm's signal: dfh_ce.
+ begin
+ if rising_edge(CLK_I) then
+ if dfh_ce = '1' then
+ dfh_out <= sp_out;
+ end if;
+ end if;
+ end process;
+
+ marin_mux : process(marin_mux_sel, pc_out, sp_out, alu_result_out)
+ -- marin_mux is 16-bit wide mux. it is controlled by fsm's signal marin_mux_sel.
+ -- its inputs are connected to: pc, sp and alu reseult output
+ begin
+ case marin_mux_sel is
+ when "00" =>
+ marin_mux_out <= pc_out;
+ when "01" =>
+ marin_mux_out <= alu_result_out;
+ when "10" =>
+ marin_mux_out <= sp_out;
+ when others =>
+ marin_mux_out <= (others => '-');
+ end case;
+ end process;
+
+ mar : process(CLK_I)
+ -- mar is 16-bit regiser, conected to address bus. it is controlled by fsm's signal
+ -- ``mar_ce". any address is first loaded into mar and then goes to address bus.
+ begin
+ if rising_edge(CLK_I) then
+ if mar_ce = '1' then
+ mar_out <= marin_mux_out;
+ end if;
+ end if;
+ end process;
+
+ mar0 <= mar_out(0);
+
+ ADR_O <= mar_out;
+
+ mdroin_mux : process(mdroin_mux_sel, pc_out, tr1_out, flags_out, dfh_out, intno_mux_out)
+ -- mdroin_mux is 16-bit wide mux. it is controlled by fsm's signal mdroin_mux_sel.
+ -- its inputs are connected to: pc, tr1, zero extended flags output, (tr1(7..0)& X"00")
+ -- zero extended tr1(7..0), dfh output, intno_mux outputs are used in stk and df exception
+ begin
+ case mdroin_mux_sel is
+ when "000" =>
+ mdroin_mux_out <= pc_out;
+ when "001" =>
+ mdroin_mux_out <= tr1_out;
+ when "010" =>
+ mdroin_mux_out <= "00000000000" & flags_out;
+ when "011" =>
+ mdroin_mux_out <= dfh_out;
+ when "100" =>
+ mdroin_mux_out <= intno_mux_out;
+ when "101" =>
+ mdroin_mux_out <= tr1_out(7 downto 0) & X"00";
+ when "110" =>
+ mdroin_mux_out <= X"00" & tr1_out(7 downto 0);
+ when others =>
+ mdroin_mux_out <= (others => '-');
+ end case;
+ end process;
+
+ -- mdro is 16-bit register connected to databus, through tri-state buffer. it has for control
+ -- signals: mdro_ce for load control, second control: mdro_oe is tri-state buffer control.
+ mdro : process(CLK_I)
+ begin
+ if rising_edge(CLK_I) then
+ if mdro_ce = '1' then
+ mdro_out <= mdroin_mux_out;
+ end if;
+ end if;
+ end process;
+
+ DAT_IO <= mdro_out when mdro_oe = '1' else
+ (others => 'Z');
+
+end rtl;
Index: trunk/impl0/rtl/vhdl/dp_pkg.vhd
===================================================================
--- trunk/impl0/rtl/vhdl/dp_pkg.vhd (nonexistent)
+++ trunk/impl0/rtl/vhdl/dp_pkg.vhd (revision 2)
@@ -0,0 +1,112 @@
+--------------------------------------------------------------
+-- dp_pkg.vhd
+--------------------------------------------------------------
+-- project: HPC-16 Microprocessor
+--
+-- usage: component declarations for datapath, constant
+-- declarations for predefined interrupt vectors
+--
+-- dependency: alu.vhd, shifter.vhd, regfile.vhd, flags.vhd, fcmp.vhd
+--
+-- Author: M. Umair Siddiqui (umairsiddiqui@opencores.org)
+---------------------------------------------------------------
+------------------------------------------------------------------------------------
+-- --
+-- Copyright (c) 2005, M. Umair Siddiqui all rights reserved --
+-- --
+-- This file is part of HPC-16. --
+-- --
+-- HPC-16 is free software; you can redistribute it and/or modify --
+-- it under the terms of the GNU Lesser General Public License as published by --
+-- the Free Software Foundation; either version 2.1 of the License, or --
+-- (at your option) any later version. --
+-- --
+-- HPC-16 is distributed in the hope that it will be useful, --
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
+-- GNU Lesser General Public License for more details. --
+-- --
+-- You should have received a copy of the GNU Lesser General Public License --
+-- along with HPC-16; if not, write to the Free Software --
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
+-- --
+------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+package dp_pkg is
+ component alu is
+ port(
+ a : in std_logic_vector(15 downto 0);
+ b : in std_logic_vector(15 downto 0);
+ opsel : in std_logic_vector(2 downto 0);
+ c_in : in std_logic;
+ result: out std_logic_vector(15 downto 0);
+ c_out: out std_logic;
+ ofl_out: out std_logic
+ );
+ end component;
+
+ component shifter is
+ port
+ (
+ a : in std_logic_vector(15 downto 0);
+ b : in std_logic_vector(3 downto 0);
+ c_in : in std_logic;
+ opsel : in std_logic_vector(2 downto 0);
+ result : out std_logic_vector(15 downto 0);
+ c_out : out std_logic;
+ ofl_out : out std_logic
+ );
+ end component;
+
+ component regfile is
+ port(
+ aadr : in std_logic_vector(3 downto 0);
+ badr : in std_logic_vector(3 downto 0);
+ ad : in std_logic_vector(15 downto 0);
+ adwe : in std_logic;
+ clk : in std_logic;
+ aq : out std_logic_vector(15 downto 0);
+ bq : out std_logic_vector(15 downto 0)
+ );
+ end component;
+
+ component flags is
+ port(
+
+ Flags_in : in std_logic_vector(4 downto 0);
+
+ CLK_in : in std_logic;
+
+ ResetAll_in : in std_logic;
+ CE_in : in std_logic;
+ CFCE_in : in std_logic;
+ IFCE_in : in std_logic;
+ CLC_in : in std_logic;
+ CMC_in : in std_logic;
+ STC_in : in std_logic;
+ STI_in : in std_logic;
+ CLI_in : in std_logic;
+
+ Flags_out : out std_logic_vector(4 downto 0)
+
+ );
+
+ end component;
+
+ component fcmp is
+ port( tttnField_in : in std_logic_vector(3 downto 0); ---(COSZ)
+ flags_in : in std_logic_vector(3 downto 0);
+ result_out : out std_logic
+ );
+ end component;
+
+
+ constant invaild_inst_vec : std_logic_vector(3 downto 0) := "0001";
+ constant align_err_vec : std_logic_vector(3 downto 0) := "0010";
+ constant stack_err_vec : std_logic_vector(3 downto 0) := "0011";
+ constant df_err_vec : std_logic_vector(3 downto 0) := "0100";
+
+end package;
\ No newline at end of file
Index: trunk/impl0/rtl/vhdl/shifter.vhd
===================================================================
--- trunk/impl0/rtl/vhdl/shifter.vhd (nonexistent)
+++ trunk/impl0/rtl/vhdl/shifter.vhd (revision 2)
@@ -0,0 +1,271 @@
+--------------------------------------------------------------
+-- shifter.vhd
+--------------------------------------------------------------
+-- project: HPC-16 Microprocessor
+--
+-- usage: combinational shifter
+--
+-- dependency: none
+--
+-- Author: M. Umair Siddiqui (umairsiddiqui@opencores.org)
+---------------------------------------------------------------
+------------------------------------------------------------------------------------
+-- --
+-- Copyright (c) 2005, M. Umair Siddiqui all rights reserved --
+-- --
+-- This file is part of HPC-16. --
+-- --
+-- HPC-16 is free software; you can redistribute it and/or modify --
+-- it under the terms of the GNU Lesser General Public License as published by --
+-- the Free Software Foundation; either version 2.1 of the License, or --
+-- (at your option) any later version. --
+-- --
+-- HPC-16 is distributed in the hope that it will be useful, --
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
+-- GNU Lesser General Public License for more details. --
+-- --
+-- You should have received a copy of the GNU Lesser General Public License --
+-- along with HPC-16; if not, write to the Free Software --
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
+-- --
+------------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+--Opsel-----|--shifter Operation--
+--000-------|--sll----------------
+--001-------|--slr----------------
+--010-------|--sal----------------
+--011-------|--sar----------------
+--100-------|--rol----------------
+--101-------|--ror----------------
+--110-------|--rcl----------------
+--111-------|--rcr----------------
+
+entity shifter is
+ port
+ (
+ a : in std_logic_vector(15 downto 0);
+ b : in std_logic_vector(3 downto 0);
+ c_in : in std_logic;
+ opsel : in std_logic_vector(2 downto 0);
+ result : out std_logic_vector(15 downto 0);
+ c_out : out std_logic;
+ ofl_out : out std_logic
+ );
+end shifter;
+
+architecture dataflow of shifter is
+ signal shltemp, shrtemp, saltemp, sartemp, roltemp,
+ rortemp, rcltemp, rcrtemp, carry_result : std_logic_vector(16 downto 0);
+begin
+ ShiftLogicalLeft: process(a , b, c_in) is
+ begin
+ case b is
+ when "0000" => shltemp <= c_in & a(15 downto 0);
+ when "0001" => shltemp <= a(15) & a(14 downto 0) & "0";
+ when "0010" => shltemp <= a(14) & a(13 downto 0) & "00";
+ when "0011" => shltemp <= a(13) & a(12 downto 0) & "000";
+ when "0100" => shltemp <= a(12) & a(11 downto 0) & "0000";
+ when "0101" => shltemp <= a(11) & a(10 downto 0) & "00000";
+ when "0110" => shltemp <= a(10) & a(09 downto 0) & "000000";
+ when "0111" => shltemp <= a(09) & a(08 downto 0) & "0000000";
+ when "1000" => shltemp <= a(08) & a(07 downto 0) & "00000000";
+ when "1001" => shltemp <= a(07) & a(06 downto 0) & "000000000";
+ when "1010" => shltemp <= a(06) & a(05 downto 0) & "0000000000";
+ when "1011" => shltemp <= a(05) & a(04 downto 0) & "00000000000";
+ when "1100" => shltemp <= a(04) & a(03 downto 0) & "000000000000";
+ when "1101" => shltemp <= a(03) & a(02 downto 0) & "0000000000000";
+ when "1110" => shltemp <= a(02) & a(01 downto 0) & "00000000000000";
+ when "1111" => shltemp <= a(01) & a(00) & "000000000000000";
+ when others => shltemp <= (others => '0');
+ end case;
+ end process;
+
+ ShiftLogicalRight: process(a, b, c_in) is
+ begin
+ case b is
+ when "0000" => shrtemp <= c_in & a(15 downto 0);
+ when "0001" => shrtemp <= a(00) & "0" & a(15 downto 01);
+ when "0010" => shrtemp <= a(01) & "00" & a(15 downto 02);
+ when "0011" => shrtemp <= a(02) & "000" & a(15 downto 03);
+ when "0100" => shrtemp <= a(03) & "0000" & a(15 downto 04);
+ when "0101" => shrtemp <= a(04) & "00000" & a(15 downto 05);
+ when "0110" => shrtemp <= a(05) & "000000" & a(15 downto 06);
+ when "0111" => shrtemp <= a(06) & "0000000" & a(15 downto 07);
+ when "1000" => shrtemp <= a(07) & "00000000" & a(15 downto 08);
+ when "1001" => shrtemp <= a(08) & "000000000" & a(15 downto 09);
+ when "1010" => shrtemp <= a(09) & "0000000000" & a(15 downto 10);
+ when "1011" => shrtemp <= a(10) & "00000000000" & a(15 downto 11);
+ when "1100" => shrtemp <= a(11) & "000000000000" & a(15 downto 12);
+ when "1101" => shrtemp <= a(12) & "0000000000000" & a(15 downto 13);
+ when "1110" => shrtemp <= a(13) & "00000000000000" & a(15 downto 14);
+ when "1111" => shrtemp <= a(14) & "000000000000000" & a(15);
+ when others => shrtemp <= (others => '0');
+ end case;
+ end process;
+
+ ShiftArithmaticLeft: saltemp <= shltemp;
+
+ ShiftArithmaticRight: process(a, b, c_in) is
+ variable s : std_logic;
+ begin
+ s := a(15);
+ case b is
+ when "0000" => sartemp <= c_in & a(15 downto 0);
+ when "0001" => sartemp <= a(00) & s & a(15 downto 01);
+ when "0010" => sartemp <= a(01) & s & s & a(15 downto 02);
+ when "0011" => sartemp <= a(02) & s & s & s & a(15 downto 03);
+ when "0100" => sartemp <= a(03) & s & s & s & s & a(15 downto 04);
+ when "0101" => sartemp <= a(04) & s & s & s & s & s & a(15 downto 05);
+ when "0110" => sartemp <= a(05) & s & s & s & s & s & s & a(15 downto 06);
+ when "0111" => sartemp <= a(06) & s & s & s & s & s & s & s & a(15 downto 07);
+ when "1000" => sartemp <= a(07) & s & s & s & s & s & s & s & s & a(15 downto 08);
+ when "1001" => sartemp <= a(08) & s & s & s & s & s & s & s & s & s & a(15 downto 09);
+ when "1010" => sartemp <= a(09) & s & s & s & s & s & s & s & s & s & s & a(15 downto 10);
+ when "1011" => sartemp <= a(10) & s & s & s & s & s & s & s & s & s & s & s & a(15 downto 11);
+ when "1100" => sartemp <= a(11) & s & s & s & s & s & s & s & s & s & s & s & s & a(15 downto 12);
+ when "1101" => sartemp <= a(12) & s & s & s & s & s & s & s & s & s & s & s & s & s & a(15 downto 13);
+ when "1110" => sartemp <= a(13) & s & s & s & s & s & s & s & s & s & s & s & s & s & s & a(15 downto 14);
+ when "1111" => sartemp <= a(14) & s & s & s & s & s & s & s & s & s & s & s & s & s & s & s & a(15);
+ when others => sartemp <= (others => '0');
+ end case;
+ end process;
+
+ RotateLeft: process(a, b, c_in) is
+ begin
+ case b is
+ when "0000" => roltemp <= c_in & a(15 downto 0);
+ when "0001" => roltemp <= a(15) & a(14 downto 0) & a(15);
+ when "0010" => roltemp <= a(14) & a(13 downto 0) & a(15 downto 14);
+ when "0011" => roltemp <= a(13) & a(12 downto 0) & a(15 downto 13);
+ when "0100" => roltemp <= a(12) & a(11 downto 0) & a(15 downto 12);
+ when "0101" => roltemp <= a(11) & a(10 downto 0) & a(15 downto 11);
+ when "0110" => roltemp <= a(10) & a(09 downto 0) & a(15 downto 10);
+ when "0111" => roltemp <= a(09) & a(08 downto 0) & a(15 downto 09);
+ when "1000" => roltemp <= a(08) & a(07 downto 0) & a(15 downto 08);
+ when "1001" => roltemp <= a(07) & a(06 downto 0) & a(15 downto 07);
+ when "1010" => roltemp <= a(06) & a(05 downto 0) & a(15 downto 06);
+ when "1011" => roltemp <= a(05) & a(04 downto 0) & a(15 downto 05);
+ when "1100" => roltemp <= a(04) & a(03 downto 0) & a(15 downto 04);
+ when "1101" => roltemp <= a(03) & a(02 downto 0) & a(15 downto 03);
+ when "1110" => roltemp <= a(02) & a(01 downto 0) & a(15 downto 02);
+ when "1111" => roltemp <= a(01) & a(00) & a(15 downto 01);
+ when others => roltemp <= (others => '0');
+ end case;
+ end process;
+
+ RotateRight: process(a, b, c_in) is
+ begin
+ case b is
+ when "0000" => rortemp <= c_in & a(15 downto 0);
+ when "0001" => rortemp <= a(00) & a(00) & a(15 downto 1);
+ when "0010" => rortemp <= a(01) & a(01 downto 0) & a(15 downto 02);
+ when "0011" => rortemp <= a(02) & a(02 downto 0) & a(15 downto 03);
+ when "0100" => rortemp <= a(03) & a(03 downto 0) & a(15 downto 04);
+ when "0101" => rortemp <= a(04) & a(04 downto 0) & a(15 downto 05);
+ when "0110" => rortemp <= a(05) & a(05 downto 0) & a(15 downto 06);
+ when "0111" => rortemp <= a(06) & a(06 downto 0) & a(15 downto 07);
+ when "1000" => rortemp <= a(07) & a(07 downto 0) & a(15 downto 08);
+ when "1001" => rortemp <= a(08) & a(08 downto 0) & a(15 downto 09);
+ when "1010" => rortemp <= a(09) & a(09 downto 0) & a(15 downto 10);
+ when "1011" => rortemp <= a(10) & a(10 downto 0) & a(15 downto 11);
+ when "1100" => rortemp <= a(11) & a(11 downto 0) & a(15 downto 12);
+ when "1101" => rortemp <= a(12) & a(12 downto 0) & a(15 downto 13);
+ when "1110" => rortemp <= a(13) & a(13 downto 0) & a(15 downto 14);
+ when "1111" => rortemp <= a(14) & a(14 downto 0) & a(15);
+ when others => rortemp <= (others => '0');
+ end case;
+ end process;
+
+ RotateCarryLeft: process(a, b, c_in) is
+ begin
+ case b is
+ when "0000" => rcltemp <= c_in & a(15 downto 0);
+ when "0001" => rcltemp <= a(15) & a(14 downto 0) & c_in;
+ when "0010" => rcltemp <= a(14) & a(13 downto 0) & c_in & a(15);
+ when "0011" => rcltemp <= a(13) & a(12 downto 0) & c_in & a(15 downto 14);
+ when "0100" => rcltemp <= a(12) & a(11 downto 0) & c_in & a(15 downto 13);
+ when "0101" => rcltemp <= a(11) & a(10 downto 0) & c_in & a(15 downto 12);
+ when "0110" => rcltemp <= a(10) & a(09 downto 0) & c_in & a(15 downto 11);
+ when "0111" => rcltemp <= a(09) & a(08 downto 0) & c_in & a(15 downto 10);
+ when "1000" => rcltemp <= a(08) & a(07 downto 0) & c_in & a(15 downto 09);
+ when "1001" => rcltemp <= a(07) & a(06 downto 0) & c_in & a(15 downto 08);
+ when "1010" => rcltemp <= a(06) & a(05 downto 0) & c_in & a(15 downto 07);
+ when "1011" => rcltemp <= a(05) & a(04 downto 0) & c_in & a(15 downto 06);
+ when "1100" => rcltemp <= a(04) & a(03 downto 0) & c_in & a(15 downto 05);
+ when "1101" => rcltemp <= a(03) & a(02 downto 0) & c_in & a(15 downto 04);
+ when "1110" => rcltemp <= a(02) & a(01 downto 0) & c_in & a(15 downto 03);
+ when "1111" => rcltemp <= a(01) & a(00) & c_in & a(15 downto 02);
+ when others => rcltemp <= (others => '0');
+ end case;
+ end process;
+
+ RotateCarryRight: process(a, b, c_in) is
+ begin
+ case b is
+ when "0000" => rcrtemp <= c_in & a(15 downto 0);
+ when "0001" => rcrtemp <= a(00) & c_in & a(15 downto 1);
+ when "0010" => rcrtemp <= a(01) & a(0) & c_in & a(15 downto 2);
+ when "0011" => rcrtemp <= a(02) & a(01 downto 0) & c_in & a(15 downto 03);
+ when "0100" => rcrtemp <= a(03) & a(02 downto 0) & c_in & a(15 downto 04);
+ when "0101" => rcrtemp <= a(04) & a(03 downto 0) & c_in & a(15 downto 05);
+ when "0110" => rcrtemp <= a(05) & a(04 downto 0) & c_in & a(15 downto 06);
+ when "0111" => rcrtemp <= a(06) & a(05 downto 0) & c_in & a(15 downto 07);
+ when "1000" => rcrtemp <= a(07) & a(06 downto 0) & c_in & a(15 downto 08);
+ when "1001" => rcrtemp <= a(08) & a(07 downto 0) & c_in & a(15 downto 09);
+ when "1010" => rcrtemp <= a(09) & a(08 downto 0) & c_in & a(15 downto 10);
+ when "1011" => rcrtemp <= a(10) & a(09 downto 0) & c_in & a(15 downto 11);
+ when "1100" => rcrtemp <= a(11) & a(10 downto 0) & c_in & a(15 downto 12);
+ when "1101" => rcrtemp <= a(12) & a(11 downto 0) & c_in & a(15 downto 13);
+ when "1110" => rcrtemp <= a(13) & a(12 downto 0) & c_in & a(15 downto 14);
+ when "1111" => rcrtemp <= a(14) & a(13 downto 0) & c_in & a(15);
+ when others => rcrtemp <= (others => '0');
+ end case;
+ end process;
+
+ with opsel select
+ carry_result <= shltemp when "000",
+ shrtemp when "001",
+ saltemp when "010",
+ sartemp when "011",
+ roltemp when "100",
+ rortemp when "101",
+ rcltemp when "110",
+ rcrtemp when "111",
+ (others => '0') when others;
+
+ result <= carry_result(15 downto 0);
+
+ c_out <= carry_result(16);
+
+ -- overflow is defined for 1-bit shift/rotates
+ process(carry_result, opsel, a) is begin
+ case opsel is
+ when "000" => -- sll
+ ofl_out <= carry_result(15) xor carry_result(16);
+ when "001" => -- slr
+ ofl_out <= a(15);
+ when "010" => -- sal
+ ofl_out <= carry_result(15) xor carry_result(16);
+ when "011" => -- sar
+ ofl_out <= '0';
+ when "100" => -- rol
+ ofl_out <= carry_result(15) xor carry_result(16);
+ when "101" => -- ror
+ ofl_out <= carry_result(15) xor carry_result(14);
+ when "110" => -- rcl
+ ofl_out <= carry_result(15) xor carry_result(16);
+ when "111" => -- rcr
+ ofl_out <= carry_result(15) xor carry_result(14);
+ when others =>
+ ofl_out <= '0';
+ end case;
+ end process;
+
+end dataflow;
Index: trunk/impl0/rtl/vhdl/fcmp.vhd
===================================================================
--- trunk/impl0/rtl/vhdl/fcmp.vhd (nonexistent)
+++ trunk/impl0/rtl/vhdl/fcmp.vhd (revision 2)
@@ -0,0 +1,152 @@
+--------------------------------------------------------------
+-- fcmp.vhd
+--------------------------------------------------------------
+-- project: HPC-16 Microprocessor
+--
+-- usage: helps in conditional execution of jump and interrupts
+--
+-- dependency: none
+--
+-- Author: M. Umair Siddiqui (umairsiddiqui@opencores.org)
+---------------------------------------------------------------
+------------------------------------------------------------------------------------
+-- --
+-- Copyright (c) 2005, M. Umair Siddiqui all rights reserved --
+-- --
+-- This file is part of HPC-16. --
+-- --
+-- HPC-16 is free software; you can redistribute it and/or modify --
+-- it under the terms of the GNU Lesser General Public License as published by --
+-- the Free Software Foundation; either version 2.1 of the License, or --
+-- (at your option) any later version. --
+-- --
+-- HPC-16 is distributed in the hope that it will be useful, --
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
+-- GNU Lesser General Public License for more details. --
+-- --
+-- You should have received a copy of the GNU Lesser General Public License --
+-- along with HPC-16; if not, write to the Free Software --
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
+-- --
+------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+
+entity fcmp is
+ port( tttnField_in : in std_logic_vector(3 downto 0); ---(COSZ)
+ flags_in : in std_logic_vector(3 downto 0);
+ result_out : out std_logic
+ );
+end fcmp;
+
+architecture Behavioral of fcmp is
+ signal CF_in : std_logic;
+ signal OF_in : std_logic;
+ signal SF_in : std_logic;
+ signal ZF_in : std_logic;
+begin
+ process(tttnField_in, flags_in) is
+ begin
+ CF_in <= Flags_in(3);
+ OF_in <= Flags_in(2);
+ SF_in <= Flags_in(1);
+ ZF_in <= Flags_in(0);
+
+ case tttnField_in is
+ when "0000" => -- JO
+ if OF_in = '1' then
+ Result_out <= '1';
+ else
+ Result_out <= '0';
+ end if;
+ when "0001" => -- JNO
+ if OF_in = '0' then
+ Result_out <= '1';
+ else
+ Result_out <= '0';
+ end if;
+ when "0010" => -- JB or JNAE
+ if CF_in = '1' then
+ Result_out <= '1';
+ else
+ Result_out <= '0';
+ end if;
+ when "0011" => -- JNB or JAE
+ if CF_in = '0' then
+ Result_out <= '1';
+ else
+ Result_out <= '0';
+ end if;
+ when "0100" => -- JE or JZ
+ if ZF_in = '1' then
+ Result_out <= '1';
+ else
+ Result_out <= '0';
+ end if;
+ when "0101" => -- JNE or JNZ
+ if ZF_in = '0' then
+ Result_out <= '1';
+ else
+ Result_out <= '0';
+ end if;
+ when "0110" => -- JBE or JNA
+ if (CF_in or ZF_in) = '1' then
+ Result_out <= '1';
+ else
+ Result_out <= '0';
+ end if;
+ when "0111" => -- JNBE or JA
+ if (CF_in or ZF_in) = '0' then
+ Result_out <= '1';
+ else
+ Result_out <= '0';
+ end if;
+ when "1000" => -- JS
+ if SF_in = '1' then
+ Result_out <= '1';
+ else
+ Result_out <= '0';
+ end if;
+ when "1001" => -- JNS
+ if SF_in = '0' then
+ Result_out <= '1';
+ else
+ Result_out <= '0';
+ end if;
+ when "1010" =>
+ Result_out <= '0';
+ when "1011" =>
+ Result_out <= '0';
+ when "1100" => -- JL or JNGE
+ if (SF_in xor OF_in) = '1' then
+ Result_out <= '1';
+ else
+ Result_out <= '0';
+ end if;
+ when "1101" => -- JNL or JGE
+ if (SF_in xor OF_in) = '0' then
+ Result_out <= '1';
+ else
+ Result_out <= '0';
+ end if;
+ when "1110" => -- JLE or JNG
+ if ((SF_in xor OF_in) or ZF_in) = '1' then
+ Result_out <= '1';
+ else
+ Result_out <= '0';
+ end if;
+ when "1111" => -- JNLE or JG
+ if ((SF_in xor OF_in) or ZF_in) = '0' then
+ Result_out <= '1';
+ else
+ Result_out <= '0';
+ end if;
+ when others =>
+ Result_out <= '0';
+ end case;
+ end process;
+
+end Behavioral;
Index: trunk/impl0/rtl/vhdl/cpu.vhd
===================================================================
--- trunk/impl0/rtl/vhdl/cpu.vhd (nonexistent)
+++ trunk/impl0/rtl/vhdl/cpu.vhd (revision 2)
@@ -0,0 +1,199 @@
+--------------------------------------------------------------
+-- cpu.vhd
+--------------------------------------------------------------
+-- project: HPC-16 Microprocessor
+--
+-- usage: main microprocessor, instantiates the datapath and control unit
+-- components and perform interconnection
+--
+-- dependency: cpu_pkg.vhd
+--
+-- Author: M. Umair Siddiqui (umairsiddiqui@opencores.org)
+---------------------------------------------------------------
+------------------------------------------------------------------------------------
+-- --
+-- Copyright (c) 2005, M. Umair Siddiqui all rights reserved --
+-- --
+-- This file is part of HPC-16. --
+-- --
+-- HPC-16 is free software; you can redistribute it and/or modify --
+-- it under the terms of the GNU Lesser General Public License as published by --
+-- the Free Software Foundation; either version 2.1 of the License, or --
+-- (at your option) any later version. --
+-- --
+-- HPC-16 is distributed in the hope that it will be useful, --
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
+-- GNU Lesser General Public License for more details. --
+-- --
+-- You should have received a copy of the GNU Lesser General Public License --
+-- along with HPC-16; if not, write to the Free Software --
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
+-- --
+------------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.cpu_pkg.all;
+entity cpu is
+ generic
+ (
+ pc_preset_value : std_logic_vector(15 downto 0) := X"0000";
+ sp_preset_value : std_logic_vector(15 downto 0) := X"0000"
+ );
+ port(
+ CLK_I : in std_logic;
+ RST_I : in std_logic;
+ ACK_I : in std_logic;
+ INTR_I : in std_logic;
+ --
+ SEL_O : out std_logic_vector(1 downto 0);
+ STB_O : out std_logic;
+ CYC_O : out std_logic;
+ WE_O : out std_logic;
+ --
+ INTA_CYC_O : out std_logic;
+ I_CYC_O : out std_logic;
+ C_CYC_O : out std_logic;
+ D_CYC_O : out std_logic;
+ --
+ DAT_IO : inout std_logic_vector(15 downto 0);
+ ADR_O : out std_logic_vector(15 downto 0)
+ );
+end cpu;
+
+architecture struct of cpu is
+ signal jcc_ok , int_flag , pc0 , sp0 , mar0 , tr20, intr_ce, ir_ce ,
+ mdri_ce, mdri_hl_zse_sign, rf_adwe, pc_pre, pc_ce,
+ spin_mux_sel, sp_pre, sp_ce, dfh_ce,
+ sbin_mux_sel, asresult_mux_sel, coszin_mux_sel,
+ flags_rst, flags_ce, flags_cfce, flags_ifce,
+ flags_clc, flags_cmc, flags_stc, flags_cli, flags_sti,
+ mar_ce, mdro_ce, mdro_oe : std_logic;
+
+ signal ir_high : std_logic_vector(7 downto 0);
+
+ signal intno_mux_sel, adin_mux_sel,
+ alub_mux_sel, aopsel, sopsel, mdroin_mux_sel : std_logic_vector(2 downto 0);
+
+ signal pcin_mux_sel, alua_mux_sel, marin_mux_sel : std_logic_vector(1 downto 0);
+
+
+
+begin
+
+ assert pc_preset_value(0) = '0' and sp_preset_value(0) = '0'
+ report "the preset values of sp and pc should be even"
+ severity failure;
+
+ control: con1
+ PORT MAP(
+ CLK_I => CLK_I,
+ RST_I => RST_I,
+ ACK_I => ACK_I,
+ INTR_I => INTR_I,
+ SEL_O => SEL_O,
+ STB_O => STB_O,
+ CYC_O => CYC_O,
+ WE_O => WE_O,
+ INTA_CYC_O => INTA_CYC_O,
+ C_CYC_O => C_CYC_O,
+ I_CYC_O => I_CYC_O,
+ D_CYC_O => D_CYC_O,
+ jcc_ok => jcc_ok,
+ int_flag => int_flag,
+ pc0 => pc0,
+ sp0 => sp0,
+ mar0 => mar0,
+ tr20 => tr20,
+ ir_high => ir_high,
+ intr_ce => intr_ce,
+ ir_ce => ir_ce,
+ mdri_ce => mdri_ce,
+ mdri_hl_zse_sign => mdri_hl_zse_sign,
+ intno_mux_sel => intno_mux_sel,
+ adin_mux_sel => adin_mux_sel,
+ rf_adwe => rf_adwe,
+ pcin_mux_sel => pcin_mux_sel,
+ pc_pre => pc_pre,
+ pc_ce => pc_ce,
+ spin_mux_sel => spin_mux_sel,
+ sp_pre => sp_pre,
+ sp_ce => sp_ce,
+ dfh_ce => dfh_ce,
+ alua_mux_sel => alua_mux_sel,
+ alub_mux_sel => alub_mux_sel,
+ aopsel => aopsel,
+ sopsel => sopsel,
+ sbin_mux_sel => sbin_mux_sel,
+ asresult_mux_sel => asresult_mux_sel,
+ coszin_mux_sel => coszin_mux_sel,
+ flags_rst => flags_rst,
+ flags_ce => flags_ce,
+ flags_cfce => flags_cfce,
+ flags_ifce => flags_ifce,
+ flags_clc => flags_clc,
+ flags_cmc => flags_cmc,
+ flags_stc => flags_stc,
+ flags_cli => flags_cli,
+ flags_sti => flags_sti,
+ marin_mux_sel => marin_mux_sel,
+ mar_ce => mar_ce,
+ mdroin_mux_sel => mdroin_mux_sel,
+ mdro_ce => mdro_ce,
+ mdro_oe => mdro_oe
+ );
+
+ datapath : dp
+ generic map
+ (
+ pc_preset_value => pc_preset_value,
+ sp_preset_value => sp_preset_value
+ )
+ PORT MAP(
+ CLK_I => CLK_I,
+ DAT_IO => DAT_IO,
+ ADR_O => ADR_O,
+ jcc_ok => jcc_ok,
+ int_flag => int_flag,
+ pc0 => pc0,
+ sp0 => sp0,
+ mar0 => mar0,
+ tr20 => tr20,
+ ir_high => ir_high,
+ intr_ce => intr_ce,
+ ir_ce => ir_ce,
+ mdri_ce => mdri_ce,
+ mdri_hl_zse_sign => mdri_hl_zse_sign,
+ intno_mux_sel => intno_mux_sel,
+ adin_mux_sel => adin_mux_sel,
+ rf_adwe => rf_adwe,
+ pcin_mux_sel => pcin_mux_sel,
+ pc_pre => pc_pre,
+ pc_ce => pc_ce,
+ spin_mux_sel => spin_mux_sel,
+ sp_pre => sp_pre,
+ sp_ce => sp_ce,
+ dfh_ce => dfh_ce,
+ alua_mux_sel => alua_mux_sel,
+ alub_mux_sel => alub_mux_sel,
+ aopsel => aopsel,
+ sopsel => sopsel,
+ sbin_mux_sel => sbin_mux_sel,
+ asresult_mux_sel => asresult_mux_sel,
+ coszin_mux_sel => coszin_mux_sel,
+ flags_rst => flags_rst,
+ flags_ce => flags_ce,
+ flags_cfce => flags_cfce,
+ flags_ifce => flags_ifce,
+ flags_clc => flags_clc,
+ flags_cmc => flags_cmc,
+ flags_stc => flags_stc,
+ flags_cli => flags_cli,
+ flags_sti => flags_sti,
+ marin_mux_sel => marin_mux_sel,
+ mar_ce => mar_ce,
+ mdroin_mux_sel => mdroin_mux_sel,
+ mdro_ce => mdro_ce,
+ mdro_oe => mdro_oe
+ );
+end struct;
\ No newline at end of file
Index: trunk/impl0/rtl/vhdl/cpu_pkg.vhd
===================================================================
--- trunk/impl0/rtl/vhdl/cpu_pkg.vhd (nonexistent)
+++ trunk/impl0/rtl/vhdl/cpu_pkg.vhd (revision 2)
@@ -0,0 +1,149 @@
+--------------------------------------------------------------
+-- cpu_pkg.vhd
+--------------------------------------------------------------
+-- project: HPC-16 Microprocessor
+--
+-- usage: component declaration of datapath and control unit
+--
+-- dependency: dp.vhd, con1.vhd
+--
+-- Author: M. Umair Siddiqui (umairsiddiqui@opencores.org)
+---------------------------------------------------------------
+------------------------------------------------------------------------------------
+-- --
+-- Copyright (c) 2005, M. Umair Siddiqui all rights reserved --
+-- --
+-- This file is part of HPC-16. --
+-- --
+-- HPC-16 is free software; you can redistribute it and/or modify --
+-- it under the terms of the GNU Lesser General Public License as published by --
+-- the Free Software Foundation; either version 2.1 of the License, or --
+-- (at your option) any later version. --
+-- --
+-- HPC-16 is distributed in the hope that it will be useful, --
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
+-- GNU Lesser General Public License for more details. --
+-- --
+-- You should have received a copy of the GNU Lesser General Public License --
+-- along with HPC-16; if not, write to the Free Software --
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
+-- --
+------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+package cpu_pkg is
+ COMPONENT con1
+ PORT(
+ CLK_I : IN std_logic;
+ RST_I : IN std_logic;
+ ACK_I : IN std_logic;
+ INTR_I : IN std_logic;
+ jcc_ok : IN std_logic;
+ int_flag : IN std_logic;
+ pc0 : IN std_logic;
+ sp0 : IN std_logic;
+ mar0 : IN std_logic;
+ tr20 : IN std_logic;
+ ir_high : IN std_logic_vector(7 downto 0);
+ SEL_O : OUT std_logic_vector(1 downto 0);
+ STB_O : OUT std_logic;
+ CYC_O : OUT std_logic;
+ WE_O : OUT std_logic;
+ INTA_CYC_O : OUT std_logic;
+ C_CYC_O : OUT std_logic;
+ I_CYC_O : OUT std_logic;
+ D_CYC_O : OUT std_logic;
+ intr_ce : OUT std_logic;
+ ir_ce : OUT std_logic;
+ mdri_ce : OUT std_logic;
+ mdri_hl_zse_sign : OUT std_logic;
+ intno_mux_sel : OUT std_logic_vector(2 downto 0);
+ adin_mux_sel : OUT std_logic_vector(2 downto 0);
+ rf_adwe : OUT std_logic;
+ pcin_mux_sel : OUT std_logic_vector(1 downto 0);
+ pc_pre : OUT std_logic;
+ pc_ce : OUT std_logic;
+ spin_mux_sel : OUT std_logic;
+ sp_pre : OUT std_logic;
+ sp_ce : OUT std_logic;
+ dfh_ce : OUT std_logic;
+ alua_mux_sel : OUT std_logic_vector(1 downto 0);
+ alub_mux_sel : OUT std_logic_vector(2 downto 0);
+ aopsel : OUT std_logic_vector(2 downto 0);
+ sopsel : OUT std_logic_vector(2 downto 0);
+ sbin_mux_sel : OUT std_logic;
+ asresult_mux_sel : OUT std_logic;
+ coszin_mux_sel : OUT std_logic;
+ flags_rst : OUT std_logic;
+ flags_ce : OUT std_logic;
+ flags_cfce : OUT std_logic;
+ flags_ifce : OUT std_logic;
+ flags_clc : OUT std_logic;
+ flags_cmc : OUT std_logic;
+ flags_stc : OUT std_logic;
+ flags_cli : OUT std_logic;
+ flags_sti : OUT std_logic;
+ marin_mux_sel : OUT std_logic_vector(1 downto 0);
+ mar_ce : OUT std_logic;
+ mdroin_mux_sel : OUT std_logic_vector(2 downto 0);
+ mdro_ce : OUT std_logic;
+ mdro_oe : OUT std_logic
+ );
+ END COMPONENT;
+ COMPONENT dp
+ generic
+ ( pc_preset_value : std_logic_vector(15 downto 0) ;
+ sp_preset_value : std_logic_vector(15 downto 0)
+ );
+ PORT(
+ CLK_I : IN std_logic;
+ intr_ce : IN std_logic;
+ ir_ce : IN std_logic;
+ mdri_ce : IN std_logic;
+ mdri_hl_zse_sign : IN std_logic;
+ intno_mux_sel : IN std_logic_vector(2 downto 0);
+ adin_mux_sel : IN std_logic_vector(2 downto 0);
+ rf_adwe : IN std_logic;
+ pcin_mux_sel : IN std_logic_vector(1 downto 0);
+ pc_pre : IN std_logic;
+ pc_ce : IN std_logic;
+ spin_mux_sel : IN std_logic;
+ sp_pre : IN std_logic;
+ sp_ce : IN std_logic;
+ dfh_ce : IN std_logic;
+ alua_mux_sel : IN std_logic_vector(1 downto 0);
+ alub_mux_sel : IN std_logic_vector(2 downto 0);
+ aopsel : IN std_logic_vector(2 downto 0);
+ sopsel : IN std_logic_vector(2 downto 0);
+ sbin_mux_sel : IN std_logic;
+ asresult_mux_sel : IN std_logic;
+ coszin_mux_sel : IN std_logic;
+ flags_rst : IN std_logic;
+ flags_ce : IN std_logic;
+ flags_cfce : IN std_logic;
+ flags_ifce : IN std_logic;
+ flags_clc : IN std_logic;
+ flags_cmc : IN std_logic;
+ flags_stc : IN std_logic;
+ flags_cli : IN std_logic;
+ flags_sti : IN std_logic;
+ marin_mux_sel : IN std_logic_vector(1 downto 0);
+ mar_ce : IN std_logic;
+ mdroin_mux_sel : IN std_logic_vector(2 downto 0);
+ mdro_ce : IN std_logic;
+ mdro_oe : IN std_logic;
+ DAT_IO : INOUT std_logic_vector(15 downto 0);
+ ADR_O : OUT std_logic_vector(15 downto 0);
+ jcc_ok : OUT std_logic;
+ int_flag : OUT std_logic;
+ pc0 : OUT std_logic;
+ sp0 : OUT std_logic;
+ mar0 : OUT std_logic;
+ tr20 : OUT std_logic;
+ ir_high : OUT std_logic_vector(7 downto 0)
+ );
+ END COMPONENT;
+end cpu_pkg;
\ No newline at end of file
Index: trunk/impl0/rtl/vhdl/flags.vhd
===================================================================
--- trunk/impl0/rtl/vhdl/flags.vhd (nonexistent)
+++ trunk/impl0/rtl/vhdl/flags.vhd (revision 2)
@@ -0,0 +1,110 @@
+--------------------------------------------------------------
+-- flags.vhd
+--------------------------------------------------------------
+-- project: HPC-16 Microprocessor
+--
+-- usage: FLAGS register implementation
+--
+-- dependency: none
+--
+-- Author: M. Umair Siddiqui (umairsiddiqui@opencores.org)
+---------------------------------------------------------------
+------------------------------------------------------------------------------------
+-- --
+-- Copyright (c) 2005, M. Umair Siddiqui all rights reserved --
+-- --
+-- This file is part of HPC-16. --
+-- --
+-- HPC-16 is free software; you can redistribute it and/or modify --
+-- it under the terms of the GNU Lesser General Public License as published by --
+-- the Free Software Foundation; either version 2.1 of the License, or --
+-- (at your option) any later version. --
+-- --
+-- HPC-16 is distributed in the hope that it will be useful, --
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
+-- GNU Lesser General Public License for more details. --
+-- --
+-- You should have received a copy of the GNU Lesser General Public License --
+-- along with HPC-16; if not, write to the Free Software --
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
+-- --
+------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity flags is
+ port(
+
+ Flags_in : in std_logic_vector(4 downto 0);
+
+ CLK_in : in std_logic;
+
+ ResetAll_in : in std_logic;
+ CE_in : in std_logic;
+ CFCE_in : in std_logic;
+ IFCE_in : in std_logic;
+ CLC_in : in std_logic;
+ CMC_in : in std_logic;
+ STC_in : in std_logic;
+ STI_in : in std_logic;
+ CLI_in : in std_logic;
+
+ Flags_out : out std_logic_vector(4 downto 0)
+
+ );
+
+end flags;
+
+architecture Behavioral of flags is
+ signal CF_in : std_logic;
+ signal OF_in : std_logic;
+ signal SF_in : std_logic;
+ signal ZF_in : std_logic;
+ signal IF_in : std_logic;
+ signal CFout_temp : std_logic;
+ signal OFout_temp : std_logic;
+ signal SFout_temp : std_logic;
+ signal ZFout_temp : std_logic;
+ signal IFout_temp : std_logic;
+begin
+
+ (CF_in, OF_in, SF_in, ZF_in, IF_in) <= Flags_in;
+
+ process(Clk_in, ResetAll_in) is
+ begin
+ if ResetAll_in = '1' then
+ CFout_temp <= '0';
+ OFout_temp <= '0';
+ SFout_temp <= '0';
+ ZFout_temp <= '0';
+ IFout_temp <= '0';
+ elsif rising_edge(CLK_in) then
+ if STI_in = '1' then
+ IFout_temp <= '1';
+ elsif CLI_in = '1' then
+ IFout_temp <= '0';
+ elsif STC_in = '1' then
+ CFout_temp <= '1';
+ elsif CLC_in = '1' then
+ CFout_temp <= '0';
+ elsif CMC_in = '1' then
+ CFout_temp <= not CFout_temp;
+ elsif CE_in = '1' then
+ if CFCE_in = '1' then
+ CFout_temp <= CF_in;
+ end if;
+ if IFCE_in = '1' then
+ IFout_temp <= IF_in;
+ end if;
+ SFout_temp <= SF_in;
+ OFout_temp <= OF_in;
+ ZFout_temp <= ZF_in;
+ end if;
+ end if;
+ end process;
+
+ Flags_out <= (CFout_temp, OFout_temp, SFout_temp, ZFout_temp, IFout_temp);
+
+end Behavioral;
Index: trunk/impl0/rtl/vhdl/sync.vhd
===================================================================
--- trunk/impl0/rtl/vhdl/sync.vhd (nonexistent)
+++ trunk/impl0/rtl/vhdl/sync.vhd (revision 2)
@@ -0,0 +1,76 @@
+--------------------------------------------------------------
+-- sync.vhd
+--------------------------------------------------------------
+-- project: HPC-16 Microprocessor
+--
+-- usage: synchronizer, 2 cascaded DFF
+--
+-- dependency: none
+--
+-- Author: M. Umair Siddiqui (umairsiddiqui@opencores.org)
+---------------------------------------------------------------
+------------------------------------------------------------------------------------
+-- --
+-- Copyright (c) 2005, M. Umair Siddiqui all rights reserved --
+-- --
+-- This file is part of HPC-16. --
+-- --
+-- HPC-16 is free software; you can redistribute it and/or modify --
+-- it under the terms of the GNU Lesser General Public License as published by --
+-- the Free Software Foundation; either version 2.1 of the License, or --
+-- (at your option) any later version. --
+-- --
+-- HPC-16 is distributed in the hope that it will be useful, --
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
+-- GNU Lesser General Public License for more details. --
+-- --
+-- You should have received a copy of the GNU Lesser General Public License --
+-- along with HPC-16; if not, write to the Free Software --
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
+-- --
+------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+
+entity sync is
+ port
+ (
+ d : in std_logic;
+ clk : in std_logic;
+ q : out std_logic
+ );
+end sync;
+
+architecture Behavioral of sync is
+ signal t : std_logic;
+begin
+ process(clk)
+ begin
+ if rising_edge(CLK) then
+ t <= d;
+ q <= t;
+ end if;
+ end process;
+end Behavioral;
+
+architecture behave2 of sync is
+ signal t : std_logic;
+begin
+ process(clk , d)
+ begin
+ if d = '1' then
+ t <= '1';
+ q <= '1';
+ elsif rising_edge(clk) then
+ t <= '0';
+ q <= t;
+ end if;
+ end process;
+end behave2;
+
+
+
+
\ No newline at end of file
Index: trunk/impl0/rtl/vhdl/regfile.vhd
===================================================================
--- trunk/impl0/rtl/vhdl/regfile.vhd (nonexistent)
+++ trunk/impl0/rtl/vhdl/regfile.vhd (revision 2)
@@ -0,0 +1,66 @@
+--------------------------------------------------------------
+-- regfile.vhd
+--------------------------------------------------------------
+-- project: HPC-16 Microprocessor
+--
+-- usage: register file with async read and sync write operations
+--
+-- dependency: none
+--
+-- Author: M. Umair Siddiqui (umairsiddiqui@opencores.org)
+---------------------------------------------------------------
+------------------------------------------------------------------------------------
+-- --
+-- Copyright (c) 2005, M. Umair Siddiqui all rights reserved --
+-- --
+-- This file is part of HPC-16. --
+-- --
+-- HPC-16 is free software; you can redistribute it and/or modify --
+-- it under the terms of the GNU Lesser General Public License as published by --
+-- the Free Software Foundation; either version 2.1 of the License, or --
+-- (at your option) any later version. --
+-- --
+-- HPC-16 is distributed in the hope that it will be useful, --
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
+-- GNU Lesser General Public License for more details. --
+-- --
+-- You should have received a copy of the GNU Lesser General Public License --
+-- along with HPC-16; if not, write to the Free Software --
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
+-- --
+------------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use ieee.std_logic_unsigned.all;
+
+
+entity regfile is
+ port(
+ aadr : in std_logic_vector(3 downto 0);
+ badr : in std_logic_vector(3 downto 0);
+ ad : in std_logic_vector(15 downto 0);
+ adwe : in std_logic;
+ clk : in std_logic;
+ aq : out std_logic_vector(15 downto 0);
+ bq : out std_logic_vector(15 downto 0)
+ );
+end regfile;
+
+architecture Behavioral of regfile is
+ type regfile_type is array(0 to 15) of std_logic_vector(15 downto 0);
+ signal regfile_data : regfile_type;
+begin
+ process(clk)
+ begin
+ if rising_edge(clk) then
+ if adwe = '1' then
+ regfile_data(conv_integer(aadr)) <= ad;
+ end if;
+ end if;
+ end process;
+ aq <= regfile_data(conv_integer(aadr));
+ bq <= regfile_data(conv_integer(badr));
+end Behavioral;
Index: trunk/impl0/docs/vhdl_impl0_testing.doc
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/impl0/docs/vhdl_impl0_testing.doc
===================================================================
--- trunk/impl0/docs/vhdl_impl0_testing.doc (nonexistent)
+++ trunk/impl0/docs/vhdl_impl0_testing.doc (revision 2)
trunk/impl0/docs/vhdl_impl0_testing.doc
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/impl0/docs/vhdl_impl0.doc
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/impl0/docs/vhdl_impl0.doc
===================================================================
--- trunk/impl0/docs/vhdl_impl0.doc (nonexistent)
+++ trunk/impl0/docs/vhdl_impl0.doc (revision 2)
trunk/impl0/docs/vhdl_impl0.doc
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/impl0/docs/impl0_organization.doc
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/impl0/docs/impl0_organization.doc
===================================================================
--- trunk/impl0/docs/impl0_organization.doc (nonexistent)
+++ trunk/impl0/docs/impl0_organization.doc (revision 2)
trunk/impl0/docs/impl0_organization.doc
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/impl0/sim/testbench/test.vhd
===================================================================
--- trunk/impl0/sim/testbench/test.vhd (nonexistent)
+++ trunk/impl0/sim/testbench/test.vhd (revision 2)
@@ -0,0 +1,228 @@
+--------------------------------------------------------------
+-- test.vhd
+--------------------------------------------------------------
+-- project: HPC-16 Microprocessor
+--
+-- usage: basic testbench top-level
+--
+-- dependency: cpu.vhd, ramNx16.vhd, ram8x16.vhd
+--
+-- Author: M. Umair Siddiqui (umairsiddiqui@opencores.org)
+---------------------------------------------------------------
+------------------------------------------------------------------------------------
+-- --
+-- Copyright (c) 2005, M. Umair Siddiqui all rights reserved --
+-- --
+-- This file is part of HPC-16. --
+-- --
+-- HPC-16 is free software; you can redistribute it and/or modify --
+-- it under the terms of the GNU Lesser General Public License as published by --
+-- the Free Software Foundation; either version 2.1 of the License, or --
+-- (at your option) any later version. --
+-- --
+-- HPC-16 is distributed in the hope that it will be useful, --
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
+-- GNU Lesser General Public License for more details. --
+-- --
+-- You should have received a copy of the GNU Lesser General Public License --
+-- along with HPC-16; if not, write to the Free Software --
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
+-- --
+------------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+-----------------------------------------------------------
+entity test is
+ generic
+ (
+ clk_period : time := 40 ns;
+ half_clk_period : time := 20 ns;
+ --
+ cpu_pc_preset_value : std_logic_vector(15 downto 0) := X"0000";
+ cpu_sp_preset_value : std_logic_vector(15 downto 0) := X"001e";
+ --
+ ram_adr_width : integer := 4;
+
+ file_name_prefix : string := "add2";
+ sim_stop_time : time := 3000 ns;
+ --
+ ram2_adr : std_logic_vector(15 downto 0) := X"ff00";
+
+ ram2_init_0 : std_logic_vector(15 downto 0) := X"7fff";
+ ram2_init_1 : std_logic_vector(15 downto 0) := X"0001";
+ ram2_init_2 : std_logic_vector(15 downto 0) := (others => '0');
+ ram2_init_3 : std_logic_vector(15 downto 0) := (others => '0');
+ ram2_init_4 : std_logic_vector(15 downto 0) := (others => '0');
+ ram2_init_5 : std_logic_vector(15 downto 0) := (others => '0');
+ ram2_init_6 : std_logic_vector(15 downto 0) := (others => '0');
+ ram2_init_7 : std_logic_vector(15 downto 0) := (others => '0')
+ );
+end test;
+
+architecture sim of test is
+ ----------------------------------------
+ -- cpu interface signal
+ ----------------------------------------
+ signal clk_i : std_logic;
+ signal rst_i : std_logic;
+ signal ack_i : std_logic;
+ signal intr_i : std_logic;
+ --
+ signal sel_o : std_logic_vector(1 downto 0);
+ signal stb_o : std_logic;
+ signal cyc_o : std_logic;
+ signal we_o : std_logic;
+ --
+ signal inta_cyc_o : std_logic;
+ signal i_cyc_o : std_logic;
+ signal c_cyc_o : std_logic;
+ signal d_cyc_o : std_logic;
+ --
+ signal adr_o : std_logic_vector(15 downto 0);
+ signal dat_io : std_logic_vector(15 downto 0);
+ -----------------------------------------
+ -- ram interfacing
+ -----------------------------------------
+ signal ram_cs : std_logic;
+ signal ram_oe : std_logic;
+ --
+ signal ram2_cs : std_logic;
+ signal ram2_oe : std_logic;
+begin
+ ------------------------------------------------------------------------
+ ram_cs_gen : process(stb_o, adr_o)
+ variable temp : integer;
+ constant max_loc : integer := (2 ** (ram_adr_width + 1)) - 1;
+ begin
+ if stb_o = '1' then
+ temp := conv_integer(adr_o);
+ if 0 <= temp and temp <= max_loc then
+ ram_cs <= '1';
+ else
+ ram_cs <= '0';
+ end if;
+ end if;
+ end process ram_cs_gen;
+ ----------------------------------------------------------------------
+ ram_oe <= not we_o;
+ ----------------------------------------------------------------------
+ clk_gen : process
+ begin
+ clk_i <= '1';
+ wait for half_clk_period;
+ clk_i <= '0';
+ wait for half_clk_period;
+ if now >= sim_stop_time then
+ assert false
+ report "simulation completed (not an error)"
+ severity error;
+ wait;
+ end if;
+ end process;
+ -----------------------------------------------------------------------
+ rst_gen : process
+ begin
+ rst_i <= '1';
+ wait for 4 * clk_period;
+ rst_i <= '0';
+ wait;
+ end process;
+ -----------------------------------------------------------------------
+ ram: entity work.ramNx16(async)
+ generic map
+ (
+ init_file_name => file_name_prefix & "_init_ram.txt",
+ adr_width => ram_adr_width
+
+ )
+ port map
+ (
+ clk => clk_i,
+ adr => adr_o(ram_adr_width downto 1),
+ dat_i => dat_io,
+ --
+ cs => ram_cs,
+ we => we_o,
+ ub => sel_o(1),
+ lb => sel_o(0),
+ oe => ram_oe,
+ --
+ dat_o => dat_io
+ );
+ -------------------------------------------------------------------------
+ cpu : entity work.cpu
+ generic map
+ (
+ pc_preset_value => cpu_pc_preset_value,
+ sp_preset_value => cpu_sp_preset_value
+ )
+ port map
+ (
+ CLK_I => clk_i,
+ RST_I => rst_i,
+ ACK_I => ack_i,
+ INTR_I => intr_i,
+ --
+ SEL_O => sel_o,
+ STB_O => stb_o,
+ CYC_O => cyc_o,
+ WE_O => we_o,
+ --
+ INTA_CYC_O => inta_cyc_o,
+ I_CYC_O => i_cyc_o,
+ C_CYC_O => c_cyc_o,
+ D_CYC_O => d_cyc_o,
+ --
+ DAT_IO => dat_io,
+ ADR_O => adr_o
+ );
+--------------------------------------------------
+ ack_gen : ack_i <= stb_o;
+--------------------------------------------------
+ram2: entity work.ram8x16
+ generic map
+ (
+ init_0 => ram2_init_0,
+ init_1 => ram2_init_1,
+ init_2 => ram2_init_2,
+ init_3 => ram2_init_3,
+ init_4 => ram2_init_4,
+ init_5 => ram2_init_5,
+ init_6 => ram2_init_6,
+ init_7 => ram2_init_7
+
+ )
+ port map
+ (
+ clk => clk_i,
+ adr => adr_o(3 downto 1),
+ dat_i => dat_io,
+ --
+ cs => ram2_cs,
+ we => we_o,
+ ub => sel_o(1),
+ lb => sel_o(0),
+ oe => ram2_oe,
+ --
+ dat_o => dat_io
+ );
+-----------------------------------------------
+ ram2_oe <= not we_o;
+----------------------------------------------
+ ram2_cs_gen : process(stb_o, adr_o)
+ variable temp : integer;
+ constant max_loc : integer := conv_integer(ram2_adr) + 15;
+ begin
+ if stb_o = '1' then
+ temp := conv_integer(adr_o);
+ if ram2_adr <= temp and temp <= max_loc then
+ ram2_cs <= '1';
+ else
+ ram2_cs <= '0';
+ end if;
+ end if;
+ end process ram2_cs_gen;
+end sim;
\ No newline at end of file
Index: trunk/impl0/sim/testbench/ram8x16.vhd
===================================================================
--- trunk/impl0/sim/testbench/ram8x16.vhd (nonexistent)
+++ trunk/impl0/sim/testbench/ram8x16.vhd (revision 2)
@@ -0,0 +1,122 @@
+--------------------------------------------------------------
+-- ram8x16.vhd
+--------------------------------------------------------------
+-- project: HPC-16 Microprocessor
+--
+-- usage: RAM with async read and sync write operation (not synthsizable, without timing params)
+--
+-- dependency: none
+--
+-- Author: M. Umair Siddiqui (umairsiddiqui@opencores.org)
+---------------------------------------------------------------
+------------------------------------------------------------------------------------
+-- --
+-- Copyright (c) 2005, M. Umair Siddiqui all rights reserved --
+-- --
+-- This file is part of HPC-16. --
+-- --
+-- HPC-16 is free software; you can redistribute it and/or modify --
+-- it under the terms of the GNU Lesser General Public License as published by --
+-- the Free Software Foundation; either version 2.1 of the License, or --
+-- (at your option) any later version. --
+-- --
+-- HPC-16 is distributed in the hope that it will be useful, --
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
+-- GNU Lesser General Public License for more details. --
+-- --
+-- You should have received a copy of the GNU Lesser General Public License --
+-- along with HPC-16; if not, write to the Free Software --
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
+-- --
+------------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+---------------------------------------------
+entity ram8x16 is
+ generic
+ (
+ init_0 : std_logic_vector(15 downto 0) := (others => '0');
+ init_1 : std_logic_vector(15 downto 0) := (others => '0');
+ init_2 : std_logic_vector(15 downto 0) := (others => '0');
+ init_3 : std_logic_vector(15 downto 0) := (others => '0');
+ init_4 : std_logic_vector(15 downto 0) := (others => '0');
+ init_5 : std_logic_vector(15 downto 0) := (others => '0');
+ init_6 : std_logic_vector(15 downto 0) := (others => '0');
+ init_7 : std_logic_vector(15 downto 0) := (others => '0')
+ );
+ port
+ (
+ clk : in std_logic;
+ adr : in std_logic_vector(2 downto 0);
+ dat_i : in std_logic_vector(15 downto 0);
+ --
+ cs : in std_logic;
+ we : in std_logic;
+ ub : in std_logic;
+ lb : in std_logic;
+ oe : in std_logic;
+ --
+ dat_o : out std_logic_vector(15 downto 0)
+ );
+end ram8x16;
+-------------------------------------------
+architecture sim of ram8x16 is
+ type rtype is array(0 to 7) of std_logic_vector(7 downto 0);
+ shared variable ram_data_lower : rtype := ( init_0(7 downto 0),
+ init_1(7 downto 0),
+ init_2(7 downto 0),
+ init_3(7 downto 0),
+ init_4(7 downto 0),
+ init_5(7 downto 0),
+ init_6(7 downto 0),
+ init_7(7 downto 0));
+ shared variable ram_data_upper : rtype := ( init_0(15 downto 8),
+ init_1(15 downto 8),
+ init_2(15 downto 8),
+ init_3(15 downto 8),
+ init_4(15 downto 8),
+ init_5(15 downto 8),
+ init_6(15 downto 8),
+ init_7(15 downto 8));
+
+ signal write_lower : std_logic;
+ signal write_upper : std_logic;
+ signal out_lower : std_logic;
+ signal out_upper : std_logic;
+begin
+ ----------------------------------------------------------------------------
+ -- main
+ ----------------------------------------------------------------------------
+ write_low: write_lower <= cs and we and lb;
+ write_up : write_upper <= cs and we and ub;
+ ----------------------------------------------------------------------------
+ upper: process(clk)
+ begin
+ if rising_edge(clk) then
+ if write_upper = '1' then
+ ram_data_upper(conv_integer(adr)) := dat_i(15 downto 8);
+ end if;
+ end if;
+ end process upper;
+ ----------------------------------------------------------------------------
+ lower: process(clk)
+ begin
+ if rising_edge(clk) then
+ if write_lower = '1' then
+ ram_data_lower(conv_integer(adr)) := dat_i(7 downto 0);
+ end if;
+ end if;
+ end process lower;
+ -----------------------------------------------------------------------
+ out_low : out_lower <= cs and (not we) and lb and oe;
+ out_up : out_upper <= cs and (not we) and ub and oe;
+ ----------------------------------------------------------------------
+ dat_up : dat_o(15 downto 8) <= ram_data_upper(conv_integer(adr)) when out_upper = '1' else
+ (others => 'Z');
+ dat_low : dat_o(7 downto 0) <= ram_data_lower(conv_integer(adr)) when out_lower = '1' else
+ (others => 'Z');
+ ----------------------------------------------------------------------
+end sim;
Index: trunk/impl0/sim/testbench/arith.vhd
===================================================================
--- trunk/impl0/sim/testbench/arith.vhd (nonexistent)
+++ trunk/impl0/sim/testbench/arith.vhd (revision 2)
@@ -0,0 +1,571 @@
+-- VHDL model created from D:\installed-software\xilinx\spartan3\data\drawing\m2_1.sch - Tue Jul 19 11:19:51 2005
+
+
+library ieee;
+use ieee.std_logic_1164.ALL;
+use ieee.numeric_std.ALL;
+-- synopsys translate_off
+library UNISIM;
+use UNISIM.Vcomponents.ALL;
+-- synopsys translate_on
+
+entity M2_1_MXILINX_arith is
+ port ( D0 : in std_logic;
+ D1 : in std_logic;
+ S0 : in std_logic;
+ O : out std_logic);
+end M2_1_MXILINX_arith;
+
+architecture BEHAVIORAL of M2_1_MXILINX_arith is
+ attribute BOX_TYPE : STRING ;
+ signal M0 : std_logic;
+ signal M1 : std_logic;
+ component AND2B1
+ port ( I0 : in std_logic;
+ I1 : in std_logic;
+ O : out std_logic);
+ end component;
+ attribute BOX_TYPE of AND2B1 : COMPONENT is "BLACK_BOX";
+
+ component OR2
+ port ( I0 : in std_logic;
+ I1 : in std_logic;
+ O : out std_logic);
+ end component;
+ attribute BOX_TYPE of OR2 : COMPONENT is "BLACK_BOX";
+
+ component AND2
+ port ( I0 : in std_logic;
+ I1 : in std_logic;
+ O : out std_logic);
+ end component;
+ attribute BOX_TYPE of AND2 : COMPONENT is "BLACK_BOX";
+
+begin
+ I_36_7 : AND2B1
+ port map (I0=>S0, I1=>D0, O=>M0);
+
+ I_36_8 : OR2
+ port map (I0=>M1, I1=>M0, O=>O);
+
+ I_36_9 : AND2
+ port map (I0=>D1, I1=>S0, O=>M1);
+
+end BEHAVIORAL;
+
+
+-- VHDL model created from D:\installed-software\xilinx\spartan3\data\drawing\adsu16.sch - Tue Jul 19 11:19:52 2005
+
+
+library ieee;
+use ieee.std_logic_1164.ALL;
+use ieee.numeric_std.ALL;
+-- synopsys translate_off
+library UNISIM;
+use UNISIM.Vcomponents.ALL;
+-- synopsys translate_on
+
+entity ADSU16_MXILINX_arith is
+ port ( A : in std_logic_vector (15 downto 0);
+ ADD : in std_logic;
+ B : in std_logic_vector (15 downto 0);
+ CI : in std_logic;
+ CO : out std_logic;
+ OFL : out std_logic;
+ S : out std_logic_vector (15 downto 0));
+end ADSU16_MXILINX_arith;
+
+architecture BEHAVIORAL of ADSU16_MXILINX_arith is
+ attribute BOX_TYPE : STRING ;
+ attribute RLOC : STRING ;
+ signal C0 : std_logic;
+ signal C1 : std_logic;
+ signal C2 : std_logic;
+ signal C3 : std_logic;
+ signal C4 : std_logic;
+ signal C5 : std_logic;
+ signal C6 : std_logic;
+ signal C7 : std_logic;
+ signal C8 : std_logic;
+ signal C9 : std_logic;
+ signal C10 : std_logic;
+ signal C11 : std_logic;
+ signal C12 : std_logic;
+ signal C13 : std_logic;
+ signal C14 : std_logic;
+ signal C14O : std_logic;
+ signal dummy : std_logic;
+ signal I0 : std_logic;
+ signal I1 : std_logic;
+ signal I2 : std_logic;
+ signal I3 : std_logic;
+ signal I4 : std_logic;
+ signal I5 : std_logic;
+ signal I6 : std_logic;
+ signal I7 : std_logic;
+ signal I8 : std_logic;
+ signal I9 : std_logic;
+ signal I10 : std_logic;
+ signal I11 : std_logic;
+ signal I12 : std_logic;
+ signal I13 : std_logic;
+ signal I14 : std_logic;
+ signal I15 : std_logic;
+ signal SUB0 : std_logic;
+ signal SUB1 : std_logic;
+ signal SUB2 : std_logic;
+ signal SUB3 : std_logic;
+ signal SUB4 : std_logic;
+ signal SUB5 : std_logic;
+ signal SUB6 : std_logic;
+ signal SUB7 : std_logic;
+ signal SUB8 : std_logic;
+ signal SUB9 : std_logic;
+ signal SUB10 : std_logic;
+ signal SUB11 : std_logic;
+ signal SUB12 : std_logic;
+ signal SUB13 : std_logic;
+ signal SUB14 : std_logic;
+ signal SUB15 : std_logic;
+ signal CO_DUMMY : std_logic;
+ component FMAP
+ port ( I1 : in std_logic;
+ I2 : in std_logic;
+ I3 : in std_logic;
+ I4 : in std_logic;
+ O : in std_logic);
+ end component;
+ attribute BOX_TYPE of FMAP : COMPONENT is "BLACK_BOX";
+
+ component XOR3
+ port ( I0 : in std_logic;
+ I1 : in std_logic;
+ I2 : in std_logic;
+ O : out std_logic);
+ end component;
+ attribute BOX_TYPE of XOR3 : COMPONENT is "BLACK_BOX";
+
+ component MUXCY_L
+ port ( CI : in std_logic;
+ DI : in std_logic;
+ S : in std_logic;
+ LO : out std_logic);
+ end component;
+ attribute BOX_TYPE of MUXCY_L : COMPONENT is "BLACK_BOX";
+
+ component MUXCY
+ port ( CI : in std_logic;
+ DI : in std_logic;
+ S : in std_logic;
+ O : out std_logic);
+ end component;
+ attribute BOX_TYPE of MUXCY : COMPONENT is "BLACK_BOX";
+
+ component XORCY
+ port ( CI : in std_logic;
+ LI : in std_logic;
+ O : out std_logic);
+ end component;
+ attribute BOX_TYPE of XORCY : COMPONENT is "BLACK_BOX";
+
+ component MUXCY_D
+ port ( CI : in std_logic;
+ DI : in std_logic;
+ S : in std_logic;
+ LO : out std_logic;
+ O : out std_logic);
+ end component;
+ attribute BOX_TYPE of MUXCY_D : COMPONENT is "BLACK_BOX";
+
+ component XOR2
+ port ( I0 : in std_logic;
+ I1 : in std_logic;
+ O : out std_logic);
+ end component;
+ attribute BOX_TYPE of XOR2 : COMPONENT is "BLACK_BOX";
+
+ component INV
+ port ( I : in std_logic;
+ O : out std_logic);
+ end component;
+ attribute BOX_TYPE of INV : COMPONENT is "BLACK_BOX";
+
+ attribute RLOC of I_36_16 : LABEL is "X1Y4";
+ attribute RLOC of I_36_17 : LABEL is "X1Y4";
+ attribute RLOC of I_36_18 : LABEL is "X1Y5";
+ attribute RLOC of I_36_19 : LABEL is "X1Y5";
+ attribute RLOC of I_36_20 : LABEL is "X1Y6";
+ attribute RLOC of I_36_21 : LABEL is "X1Y6";
+ attribute RLOC of I_36_22 : LABEL is "X1Y7";
+ attribute RLOC of I_36_23 : LABEL is "X1Y7";
+ attribute RLOC of I_36_55 : LABEL is "X1Y4";
+ attribute RLOC of I_36_58 : LABEL is "X1Y5";
+ attribute RLOC of I_36_62 : LABEL is "X1Y5";
+ attribute RLOC of I_36_63 : LABEL is "X1Y6";
+ attribute RLOC of I_36_64 : LABEL is "X1Y7";
+ attribute RLOC of I_36_107 : LABEL is "X1Y7";
+ attribute RLOC of I_36_110 : LABEL is "X1Y6";
+ attribute RLOC of I_36_111 : LABEL is "X1Y4";
+ attribute RLOC of I_36_248 : LABEL is "X1Y3";
+ attribute RLOC of I_36_249 : LABEL is "X1Y3";
+ attribute RLOC of I_36_250 : LABEL is "X1Y2";
+ attribute RLOC of I_36_251 : LABEL is "X1Y2";
+ attribute RLOC of I_36_252 : LABEL is "X1Y1";
+ attribute RLOC of I_36_253 : LABEL is "X1Y1";
+ attribute RLOC of I_36_254 : LABEL is "X1Y0";
+ attribute RLOC of I_36_255 : LABEL is "X1Y0";
+ attribute RLOC of I_36_272 : LABEL is "X1Y0";
+ attribute RLOC of I_36_275 : LABEL is "X1Y0";
+ attribute RLOC of I_36_279 : LABEL is "X1Y1";
+ attribute RLOC of I_36_283 : LABEL is "X1Y1";
+ attribute RLOC of I_36_287 : LABEL is "X1Y2";
+ attribute RLOC of I_36_291 : LABEL is "X1Y2";
+ attribute RLOC of I_36_295 : LABEL is "X1Y3";
+ attribute RLOC of I_36_299 : LABEL is "X1Y3";
+begin
+ CO <= CO_DUMMY;
+ I_36_16 : FMAP
+ port map (I1=>A(8), I2=>B(8), I3=>ADD, I4=>dummy, O=>I8);
+
+ I_36_17 : FMAP
+ port map (I1=>A(9), I2=>B(9), I3=>ADD, I4=>dummy, O=>I9);
+
+ I_36_18 : FMAP
+ port map (I1=>A(10), I2=>B(10), I3=>ADD, I4=>dummy, O=>I10);
+
+ I_36_19 : FMAP
+ port map (I1=>A(11), I2=>B(11), I3=>ADD, I4=>dummy, O=>I11);
+
+ I_36_20 : FMAP
+ port map (I1=>A(12), I2=>B(12), I3=>ADD, I4=>dummy, O=>I12);
+
+ I_36_21 : FMAP
+ port map (I1=>A(13), I2=>B(13), I3=>ADD, I4=>dummy, O=>I13);
+
+ I_36_22 : FMAP
+ port map (I1=>A(14), I2=>B(14), I3=>ADD, I4=>dummy, O=>I14);
+
+ I_36_23 : FMAP
+ port map (I1=>A(15), I2=>B(15), I3=>ADD, I4=>dummy, O=>I15);
+
+ I_36_50 : XOR3
+ port map (I0=>A(8), I1=>B(8), I2=>SUB8, O=>I8);
+
+ I_36_55 : MUXCY_L
+ port map (CI=>C8, DI=>A(9), S=>I9, LO=>C9);
+
+ I_36_56 : XOR3
+ port map (I0=>A(10), I1=>B(10), I2=>SUB10, O=>I10);
+
+ I_36_57 : XOR3
+ port map (I0=>A(11), I1=>B(11), I2=>SUB11, O=>I11);
+
+ I_36_58 : MUXCY_L
+ port map (CI=>C10, DI=>A(11), S=>I11, LO=>C11);
+
+ I_36_59 : XOR3
+ port map (I0=>A(14), I1=>B(14), I2=>SUB14, O=>I14);
+
+ I_36_60 : XOR3
+ port map (I0=>A(12), I1=>B(12), I2=>SUB12, O=>I12);
+
+ I_36_62 : MUXCY_L
+ port map (CI=>C9, DI=>A(10), S=>I10, LO=>C10);
+
+ I_36_63 : MUXCY_L
+ port map (CI=>C11, DI=>A(12), S=>I12, LO=>C12);
+
+ I_36_64 : MUXCY
+ port map (CI=>C14, DI=>A(15), S=>I15, O=>CO_DUMMY);
+
+ I_36_73 : XORCY
+ port map (CI=>C7, LI=>I8, O=>S(8));
+
+ I_36_74 : XORCY
+ port map (CI=>C8, LI=>I9, O=>S(9));
+
+ I_36_75 : XORCY
+ port map (CI=>C10, LI=>I11, O=>S(11));
+
+ I_36_76 : XORCY
+ port map (CI=>C9, LI=>I10, O=>S(10));
+
+ I_36_77 : XORCY
+ port map (CI=>C12, LI=>I13, O=>S(13));
+
+ I_36_78 : XORCY
+ port map (CI=>C11, LI=>I12, O=>S(12));
+
+ I_36_79 : XOR3
+ port map (I0=>A(15), I1=>B(15), I2=>SUB15, O=>I15);
+
+ I_36_80 : XORCY
+ port map (CI=>C14, LI=>I15, O=>S(15));
+
+ I_36_81 : XORCY
+ port map (CI=>C13, LI=>I14, O=>S(14));
+
+ I_36_100 : XOR3
+ port map (I0=>A(9), I1=>B(9), I2=>SUB9, O=>I9);
+
+ I_36_107 : MUXCY_D
+ port map (CI=>C13, DI=>A(14), S=>I14, LO=>C14, O=>C14O);
+
+ I_36_109 : XOR3
+ port map (I0=>A(13), I1=>B(13), I2=>SUB13, O=>I13);
+
+ I_36_110 : MUXCY_L
+ port map (CI=>C12, DI=>A(13), S=>I13, LO=>C13);
+
+ I_36_111 : MUXCY_L
+ port map (CI=>C7, DI=>A(8), S=>I8, LO=>C8);
+
+ I_36_220 : XOR3
+ port map (I0=>A(0), I1=>B(0), I2=>SUB0, O=>I0);
+
+ I_36_222 : XOR3
+ port map (I0=>A(2), I1=>B(2), I2=>SUB2, O=>I2);
+
+ I_36_223 : XOR3
+ port map (I0=>A(3), I1=>B(3), I2=>SUB3, O=>I3);
+
+ I_36_224 : XOR3
+ port map (I0=>A(6), I1=>B(6), I2=>SUB6, O=>I6);
+
+ I_36_225 : XOR3
+ port map (I0=>A(4), I1=>B(4), I2=>SUB4, O=>I4);
+
+ I_36_226 : XORCY
+ port map (CI=>CI, LI=>I0, O=>S(0));
+
+ I_36_227 : XORCY
+ port map (CI=>C0, LI=>I1, O=>S(1));
+
+ I_36_228 : XORCY
+ port map (CI=>C2, LI=>I3, O=>S(3));
+
+ I_36_229 : XORCY
+ port map (CI=>C1, LI=>I2, O=>S(2));
+
+ I_36_230 : XORCY
+ port map (CI=>C4, LI=>I5, O=>S(5));
+
+ I_36_231 : XORCY
+ port map (CI=>C3, LI=>I4, O=>S(4));
+
+ I_36_232 : XOR3
+ port map (I0=>A(7), I1=>B(7), I2=>SUB7, O=>I7);
+
+ I_36_233 : XORCY
+ port map (CI=>C6, LI=>I7, O=>S(7));
+
+ I_36_234 : XORCY
+ port map (CI=>C5, LI=>I6, O=>S(6));
+
+ I_36_243 : XOR3
+ port map (I0=>A(1), I1=>B(1), I2=>SUB1, O=>I1);
+
+ I_36_245 : XOR3
+ port map (I0=>A(5), I1=>B(5), I2=>SUB5, O=>I5);
+
+ I_36_248 : MUXCY_L
+ port map (CI=>C6, DI=>A(7), S=>I7, LO=>C7);
+
+ I_36_249 : MUXCY_L
+ port map (CI=>C5, DI=>A(6), S=>I6, LO=>C6);
+
+ I_36_250 : MUXCY_L
+ port map (CI=>C4, DI=>A(5), S=>I5, LO=>C5);
+
+ I_36_251 : MUXCY_L
+ port map (CI=>C3, DI=>A(4), S=>I4, LO=>C4);
+
+ I_36_252 : MUXCY_L
+ port map (CI=>C2, DI=>A(3), S=>I3, LO=>C3);
+
+ I_36_253 : MUXCY_L
+ port map (CI=>C1, DI=>A(2), S=>I2, LO=>C2);
+
+ I_36_254 : MUXCY_L
+ port map (CI=>C0, DI=>A(1), S=>I1, LO=>C1);
+
+ I_36_255 : MUXCY_L
+ port map (CI=>CI, DI=>A(0), S=>I0, LO=>C0);
+
+ I_36_272 : FMAP
+ port map (I1=>A(1), I2=>B(1), I3=>ADD, I4=>dummy, O=>I1);
+
+ I_36_275 : FMAP
+ port map (I1=>A(0), I2=>B(0), I3=>ADD, I4=>dummy, O=>I0);
+
+ I_36_279 : FMAP
+ port map (I1=>A(2), I2=>B(2), I3=>ADD, I4=>dummy, O=>I2);
+
+ I_36_283 : FMAP
+ port map (I1=>A(3), I2=>B(3), I3=>ADD, I4=>dummy, O=>I3);
+
+ I_36_287 : FMAP
+ port map (I1=>A(4), I2=>B(4), I3=>ADD, I4=>dummy, O=>I4);
+
+ I_36_291 : FMAP
+ port map (I1=>A(5), I2=>B(5), I3=>ADD, I4=>dummy, O=>I5);
+
+ I_36_295 : FMAP
+ port map (I1=>A(6), I2=>B(6), I3=>ADD, I4=>dummy, O=>I6);
+
+ I_36_299 : FMAP
+ port map (I1=>A(7), I2=>B(7), I3=>ADD, I4=>dummy, O=>I7);
+
+ I_36_353 : XOR2
+ port map (I0=>C14O, I1=>CO_DUMMY, O=>OFL);
+
+ I_36_355 : INV
+ port map (I=>ADD, O=>SUB0);
+
+ I_36_356 : INV
+ port map (I=>ADD, O=>SUB1);
+
+ I_36_357 : INV
+ port map (I=>ADD, O=>SUB2);
+
+ I_36_358 : INV
+ port map (I=>ADD, O=>SUB3);
+
+ I_36_359 : INV
+ port map (I=>ADD, O=>SUB4);
+
+ I_36_360 : INV
+ port map (I=>ADD, O=>SUB5);
+
+ I_36_361 : INV
+ port map (I=>ADD, O=>SUB6);
+
+ I_36_362 : INV
+ port map (I=>ADD, O=>SUB7);
+
+ I_36_363 : INV
+ port map (I=>ADD, O=>SUB8);
+
+ I_36_364 : INV
+ port map (I=>ADD, O=>SUB9);
+
+ I_36_365 : INV
+ port map (I=>ADD, O=>SUB10);
+
+ I_36_366 : INV
+ port map (I=>ADD, O=>SUB11);
+
+ I_36_367 : INV
+ port map (I=>ADD, O=>SUB12);
+
+ I_36_368 : INV
+ port map (I=>ADD, O=>SUB13);
+
+ I_36_369 : INV
+ port map (I=>ADD, O=>SUB14);
+
+ I_36_370 : INV
+ port map (I=>ADD, O=>SUB15);
+
+end BEHAVIORAL;
+
+
+-- VHDL model created from arith.sch - Tue Jul 19 11:19:52 2005
+
+
+library ieee;
+use ieee.std_logic_1164.ALL;
+use ieee.numeric_std.ALL;
+-- synopsys translate_off
+library UNISIM;
+use UNISIM.Vcomponents.ALL;
+-- synopsys translate_on
+
+entity arith is
+ port ( a : in std_logic_vector (15 downto 0);
+ b : in std_logic_vector (15 downto 0);
+ c_in : in std_logic;
+ s0 : in std_logic;
+ s1 : in std_logic;
+ c_out : out std_logic;
+ ofl_out : out std_logic;
+ result : out std_logic_vector (15 downto 0));
+end arith;
+
+architecture BEHAVIORAL of arith is
+ attribute HU_SET : STRING ;
+ attribute BOX_TYPE : STRING ;
+ signal XLXN_14 : std_logic;
+ signal XLXN_15 : std_logic;
+ signal XLXN_18 : std_logic;
+ signal XLXN_24 : std_logic;
+ signal XLXN_29 : std_logic;
+ signal XLXN_30 : std_logic;
+ signal XLXN_35 : std_logic;
+ signal zero_i : std_logic;
+ component ADSU16_MXILINX_arith
+ port ( A : in std_logic_vector (15 downto 0);
+ ADD : in std_logic;
+ B : in std_logic_vector (15 downto 0);
+ CI : in std_logic;
+ CO : out std_logic;
+ OFL : out std_logic;
+ S : out std_logic_vector (15 downto 0));
+ end component;
+
+ component M2_1_MXILINX_arith
+ port ( D0 : in std_logic;
+ D1 : in std_logic;
+ S0 : in std_logic;
+ O : out std_logic);
+ end component;
+
+ component INV
+ port ( I : in std_logic;
+ O : out std_logic);
+ end component;
+ attribute BOX_TYPE of INV : COMPONENT is "BLACK_BOX";
+
+ component GND
+ port ( G : out std_logic);
+ end component;
+ attribute BOX_TYPE of GND : COMPONENT is "BLACK_BOX";
+
+ attribute HU_SET of XLXI_1 : LABEL is "XLXI_1_0";
+ attribute HU_SET of XLXI_2 : LABEL is "XLXI_2_1";
+ attribute HU_SET of XLXI_3 : LABEL is "XLXI_3_2";
+ attribute HU_SET of XLXI_4 : LABEL is "XLXI_4_4";
+ attribute HU_SET of XLXI_11 : LABEL is "XLXI_11_3";
+begin
+ XLXI_1 : ADSU16_MXILINX_arith
+ port map (A(15 downto 0)=>a(15 downto 0), ADD=>s0, B(15 downto 0)=>b(15
+ downto 0), CI=>XLXN_35, CO=>XLXN_14, OFL=>ofl_out, S(15 downto
+ 0)=>result(15 downto 0));
+
+ XLXI_2 : M2_1_MXILINX_arith
+ port map (D0=>XLXN_15, D1=>XLXN_14, S0=>s0, O=>c_out);
+
+ XLXI_3 : M2_1_MXILINX_arith
+ port map (D0=>XLXN_29, D1=>XLXN_30, S0=>s1, O=>XLXN_35);
+
+ XLXI_4 : M2_1_MXILINX_arith
+ port map (D0=>XLXN_24, D1=>c_in, S0=>s0, O=>XLXN_30);
+
+ XLXI_8 : INV
+ port map (I=>zero_i, O=>XLXN_18);
+
+ XLXI_10 : INV
+ port map (I=>XLXN_14, O=>XLXN_15);
+
+ XLXI_11 : M2_1_MXILINX_arith
+ port map (D0=>XLXN_18, D1=>zero_i, S0=>s0, O=>XLXN_29);
+
+ XLXI_13 : INV
+ port map (I=>c_in, O=>XLXN_24);
+
+ XLXI_14 : GND
+ port map (G=>zero_i);
+
+end BEHAVIORAL;
+
+
Index: trunk/impl0/sim/testbench/add2_init_ram.txt
===================================================================
--- trunk/impl0/sim/testbench/add2_init_ram.txt (nonexistent)
+++ trunk/impl0/sim/testbench/add2_init_ram.txt (revision 2)
@@ -0,0 +1,11 @@
+0:0100100100000000
+1:1111111100000000
+2:0100100101100000
+3:1111111100000010
+4:0000100000100000
+5:0000100000110110
+6:0011000100100011
+7:0100100110000000
+8:1111111100000100
+9:0001000000101000
+10:1111100000000000
\ No newline at end of file
Index: trunk/impl0/sim/testbench/ramNx16.vhd
===================================================================
--- trunk/impl0/sim/testbench/ramNx16.vhd (nonexistent)
+++ trunk/impl0/sim/testbench/ramNx16.vhd (revision 2)
@@ -0,0 +1,159 @@
+--------------------------------------------------------------
+-- ramNx16.vhd
+--------------------------------------------------------------
+-- project: HPC-16 Microprocessor
+--
+-- usage: RAM with async read and sync write operation (not synthsizable, without timing params)
+--
+-- dependency: none
+--
+-- Author: M. Umair Siddiqui (umairsiddiqui@opencores.org)
+---------------------------------------------------------------
+------------------------------------------------------------------------------------
+-- --
+-- Copyright (c) 2005, M. Umair Siddiqui all rights reserved --
+-- --
+-- This file is part of HPC-16. --
+-- --
+-- HPC-16 is free software; you can redistribute it and/or modify --
+-- it under the terms of the GNU Lesser General Public License as published by --
+-- the Free Software Foundation; either version 2.1 of the License, or --
+-- (at your option) any later version. --
+-- --
+-- HPC-16 is distributed in the hope that it will be useful, --
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
+-- GNU Lesser General Public License for more details. --
+-- --
+-- You should have received a copy of the GNU Lesser General Public License --
+-- along with HPC-16; if not, write to the Free Software --
+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
+-- --
+------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+-- synopsis synthesis_off
+use std.textio.all;
+use ieee.std_logic_textio.all;
+-- synopsis synthesis_on
+-------------------------------------
+entity ramNx16 is
+ generic
+ (
+ -- synopsis synthesis_off
+ init_file_name : string := "init_ramNx16.txt";
+ -- synopsis synthesis_on
+ adr_width : integer := 4;
+ dat_width : integer := 16
+ );
+ port
+ (
+ clk : in std_logic;
+ adr : in std_logic_vector(adr_width - 1 downto 0);
+ dat_i : in std_logic_vector(dat_width - 1 downto 0);
+ --
+ cs : in std_logic;
+ we : in std_logic;
+ ub : in std_logic;
+ lb : in std_logic;
+ oe : in std_logic;
+ --
+ dat_o : out std_logic_vector(dat_width - 1 downto 0)
+ );
+end ramNx16;
+-----------------------------------------------------------------------
+-----------------------------------------------------------------------
+architecture async of ramNx16 is
+ constant locs : integer := 2 ** adr_width;
+ type rtype is array(0 to locs - 1) of std_logic_vector((dat_width/2) - 1 downto 0);
+ shared variable ram_data_lower : rtype;
+ shared variable ram_data_upper : rtype;
+ --
+ signal s_init : boolean := false;
+ --
+ signal write_lower : std_logic;
+ signal write_upper : std_logic;
+ signal out_lower : std_logic;
+ signal out_upper : std_logic;
+begin
+ ----------------------------------------------------------------------------
+ -- assertion
+ ----------------------------------------------------------------------------
+ assert dat_width = 16
+ report "module is designed for 16-bit data"
+ severity error;
+ ----------------------------------------------------------------------------
+ -- init
+ ----------------------------------------------------------------------------
+ -- synopsis sythesis_off
+ init: process
+ file init_file : text;
+ variable buf : line;
+ variable address: integer;
+ variable sep : character;
+ variable data : std_logic_vector(dat_width - 1 downto 0);
+ begin
+ if ((not s_init) and (init_file_name /= "none")) then
+ file_open(init_file, init_file_name, read_mode);
+ while (not endfile(init_file)) loop
+ readline(init_file, buf);
+ read(buf, address);
+ read(buf, sep);
+ read(buf, data);
+ ram_data_lower(address) := data(7 downto 0);
+ ram_data_upper(address) := data(15 downto 8);
+ end loop;
+ file_close(init_file);
+ s_init <= true;
+ end if;
+ wait;
+ end process init;
+ -- synopsis synthesis_on
+ ----------------------------------------------------------------------------
+ -- main
+ ----------------------------------------------------------------------------
+ write_low: write_lower <= cs and lb and we;
+ write_up : write_upper <= cs and ub and we;
+ ----------------------------------------------------------------------------
+ upper: process(clk)
+ begin
+ -- synopsis synthesis_off
+ if (s_init) then
+ -- synopsis synthesis_on
+ if rising_edge(clk) then
+ if write_upper = '1' then
+ ram_data_upper(conv_integer(adr)) := dat_i(15 downto 8);
+ end if;
+ end if;
+ -- synopsis synthesis_off
+ end if;
+ -- synopsis synthesis_on
+ end process upper;
+ ----------------------------------------------------------------------------
+ lower: process(clk)
+ begin
+ -- synopsis synthesis_off
+ if (s_init) then
+ -- synopsis synthesis_on
+ if rising_edge(clk) then
+ if write_lower = '1' then
+ ram_data_lower(conv_integer(adr)) := dat_i(7 downto 0);
+ end if;
+ end if;
+ -- synopsis synthesis_off
+ end if;
+ -- synopsis synthesis_on
+ end process lower;
+ -----------------------------------------------------------------------
+ out_low : out_lower <= cs and lb and (not we) and oe;
+ out_up : out_upper <= cs and ub and (not we) and oe;
+ ----------------------------------------------------------------------
+ dat_low : dat_o(15 downto 8) <= ram_data_upper(conv_integer(adr)) when out_upper = '1' else
+ (others => 'Z');
+ dat_up : dat_o(7 downto 0) <= ram_data_lower(conv_integer(adr)) when out_lower = '1' else
+ (others => 'Z');
+ ----------------------------------------------------------------------
+end async;
Index: trunk/common/docs/HPC-16_architecture.doc
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/common/docs/HPC-16_architecture.doc
===================================================================
--- trunk/common/docs/HPC-16_architecture.doc (nonexistent)
+++ trunk/common/docs/HPC-16_architecture.doc (revision 2)
trunk/common/docs/HPC-16_architecture.doc
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/common/docs/HPC-16_instruction_ref_manual.doc
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/common/docs/HPC-16_instruction_ref_manual.doc
===================================================================
--- trunk/common/docs/HPC-16_instruction_ref_manual.doc (nonexistent)
+++ trunk/common/docs/HPC-16_instruction_ref_manual.doc (revision 2)
trunk/common/docs/HPC-16_instruction_ref_manual.doc
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/LGPL.txt
===================================================================
--- trunk/LGPL.txt (nonexistent)
+++ trunk/LGPL.txt (revision 2)
@@ -0,0 +1,504 @@
+ GNU LESSER GENERAL PUBLIC LICENSE
+ Version 2.1, February 1999
+
+ Copyright (C) 1991, 1999 Free Software Foundation, Inc.
+ 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+[This is the first released version of the Lesser GPL. It also counts
+ as the successor of the GNU Library Public License, version 2, hence
+ the version number 2.1.]
+
+ Preamble
+
+ The licenses for most software are designed to take away your
+freedom to share and change it. By contrast, the GNU General Public
+Licenses are intended to guarantee your freedom to share and change
+free software--to make sure the software is free for all its users.
+
+ This license, the Lesser General Public License, applies to some
+specially designated software packages--typically libraries--of the
+Free Software Foundation and other authors who decide to use it. You
+can use it too, but we suggest you first think carefully about whether
+this license or the ordinary General Public License is the better
+strategy to use in any particular case, based on the explanations below.
+
+ When we speak of free software, we are referring to freedom of use,
+not price. Our General Public Licenses are designed to make sure that
+you have the freedom to distribute copies of free software (and charge
+for this service if you wish); that you receive source code or can get
+it if you want it; that you can change the software and use pieces of
+it in new free programs; and that you are informed that you can do
+these things.
+
+ To protect your rights, we need to make restrictions that forbid
+distributors to deny you these rights or to ask you to surrender these
+rights. These restrictions translate to certain responsibilities for
+you if you distribute copies of the library or if you modify it.
+
+ For example, if you distribute copies of the library, whether gratis
+or for a fee, you must give the recipients all the rights that we gave
+you. You must make sure that they, too, receive or can get the source
+code. If you link other code with the library, you must provide
+complete object files to the recipients, so that they can relink them
+with the library after making changes to the library and recompiling
+it. And you must show them these terms so they know their rights.
+
+ We protect your rights with a two-step method: (1) we copyright the
+library, and (2) we offer you this license, which gives you legal
+permission to copy, distribute and/or modify the library.
+
+ To protect each distributor, we want to make it very clear that
+there is no warranty for the free library. Also, if the library is
+modified by someone else and passed on, the recipients should know
+that what they have is not the original version, so that the original
+author's reputation will not be affected by problems that might be
+introduced by others.
+
+ Finally, software patents pose a constant threat to the existence of
+any free program. We wish to make sure that a company cannot
+effectively restrict the users of a free program by obtaining a
+restrictive license from a patent holder. Therefore, we insist that
+any patent license obtained for a version of the library must be
+consistent with the full freedom of use specified in this license.
+
+ Most GNU software, including some libraries, is covered by the
+ordinary GNU General Public License. This license, the GNU Lesser
+General Public License, applies to certain designated libraries, and
+is quite different from the ordinary General Public License. We use
+this license for certain libraries in order to permit linking those
+libraries into non-free programs.
+
+ When a program is linked with a library, whether statically or using
+a shared library, the combination of the two is legally speaking a
+combined work, a derivative of the original library. The ordinary
+General Public License therefore permits such linking only if the
+entire combination fits its criteria of freedom. The Lesser General
+Public License permits more lax criteria for linking other code with
+the library.
+
+ We call this license the "Lesser" General Public License because it
+does Less to protect the user's freedom than the ordinary General
+Public License. It also provides other free software developers Less
+of an advantage over competing non-free programs. These disadvantages
+are the reason we use the ordinary General Public License for many
+libraries. However, the Lesser license provides advantages in certain
+special circumstances.
+
+ For example, on rare occasions, there may be a special need to
+encourage the widest possible use of a certain library, so that it becomes
+a de-facto standard. To achieve this, non-free programs must be
+allowed to use the library. A more frequent case is that a free
+library does the same job as widely used non-free libraries. In this
+case, there is little to gain by limiting the free library to free
+software only, so we use the Lesser General Public License.
+
+ In other cases, permission to use a particular library in non-free
+programs enables a greater number of people to use a large body of
+free software. For example, permission to use the GNU C Library in
+non-free programs enables many more people to use the whole GNU
+operating system, as well as its variant, the GNU/Linux operating
+system.
+
+ Although the Lesser General Public License is Less protective of the
+users' freedom, it does ensure that the user of a program that is
+linked with the Library has the freedom and the wherewithal to run
+that program using a modified version of the Library.
+
+ The precise terms and conditions for copying, distribution and
+modification follow. Pay close attention to the difference between a
+"work based on the library" and a "work that uses the library". The
+former contains code derived from the library, whereas the latter must
+be combined with the library in order to run.
+
+ GNU LESSER GENERAL PUBLIC LICENSE
+ TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
+
+ 0. This License Agreement applies to any software library or other
+program which contains a notice placed by the copyright holder or
+other authorized party saying it may be distributed under the terms of
+this Lesser General Public License (also called "this License").
+Each licensee is addressed as "you".
+
+ A "library" means a collection of software functions and/or data
+prepared so as to be conveniently linked with application programs
+(which use some of those functions and data) to form executables.
+
+ The "Library", below, refers to any such software library or work
+which has been distributed under these terms. A "work based on the
+Library" means either the Library or any derivative work under
+copyright law: that is to say, a work containing the Library or a
+portion of it, either verbatim or with modifications and/or translated
+straightforwardly into another language. (Hereinafter, translation is
+included without limitation in the term "modification".)
+
+ "Source code" for a work means the preferred form of the work for
+making modifications to it. For a library, complete source code means
+all the source code for all modules it contains, plus any associated
+interface definition files, plus the scripts used to control compilation
+and installation of the library.
+
+ Activities other than copying, distribution and modification are not
+covered by this License; they are outside its scope. The act of
+running a program using the Library is not restricted, and output from
+such a program is covered only if its contents constitute a work based
+on the Library (independent of the use of the Library in a tool for
+writing it). Whether that is true depends on what the Library does
+and what the program that uses the Library does.
+
+ 1. You may copy and distribute verbatim copies of the Library's
+complete source code as you receive it, in any medium, provided that
+you conspicuously and appropriately publish on each copy an
+appropriate copyright notice and disclaimer of warranty; keep intact
+all the notices that refer to this License and to the absence of any
+warranty; and distribute a copy of this License along with the
+Library.
+
+ You may charge a fee for the physical act of transferring a copy,
+and you may at your option offer warranty protection in exchange for a
+fee.
+
+ 2. You may modify your copy or copies of the Library or any portion
+of it, thus forming a work based on the Library, and copy and
+distribute such modifications or work under the terms of Section 1
+above, provided that you also meet all of these conditions:
+
+ a) The modified work must itself be a software library.
+
+ b) You must cause the files modified to carry prominent notices
+ stating that you changed the files and the date of any change.
+
+ c) You must cause the whole of the work to be licensed at no
+ charge to all third parties under the terms of this License.
+
+ d) If a facility in the modified Library refers to a function or a
+ table of data to be supplied by an application program that uses
+ the facility, other than as an argument passed when the facility
+ is invoked, then you must make a good faith effort to ensure that,
+ in the event an application does not supply such function or
+ table, the facility still operates, and performs whatever part of
+ its purpose remains meaningful.
+
+ (For example, a function in a library to compute square roots has
+ a purpose that is entirely well-defined independent of the
+ application. Therefore, Subsection 2d requires that any
+ application-supplied function or table used by this function must
+ be optional: if the application does not supply it, the square
+ root function must still compute square roots.)
+
+These requirements apply to the modified work as a whole. If
+identifiable sections of that work are not derived from the Library,
+and can be reasonably considered independent and separate works in
+themselves, then this License, and its terms, do not apply to those
+sections when you distribute them as separate works. But when you
+distribute the same sections as part of a whole which is a work based
+on the Library, the distribution of the whole must be on the terms of
+this License, whose permissions for other licensees extend to the
+entire whole, and thus to each and every part regardless of who wrote
+it.
+
+Thus, it is not the intent of this section to claim rights or contest
+your rights to work written entirely by you; rather, the intent is to
+exercise the right to control the distribution of derivative or
+collective works based on the Library.
+
+In addition, mere aggregation of another work not based on the Library
+with the Library (or with a work based on the Library) on a volume of
+a storage or distribution medium does not bring the other work under
+the scope of this License.
+
+ 3. You may opt to apply the terms of the ordinary GNU General Public
+License instead of this License to a given copy of the Library. To do
+this, you must alter all the notices that refer to this License, so
+that they refer to the ordinary GNU General Public License, version 2,
+instead of to this License. (If a newer version than version 2 of the
+ordinary GNU General Public License has appeared, then you can specify
+that version instead if you wish.) Do not make any other change in
+these notices.
+
+ Once this change is made in a given copy, it is irreversible for
+that copy, so the ordinary GNU General Public License applies to all
+subsequent copies and derivative works made from that copy.
+
+ This option is useful when you wish to copy part of the code of
+the Library into a program that is not a library.
+
+ 4. You may copy and distribute the Library (or a portion or
+derivative of it, under Section 2) in object code or executable form
+under the terms of Sections 1 and 2 above provided that you accompany
+it with the complete corresponding machine-readable source code, which
+must be distributed under the terms of Sections 1 and 2 above on a
+medium customarily used for software interchange.
+
+ If distribution of object code is made by offering access to copy
+from a designated place, then offering equivalent access to copy the
+source code from the same place satisfies the requirement to
+distribute the source code, even though third parties are not
+compelled to copy the source along with the object code.
+
+ 5. A program that contains no derivative of any portion of the
+Library, but is designed to work with the Library by being compiled or
+linked with it, is called a "work that uses the Library". Such a
+work, in isolation, is not a derivative work of the Library, and
+therefore falls outside the scope of this License.
+
+ However, linking a "work that uses the Library" with the Library
+creates an executable that is a derivative of the Library (because it
+contains portions of the Library), rather than a "work that uses the
+library". The executable is therefore covered by this License.
+Section 6 states terms for distribution of such executables.
+
+ When a "work that uses the Library" uses material from a header file
+that is part of the Library, the object code for the work may be a
+derivative work of the Library even though the source code is not.
+Whether this is true is especially significant if the work can be
+linked without the Library, or if the work is itself a library. The
+threshold for this to be true is not precisely defined by law.
+
+ If such an object file uses only numerical parameters, data
+structure layouts and accessors, and small macros and small inline
+functions (ten lines or less in length), then the use of the object
+file is unrestricted, regardless of whether it is legally a derivative
+work. (Executables containing this object code plus portions of the
+Library will still fall under Section 6.)
+
+ Otherwise, if the work is a derivative of the Library, you may
+distribute the object code for the work under the terms of Section 6.
+Any executables containing that work also fall under Section 6,
+whether or not they are linked directly with the Library itself.
+
+ 6. As an exception to the Sections above, you may also combine or
+link a "work that uses the Library" with the Library to produce a
+work containing portions of the Library, and distribute that work
+under terms of your choice, provided that the terms permit
+modification of the work for the customer's own use and reverse
+engineering for debugging such modifications.
+
+ You must give prominent notice with each copy of the work that the
+Library is used in it and that the Library and its use are covered by
+this License. You must supply a copy of this License. If the work
+during execution displays copyright notices, you must include the
+copyright notice for the Library among them, as well as a reference
+directing the user to the copy of this License. Also, you must do one
+of these things:
+
+ a) Accompany the work with the complete corresponding
+ machine-readable source code for the Library including whatever
+ changes were used in the work (which must be distributed under
+ Sections 1 and 2 above); and, if the work is an executable linked
+ with the Library, with the complete machine-readable "work that
+ uses the Library", as object code and/or source code, so that the
+ user can modify the Library and then relink to produce a modified
+ executable containing the modified Library. (It is understood
+ that the user who changes the contents of definitions files in the
+ Library will not necessarily be able to recompile the application
+ to use the modified definitions.)
+
+ b) Use a suitable shared library mechanism for linking with the
+ Library. A suitable mechanism is one that (1) uses at run time a
+ copy of the library already present on the user's computer system,
+ rather than copying library functions into the executable, and (2)
+ will operate properly with a modified version of the library, if
+ the user installs one, as long as the modified version is
+ interface-compatible with the version that the work was made with.
+
+ c) Accompany the work with a written offer, valid for at
+ least three years, to give the same user the materials
+ specified in Subsection 6a, above, for a charge no more
+ than the cost of performing this distribution.
+
+ d) If distribution of the work is made by offering access to copy
+ from a designated place, offer equivalent access to copy the above
+ specified materials from the same place.
+
+ e) Verify that the user has already received a copy of these
+ materials or that you have already sent this user a copy.
+
+ For an executable, the required form of the "work that uses the
+Library" must include any data and utility programs needed for
+reproducing the executable from it. However, as a special exception,
+the materials to be distributed need not include anything that is
+normally distributed (in either source or binary form) with the major
+components (compiler, kernel, and so on) of the operating system on
+which the executable runs, unless that component itself accompanies
+the executable.
+
+ It may happen that this requirement contradicts the license
+restrictions of other proprietary libraries that do not normally
+accompany the operating system. Such a contradiction means you cannot
+use both them and the Library together in an executable that you
+distribute.
+
+ 7. You may place library facilities that are a work based on the
+Library side-by-side in a single library together with other library
+facilities not covered by this License, and distribute such a combined
+library, provided that the separate distribution of the work based on
+the Library and of the other library facilities is otherwise
+permitted, and provided that you do these two things:
+
+ a) Accompany the combined library with a copy of the same work
+ based on the Library, uncombined with any other library
+ facilities. This must be distributed under the terms of the
+ Sections above.
+
+ b) Give prominent notice with the combined library of the fact
+ that part of it is a work based on the Library, and explaining
+ where to find the accompanying uncombined form of the same work.
+
+ 8. You may not copy, modify, sublicense, link with, or distribute
+the Library except as expressly provided under this License. Any
+attempt otherwise to copy, modify, sublicense, link with, or
+distribute the Library is void, and will automatically terminate your
+rights under this License. However, parties who have received copies,
+or rights, from you under this License will not have their licenses
+terminated so long as such parties remain in full compliance.
+
+ 9. You are not required to accept this License, since you have not
+signed it. However, nothing else grants you permission to modify or
+distribute the Library or its derivative works. These actions are
+prohibited by law if you do not accept this License. Therefore, by
+modifying or distributing the Library (or any work based on the
+Library), you indicate your acceptance of this License to do so, and
+all its terms and conditions for copying, distributing or modifying
+the Library or works based on it.
+
+ 10. Each time you redistribute the Library (or any work based on the
+Library), the recipient automatically receives a license from the
+original licensor to copy, distribute, link with or modify the Library
+subject to these terms and conditions. You may not impose any further
+restrictions on the recipients' exercise of the rights granted herein.
+You are not responsible for enforcing compliance by third parties with
+this License.
+
+ 11. If, as a consequence of a court judgment or allegation of patent
+infringement or for any other reason (not limited to patent issues),
+conditions are imposed on you (whether by court order, agreement or
+otherwise) that contradict the conditions of this License, they do not
+excuse you from the conditions of this License. If you cannot
+distribute so as to satisfy simultaneously your obligations under this
+License and any other pertinent obligations, then as a consequence you
+may not distribute the Library at all. For example, if a patent
+license would not permit royalty-free redistribution of the Library by
+all those who receive copies directly or indirectly through you, then
+the only way you could satisfy both it and this License would be to
+refrain entirely from distribution of the Library.
+
+If any portion of this section is held invalid or unenforceable under any
+particular circumstance, the balance of the section is intended to apply,
+and the section as a whole is intended to apply in other circumstances.
+
+It is not the purpose of this section to induce you to infringe any
+patents or other property right claims or to contest validity of any
+such claims; this section has the sole purpose of protecting the
+integrity of the free software distribution system which is
+implemented by public license practices. Many people have made
+generous contributions to the wide range of software distributed
+through that system in reliance on consistent application of that
+system; it is up to the author/donor to decide if he or she is willing
+to distribute software through any other system and a licensee cannot
+impose that choice.
+
+This section is intended to make thoroughly clear what is believed to
+be a consequence of the rest of this License.
+
+ 12. If the distribution and/or use of the Library is restricted in
+certain countries either by patents or by copyrighted interfaces, the
+original copyright holder who places the Library under this License may add
+an explicit geographical distribution limitation excluding those countries,
+so that distribution is permitted only in or among countries not thus
+excluded. In such case, this License incorporates the limitation as if
+written in the body of this License.
+
+ 13. The Free Software Foundation may publish revised and/or new
+versions of the Lesser General Public License from time to time.
+Such new versions will be similar in spirit to the present version,
+but may differ in detail to address new problems or concerns.
+
+Each version is given a distinguishing version number. If the Library
+specifies a version number of this License which applies to it and
+"any later version", you have the option of following the terms and
+conditions either of that version or of any later version published by
+the Free Software Foundation. If the Library does not specify a
+license version number, you may choose any version ever published by
+the Free Software Foundation.
+
+ 14. If you wish to incorporate parts of the Library into other free
+programs whose distribution conditions are incompatible with these,
+write to the author to ask for permission. For software which is
+copyrighted by the Free Software Foundation, write to the Free
+Software Foundation; we sometimes make exceptions for this. Our
+decision will be guided by the two goals of preserving the free status
+of all derivatives of our free software and of promoting the sharing
+and reuse of software generally.
+
+ NO WARRANTY
+
+ 15. BECAUSE THE LIBRARY IS LICENSED FREE OF CHARGE, THERE IS NO
+WARRANTY FOR THE LIBRARY, TO THE EXTENT PERMITTED BY APPLICABLE LAW.
+EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR
+OTHER PARTIES PROVIDE THE LIBRARY "AS IS" WITHOUT WARRANTY OF ANY
+KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE
+LIBRARY IS WITH YOU. SHOULD THE LIBRARY PROVE DEFECTIVE, YOU ASSUME
+THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
+
+ 16. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN
+WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY
+AND/OR REDISTRIBUTE THE LIBRARY AS PERMITTED ABOVE, BE LIABLE TO YOU
+FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR
+CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE
+LIBRARY (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING
+RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A
+FAILURE OF THE LIBRARY TO OPERATE WITH ANY OTHER SOFTWARE), EVEN IF
+SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
+DAMAGES.
+
+ END OF TERMS AND CONDITIONS
+
+ How to Apply These Terms to Your New Libraries
+
+ If you develop a new library, and you want it to be of the greatest
+possible use to the public, we recommend making it free software that
+everyone can redistribute and change. You can do so by permitting
+redistribution under these terms (or, alternatively, under the terms of the
+ordinary General Public License).
+
+ To apply these terms, attach the following notices to the library. It is
+safest to attach them to the start of each source file to most effectively
+convey the exclusion of warranty; and each file should have at least the
+"copyright" line and a pointer to where the full notice is found.
+
+
+ Copyright (C)
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+
+Also add information on how to contact you by electronic and paper mail.
+
+You should also get your employer (if you work as a programmer) or your
+school, if any, to sign a "copyright disclaimer" for the library, if
+necessary. Here is a sample; alter the names:
+
+ Yoyodyne, Inc., hereby disclaims all copyright interest in the
+ library `Frob' (a library for tweaking knobs) written by James Random Hacker.
+
+ , 1 April 1990
+ Ty Coon, President of Vice
+
+That's all there is to it!
+
+