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URL https://opencores.org/ocsvn/i2s_to_wb/i2s_to_wb/trunk

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/i2s_to_wb/trunk/src/i2s_to_wb_dma_fsm.v
0,0 → 1,81
//
//
//
 
`include "timescale.v"
 
 
module
i2s_to_wb_dma_fsm
(
input dma_enable,
input dma_ack_i,
input fifo_empty,
input fifo_full,
output fifo_wr_enable,
output dma_fsm_error,
 
input dma_clk_i,
input dma_rst_i
);
 
// -----------------------------
// state machine binary definitions
parameter IDLE_STATE = 4'b0001;
parameter DMA_STATE = 4'b0010;
parameter WAIT_STATE = 4'b0100;
parameter ERROR_STATE = 4'b1000;
 
 
// -----------------------------
// state machine flop
reg [3:0] state;
reg [3:0] next_state;
 
always @(posedge dma_clk_i)
if(dma_rst_i)
state <= IDLE_STATE;
else
state <= next_state;
 
 
// -----------------------------
// state machine
always @(*)
case(state)
IDLE_STATE: if( dma_enable & fifo_empty )
next_state <= DMA_STATE;
else
next_state <= IDLE_STATE;
 
DMA_STATE: if( ~dma_enable | fifo_full )
next_state <= IDLE_STATE;
else if( ~dma_ack_i )
next_state <= WAIT_STATE;
else
next_state <= DMA_STATE;
 
WAIT_STATE: if( dma_ack_i )
next_state <= DMA_STATE;
else
next_state <= WAIT_STATE;
 
ERROR_STATE: next_state <= IDLE_STATE;
 
default: next_state <= ERROR_STATE;
 
endcase
// -----------------------------
// outputs
assign fifo_wr_enable = ( (state == DMA_STATE) | (state == WAIT_STATE) ) & (next_state != WAIT_STATE) & dma_enable & ~fifo_full;
assign dma_fsm_error = (state == ERROR_STATE);
 
endmodule
 
/i2s_to_wb/trunk/src/tone_660_rom.v
0,0 → 1,28
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
`include "timescale.v"
 
 
module tone_660_rom( addr, q );
 
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 7;
input [(ADDR_WIDTH-1):0] addr;
output [(DATA_WIDTH-1):0] q;
// Declare the RAM variable
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
reg [ADDR_WIDTH-1:0] addr_reg;
assign q = ram[addr];
 
initial
$readmemh( "../../../../i2s_to_wb/scilab/tone_roms/tone_660_at_48000sps_rom.txt", ram );
 
endmodule
 
 
/i2s_to_wb/trunk/src/i2s_to_wb_fifo_fsm.v
0,0 → 1,84
//
//
//
 
`include "timescale.v"
 
 
module
i2s_to_wb_fifo_fsm
(
input i2s_ws_edge,
input i2s_ws_i,
input fifo_enable,
input fifo_empty,
input fifo_ack,
output fifo_pop_right,
output fifo_pop_left,
output fifo_fsm_error,
output fifo_ready,
 
input i2s_clk_i,
input i2s_rst_i
);
 
// -----------------------------
// state machine binary definitions
parameter IDLE_STATE = 4'b0001;
parameter ACK_WAIT = 4'b0010;
parameter POP_STATE = 4'b0100;
parameter ERROR_STATE = 4'b1000;
 
 
// -----------------------------
// state machine flop
reg [3:0] state;
reg [3:0] next_state;
 
always @(posedge i2s_clk_i or posedge i2s_rst_i)
if(i2s_rst_i)
state <= IDLE_STATE;
else
state <= next_state;
 
 
// -----------------------------
// state machine
always @(*)
case(state)
IDLE_STATE: if( fifo_enable & ~fifo_ack )
next_state <= ACK_WAIT;
else
next_state <= IDLE_STATE;
 
ACK_WAIT: if( ~fifo_enable )
next_state <= IDLE_STATE;
else if( fifo_ack )
next_state <= POP_STATE;
else
next_state <= ACK_WAIT;
 
POP_STATE: if( fifo_empty )
next_state <= ERROR_STATE;
else
next_state <= IDLE_STATE;
 
ERROR_STATE: next_state <= ACK_WAIT;
 
default: next_state <= ERROR_STATE;
 
endcase
// -----------------------------
// outputs
assign fifo_pop_right = (state == POP_STATE) & i2s_ws_i;
assign fifo_pop_left = (state == POP_STATE) & ~i2s_ws_i;
assign fifo_fsm_error = (state == ERROR_STATE);
assign fifo_ready = (state == ACK_WAIT);
 
endmodule
 
/i2s_to_wb/trunk/src/sync_fifo.v
0,0 → 1,161
// -*- mode: Verilog; verilog-auto-lineup-declaration: nil; -*-
//-----------------------------------------------------------------------------
// Title : Synchronous FIFO
// Project : Common
//-----------------------------------------------------------------------------
// File : sync_fifo.v
//-----------------------------------------------------------------------------
// Description : Synchronous FIFO using BRAM.
//
// Implements a variable width/depth synchronous FIFO. The synthesis
// tool may choose to implement the memory as a block RAM.
//-----------------------------------------------------------------------------
// Copyright 1994-2009 Beyond Circuits. All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE BEYOND CIRCUITS ``AS IS'' AND ANY EXPRESS OR
// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
// SHALL BEYOND CIRCUITS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
// OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//------------------------------------------------------------------------------
 
`timescale 1ns/1ns
module sync_fifo
#(
parameter depth = 32,
parameter width = 32,
// Need the log of the parameters as parameters also due to an XST bug.
parameter log2_depth = log2(depth),
parameter log2_depthp1 = log2(depth+1)
)
(
input clk,
input reset,
input wr_enable,
input rd_enable,
output reg empty,
output reg full,
output [width-1:0] rd_data,
input [width-1:0] wr_data,
output reg [log2_depthp1-1:0] count
);
 
// log2 -- return the log base 2 of value.
function integer log2;
input [31:0] value;
begin
value = value-1;
for (log2=0; value>0; log2=log2+1)
value = value>>1;
end
endfunction
 
// increment -- add one to value modulo depth.
function [log2_depth-1:0] increment;
input [log2_depth-1:0] value;
begin
if (value == depth-1)
increment = 0;
else
increment = value+1;
end
endfunction
 
// writing -- true when we write to the RAM.
wire writing = wr_enable && (rd_enable || !full);
 
// reading -- true when we are reading from the RAM.
wire reading = rd_enable && !empty;
 
// rd_ptr -- the read pointer.
reg [log2_depth-1:0] rd_ptr;
 
// next_rd_ptr -- the next value for the read pointer.
// We need to name this combinational value because it
// is needed to use the write-before-read style RAM.
reg [log2_depth-1:0] next_rd_ptr;
always @(*)
if (reset)
next_rd_ptr = 0;
else if (reading)
next_rd_ptr = increment(rd_ptr);
else
next_rd_ptr = rd_ptr;
 
always @(posedge clk)
rd_ptr <= next_rd_ptr;
 
// wr_ptr -- the write pointer
reg [log2_depth-1:0] wr_ptr;
 
// next_wr_ptr -- the next value for the write pointer.
reg [log2_depth-1:0] next_wr_ptr;
always @(*)
if (reset)
next_wr_ptr = 0;
else if (writing)
next_wr_ptr = increment(wr_ptr);
else
next_wr_ptr = wr_ptr;
 
always @(posedge clk)
wr_ptr <= next_wr_ptr;
// count -- the number of valid entries in the FIFO.
always @(posedge clk)
if (reset)
count <= 0;
else if (writing && !reading)
count <= count+1;
else if (reading && !writing)
count <= count-1;
 
// empty -- true if the FIFO is empty.
// Note that this doesn't depend on count so if the count
// output is unused the logic for computing the count can
// be optimized away.
always @(posedge clk)
if (reset)
empty <= 1;
else if (reading && next_wr_ptr == next_rd_ptr && !full)
empty <= 1;
else
if (writing && !reading)
empty <= 0;
// full -- true if the FIFO is full.
// Again, this is not dependent on count.
always @(posedge clk)
if (reset)
full <= 0;
else if (writing && next_wr_ptr == next_rd_ptr)
full <= 1;
else if (reading && !writing)
full <= 0;
// We need to infer a write first style RAM so that when
// the FIFO is empty the write data can flow through to
// the read side and be available the next clock cycle.
reg [width-1:0] mem [depth-1:0];
always @(posedge clk)
begin
if (writing)
mem[wr_ptr] <= wr_data;
rd_ptr <= next_rd_ptr;
end
 
assign rd_data = mem[rd_ptr];
 
endmodule
/i2s_to_wb/trunk/src/i2s_to_wb_tx_if.v
0,0 → 1,168
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
`include "timescale.v"
 
 
module
i2s_to_wb_tx_if
#(
parameter DMA_BUFFER_MAX_WIDTH = 12
)
(
input i2s_enable,
input i2s_ws_edge,
input i2s_ws_i,
input fifo_ack,
output fifo_ready,
output [31:0] fifo_right_data,
output [31:0] fifo_left_data,
output [31:0] dma_rd_pointer_o,
input [31:0] dma_rd_pointer_i,
input dma_rd_pointer_we,
input [(DMA_BUFFER_MAX_WIDTH - 1):0] dma_word_size,
input [(DMA_BUFFER_MAX_WIDTH - 1):0] dma_buffer_size,
output dma_overflow_error,
 
input i2s_clk_i,
input i2s_rst_i
);
//---------------------------------------------------
//
wire [31:0] wbm_right_data_i;
wire [31:0] wbm_right_data_o;
wire [31:0] wbm_right_addr_o;
wire [3:0] wbm_right_sel_o;
wire wbm_right_we_o;
wire wbm_right_cyc_o;
wire wbm_right_stb_o;
wire wbm_right_ack_i;
wire wbm_right_err_i;
wire wbm_right_rty_i;
 
//---------------------------------------------------
// sync fifo_ack
reg [1:0] fifo_ack_r;
wire fifo_ack_s = fifo_ack_r[1];
 
always @(posedge i2s_clk_i)
fifo_ack_r <= {fifo_ack_r[0], fifo_ack};
 
//---------------------------------------------------
// sync i2s_ws_edge
reg [1:0] i2s_ws_edge_r;
wire i2s_ws_edge_s = i2s_ws_edge_r[1];
 
always @(posedge i2s_clk_i)
i2s_ws_edge_r <= {i2s_ws_edge_r[0], i2s_ws_edge};
 
//---------------------------------------------------
// sync i2s_ws_i
reg [1:0] i2s_ws_i_r;
wire i2s_ws_i_s = i2s_ws_i_r[1];
 
always @(posedge i2s_clk_i)
i2s_ws_i_r <= {i2s_ws_i_r[0], i2s_ws_i};
 
//---------------------------------------------------
//
wire [31:0] tone_out;
 
tone_440_rom
i_tone_440_rom
(
.addr(dma_rd_pointer_o[8:2]),
.q(tone_out)
);
assign wbm_right_ack_i = wbm_right_cyc_o & wbm_right_stb_o;
assign wbm_right_data_i = tone_out;
 
//---------------------------------------------------
// fifo fsm
wire fifo_empty;
wire fifo_pop_right;
wire fifo_pop_left;
wire fifo_fsm_error;
i2s_to_wb_fifo_fsm
i_i2s_to_wb_fifo_fsm
(
.i2s_ws_edge(i2s_ws_edge_s),
.i2s_ws_i(i2s_ws_i_s),
.fifo_enable(i2s_enable),
.fifo_empty(fifo_empty),
.fifo_ack(fifo_ack_s),
.fifo_pop_right(fifo_pop_right),
.fifo_pop_left(fifo_pop_left),
.fifo_fsm_error(fifo_fsm_error),
.fifo_ready(fifo_ready),
.i2s_clk_i(i2s_clk_i),
.i2s_rst_i(i2s_rst_i)
);
//---------------------------------------------------
//
i2s_to_wb_tx_dma #( .DMA_BUFFER_MAX_WIDTH(DMA_BUFFER_MAX_WIDTH) )
i_tx_dma_right
(
.wbm_data_i(wbm_right_data_i),
.wbm_data_o(wbm_right_data_o),
.wbm_addr_o(wbm_right_addr_o),
.wbm_sel_o(wbm_right_sel_o),
.wbm_we_o(wbm_right_we_o),
.wbm_cyc_o(wbm_right_cyc_o),
.wbm_stb_o(wbm_right_stb_o),
.wbm_ack_i(wbm_right_ack_i),
.wbm_err_i(wbm_right_err_i),
.wbm_rty_i(wbm_right_rty_i),
.i2s_enable(i2s_enable),
.fifo_pop(fifo_pop_right),
.fifo_empty(fifo_empty),
.dma_rd_pointer_o(dma_rd_pointer_o),
.dma_rd_pointer_i(dma_rd_pointer_i),
.dma_rd_pointer_we(dma_rd_pointer_we),
.dma_word_size(dma_word_size),
.dma_buffer_size(dma_buffer_size),
.dma_overflow_error(dma_overflow_error),
.i2s_clk_i(i2s_clk_i),
.i2s_rst_i(i2s_rst_i)
);
 
//---------------------------------------------------
// assign outputs
assign fifo_left_data = 32'h0;
assign fifo_right_data = wbm_right_data_o;
 
endmodule
 
 
 
/i2s_to_wb/trunk/src/i2s_to_wb_tx.v
0,0 → 1,79
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
`include "timescale.v"
 
 
module
i2s_to_wb_tx
(
input [31:0] fifo_right_data,
input [31:0] fifo_left_data,
input fifo_ready,
output reg fifo_ack,
output i2s_ws_edge,
input i2s_enable,
input i2s_sck_i,
input i2s_ws_i,
output i2s_sd_o
);
 
//---------------------------------------------------
// fifo_ready edge detection
reg [2:0] fifo_ready_r;
wire fifo_ready_s = fifo_ready_r[1];
 
always @(posedge i2s_sck_i)
fifo_ready_r <= {fifo_ready_r[1:0], fifo_ready};
 
wire fifo_ready_rise_edge = (fifo_ready_r[1] ^ fifo_ready_r[2]) & fifo_ready_r[1];
 
 
//---------------------------------------------------
// i2s_ws_i edge detection
reg [1:0] i2s_ws_i_r;
 
always @(posedge i2s_sck_i)
i2s_ws_i_r <= {i2s_ws_i_r[0], i2s_ws_i};
 
wire i2s_ws_rise_edge;
wire i2s_ws_fall_edge;
 
assign i2s_ws_rise_edge = (i2s_ws_i_r[0] ^ i2s_ws_i_r[1]) & i2s_ws_i_r[0]; // right
assign i2s_ws_fall_edge = (i2s_ws_i_r[0] ^ i2s_ws_i_r[1]) & ~i2s_ws_i_r[0]; // left
 
 
//---------------------------------------------------
// data out shift reg
reg [31:0] sd_r;
wire [31:0] sd_w = i2s_ws_i ? fifo_right_data : fifo_left_data;
 
always @(negedge i2s_sck_i)
if( i2s_ws_edge )
sd_r <= sd_w;
else
sd_r <= {sd_r[30:0], 1'b0};
 
//---------------------------------------------------
// ack flop
always @(posedge i2s_sck_i)
if( fifo_ready_s & i2s_ws_edge )
fifo_ack <= 1'b1;
else if( ~fifo_ready_s )
fifo_ack <= 1'b0;
//---------------------------------------------------
// assign outputs
 
assign i2s_sd_o = sd_r[31];
assign i2s_ws_edge = i2s_ws_rise_edge | i2s_ws_fall_edge;
 
endmodule
 
 
 
/i2s_to_wb/trunk/src/i2s_to_wb_tx_dma.v
0,0 → 1,129
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
`include "timescale.v"
 
 
module
i2s_to_wb_tx_dma
#(
parameter DMA_BUFFER_MAX_WIDTH = 12
)
(
input [31:0] wbm_data_i,
output [31:0] wbm_data_o,
output [31:0] wbm_addr_o,
output [3:0] wbm_sel_o,
output wbm_we_o,
output wbm_cyc_o,
output wbm_stb_o,
input wbm_ack_i,
input wbm_err_i,
input wbm_rty_i,
input i2s_enable,
 
input fifo_pop,
output fifo_empty,
output [31:0] dma_rd_pointer_o,
input [31:0] dma_rd_pointer_i,
input dma_rd_pointer_we,
input [(DMA_BUFFER_MAX_WIDTH - 1):0] dma_word_size,
input [(DMA_BUFFER_MAX_WIDTH - 1):0] dma_buffer_size,
output dma_overflow_error,
input i2s_clk_i,
output i2s_rst_i
);
 
//---------------------------------------------------
// fifo
wire fifo_wr_enable;
wire fifo_full;
sync_fifo #( .depth(4), .width(32) )
i_fifo
(
.clk(i2s_clk_i),
.reset(i2s_rst_i),
.wr_enable(fifo_wr_enable),
.rd_enable( fifo_pop ),
.empty(fifo_empty),
.full(fifo_full),
.rd_data(wbm_data_o),
.wr_data(wbm_data_i),
.count()
);
//---------------------------------------------------
//
wire dma_fsm_error;
i2s_to_wb_dma_fsm
i_i2s_to_wb_dma_fsm
(
.dma_enable(i2s_enable),
.dma_ack_i(wbm_ack_i),
.fifo_empty(fifo_empty),
.fifo_full(fifo_full),
.fifo_wr_enable(fifo_wr_enable),
.dma_fsm_error(dma_fsm_error),
.dma_clk_i(i2s_clk_i),
.dma_rst_i(i2s_rst_i)
);
 
//---------------------------------------------------
//
reg [31:0] dma_buffer_base_r;
wire [31:DMA_BUFFER_MAX_WIDTH] dma_buffer_base_w = dma_buffer_base_r[31:DMA_BUFFER_MAX_WIDTH];
always @(posedge i2s_clk_i)
if( i2s_rst_i )
dma_buffer_base_r <= 0;
else if( dma_rd_pointer_we )
dma_buffer_base_r <= dma_rd_pointer_i;
 
//---------------------------------------------------
//
reg [DMA_BUFFER_MAX_WIDTH:0] dma_rd_pointer_o_r;
wire [(DMA_BUFFER_MAX_WIDTH - 1):0] dma_middle = dma_buffer_base_r[(DMA_BUFFER_MAX_WIDTH - 1):0] + {1'b0, dma_buffer_size[(DMA_BUFFER_MAX_WIDTH - 1):1]};
wire [(DMA_BUFFER_MAX_WIDTH - 1):0] dma_bottom = dma_buffer_base_r[(DMA_BUFFER_MAX_WIDTH - 1):0] + dma_buffer_size - dma_word_size - 1;
always @(posedge i2s_clk_i)
if( dma_rd_pointer_we )
dma_rd_pointer_o_r <= {1'b0, dma_buffer_base_r[(DMA_BUFFER_MAX_WIDTH - 1):0]};
else if( dma_rd_pointer_o_r > dma_bottom )
dma_rd_pointer_o_r <= {1'b0, dma_buffer_base_r[(DMA_BUFFER_MAX_WIDTH - 1):0]};
else if(fifo_wr_enable)
dma_rd_pointer_o_r <= dma_rd_pointer_o_r + dma_word_size;
 
//---------------------------------------------------
// assign outputs
assign dma_rd_pointer_o = {dma_buffer_base_w, dma_rd_pointer_o_r[(DMA_BUFFER_MAX_WIDTH - 1):0]};
assign dma_overflow_error = dma_rd_pointer_o_r[DMA_BUFFER_MAX_WIDTH];
assign wbm_addr_o = {dma_buffer_base_w, dma_rd_pointer_o_r[(DMA_BUFFER_MAX_WIDTH - 1):0]};
assign wbm_sel_o = 4'b1111;
assign wbm_we_o = 1'b0;
assign wbm_cyc_o = fifo_wr_enable;
assign wbm_stb_o = fifo_wr_enable;
endmodule
 
 
/i2s_to_wb/trunk/src/timescale.v
0,0 → 1,129
`timescale 1ns/10ps
/i2s_to_wb/trunk/src/i2s_to_wb_top.v
0,0 → 1,166
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
`include "timescale.v"
 
 
module
i2s_to_wb_top
(
input [31:0] wbs_data_i,
output [31:0] wbs_data_o,
input [31:0] wbs_addr_i,
input [3:0] wbs_sel_i,
input wbs_we_i,
input wbs_cyc_i,
input wbs_stb_i,
output wbs_ack_o,
output wbs_err_o,
output wbs_rty_o,
 
input i2s_sck_i,
input i2s_ws_i,
output i2s_sd_o,
 
input i2s_clk_i,
input i2s_rst_i
);
//---------------------------------------------------
// register encoder
reg [3:0] register_index_r;
 
always @(*)
case( wbs_addr_i[19:0] )
20'h0_0000: register_index_r = 4'h0;
20'h0_0004: register_index_r = 4'h1;
20'h0_0008: register_index_r = 4'h2;
20'h0_000c: register_index_r = 4'h3;
20'h0_0010: register_index_r = 4'h4;
default: register_index_r = 4'hf;
endcase
 
 
//---------------------------------------------------
// register offset 0x0 --
reg [31:0] i2s_register_0;
wire i2s_register_0_we = (wbs_cyc_i & wbs_stb_i & wbs_we_i) & (register_index_r == 4'h0);
 
always @( posedge i2s_clk_i )
if( i2s_rst_i )
i2s_register_0 <= 32'h00000000;
else if( i2s_register_0_we )
i2s_register_0 <= wbs_data_i;
 
 
//---------------------------------------------------
// register offset 0x4 --
reg [31:0] i2s_register_1;
 
always @( posedge i2s_clk_i )
if( i2s_rst_i )
i2s_register_1 <= 32'h00000000;
else if( (wbs_cyc_i & wbs_stb_i & wbs_we_i) & (register_index_r == 4'h1) )
i2s_register_1 <= wbs_data_i;
 
//---------------------------------------------------
// register offset 0x8 -- read only
wire [31:0] i2s_register_2;
 
//---------------------------------------------------
// register offset 0xc -- read only
wire [31:0] i2s_register_3;
 
//---------------------------------------------------
// register offset 0x10 -- write only
wire [31:0] i2s_register_4;
wire i2s_register_4_we = (wbs_cyc_i & wbs_stb_i & wbs_we_i) & (register_index_r == 4'h4);
 
//---------------------------------------------------
// register mux
reg [31:0] wbs_data_o_r;
 
always @(*)
case( register_index_r )
4'h0: wbs_data_o_r = i2s_register_0;
4'h1: wbs_data_o_r = i2s_register_1;
4'h2: wbs_data_o_r = i2s_register_2;
4'h3: wbs_data_o_r = i2s_register_3;
4'h4: wbs_data_o_r = i2s_register_4;
4'hf: wbs_data_o_r = 32'h1bad_c0de;
default: wbs_data_o_r = 32'h1bad_c0de;
endcase
 
//---------------------------------------------------
// wishbone clock domain
wire i2s_ws_edge;
wire [31:0] fifo_right_data;
wire [31:0] fifo_left_data;
wire fifo_ack;
wire fifo_ready;
i2s_to_wb_tx_if #( .DMA_BUFFER_MAX_WIDTH(12) )
i_i2s_to_wb_tx_if
(
.i2s_enable(i2s_register_0[0]),
.i2s_ws_edge(i2s_ws_edge),
.i2s_ws_i(i2s_ws_i),
.fifo_ack(fifo_ack),
.fifo_ready(fifo_ready),
.fifo_right_data(fifo_right_data),
.fifo_left_data(fifo_left_data),
.dma_rd_pointer_i( wbs_data_i ),
.dma_rd_pointer_o( i2s_register_4 ),
.dma_rd_pointer_we( i2s_register_4_we ),
.dma_word_size( {9'h0, 3'b100} ),
.dma_buffer_size( 12'h1BC ),
.dma_overflow_error(),
.i2s_clk_i(i2s_clk_i),
.i2s_rst_i(i2s_rst_i)
);
//---------------------------------------------------
// i2s clock domain
i2s_to_wb_tx
i_i2s_to_wb_tx
(
.fifo_right_data(fifo_right_data),
.fifo_left_data(fifo_left_data),
.fifo_ready(fifo_ready),
.fifo_ack(fifo_ack),
.i2s_ws_edge(i2s_ws_edge),
.i2s_enable(i2s_register_0[0]),
.i2s_sck_i(i2s_sck_i),
.i2s_ws_i(i2s_ws_i),
.i2s_sd_o(i2s_sd_o)
);
//---------------------------------------------------
// assign outputs
assign wbs_data_o = wbs_data_o_r;
assign wbs_ack_o = wbs_cyc_i & wbs_stb_i;
assign wbs_err_o = 1'b0;
assign wbs_rty_o = 1'b0;
 
endmodule
/i2s_to_wb/trunk/src/tone_440_rom.v
0,0 → 1,26
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
`include "timescale.v"
 
 
module tone_440_rom( addr, q );
 
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 7;
input [(ADDR_WIDTH-1):0] addr;
output [(DATA_WIDTH-1):0] q;
// Declare the RAM variable
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
reg [ADDR_WIDTH-1:0] addr_reg;
assign q = ram[addr];
 
initial
$readmemh( "../../../../i2s_to_wb/scilab/tone_roms/tone_440_at_48000sps_rom.txt", ram );
 
endmodule
/i2s_to_wb/trunk/i2s_to_wb_files.txt
0,0 → 1,9
 
// +incdir+${ROOT_DIR}/de1_olpcl2294_system/src
 
${ROOT_DIR}/i2s_to_wb/src/i2s_to_wb_tx.v
${ROOT_DIR}/i2s_to_wb/src/tone_440_rom.v
${ROOT_DIR}/i2s_to_wb/src/tone_660_rom.v
${ROOT_DIR}/i2s_to_wb/src/sync_fifo.v
${ROOT_DIR}/i2s_to_wb/src/i2s_to_wb_top.v
${ROOT_DIR}/i2s_to_wb/src/i2s_to_wb_fifo_fsm.v
/i2s_to_wb/trunk/docs/I2SBUS.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/i2s_to_wb/trunk/docs/I2SBUS.pdf
i2s_to_wb/trunk/docs/I2SBUS.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: i2s_to_wb/trunk/sim/tests/debug/the_test.v =================================================================== --- i2s_to_wb/trunk/sim/tests/debug/the_test.v (nonexistent) +++ i2s_to_wb/trunk/sim/tests/debug/the_test.v (revision 2) @@ -0,0 +1,70 @@ +// -------------------------------------------------------------------- +// +// -------------------------------------------------------------------- + +`timescale 1ns/10ps + + +module the_test( + input tb_clk, + input tb_rst + ); + + reg [31:0] d_out; + + task run_the_test; + begin + +// -------------------------------------------------------------------- +// insert test below +// -------------------------------------------------------------------- + + repeat(6) @(posedge tb_clk); + +// wbm.wb_write(0, 0, 32'h6000_0004, 32'habba_beef); +// wbm.wb_write(0, 0, 32'h6000_0000, 32'h0000_0001); +// wbm.wb_write(0, 0, 32'h6000_0000, 32'h0000_0000); +// repeat(2) @(posedge tb_clk); +// +// wbm.wb_write(0, 0, 32'h6000_0004, 32'hcafe_1a7a); +// wbm.wb_write(0, 0, 32'h6000_0000, 32'h0000_0001); +// wbm.wb_write(0, 0, 32'h6000_0000, 32'h0000_0000); +// repeat(2) @(posedge tb_clk); +// +// wbm.wb_write(0, 0, 32'h6000_0004, 32'h3333_3333); +// wbm.wb_write(0, 0, 32'h6000_0000, 32'h0000_0001); +// wbm.wb_write(0, 0, 32'h6000_0000, 32'h0000_0000); +// repeat(2) @(posedge tb_clk); +// +// +// wbm.wb_write(0, 0, 32'h6000_0004, 32'hffff_ffff); +// wbm.wb_write(0, 0, 32'h6000_0000, 32'h0000_0001); +// wbm.wb_write(0, 0, 32'h6000_0000, 32'h0000_0000); +// repeat(2) @(posedge tb_clk); + + wbm.wb_write(0, 0, 32'h6000_0010, 32'h8001_0000); + repeat(2) @(posedge tb_clk); + + // enable i2s + repeat(2) @(posedge tb_clk); + rx_bfm.enable_bfm(); + + repeat(2) @(posedge tb_clk); + wbm.wb_write(0, 0, 32'h6000_0000, 32'h0000_0001); + +// repeat(6*32) @(posedge tb_clk); + + + repeat('h72) @(posedge i_i2s_to_wb_top.i2s_ws_i); + + +// -------------------------------------------------------------------- +// insert test above +// -------------------------------------------------------------------- + + end + endtask + + +endmodule + Index: i2s_to_wb/trunk/sim/tests/debug/debug.mpf =================================================================== --- i2s_to_wb/trunk/sim/tests/debug/debug.mpf (nonexistent) +++ i2s_to_wb/trunk/sim/tests/debug/debug.mpf (revision 2) @@ -0,0 +1,467 @@ +; Copyright 1991-2009 Mentor Graphics Corporation +; +; All Rights Reserved. +; +; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF +; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. +; + +[Library] +std = $MODEL_TECH/../std +ieee = $MODEL_TECH/../ieee +verilog = $MODEL_TECH/../verilog +vital2000 = $MODEL_TECH/../vital2000 +std_developerskit = $MODEL_TECH/../std_developerskit +synopsys = $MODEL_TECH/../synopsys +modelsim_lib = $MODEL_TECH/../modelsim_lib +sv_std = $MODEL_TECH/../sv_std + +; Altera Primitive libraries +; +; VHDL Section +; +altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf +altera = $MODEL_TECH/../altera/vhdl/altera +lpm = $MODEL_TECH/../altera/vhdl/220model +220model = $MODEL_TECH/../altera/vhdl/220model +max = $MODEL_TECH/../altera/vhdl/max +maxii = $MODEL_TECH/../altera/vhdl/maxii +stratix = $MODEL_TECH/../altera/vhdl/stratix +stratixii = $MODEL_TECH/../altera/vhdl/stratixii +stratixiigx = $MODEL_TECH/../altera/vhdl/stratixiigx +hardcopyii = $MODEL_TECH/../altera/vhdl/hardcopyii +hardcopyiii = $MODEL_TECH/../altera/vhdl/hardcopyiii +hardcopyiv = $MODEL_TECH/../altera/vhdl/hardcopyiv +cyclone = $MODEL_TECH/../altera/vhdl/cyclone +cycloneii = $MODEL_TECH/../altera/vhdl/cycloneii +cycloneiii = $MODEL_TECH/../altera/vhdl/cycloneiii +cycloneiiils = $MODEL_TECH/../altera/vhdl/cycloneiiils +sgate = $MODEL_TECH/../altera/vhdl/sgate +stratixgx = $MODEL_TECH/../altera/vhdl/stratixgx +altgxb = $MODEL_TECH/../altera/vhdl/altgxb +stratixgx_gxb = $MODEL_TECH/../altera/vhdl/stratixgx_gxb +stratixiigx_hssi = $MODEL_TECH/../altera/vhdl/stratixiigx_hssi +arriagx_hssi = $MODEL_TECH/../altera/vhdl/arriagx_hssi +arriaii = $MODEL_TECH/../altera/vhdl/arriaii +arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi +arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip +arriagx = $MODEL_TECH/../altera/vhdl/arriagx +altgxb_lib = $MODEL_TECH/../altera/vhdl/altgxb +stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv +stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi +stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip +cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv +cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi +cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip +hardcopyiv_hssi = $MODEL_TECH/../altera/vhdl/hardcopyiv_hssi +hardcopyiv_pcie_hip = $MODEL_TECH/../altera/vhdl/hardcopyiv_pcie_hip +; +; Verilog Section +; +altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf +altera_ver = $MODEL_TECH/../altera/verilog/altera +lpm_ver = $MODEL_TECH/../altera/verilog/220model +220model_ver = $MODEL_TECH/../altera/verilog/220model +max_ver = $MODEL_TECH/../altera/verilog/max +maxii_ver = $MODEL_TECH/../altera/verilog/maxii +stratix_ver = $MODEL_TECH/../altera/verilog/stratix +stratixii_ver = $MODEL_TECH/../altera/verilog/stratixii +stratixiigx_ver = $MODEL_TECH/../altera/verilog/stratixiigx +arriagx_ver = $MODEL_TECH/../altera/verilog/arriagx +hardcopyii_ver = $MODEL_TECH/../altera/verilog/hardcopyii +hardcopyiii_ver = $MODEL_TECH/../altera/verilog/hardcopyiii +hardcopyiv_ver = $MODEL_TECH/../altera/verilog/hardcopyiv +cyclone_ver = $MODEL_TECH/../altera/verilog/cyclone +cycloneii_ver = $MODEL_TECH/../altera/verilog/cycloneii +cycloneiii_ver = $MODEL_TECH/../altera/verilog/cycloneiii +cycloneiiils_ver = $MODEL_TECH/../altera/verilog/cycloneiiils +sgate_ver = $MODEL_TECH/../altera/verilog/sgate +stratixgx_ver = $MODEL_TECH/../altera/verilog/stratixgx +altgxb_ver = $MODEL_TECH/../altera/verilog/altgxb +stratixgx_gxb_ver = $MODEL_TECH/../altera/verilog/stratixgx_gxb +stratixiigx_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiigx_hssi +arriagx_hssi_ver = $MODEL_TECH/../altera/verilog/arriagx_hssi +arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii +arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi +arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip +stratixiii_ver = $MODEL_TECH/../altera/verilog/stratixiii +stratixiii = $MODEL_TECH/../altera/vhdl/stratixiii +stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv +stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi +stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip +cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv +cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi +cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip +hardcopyiv_hssi_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_hssi +hardcopyiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_pcie_hip + +work = work +sim = ../../../libs/sim +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +VHDL93 = 2002 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +[vlog] + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Turn on incremental compilation of modules. Default is off. +; Incremental = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +[vsim] +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +resolution = 10ps + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 1 us + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 5000 + +; Directive to license manager: +; vhdl Immediately reserve a VHDL license +; vlog Immediately reserve a Verilog license +; plus Immediately reserve a VHDL and Verilog license +; nomgc Do not look for Mentor Graphics Licenses +; nomti Do not look for Model Technology Licenses +; noqueue Do not wait in the license queue when a license isn't available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license +; License = plus + +; Stop the simulator after a VHDL/Verilog assertion message +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; Assertion Message Format +; %S - Severity Level +; %R - Report Message +; %T - Time of assertion +; %D - Delta +; %I - Instance or Region pathname (if available) +; %% - print '%' character +; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" + +; Assertion File - alternate file for storing VHDL/Verilog assertion messages +; AssertFile = assert.log + +; Default radix for all windows and commands... +; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned +DefaultRadix = symbolic + +; VSIM Startup command +; Startup = do startup.do + +; File for saving command transcript +TranscriptFile = transcript + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example, sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings from the std_logic_arith, std_logic_unsigned +; and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from the IEEE numeric_std and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Control the format of the (VHDL) FOR generate statement label +; for each iteration. Do not quote it. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate_label; the %d represents the generate parameter value +; at a particular generate iteration (this is the position number if +; the generate parameter is of an enumeration type). Embedded whitespace +; is allowed (but discouraged); leading and trailing whitespace is ignored. +; Application of the format must result in a unique scope name over all +; such names in the design so that name lookup can function properly. +; GenerateFormat = %s__%d + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave +; DefaultRestartOptions = -force + +; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs +; (> 500 megabyte memory footprint). Default is disabled. +; Specify number of megabytes to lock. +; LockedMemory = 1000 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Automatic SDF compilation +; Disables automatic compilation of SDF files in flows that support it. +; Default is on, uncomment to turn off. +; NoAutoSDFCompile = 1 + +[lmc] + +[msg_system] +; Change a message severity or suppress a message. +; The format is: = [,...] +; Examples: +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3043 +; The command verror can be used to get the complete +; description of a message. + +; Control transcripting of elaboration/runtime messages. +; The default is to have messages appear in the transcript and +; recorded in the wlf file (messages that are recorded in the +; wlf file can be viewed in the MsgViewer). The other settings +; are to send messages only to the transcript or only to the +; wlf file. The valid values are +; both {default} +; tran {transcript only} +; wlf {wlf file only} +; msgmode = both +[Project] +; Warning -- Do not edit the project properties directly. +; Property names are dynamic in nature and property +; values have special syntax. Changing property data directly +; can result in a corrupt MPF file. All project properties +; can be modified through project window dialogs. +Project_Version = 6 +Project_DefaultLib = work +Project_SortMethod = unused +Project_Files_Count = 10 +Project_File_0 = V:/work/i2s_to_wb/src/i2s_to_wb_tx_if.v +Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1301358594 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+V:../../../src compile_order 8 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_1 = V:/work/i2s_to_wb/sim/tests/debug/the_test.v +Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1301351396 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_2 = V:/work/i2s_to_wb/src/tone_660_rom.v +Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1301097186 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+V:../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 7 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_3 = V:/work/i2s_to_wb/src/tone_440_rom.v +Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1301097146 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+V:../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 6 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_4 = V:/work/i2s_to_wb/src/i2s_to_wb_top.v +Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1301351280 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+V:../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 3 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_5 = V:/work/i2s_to_wb/src/i2s_to_wb_dma_fsm.v +Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1301350352 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+V:../../../src compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_6 = V:/work/i2s_to_wb/src/i2s_to_wb_tx.v +Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1301090244 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+V:../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 4 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_7 = V:/work/i2s_to_wb/src/i2s_to_wb_tx_dma.v +Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1301358614 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+V:../../../src compile_order 9 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_8 = V:/work/i2s_to_wb/src/sync_fifo.v +Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1298324862 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_9 = V:/work/i2s_to_wb/src/i2s_to_wb_fifo_fsm.v +Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1301088894 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+V:../../../src compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_Sim_Count = 0 +Project_Folder_Count = 0 +Echo_Compile_Output = 0 +Save_Compile_Report = 1 +Project_Opt_Count = 0 +ForceSoftPaths = 0 +ProjectStatusDelay = 5000 +VERILOG_DoubleClick = Edit +VERILOG_CustomDoubleClick = +SYSTEMVERILOG_DoubleClick = Edit +SYSTEMVERILOG_CustomDoubleClick = +VHDL_DoubleClick = Edit +VHDL_CustomDoubleClick = +PSL_DoubleClick = Edit +PSL_CustomDoubleClick = +TEXT_DoubleClick = Edit +TEXT_CustomDoubleClick = +SYSTEMC_DoubleClick = Edit +SYSTEMC_CustomDoubleClick = +TCL_DoubleClick = Edit +TCL_CustomDoubleClick = +MACRO_DoubleClick = Edit +MACRO_CustomDoubleClick = +VCD_DoubleClick = Edit +VCD_CustomDoubleClick = +SDF_DoubleClick = Edit +SDF_CustomDoubleClick = +XML_DoubleClick = Edit +XML_CustomDoubleClick = +LOGFILE_DoubleClick = Edit +LOGFILE_CustomDoubleClick = +UCDB_DoubleClick = Edit +UCDB_CustomDoubleClick = +Project_Major_Version = 6 +Project_Minor_Version = 5 Index: i2s_to_wb/trunk/sim/tests/debug/do_sim.do =================================================================== --- i2s_to_wb/trunk/sim/tests/debug/do_sim.do (nonexistent) +++ i2s_to_wb/trunk/sim/tests/debug/do_sim.do (revision 2) @@ -0,0 +1,11 @@ + +# vmap sim ../../../libs/sim + +vsim -f ../../../libs/library_files.txt sim.tb_top + +# view wave +# do ./wave.do + +# run 2us + +# wave zoomrange 400ns 1400ns Index: i2s_to_wb/trunk/sim/models/i2s_rx_bfm.v =================================================================== --- i2s_to_wb/trunk/sim/models/i2s_rx_bfm.v (nonexistent) +++ i2s_to_wb/trunk/sim/models/i2s_rx_bfm.v (revision 2) @@ -0,0 +1,121 @@ +// -------------------------------------------------------------------- +// +// -------------------------------------------------------------------- + +`timescale 1ns/10ps + + +module + i2s_rx_bfm + #( + parameter DELAY = 3 + ) + ( + input [31:0] bfm_data_i, + output [31:0] bfm_data_o, + input [31:0] bfm_addr_i, + input [3:0] bfm_sel_i, + input bfm_we_i, + input bfm_cyc_i, + input bfm_stb_i, + output bfm_ack_o, + output bfm_err_o, + output bfm_rty_o, + + output bfm_sck_o, + output bfm_ws_o, + input bfm_sck_i, + input bfm_ws_i, + input bfm_sd_i, + + input bfm_clk_i, + input bfm_rst_i + ); + + //--------------------------------------------------- + // init regs + reg enable_r; + + initial + begin + enable_r <= 1'b0; + end + + + //--------------------------------------------------- + // enable + task enable_bfm; + begin + + enable_r <= 1'b1; + + $display( "-#- %15.t | %m: BFM enabled.", $time ); + + end + endtask + + + //--------------------------------------------------- + // disable + task disable_bfm; + begin + + enable_r <= 1'b0; + + $display( "-#- %15.t | %m: BFM disabled.", $time ); + + end + endtask + + + //--------------------------------------------------- + // generate ws + reg [5:0] count; + + always @(negedge bfm_clk_i) + if( bfm_rst_i ) + count <= 0; + else + count <= count + 1; + + //--------------------------------------------------- + // + reg [31:0] i2s_data; + + always @(posedge bfm_sck_i) + i2s_data <= { i2s_data[30:0], bfm_sd_i }; + + reg [1:0] bfm_ws_i_r; + + always @(posedge bfm_sck_i) + bfm_ws_i_r <= {bfm_ws_i_r[0], bfm_ws_i}; + + wire bfm_ws_rise_edge; + wire bfm_ws_fall_edge; + + assign bfm_ws_rise_edge = (bfm_ws_i_r[0] ^ bfm_ws_i_r[1]) & bfm_ws_i_r[0]; // right + assign bfm_ws_fall_edge = (bfm_ws_i_r[0] ^ bfm_ws_i_r[1]) & ~bfm_ws_i_r[0]; // left + + + //--------------------------------------------------- + // + always @(posedge bfm_sck_i) + begin + + if(bfm_ws_fall_edge) + $display( "-#- %15.t | %m: right channel is 0x%8.x.", $time, i2s_data ); + + if(bfm_ws_rise_edge) + $display( "-#- %15.t | %m: left channel is 0x%8.x.", $time, i2s_data ); + + end + + + //--------------------------------------------------- + // assign outputs + assign #DELAY bfm_ws_o = enable_r ? count[5] : 1'bz; + assign #DELAY bfm_sck_o = enable_r ? bfm_clk_i : 1'bz; + + +endmodule + Index: i2s_to_wb/trunk/sim/__notes.txt =================================================================== Index: i2s_to_wb/trunk/sim/src/tb_clk.v =================================================================== --- i2s_to_wb/trunk/sim/src/tb_clk.v (nonexistent) +++ i2s_to_wb/trunk/sim/src/tb_clk.v (revision 2) @@ -0,0 +1,28 @@ +// -------------------------------------------------------------------- +// +// -------------------------------------------------------------------- + +`timescale 1ns/10ps + + +module + tb_clk + #( + parameter CLK_PERIOD = 32 + ) + ( + output clk_out + ); + + reg tb_clk; + + initial + tb_clk <= 1'b1; + + always + #(CLK_PERIOD/2) tb_clk <= ~tb_clk; + + assign clk_out = tb_clk; + +endmodule + Index: i2s_to_wb/trunk/sim/src/tb_reset.v =================================================================== --- i2s_to_wb/trunk/sim/src/tb_reset.v (nonexistent) +++ i2s_to_wb/trunk/sim/src/tb_reset.v (revision 2) @@ -0,0 +1,37 @@ +// -------------------------------------------------------------------- +// +// -------------------------------------------------------------------- + +`timescale 1ns/10ps + + +module + tb_reset + #( + parameter ASSERT_TIME = 32 + ) + ( + output rst_out + ); + + reg tb_rst; + + initial + tb_rst <= 1'b1; + + task assert_reset; + begin + + tb_rst = 1'b1; + #ASSERT_TIME; + tb_rst = 1'b0; + + $display( "-#- %15.t | %m: tb_rst asserted!", $time ); + + end + endtask + + assign rst_out = tb_rst; + +endmodule + Index: i2s_to_wb/trunk/sim/src/tb_top.v =================================================================== --- i2s_to_wb/trunk/sim/src/tb_top.v (nonexistent) +++ i2s_to_wb/trunk/sim/src/tb_top.v (revision 2) @@ -0,0 +1,149 @@ +// -------------------------------------------------------------------- +// +// -------------------------------------------------------------------- + +`timescale 1ns/10ps + + +module tb_top(); + + // -------------------------------------------------------------------- + // clock & reset + + parameter CLK_PERIOD = 54; // use ~18.4MHZ for main clk + + wire tb_clk; + tb_clk #( .CLK_PERIOD(CLK_PERIOD) ) i_tb_clk ( tb_clk ); + + + wire tb_rst; + + tb_reset #( .ASSERT_TIME(CLK_PERIOD*10) ) i_tb_rst( tb_rst ); + + initial + begin + $display("\n^^^---------------------------------"); + #(CLK_PERIOD/3); + i_tb_rst.assert_reset(); + end + + + // -------------------------------------------------------------------- + // system wires + + + +// -------------------------------------------------------------------- +// dut + wire [31:0] wbs_tx_data_i; + wire [31:0] wbs_tx_data_o; + wire [31:0] wbs_tx_addr_i; + wire [3:0] wbs_tx_sel_i; + wire wbs_tx_we_i; + wire wbs_tx_cyc_i; + wire wbs_tx_stb_i; + wire wbs_tx_ack_o; + wire wbs_tx_err_o; + wire wbs_tx_rty_o; + + wire i2s_tx_sck; + wire i2s_tx_ws; + wire i2s_tx_sd; + + i2s_to_wb_top + i_i2s_to_wb_top + ( + .wbs_data_i(wbs_tx_data_i), + .wbs_data_o(wbs_tx_data_o), + .wbs_addr_i(wbs_tx_addr_i), + .wbs_sel_i(wbs_tx_sel_i), + .wbs_we_i(wbs_tx_we_i), + .wbs_cyc_i(wbs_tx_cyc_i), + .wbs_stb_i(wbs_tx_stb_i), + .wbs_ack_o(wbs_tx_ack_o), + .wbs_err_o(wbs_tx_err_o), + .wbs_rty_o(wbs_tx_rty_o), + + .i2s_sck_i(i2s_tx_sck), + .i2s_ws_i(i2s_tx_ws), + .i2s_sd_o(i2s_tx_sd), + + .i2s_clk_i(tb_clk), + .i2s_rst_i(tb_rst) + ); + + + // -------------------------------------------------------------------- + // i2s_rx_bfm + i2s_rx_bfm + rx_bfm + ( + .bfm_data_i(wbs_tx_data_o), + .bfm_data_o(wbs_tx_data_i), + .bfm_addr_i(wbs_tx_addr_i), + .bfm_sel_i(wbs_tx_sel_i), + .bfm_we_i(wbs_tx_we_i), + .bfm_cyc_i(wbs_tx_cyc_i), + .bfm_stb_i(wbs_tx_stb_i), + .bfm_ack_o(wbs_tx_ack_o), + .bfm_err_o(wbs_tx_err_o), + .bfm_rty_o(wbs_tx_rty_o), + + .bfm_sck_o(i2s_tx_sck), + .bfm_ws_o(i2s_tx_ws), + .bfm_sck_i(i2s_tx_sck), + .bfm_ws_i(i2s_tx_ws), + .bfm_sd_i(i2s_tx_sd), + + .bfm_clk_i(tb_clk), + .bfm_rst_i(tb_rst) + ); + + + // -------------------------------------------------------------------- + // wb_hi_master_model + wb_master_model + wbm + ( + .clk(tb_clk), + .rst(tb_rst), + .adr(wbs_tx_addr_i), + .din(wbs_tx_data_o), + .dout(wbs_tx_data_i), + .cyc(wbs_tx_cyc_i), + .stb(wbs_tx_stb_i), + .we(wbs_tx_we_i), + .sel(wbs_tx_sel_i), + .ack(wbs_tx_ack_o), + .err(wbs_tx_err_o), + .rty(wbs_tx_rty_o) + ); + + +// dut +// -------------------------------------------------------------------- + + +// -------------------------------------------------------------------- +// test + + the_test test( tb_clk, tb_rst ); + + initial + begin + + wait( ~tb_rst ); + + repeat(2) @(posedge tb_clk); + + test.run_the_test(); + + $display("\n^^^---------------------------------"); + $display("^^^ %15.t | Testbench done.\n", $time); + + $stop(); + + end + +endmodule + Index: i2s_to_wb/trunk/libs/library_files.txt =================================================================== --- i2s_to_wb/trunk/libs/library_files.txt (nonexistent) +++ i2s_to_wb/trunk/libs/library_files.txt (revision 2) @@ -0,0 +1,6 @@ +-L ./work + +-L $MODEL_TECH/../altera/verilog/cycloneii +-L $MODEL_TECH/../altera/verilog/altera_mf + +-L ../../../libs/sim Index: i2s_to_wb/trunk/libs/sim_files.txt =================================================================== --- i2s_to_wb/trunk/libs/sim_files.txt (nonexistent) +++ i2s_to_wb/trunk/libs/sim_files.txt (revision 2) @@ -0,0 +1,11 @@ + ++incdir+${ROOT_DIR}/i2s_to_wb/src + +${ROOT_DIR}/i2s_to_wb/sim/models/i2s_rx_bfm.v + +${ROOT_DIR}/i2s_to_wb/sim/src/tb_clk.v +${ROOT_DIR}/i2s_to_wb/sim/src/tb_reset.v +${ROOT_DIR}/i2s_to_wb/sim/src/tb_top.v + +${ROOT_DIR}/de1_olpcl2294_system/sim/models/wb_slave_model.v +${ROOT_DIR}/de1_olpcl2294_system/sim/models/wb_master_model.v Index: i2s_to_wb/trunk/libs/Makefile =================================================================== --- i2s_to_wb/trunk/libs/Makefile (nonexistent) +++ i2s_to_wb/trunk/libs/Makefile (revision 2) @@ -0,0 +1,65 @@ +# + +export ROOT_DIR = ../.. + +MODEL_TECH ?= /cygdrive/c/altera/91/modelsim_ase/win32aloem +PATH := ${MODEL_TECH}:${PATH} + + +VLIB = vlib +VLOG = vlog +VMAKE = vmake + +# WORK_LIBRARY_FILES += $(shell grep [\.]v[[:space:]]*$$ $(WORK_LIBRARY)_files.txt | tr '\n' ' ' ) + +WORK_LIBRARY += sim + + +ALL_MK_FILES = $(foreach mk, $(WORK_LIBRARY), ./$(mk)/$(mk).mk) +ALL_REFRESH = $(foreach refresh, $(WORK_LIBRARY), $(refresh)_refresh ) +# ALL_DEBUG = $(foreach debug, $(WORK_LIBRARY), $(debug)_debug ) +# ALL_INFO = $(foreach info, $(WORK_LIBRARY), ./$(info)/_info ) + + +define build_unit +$(1): $(1)_files.txt + @echo "-#- initial build of $$@ library." + $(VLIB) $$@ + $(VLOG) -O0 -work $$@ -f $$@_files.txt + @echo "-#- " + +./$(1)/$(1).mk: $(1)_files.txt + @echo "-#- generating unit make file for $$*." + $(VMAKE) $(1) > $$@ + @echo "-#- " + +$(1)_refresh: + @echo "-#- refreshing unit $(1)." + $$(MAKE) -f ./$(1)/$(1).mk + @echo "-#- " + +# $(1)_debug: +# @echo "-d- " +# @echo "-d- $$@ - $$* - $$% - $$< " +# @echo "-d- $(shell grep [\.]v[[:space:]]*$$ $(1)_files.txt | tr '\n' ' ' ) " +# @echo "-d- " + +endef + + +.PHONY: all clean + +all: $(WORK_LIBRARY) $(ALL_MK_FILES) $(ALL_REFRESH) +# all: debug +# all: $(WORK_LIBRARY) $(ALL_MK_FILES) $(ALL_DEBUG) + +$(foreach unit,$(WORK_LIBRARY),$(eval $(call build_unit,$(unit)))) + +clean: + -rm -Rf $(WORK_LIBRARY) + +# debug: +# @echo "-d- $@ - $* - $% - $< " +# @echo "-d- $(PATH) " + + Index: i2s_to_wb/trunk/scilab/sin_440hz/How to Create a Wave File using Scilab at Luman Magnum.URL =================================================================== --- i2s_to_wb/trunk/scilab/sin_440hz/How to Create a Wave File using Scilab at Luman Magnum.URL (nonexistent) +++ i2s_to_wb/trunk/scilab/sin_440hz/How to Create a Wave File using Scilab at Luman Magnum.URL (revision 2) @@ -0,0 +1,2 @@ +[InternetShortcut] +URL=http://www.lumanmagnum.net/physics/sci_wav.html Index: i2s_to_wb/trunk/scilab/sin_440hz/sin_8k_rom.txt =================================================================== --- i2s_to_wb/trunk/scilab/sin_440hz/sin_8k_rom.txt (nonexistent) +++ i2s_to_wb/trunk/scilab/sin_440hz/sin_8k_rom.txt (revision 2) @@ -0,0 +1,60 @@ +@00000001 + 00000000 + +@00000002 + 2a62822a + +@00000003 + 4ffcf005 + +@00000004 + 6c914cdd + +@00000005 + 7ce6370a + +@00000006 + 7f24051c + +@00000007 + 7309fb80 + +@00000008 + 59f599ff + +@00000009 + 36bb2e29 + +@0000000a + 0d541d58 + +@0000000b + e26c1e25 + +@0000000c + bada540a + +@0000000d + 9b1584db + +@0000000e + 86b32d59 + +@0000000f + 80000000 + +@00000010 + 87bd7b64 + +@00000011 + 9d0c1605 + +@00000012 + bd84761d + +@00000013 + e57cdd06 + +@00000014 + 1072f174 + Index: i2s_to_wb/trunk/scilab/sin_440hz/sin_8k.sci =================================================================== --- i2s_to_wb/trunk/scilab/sin_440hz/sin_8k.sci (nonexistent) +++ i2s_to_wb/trunk/scilab/sin_440hz/sin_8k.sci (revision 2) @@ -0,0 +1,34 @@ +// +// get one cycle of 440khz data for rom; +// + +Fs = 8192; +f = 440; + +samples_per_wavelength = ceil( (1/f)/(1/Fs) ); + +N = 0 : samples_per_wavelength; +x = 2 * %pi * (f / Fs) * N; + +y = sin(x); + +// plot(x, y); + +y_transpose = y'; + +wn = y_transpose / max(abs(y_transpose)); + +wn = wn * ((2^32) / 2); + +wn = round( wn ); + + + +u=file('open','sin_8k_rom.txt','unknown') //open the result file + +for i = 1:(samples_per_wavelength + 1), fprintf( u, '@%8.8x\n %8.8x\n\n', i, wn(i) ), end + +file('close',u) //close the result file + + + Index: i2s_to_wb/trunk/scilab/sin_440hz/sin_8k_wave.sci =================================================================== --- i2s_to_wb/trunk/scilab/sin_440hz/sin_8k_wave.sci (nonexistent) +++ i2s_to_wb/trunk/scilab/sin_440hz/sin_8k_wave.sci (revision 2) @@ -0,0 +1,17 @@ + +N = 0 : 88200; +Fs = 44100; +f = 440; +x = 2 * %pi * (f / Fs) * N; + +y = sin(x); + +plot(x, y); + +y_transpose = y'; + +wn = y_transpose / max(abs(y_transpose)); + +Ws = [wn ; wn]; + +wavwrite(Ws, Fs, 'first_wave.wav'); Index: i2s_to_wb/trunk/scilab/tone_roms/make_all.sci =================================================================== --- i2s_to_wb/trunk/scilab/tone_roms/make_all.sci (nonexistent) +++ i2s_to_wb/trunk/scilab/tone_roms/make_all.sci (revision 2) @@ -0,0 +1,14 @@ + +cd 'C:\qaz\_CVS_WORK\units\i2s_to_wb\scilab\tone_roms' + +clear + +exec('make_tone_rom.sci'); + +make_tone_rom( 440, 8000 ); +make_tone_rom( 660, 8000 ); + +make_tone_rom( 440, 48000 ); +make_tone_rom( 660, 48000 ); + +make_tone_rom( 1, 48000 ); Index: i2s_to_wb/trunk/scilab/tone_roms/make_tone_rom.sci =================================================================== --- i2s_to_wb/trunk/scilab/tone_roms/make_tone_rom.sci (nonexistent) +++ i2s_to_wb/trunk/scilab/tone_roms/make_tone_rom.sci (revision 2) @@ -0,0 +1,47 @@ +function [g] = make_tone_rom( tone_freq, sample_freq ) + +// Ouput variables initialisation (not found in input variables) +g=[]; + +// Number of arguments in function call +[%nargout,%nargin] = argn(0) + +// Display mode +mode(0); + +// Display warning for floating point exception +ieee(1); + + +// Fs = 8192; +// f = 440; +Fs = sample_freq; +f = tone_freq; + +samples_per_wavelength = ceil( (1/f)/(1/Fs) ); + +N = 0 : samples_per_wavelength; +x = 2 * %pi * (f / Fs) * N; + +y = sin(x); + +y_transpose = y'; + +wn = y_transpose / max(abs(y_transpose)); + +wn = wn * ((2^31) / 10); // leave one bit for sign and scale + +wn = round( wn ); + + +file_name = 'tone_' + string( tone_freq ) + '_at_' + string( sample_freq ) + 'sps_rom.txt'; + +u=file('open', file_name, 'unknown') //open the result file + +for i = 1:(samples_per_wavelength + 1), fprintf( u, '@%8.8x\n %8.8x\n\n', (i - 1), wn(i) ), end + +file('close',u) //close the result file + + +endfunction +

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