URL https://opencores.org/ocsvn/layer2/layer2/trunk

Subversion Repositories layer2

Compare Revisions

This comparison shows the changes necessary to convert path
```
/
```
from Rev 1 to Rev 2
↔ Reverse comparison
Compare Path: Rev

With Path: Rev

Rev 1 → Rev 2

/layer2/trunk/license.txt

0,0 → 1,674

/layer2/trunk/sw/void/view.h

0,0 → 1,154

/layer2/trunk/sw/void/main.c

0,0 → 1,264

/layer2/trunk/sw/void/void.bin Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

/layer2/trunk/sw/void/void.bin

layer2/trunk/sw/void/void.bin Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: layer2/trunk/sw/void/Makefile =================================================================== --- layer2/trunk/sw/void/Makefile (nonexistent) +++ layer2/trunk/sw/void/Makefile (revision 2) @@ -0,0 +1,23 @@ +include ../common/Makefile + +OBJ = flash.o stdlib.o stdio.o ui.o main.o + +standalone : boot.o $(OBJ) + $(LD) boot.o $(OBJ) -o void.axf + $(OPC) void.axf void.bin + $(MEM) void.bin $(BIN_DIR) + +void.bin : start.o $(OBJ) + $(LD2) start.o $(OBJ) -o void.axf + $(OPC) void.axf void.bin + +upload : void.bin + $(LOAD) void.bin + +details : void.axf $(OBJ) + -@$(DMP) void.axf > void.lst + -@$(DMP) ui.o > ui.lst + -@$(DMP) stdlib.o > stdlib.lst + -@$(DMP) stdio.o > stdio.lst + -@$(DMP) main.o > main.lst + -@$(DMP) flash.o > flash.lst \ No newline at end of file Index: layer2/trunk/sw/void =================================================================== --- layer2/trunk/sw/void (nonexistent) +++ layer2/trunk/sw/void (revision 2)

layer2/trunk/sw/void Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: layer2/trunk/sw/lib/stdlib.c =================================================================== --- layer2/trunk/sw/lib/stdlib.c (nonexistent) +++ layer2/trunk/sw/lib/stdlib.c (revision 2) @@ -0,0 +1,209 @@ +/****************************************************************************** + * Standard Library * + ****************************************************************************** + * Copyright (C)2011 Mathias H�rtnagl * + * * + * This program is free software: you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation, either version 3 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program. If not, see . * + ******************************************************************************/ +#include "stddef.h" +#include "stdlib.h" + +/****************************************************************************** + * Timer * + ******************************************************************************/ +/* Resets the counter. If you call reset before the counter has finished, it + returns the count progress. */ +uint pit_reset() { + return PIT_ADDRESS[0]; +} + +/* Set PIT limit and start counting. */ +void pit_run(uint cycles) { + PIT_ADDRESS[0] = cycles; +} + + +/****************************************************************************** + * RS-232 * + ******************************************************************************/ +/* Wait for one byte of data. Return n reception. */ +uchar rs232_receive() { + return RS232_ADDRESS[0]; +} + +/* Send one byte of data. */ +void rs232_transmit(uchar chr) { + RS232_ADDRESS[1] = chr; +} + + +/****************************************************************************** + * Memory Operations * + ******************************************************************************/ + +void memcpy(const void *src, void *dst, uint len) { + for(char *s = src, *d = dst; len-- > 0; *d++ = *s++); +} + +void memset(const void *ptr, int val, uint len) { + for(char *p = ptr; len-- > 0; *p++ = val); +} + +// +// int memcmp(const void *src, void *dst, uint len) { + // for(char *s = src, *d = dst; len > 0; len--) + // if(*s++ != *p++) return 1; + // return 0; +// } + + +/****************************************************************************** + * String Operations * + ******************************************************************************/ +/* Returns the length of a string */ +uint strlen(const uchar *str) { + uint c = 0; + for(uchar *s = str; *s++; c++); + return c; +} + +/* Copys a string at location src to location dst. */ +void strcpy(const uchar *src, uchar *dst) { + for(uchar *s = src, *d = dst; *d++ = *s++; ); +} + +/* Returns a pointer to the leftmost occurence of character chr in + string str or NULL, if not found. */ +uchar *strchr(const uchar *str, const uchar chr) { + for(uchar *s = str; *s; s++) + if(*s == chr) return *s; + return NULL; +} + + +/****************************************************************************** + * Number/String Conversion * + ******************************************************************************/ + /* Convert a string containing a decimal number into a number. */ +int atoi(const uchar *str) { + + int num = 0; + uchar sign; + uchar *s = str; + + for(; !( isdigit(*s) || (*s == '-') ) && (*s != NULL); s++); + sign = *s++; + + for(; isdigit(*s); s++) + num = x10(num) + (*s-'0'); + return (sign == '-') ? -num : num; +} + +/* Returns a binary representation of an integer . The buffer must be + at least 35 byte wide to hold the char sequence of the form '0bn...n\0'. */ +uchar* itob(int num, uchar *str) { + + uchar *s = str; + uint p = 0x80000000; + + *s++ = '0'; + *s++ = 'b'; + //while( !(num & p) ) p >>= 1; + while(p) { + *s++ = (num & p) ? '1' : '0'; + p >>= 1; + } + *s = '\0'; + return str; +} + +/* Returns a hexadecimal representation of an integer . The buffer + must be at least 11 byte wide to hold the char sequence of the form + '0xn...n\0'. */ +uchar* itox(int num, uchar *str) { + + uchar *s = str; + uchar n; + uint p = 0xf0000000; + + *s++ = '0'; + *s++ = 'x'; + //while( !(num & p) ) p >>= 1; + for(int i=28; i>=0; i-=4) { + n = ((uint) num & p) >> i; + if ( n <= 9 ) + *s++ = n + '0'; + else + *s++ = n - 10 + 'a'; + p >>= 4; + } + *s = '\0'; + return str; +} + + +/****************************************************************************** + * Nathematics * + ******************************************************************************/ +static uint x = 314159265; +/* Xorshift RNGs, George Marsaglia + http://www.jstatsoft.org/v08/i14/paper */ +uint rand() { + x ^= x << 13; + x ^= x >> 17; + x ^= x << 5; + return x; +} + +/* Radix-4 Booth Multiplication Algorithm */ +int mul(short a, short b) { + + int r = 0; + int ai = a << 1; + + for(int i=0; i++<16; ai>>=1, b<<=1) + switch (ai & 3) { + case 1: r += b; break; + case 2: r -= b; break; + } + return r; +} + + +short div(int a, int b) { + + char s = 0; + short m = 0; + + if(a < 0) { + s = 1; + a = -a; + } + if(b < 0) { + if(s == 1) + s = 0; + else + s = 1; + + b = -b; + } + if(b == 0) { + return 0; + } + while(a > b) { + m++; + a = a-b; + } + return m; +} Index: layer2/trunk/sw/lib/include/stddef.h =================================================================== --- layer2/trunk/sw/lib/include/stddef.h (nonexistent) +++ layer2/trunk/sw/lib/include/stddef.h (revision 2) @@ -0,0 +1,47 @@ +/****************************************************************************** + * Standard Definitions * + ****************************************************************************** + * Copyright (C)2011 Mathias H�rtnagl * + * * + * This program is free software: you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation, either version 3 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program. If not, see . * + ******************************************************************************/ +#ifndef _STDDEF_H +#define _STDDEF_H + +#ifndef NULL +#define NULL ( (void *) 0 ) +#endif + +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef FALSE +#define FALSE 0 +#endif + +#define isdigit(c) ( (c >= '0') && (c <= '9') ) +#define islower(c) ( (c >= 'a') && (c <= 'z') ) +#define isupper(c) ( (c >= 'A') && (c <= 'Z') ) +#define isalpha(c) ( islower(c) || isupper(c) ) +#define isalnum(c) ( isalpha(c) || isdigit(c) ) + +#define tolower(c) ( isupper(c) ? (c + 0x20) : c ) +#define toupper(c) ( islower(c) ? (c - 0x20) : c ) + +typedef unsigned char uchar; +typedef unsigned short ushort; +typedef unsigned long uint; + +#endif Index: layer2/trunk/sw/lib/include/interrupt.h =================================================================== --- layer2/trunk/sw/lib/include/interrupt.h (nonexistent) +++ layer2/trunk/sw/lib/include/interrupt.h (revision 2) @@ -0,0 +1,74 @@ +/****************************************************************************** + * Interrupts * + ****************************************************************************** + * Copyright (C)2011 Mathias H�rtnagl * + * * + * This program is free software: you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation, either version 3 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program. If not, see . * + ******************************************************************************/ +#include "stddef.h" + +#ifndef _INTERRUPT_H +#define _INTERRUPT_H + +/* Register a callback at line IRQ_X. */ +#define IRQ_PIT0 0 +#define IRQ_1 1 +#define IRQ_2 2 +#define IRQ_3 3 +#define IRQ_4 4 +#define IRQ_5 5 +#define IRQ_6 6 +#define IRQ_KEYB 7 + + +/* Enable or disable interrupt handling. */ + +#define INTR_EN 0x0001 /* Global interrupt enable. */ +#define INTR_PIT0 0x0100 /* Possible interrupt line masks. */ +#define INTR_1 0x0200 +#define INTR_2 0x0400 +#define INTR_3 0x0800 +#define INTR_4 0x1000 +#define INTR_5 0x2000 +#define INTR_6 0x4000 +#define INTR_KEYB 0x8000 + + +/* Type definition for the interrupt callback routines. A callback routine is + a function with no arguments and no return value. */ +typedef void (*callback)(); + + +/****************************************************************************** + * Status Register Operations * + ******************************************************************************/ +/* Set interrupts of mask. */ +extern void set_intr(ushort mask); + +/* Unset interrupts of mask. */ +extern void unset_intr(ushort mask); + + +/****************************************************************************** + * Callback Functions * + ******************************************************************************/ +/* Set a interrupt callback to NULL. If a interrupt callback points to NULL, + the interrupt will be ignored. */ +extern void register_callback(int irq_line, callback c); + +/* Call the interrupt routines one by one starting with the interrupt at INTR_0 + (or IRQ_0). Interrupts with NULL interrupt routines are ignored. */ +extern void free_callback(int irq_line); + +#endif \ No newline at end of file Index: layer2/trunk/sw/lib/include/flash.h =================================================================== --- layer2/trunk/sw/lib/include/flash.h (nonexistent) +++ layer2/trunk/sw/lib/include/flash.h (revision 2) @@ -0,0 +1,87 @@ +/****************************************************************************** + * Numonyx� 128 Mbit EMBEDDED FLASH MEMORY J3 Version D * + ****************************************************************************** + * REFERENCES * + * [1] Numonyx� Embedded Flash Memory(J3 v. D) Datasheet Revision 5 * + * * + ****************************************************************************** + * Copyright (C)2011 Mathias H�rtnagl * + * * + * This program is free software: you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation, either version 3 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program. If not, see . * + ******************************************************************************/ +#include "stddef.h" + +#ifndef _FLASH_H +#define _FLASH_H + +/* Flash memory location */ +#define FLASH_MEMORY ((volatile uchar *) 0x10000000) + +/* Flash status register flags. */ +#define FLASH_READY ((uint) 0x80) // Bit 8: Flash is ready. +#define FLASH_ERASE_ERROR ((uint) 0x20) // Bit 5: Error while errasing. +#define FLASH_PROGRAM_ERROR ((uint) 0x10) // Bit 4: Error while programming. +#define FLASH_CMD_ERROR (FLASH_ERASE_ERROR | FLASH_PROGRAM_ERROR) +#define FLASH_BLOCK_LOCKED ((uint) 0x02) // Bit 2: Block is locked. + +/* Status register commands */ +#define CMD_READ_SR ((uint) 0x70) // Read the status register. +#define CMD_CLEAR_SR ((uint) 0x50) // Clear error states. + +/* Memory operations */ +#define CMD_READ_ARRAY ((uint) 0xff) // Read 32bit of data. +#define CMD_BYTE_PROGRAM ((uint) 0x10) // Write one byte of data. +#define CMD_BLOCK_ERASE_SETUP ((uint) 0x20) // Setup erase command. +#define CMD_BLOCK_ERASE_CONFIRM ((uint) 0xd0) // Confirm errase command. + +/* Memory size */ +#define FLASH_BLOCK_SIZE 131072 // Size of one block in bytes. +#define FLASH_BLOCKS 128 // Number of blocks available. + +/* Read the status register. */ +extern uchar flash_read_status(); + +/* Clear the status register. + The Status Register (SR) contain status and error bits which are set by the + device. SR status bits are cleared by the device, however SR error bits are + cleared by issuing the Clear Status Register command. Resetting the device + also clears the Status Register. */ +extern void flash_clear_sr(); + +/* Write a byte of data to a specific device address. + Writing only changes '1' to '0'. If you overwrite data that would change '0' + to '1', erase the block beforhand. + Issuing the Read Array command to the device while it is actively programming + causes subsequent reads from the device to output invalid data. [1] */ +extern void flash_write(uint adr, uchar b); + +/* Read 32bit of data from a specific device address. + Issues a Read Array Command each time, although device stays in Array Read + mode until another command operation takes place. */ +extern uint flash_read(uint adr); + +/* Erase block. Point to an address within the block address space you want to + erase. 16 Mbytes or 8 Mword (128-Mbit), organized as 128-Kbyte erase blocks. + Erasing is performed on a block basis - an entire block is erased each time + an erase command sequence is issued. Once a block is fully erased, all + addressable locations within that block read as logical ones (FFFFh). [1] */ +extern void flash_block_erase(uint blk); + +/* Wait for the end of a operation and return the status register when ready. + Block erasure and writing data takes longer than a WB write operation. + So after each erase or write call flash_wait() or do something else + meanwhile. */ +extern uchar flash_wait(); + +#endif \ No newline at end of file Index: layer2/trunk/sw/lib/include/ui.h =================================================================== --- layer2/trunk/sw/lib/include/ui.h (nonexistent) +++ layer2/trunk/sw/lib/include/ui.h (revision 2) @@ -0,0 +1,181 @@ +/****************************************************************************** + * User Interface * + ****************************************************************************** + * Copyright (C)2011 Mathias H�rtnagl * + * * + * This program is free software: you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation, either version 3 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program. If not, see . * + ******************************************************************************/ +//#include "stddef.h" +#include "stdio.h" +#include "stdlib.h" + +#ifndef _UI_H +#define _UI_H + +/****************************************************************************** + * Box Drawing Constants * + ******************************************************************************/ +#define DOUBLE_UPPER_RIGHT 0xbb +#define DOUBLE_UPPER_LEFT 0xc9 +#define DOUBLE_LOWER_RIGHT 0xbc +#define DOUBLE_LOWER_LEFT 0xc8 +#define DOUBLE_HORIZONTAL 0xcd +#define DOUBLE_VERTICAL 0xba + +#define DOUBLE_DOUBLE_T_LEFT 0xcc +#define DOUBLE_DOUBLE_T_RIGHT 0xb9 + +#define VERTICAL_BLOCK_LEFT 0xdd +#define VERTICAL_BLOCK_RIGHT 0xde + + +/****************************************************************************** + * Various Character Constants * + ******************************************************************************/ +#define FULL_BOX 0xdb +#define SQUARE_BOX 0xfe + + + +/****************************************************************************** + * Window * + ******************************************************************************/ +/* Window component identification integers. */ +#define ID_MESSAGE 0x00 +#define ID_MENU 0x01 +#define ID_PROGRESS_BAR 0x02 + +/* Super class for all Window components. Each component struct contains this + three variables at the beginning. + The location struct 'pos' is the relative position of the item within a + Window. */ +typedef struct _WindowItem { + uchar id; + cursor pos; +} WindowItem; + +/* Represents a Contents Box. Origin is top lefft corner. */ +typedef struct _Box { + uchar x; + uchar y; + uchar w; // Width (+ 2 for borders). + uchar h; // Height (+ 2 for borders). +} Box; + +/* A Window is a Box with a double line border and a Window title. The fore- + ground and background colors can be specified. + The array itemv[] contains pointers to contents elements such as Messages, + Menus or ProgessBars. The integer itemc is the size of this array and must be + set manually by the programmer. */ +typedef struct _Window { + Box box; // Spatial dimensions. + color col; + uchar *title; // Window title. + uchar itemc; // Number of contetnts objects. + void *itemv[]; // Contents objects of the window. +} Window; + + +/****************************************************************************** + * Message * + ******************************************************************************/ +/* A simple text string. + For a Message, 'id' must be 'ID_MESSAGE'. */ +typedef struct _Message { + uchar id; + cursor pos; + uchar *msg; +} Message; + + +/****************************************************************************** + * Progress Bar * + ******************************************************************************/ +/* A simple progress bar. + For a Message, 'id' must be 'ID_PROGRESS_BAR'. */ +typedef struct _ProgressBar { + uchar id; + cursor pos; + // uint max; + uint val; +} ProgressBar; + + +/****************************************************************************** + * Menu * + ******************************************************************************/ +typedef struct _MenuItem { + uchar *name; +} MenuItem; + +/* A vertical menu, where 'itemv[]' is a array of MenuItems and 'itemc' its + size. The member 'index' inidactes the current selected MenuItem, where 0 + menas the first entry of the Menu. + For a Message, 'id' must be 'ID_MENU'. */ +typedef struct _Menu { + uchar id; + cursor pos; + uchar index; + uchar itemc; + MenuItem *itemv[]; +} Menu; + + + +/****************************************************************************** + * Windows * + ******************************************************************************/ +/* Draws a Window. */ +extern void drawWindow(Window *win); + +/* Prints an Error Message Window. The window is always 'wError' defined in this + file. The function set the Boxes width and x-axis according to the message + length. The message should not exceed 96 characters. */ +extern void drawErrorWindow(Message *errmsg); + + +/****************************************************************************** + * Message * + ******************************************************************************/ +/* Draws a simple text message. + Or override an existing Message, by setting the same relativ position of the + new Message 'msg' like the old message. */ +extern void drawMessage(Window *win, Message *msg); + + +/****************************************************************************** + * Progress Bar * + ******************************************************************************/ +/* Draws a Progress Bar element. + The value 'ProgressBar.val' must be between 0 and 63. The Window should be + therefor 68 wide. */ +extern void drawProgressBar(Window *win, ProgressBar *bar); + + +/****************************************************************************** + * Menus * + ******************************************************************************/ +/* Redraw the Menu by selecting the next element of the MenuItems and set + 'menu.index' acordingly. + If the current selected MenuItem is 'menu.itemv[menu.itemc-1]' the next + MenuItem will be 'menu.itemv[0]'. */ +extern void menuKeyDown(Window *win, Menu *menu); + +/* Redraw the Menu by selecting the previous element of the MenuItems and set + 'menu.index' acordingly. + If the current selected MenuItem is 'menu.itemv[0]' the next MenuItem will be + 'menu.itemv[menu.itemc-1]'. */ +extern void menuKeyUp(Window *win, Menu *menu); + +#endif \ No newline at end of file Index: layer2/trunk/sw/lib/include/stdlib.h =================================================================== --- layer2/trunk/sw/lib/include/stdlib.h (nonexistent) +++ layer2/trunk/sw/lib/include/stdlib.h (revision 2) @@ -0,0 +1,134 @@ +/****************************************************************************** + * Standard Library * + ****************************************************************************** + * Copyright (C)2011 Mathias H�rtnagl * + * * + * This program is free software: you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation, either version 3 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program. If not, see . * + ******************************************************************************/ +#include "stddef.h" + +#ifndef _STDLIB_H +#define _STDLIB_H + +/****************************************************************************** + * Timer * + ******************************************************************************/ + /* Porgammable Intervall Timer control loaction. */ +#define PIT_ADDRESS ((volatile uint *) 0xfffff000) + +/* Time periods in seconds and milliseconds respectivly. + NOTE: No hardware implementation of multiplication available! */ +#define sec(x) ( 50000000*x ) +#define msec(x) ( 50000*x ) + + +/****************************************************************************** + * RS-232 * + ******************************************************************************/ +/* RS-232 Receiver Address. */ +#define RS232_ADDRESS ((volatile uint *) 0xffff4000) + +/* Poll for valid received serial data. */ +#define RS232_RCV_POLL ((ushort) 0x8000) + + +/* 10 times x. */ +#define x10(x) ( (x << 3) + (x << 1) ) + + +/****************************************************************************** + * Timer * + ******************************************************************************/ +/* Resets the counter. If you call reset before the counter has finished, it + returns the count progress. */ +extern uint pit_reset(); + +/* Set the PIT limit and start counting. */ +extern void pit_run(uint cycles); + + +/****************************************************************************** + * RS-232 * + ******************************************************************************/ + /* Wait for one byte of data. Return n reception. */ +extern uchar rs232_receive(); + +/* Send one byte of data. */ +extern void rs232_transmit(uchar chr); + + +/****************************************************************************** + * Memory Operations * + ******************************************************************************/ + +extern void memcpy(const void *src, void *dst, uint len); + +extern void memset(const void *ptr, int val, uint len); + +extern int memcmp(const void *src, void *dst, uint len); + + +/****************************************************************************** + * String Operations * + ******************************************************************************/ +/* Returns the length of a string */ +extern uint strlen(const uchar *str); + +/* Copys a string at location src to location dst. */ +extern void strcpy(const uchar *src, uchar *dst); + +// KMP algo +// char *strstr(const char *str, const char *pat); + +/* Returns a pointer to the leftmost occurence of character chr in + string str or NULL, if not found. */ +extern uchar *strchr(const uchar *str, const uchar chr); + + +/****************************************************************************** + * Number/String Conversion * + ******************************************************************************/ +/* Convert a string containing a decimal number into a number. */ +extern int atoi(const uchar *str); + +//extern char* itoa(int num, char *str); + +/* Returns a binary representation of an integer . The buffer must be + at least 35 byte wide to hold the char sequence of the form '0bn...n\0'. */ +extern uchar* itob(int num, uchar *str); + +/* Returns a hexadecimal representation of an integer . The buffer + must be at least 11 byte wide to hold the char sequence of the form + '0xn...n\0'. */ +extern uchar* itox(int num, uchar *str); + + +/****************************************************************************** + * Nathematics * + ******************************************************************************/ +/* Xorshift RNGs, George Marsaglia + http://www.jstatsoft.org/v08/i14/paper */ +extern uint rand(); + +/* Radix-4 Booth Multiplication Algorithm */ +extern int mul(short a, short b); + +extern short div(int a, int b); + + +// extern void *malloc(uint size); +// extern void *calloc(uint num, uint size); +// extern void free(void *ptr); + +#endif \ No newline at end of file Index: layer2/trunk/sw/lib/include/stdio.h =================================================================== --- layer2/trunk/sw/lib/include/stdio.h (nonexistent) +++ layer2/trunk/sw/lib/include/stdio.h (revision 2) @@ -0,0 +1,171 @@ +/****************************************************************************** + * Standard Input/Output * + ****************************************************************************** + * Copyright (C)2011 Mathias H�rtnagl * + * * + * This program is free software: you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation, either version 3 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program. If not, see . * + ******************************************************************************/ +#include "stddef.h" + +#ifndef _STDIO_H +#define _STDIO_H + +/****************************************************************************** + * VGA * + ******************************************************************************/ +/* Pointer to VGA display memory. */ +#define VGA_MEMORY ( (volatile ushort *) 0xffff0000 ) + +/* Maximum values of the display's horizontal and vertical coordinates. */ +#define VGA_H 100 +#define VGA_V 37 + +/* Calculates the position of the cursor from its x and y coordinates that is + actually 10*y + x, substituting a multiplication with left shifts and + additions. */ +#define VGA_POS(x,y) ( (y << 6) + (y << 5) + (y << 2) + x ) + +/* Set up character information of type 0fff0bbb cccccccc where f and b are the + 3-bit foreground and background colors respectively. c denotes the 8-bit + character. + NOTE: Does not check for 3 bit color and 8 bit character limits. */ +#define VGA_CHR(f,b,c) ( (f << 12) | (b << 8) | c ) + +/* Available colors on an 8 color VGA display. */ +#define BLACK ((uchar) 0) +#define BLUE ((uchar) 1) +#define GREEN ((uchar) 2) +#define CYAN ((uchar) 3) +#define RED ((uchar) 4) +#define MAGENTA ((uchar) 5) +#define YELLOW ((uchar) 6) +#define WHITE ((uchar) 7) + + +/****************************************************************************** + * Keyboard * + ******************************************************************************/ +/* Pointer to Keyboard character memory. */ +#define KEYB_MEMORY ((volatile uint *) 0xffff3000) + +/* Input buffer size */ +#define INBUF_SIZE 128 + +/* Funtional key flags. */ +#define KEYB_SHIFT ((uchar) 0x80) +#define KEYB_CTRL ((uchar) 0x40) +#define KEYB_ALT ((uchar) 0x20) +#define KEYB_ALTGR ((uchar) 0x10) + +/* Special keys. */ +#define KEY_ENTER ((uchar) 0x0d) +#define KEY_BACKSP ((uchar) 0x08) +#define KEY_TAB ((uchar) 0x09) +#define KEY_ESC ((uchar) 0x1b) +#define KEY_DEL ((uchar) 0x7f) +#define KEY_SCROLL ((uchar) 0x80) +#define KEY_ARROWU ((uchar) 0xf0) +#define KEY_ARROWL ((uchar) 0xf1) +#define KEY_ARROWD ((uchar) 0xf2) +#define KEY_ARROWR ((uchar) 0xf3) + + +/****************************************************************************** + * Type Definitions * + ******************************************************************************/ +/* Color information structure. */ +typedef struct _color { + uchar fg; + uchar bg; +} color; + +/* Cursor position structure. */ +typedef struct _cursor { + uchar x; + uchar y; +} cursor; + +/* Key */ +typedef struct _key { + uchar flags; + uchar chr; +} key; + + +/****************************************************************************** + * Output Functions * + ******************************************************************************/ +/* Set text and background colors. */ +extern void setcolor(uchar fg, uchar bg); + +/* Set cursor at position x,y. */ +extern void gotoxy(uchar x, uchar y); + +/* Clears the entire display and resets the cursor. */ +extern void cls(); + +/* Scrolls down one line and clears the lowest line. The vertical cursor jumps + one line up, if not already on line one. If the cursor is on the first line + the horizontal cursor is reset to zero. */ +extern void scroll(); + +/* Outputs a single character onto the screen. */ +extern void putc(const uchar chr); + +/* Print a string without it's trailing '\0' onto the screen. */ +extern void puts(const uchar *str); + +/* Formatted string printig. The following parameters are available: + +----+--------------------------------------------------+ + | %s | print a string | + | %c | print a single character | + | %x | print a hexadecimal representation of an integer | + | %b | print a binary representation of an intger | + | %% | print a '%' | + +----+--------------------------------------------------+ + +----+----------------+ + | \n | line break | + | \r | carrage return | + | \t | tab space | + | \b | back space | + | \\ | print a '\' | + +----+----------------+ + + Despite the standard printf implementation, you can manipulate the background + and text colors: + +----+---------+----+---------+----+---------+----+---------+ + | $k | black | $b | blue | $g | green | $c | cyan | + | $r | red | $m | magenta | $y | yellow | $w | white | + +----+---------+----+---------+----+---------+----+---------+ + $$ - print a '$' + + The background colors can be specified the same way with a '#' as a format + indicator. Besides the format string, the function takes only one value + argunment. */ +extern void printf(const uchar *format, void *arg); + +#define printf0(f) printf(f, NULL); + +/****************************************************************************** + * Input Functions * + ******************************************************************************/ +/* Polls for a singe character. The keyboard controller only sends make codes + and postpones the read ack until a key is pressed. */ +extern key* getc(); + +/* Returns a string of at most INBUF_SIZE characters (without '\0'). The user + can confirm the input with the enter button. */ +extern uchar* gets(); + +#endif Index: layer2/trunk/sw/lib/include =================================================================== --- layer2/trunk/sw/lib/include (nonexistent) +++ layer2/trunk/sw/lib/include (revision 2)

layer2/trunk/sw/lib/include Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: layer2/trunk/sw/lib/stdio.c =================================================================== --- layer2/trunk/sw/lib/stdio.c (nonexistent) +++ layer2/trunk/sw/lib/stdio.c (revision 2) @@ -0,0 +1,270 @@ +/****************************************************************************** + * Standard Input/Output * + ****************************************************************************** + * Copyright (C)2011 Mathias H�rtnagl * + * * + * This program is free software: you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation, either version 3 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program. If not, see . * + ******************************************************************************/ +#include "stddef.h" +#include "stdio.h" +#include "stdlib.h" + +/* Current character and background color. */ +static color col = {WHITE, BLACK}; + +/* Current cursor position. */ +static cursor cur = {0, 0}; + +/* Current received key. */ +static key ckey; + +/* Input buffer. Holds INBUF_SIZE keyboard input characters. This variable is + located in the *.bss section and thus all zero. Important for the termination + character '\0' at position INBUF_SIZE. */ +static uchar inbuf[INBUF_SIZE+1]; + +/* Buffer for all number to string converting functions: itoa, itox, itob */ +static uchar bufc[35]; + +/****************************************************************************** + * Private Functions * + ******************************************************************************/ +/* Save cur.y--; */ +static void decy() { + if(cur.y > 0) cur.y--; +} + +/* Save cur.x--; */ +static void decx() { + if(cur.x > 0) { + cur.x--; + } + else { + decy(); + cur.x = VGA_H-1; + } + + // if(--cur.x < 0) { + // decy(); + // cur.x = VGA_H-1; + // } +} + +/* Save cur.y++; */ +static void incy() { + if(++cur.y >= VGA_V) scroll(); +} + +/* Save cur.x++; */ +static void incx() { + if(++cur.x >= VGA_H) { + incy(); + cur.x = 0; + } +} + +/****************************************************************************** + * Output Functions * + ******************************************************************************/ +/* Set text and background colors. */ +void setcolor(uchar fg, uchar bg) { + col.fg = fg; + col.bg = bg; +} + + /* Set cursor at position x,y. */ +void gotoxy(uchar x, uchar y) { + if(x < 100) cur.x = x; + if(y < 37) cur.y = y; +} + +/* Clears the entire display and resets the cursor. */ +void cls() { + for(int i=0; i < VGA_H * VGA_V; VGA_MEMORY[i++] = 0); // Clear display. + cur.x = 0; // Reset cursor. + cur.y = 0; +} + +/* Scrolls down one line and clears the lowest line. The vertical cursor jumps + one line up, if not already on line one. If the cursor is on the first line + the horizontal cursor is reset to zero. */ +void scroll() { + + // Shift up content one line. + for(int i=VGA_H; i < VGA_H * VGA_V; VGA_MEMORY[i-VGA_H] = VGA_MEMORY[i++]); + // Clean up last line. + for(int i=VGA_H * (VGA_V-1); i < VGA_H * VGA_V; VGA_MEMORY[i++] = 0); + // Reposition cursor. + if(cur.y == 0) cur.x = 0; // On top line carrage return. + decy(); +} + +/* Outputs a single character onto the screen. */ +void putc(const uchar chr) { + VGA_MEMORY[ VGA_POS(cur.x, cur.y) ] = VGA_CHR(col.fg, col.bg, chr); + incx(); +} + +/* Print a string without it's trailing '\0' onto the screen. */ +void puts(const uchar *str) { + for(char *s = str; *s; putc(*s++)); +} + +/* Formatted string printig. The following parameters are available: + +----+--------------------------------------------------+ + | %s | print a string | + | %c | print a single character | + | %x | print a hexadecimal representation of an integer | + | %b | print a binary representation of an intger | + | %% | print a '%' | + +----+--------------------------------------------------+ + +----+----------------+ + | \n | line break | + | \r | carrage return | + | \t | tab space | + | \b | back space | + | \\ | print a '\' | + +----+----------------+ + + Despite the standard printf implementation, you can manipulate the background + and text colors: + +----+---------+----+---------+----+---------+----+---------+ + | $k | black | $b | blue | $g | green | $c | cyan | + | $r | red | $m | magenta | $y | yellow | $w | white | + +----+---------+----+---------+----+---------+----+---------+ + $$ - print a '$' + + The background colors can be specified the same way with a '#' as a format + indicator. Besides the format string, the function takes only one value + argunment. */ +void printf(const uchar *format, void *arg) { + + char *f = format; + + for(char c; c = *f; f++) { + switch(c) { + + // Argument format flags. + case '%': + switch( (c = *++f) ) { + case '%': putc(c); break; + case 's': puts( (uchar *) arg ); break; + case 'c': putc( (uchar) arg ); break; + case 'd': /*puts( itoa((int *) arg, bufc) );*/ break; + case 'x': puts( itox((int *) arg, bufc) ); break; + case 'b': puts( itob((int *) arg, bufc) ); break; + } + break; + + // Foreground color state arguments. + case '$': + switch( (c = *++f) ) { + case '$': putc(c); break; + case 'k': col.fg = BLACK; break; + case 'b': col.fg = BLUE; break; + case 'g': col.fg = GREEN; break; + case 'c': col.fg = CYAN; break; + case 'r': col.fg = RED; break; + case 'm': col.fg = MAGENTA; break; + case 'y': col.fg = YELLOW; break; + case 'w': col.fg = WHITE; break; + } + break; + + // Background color state arguments. + case '#': + switch( (c = *++f) ) { + case '#': putc(c); break; + case 'k': col.bg = BLACK; break; + case 'b': col.bg = BLUE; break; + case 'g': col.bg = GREEN; break; + case 'c': col.bg = CYAN; break; + case 'r': col.bg = RED; break; + case 'm': col.bg = MAGENTA; break; + case 'y': col.bg = YELLOW; break; + case 'w': col.bg = WHITE; break; + } + break; + + // Text layout flags. + case '\\': + putc(c); + break; + case '\n': + incy(); + cur.x = 0; + break; + case '\r': + cur.x = 0; + break; + case '\t': + cur.x += 4; // ohohhhh + cur.x &= ~3; + break; + case '\b': + decx(); + break; + + default: + putc(c); + break; + } + } +} + +/****************************************************************************** + * Input Functions * + ******************************************************************************/ +/* Polls for a singe character. The keyboard controller only sends make codes + and postpones the read ack until a key is pressed. */ +key* getc() { + + // Blocks until keyboard input is ready. + uint k = KEYB_MEMORY[0]; + + ckey.flags = k >> 4; + ckey.chr = k; + return &ckey; +} + +/* Returns a string of at most INBUF_SIZE characters (without '\0'). The user + can confirm the input with the enter button. */ +uchar* gets() { + + int i=0; + uchar chr; + + while( ((chr = getc()->chr) != KEY_ENTER) && (i < INBUF_SIZE) ) { + + if(chr == KEY_BACKSP) { + // Go back no further than the start of the input. + if(i > 0) { + decx(); + // Undo last character. + VGA_MEMORY[ VGA_POS(cur.x, cur.y) ] = 0; + // Clear buffer. + inbuf[i--] = '\0'; + } + } + else { + putc(chr); + inbuf[i++] = chr; + } + } + + // We do not need to terrminate the string if we ran out of buffer size + // (i == INBUF_SZE), since it is by default zero and will not be altered. + inbuf[i] = '\0'; + return inbuf; +} Index: layer2/trunk/sw/lib/interrupt.c =================================================================== --- layer2/trunk/sw/lib/interrupt.c (nonexistent) +++ layer2/trunk/sw/lib/interrupt.c (revision 2) @@ -0,0 +1,78 @@ +/****************************************************************************** + * Interrupts * + ****************************************************************************** + * Copyright (C)2011 Mathias H�rtnagl * + * * + * This program is free software: you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation, either version 3 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program. If not, see . * + ******************************************************************************/ +#include "stddef.h" +#include "interrupt.h" + +/* Holds all interrupt callback routines. */ +static callback irq_callbacks[8]; + + +/****************************************************************************** + * Status Register Operations * + ******************************************************************************/ +/* Set interrupts of mask. */ +void set_intr(ushort mask) { + __asm__( + "mfc0 $k0, $12 \n\t" + "or $k0, $k0, $a0 \n\t" + "mtc0 $k0, $12 \n\t" + ); +} + +/* Unset interrupts of mask. */ +void unset_intr(ushort mask) { + __asm__( + "mfc0 $k0, $12 \n\t" + "nor $k1, $0, $a0 \n\t" // Negate mask. + "and $k0, $k0, $k1 \n\t" // Turn off those, that are set in mask. + "mtc0 $k0, $12 \n\t" + ); +} + + +/****************************************************************************** + * Callback Functions * + ******************************************************************************/ +/* Registers a callback routine at some interrupt line. The interrupt line + can be one out of IRQ_0 - IRQ_7. */ +void register_callback(int irq_line, callback c) { + irq_callbacks[irq_line] = c; +} + +/* Set a interrupt callback to NULL. If a interrupt callback points to NULL, + the interrupt will be ignored. */ +void free_callback(int irq_line) { + irq_callbacks[irq_line] = NULL; +} + +/* Call the interrupt routines one by one starting with the interrupt at INTR_0 + (or IRQ_0). Interrupts with NULL interrupt routines are ignored. */ +void intr_dispatch(uchar irq) { + + // Iterate through all interrupt lines. + for(int i=0; i<8; i++) { + + // Check if callback function is defined. + // Check if there exists a pending interrupt. + if( ((*irq_callbacks[i]) != NULL) && (irq & 0x1) ) { + (*irq_callbacks[i])(); + } + irq >>= 1; + } +} \ No newline at end of file Index: layer2/trunk/sw/lib/flash.c =================================================================== --- layer2/trunk/sw/lib/flash.c (nonexistent) +++ layer2/trunk/sw/lib/flash.c (revision 2) @@ -0,0 +1,66 @@ +/****************************************************************************** + * Numonyx� 128 Mbit EMBEDDED FLASH MEMORY J3 Version D * + ****************************************************************************** + * Copyright (C)2011 Mathias H�rtnagl * + * * + * This program is free software: you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation, either version 3 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program. If not, see . * + ******************************************************************************/ +#include "stddef.h" +#include "flash.h" + +/* Read the status register. */ +uchar flash_read_status() { + FLASH_MEMORY[0] = CMD_READ_SR; + return FLASH_MEMORY[0]; +} + +/* Clear the status register. */ +void flash_clear_sr() { + FLASH_MEMORY[0] = CMD_CLEAR_SR; +} + +/* Write a byte of data to a specific device address. + Writing only changes '1' to '0'. If you overwrite data that would change '0' + to '1', erase the block beforhand. */ +void flash_write(uint adr, uchar b) { + FLASH_MEMORY[adr] = CMD_BYTE_PROGRAM; + FLASH_MEMORY[adr] = b; +} + +/* Read 32bit of data from a specific device address. + Issues a Read Array Command each time, although device stays in Array Read + mode until another command operation takes place. */ +uint flash_read(uint adr) { + FLASH_MEMORY[0] = CMD_READ_ARRAY; + return ( (volatile uint *) FLASH_MEMORY )[adr]; +} + +/* Erase block. Point to an address within the block address space you want to + erase. 16 Mbytes, organized as 128-Kbyte erase blocks. */ +void flash_block_erase(uint blk) { + FLASH_MEMORY[blk] = CMD_BLOCK_ERASE_SETUP; + FLASH_MEMORY[blk] = CMD_BLOCK_ERASE_CONFIRM; +} + +/* Wait for the end of a operation and return the status register when ready. + Block erasure and writing data takes longer than a WB write operation. + So after each erase or write one should call flash_wait() or do something + else meanwhile. */ +uchar flash_wait() { + + uchar s; + + while( !( (s = flash_read_status()) & FLASH_READY) ); + return s; +} Index: layer2/trunk/sw/lib/ui.c =================================================================== --- layer2/trunk/sw/lib/ui.c (nonexistent) +++ layer2/trunk/sw/lib/ui.c (revision 2) @@ -0,0 +1,256 @@ +/****************************************************************************** + * User Interface * + ****************************************************************************** + * Copyright (C)2011 Mathias H�rtnagl * + * * + * This program is free software: you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation, either version 3 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program. If not, see . * + ******************************************************************************/ +#include "ui.h" + +/* A container for all Error Windows. + Used by 'void drawErrorWindow(Message *errmsg)'. */ +static Window wError = { + {25, 12, 50, 5}, + {RED, BLACK}, + "FATAL ERROR", + 1, + NULL +}; + +/****************************************************************************** + * Pattern Functions * + ******************************************************************************/ + +/* Print a single character multiple times. */ +void putnc(const uchar c, uchar n) { + for(uchar i=0; i++ < n; putc(c)); +} + +/* Print character l once. Print character c multiple times. Print r once. */ +void putlrnc(const uchar l, const uchar c, const uchar r, uchar n) { + putc(l); putnc(c, n-2); putc(r); +} + +/****************************************************************************** + * Windows * + ******************************************************************************/ +/* Draws a Window. */ +void drawWindow(Window *win) { + + uchar rb = win->box.x + win->box.w - 1; // Right border position. + uchar lb = win->box.y + win->box.h - 1; // Lower border position. + + setcolor(win->col.fg, win->col.bg); + + // Print upper horizontal border. + gotoxy(win->box.x, win->box.y); + putlrnc( + DOUBLE_UPPER_LEFT, + DOUBLE_HORIZONTAL, + DOUBLE_UPPER_RIGHT, + win->box.w + ); + + // Draw vertical left and right border. + gotoxy(win->box.x, win->box.y + 1); + putlrnc(DOUBLE_VERTICAL, ' ', DOUBLE_VERTICAL, win->box.w); + + // Draw the title. + gotoxy(win->box.x + 2, win->box.y + 1); puts(win->title); + + // Print divider between header and contents plane. + gotoxy(win->box.x, win->box.y + 2); + putlrnc( + DOUBLE_DOUBLE_T_LEFT, + DOUBLE_HORIZONTAL, + DOUBLE_DOUBLE_T_RIGHT, + win->box.w + ); + + // Print vertical left and right border. + for(uchar i = win->box.y + 3; i < lb; i++) { + gotoxy(win->box.x, i); + putc(DOUBLE_VERTICAL); + gotoxy(rb, i); + putc(DOUBLE_VERTICAL); + } + + // Print lower horizontal border. + gotoxy(win->box.x, lb); + putlrnc( + DOUBLE_LOWER_LEFT, + DOUBLE_HORIZONTAL, + DOUBLE_LOWER_RIGHT, + win->box.w + ); + + // Draw contents components. + drawComponents(win); + + setcolor(WHITE, BLACK); +} + +/* Draw all the contents of the Window 'win'. */ +void drawComponents(Window *win) { + + WindowItem *item; + + for(uchar i = 0; i < win->itemc; i++) { + + item = (WindowItem *) win->itemv[i]; + + switch(item->id) { + case ID_MESSAGE: + drawMessage(win, (Message *) item); + break; + case ID_MENU: + drawMenu(win, (Menu *) item); + break; + case ID_PROGRESS_BAR: + drawProgressBar(win, (ProgressBar *) item); + break; + default: + break; + } + } +} + +/* Prints an Error Message Window. The window is always 'wError' defined in this + file. The function set the Boxes width and x-axis according to the message + length. The message should not exceed 96 characters. */ +void drawErrorWindow(Message *errmsg) { + + uchar w = strlen(errmsg->msg) + 4; + + // Clean screen. we only want to display the errror message. + cls(); + + // Adjust the Error Box size according to message size. + wError.box.w = w; + wError.box.x = (100 - w) / 2; + wError.itemv[0] = errmsg; + + drawWindow(&wError); +} + + +/****************************************************************************** + * Message * + ******************************************************************************/ +/* Draws a simple text message. + Or override an existing Message, by setting the same relativ position of the + new Message 'msg' like the old message. */ +void drawMessage(Window *win, Message *msg) { + + uint len = strlen(msg->msg); + uint width = win->box.w - len - msg->pos.x; + + gotoxy(win->box.x + msg->pos.x + 1, win->box.y + msg->pos.y + 3); + putc(' '); puts(msg->msg); putnc(' ', width - 3); +} + + +/****************************************************************************** + * Progress Bar * + ******************************************************************************/ +/* Draws a Progress Bar element. + The value 'ProgressBar.val' must be between 0 and 63. The Window should be + therefor 68 wide. */ +void drawProgressBar(Window *win, ProgressBar *bar) { + + //uint width = win->box.w - bar->pos.x - 3; + //uint factor = div( mul(bar->val, width), bar->max ); + + gotoxy(win->box.x + bar->pos.x + 2, win->box.y + bar->pos.y + 3); + + // for(uint i=0; i < width; i++) { + // if(i <= factor) + // putc(SQUARE_BOX); + // else + // putc(' '); + // } + + putnc(SQUARE_BOX, bar->val); + putnc(' ', 64 - bar->val); +} + + +/****************************************************************************** + * Menus * + ******************************************************************************/ +/* Redraw the Menu by selecting the next element of the MenuItems and set + 'menu.index' acordingly. + If the current selected MenuItem is 'menu.itemv[menu.itemc-1]' the next + MenuItem will be 'menu.itemv[0]'. */ +void menuKeyDown(Window *win, Menu *menu) { + + if(menu->index == menu->itemc - 1) + menu->index = 0; + else + menu->index++; + + drawMenu(win, menu); +} + +/* Redraw the Menu by selecting the previous element of the MenuItems and set + 'menu.index' acordingly. + If the current selected MenuItem is 'menu.itemv[0]' the next MenuItem will be + 'menu.itemv[menu.itemc-1]'. */ +void menuKeyUp(Window *win, Menu *menu) { + + if(menu->index == 0) + menu->index = menu->itemc - 1; + else + menu->index--; + + drawMenu(win, menu); +} + +/* Draws a vertical menu. */ +void drawMenu(Window *win, Menu *menu) { + + MenuItem *item; + cursor pos; + uint len; + uint width; + + pos.x = win->box.x + menu->pos.x + 1; + pos.y = win->box.y + menu->pos.y + 3; + width = win->box.w - menu->pos.x; + + for(uchar idx = 0; idx < menu->itemc; idx++) { + + gotoxy(pos.x, pos.y + idx); + + item = menu->itemv[idx]; + len = strlen(item->name); + + if(menu->index == idx) { + + // Invert color scheme for selected items. + setcolor(win->col.bg, win->col.fg); + + putc(VERTICAL_BLOCK_LEFT); + puts(item->name); putnc(' ', width - len - 4); + putc(VERTICAL_BLOCK_RIGHT); + + // Reset color options to default. + setcolor(win->col.fg, win->col.bg); + } + else { + putc(' '); puts(item->name); putnc(' ', width - len - 3); + } + } +} + Index: layer2/trunk/sw/lib =================================================================== --- layer2/trunk/sw/lib (nonexistent) +++ layer2/trunk/sw/lib (revision 2)

layer2/trunk/sw/lib Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: layer2/trunk/sw/tennmino/view.h =================================================================== --- layer2/trunk/sw/tennmino/view.h (nonexistent) +++ layer2/trunk/sw/tennmino/view.h (revision 2) @@ -0,0 +1,37 @@ +/****************************************************************************** + * Tennmino Version 0.1 * + ****************************************************************************** + * Copyright (C)2011 Mathias H�rtnagl * + * * + * This program is free software: you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation, either version 3 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program. If not, see . * + ******************************************************************************/ +#include "stdio.h" + +#ifndef _VIEW_H +#define _VIEW_H + +#define BOARD_LEFT 30 +#define BOARD_RIGHT 64 +#define BOARD_HEIGHT 36 + +#define BORDER_FULL 0xdb +#define BORDER_DOTTED 0xb1 + +/* Draw the board. */ +extern void drawBoard(); + +/* Game Over screen. */ +extern void drawGameOver(); + +#endif Index: layer2/trunk/sw/tennmino/tiles.c =================================================================== --- layer2/trunk/sw/tennmino/tiles.c (nonexistent) +++ layer2/trunk/sw/tennmino/tiles.c (revision 2) @@ -0,0 +1,221 @@ +/****************************************************************************** + * Tennmino Version 0.1 * + ****************************************************************************** + * Copyright (C)2011 Mathias H�rtnagl * + * * + * This program is free software: you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation, either version 3 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program. If not, see . * + ******************************************************************************/ +#include "tiles.h" + +/* The current tile. */ +static Tile tile; + +/* The state of the move. Can be either + MOVE_CONTINUE when everything is okay to move or + MOVE_BLOCKED when the tile can not move down anymore. */ +static uchar moveState = MOVE_CONTINUE; + +/* The sequences of each tile + A tile is represented by a 16bit unsigned number. Every 4bit represent a + line of the 4x4 tile starting on the top. */ +static ushort seq[7][4] = { + {0x4444, 0x00f0, 0x4444, 0x00f0}, /* I */ + {0x0e20, 0x6440, 0x8e00, 0x44c0}, /* J */ + {0x02e0, 0x6220, 0xe800, 0x88c0}, /* L */ + {0x0660, 0x0660, 0x0660, 0x0660}, /* O */ + {0x0e40, 0x4c40, 0x4e00, 0x4640}, /* T */ + {0x06c0, 0x4620, 0x06c0, 0x4620}, /* S */ + {0x0c60, 0x2640, 0x0c60, 0x2640} /* Z */ +}; + + +/****************************************************************************** + * Reading VGA RAM * + ******************************************************************************/ +/* Read contetnts of the VGA RAM at location (x,y). */ +uchar getVGAContents(uchar x, uchar y) { + return (VGA_MEMORY[ VGA_POS(x, y) ] & 0xff); +} + +/* Read a 4x4 area of the VGA RAM starting at loaction (x,y). */ +uint getVGAMask(uchar x, uchar y) { + + uint mask = 0; + + for(uchar i=0; i < 4; i++) { + for(uchar j=0; j < 8; j+=2) { + if( getVGAContents(x + j, y + i) == CHR_FULL ) + mask |= 1; + + mask <<= 1; + } + } + return mask >> 1; // Shifting happens once too often. +} + + +/****************************************************************************** + * Tile Placement * + ******************************************************************************/ +/* Initialize a tile at te top of the board. */ +void initTile(uchar type) { + tile.type = type; + tile.tile = seq[type][0]; + tile.ridx = 0; + tile.pos.x = VGA_H/2 - 2; // Center tile horizontally. + tile.pos.y = 0; + drawTile(); +} + +/* Print the current tile either visible or invisible to erase it from the + screen. */ +void printTile(uchar chr) { + + ushort pos; + ushort mask = 0x8000; + + for(uchar i=0; i < 4; i++) { + for(uchar j=0; j < 8; j+=2) { + if(tile.tile & mask) { + pos = VGA_POS(tile.pos.x + j, tile.pos.y + i); + VGA_MEMORY[pos] = VGA_CHR(tile.type + 1, BLACK, chr); + VGA_MEMORY[++pos] = VGA_CHR(tile.type + 1, BLACK, chr); + } + mask >>= 1; + } + } +} + + +/****************************************************************************** + * Tile Movement * + ******************************************************************************/ +/* Rotate the tile if its new rotation does not interfere with already present + tiles or the game board. */ +void rotate() { + + ushort mask; + uchar ridx; + ushort rtile; + + eraseTile(); + + mask = (ushort) getVGAMask(tile.pos.x, tile.pos.y); + ridx = ++tile.ridx & 3; // Mod 4 counter. + rtile = seq[tile.type][ridx]; + + // See if the rotated tile and the area share occupied blocks. + if(mask & rtile) { + // If true we can not accept the rotation of the tile. Instead + // draw the original tile once more. + moveState = MOVE_BLOCKED; + } + else { + tile.ridx = ridx; + tile.tile = rtile; + moveState = MOVE_CONTINUE; + } + + drawTile(); +} + +/* Move in any direction and check if the tile does not interfere with already + present tiles or the borders of the game board. */ +void move(char x, char y) { + + ushort mask; + + eraseTile(); + + // Grab the area for the tiles next position. The old tile is erased and + // won't interfere with the match. + mask = (ushort) getVGAMask(tile.pos.x + x, tile.pos.y + y); + + // See if the tile and the area share occupied blocks. + if(mask & tile.tile) { + // If true we can not continue with the movement of the tile. Instead + // draw the tile at the old position once more and change moveState. + moveState = MOVE_BLOCKED; + } + else { + tile.pos.x += x; + tile.pos.y += y; + moveState = MOVE_CONTINUE; + } + + drawTile(); +} + + +/****************************************************************************** + * Game State * + ******************************************************************************/ +/* Return the current game state. Can be either + GAME_CONTINUE if the game can continue without further processing. + GAME_NEW_TILE if the current tile is stuck and a new tile needs to be + initialized. + GAME_OVER if the current tile can not move down from the beginning. + */ +uchar getGameState() { + + switch(moveState) { + case MOVE_BLOCKED: + return (tile.pos.y == 0) ? GAME_OVER : GAME_NEW_TILE; + + default: + return GAME_CONTINUE; + break; + } +} + + +/****************************************************************************** + * Deletion of Lines * + ******************************************************************************/ +/* Deletes one complete row and scrolls down the remaining board. */ +uchar deleteCompletedRow(uchar x, uchar y, uchar w) { + + ushort pos = VGA_POS(x, y); + + for(uchar i=0; i0; j--) + for(uchar i=0; i> (i*4)) ) + cnt += deleteCompletedRow(x, tile.pos.y + i, w); + } + return (cnt << 7); +} Index: layer2/trunk/sw/tennmino/main.c =================================================================== --- layer2/trunk/sw/tennmino/main.c (nonexistent) +++ layer2/trunk/sw/tennmino/main.c (revision 2) @@ -0,0 +1,129 @@ +/****************************************************************************** + * Tennmino Version 0.1 * + ****************************************************************************** + * Copyright (C)2011 Mathias H�rtnagl * + * * + * This program is free software: you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation, either version 3 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program. If not, see . * + ******************************************************************************/ +#include "tiles.h" +#include "view.h" +#include "interrupt.h" +#include "stdlib.h" + +static uint interval; // Timing interval. +static uint score; // Game score. + +/* Print the score. */ +void printScore() { + gotoxy(80, 6); + printf("%x", score); +} + +/* Randomly select the next tile. */ +uchar nextTile() { + + uchar t; + + while( (t = rand() & 0x7) == 7 ); + return t; +} + +/* With each move down, check if the tile is stuck. If so, either add a new tile + or if the tile could not be moved any from initial position quit the game. */ +void checkAndMoveDown() { + + moveDown(); + + switch( getGameState() ) { + case GAME_NEW_TILE: + score += deleteCompletedRows(BOARD_LEFT + 2, BOARD_RIGHT - BOARD_LEFT); + printScore(); + initTile( nextTile() ); + break; + + case GAME_OVER: + unset_intr(INTR_KEYB | INTR_PIT0 | INTR_EN); + drawGameOver(); + break; + + default: + break; + } +} + +/* Callback function for the timer. On every tick reset the clock and move + the tile one position downwards. */ +void clock() { + pit_reset(); + checkAndMoveDown(); + pit_run(interval - score); +} + +/* Callback function for the keyboard. The user can move a tile left, right, + down or rotate it counter-clockwise */ +void keyboard() { + switch(getc()->chr) { + case KEY_ARROWU: + rotate(); + break; + + case KEY_ARROWL: + moveLeft(); + break; + + case KEY_ARROWR: + moveRight(); + break; + + case KEY_ARROWD: + checkAndMoveDown(); + break; + + case KEY_ESC: + unset_intr(INTR_KEYB | INTR_PIT0 | INTR_EN); + boot(); + + default: + break; + } +} + +int main() { + + drawBoard(); + + interval = 50000 * 800; // Movement period. + score = 0; // Game score reset. + gotoxy(80, 5); + printf0("My Score:") + printScore(); + + // Enable timer and global interrupt. + set_intr(INTR_KEYB | INTR_PIT0 | INTR_EN); + + // Set clock() as a callback for the PIT (IRQ_PIT0). + register_callback(IRQ_PIT0, &clock); + + // Set keyboard() as a callback for the Keyboard (IRQ_KEYB). + register_callback(IRQ_KEYB, &keyboard); + + // Just to be sure the PIT is ready. + pit_reset(); + pit_run(interval); + + // Display the first tile. + initTile( nextTile() ); + + while(TRUE); +} \ No newline at end of file Index: layer2/trunk/sw/tennmino/tiles.h =================================================================== --- layer2/trunk/sw/tennmino/tiles.h (nonexistent) +++ layer2/trunk/sw/tennmino/tiles.h (revision 2) @@ -0,0 +1,106 @@ +/****************************************************************************** + * Tennmino Version 0.1 * + ****************************************************************************** + * Copyright (C)2011 Mathias H�rtnagl * + * * + * This program is free software: you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation, either version 3 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program. If not, see . * + ******************************************************************************/ +#include "stdio.h" + +#ifndef _TILES_H +#define _TILES_H + +// #define TILE_I 0x00 +// #define TILE_J 0x01 +// #define TILE_L 0x02 +// #define TILE_O 0x03 +// #define TILE_T 0x04 +// #define TILE_S 0x05 +// #define TILE_Z 0x06 + +#define CHR_FULL 0xdb +#define CHR_EMPTY 0xff + +#define MOVE_CONTINUE 0 // Tile can move down. +#define MOVE_BLOCKED 1 // Tile is stuck. + +#define GAME_CONTINUE 2 // Continue execution of game. +#define GAME_NEW_TILE 3 // Current tile can not move down. Get a new one. +#define GAME_OVER 4 // Current tile can not move. Game over. + + +typedef struct _Tile { + uchar type; + ushort tile; + uchar ridx; + cursor pos; +} Tile; + + +/****************************************************************************** + * Tile Placement * + ******************************************************************************/ +/* Initialize a tile at te top of the board. */ +extern void initTile(uchar type); + +/* Draw the current tile. */ +#define drawTile() printTile(CHR_FULL); + +/* Erase the curent tile from the display. */ +#define eraseTile() printTile(CHR_EMPTY); + + +/****************************************************************************** + * Tile Movement * + ******************************************************************************/ +/* Rotate the tile if its new rotation does not interfere with already present + tiles or the game board. */ +extern void rotate(); + +/* Move current tile left. */ +#define moveLeft() move(-2, 0) + +/* Move current tile right. */ +#define moveRight() move(+2, 0) + +/* Move current tile down. */ +#define moveDown() move(0, +1) + + +/****************************************************************************** + * Game State * + ******************************************************************************/ +/* Return the current game state. Can be either + GAME_CONTINUE if the game can continue without further processing. + GAME_NEW_TILE if the current tile is stuck and a new tile needs to be + initialized. + GAME_OVER if the current tile can not move down from the beginning. + */ +extern uchar getGameState(); + + +/****************************************************************************** + * Deletion of Lines * + ******************************************************************************/ +/* Deletes up to four complete rows and scrolls down acordingly. Returns the + number of deleted rows. For x deleted lines return + 0 ... 0 Points + 1 ... 128 points + 2 ... 256 points + 3 ... 512 points + 4 ... 1024 points + */ +extern uint deleteCompletedRows(uchar x, uchar w); + +#endif Index: layer2/trunk/sw/tennmino/view.c =================================================================== --- layer2/trunk/sw/tennmino/view.c (nonexistent) +++ layer2/trunk/sw/tennmino/view.c (revision 2) @@ -0,0 +1,59 @@ +/****************************************************************************** + * Tennmino Version 0.1 * + ****************************************************************************** + * Copyright (C)2011 Mathias H�rtnagl * + * * + * This program is free software: you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation, either version 3 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program. If not, see . * + ******************************************************************************/ +#include "view.h" + +/* Draw a vertical border line. The line width is 2 characters. */ +void drawVerticalBorder(uchar x, uchar y, uchar h, uchar chr) { + for(uchar i=y; i < h; i++) { + gotoxy(x, i); + putc(chr); putc(chr); + } +} + +/* Draw a horizontal border line. */ +void drawHorizontalBorder(uchar x, uchar y, uchar w, uchar chr) { + gotoxy(x, y); + for(uchar i=0; i < w + 2; i++) { + putc(chr); + } +} + +/* Draw the board. */ +void drawBoard() { + + cls(); + + drawVerticalBorder(BOARD_LEFT, 0, BOARD_HEIGHT, BORDER_FULL); + drawVerticalBorder(BOARD_RIGHT, 0, BOARD_HEIGHT, BORDER_FULL); + drawHorizontalBorder( + BOARD_LEFT, + BOARD_HEIGHT, + BOARD_RIGHT - BOARD_LEFT, + BORDER_FULL + ); +} + +/* Game Over screen. */ +void drawGameOver() { + + cls(); + + gotoxy(45, 15); + printf0("GAME OVER!"); +} \ No newline at end of file Index: layer2/trunk/sw/tennmino/Makefile =================================================================== --- layer2/trunk/sw/tennmino/Makefile (nonexistent) +++ layer2/trunk/sw/tennmino/Makefile (revision 2) @@ -0,0 +1,21 @@ +include ../common/Makefile + +# Redefine the assembler, with interrupts enabled. +# Found no better solution yet. +AS = $(TOOL_DIR)as.exe --defsym _INTERRUPT=1 + +OBJ = stdlib.o stdio.o view.o tiles.o interrupt.o main.o + +ten.bin : start.o $(OBJ) + $(LD2) start.o $(OBJ) -o ten.axf + $(OPC) ten.axf ten.bin + +upload : ten.bin + $(LOAD) ten.bin + +details : ten.axf $(OBJ) + -@$(DMP) ten.axf > ten.lst + -@$(DMP) stdlib.o > stdlib.lst + -@$(DMP) stdio.o > stdio.lst + -@$(DMP) tiles.o > tiles.lst + -@$(DMP) main.o > main.lst \ No newline at end of file Index: layer2/trunk/sw/tennmino/ten.bin =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: layer2/trunk/sw/tennmino/ten.bin =================================================================== --- layer2/trunk/sw/tennmino/ten.bin (nonexistent) +++ layer2/trunk/sw/tennmino/ten.bin (revision 2)

layer2/trunk/sw/tennmino/ten.bin Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: layer2/trunk/sw/tennmino =================================================================== --- layer2/trunk/sw/tennmino (nonexistent) +++ layer2/trunk/sw/tennmino (revision 2)

layer2/trunk/sw/tennmino Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: layer2/trunk/sw/bin/data.vhd =================================================================== --- layer2/trunk/sw/bin/data.vhd (nonexistent) +++ layer2/trunk/sw/bin/data.vhd (revision 2) @@ -0,0 +1,777 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.imem.all; + +package data is + + constant data : mem_block_t := ( + 0 => ( + x"01", x"70", x"00", x"F8", x"00", x"60", x"00", x"10", x"00", x"04", + x"2A", x"FC", x"00", x"24", x"24", x"24", x"24", x"24", x"24", x"24", + x"24", x"24", x"24", x"24", x"24", x"24", x"24", x"24", x"24", x"24", + x"24", x"24", x"24", x"24", x"24", x"24", x"24", x"24", x"24", x"24", + x"24", x"24", x"B3", x"00", x"00", x"2C", x"00", x"00", x"00", x"08", + x"00", x"00", x"70", x"00", x"00", x"08", x"FF", x"50", x"00", x"00", + x"08", x"00", x"00", x"21", x"FF", x"10", x"00", x"00", x"08", x"00", + x"00", x"80", x"FF", x"00", x"21", x"00", x"08", x"00", x"00", x"21", + x"20", x"00", x"D0", x"00", x"08", x"00", x"00", x"70", x"00", x"00", + x"00", x"FF", x"00", x"03", x"F9", x"00", x"08", x"00", x"00", x"08", + x"00", x"00", x"08", x"00", x"FF", x"00", x"08", x"FF", x"FF", x"FF", + x"04", x"08", x"00", x"07", x"00", x"00", x"FF", x"00", x"01", x"FB", + x"01", x"08", x"00", x"06", x"00", x"03", x"FF", x"00", x"FD", x"01", + x"08", x"00", x"00", x"00", x"0A", x"00", x"21", x"01", x"21", x"00", + x"00", x"FC", x"01", x"08", x"FF", x"08", x"21", x"00", x"01", x"00", + x"FC", x"01", x"08", x"00", x"00", x"00", x"0D", x"FF", x"09", x"01", + x"A4", x"00", x"09", x"00", x"00", x"00", x"FB", x"01", x"08", x"00", + x"08", x"21", x"08", x"00", x"00", x"00", x"D0", x"FF", x"0A", x"13", + x"2D", x"11", x"00", x"0F", x"2D", x"C0", x"01", x"0B", x"00", x"09", + x"00", x"01", x"00", x"00", x"D0", x"FF", x"0A", x"F5", x"00", x"01", + x"00", x"D0", x"FF", x"0A", x"13", x"02", x"21", x"00", x"C0", x"40", + x"21", x"21", x"D0", x"FF", x"0A", x"F7", x"01", x"2D", x"03", x"00", + x"08", x"00", x"08", x"23", x"D9", x"21", x"30", x"00", x"62", x"01", + x"21", x"02", x"22", x"00", x"31", x"24", x"01", x"23", x"00", x"01", + x"FA", x"42", x"08", x"00", x"30", x"00", x"78", x"01", x"21", x"03", + x"1C", x"00", x"03", x"FC", x"FC", x"FF", x"02", x"0D", x"01", x"24", + x"06", x"FF", x"0A", x"30", x"F5", x"57", x"FC", x"FF", x"02", x"F5", + x"01", x"08", x"0A", x"10", x"00", x"40", x"26", x"42", x"26", x"40", + x"26", x"08", x"10", x"00", x"03", x"00", x"03", x"40", x"10", x"21", + x"01", x"2E", x"02", x"02", x"00", x"23", x"40", x"00", x"FF", x"43", + x"0B", x"03", x"03", x"F5", x"00", x"21", x"40", x"00", x"FF", x"43", + x"F7", x"03", x"08", x"00", x"05", x"00", x"04", x"21", x"08", x"00", + x"23", x"0D", x"00", x"2A", x"0C", x"23", x"21", x"21", x"01", x"00", + x"2A", x"FB", x"03", x"08", x"00", x"43", x"23", x"08", x"21", x"98", + x"00", x"09", x"FF", x"99", x"00", x"02", x"FF", x"99", x"63", x"08", + x"98", x"08", x"98", x"14", x"08", x"15", x"FF", x"64", x"02", x"FF", + x"98", x"25", x"02", x"00", x"99", x"08", x"00", x"FF", x"E8", x"00", + x"02", x"FD", x"00", x"98", x"08", x"99", x"FF", x"C8", x"E8", x"00", + x"FF", x"FF", x"38", x"02", x"FA", x"00", x"20", x"E8", x"00", x"02", + x"FD", x"00", x"99", x"00", x"03", x"FF", x"08", x"98", x"08", x"99", + x"99", x"00", x"01", x"FF", x"25", x"03", x"99", x"08", x"00", x"78", + x"00", x"99", x"15", x"80", x"40", x"14", x"98", x"21", x"80", x"21", + x"00", x"00", x"FF", x"21", x"25", x"01", x"FF", x"25", x"40", x"FF", + x"E8", x"21", x"FF", x"64", x"14", x"98", x"00", x"04", x"00", x"90", + x"00", x"98", x"14", x"00", x"08", x"18", x"E8", x"14", x"10", x"00", + x"00", x"08", x"01", x"FF", x"9B", x"01", x"FF", x"00", x"FB", x"FF", + x"14", x"10", x"08", x"18", x"D8", x"14", x"24", x"20", x"1C", x"18", + x"10", x"00", x"00", x"38", x"21", x"00", x"00", x"21", x"58", x"00", + x"EE", x"FC", x"61", x"0A", x"5B", x"08", x"55", x"00", x"9B", x"FF", + x"01", x"00", x"25", x"01", x"0D", x"4A", x"0E", x"F0", x"09", x"24", + x"38", x"25", x"11", x"25", x"23", x"EE", x"00", x"01", x"00", x"DD", + x"FF", x"57", x"E9", x"01", x"80", x"21", x"00", x"00", x"08", x"00", + x"11", x"5C", x"DD", x"00", x"9B", x"5C", x"01", x"00", x"DD", x"01", + x"24", x"20", x"1C", x"18", x"14", x"10", x"08", x"28", x"01", x"63", + x"76", x"01", x"64", x"2A", x"00", x"73", x"68", x"78", x"C5", x"00", + x"21", x"F4", x"60", x"BE", x"21", x"EA", x"00", x"01", x"00", x"DC", + x"FF", x"56", x"B7", x"01", x"80", x"21", x"00", x"00", x"08", x"00", + x"EA", x"98", x"53", x"00", x"EA", x"00", x"90", x"00", x"EA", x"98", + x"98", x"FC", x"04", x"24", x"EA", x"98", x"44", x"62", x"9D", x"00", + x"21", x"E2", x"60", x"BE", x"21", x"EA", x"00", x"9B", x"24", x"EA", + x"00", x"01", x"EA", x"14", x"03", x"EA", x"14", x"02", x"EA", x"14", + x"EA", x"14", x"05", x"EA", x"14", x"04", x"EA", x"14", x"07", x"EA", + x"14", x"06", x"EA", x"14", x"9B", x"23", x"EA", x"00", x"01", x"EA", + x"15", x"03", x"EA", x"15", x"02", x"EA", x"15", x"EA", x"15", x"05", + x"EA", x"15", x"04", x"EA", x"15", x"07", x"EA", x"15", x"06", x"EA", + x"15", x"BE", x"21", x"EA", x"00", x"9B", x"25", x"EA", x"00", x"9B", + x"FF", x"EA", x"00", x"FF", x"00", x"9C", x"02", x"9C", x"08", x"9D", + x"D0", x"28", x"00", x"24", x"20", x"1C", x"18", x"2C", x"14", x"21", + x"84", x"FF", x"0D", x"08", x"00", x"80", x"FF", x"02", x"21", x"9C", + x"1F", x"9D", x"1D", x"00", x"27", x"00", x"F3", x"00", x"53", x"00", + x"99", x"98", x"80", x"40", x"21", x"80", x"21", x"21", x"40", x"21", + x"21", x"00", x"00", x"00", x"FF", x"FF", x"02", x"80", x"21", x"9C", + x"E3", x"9D", x"21", x"00", x"2C", x"21", x"24", x"28", x"20", x"1C", + x"18", x"14", x"08", x"30", x"9B", x"00", x"21", x"00", x"AC", x"01", + x"E0", x"14", x"FF", x"18", x"1C", x"10", x"09", x"FF", x"21", x"21", + x"9B", x"01", x"FF", x"2B", x"FB", x"21", x"1C", x"18", x"14", x"10", + x"08", x"20", x"C0", x"28", x"20", x"3C", x"38", x"34", x"30", x"2C", + x"24", x"1C", x"01", x"02", x"01", x"21", x"02", x"04", x"03", x"21", + x"21", x"00", x"FF", x"40", x"23", x"21", x"01", x"FD", x"FF", x"21", + x"27", x"FC", x"9B", x"10", x"00", x"BE", x"01", x"10", x"20", x"23", + x"E4", x"FF", x"04", x"FF", x"2B", x"2A", x"00", x"21", x"FF", x"64", + x"21", x"02", x"80", x"21", x"00", x"00", x"00", x"84", x"00", x"03", + x"00", x"E2", x"20", x"04", x"05", x"61", x"10", x"9B", x"DD", x"00", + x"BE", x"01", x"10", x"20", x"23", x"E4", x"FF", x"9B", x"DE", x"04", + x"05", x"61", x"FF", x"04", x"00", x"2B", x"D9", x"21", x"3C", x"38", + x"34", x"30", x"2C", x"28", x"24", x"20", x"1C", x"08", x"40", x"E0", + x"10", x"FF", x"FF", x"1C", x"18", x"14", x"FF", x"9B", x"FF", x"FE", + x"21", x"E4", x"FF", x"21", x"1C", x"18", x"14", x"10", x"9B", x"20", + x"D8", x"24", x"20", x"10", x"1C", x"21", x"18", x"14", x"03", x"01", + x"05", x"04", x"00", x"02", x"61", x"21", x"00", x"01", x"64", x"FF", + x"02", x"BB", x"C9", x"5B", x"CD", x"01", x"00", x"01", x"64", x"FF", + x"02", x"BA", x"BA", x"5B", x"20", x"00", x"01", x"02", x"01", x"FF", + x"64", x"FF", x"08", x"BE", x"FF", x"01", x"00", x"02", x"64", x"FF", + x"02", x"CC", x"CD", x"5B", x"B9", x"01", x"00", x"03", x"FF", x"2B", + x"12", x"21", x"FF", x"FF", x"00", x"64", x"21", x"9B", x"BA", x"21", + x"21", x"64", x"01", x"FF", x"9B", x"BA", x"2B", x"F2", x"00", x"00", + x"64", x"21", x"02", x"CD", x"BC", x"5B", x"C8", x"2B", x"21", x"24", + x"20", x"1C", x"18", x"14", x"10", x"07", x"21", x"61", x"28", x"E0", + x"14", x"21", x"04", x"1C", x"84", x"18", x"04", x"6F", x"FF", x"64", + x"23", x"00", x"F8", x"C2", x"02", x"21", x"43", x"10", x"1C", x"18", + x"14", x"21", x"20", x"70", x"F8", x"E0", x"18", x"21", x"04", x"14", + x"1C", x"84", x"21", x"01", x"01", x"00", x"02", x"21", x"21", x"02", + x"01", x"03", x"23", x"FF", x"FF", x"64", x"23", x"9B", x"20", x"04", + x"BE", x"00", x"FD", x"1C", x"18", x"14", x"20", x"FF", x"E4", x"20", + x"E8", x"14", x"10", x"21", x"02", x"01", x"00", x"01", x"21", x"21", + x"02", x"03", x"FF", x"64", x"FF", x"07", x"E4", x"FE", x"04", x"40", + x"23", x"14", x"10", x"20", x"FF", x"E4", x"18", x"D8", x"18", x"24", + x"20", x"1C", x"14", x"0C", x"00", x"22", x"21", x"21", x"01", x"41", + x"02", x"ED", x"00", x"0C", x"01", x"FF", x"2B", x"16", x"00", x"04", + x"80", x"21", x"00", x"21", x"00", x"00", x"14", x"21", x"EE", x"00", + x"EF", x"00", x"10", x"21", x"01", x"0C", x"FF", x"2B", x"ED", x"04", + x"24", x"20", x"1C", x"18", x"14", x"08", x"28", x"FA", x"01", x"0C", + x"3E", x"FF", x"04", x"03", x"FF", x"03", x"01", x"FA", x"03", x"FA", + x"03", x"03", x"00", x"03", x"FF", x"FA", x"03", x"04", x"00", x"FF", + x"FA", x"03", x"D8", x"18", x"00", x"24", x"10", x"20", x"1C", x"6F", + x"14", x"70", x"48", x"48", x"ED", x"48", x"48", x"38", x"3C", x"10", + x"04", x"68", x"FF", x"00", x"FF", x"FB", x"21", x"00", x"01", x"2B", + x"24", x"00", x"48", x"ED", x"50", x"42", x"48", x"38", x"3C", x"10", + x"01", x"21", x"A2", x"48", x"1F", x"00", x"4E", x"40", x"42", x"21", + x"38", x"10", x"3C", x"56", x"01", x"20", x"F3", x"2B", x"24", x"20", + x"1C", x"18", x"14", x"10", x"58", x"D3", x"28", x"24", x"20", x"1C", + x"18", x"14", x"10", x"70", x"D3", x"28", x"6C", x"02", x"02", x"6C", + x"FF", x"02", x"6C", x"FF", x"6C", x"FF", x"21", x"ED", x"40", x"34", + x"3C", x"82", x"21", x"DC", x"21", x"56", x"01", x"02", x"18", x"10", + x"31", x"60", x"1D", x"00", x"68", x"00", x"21", x"3E", x"21", x"F1", + x"21", x"3C", x"00", x"01", x"38", x"10", x"3C", x"56", x"21", x"02", + x"10", x"EA", x"01", x"24", x"20", x"1C", x"18", x"14", x"10", x"68", + x"D3", x"28", x"82", x"08", x"00", x"21", x"46", x"21", x"01", x"00", + x"FB", x"04", x"24", x"20", x"1C", x"18", x"14", x"10", x"00", x"28", + x"24", x"20", x"1C", x"18", x"14", x"10", x"D3", x"28", x"C8", x"18", + x"4D", x"2B", x"30", x"34", x"2C", x"28", x"24", x"20", x"1C", x"14", + x"10", x"51", x"21", x"00", x"00", x"21", x"21", x"21", x"C8", x"06", + x"00", x"36", x"BC", x"46", x"00", x"21", x"D0", x"21", x"4C", x"01", + x"FF", x"01", x"16", x"00", x"F4", x"21", x"04", x"06", x"64", x"FF", + x"80", x"21", x"D0", x"21", x"46", x"21", x"01", x"21", x"21", x"01", + x"D0", x"FF", x"ED", x"01", x"00", x"80", x"21", x"00", x"00", x"4D", + x"21", x"21", x"C8", x"06", x"5F", x"BC", x"00", x"D0", x"00", x"25", + x"01", x"FF", x"FF", x"13", x"04", x"F6", x"21", x"14", x"06", x"64", + x"FF", x"21", x"D0", x"21", x"00", x"01", x"21", x"FF", x"D0", x"FF", + x"01", x"EF", x"04", x"34", x"30", x"2C", x"28", x"24", x"20", x"1C", + x"18", x"14", x"10", x"08", x"38", x"33", x"21", x"5C", x"21", x"D8", + x"24", x"20", x"1C", x"18", x"6F", x"14", x"00", x"70", x"34", x"00", + x"70", x"20", x"12", x"21", x"21", x"F0", x"F2", x"1B", x"97", x"00", + x"01", x"00", x"0D", x"00", x"13", x"00", x"F7", x"00", x"00", x"00", + x"97", x"00", x"01", x"00", x"F5", x"00", x"4D", x"02", x"00", x"B3", + x"12", x"21", x"94", x"00", x"4D", x"12", x"21", x"94", x"00", x"D8", + x"24", x"20", x"1C", x"18", x"14", x"6F", x"10", x"56", x"00", x"00", + x"03", x"10", x"30", x"12", x"00", x"D3", x"78", x"39", x"00", x"24", + x"21", x"20", x"1C", x"18", x"14", x"10", x"08", x"28", x"D3", x"80", + x"C7", x"00", x"70", x"0C", x"F0", x"F2", x"0C", x"0D", x"01", x"97", + x"00", x"01", x"00", x"13", x"21", x"0D", x"00", x"F7", x"00", x"1B", + x"00", x"15", x"00", x"0D", x"02", x"76", x"00", x"DB", x"00", x"62", + x"18", x"DB", x"00", x"6B", x"18", x"DB", x"00", x"E3", x"00", x"30", + x"00", x"DB", x"00", x"81", x"00", x"C0", x"A8", x"A8", x"A8", x"A8", + x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", + x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", + x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", + x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", + x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", + x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", x"D0", x"DC", + x"A8", x"A8", x"A8", x"E8", x"A8", x"A8", x"A8", x"F4", x"A8", x"FC", + x"A8", x"A8", x"A8", x"A8", x"08", x"A8", x"A8", x"A8", x"A8", x"14", + x"A8", x"20", x"54", x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", + x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", + x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", + x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", + x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", + x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", + x"A8", x"A8", x"A8", x"A8", x"64", x"70", x"A8", x"A8", x"A8", x"7C", + x"A8", x"A8", x"A8", x"88", x"A8", x"90", x"A8", x"A8", x"A8", x"A8", + x"9C", x"A8", x"A8", x"A8", x"A8", x"A8", x"A8", x"B4", x"41", x"52", + x"00", x"78", x"20", x"00", x"00", x"64", x"6F", x"61", x"20", x"32", + x"00", x"72", x"2E", x"00", x"77", x"6D", x"20", x"74", x"73", x"2E", + x"00", x"6F", x"69", x"65", x"2E", x"00", x"20", x"6F", x"00", x"73", + x"65", x"79", x"00", x"67", x"70", x"64", x"00", x"6F", x"6E", x"61", + x"2E", x"00", x"74", x"20", x"20", x"6F", x"6E", x"72", x"6D", x"69", + x"2E", x"00", x"73", x"20", x"73", x"6F", x"6E", x"2E", x"00", x"6C", + x"6F", x"72", x"20", x"73", x"6C", x"2E", x"00", x"6C", x"6F", x"72", + x"20", x"66", x"68", x"00", x"73", x"6C", x"20", x"6C", x"65", x"00", + x"67", x"69", x"65", x"65", x"61", x"6C", x"65", x"61", x"6D", x"72", + x"00", x"73", x"73", x"20", x"65", x"72", x"20", x"74", x"50", x"73", + x"65", x"72", x"00", x"73", x"73", x"74", x"61", x"20", x"68", x"68", + x"20", x"75", x"62", x"00", x"A1", x"00", x"00", x"00", x"A4", x"A0", + x"9C", x"E4", x"F0", x"0C", x"00", x"00", x"00", x"4C", x"00", x"60", + x"00", x"88", x"00", x"A4", x"00", x"C4", x"00", x"E0", x"00", x"F8", + x"00", x"24", x"00", x"54", x"05", x"00", x"B0", x"00", x"00", x"07", + x"00", x"CC", x"00", x"88", x"0F", x"00", x"20", x"00", x"00", x"0F", + x"00", x"2C", x"00", x"00", x"06", x"00", x"3C", x"00", x"B8", x"A8", + others => x"00" + ), + 1 => ( + x"00", x"9C", x"00", x"3D", x"00", x"1D", x"00", x"1E", x"00", x"00", + x"08", x"FF", x"00", x"08", x"10", x"18", x"20", x"28", x"30", x"38", + x"40", x"48", x"50", x"58", x"60", x"68", x"70", x"78", x"80", x"88", + x"90", x"98", x"A0", x"A8", x"B0", x"B8", x"C0", x"C8", x"D0", x"D8", + x"F0", x"F8", x"05", x"00", x"00", x"00", x"00", x"00", x"20", x"00", + x"00", x"10", x"00", x"00", x"00", x"00", x"00", x"00", x"10", x"00", + x"00", x"00", x"10", x"10", x"00", x"00", x"00", x"00", x"00", x"00", + x"10", x"20", x"FF", x"00", x"10", x"00", x"00", x"00", x"10", x"10", + x"00", x"00", x"FF", x"00", x"00", x"00", x"10", x"00", x"00", x"00", + x"00", x"00", x"26", x"26", x"FF", x"00", x"00", x"00", x"F0", x"00", + x"00", x"F0", x"00", x"00", x"FF", x"40", x"00", x"00", x"00", x"FF", + x"40", x"00", x"00", x"00", x"00", x"00", x"FF", x"00", x"00", x"FF", + x"00", x"00", x"00", x"00", x"2E", x"2E", x"FF", x"00", x"FF", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"10", x"00", x"18", x"00", + x"00", x"FF", x"00", x"00", x"FF", x"00", x"10", x"00", x"00", x"00", + x"FF", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"FF", x"00", x"00", x"00", + x"00", x"10", x"00", x"00", x"00", x"00", x"FF", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"FF", x"00", x"00", x"FF", x"00", x"00", + x"00", x"FF", x"00", x"00", x"00", x"00", x"10", x"00", x"38", x"10", + x"10", x"10", x"FF", x"00", x"00", x"FF", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"10", x"00", x"10", x"00", x"00", x"00", x"00", + x"10", x"00", x"00", x"80", x"00", x"28", x"00", x"28", x"00", x"00", + x"FF", x"30", x"00", x"00", x"00", x"00", x"00", x"00", x"10", x"00", + x"00", x"F0", x"01", x"FF", x"FF", x"FF", x"31", x"00", x"00", x"28", + x"28", x"00", x"00", x"00", x"FF", x"00", x"FF", x"FF", x"31", x"FF", + x"00", x"00", x"00", x"80", x"00", x"1B", x"10", x"1C", x"10", x"19", + x"10", x"00", x"80", x"24", x"24", x"2C", x"2C", x"20", x"00", x"10", + x"00", x"01", x"00", x"00", x"00", x"10", x"28", x"2C", x"FF", x"20", + x"00", x"2C", x"00", x"FF", x"00", x"10", x"28", x"2C", x"FF", x"20", + x"FF", x"2C", x"00", x"00", x"00", x"00", x"00", x"10", x"00", x"00", + x"28", x"00", x"00", x"10", x"00", x"30", x"10", x"20", x"00", x"14", + x"18", x"FF", x"14", x"00", x"00", x"01", x"20", x"00", x"10", x"81", + x"00", x"00", x"FF", x"81", x"00", x"00", x"FF", x"81", x"00", x"00", + x"81", x"00", x"81", x"80", x"00", x"80", x"00", x"00", x"00", x"00", + x"81", x"00", x"00", x"00", x"81", x"00", x"00", x"FF", x"1C", x"00", + x"00", x"FF", x"00", x"81", x"00", x"81", x"FF", x"00", x"1C", x"00", + x"FF", x"FF", x"FF", x"00", x"FF", x"00", x"1C", x"1C", x"00", x"00", + x"FF", x"00", x"81", x"00", x"00", x"FF", x"00", x"81", x"00", x"81", + x"81", x"00", x"00", x"00", x"00", x"00", x"81", x"00", x"00", x"01", + x"00", x"81", x"80", x"41", x"39", x"80", x"81", x"38", x"10", x"10", + x"32", x"2B", x"00", x"10", x"28", x"00", x"00", x"28", x"10", x"FF", + x"FF", x"10", x"FF", x"00", x"00", x"81", x"00", x"00", x"00", x"01", + x"00", x"81", x"00", x"00", x"00", x"00", x"FF", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"01", x"00", x"FF", x"00", x"FF", x"00", + x"00", x"00", x"00", x"00", x"FF", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"88", x"00", x"00", x"80", x"19", x"00", + x"01", x"17", x"00", x"00", x"00", x"00", x"00", x"00", x"01", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"FF", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"FF", x"00", x"00", x"00", x"FF", + x"00", x"00", x"FF", x"00", x"10", x"10", x"00", x"00", x"00", x"00", + x"00", x"00", x"FF", x"00", x"01", x"00", x"00", x"00", x"FF", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"FF", x"00", + x"20", x"00", x"1D", x"01", x"20", x"01", x"00", x"00", x"00", x"FF", + x"00", x"00", x"FF", x"00", x"10", x"10", x"00", x"00", x"00", x"00", + x"01", x"81", x"01", x"00", x"01", x"00", x"01", x"00", x"01", x"81", + x"81", x"FF", x"00", x"10", x"01", x"81", x"00", x"00", x"FF", x"00", + x"20", x"00", x"1D", x"01", x"20", x"01", x"00", x"01", x"00", x"01", + x"00", x"00", x"01", x"80", x"00", x"01", x"80", x"00", x"01", x"80", + x"01", x"80", x"00", x"01", x"80", x"00", x"01", x"80", x"00", x"01", + x"80", x"00", x"01", x"80", x"01", x"00", x"01", x"00", x"00", x"01", + x"80", x"00", x"01", x"80", x"00", x"01", x"80", x"01", x"80", x"00", + x"01", x"80", x"00", x"01", x"80", x"00", x"01", x"80", x"00", x"01", + x"80", x"01", x"20", x"01", x"00", x"01", x"00", x"01", x"00", x"01", + x"00", x"01", x"00", x"FF", x"30", x"81", x"21", x"81", x"00", x"81", + x"FF", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"88", + x"1D", x"FF", x"00", x"00", x"30", x"00", x"00", x"11", x"20", x"81", + x"00", x"81", x"00", x"00", x"00", x"00", x"FF", x"00", x"01", x"00", + x"81", x"81", x"29", x"21", x"20", x"10", x"10", x"10", x"10", x"18", + x"10", x"00", x"00", x"30", x"FF", x"00", x"11", x"00", x"20", x"81", + x"FF", x"81", x"88", x"00", x"00", x"10", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"01", x"00", x"10", x"00", x"02", x"00", + x"FF", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"80", x"20", + x"01", x"00", x"00", x"10", x"FF", x"20", x"00", x"00", x"00", x"00", + x"00", x"00", x"FF", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"A0", x"00", x"00", x"00", x"98", + x"88", x"00", x"00", x"00", x"B8", x"A8", x"00", x"FF", x"00", x"80", + x"03", x"FF", x"01", x"00", x"00", x"01", x"00", x"00", x"00", x"10", + x"02", x"00", x"00", x"00", x"10", x"00", x"00", x"28", x"00", x"01", + x"20", x"00", x"10", x"10", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"FF", x"00", x"00", x"00", x"01", x"00", x"01", x"00", x"00", + x"01", x"00", x"00", x"00", x"10", x"02", x"00", x"01", x"00", x"00", + x"00", x"01", x"00", x"00", x"00", x"10", x"FF", x"28", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"FF", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"01", x"00", x"FF", + x"20", x"02", x"00", x"20", x"00", x"00", x"00", x"00", x"01", x"00", + x"FF", x"00", x"00", x"00", x"00", x"80", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"01", x"88", x"00", x"00", x"01", x"FF", + x"00", x"00", x"00", x"03", x"00", x"00", x"00", x"00", x"01", x"00", + x"00", x"00", x"00", x"03", x"00", x"00", x"00", x"00", x"00", x"00", + x"01", x"00", x"00", x"01", x"00", x"00", x"00", x"00", x"01", x"00", + x"00", x"00", x"00", x"03", x"00", x"00", x"00", x"00", x"00", x"10", + x"00", x"90", x"FF", x"00", x"00", x"01", x"28", x"01", x"00", x"28", + x"20", x"01", x"00", x"00", x"01", x"00", x"10", x"FF", x"00", x"00", + x"01", x"28", x"00", x"00", x"00", x"03", x"00", x"04", x"20", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"28", x"01", x"00", x"FF", + x"00", x"80", x"00", x"00", x"00", x"00", x"00", x"01", x"00", x"00", + x"28", x"00", x"1C", x"27", x"00", x"28", x"28", x"00", x"00", x"00", + x"00", x"20", x"00", x"03", x"1C", x"FF", x"00", x"88", x"00", x"00", + x"00", x"00", x"80", x"00", x"00", x"00", x"00", x"20", x"28", x"00", + x"00", x"00", x"88", x"00", x"00", x"01", x"88", x"01", x"00", x"00", + x"01", x"00", x"FF", x"00", x"00", x"00", x"00", x"00", x"02", x"00", + x"FF", x"00", x"00", x"80", x"00", x"00", x"00", x"00", x"20", x"28", + x"00", x"00", x"00", x"01", x"00", x"00", x"02", x"00", x"00", x"00", + x"28", x"00", x"00", x"00", x"00", x"02", x"00", x"FF", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"88", x"80", x"00", x"04", + x"00", x"03", x"00", x"00", x"00", x"00", x"10", x"00", x"00", x"00", + x"10", x"10", x"00", x"20", x"00", x"00", x"00", x"28", x"FF", x"00", + x"FF", x"00", x"04", x"20", x"00", x"00", x"00", x"10", x"FF", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"02", x"00", x"00", + x"04", x"00", x"00", x"00", x"FF", x"00", x"00", x"02", x"00", x"02", + x"00", x"00", x"00", x"00", x"FF", x"02", x"00", x"00", x"00", x"FF", + x"02", x"00", x"FF", x"00", x"00", x"00", x"00", x"00", x"00", x"01", + x"00", x"03", x"1D", x"1D", x"03", x"80", x"1D", x"80", x"80", x"04", + x"00", x"00", x"FF", x"8A", x"00", x"FF", x"88", x"01", x"00", x"10", + x"00", x"00", x"1D", x"03", x"80", x"9C", x"1D", x"80", x"80", x"04", + x"00", x"80", x"04", x"1D", x"00", x"00", x"00", x"24", x"10", x"20", + x"80", x"04", x"80", x"00", x"00", x"00", x"FF", x"18", x"00", x"00", + x"00", x"00", x"00", x"00", x"80", x"03", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"80", x"03", x"00", x"00", x"26", x"24", x"00", + x"00", x"22", x"00", x"00", x"00", x"00", x"20", x"03", x"80", x"00", + x"80", x"A1", x"98", x"04", x"80", x"00", x"00", x"00", x"00", x"00", + x"00", x"80", x"00", x"00", x"00", x"00", x"28", x"00", x"20", x"FF", + x"20", x"80", x"00", x"00", x"80", x"04", x"80", x"00", x"98", x"00", + x"00", x"FF", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"80", + x"03", x"00", x"80", x"00", x"20", x"88", x"00", x"20", x"00", x"00", + x"FF", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"03", x"00", x"FF", x"00", + x"00", x"10", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"F0", x"00", x"00", x"80", x"A0", x"88", x"1A", x"00", + x"10", x"05", x"1A", x"00", x"00", x"28", x"01", x"20", x"00", x"00", + x"00", x"00", x"00", x"20", x"FF", x"20", x"00", x"00", x"01", x"00", + x"28", x"28", x"01", x"20", x"00", x"20", x"00", x"20", x"28", x"00", + x"01", x"00", x"FF", x"00", x"20", x"F0", x"F0", x"00", x"00", x"00", + x"98", x"80", x"1A", x"00", x"05", x"1A", x"00", x"01", x"00", x"00", + x"00", x"00", x"FF", x"00", x"00", x"FF", x"20", x"00", x"00", x"01", + x"00", x"28", x"01", x"20", x"00", x"00", x"20", x"FF", x"01", x"00", + x"00", x"FF", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"05", x"88", x"05", x"80", x"FF", + x"00", x"00", x"00", x"00", x"01", x"00", x"00", x"03", x"1D", x"00", + x"03", x"1D", x"05", x"20", x"80", x"00", x"00", x"00", x"02", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"FF", x"00", x"00", x"00", + x"02", x"00", x"00", x"00", x"FF", x"00", x"00", x"00", x"00", x"FF", + x"05", x"20", x"05", x"00", x"00", x"05", x"20", x"05", x"00", x"FF", + x"00", x"00", x"00", x"00", x"00", x"01", x"00", x"00", x"00", x"1E", + x"1E", x"00", x"00", x"00", x"00", x"03", x"80", x"00", x"00", x"00", + x"10", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"03", x"80", + x"05", x"00", x"03", x"1D", x"00", x"00", x"1D", x"00", x"00", x"02", + x"00", x"00", x"00", x"00", x"20", x"00", x"00", x"FF", x"00", x"80", + x"00", x"00", x"00", x"00", x"00", x"04", x"00", x"05", x"00", x"04", + x"80", x"05", x"00", x"04", x"80", x"05", x"00", x"FF", x"00", x"00", + x"00", x"05", x"00", x"05", x"00", x"09", x"07", x"07", x"07", x"07", + x"07", x"07", x"07", x"07", x"07", x"07", x"07", x"07", x"07", x"07", + x"07", x"07", x"07", x"07", x"07", x"07", x"07", x"07", x"07", x"07", + x"07", x"07", x"07", x"07", x"07", x"07", x"07", x"07", x"07", x"07", + x"07", x"07", x"07", x"07", x"07", x"07", x"07", x"07", x"07", x"07", + x"07", x"07", x"07", x"07", x"07", x"07", x"07", x"07", x"07", x"07", + x"07", x"07", x"07", x"07", x"07", x"07", x"07", x"07", x"09", x"09", + x"07", x"07", x"07", x"09", x"07", x"07", x"07", x"09", x"07", x"09", + x"07", x"07", x"07", x"07", x"0A", x"07", x"07", x"07", x"07", x"0A", + x"07", x"0A", x"09", x"07", x"07", x"07", x"07", x"07", x"07", x"07", + x"07", x"07", x"07", x"07", x"07", x"07", x"07", x"07", x"07", x"07", + x"07", x"07", x"07", x"07", x"07", x"07", x"07", x"07", x"07", x"07", + x"07", x"07", x"07", x"07", x"07", x"07", x"07", x"07", x"07", x"07", + x"07", x"07", x"07", x"07", x"07", x"07", x"07", x"07", x"07", x"07", + x"07", x"07", x"07", x"07", x"07", x"07", x"07", x"07", x"07", x"07", + x"07", x"07", x"07", x"07", x"09", x"09", x"07", x"07", x"07", x"09", + x"07", x"07", x"07", x"09", x"07", x"09", x"07", x"07", x"07", x"07", + x"09", x"07", x"07", x"07", x"07", x"09", x"07", x"09", x"54", x"45", + x"52", x"25", x"77", x"00", x"20", x"69", x"6F", x"6F", x"72", x"2E", + x"00", x"61", x"2E", x"00", x"65", x"65", x"79", x"6E", x"74", x"2E", + x"00", x"6C", x"20", x"67", x"2E", x"00", x"52", x"6D", x"00", x"61", + x"4D", x"72", x"00", x"61", x"55", x"61", x"00", x"6C", x"69", x"64", + x"20", x"00", x"69", x"67", x"72", x"63", x"69", x"74", x"73", x"73", + x"20", x"00", x"61", x"67", x"61", x"63", x"65", x"20", x"00", x"75", + x"6E", x"65", x"65", x"61", x"62", x"6B", x"00", x"75", x"6E", x"77", + x"65", x"20", x"73", x"00", x"61", x"62", x"6B", x"20", x"6B", x"00", + x"61", x"73", x"20", x"65", x"20", x"69", x"6C", x"6C", x"20", x"6F", + x"00", x"61", x"69", x"6E", x"20", x"6F", x"73", x"61", x"20", x"61", + x"72", x"61", x"00", x"61", x"69", x"6F", x"65", x"2C", x"74", x"67", + x"74", x"6F", x"20", x"00", x"B0", x"00", x"00", x"00", x"1C", x"1C", + x"1C", x"1A", x"1A", x"1B", x"01", x"00", x"00", x"1B", x"00", x"1B", + x"00", x"1B", x"00", x"1B", x"00", x"1B", x"00", x"1B", x"00", x"1B", + x"00", x"1C", x"00", x"1C", x"32", x"00", x"1A", x"00", x"00", x"32", + x"00", x"1A", x"00", x"1C", x"62", x"00", x"1B", x"00", x"00", x"62", + x"00", x"1B", x"00", x"00", x"44", x"00", x"1B", x"00", x"1C", x"1C", + others => x"00" + ), + 2 => ( + x"1C", x"9C", x"1D", x"BD", x"02", x"42", x"03", x"63", x"40", x"42", + x"43", x"20", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"1A", x"40", + x"00", x"02", x"03", x"43", x"42", x"E0", x"42", x"03", x"02", x"43", + x"E0", x"00", x"02", x"82", x"A5", x"03", x"43", x"45", x"E0", x"00", + x"02", x"04", x"03", x"43", x"82", x"42", x"E0", x"00", x"02", x"82", + x"03", x"43", x"03", x"43", x"E0", x"00", x"03", x"05", x"65", x"62", + x"00", x"42", x"02", x"04", x"81", x"00", x"E0", x"00", x"02", x"E0", + x"00", x"04", x"E0", x"00", x"02", x"42", x"E0", x"42", x"84", x"02", + x"44", x"E0", x"00", x"C0", x"00", x"82", x"C6", x"A2", x"84", x"C0", + x"A5", x"E0", x"00", x"C0", x"05", x"05", x"C6", x"85", x"C0", x"84", + x"E0", x"00", x"82", x"00", x"40", x"00", x"00", x"42", x"82", x"63", + x"00", x"60", x"42", x"E0", x"42", x"E0", x"00", x"82", x"84", x"A2", + x"40", x"A5", x"E0", x"00", x"82", x"00", x"40", x"A5", x"45", x"84", + x"00", x"00", x"45", x"00", x"82", x"00", x"40", x"84", x"E0", x"00", + x"E0", x"00", x"E0", x"00", x"83", x"00", x"62", x"42", x"42", x"40", + x"02", x"62", x"00", x"60", x"05", x"00", x"84", x"65", x"00", x"60", + x"00", x"84", x"83", x"00", x"62", x"42", x"42", x"40", x"00", x"86", + x"00", x"C5", x"A2", x"42", x"40", x"84", x"00", x"86", x"02", x"02", + x"E2", x"45", x"C5", x"A6", x"C6", x"C0", x"84", x"04", x"64", x"00", + x"E0", x"00", x"E0", x"02", x"00", x"00", x"03", x"A3", x"03", x"A3", + x"A0", x"A3", x"A8", x"06", x"07", x"C4", x"A5", x"E5", x"65", x"63", + x"68", x"06", x"E0", x"60", x"03", x"A3", x"03", x"A3", x"A0", x"A7", + x"03", x"06", x"00", x"0A", x"63", x"E9", x"06", x"6A", x"E7", x"C4", + x"65", x"A5", x"A8", x"A9", x"00", x"A5", x"63", x"E5", x"06", x"6A", + x"E7", x"E0", x"40", x"82", x"00", x"02", x"62", x"02", x"62", x"02", + x"62", x"E0", x"82", x"04", x"04", x"05", x"05", x"04", x"03", x"00", + x"07", x"00", x"08", x"C8", x"00", x"45", x"05", x"05", x"63", x"04", + x"60", x"05", x"86", x"C7", x"00", x"45", x"05", x"05", x"63", x"04", + x"60", x"05", x"E0", x"00", x"A0", x"00", x"A0", x"00", x"E0", x"00", + x"05", x"80", x"00", x"A4", x"40", x"05", x"00", x"86", x"42", x"02", + x"A4", x"60", x"02", x"E0", x"00", x"00", x"04", x"E0", x"00", x"82", + x"00", x"40", x"42", x"82", x"00", x"40", x"42", x"82", x"02", x"E0", + x"82", x"E0", x"82", x"84", x"E0", x"85", x"84", x"82", x"40", x"A5", + x"84", x"A2", x"40", x"00", x"85", x"E0", x"00", x"02", x"43", x"40", + x"42", x"43", x"00", x"80", x"E0", x"80", x"05", x"A2", x"A5", x"43", + x"04", x"63", x"43", x"42", x"45", x"00", x"82", x"84", x"40", x"42", + x"44", x"00", x"82", x"00", x"40", x"42", x"E0", x"80", x"E0", x"82", + x"82", x"00", x"42", x"42", x"43", x"60", x"82", x"E0", x"00", x"00", + x"00", x"82", x"86", x"02", x"02", x"85", x"83", x"07", x"02", x"E2", + x"06", x"05", x"84", x"43", x"C5", x"63", x"63", x"A4", x"02", x"04", + x"BD", x"44", x"A5", x"67", x"BF", x"83", x"45", x"E0", x"00", x"00", + x"00", x"80", x"BF", x"00", x"E0", x"BD", x"BD", x"BF", x"B0", x"82", + x"00", x"40", x"90", x"44", x"00", x"10", x"02", x"00", x"40", x"44", + x"BF", x"B0", x"E0", x"BD", x"BD", x"B1", x"BF", x"B4", x"B3", x"B2", + x"B0", x"82", x"00", x"40", x"A0", x"13", x"12", x"80", x"73", x"14", + x"00", x"52", x"43", x"03", x"43", x"03", x"43", x"00", x"00", x"44", + x"02", x"00", x"40", x"10", x"03", x"43", x"43", x"60", x"03", x"03", + x"43", x"43", x"60", x"03", x"03", x"43", x"00", x"02", x"00", x"42", + x"42", x"43", x"60", x"10", x"02", x"42", x"42", x"00", x"40", x"00", + x"43", x"03", x"43", x"00", x"00", x"04", x"02", x"00", x"40", x"10", + x"BF", x"B4", x"B3", x"B2", x"B1", x"B0", x"E0", x"BD", x"03", x"04", + x"64", x"10", x"64", x"80", x"00", x"02", x"62", x"02", x"62", x"00", + x"20", x"00", x"85", x"00", x"40", x"00", x"00", x"02", x"00", x"42", + x"42", x"43", x"60", x"10", x"02", x"62", x"42", x"00", x"40", x"00", + x"00", x"80", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"80", + x"82", x"03", x"42", x"43", x"00", x"82", x"62", x"02", x"62", x"00", + x"20", x"00", x"85", x"00", x"40", x"00", x"00", x"00", x"04", x"00", + x"00", x"02", x"00", x"82", x"02", x"00", x"82", x"02", x"00", x"82", + x"00", x"80", x"02", x"00", x"82", x"02", x"00", x"82", x"02", x"00", + x"82", x"02", x"00", x"82", x"00", x"04", x"00", x"00", x"02", x"00", + x"82", x"02", x"00", x"82", x"02", x"00", x"82", x"00", x"80", x"02", + x"00", x"82", x"02", x"00", x"82", x"02", x"00", x"82", x"02", x"00", + x"82", x"00", x"20", x"00", x"00", x"00", x"04", x"00", x"00", x"00", + x"24", x"00", x"00", x"02", x"43", x"82", x"03", x"84", x"E0", x"83", + x"BD", x"B5", x"15", x"B4", x"B3", x"B2", x"B1", x"BF", x"B0", x"00", + x"B5", x"12", x"13", x"14", x"42", x"23", x"50", x"02", x"00", x"82", + x"13", x"90", x"60", x"00", x"14", x"00", x"20", x"00", x"00", x"00", + x"82", x"83", x"02", x"02", x"A4", x"02", x"82", x"43", x"02", x"B1", + x"52", x"40", x"60", x"42", x"31", x"50", x"02", x"23", x"00", x"82", + x"13", x"90", x"B1", x"20", x"BF", x"A0", x"B4", x"B5", x"B3", x"B2", + x"B1", x"B0", x"E0", x"BD", x"00", x"00", x"B1", x"50", x"00", x"31", + x"BD", x"B1", x"B1", x"B2", x"BF", x"B0", x"20", x"92", x"00", x"40", + x"00", x"10", x"02", x"51", x"40", x"40", x"BF", x"B2", x"B1", x"B0", + x"E0", x"BD", x"BD", x"B3", x"B1", x"BF", x"B7", x"B6", x"B5", x"B4", + x"B2", x"B0", x"83", x"B4", x"A2", x"83", x"97", x"A3", x"94", x"80", + x"A0", x"95", x"94", x"60", x"E2", x"A2", x"B5", x"F6", x"B5", x"00", + x"00", x"F7", x"00", x"A2", x"44", x"00", x"10", x"A2", x"04", x"C2", + x"00", x"45", x"22", x"10", x"02", x"40", x"00", x"90", x"A5", x"00", + x"A0", x"02", x"02", x"22", x"52", x"00", x"44", x"00", x"00", x"23", + x"00", x"70", x"04", x"65", x"64", x"00", x"A2", x"00", x"04", x"44", + x"00", x"10", x"A2", x"04", x"E2", x"00", x"45", x"00", x"04", x"64", + x"65", x"00", x"10", x"22", x"00", x"02", x"40", x"90", x"BF", x"B7", + x"B6", x"B5", x"B4", x"B3", x"B2", x"B1", x"B0", x"E0", x"BD", x"BD", + x"B0", x"84", x"F0", x"BF", x"B2", x"B1", x"B2", x"00", x"D1", x"05", + x"40", x"00", x"A5", x"20", x"BF", x"B2", x"B1", x"B0", x"00", x"BD", + x"BD", x"BF", x"B4", x"B0", x"B3", x"80", x"B2", x"B1", x"82", x"91", + x"05", x"84", x"13", x"12", x"00", x"22", x"04", x"05", x"00", x"31", + x"07", x"06", x"04", x"00", x"05", x"05", x"04", x"A5", x"00", x"A5", + x"07", x"06", x"04", x"00", x"05", x"04", x"05", x"84", x"A5", x"A5", + x"00", x"84", x"04", x"00", x"31", x"05", x"04", x"A5", x"00", x"A5", + x"07", x"04", x"05", x"00", x"06", x"14", x"00", x"94", x"94", x"91", + x"40", x"72", x"52", x"52", x"04", x"00", x"80", x"00", x"04", x"80", + x"40", x"00", x"94", x"94", x"00", x"04", x"91", x"40", x"00", x"04", + x"00", x"20", x"07", x"05", x"06", x"00", x"04", x"00", x"00", x"BF", + x"B4", x"B3", x"B2", x"B1", x"B0", x"04", x"00", x"00", x"BD", x"BD", + x"B0", x"80", x"84", x"BF", x"00", x"B1", x"42", x"00", x"51", x"05", + x"B1", x"03", x"62", x"05", x"51", x"85", x"05", x"50", x"BF", x"B1", + x"B0", x"40", x"BD", x"00", x"65", x"BD", x"B1", x"80", x"A4", x"B0", + x"BF", x"00", x"A0", x"03", x"26", x"24", x"05", x"64", x"C5", x"31", + x"84", x"A5", x"22", x"A5", x"84", x"00", x"23", x"00", x"04", x"04", + x"00", x"00", x"25", x"BF", x"B1", x"B0", x"04", x"A5", x"00", x"BD", + x"BD", x"BF", x"B0", x"A0", x"02", x"A3", x"86", x"85", x"C3", x"A2", + x"84", x"A5", x"84", x"00", x"A5", x"05", x"00", x"04", x"02", x"05", + x"A2", x"BF", x"B0", x"04", x"A5", x"00", x"BD", x"BD", x"B1", x"BF", + x"B3", x"B2", x"B0", x"86", x"00", x"C0", x"80", x"00", x"12", x"00", + x"13", x"00", x"00", x"26", x"10", x"10", x"06", x"40", x"00", x"02", + x"02", x"22", x"42", x"20", x"43", x"00", x"72", x"40", x"60", x"00", + x"73", x"00", x"00", x"20", x"10", x"26", x"10", x"06", x"40", x"02", + x"BF", x"B3", x"B2", x"B1", x"B0", x"E0", x"BD", x"00", x"10", x"26", + x"00", x"10", x"A3", x"A2", x"63", x"43", x"42", x"00", x"A2", x"00", + x"A0", x"A2", x"00", x"40", x"42", x"00", x"A2", x"A2", x"00", x"42", + x"00", x"A2", x"BD", x"B2", x"12", x"BF", x"B0", x"B4", x"B3", x"00", + x"B1", x"00", x"44", x"44", x"00", x"85", x"44", x"85", x"80", x"00", + x"10", x"00", x"10", x"11", x"10", x"00", x"51", x"02", x"42", x"22", + x"40", x"00", x"44", x"00", x"85", x"11", x"44", x"85", x"80", x"00", + x"73", x"00", x"00", x"52", x"60", x"00", x"00", x"10", x"10", x"40", + x"85", x"00", x"82", x"00", x"10", x"42", x"40", x"13", x"BF", x"B4", + x"B3", x"B2", x"B1", x"B0", x"84", x"00", x"BD", x"BF", x"B4", x"B3", + x"B2", x"B1", x"B0", x"84", x"00", x"BD", x"00", x"11", x"11", x"00", + x"84", x"11", x"00", x"84", x"00", x"24", x"40", x"00", x"85", x"20", + x"80", x"11", x"80", x"00", x"00", x"00", x"10", x"43", x"60", x"42", + x"40", x"84", x"11", x"00", x"00", x"00", x"40", x"00", x"00", x"13", + x"40", x"82", x"00", x"42", x"85", x"00", x"82", x"00", x"14", x"43", + x"42", x"60", x"10", x"BF", x"B4", x"B3", x"B2", x"B1", x"B0", x"84", + x"00", x"BD", x"10", x"00", x"12", x"00", x"00", x"20", x"31", x"42", + x"30", x"52", x"BF", x"B4", x"B3", x"B2", x"B1", x"B0", x"00", x"BD", + x"BF", x"B4", x"B3", x"B2", x"B1", x"B0", x"00", x"BD", x"BD", x"B2", + x"92", x"92", x"BE", x"BF", x"B7", x"B6", x"B5", x"B4", x"B3", x"B1", + x"B0", x"40", x"80", x"02", x"16", x"80", x"00", x"00", x"53", x"15", + x"17", x"00", x"D6", x"00", x"00", x"40", x"00", x"60", x"35", x"22", + x"51", x"10", x"12", x"02", x"20", x"00", x"85", x"04", x"00", x"A5", + x"10", x"B7", x"00", x"C0", x"00", x"00", x"94", x"60", x"40", x"10", + x"00", x"94", x"12", x"11", x"02", x"1E", x"C2", x"15", x"02", x"11", + x"00", x"00", x"52", x"14", x"00", x"B5", x"C5", x"00", x"00", x"14", + x"02", x"50", x"31", x"20", x"DE", x"00", x"40", x"65", x"04", x"00", + x"A5", x"C0", x"00", x"A0", x"C5", x"73", x"40", x"31", x"00", x"73", + x"10", x"20", x"DE", x"BF", x"BE", x"B7", x"B6", x"B5", x"B4", x"B3", + x"B2", x"B1", x"B0", x"E0", x"BD", x"00", x"00", x"00", x"00", x"BD", + x"BF", x"B3", x"B2", x"B1", x"00", x"B0", x"04", x"00", x"84", x"04", + x"00", x"84", x"00", x"00", x"00", x"11", x"12", x"13", x"00", x"00", + x"42", x"00", x"51", x"00", x"52", x"00", x"53", x"00", x"00", x"00", + x"00", x"00", x"42", x"00", x"51", x"00", x"02", x"40", x"00", x"10", + x"00", x"00", x"00", x"00", x"10", x"00", x"00", x"00", x"00", x"BD", + x"BF", x"B4", x"B3", x"B2", x"B1", x"00", x"B0", x"00", x"00", x"02", + x"03", x"61", x"42", x"40", x"11", x"00", x"84", x"00", x"00", x"BF", + x"00", x"B4", x"B3", x"B2", x"B1", x"B0", x"E0", x"BD", x"00", x"84", + x"00", x"00", x"00", x"24", x"10", x"12", x"31", x"14", x"13", x"00", + x"00", x"42", x"00", x"50", x"20", x"52", x"00", x"54", x"00", x"82", + x"00", x"53", x"00", x"40", x"03", x"00", x"00", x"00", x"00", x"00", + x"85", x"00", x"00", x"00", x"85", x"00", x"00", x"43", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"41", x"20", + x"4F", x"79", x"24", x"00", x"78", x"6F", x"42", x"6C", x"65", x"30", + x"31", x"74", x"20", x"00", x"69", x"6D", x"72", x"6F", x"6E", x"2E", + x"00", x"70", x"64", x"61", x"2E", x"00", x"44", x"65", x"79", x"6C", + x"20", x"6F", x"00", x"6D", x"20", x"6F", x"00", x"70", x"64", x"20", + x"61", x"2E", x"61", x"6E", x"6F", x"6E", x"6D", x"20", x"6E", x"73", + x"6E", x"2E", x"72", x"6E", x"6C", x"20", x"74", x"73", x"2E", x"6F", + x"20", x"20", x"73", x"6C", x"20", x"63", x"00", x"6F", x"20", x"20", + x"74", x"6F", x"61", x"00", x"6C", x"20", x"63", x"73", x"63", x"2E", + x"6D", x"20", x"65", x"63", x"73", x"61", x"62", x"66", x"68", x"6D", + x"2E", x"6C", x"20", x"69", x"6E", x"72", x"75", x"74", x"2E", x"65", + x"20", x"74", x"2E", x"6C", x"20", x"6E", x"72", x"79", x"6C", x"75", + x"69", x"68", x"64", x"2E", x"B9", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"0C", x"00", x"00", x"00", x"00", x"0C", + x"00", x"00", x"00", x"00", x"11", x"00", x"00", x"00", x"00", x"01", + x"00", x"00", x"00", x"00", x"0C", x"00", x"00", x"00", x"00", x"00", + others => x"00" + ), + 3 => ( + x"3C", x"27", x"3C", x"27", x"3C", x"24", x"3C", x"24", x"AC", x"24", + x"00", x"14", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"0C", x"00", x"00", x"08", x"00", x"00", x"3C", x"03", + x"00", x"3C", x"24", x"A0", x"90", x"03", x"30", x"24", x"3C", x"A0", + x"03", x"00", x"3C", x"00", x"30", x"24", x"A0", x"A0", x"03", x"00", + x"3C", x"00", x"24", x"A0", x"00", x"8C", x"03", x"00", x"3C", x"00", + x"24", x"A0", x"24", x"A0", x"03", x"00", x"3C", x"24", x"A0", x"90", + x"00", x"30", x"00", x"00", x"04", x"00", x"03", x"00", x"8C", x"03", + x"00", x"AC", x"03", x"00", x"3C", x"8C", x"03", x"30", x"30", x"3C", + x"AC", x"03", x"00", x"10", x"00", x"80", x"24", x"A0", x"24", x"14", + x"24", x"03", x"00", x"10", x"00", x"00", x"24", x"A0", x"14", x"24", + x"03", x"00", x"90", x"00", x"10", x"00", x"00", x"24", x"00", x"90", + x"00", x"14", x"24", x"03", x"24", x"03", x"00", x"90", x"24", x"A0", + x"14", x"24", x"03", x"00", x"90", x"00", x"10", x"30", x"10", x"24", + x"08", x"00", x"10", x"00", x"90", x"00", x"14", x"24", x"03", x"00", + x"03", x"00", x"03", x"00", x"90", x"00", x"24", x"30", x"2C", x"14", + x"24", x"10", x"00", x"10", x"24", x"08", x"24", x"10", x"00", x"10", + x"00", x"24", x"90", x"00", x"24", x"30", x"2C", x"10", x"00", x"90", + x"00", x"24", x"30", x"2C", x"10", x"24", x"00", x"90", x"00", x"00", + x"00", x"00", x"24", x"30", x"2C", x"14", x"24", x"24", x"10", x"00", + x"03", x"00", x"03", x"00", x"08", x"00", x"24", x"A0", x"24", x"A0", + x"00", x"24", x"24", x"3C", x"24", x"00", x"2C", x"00", x"A0", x"24", + x"14", x"00", x"03", x"A0", x"24", x"A0", x"24", x"A0", x"00", x"24", + x"24", x"3C", x"08", x"24", x"24", x"A0", x"00", x"10", x"24", x"00", + x"00", x"30", x"2C", x"24", x"15", x"24", x"24", x"A0", x"00", x"14", + x"24", x"03", x"A0", x"8F", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"03", x"AF", x"00", x"00", x"00", x"00", x"00", x"24", x"00", + x"24", x"08", x"24", x"14", x"00", x"00", x"00", x"00", x"24", x"00", + x"10", x"00", x"30", x"14", x"00", x"00", x"00", x"00", x"24", x"00", + x"14", x"00", x"03", x"00", x"04", x"00", x"14", x"00", x"03", x"00", + x"00", x"04", x"00", x"00", x"10", x"00", x"00", x"00", x"24", x"00", + x"00", x"14", x"00", x"03", x"00", x"08", x"00", x"03", x"00", x"93", + x"00", x"14", x"24", x"93", x"00", x"10", x"24", x"A3", x"24", x"03", + x"A3", x"03", x"A3", x"A3", x"03", x"A3", x"30", x"2C", x"10", x"30", + x"A3", x"2C", x"10", x"00", x"A3", x"03", x"00", x"3C", x"24", x"A4", + x"24", x"14", x"00", x"A3", x"03", x"A3", x"3C", x"24", x"24", x"94", + x"3C", x"30", x"A4", x"24", x"14", x"00", x"24", x"24", x"A4", x"24", + x"14", x"00", x"93", x"00", x"14", x"24", x"03", x"A3", x"03", x"A3", + x"93", x"00", x"24", x"30", x"2C", x"10", x"A3", x"03", x"00", x"08", + x"00", x"93", x"93", x"00", x"00", x"93", x"93", x"01", x"00", x"00", + x"00", x"00", x"30", x"00", x"00", x"24", x"30", x"00", x"00", x"3C", + x"27", x"00", x"30", x"2C", x"AF", x"A3", x"A4", x"14", x"00", x"0C", + x"00", x"A3", x"8F", x"00", x"03", x"27", x"27", x"AF", x"AF", x"80", + x"00", x"10", x"24", x"30", x"0C", x"26", x"82", x"00", x"14", x"30", + x"8F", x"8F", x"03", x"27", x"27", x"AF", x"AF", x"AF", x"AF", x"AF", + x"AF", x"80", x"00", x"10", x"00", x"3C", x"3C", x"00", x"26", x"3C", + x"08", x"26", x"10", x"24", x"10", x"24", x"10", x"00", x"0C", x"30", + x"82", x"00", x"10", x"26", x"24", x"10", x"28", x"14", x"24", x"24", + x"10", x"28", x"10", x"24", x"24", x"14", x"00", x"92", x"00", x"24", + x"30", x"2C", x"10", x"26", x"00", x"02", x"8C", x"00", x"00", x"00", + x"10", x"24", x"14", x"00", x"0C", x"24", x"82", x"00", x"14", x"26", + x"8F", x"8F", x"8F", x"8F", x"8F", x"8F", x"03", x"27", x"82", x"24", + x"10", x"26", x"28", x"14", x"00", x"24", x"10", x"24", x"14", x"00", + x"02", x"0C", x"26", x"0C", x"00", x"08", x"00", x"92", x"00", x"24", + x"30", x"2C", x"10", x"26", x"00", x"02", x"8C", x"00", x"00", x"00", + x"08", x"A3", x"0C", x"00", x"08", x"00", x"0C", x"00", x"08", x"A3", + x"93", x"24", x"24", x"00", x"08", x"A3", x"10", x"24", x"14", x"00", + x"02", x"0C", x"26", x"0C", x"00", x"08", x"00", x"0C", x"24", x"08", + x"00", x"24", x"08", x"A3", x"24", x"08", x"A3", x"24", x"08", x"A3", + x"08", x"A3", x"24", x"08", x"A3", x"24", x"08", x"A3", x"24", x"08", + x"A3", x"24", x"08", x"A3", x"0C", x"24", x"08", x"00", x"24", x"08", + x"A3", x"24", x"08", x"A3", x"24", x"08", x"A3", x"08", x"A3", x"24", + x"08", x"A3", x"24", x"08", x"A3", x"24", x"08", x"A3", x"24", x"08", + x"A3", x"0C", x"02", x"08", x"00", x"0C", x"24", x"08", x"00", x"0C", + x"32", x"08", x"00", x"3C", x"8C", x"27", x"00", x"A3", x"03", x"A3", + x"27", x"AF", x"3C", x"AF", x"AF", x"AF", x"AF", x"AF", x"AF", x"00", + x"26", x"3C", x"24", x"24", x"8E", x"2A", x"30", x"00", x"02", x"A3", + x"12", x"A3", x"10", x"00", x"16", x"00", x"12", x"00", x"0C", x"00", + x"93", x"93", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"02", + x"00", x"A4", x"A0", x"8E", x"26", x"30", x"00", x"2A", x"02", x"A3", + x"16", x"A3", x"02", x"A2", x"8F", x"02", x"8F", x"8F", x"8F", x"8F", + x"8F", x"8F", x"03", x"27", x"0C", x"00", x"02", x"A0", x"08", x"26", + x"27", x"AF", x"30", x"AF", x"AF", x"AF", x"12", x"30", x"00", x"02", + x"0C", x"26", x"32", x"00", x"14", x"02", x"8F", x"8F", x"8F", x"8F", + x"03", x"27", x"27", x"AF", x"AF", x"AF", x"AF", x"AF", x"AF", x"AF", + x"AF", x"AF", x"90", x"90", x"90", x"02", x"90", x"90", x"26", x"00", + x"00", x"90", x"32", x"10", x"02", x"02", x"26", x"26", x"32", x"00", + x"08", x"26", x"0C", x"AF", x"8E", x"0C", x"26", x"8F", x"24", x"02", + x"0C", x"30", x"92", x"32", x"02", x"10", x"00", x"02", x"30", x"0C", + x"02", x"26", x"00", x"02", x"8C", x"00", x"8E", x"0C", x"00", x"92", + x"00", x"14", x"24", x"92", x"92", x"0C", x"AF", x"0C", x"24", x"8E", + x"0C", x"26", x"8F", x"24", x"02", x"0C", x"30", x"0C", x"24", x"92", + x"92", x"0C", x"32", x"92", x"00", x"02", x"14", x"02", x"8F", x"8F", + x"8F", x"8F", x"8F", x"8F", x"8F", x"8F", x"8F", x"03", x"27", x"27", + x"AF", x"30", x"30", x"AF", x"AF", x"AF", x"30", x"0C", x"30", x"26", + x"02", x"0C", x"30", x"02", x"8F", x"8F", x"8F", x"8F", x"08", x"27", + x"27", x"AF", x"AF", x"AF", x"AF", x"00", x"AF", x"AF", x"90", x"90", + x"92", x"90", x"92", x"92", x"0C", x"02", x"92", x"92", x"0C", x"26", + x"92", x"24", x"24", x"0C", x"24", x"92", x"92", x"24", x"0C", x"30", + x"92", x"24", x"24", x"0C", x"24", x"92", x"92", x"24", x"24", x"30", + x"0C", x"30", x"8E", x"0C", x"32", x"92", x"92", x"24", x"0C", x"30", + x"92", x"24", x"24", x"0C", x"24", x"92", x"00", x"26", x"32", x"02", + x"10", x"02", x"26", x"32", x"92", x"0C", x"02", x"0C", x"24", x"02", + x"02", x"0C", x"26", x"32", x"0C", x"24", x"02", x"14", x"00", x"92", + x"0C", x"02", x"92", x"24", x"24", x"0C", x"24", x"0C", x"02", x"8F", + x"8F", x"8F", x"8F", x"8F", x"8F", x"24", x"00", x"08", x"27", x"27", + x"AF", x"00", x"8C", x"AF", x"0C", x"AF", x"24", x"0C", x"30", x"24", + x"00", x"3C", x"24", x"00", x"A0", x"00", x"00", x"AC", x"8F", x"8F", + x"8F", x"00", x"27", x"08", x"A0", x"27", x"AF", x"00", x"8C", x"AF", + x"AF", x"0C", x"00", x"92", x"92", x"92", x"92", x"00", x"00", x"92", + x"24", x"24", x"02", x"30", x"30", x"0C", x"02", x"0C", x"24", x"8E", + x"0C", x"00", x"26", x"8F", x"8F", x"8F", x"24", x"30", x"08", x"27", + x"27", x"AF", x"AF", x"00", x"92", x"90", x"90", x"90", x"00", x"00", + x"24", x"24", x"30", x"0C", x"30", x"92", x"0C", x"24", x"8E", x"24", + x"00", x"8F", x"8F", x"24", x"30", x"08", x"27", x"27", x"AF", x"AF", + x"AF", x"AF", x"AF", x"90", x"00", x"10", x"00", x"00", x"24", x"08", + x"24", x"0C", x"00", x"92", x"26", x"32", x"02", x"10", x"00", x"26", + x"00", x"02", x"8C", x"02", x"90", x"00", x"10", x"00", x"10", x"00", + x"14", x"00", x"0C", x"02", x"26", x"92", x"32", x"02", x"14", x"26", + x"8F", x"8F", x"8F", x"8F", x"8F", x"03", x"27", x"0C", x"26", x"92", + x"08", x"32", x"90", x"90", x"24", x"10", x"24", x"08", x"A0", x"08", + x"A0", x"90", x"00", x"10", x"24", x"08", x"A0", x"90", x"00", x"24", + x"08", x"A0", x"27", x"AF", x"3C", x"AF", x"AF", x"AF", x"AF", x"0C", + x"AF", x"0C", x"26", x"26", x"0C", x"27", x"26", x"27", x"AF", x"0C", + x"24", x"0C", x"26", x"00", x"32", x"16", x"00", x"3C", x"24", x"02", + x"10", x"00", x"26", x"0C", x"27", x"00", x"26", x"27", x"AF", x"0C", + x"26", x"00", x"08", x"26", x"10", x"00", x"0C", x"00", x"00", x"02", + x"27", x"0C", x"AF", x"0C", x"26", x"30", x"10", x"02", x"8F", x"8F", + x"8F", x"8F", x"8F", x"8F", x"27", x"08", x"27", x"8F", x"8F", x"8F", + x"8F", x"8F", x"8F", x"27", x"08", x"27", x"0C", x"00", x"00", x"0C", + x"30", x"00", x"0C", x"30", x"0C", x"32", x"02", x"0C", x"27", x"12", + x"AF", x"00", x"02", x"08", x"00", x"0C", x"26", x"30", x"14", x"30", + x"14", x"27", x"12", x"00", x"0C", x"00", x"00", x"0C", x"02", x"16", + x"02", x"8F", x"00", x"24", x"27", x"0C", x"AF", x"0C", x"02", x"30", + x"30", x"10", x"26", x"8F", x"8F", x"8F", x"8F", x"8F", x"8F", x"27", + x"08", x"27", x"00", x"12", x"3C", x"00", x"0C", x"02", x"26", x"AE", + x"16", x"26", x"8F", x"8F", x"8F", x"8F", x"8F", x"8F", x"08", x"27", + x"8F", x"8F", x"8F", x"8F", x"8F", x"8F", x"08", x"27", x"27", x"AF", + x"24", x"00", x"AF", x"AF", x"AF", x"AF", x"AF", x"AF", x"AF", x"AF", + x"AF", x"10", x"00", x"3C", x"3C", x"00", x"00", x"00", x"24", x"24", + x"3C", x"08", x"26", x"0C", x"00", x"00", x"0C", x"02", x"12", x"26", + x"30", x"26", x"12", x"3C", x"16", x"02", x"26", x"24", x"0C", x"30", + x"00", x"00", x"0C", x"02", x"0C", x"02", x"26", x"02", x"00", x"26", + x"0C", x"32", x"16", x"24", x"3C", x"00", x"03", x"3C", x"3C", x"24", + x"00", x"00", x"24", x"24", x"08", x"26", x"8F", x"0C", x"00", x"12", + x"26", x"30", x"26", x"12", x"27", x"16", x"02", x"26", x"24", x"0C", + x"30", x"03", x"0C", x"02", x"8F", x"26", x"02", x"26", x"0C", x"32", + x"24", x"16", x"27", x"8F", x"8F", x"8F", x"8F", x"8F", x"8F", x"8F", + x"8F", x"8F", x"8F", x"03", x"27", x"08", x"00", x"08", x"00", x"27", + x"AF", x"AF", x"AF", x"AF", x"0C", x"AF", x"3C", x"0C", x"24", x"3C", + x"0C", x"24", x"0C", x"00", x"00", x"24", x"24", x"24", x"0C", x"00", + x"90", x"00", x"10", x"00", x"10", x"00", x"14", x"00", x"0C", x"00", + x"0C", x"00", x"90", x"00", x"14", x"00", x"2E", x"14", x"00", x"26", + x"0C", x"02", x"08", x"00", x"26", x"0C", x"02", x"08", x"00", x"27", + x"AF", x"AF", x"AF", x"AF", x"AF", x"0C", x"AF", x"0C", x"00", x"00", + x"00", x"04", x"30", x"10", x"3C", x"0C", x"27", x"0C", x"00", x"8F", + x"00", x"8F", x"8F", x"8F", x"8F", x"8F", x"03", x"27", x"0C", x"27", + x"08", x"00", x"0C", x"26", x"24", x"24", x"26", x"24", x"24", x"0C", + x"00", x"90", x"00", x"10", x"02", x"10", x"00", x"14", x"00", x"93", + x"00", x"10", x"00", x"14", x"24", x"0C", x"00", x"08", x"00", x"0C", + x"27", x"08", x"00", x"0C", x"27", x"08", x"00", x"14", x"00", x"0C", + x"00", x"08", x"00", x"0C", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"46", x"4C", + x"52", x"24", x"3A", x"00", x"25", x"76", x"20", x"74", x"64", x"76", + x"2E", x"53", x"74", x"2E", x"56", x"20", x"6F", x"63", x"65", x"20", + x"00", x"55", x"61", x"6D", x"20", x"00", x"44", x"4D", x"72", x"46", + x"68", x"6D", x"00", x"49", x"65", x"6C", x"00", x"55", x"61", x"67", + x"74", x"2E", x"57", x"69", x"66", x"69", x"6D", x"67", x"61", x"69", + x"6F", x"2E", x"45", x"69", x"66", x"68", x"6E", x"74", x"2E", x"43", + x"64", x"74", x"61", x"66", x"68", x"6F", x"00", x"43", x"64", x"74", + x"69", x"74", x"6C", x"2E", x"46", x"68", x"6F", x"69", x"6F", x"64", + x"49", x"65", x"7A", x"78", x"64", x"76", x"61", x"20", x"73", x"65", + x"79", x"46", x"68", x"20", x"61", x"72", x"6F", x"73", x"65", x"6C", + x"65", x"73", x"74", x"46", x"68", x"20", x"20", x"64", x"61", x"6F", + x"20", x"73", x"6C", x"65", x"12", x"07", x"01", x"03", x"00", x"00", + x"00", x"00", x"00", x"00", x"02", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00", x"19", x"04", x"00", x"01", x"00", x"19", + x"07", x"00", x"01", x"00", x"01", x"06", x"00", x"00", x"00", x"01", + x"06", x"00", x"00", x"00", x"10", x"07", x"00", x"02", x"00", x"00", + others => x"00" + ) + ); + +end data; \ No newline at end of file Index: layer2/trunk/sw/bin =================================================================== --- layer2/trunk/sw/bin (nonexistent) +++ layer2/trunk/sw/bin (revision 2)

layer2/trunk/sw/bin Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: layer2/trunk/sw/common/bram.lds =================================================================== --- layer2/trunk/sw/common/bram.lds (nonexistent) +++ layer2/trunk/sw/common/bram.lds (revision 2) @@ -0,0 +1,31 @@ +MEMORY +{ + BRAM : ORIGIN = 0x00000000, LENGTH = 16K +} + +SECTIONS +{ + .text : + { + *(.text) + *(.text.*) + } > BRAM + .rodata : + { + *(.rodata) + *(.rodata.*); + } > BRAM + .data : + { + _gp = . + 0x7ff0; /* 0x7ff0 -> middle of 64K area */ + *(.sdata) + *(.data) + } > BRAM + .bss : + { + _bss_start = .; + *(.bss) + *(.sbss) + _bss_end = .; + } > BRAM +} Index: layer2/trunk/sw/common/boot.s =================================================================== --- layer2/trunk/sw/common/boot.s (nonexistent) +++ layer2/trunk/sw/common/boot.s (revision 2) @@ -0,0 +1,188 @@ +################################################################################ +# Boot Up Code # +#------------------------------------------------------------------------------# +# REFERENCES # +# # +# [1] The MIPS programmer's handbook # +# Erin Frquhar and Philip Bunce # +# San Francisco, CA, Morgan Kaufmann Publishers, 1994 # +# ISBN 1-55860-297-6 # +# # +#------------------------------------------------------------------------------# +# Copyright (C)2011 Mathias H�rtnagl # +# # +# This program is free software: you can redistribute it and/or modify # +# it under the terms of the GNU General Public License as published by # +# the Free Software Foundation, either version 3 of the License, or # +# (at your option) any later version. # +# # +# This program is distributed in the hope that it will be useful, # +# but WITHOUT ANY WARRANTY; without even the implied warranty of # +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # +# GNU General Public License for more details. # +# # +# You should have received a copy of the GNU General Public License # +# along with this program. If not, see . # +################################################################################ + + .ifndef STACKSIZE # Stack size in byte. + .set STACKSIZE, 8192 + .endif + + .comm stack, STACKSIZE # Global memory: stack. + + .text + .align 2 +################################################################################ +# Execution Start # +#------------------------------------------------------------------------------# + .globl boot + .ent boot +boot: + .set noreorder + + la $gp, _gp # Set global pointer. + la $sp, stack+STACKSIZE-24 # Set stack pointer. + + la $v0, _bss_start # Global variable region start. + la $v1, _bss_end # Global variable region end. + +clrbss: # Clear global variable region. + sw $0, ($v0) + addiu $v0, 4 + blt $v0, $v1, clrbss # Continue execution when .bss region is clear. + nop + + .set noat + and $at, $0, $0 # Clear all registers. + .set at + and $v0, $0, $0 + and $v1, $0, $0 + and $a0, $0, $0 + and $a1, $0, $0 + and $a2, $0, $0 + and $a3, $0, $0 + and $t0, $0, $0 + and $t1, $0, $0 + and $t2, $0, $0 + and $t3, $0, $0 + and $t4, $0, $0 + and $t5, $0, $0 + and $t6, $0, $0 + and $t7, $0, $0 + and $s0, $0, $0 + and $s1, $0, $0 + and $s2, $0, $0 + and $s3, $0, $0 + and $s4, $0, $0 + and $s5, $0, $0 + and $s6, $0, $0 + and $s7, $0, $0 + and $t8, $0, $0 + and $t9, $0, $0 + and $k0, $0, $0 + and $k1, $0, $0 + and $fp, $0, $0 + and $ra, $0, $0 + + jal main # Start execution of the C main procedure. + nop + +loop: # Final loop. Afer returning from C main loop. + nop + j loop # Real Infinity. + nop + nop + + .set reorder + .end boot + + +################################################################################ +# Interrupt Start # +#------------------------------------------------------------------------------# + # .ent intr_handler +# intr_handler: + # .set noreorder + # .set noat + +# If we do not include the Interrupt API, simply return to normal execution +# immediately. +# .ifdef _INTERRUPT + + # addiu $sp, $sp, -72 # Allocate space for all relevant registers. + # sw $at, 4($sp) # Save all registers, that are used directily + # sw $v0, 8($sp) # after a successful execution of the interrupt + # sw $v1, 12($sp) # service routines. + # sw $a0, 16($sp) # Registers $s0 - $s8 do not need to be saved, + # sw $a1, 20($sp) # since the compiler stores them if they are + # sw $a2, 24($sp) # used in a procedure. + # sw $a3, 28($sp) # $gp is the same for the entire source code. + # sw $t0, 32($sp) # Registers $k0 and $k1 are reserved for ASM + # sw $t1, 36($sp) # routines. The C compiler does not use them. + # sw $t2, 40($sp) + # sw $t3, 44($sp) + # sw $t4, 48($sp) + # sw $t5, 52($sp) + # sw $t6, 56($sp) + # sw $t7, 60($sp) + # sw $t8, 64($sp) + # sw $t9, 68($sp) + # sw $ra, 72($sp) + + # mfc0 $k0, $13 # Retrieve CAUSE (Pending Interrupts). + #nop + # mfc0 $k1, $12 # Retrieve SR (Interrupt mask and global IE). + # nop + # and $k0, $k0, $k1 # Get legal pending interrupts. + # addiu $sp, $sp, -24 + # jal intr_dispatch # Jump to C interrupt dispatch routine. + # srl $a0, $k0, 8 + # addiu $sp, $sp, 24 + + # lw $at, 4($sp) # Restore saved registers. + # lw $v0, 8($sp) + # lw $v1, 12($sp) + # lw $a0, 16($sp) + # lw $a1, 20($sp) + # lw $a2, 24($sp) + # lw $a3, 28($sp) + # lw $t0, 32($sp) + # lw $t1, 36($sp) + # lw $t2, 40($sp) + # lw $t3, 44($sp) + # lw $t4, 48($sp) + # lw $t5, 52($sp) + # lw $t6, 56($sp) + # lw $t7, 60($sp) + # lw $t8, 64($sp) + # lw $t9, 68($sp) + # lw $ra, 72($sp) + # addiu $sp, $sp, 72 # Undo stack allocation. + +# .endif + + # mfc0 $k1, $14 # Retrieve EPC + # nop + # jr $k1 # Return to normal execution. + # rfe # Restore from exception. Pop IE stack. + + # .set at + # .set reorder + # .end intr_handler + + +################################################################################ +# Start Flash Application # +#------------------------------------------------------------------------------# + .globl start + .ent start +start: + .set noreorder + + lui $k0, 0x2000 + jr $k0 + nop + + .set reorder + .end start Index: layer2/trunk/sw/common/vhd.py =================================================================== --- layer2/trunk/sw/common/vhd.py (nonexistent) +++ layer2/trunk/sw/common/vhd.py (revision 2) @@ -0,0 +1,89 @@ +#!/usr/bin/env python +#------------------------------------------------------------------------------# +# BIN to VHD converter # +#------------------------------------------------------------------------------# +# Copyright (C) 2011 Mathias Hoertnagl, mathias.hoertnagl@gmail.com # +# # +# This program is free software; you can redistribute it and/or modify it # +# under the terms of the GNU General Public License as published by the Free # +# Software Foundation; either version 3 of the License, or (at your option) # +# any later version. # +# This program is distributed in the hope that it will be useful, but WITHOUT # +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or # +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for # +# more details. # +# You should have received a copy of the GNU General Public License along with # +# this program; if not, see . # +#------------------------------------------------------------------------------# +import sys + +header = "\ +library ieee;\n\ +use ieee.std_logic_1164.all;\n\ +use ieee.numeric_std.all;\n\ +\n\ +library work;\n\ +use work.imem.all;\n\ +\n\ +package data is\n\ +\n\ + constant data : mem_block_t := (\n" + + +if len(sys.argv) != 3: + print "Usage: python", sys.argv[0], "<*.bin file>", "" + sys.exit() + +outp = {} +data = {} + +data[0] = " 0 => (\n " +data[1] = " 1 => (\n " +data[2] = " 2 => (\n " +data[3] = " 3 => (\n " + +print "" +print "************************************************************************" +print "* Memory File Generation *" +print "************************************************************************" + +print "Loading:", sys.argv[1] + +inp = open(sys.argv[1], 'rb') +bin = inp.read() +inp.close() + +# Outout name is fixed to make it automatically loadable. +outp = open(sys.argv[2] + 'data.vhd', 'w') +outp.write(header) + +print "Writing memory file ..." + +i = 3 +j = 39 +for c in bin: + data[i] = data[i] + ('x"%02X", ' % ord(c)) + + if j == 0: + j = 39 + for k in range(4): + data[k] = data[k] + "\n " + else: + j = j - 1 + + if i == 0: + i = 3 + else: + i = i-1 + +for i in range(3): + data[i] = data[i] + 'others => x"00"\n ),\n' + +data[3] = data[3] + 'others => x"00"\n )\n );\n\nend data;' + +for i in range(4): + outp.write(data[i]) + +outp.close() + +print "Done!" \ No newline at end of file Index: layer2/trunk/sw/common/upload.py =================================================================== --- layer2/trunk/sw/common/upload.py (nonexistent) +++ layer2/trunk/sw/common/upload.py (revision 2) @@ -0,0 +1,73 @@ +#!/usr/bin/env python +#------------------------------------------------------------------------------# +# Serial Upload Tool # +#------------------------------------------------------------------------------# +# Uses pySerial visit [1] for the module. # +# # +# REFERENCES # +# [1] pySerial, http://pyserial.sourceforge.net/ # +# [2] Fabio Varesano, http://www.varesano.net/blog/fabio/ # +# serial%20rs232%20connections%20python # +#------------------------------------------------------------------------------# +# Copyright (C) 2011 Mathias Hoertnagl, mathias.hoertnagl@gmail.com # +# # +# This program is free software; you can redistribute it and/or modify it # +# under the terms of the GNU General Public License as published by the Free # +# Software Foundation; either version 3 of the License, or (at your option) # +# any later version. # +# This program is distributed in the hope that it will be useful, but WITHOUT # +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or # +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for # +# more details. # +# You should have received a copy of the GNU General Public License along with # +# this program; if not, see . # +#------------------------------------------------------------------------------# +import sys, struct, time +import serial + +if len(sys.argv) != 2: + print "Usage: python", sys.argv[0], "<*.bin file>" + sys.exit() + +# Set up serial port object. +s = serial.Serial( + port = 4, # 'COM5', + baudrate = 19200 +) + +# Load binary file. +inp = open(sys.argv[1], 'rb') +bin = inp.read() +inp.close() + +print "" +print "************************************************************************" +print "* Upload *" +print "************************************************************************" + +size = len(bin) +print "File size of '{0}' is: {1} bytes.".format(sys.argv[1], size) + +if s.isOpen(): + s.write(struct.pack('>I', size)) + + # void echoes the image size, after it has erased the flash. + # Check if it is the correct size. + esize = struct.unpack('>I', s.read(4))[0] + + if esize != size: + print "ERROR: Size echo is {0}. Expected: {1}.".format(esize, size) + sys.exit() + + print "Flash ready. Size echo correct." + + print "Sending data ..." + + # NOTE: Writing the entire file with s.write(bin) does not work. Possibly + # due to limited buffer size. + for c in bin: + s.write(c) + + s.close() + + print "Done!" \ No newline at end of file Index: layer2/trunk/sw/common/Makefile =================================================================== --- layer2/trunk/sw/common/Makefile (nonexistent) +++ layer2/trunk/sw/common/Makefile (revision 2) @@ -0,0 +1,57 @@ +#------------------------------------------------------------------------------# +# Common makefile # +#------------------------------------------------------------------------------# +# Copyright (C) 2011 Mathias Hoertnagl, mathias.hoertnagl@student.uibk.ac.at # +# # +# This program is free software; you can redistribute it and/or modify it # +# under the terms of the GNU General Public License as published by the Free # +# Software Foundation; either version 3 of the License, or (at your option) # +# any later version. # +# This program is distributed in the hope that it will be useful, but WITHOUT # +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or # +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for # +# more details. # +# You should have received a copy of the GNU General Public License along with # +# this program; if not, see . # +#------------------------------------------------------------------------------# +TOOL_DIR = /usr/local/mips-elf/bin/mips-elf- +SRC_DIR = ../ +BIN_DIR = $(SRC_DIR)bin/ +COM_DIR = $(SRC_DIR)common/ +LIB_DIR = $(SRC_DIR)lib/ +INC_DIR = $(SRC_DIR)lib/include/ + +LINK = $(COM_DIR)bram.lds +LINK2 = $(COM_DIR)flash.lds + +VPATH = $(SRC_DIR):$(COM_DIR):$(LIB_DIR):$(INC_DIR) + +CFLAGS = -march=r3000 -c -s -O2 -nostdlib -nodefaultlibs -std=c99 -Wall -w -I$(INC_DIR) +ASFLAGS = +ARFLAGS = rcs +LDFLAGS = -s -N -nodefaultlibs -nostdlib -T$(LINK) -Ttext 0 -eboot -Map mem.map +LDFLAGS2 = -s -N -nodefaultlibs -nostdlib -T$(LINK2) -Ttext 0x20000000 -estart -Map mem.map +OCPFLAGS = -I elf32-big -O binary +DMPFLAGS = --disassemble-all + +GCC = $(TOOL_DIR)gcc.exe $(CFLAGS) +AS = $(TOOL_DIR)as.exe $(ASFLAGS) +AR = $(TOOL_DIR)ar.exe $(ARFLAGS) +LD = $(TOOL_DIR)ld.exe $(LDFLAGS) +LD2 = $(TOOL_DIR)ld.exe $(LDFLAGS2) +OPC = $(TOOL_DIR)objcopy.exe $(OCPFLAGS) +DMP = $(TOOL_DIR)objdump.exe $(DMPFLAGS) +RM = rm +MEM = python $(COM_DIR)vhd.py +MEM2 = python $(COM_DIR)vhd2.py +LOAD = python $(COM_DIR)upload.py + +%.o : %.c + $(GCC) $< -o $@ + +%.o : %.s + $(AS) $< -o $@ + +.PHONY: clean +clean : + -@$(RM) *.o *.bin *.axf *.lst *.map \ No newline at end of file Index: layer2/trunk/sw/common/start.s =================================================================== --- layer2/trunk/sw/common/start.s (nonexistent) +++ layer2/trunk/sw/common/start.s (revision 2) @@ -0,0 +1,188 @@ +################################################################################ +# Start Up Code # +#------------------------------------------------------------------------------# +# REFERENCES # +# # +# [1] The MIPS programmer's handbook # +# Erin Frquhar and Philip Bunce # +# San Francisco, CA, Morgan Kaufmann Publishers, 1994 # +# ISBN 1-55860-297-6 # +# # +#------------------------------------------------------------------------------# +# Copyright (C)2011 Mathias H�rtnagl # +# # +# This program is free software: you can redistribute it and/or modify # +# it under the terms of the GNU General Public License as published by # +# the Free Software Foundation, either version 3 of the License, or # +# (at your option) any later version. # +# # +# This program is distributed in the hope that it will be useful, # +# but WITHOUT ANY WARRANTY; without even the implied warranty of # +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # +# GNU General Public License for more details. # +# # +# You should have received a copy of the GNU General Public License # +# along with this program. If not, see . # +################################################################################ + + .ifndef STACKSIZE # Stack size in byte. + .set STACKSIZE, 8192 + .endif + + .comm stack, STACKSIZE # Global memory: stack. + + .text + .align 2 +################################################################################ +# Execution Start # +#------------------------------------------------------------------------------# + .globl start + .ent start +start: + .set noreorder + + la $gp, _gp # Set global pointer. + la $sp, stack+STACKSIZE-24 # Set stack pointer. + + la $v0, _bss_start # Global variable region start. + la $v1, _bss_end # Global variable region end. + +clrbss: # Clear global variable region. + sw $0, ($v0) + addiu $v0, 4 + blt $v0, $v1, clrbss # Continue execution when .bss region is clear. + nop + + .set noat + and $at, $0, $0 # Clear all registers. + .set at + and $v0, $0, $0 + and $v1, $0, $0 + and $a0, $0, $0 + and $a1, $0, $0 + and $a2, $0, $0 + and $a3, $0, $0 + and $t0, $0, $0 + and $t1, $0, $0 + and $t2, $0, $0 + and $t3, $0, $0 + and $t4, $0, $0 + and $t5, $0, $0 + and $t6, $0, $0 + and $t7, $0, $0 + and $s0, $0, $0 + and $s1, $0, $0 + and $s2, $0, $0 + and $s3, $0, $0 + and $s4, $0, $0 + and $s5, $0, $0 + and $s6, $0, $0 + and $s7, $0, $0 + and $t8, $0, $0 + and $t9, $0, $0 + and $k0, $0, $0 + and $k1, $0, $0 + and $fp, $0, $0 + and $ra, $0, $0 + + jal main # Start execution of the C main procedure. + nop + +loop: # Final loop. Afer returning from C main loop. + nop + j loop # Real Infinity. + nop + nop + + .set reorder + .end start + + +################################################################################ +# Interrupt Start # +#------------------------------------------------------------------------------# + .ent intr_handler +intr_handler: + .set noreorder + .set noat + +# If we do not include the Interrupt API, simply return to normal execution +# immediately. +.ifdef _INTERRUPT + + addiu $sp, $sp, -72 # Allocate space for all relevant registers. + sw $at, 4($sp) # Save all registers, that are used directily + sw $v0, 8($sp) # after a successful execution of the interrupt + sw $v1, 12($sp) # service routines. + sw $a0, 16($sp) # Registers $s0 - $s8 do not need to be saved, + sw $a1, 20($sp) # since the compiler stores them if they are + sw $a2, 24($sp) # used in a procedure. + sw $a3, 28($sp) # $gp is the same for the entire source code. + sw $t0, 32($sp) # Registers $k0 and $k1 are reserved for ASM + sw $t1, 36($sp) # routines. The C compiler does not use them. + sw $t2, 40($sp) + sw $t3, 44($sp) + sw $t4, 48($sp) + sw $t5, 52($sp) + sw $t6, 56($sp) + sw $t7, 60($sp) + sw $t8, 64($sp) + sw $t9, 68($sp) + sw $ra, 72($sp) + + mfc0 $k0, $13 # Retrieve CAUSE (Pending Interrupts). + nop + mfc0 $k1, $12 # Retrieve SR (Interrupt mask and global IE). + nop + and $k0, $k0, $k1 # Get legal pending interrupts. + + addiu $sp, $sp, -24 # Allocate minimal procedure context. + jal intr_dispatch # Jump to C interrupt dispatch routine. + srl $a0, $k0, 8 # a0 <- legal pending interrupts. + addiu $sp, $sp, 24 # Deallocate minimal procedure context. + + lw $at, 4($sp) # Restore saved registers. + lw $v0, 8($sp) + lw $v1, 12($sp) + lw $a0, 16($sp) + lw $a1, 20($sp) + lw $a2, 24($sp) + lw $a3, 28($sp) + lw $t0, 32($sp) + lw $t1, 36($sp) + lw $t2, 40($sp) + lw $t3, 44($sp) + lw $t4, 48($sp) + lw $t5, 52($sp) + lw $t6, 56($sp) + lw $t7, 60($sp) + lw $t8, 64($sp) + lw $t9, 68($sp) + lw $ra, 72($sp) + addiu $sp, $sp, 72 # Undo stack allocation. + +.endif + + mfc0 $k1, $14 # Retrieve EPC. + nop + jr $k1 # Return to normal execution. + rfe # Restore from exception. Pop IE stack. + + .set at + .set reorder + .end intr_handler + + +################################################################################ +# Return to Bootloader # +#------------------------------------------------------------------------------# + .globl boot + .ent boot +boot: + .set noreorder + + jr $0 + nop + + .set reorder + .end boot Index: layer2/trunk/sw/common/flash.lds =================================================================== --- layer2/trunk/sw/common/flash.lds (nonexistent) +++ layer2/trunk/sw/common/flash.lds (revision 2) @@ -0,0 +1,31 @@ +MEMORY +{ + FLASH : ORIGIN = 0x20000000, LENGTH = 16M +} + +SECTIONS +{ + .text : + { + *(.text) + *(.text.*) + } > FLASH + .rodata : + { + *(.rodata) + *(.rodata.*); + } > FLASH + .data : + { + _gp = . + 0x7ff0; /* 0x7ff0 -> middle of 64K area */ + *(.sdata) + *(.data) + } > FLASH + .bss : + { + _bss_start = .; + *(.bss) + *(.sbss) + _bss_end = .; + } > FLASH +} Index: layer2/trunk/sw/common =================================================================== --- layer2/trunk/sw/common (nonexistent) +++ layer2/trunk/sw/common (revision 2)

layer2/trunk/sw/common Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: layer2/trunk/sw =================================================================== --- layer2/trunk/sw (nonexistent) +++ layer2/trunk/sw (revision 2)

layer2/trunk/sw Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: layer2/trunk/xilinx/_ngo/netlist.lst =================================================================== --- layer2/trunk/xilinx/_ngo/netlist.lst (nonexistent) +++ layer2/trunk/xilinx/_ngo/netlist.lst (revision 2) @@ -0,0 +1,2 @@ +C:\Mathias\xrisc\xilinx\layer2.ngc 1335895037 +OK Index: layer2/trunk/xilinx/_ngo =================================================================== --- layer2/trunk/xilinx/_ngo (nonexistent) +++ layer2/trunk/xilinx/_ngo (revision 2)

layer2/trunk/xilinx/_ngo Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: layer2/trunk/xilinx/layer2.xise =================================================================== --- layer2/trunk/xilinx/layer2.xise (nonexistent) +++ layer2/trunk/xilinx/layer2.xise (revision 2) @@ -0,0 +1,502 @@ + + + +

+ + + + + + + + +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: layer2/trunk/xilinx/layer2.ucf =================================================================== --- layer2/trunk/xilinx/layer2.ucf (nonexistent) +++ layer2/trunk/xilinx/layer2.ucf (revision 2) @@ -0,0 +1,136 @@ +# Primary Clock +NET "CLK_I" LOC = C9 | IOSTANDARD = "LVCMOS33" | TNM_NET = CLK_I; +TIMESPEC TS_CLK_I = PERIOD "CLK_I" 20 ns HIGH 50%; + +# VGA Connections +NET "VGA_RED" LOC = H14 |IOSTANDARD = "LVTTL" |DRIVE = 8 |SLEW = FAST; +NET "VGA_GREEN" LOC = H15 |IOSTANDARD = "LVTTL" |DRIVE = 8 |SLEW = FAST; +NET "VGA_BLUE" LOC = G15 |IOSTANDARD = "LVTTL" |DRIVE = 8 |SLEW = FAST; +NET "VGA_HSYNC" LOC = F15 |IOSTANDARD = "LVTTL" |DRIVE = 8 |SLEW = FAST; +NET "VGA_VSYNC" LOC = F14 |IOSTANDARD = "LVTTL" |DRIVE = 8 |SLEW = FAST; + +# Keyboard +NET "PS2_CLK" LOC = G14 |IOSTANDARD = "LVCMOS33" |DRIVE = 8 |SLEW = SLOW; +NET "PS2_DATA" LOC = G13 |IOSTANDARD = "LVCMOS33" |DRIVE = 8 |SLEW = SLOW; + +# RS232 DCE Connections +NET "RS232_DCE_RXD" LOC = "R7" |IOSTANDARD = LVTTL; +NET "RS232_DCE_TXD" LOC = "M14" |IOSTANDARD = LVTTL |DRIVE = 8 |SLEW = SLOW ; + +# LEDS +NET "LED<7>" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; +NET "LED<6>" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; +NET "LED<5>" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; +NET "LED<4>" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; +NET "LED<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; +NET "LED<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; +NET "LED<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; +NET "LED<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; + +# StrataFlash +NET "SF_OE" LOC = "C18" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4; +NET "SF_CE" LOC = "D16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4; +NET "SF_WE" LOC = "D17" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4; +NET "SF_BYTE" LOC = "C17" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4; +#NET "SF_STS" LOC = "B18" | IOSTANDARD = LVCMOS33 | PULLUP; + +NET "SF_A<0>" LOC = "H17" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4; +NET "SF_A<1>" LOC = "J13" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4; +NET "SF_A<2>" LOC = "J12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4; +NET "SF_A<3>" LOC = "J14" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4; +NET "SF_A<4>" LOC = "J15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4; +NET "SF_A<5>" LOC = "J16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4; +NET "SF_A<6>" LOC = "J17" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4; +NET "SF_A<7>" LOC = "K14" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4; +NET "SF_A<8>" LOC = "K15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4; +NET "SF_A<9>" LOC = "K12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4; +NET "SF_A<10>" LOC = "K13" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4; +NET "SF_A<11>" LOC = "L15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4; +NET "SF_A<12>" LOC = "L16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4; +NET "SF_A<13>" LOC = "T18" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4; +NET "SF_A<14>" LOC = "R18" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4; +NET "SF_A<15>" LOC = "T17" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4; +NET "SF_A<16>" LOC = "U18" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4; +NET "SF_A<17>" LOC = "T16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4; +NET "SF_A<18>" LOC = "U15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4; +NET "SF_A<19>" LOC = "V15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4; +NET "SF_A<20>" LOC = "T12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4; +NET "SF_A<21>" LOC = "V13" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4; +NET "SF_A<22>" LOC = "V12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4; +NET "SF_A<23>" LOC = "N11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4; + +NET "SF_D<0>" LOC = "N10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4; +NET "SF_D<1>" LOC = "P10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4; +NET "SF_D<2>" LOC = "R10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4; +NET "SF_D<3>" LOC = "V9" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4; +NET "SF_D<4>" LOC = "U9" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4; +NET "SF_D<5>" LOC = "R9" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4; +NET "SF_D<6>" LOC = "M9" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4; +NET "SF_D<7>" LOC = "N9" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4; + +NET "LCD_RW" LOC = "L17" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2; +NET "LCD_E" LOC = "M18" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2; +NET "SPI_ROM_CS" LOC = "U3" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2; +NET "SPI_ADC_CONV" LOC = "P11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2; +NET "SPI_DAC_CS" LOC = "N8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2; +NET "PF_OE" LOC = "T3" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2; + +# DDR2 +NET "SD_A<12>" LOC = "P2" | IOSTANDARD = SSTL2_I; +NET "SD_A<11>" LOC = "N5" | IOSTANDARD = SSTL2_I; +NET "SD_A<10>" LOC = "T2" | IOSTANDARD = SSTL2_I; +NET "SD_A<9>" LOC = "N4" | IOSTANDARD = SSTL2_I; +NET "SD_A<8>" LOC = "H2" | IOSTANDARD = SSTL2_I; +NET "SD_A<7>" LOC = "H1" | IOSTANDARD = SSTL2_I; +NET "SD_A<6>" LOC = "H3" | IOSTANDARD = SSTL2_I; +NET "SD_A<5>" LOC = "H4" | IOSTANDARD = SSTL2_I; +NET "SD_A<4>" LOC = "F4" | IOSTANDARD = SSTL2_I; +NET "SD_A<3>" LOC = "P1" | IOSTANDARD = SSTL2_I; +NET "SD_A<2>" LOC = "R2" | IOSTANDARD = SSTL2_I; +NET "SD_A<1>" LOC = "R3" | IOSTANDARD = SSTL2_I; +NET "SD_A<0>" LOC = "T1" | IOSTANDARD = SSTL2_I; + +NET "SD_DQ<15>" LOC = "H5" | IOSTANDARD = SSTL2_I; +NET "SD_DQ<14>" LOC = "H6" | IOSTANDARD = SSTL2_I; +NET "SD_DQ<13>" LOC = "G5" | IOSTANDARD = SSTL2_I; +NET "SD_DQ<12>" LOC = "G6" | IOSTANDARD = SSTL2_I; +NET "SD_DQ<11>" LOC = "F2" | IOSTANDARD = SSTL2_I; +NET "SD_DQ<10>" LOC = "F1" | IOSTANDARD = SSTL2_I; +NET "SD_DQ<9>" LOC = "E1" | IOSTANDARD = SSTL2_I; +NET "SD_DQ<8>" LOC = "E2" | IOSTANDARD = SSTL2_I; +NET "SD_DQ<7>" LOC = "M6" | IOSTANDARD = SSTL2_I; +NET "SD_DQ<6>" LOC = "M5" | IOSTANDARD = SSTL2_I; +NET "SD_DQ<5>" LOC = "M4" | IOSTANDARD = SSTL2_I; +NET "SD_DQ<4>" LOC = "M3" | IOSTANDARD = SSTL2_I; +NET "SD_DQ<3>" LOC = "L4" | IOSTANDARD = SSTL2_I; +NET "SD_DQ<2>" LOC = "L3" | IOSTANDARD = SSTL2_I; +NET "SD_DQ<1>" LOC = "L1" | IOSTANDARD = SSTL2_I; +NET "SD_DQ<0>" LOC = "L2" | IOSTANDARD = SSTL2_I; + +NET "SD_BA<0>" LOC = "K5" | IOSTANDARD = SSTL2_I ; +NET "SD_BA<1>" LOC = "K6" | IOSTANDARD = SSTL2_I ; + +NET "SD_CK_N" LOC = "J4" | IOSTANDARD = SSTL2_I ; +NET "SD_CK_P" LOC = "J5" | IOSTANDARD = SSTL2_I ; +NET "SD_CKE" LOC = "K3" | IOSTANDARD = SSTL2_I ; + +NET "SD_CMD<3>" LOC = "K4" | IOSTANDARD = SSTL2_I; # SD_CS +NET "SD_CMD<2>" LOC = "C1" | IOSTANDARD = SSTL2_I; # SC_RAS +NET "SD_CMD<1>" LOC = "C2" | IOSTANDARD = SSTL2_I; # SD_CAS +NET "SD_CMD<0>" LOC = "D1" | IOSTANDARD = SSTL2_I; # SD_WE + +NET "SD_DM<1>" LOC = "J1" | IOSTANDARD = SSTL2_I; # SD_UDM +NET "SD_DM<0>" LOC = "J2" | IOSTANDARD = SSTL2_I; # SD_LDM + +NET "SD_DQS<1>" LOC = "G3" | IOSTANDARD = SSTL2_I; # SD_UDQS +NET "SD_DQS<0>" LOC = "L6" | IOSTANDARD = SSTL2_I; # SD_LDQS + +# Path to allow connection to top DCM connection +#NET "SD_CK_FB" LOC = "B9" | IOSTANDARD = LVCMOS33; + +# Prohibit VREF pins +CONFIG PROHIBIT = D2; +CONFIG PROHIBIT = G4; +CONFIG PROHIBIT = J6; +CONFIG PROHIBIT = L5; +CONFIG PROHIBIT = R4; \ No newline at end of file Index: layer2/trunk/xilinx/clock.vhd =================================================================== --- layer2/trunk/xilinx/clock.vhd (nonexistent) +++ layer2/trunk/xilinx/clock.vhd (revision 2) @@ -0,0 +1,191 @@ +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 13.1 +-- \ \ Application : xaw2vhdl +-- / / Filename : clook.vhd +-- /___/ /\ Timestamp : 04/15/2012 16:20:50 +-- \ \ / \ +-- \___\/\___\ +-- +--Command: xaw2vhdl-intstyle C:/Mathias/xrisc/xilinx/ipcore_dir/clook.xaw -st clook.vhd +--Design Name: clook +--Device: xc3s500e-4fg320 +-- +-- Module clook +-- Generated by Xilinx Architecture Wizard +-- Written for synthesis tool: XST + +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +library UNISIM; +use UNISIM.Vcomponents.ALL; + +entity clook is + port ( U1_CLKIN_IN : in std_logic; + U1_RST_IN : in std_logic; + U1_CLKDV_OUT : out std_logic; + U1_CLKIN_IBUFG_OUT : out std_logic; + U1_CLK0_OUT : out std_logic; + U2_CLK0_OUT : out std_logic; + U2_CLK90_OUT : out std_logic; + U2_LOCKED_OUT : out std_logic); +end clook; + +architecture BEHAVIORAL of clook is + signal GND_BIT : std_logic; + signal U1_CLKDV_BUF : std_logic; + signal U1_CLKFB_IN : std_logic; + signal U1_CLKIN_IBUFG : std_logic; + signal U1_CLK0_BUF : std_logic; + signal U1_LOCKED_INV_IN : std_logic; + signal U2_CLKFB_IN : std_logic; + signal U2_CLKIN_IN : std_logic; + signal U2_CLK0_BUF : std_logic; + signal U2_CLK90_BUF : std_logic; + signal U2_FDS_Q_OUT : std_logic; + signal U2_FD1_Q_OUT : std_logic; + signal U2_FD2_Q_OUT : std_logic; + signal U2_FD3_Q_OUT : std_logic; + signal U2_LOCKED_INV_RST : std_logic; + signal U2_OR3_O_OUT : std_logic; + signal U2_RST_IN : std_logic; +begin + GND_BIT <= '0'; + U1_CLKDV_OUT <= U2_CLKIN_IN; + U1_CLKIN_IBUFG_OUT <= U1_CLKIN_IBUFG; + U1_CLK0_OUT <= U1_CLKFB_IN; + U2_CLK0_OUT <= U2_CLKFB_IN; + DCM_SP_INST1 : DCM_SP + generic map( CLK_FEEDBACK => "1X", + CLKDV_DIVIDE => 2.0, + CLKFX_DIVIDE => 1, + CLKFX_MULTIPLY => 4, + CLKIN_DIVIDE_BY_2 => FALSE, + CLKIN_PERIOD => 20.000, + CLKOUT_PHASE_SHIFT => "NONE", + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", + DFS_FREQUENCY_MODE => "LOW", + DLL_FREQUENCY_MODE => "LOW", + DUTY_CYCLE_CORRECTION => TRUE, + FACTORY_JF => x"C080", + PHASE_SHIFT => 0, + STARTUP_WAIT => FALSE) + port map (CLKFB=>U1_CLKFB_IN, + CLKIN=>U1_CLKIN_IBUFG, + DSSEN=>GND_BIT, + PSCLK=>GND_BIT, + PSEN=>GND_BIT, + PSINCDEC=>GND_BIT, + RST=>U1_RST_IN, + CLKDV=>U1_CLKDV_BUF, + CLKFX=>open, + CLKFX180=>open, + CLK0=>U1_CLK0_BUF, + CLK2X=>open, + CLK2X180=>open, + CLK90=>open, + CLK180=>open, + CLK270=>open, + LOCKED=>U1_LOCKED_INV_IN, + PSDONE=>open, + STATUS=>open); + + DCM_SP_INST2 : DCM_SP + generic map( CLK_FEEDBACK => "1X", + CLKDV_DIVIDE => 2.0, + CLKFX_DIVIDE => 1, + CLKFX_MULTIPLY => 4, + CLKIN_DIVIDE_BY_2 => FALSE, + CLKIN_PERIOD => 40.000, + CLKOUT_PHASE_SHIFT => "NONE", + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", + DFS_FREQUENCY_MODE => "LOW", + DLL_FREQUENCY_MODE => "LOW", + DUTY_CYCLE_CORRECTION => TRUE, + FACTORY_JF => x"C080", + PHASE_SHIFT => 0, + STARTUP_WAIT => FALSE) + port map (CLKFB=>U2_CLKFB_IN, + CLKIN=>U2_CLKIN_IN, + DSSEN=>GND_BIT, + PSCLK=>GND_BIT, + PSEN=>GND_BIT, + PSINCDEC=>GND_BIT, + RST=>U2_RST_IN, + CLKDV=>open, + CLKFX=>open, + CLKFX180=>open, + CLK0=>U2_CLK0_BUF, + CLK2X=>open, + CLK2X180=>open, + CLK90=>U2_CLK90_BUF, + CLK180=>open, + CLK270=>open, + LOCKED=>U2_LOCKED_OUT, + PSDONE=>open, + STATUS=>open); + + U1_CLKDV_BUFG_INST : BUFG + port map (I=>U1_CLKDV_BUF, + O=>U2_CLKIN_IN); + + U1_CLKIN_IBUFG_INST : IBUFG + port map (I=>U1_CLKIN_IN, + O=>U1_CLKIN_IBUFG); + + U1_CLK0_BUFG_INST : BUFG + port map (I=>U1_CLK0_BUF, + O=>U1_CLKFB_IN); + + U1_INV_INST : INV + port map (I=>U1_LOCKED_INV_IN, + O=>U2_LOCKED_INV_RST); + + U2_CLK0_BUFG_INST : BUFG + port map (I=>U2_CLK0_BUF, + O=>U2_CLKFB_IN); + + U2_CLK90_BUFG_INST : BUFG + port map (I=>U2_CLK90_BUF, + O=>U2_CLK90_OUT); + + U2_FDS_INST : FDS + port map (C=>U2_CLKIN_IN, + D=>GND_BIT, + S=>GND_BIT, + Q=>U2_FDS_Q_OUT); + + U2_FD1_INST : FD + port map (C=>U2_CLKIN_IN, + D=>U2_FDS_Q_OUT, + Q=>U2_FD1_Q_OUT); + + U2_FD2_INST : FD + port map (C=>U2_CLKIN_IN, + D=>U2_FD1_Q_OUT, + Q=>U2_FD2_Q_OUT); + + U2_FD3_INST : FD + port map (C=>U2_CLKIN_IN, + D=>U2_FD2_Q_OUT, + Q=>U2_FD3_Q_OUT); + + U2_OR2_INST : OR2 + port map (I0=>U2_LOCKED_INV_RST, + I1=>U2_OR3_O_OUT, + O=>U2_RST_IN); + + U2_OR3_INST : OR3 + port map (I0=>U2_FD3_Q_OUT, + I1=>U2_FD2_Q_OUT, + I2=>U2_FD1_Q_OUT, + O=>U2_OR3_O_OUT); + +end BEHAVIORAL; + + Index: layer2/trunk/xilinx/layer2.vhd =================================================================== --- layer2/trunk/xilinx/layer2.vhd (nonexistent) +++ layer2/trunk/xilinx/layer2.vhd (revision 2) @@ -0,0 +1,332 @@ +-------------------------------------------------------------------------------- +-- layer[2] System-on-a-Chip -- +-------------------------------------------------------------------------------- +-- Copyright (C)2011 Mathias H�rtnagl -- +-- -- +-- This program is free software: you can redistribute it and/or modify -- +-- it under the terms of the GNU General Public License as published by -- +-- the Free Software Foundation, either version 3 of the License, or -- +-- (at your option) any later version. -- +-- -- +-- This program is distributed in the hope that it will be useful, -- +-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- +-- GNU General Public License for more details. -- +-- -- +-- You should have received a copy of the GNU General Public License -- +-- along with this program. If not, see . -- +-------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.iwb.all; +use work.iwbm.all; +use work.icon.all; +use work.icpu.all; +use work.imem.all; +use work.iflash.all; +use work.iddr.all; +use work.ivga.all; +use work.ikeyb.all; +use work.ipit.all; +use work.iuart.all; + +entity layer2 is + port( + CLK_I : in std_logic; + -- Flash + SF_OE : out std_logic; + SF_CE : out std_logic; + SF_WE : out std_logic; + SF_BYTE : out std_logic; + --SF_STS : in std_logic; + SF_A : out std_logic_vector(23 downto 0); + SF_D : inout std_logic_vector(7 downto 0); + PF_OE : out std_logic; + LCD_RW : out std_logic; + LCD_E : out std_logic; + SPI_ROM_CS : out std_logic; + SPI_ADC_CONV : out std_logic; + SPI_DAC_CS : out std_logic; + -- DDR2 + SD_CK_N : out std_logic; + SD_CK_P : out std_logic; + SD_CKE : out std_logic; + SD_BA : out std_logic_vector(1 downto 0); + SD_A : out std_logic_vector(12 downto 0); + SD_CMD : out std_logic_vector(3 downto 0); + SD_DM : out std_logic_vector(1 downto 0); + SD_DQS : inout std_logic_vector(1 downto 0); + SD_DQ : inout std_logic_vector(15 downto 0); + -- VGA + VGA_HSYNC : out std_logic; + VGA_VSYNC : out std_logic; + VGA_RED : out std_logic; + VGA_GREEN : out std_logic; + VGA_BLUE : out std_logic; + -- Keyboard + PS2_CLK : in std_logic; + PS2_DATA : in std_logic; + -- RS-232 Serial Port + RS232_DCE_RXD : in std_logic; + RS232_DCE_TXD : out std_logic; + LED : out std_logic_vector(7 downto 0) + ); +end layer2; + +architecture rtl of layer2 is + + ----------------------------------------------------------------------------- + -- Clocks -- + ----------------------------------------------------------------------------- + component clook + port( + U1_CLKIN_IN : in std_logic; + U1_RST_IN : in std_logic; + U1_CLKDV_OUT : out std_logic; + U1_CLKIN_IBUFG_OUT : out std_logic; + U1_CLK0_OUT : out std_logic; + U2_CLK0_OUT : out std_logic; + U2_CLK90_OUT : out std_logic; + U2_LOCKED_OUT : out std_logic + ); + end component; + + signal clk50MHz : std_logic; -- 50 MHz clock of DCM 1. + signal clk50MHz_BUF : std_logic; -- 50 MHz clock for DCM reset operations. + signal clk25MHz0D : std_logic; -- 25 MHz phase 0 for DDR. + signal clk25MHz90D : std_logic; -- 25 MHz pahse 90 for DDR. + + + ----------------------------------------------------------------------------- + -- Shared Bus -- + ----------------------------------------------------------------------------- + signal ci : cpu_in_t; -- CPU input signals. + signal co : cpu_out_t; -- CPU output signals. + signal mi : master_in_t; -- CPU WB Master input. + signal mo : master_out_t; -- CPU WB Master output. + + signal irq : std_logic_vector(7 downto 0); -- Interrupt vector. + signal pit_intr : std_logic; -- PIT interrupt. + signal key_intr : std_logic; -- Keyboard interrupt. + + signal brami, flasi, ddri, dispi, keybi, piti, uartri, uartti : slave_in_t; + signal bramo, flaso, ddro, dispo, keybo, pito, uartro, uartto : slave_out_t; + + + ----------------------------------------------------------------------------- + -- Global Reset -- + ----------------------------------------------------------------------------- + type rst_state_t is (Setup, Done); + + type rst_t is record + s : rst_state_t; + c : natural range 0 to 3; + end record; + + signal r, rin : rst_t := rst_t'(Setup, 0); + signal rst : std_logic; -- Global reset signal. +begin + + ----------------------------------------------------------------------------- + -- Global Reset -- + ----------------------------------------------------------------------------- + -- Reset for 4 clock cycles at start-up. Something the DCM wishes for. + nsl : process(r) + begin + + rin <= r; + + case r.s is + when Setup => + rst <= '1'; + if r.c = 3 then + rin.c <= 0; + rin.s <= Done; + else + rin.c <= r.c + 1; + end if; + + when Done => + rst <= '0'; + end case; + end process; + + reg : process(clk50MHz_BUF) + begin + if rising_edge(clk50MHz_BUF) then r <= rin; end if; + end process; + + ----------------------------------------------------------------------------- + -- Clocks -- + ----------------------------------------------------------------------------- + mclk: clook port map( + U1_CLKIN_IN => CLK_I, + U1_RST_IN => rst, + U1_CLKDV_OUT => open, + U1_CLKIN_IBUFG_OUT => clk50MHz_BUF, + U1_CLK0_OUT => clk50MHz, + U2_CLK0_OUT => clk25MHz0D, + U2_CLK90_OUT => clk25MHz90D, + U2_LOCKED_OUT => open + ); + + ----------------------------------------------------------------------------- + -- MIPS I Cpu -- + ----------------------------------------------------------------------------- + irq <= key_intr & "000000" & pit_intr; + LED <= irq; + + mips : cpu port map( + ci => ci, + co => co + ); + + ----------------------------------------------------------------------------- + -- Cpu's Wishbone Master -- + ----------------------------------------------------------------------------- + master : wbm port map( + mi => mi, + mo => mo, + -- Non Wishbone Signals + ci => ci, + co => co, + irq => irq + ); + + ----------------------------------------------------------------------------- + -- Block Memory -- + ----------------------------------------------------------------------------- + -- NOTE: The starting point of execution. + ram : mem port map( + si => brami, + so => bramo + ); + + ----------------------------------------------------------------------------- + -- Flash Memory -- + ----------------------------------------------------------------------------- + flas : flash port map( + si => flasi, + so => flaso, + -- Non Wishbone Signals + SF_OE => SF_OE, + SF_CE => SF_CE, + SF_WE => SF_WE, + SF_BYTE => SF_BYTE, + --SF_STS => SF_STS, + SF_A => SF_A, + SF_D => SF_D, + PF_OE => PF_OE, + LCD_RW => LCD_RW, + LCD_E => LCD_E, + SPI_ROM_CS => SPI_ROM_CS, + SPI_ADC_CONV => SPI_ADC_CONV, + SPI_DAC_CS => SPI_DAC_CS + ); + + ----------------------------------------------------------------------------- + -- DDR2 Memory -- + ----------------------------------------------------------------------------- + ddr2 : ddr port map( + si => ddri, + so => ddro, + -- Non Wishbone Signals + clk0 => clk25MHz0D, + clk90 => clk25MHz90D, + SD_CK_N => SD_CK_N, + SD_CK_P => SD_CK_P, + SD_CKE => SD_CKE, + SD_BA => SD_BA, + SD_A => SD_A, + SD_CMD => SD_CMD, + SD_DM => SD_DM, + SD_DQS => SD_DQS, + SD_DQ => SD_DQ + ); + + ----------------------------------------------------------------------------- + -- VGA 100x37 Text Display -- + ----------------------------------------------------------------------------- + disp : vga port map( + si => dispi, + so => dispo, + -- Non Wishbone Signals + VGA_HSYNC => VGA_HSYNC, + VGA_VSYNC => VGA_VSYNC, + VGA_RED => VGA_RED, + VGA_GREEN => VGA_GREEN, + VGA_BLUE => VGA_BLUE + ); + + ----------------------------------------------------------------------------- + -- Keyboard -- + ----------------------------------------------------------------------------- + key : keyb port map( + si => keybi, + so => keybo, + -- Non-Wishbone Signals + PS2_CLK => PS2_CLK, + PS2_DATA => PS2_DATA, + intr => key_intr + ); + + ----------------------------------------------------------------------------- + -- Programmable Intervall Timer -- + ----------------------------------------------------------------------------- + pit0 : pit port map( + si => piti, + so => pito, + -- Non-Wishbone Signals + intr => pit_intr + ); + + ----------------------------------------------------------------------------- + -- RS-232 Receiver -- + ----------------------------------------------------------------------------- + recv : uartr port map( + si => uartri, + so => uartro, + -- Non-Wishbone Signals + RS232_DCE_RXD => RS232_DCE_RXD + ); + + ----------------------------------------------------------------------------- + -- RS-232 Transmitter -- + ----------------------------------------------------------------------------- + send : uartt port map( + si => uartti, + so => uartto, + -- Non-Wishbone Signals + RS232_DCE_TXD => RS232_DCE_TXD + ); + + ----------------------------------------------------------------------------- + -- Shared Bus -- + ----------------------------------------------------------------------------- + sbus : intercon port map( + CLK50_I => clk50MHz, + CLK25_I => clk25MHz0D, + RST_I => rst, + mi => mi, + mo => mo, + brami => brami, + bramo => bramo, + flasi => flasi, + flaso => flaso, + ddri => ddri, + ddro => ddro, + dispi => dispi, + dispo => dispo, + keybi => keybi, + keybo => keybo, + piti => piti, + pito => pito, + uartri => uartri, + uartro => uartro, + uartti => uartti, + uartto => uartto + ); +end rtl; \ No newline at end of file Index: layer2/trunk/xilinx =================================================================== --- layer2/trunk/xilinx (nonexistent) +++ layer2/trunk/xilinx (revision 2)

layer2/trunk/xilinx Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: layer2/trunk/vhdl/intercon/bench/modelsim.ini =================================================================== --- layer2/trunk/vhdl/intercon/bench/modelsim.ini (nonexistent) +++ layer2/trunk/vhdl/intercon/bench/modelsim.ini (revision 2) @@ -0,0 +1,1668 @@ +; Copyright 1991-2011 Mentor Graphics Corporation +; +; All Rights Reserved. +; +; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF +; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. +; + +[Library] +others = C:\Modeltech_pe_edu_10.0d\win32pe_edu/../modelsim.ini +; +; VITAL concerns: +; +; The library ieee contains (among other packages) the packages of the +; VITAL 2000 standard. When a design uses VITAL 2000 exclusively, it should use +; the physical library ieee (recommended), or use the physical library +; vital2000, but not both. The design can use logical library ieee and/or +; vital2000 as long as each of these maps to the same physical library, either +; ieee or vital2000. +; +; A design using the 1995 version of the VITAL packages, whether or not +; it also uses the 2000 version of the VITAL packages, must have logical library +; name ieee mapped to physical library vital1995. (A design cannot use library +; vital1995 directly because some packages in this library use logical name ieee +; when referring to the other packages in the library.) The design source +; should use logical name ieee when referring to any packages there except the +; VITAL 2000 packages. Any VITAL 2000 present in the design must use logical +; name vital2000 (mapped to physical library vital2000) to refer to those +; packages. +; ieee = $MODEL_TECH/../vital1995 +; +; For compatiblity with previous releases, logical library name vital2000 maps +; to library vital2000 (a different library than library ieee, containing the +; same packages). +; A design should not reference VITAL from both the ieee library and the +; vital2000 library because the vital packages are effectively different. +; A design that references both the ieee and vital2000 libraries must have +; both logical names ieee and vital2000 mapped to the same library, either of +; these: +; $MODEL_TECH/../ieee +; $MODEL_TECH/../vital2000 +; +;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release +;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release +;mvc_lib = $MODEL_TECH/../mvc_lib + +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +; Value of 3 or 2008 for VHDL-2008 +VHDL93 = 2008 + +; Ignore VHDL-2008 declaration of REAL_VECTOR in package STANDARD. Default is off. +; ignoreStandardRealVector = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Turn off PSL assertion warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Treat as errors: +; case statement static warnings +; warnings caused by aggregates that are not locally static +; Overrides NoCaseStaticError, NoOthersStaticError settings. +; PedanticErrors = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Perform default binding at compile time. +; Default is to do default binding at load time. +; BindAtCompile = 1; + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +; Run the 0-in compiler on the VHDL source files +; Default is off. +; ZeroIn = 1 + +; Set the options to be passed to the 0-in compiler. +; Default is "". +; ZeroInOptions = "" + +; Set the synthesis prefix to be honored for synthesis pragma recognition. +; Default is "". +; SynthPrefix = "" + +; Ignore synthesis and coverage pragmas with this prefix. +; Default is "". +; IgnorePragmaPrefix = "" + +; Turn on code coverage in VHDL design units. Default is off. +; Coverage = sbceft + +; Turn off code coverage in VHDL subprograms. Default is on. +; CoverageSub = 0 + +; Automatically exclude VHDL case statement OTHERS choice branches. +; This includes OTHERS choices in selected signal assigment statements. +; Default is to not exclude. +; CoverExcludeDefault = 1 + +; Control compiler and VOPT optimizations that are allowed when +; code coverage is on. Refer to the comment for this in the [vlog] area. +; CoverOpt = 3 + +; Turn on or off clkOpt optimization for code coverage. Default is on. +; CoverClkOpt = 1 + +; Turn on or off clkOpt optimization builtins for code coverage. Default is on. +; CoverClkOptBuiltins = 0 + +; Inform code coverage optimizations to respect VHDL 'H' and 'L' +; values on signals in conditions and expressions, and to not automatically +; convert them to '1' and '0'. Default is to not convert. +; CoverRespectHandL = 0 + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a VHDL condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Enable or disable Focused Expression Coverage analysis for conditions and +; expressions. Focused Expression Coverage data is provided by default when +; expression and/or condition coverage is active. +; CoverFEC = 0 + +; Enable or disable UDP Coverage analysis for conditions and expressions. +; UDP Coverage data is provided by default when expression and/or condition +; coverage is active. +; CoverUDP = 0 + +; Enable or disable short circuit evaluation of conditions and expressions when +; condition or expression coverage is active. Short circuit evaluation is enabled +; by default. +; CoverShortCircuit = 0 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Use this directory for compiler temporary files instead of "work/_temp" +; CompilerTempDir = /tmp + +; Set this to cause the compilers to force data to be committed to disk +; when the files are closed. +; SyncCompilerFiles = 1 + +; Add VHDL-AMS declarations to package STANDARD +; Default is not to add +; AmsStandard = 1 + +; Range and length checking will be performed on array indices and discrete +; ranges, and when violations are found within subprograms, errors will be +; reported. Default is to issue warnings for violations, because subprograms +; may not be invoked. +; NoDeferSubpgmCheck = 0 + +; Turn ON detection of FSMs having single bit current state variable. +; FsmSingle = 1 + +; Turn off reset state transitions in FSM. +; FsmResetTrans = 0 + +; Turn ON detection of FSM Implicit Transitions. +; FsmImplicitTrans = 1 + +; Controls whether or not to show immediate assertions with constant expressions +; in GUI/report/UCDB etc. By default, immediate assertions with constant +; expressions are shown in GUI/report/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Controls how VHDL basic identifiers are stored with the design unit. +; Does not make the language case-sensitive, effects only how declarations +; declared with basic identifiers have their names stored and printed +; (examine, etc.). +; Default is to preserve the case as originally depicted in the VHDL source. +; Value of 0 indicates to change basic identifiers to lower case. +; PreserveCase = 0 + +; For Configuration Declarations, controls the effect that USE clauses have +; on visibility inside the configuration items being configured. If 1 +; (the default), then use pre-10.0 behavior. If 0, then for stricter LRM-compliance +; extend the visibility of objects made visible through USE clauses into nested +; component configurations. +; OldVHDLConfigurationVisibility = 0 + +; Allows VHDL configuration declarations to be in a different library from +; the corresponding configured entity. Default is to not allow this for +; stricter LRM-compliance +; SeparateConfigLibrary = 1; + +; Change how subprogram out parameter of type array and record are treated. +; If 1, always initial the out parameter to its default value. +; If 2, do not initialize the out parameter. +; The value 0 indicates use the default for the langauge version being compiled. +; Prior to 10.1 all langauge version did not initialize out composite parameters. +; 10.1 and later files compile with -2008 initialize by default +; InitOutCompositeParam = 0 + +NoDebug = 0 +CheckSynthesis = 0 +NoVitalCheck = 0 +Optimize_1164 = 1 +NoVital = 0 +Quiet = 0 +Show_source = 0 +DisableOpt = 0 +ZeroIn = 0 +CoverageNoSub = 0 +NoCoverage = 1 +CoverCells = 0 +CoverExcludeDefault = 0 +CoverFEC = 1 +CoverShortCircuit = 1 +CoverOpt = 3 +Show_Warning1 = 1 +Show_Warning2 = 1 +Show_Warning3 = 1 +Show_Warning4 = 1 +Show_Warning5 = 1 +[vlog] +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn on `protect compiler directive processing. +; Default is to ignore `protect directives. +; Protect = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn on bad option warning. Default is off. +; Show_BadOptionWarning = 1 + +; Revert back to IEEE 1364-1995 syntax, default is 0 (off). +; vlog95compat = 1 + +; Turn off PSL warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Set the threshold for automatically identifying sparse Verilog memories. +; A memory with depth equal to or more than the sparse memory threshold gets +; marked as sparse automatically, unless specified otherwise in source code +; or by +nosparse commandline option of vlog or vopt. +; The default is 1M. (i.e. memories with depth equal +; to or greater than 1M are marked as sparse) +; SparseMemThreshold = 1048576 + +; Run the 0-in compiler on the Verilog source files +; Default is off. +; ZeroIn = 1 + +; Set the options to be passed to the 0-in compiler. +; Default is "". +; ZeroInOptions = "" + +; Set the synthesis prefix to be honored for synthesis pragma recognition. +; Default is "". +; SynthPrefix = "" + +; Ignore synthesis and coverage pragmas with this prefix. +; Default is "". +; IgnorePragmaPrefix = "" + +; Set the option to treat all files specified in a vlog invocation as a +; single compilation unit. The default value is set to 0 which will treat +; each file as a separate compilation unit as specified in the P1800 draft standard. +; MultiFileCompilationUnit = 1 + +; Turn on code coverage in Verilog design units. Default is off. +; Coverage = sbceft + +; Automatically exclude Verilog case statement default branches. +; Default is to not automatically exclude defaults. +; CoverExcludeDefault = 1 + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a Verilog condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Enable or disable Focused Expression Coverage analysis for conditions and +; expressions. Focused Expression Coverage data is provided by default when +; expression and/or condition coverage is active. +; CoverFEC = 0 + +; Enable or disable UDP Coverage analysis for conditions and expressions. +; UDP Coverage data is provided by default when expression and/or condition +; coverage is active. +; CoverUDP = 0 + +; Enable or disable short circuit evaluation of conditions and expressions when +; condition or expression coverage is active. Short circuit evaluation is enabled +; by default. +; CoverShortCircuit = 0 + + +; Turn on code coverage in VLOG `celldefine modules and modules included +; using vlog -v and -y. Default is off. +; CoverCells = 1 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Control compiler and VOPT optimizations that are allowed when +; code coverage is on. This is a number from 1 to 4, with the following +; meanings (the default is 3): +; 1 -- Turn off all optimizations that affect coverage reports. +; 2 -- Allow optimizations that allow large performance improvements +; by invoking sequential processes only when the data changes. +; This may make major reductions in coverage counts. +; 3 -- In addition, allow optimizations that may change expressions or +; remove some statements. Allow constant propagation. Allow VHDL +; subprogram inlining and VHDL FF recognition. +; 4 -- In addition, allow optimizations that may remove major regions of +; code by changing assignments to built-ins or removing unused +; signals. Change Verilog gates to continuous assignments. +; CoverOpt = 3 + +; Specify the override for the default value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then LRM default +; value of 0 (zero) is used. This is a compile time option. +; SVCrossNumPrintMissingDefault = 0 + +; Setting following to 1 would cause creation of variables which +; would represent the value of Coverpoint expressions. This is used +; in conjunction with "SVCoverpointExprVariablePrefix" option +; in the modelsim.ini +; EnableSVCoverpointExprVariable = 0 + +; Specify the override for the prefix used in forming the variable names +; which represent the Coverpoint expressions. This is used in conjunction with +; "EnableSVCoverpointExprVariable" option of the modelsim.ini +; The default prefix is "expr". +; The variable name is +; variable name => _ +; SVCoverpointExprVariablePrefix = expr + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross option.goal (defined to be 100 in the LRM). +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal" +; in the [vsim] section can override this value. +; SVCovergroupGoalDefault = 100 + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross type_option.goal (defined to be 100 in the LRM) +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal" +; in the [vsim] section can override this value. +; SVCovergroupTypeGoalDefault = 100 + +; Specify the override for the default value of "strobe" option for the +; Covergroup Type. This is a compile time option which forces "strobe" to +; a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). NOTE: This can be overriden by a runtime +; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section. +; SVCovergroupStrobeDefault = 0 + +; Specify the override for the default value of "merge_instances" option for +; the Covergroup Type. This is a compile time option which forces +; "merge_instances" to a user specified default value and supersedes +; SystemVerilog specified default value of '0'(zero). +; SVCovergroupMergeInstancesDefault = 0 + +; Specify the override for the default value of "per_instance" option for the +; Covergroup variables. This is a compile time option which forces "per_instance" +; to a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). +; SVCovergroupPerInstanceDefault = 0 + +; Specify the override for the default value of "get_inst_coverage" option for the +; Covergroup variables. This is a compile time option which forces +; "get_inst_coverage" to a user specified default value and supersedes +; SystemVerilog specified default value of '0'(zero). +; SVCovergroupGetInstCoverageDefault = 0 + +; +; A space separated list of resource libraries that contain precompiled +; packages. The behavior is identical to using the "-L" switch. +; +; LibrarySearchPath = [ ...] +LibrarySearchPath = mtiAvm mtiOvm mtiUvm mtiUPF + +; The behavior is identical to the "-mixedansiports" switch. Default is off. +; MixedAnsiPorts = 1 + +; Enable SystemVerilog 3.1a $typeof() function. Default is off. +; EnableTypeOf = 1 + +; Only allow lower case pragmas. Default is disabled. +; AcceptLowerCasePragmaOnly = 1 + +; Set the maximum depth permitted for a recursive include file nesting. +; IncludeRecursionDepthMax = 5 + +; Turn ON detection of FSMs having single bit current state variable. +; FsmSingle = 1 + +; Turn off reset state transitions in FSM. +; FsmResetTrans = 0 + +; Turn off detections of FSMs having x-assignment. +; FsmXAssign = 0 + +; Turn ON detection of FSM Implicit Transitions. +; FsmImplicitTrans = 1 + +; List of file suffixes which will be read as SystemVerilog. White space +; in extensions can be specified with a back-slash: "\ ". Back-slashes +; can be specified with two consecutive back-slashes: "\\"; +; SVFileExtensions = sv svp svh + +; This setting is the same as the vlog -sv command line switch. +; Enables SystemVerilog features and keywords when true (1). +; When false (0), the rules of IEEE Std 1364-2001 are followed and +; SystemVerilog keywords are ignored. +; Svlog = 0 + +; Prints attribute placed upon SV packages during package import +; when true (1). The attribute will be ignored when this +; entry is false (0). The attribute name is "package_load_message". +; The value of this attribute is a string literal. +; Default is true (1). +; PrintSVPackageLoadingAttribute = 1 + +; Do not show immediate assertions with constant expressions in +; GUI/reports/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/reports/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Controls if untyped parameters that are initialized with values greater +; than 2147483647 are mapped to generics of type INTEGER or ignored. +; If mapped to VHDL Integers, values greater than 2147483647 +; are mapped to negative values. +; Default is to map these parameter to generic of type INTEGER +; ForceUnsignedToVHDLInteger = 1 + +; Enable AMS wreal (wired real) extensions. Default is 0. +; WrealType = 1 + +vlog95compat = 0 +Vlog01Compat = 0 +Svlog = 0 +CoverCells = 0 +CoverExcludeDefault = 0 +CoverFEC = 1 +CoverShortCircuit = 1 +CoverOpt = 3 +OptionFile = C:/Mathias/xrisc/intercon/bench/vlog.opt +Quiet = 0 +Show_source = 0 +Protect = 0 +NoDebug = 0 +Hazard = 0 +UpCase = 0 +DisableOpt = 0 +ZeroIn = 0 +[sccom] +; Enable use of SCV include files and library. Default is off. +; UseScv = 1 + +; Add C++ compiler options to the sccom command line by using this variable. +; CppOptions = -g + +; Use custom C++ compiler located at this path rather than the default path. +; The path should point directly at a compiler executable. +; CppPath = /usr/bin/g++ + +; Enable verbose messages from sccom. Default is off. +; SccomVerbose = 1 + +; sccom logfile. Default is no logfile. +; SccomLogfile = sccom.log + +; Enable use of SC_MS include files and library. Default is off. +; UseScMs = 1 + +[vopt] +; Turn on code coverage in vopt. Default is off. +; Coverage = sbceft + +; Control compiler optimizations that are allowed when +; code coverage is on. Refer to the comment for this in the [vlog] area. +; CoverOpt = 3 + +; Increase or decrease the maximum number of rows allowed in a UDP table +; implementing a vopt condition coverage or expression coverage expression. +; More rows leads to a longer compile time, but more expressions covered. +; CoverMaxUDPRows = 192 + +; Increase or decrease the maximum number of input patterns that are present +; in FEC table. This leads to a longer compile time with more expressions +; covered with FEC metric. +; CoverMaxFECRows = 192 + +; Enable code coverage reporting of code that has been optimized away. +; The default is not to report. +; CoverReportCancelled = 1 + +; Do not show immediate assertions with constant expressions in +; GUI/reports/UCDB etc. By default immediate assertions with constant +; expressions are shown in GUI/reports/UCDB etc. This does not affect +; evaluation of immediate assertions. +; ShowConstantImmediateAsserts = 0 + +; Set the maximum number of iterations permitted for a generate loop. +; Restricting this permits the implementation to recognize infinite +; generate loops. +; GenerateLoopIterationMax = 100000 + +; Set the maximum depth permitted for a recursive generate instantiation. +; Restricting this permits the implementation to recognize infinite +; recursions. +; GenerateRecursionDepthMax = 200 + + +[vsim] +; vopt flow +; Set to turn on automatic optimization of a design. +; Default is on +VoptFlow = 1 + +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = ns + +; Disable certain code coverage exclusions automatically. +; Assertions and FSM are exluded from the code coverage by default +; Set AutoExclusionsDisable = fsm to enable code coverage for fsm +; Set AutoExclusionsDisable = assertions to enable code coverage for assertions +; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions +; Or specify comma or space separated list +;AutoExclusionsDisable = fsm,assertions + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 100 + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 5000 + +; Control PSL and Verilog Assume directives during simulation +; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts +; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts +; SimulateAssumeDirectives = 1 + +; Control the simulation of PSL and SVA +; These switches can be overridden by the vsim command line switches: +; -psl, -nopsl, -sva, -nosva. +; Set SimulatePSL = 0 to disable PSL simulation +; Set SimulatePSL = 1 to enable PSL simulation (default) +; SimulatePSL = 1 +; Set SimulateSVA = 0 to disable SVA simulation +; Set SimulateSVA = 1 to enable concurrent SVA simulation (default) +; SimulateSVA = 1 + +; Directives to license manager can be set either as single value or as +; space separated multi-values: +; vhdl Immediately reserve a VHDL license +; vlog Immediately reserve a Verilog license +; plus Immediately reserve a VHDL and Verilog license +; noqueue Do not wait in the license queue when a license is not available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license (PE ONLY) +; noviewer Disable checkout of msimviewer and vsim-viewer license +; features (PE ONLY) +; noslvhdl Disable checkout of qhsimvh and vsim license features +; noslvlog Disable checkout of qhsimvl and vsimvlog license features +; nomix Disable checkout of msimhdlmix and hdlmix license features +; nolnl Disable checkout of msimhdlsim and hdlsim license features +; mixedonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license +; features +; lnlonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix, +; hdlmix license features +; Single value: +; License = plus +; Multi-value: +; License = noqueue plus + +; Severity level of a VHDL assertion message or of a SystemVerilog immediate assertion +; which will cause a running simulation to stop. +; VHDL assertions and SystemVerilog immediate assertions that occur with the +; given severity or higher will cause a running simulation to stop. +; This value is ignored during elaboration. +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; Message Format conversion specifications: +; %S - Severity Level of message/assertion +; %R - Text of message +; %T - Time of message +; %D - Delta value (iteration number) of Time +; %K - Kind of path: Instance/Region/Signal/Process/Foreign Process/Unknown/Protected +; %i - Instance/Region/Signal pathname with Process name (if available) +; %I - shorthand for one of these: +; " %K: %i" +; " %K: %i File: %F" (when path is not Process or Signal) +; except that the %i in this case does not report the Process name +; %O - Process name +; %P - Instance/Region path without leaf process +; %F - File name +; %L - Line number; if assertion message, then line number of assertion or, if +; assertion is in a subprogram, line from which the call is made +; %u - Design unit name in form library.primary +; %U - Design unit name in form library.primary(secondary) +; %% - The '%' character itself +; +; If specific format for Severity Level is defined, use that format. +; Else, for a message that occurs during elaboration: +; -- Failure/Fatal message in VHDL region that is not a Process, and in +; certain non-VHDL regions, uses MessageFormatBreakLine; +; -- Failure/Fatal message otherwise uses MessageFormatBreak; +; -- Note/Warning/Error message uses MessageFormat. +; Else, for a message that occurs during runtime and triggers a breakpoint because +; of the BreakOnAssertion setting: +; -- if in a VHDL region that is not a Process, uses MessageFormatBreakLine; +; -- otherwise uses MessageFormatBreak. +; Else (a runtime message that does not trigger a breakpoint) uses MessageFormat. +; +; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n" +; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n" +; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" + +; Error File - alternate file for storing error messages +; ErrorFile = error.log + +; Simulation Breakpoint messages +; This flag controls the display of function names when reporting the location +; where the simulator stops because of a breakpoint or fatal error. +; Example with function name: # Break in Process ctr at counter.vhd line 44 +; Example without function name: # Break at counter.vhd line 44 +; Default value is 1. +ShowFunctions = 1 + +; Default radix for all windows and commands. +; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned +DefaultRadix = symbolic + +; VSIM Startup command +; Startup = do startup.do + +; VSIM Shutdown file +; Filename to save u/i formats and configurations. +; ShutdownFile = restart.do +; To explicitly disable auto save: +; ShutdownFile = --disable-auto-save + +; File for saving command transcript +TranscriptFile = transcript + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example: sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Specify a unique path separator for the Signal Spy set of functions. +; The default will be to use the PathSeparator variable. +; Must not be the same character as DatasetSeparator. +; SignalSpyPathSeparator = / + +; Used to control parsing of HDL identifiers input to the tool. +; This includes CLI commands, vsim/vopt/vlog/vcom options, +; string arguments to FLI/VPI/DPI calls, etc. +; If set to 1, accept either Verilog escaped Id syntax or +; VHDL extended id syntax, regardless of source language. +; If set to 0, the syntax of the source language must be used. +; Each identifier in a hierarchical name may need different syntax, +; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or +; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom" +; GenerousIdentifierParsing = 1 + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Disable SystemVerilog assertion messages +; IgnoreSVAInfo = 1 +; IgnoreSVAWarning = 1 +; IgnoreSVAError = 1 +; IgnoreSVAFatal = 1 + +; Do not print any additional information from Severity System tasks. +; Only the message provided by the user is printed along with severity +; information. +; SVAPrintOnlyUserMessage = 1; + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; Control the iteration of events when a VHDL signal is forced to a value +; This flag can be set to honour the signal update event in next iteration, +; the default is to update and propagate in the same iteration. +; ForceSigNextIter = 1 + + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings when changing VHDL constants and generics +; Default is 1 to generate warning messages +; WarnConstantChange = 0 + +; Turn off warnings from accelerated versions of the std_logic_arith, +; std_logic_unsigned, and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from accelerated versions of the IEEE numeric_std +; and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Use old-style (pre-6.6) VHDL FOR generate statement iteration names +; in the design hierarchy. +; This style is controlled by the value of the GenerateFormat +; value described next. Default is to use new-style names, which +; comprise the generate statement label, '(', the value of the generate +; parameter, and a closing ')'. +; Uncomment this to use old-style names. +; OldVhdlForGenNames = 1 + +; Enable changes in VHDL elaboration to allow for Variable Logging +; This trades off simulation performance for the ability to log variables +; efficiently. By default this is disable for maximum simulation performance +; VhdlVariableLogging = 1 + +; Control the format of the old-style VHDL FOR generate statement region +; name for each iteration. Do not quote it. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate statement label; the %d represents the generate parameter value +; at a particular iteration (this is the position number if the generate parameter +; is of an enumeration type). Embedded whitespace is allowed (but discouraged); +; leading and trailing whitespace is ignored. +; Application of the format must result in a unique region name over all +; loop iterations for a particular immediately enclosing scope so that name +; lookup can function properly. The default is %s__%d. +; GenerateFormat = %s__%d + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; Specify gcc compiler used in the compilation of automatically generated DPI exportwrapper. +; Use custom gcc compiler located at this path rather than the default path. +; The path should point directly at a compiler executable. +; DpiCppPath = /bin/gcc + +; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls. +; The term "out-of-the-blue" refers to SystemVerilog export function calls +; made from C functions that don't have the proper context setup +; (as is the case when running under "DPI-C" import functions). +; When this is enabled, one can call a DPI export function +; (but not task) from any C code. +; the setting of this variable can be one of the following values: +; 0 : dpioutoftheblue call is disabled (default) +; 1 : dpioutoftheblue call is enabled, but export call debug support is not available. +; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available. +; DpiOutOfTheBlue = 1 + +; Specify whether continuous assignments are run before other normal priority +; processes scheduled in the same iteration. This event ordering minimizes race +; differences between optimized and non-optimized designs, and is the default +; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set +; ImmediateContinuousAssign to 0. +; The default is 1 (enabled). +; ImmediateContinuousAssign = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Which default VPI object model should the tool conform to? +; The 1364 modes are Verilog-only, for backwards compatibility with older +; libraries, and SystemVerilog objects are not available in these modes. +; +; In the absence of a user-specified default, the tool default is the +; latest available LRM behavior. +; Options for PliCompatDefault are: +; VPI_COMPATIBILITY_VERSION_1364v1995 +; VPI_COMPATIBILITY_VERSION_1364v2001 +; VPI_COMPATIBILITY_VERSION_1364v2005 +; VPI_COMPATIBILITY_VERSION_1800v2005 +; VPI_COMPATIBILITY_VERSION_1800v2008 +; +; Synonyms for each string are also recognized: +; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995) +; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001) +; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005) +; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005) +; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008) + + +; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005 + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions +; DefaultRestartOptions = -force + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Specify whether or not a WLF file should be optimized during +; simulation. If set to 0, the WLF file will not be optimized. +; The default is 1, optimize the WLF file. +; WLFOptimize = 0 + +; Specify the name of the WLF file. +; The default is vsim.wlf +; WLFFilename = vsim.wlf + +; Specify whether to lock the WLF file. +; Locking the file prevents other invocations of ModelSim/Questa tools from +; inadvertently overwriting the WLF file. +; The default is 1, lock the WLF file. +; WLFFileLock = 0 + +; Specify the WLF reader cache size limit for each open WLF file. +; The size is giving in megabytes. A value of 0 turns off the +; WLF cache. +; WLFSimCacheSize allows a different cache size to be set for +; simulation WLF file independent of post-simulation WLF file +; viewing. If WLFSimCacheSize is not set it defaults to the +; WLFCacheSize setting. +; The default WLFCacheSize setting is enabled to 256M per open WLF file. +; WLFCacheSize = 2000 +; WLFSimCacheSize = 500 + +; Specify the WLF file event collapse mode. +; 0 = Preserve all events and event order. (same as -wlfnocollapse) +; 1 = Only record values of logged objects at the end of a simulator iteration. +; (same as -wlfcollapsedelta) +; 2 = Only record values of logged objects at the end of a simulator time step. +; (same as -wlfcollapsetime) +; The default is 1. +; WLFCollapseMode = 0 + +; Specify whether WLF file logging can use threads on multi-processor machines +; if 0, no threads will be used, if 1, threads will be used if the system has +; more than one processor +; WLFUseThreads = 1 + +; Turn on/off undebuggable SystemC type warnings. Default is on. +; ShowUndebuggableScTypeWarning = 0 + +; Turn on/off unassociated SystemC name warnings. Default is off. +; ShowUnassociatedScNameWarning = 1 + +; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off. +; ScShowIeeeDeprecationWarnings = 1 + +; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off. +; ScEnableScSignalWriteCheck = 1 + +; Set SystemC default time unit. +; Set to fs, ps, ns, us, ms, or sec with optional +; prefix of 1, 10, or 100. The default is 1 ns. +; The ScTimeUnit value is honored if it is coarser than Resolution. +; If ScTimeUnit is finer than Resolution, it is set to the value +; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns, +; then the default time unit will be 1 ns. However if Resolution +; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns. +ScTimeUnit = ns + +; Set SystemC sc_main stack size. The stack size is set as an integer +; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or +; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends +; on the amount of data on the sc_main() stack and the memory required +; to succesfully execute the longest function call chain of sc_main(). +ScMainStackSize = 10 Mb + +; Turn on/off execution of remainder of sc_main upon quitting the current +; simulation session. If the cumulative length of sc_main() in terms of +; simulation time units is less than the length of the current simulation +; run upon quit or restart, sc_main() will be in the middle of execution. +; This switch gives the option to execute the remainder of sc_main upon +; quitting simulation. The drawback of not running sc_main till the end +; is memory leaks for objects created by sc_main. If on, the remainder of +; sc_main will be executed ignoring all delays. This may cause the simulator +; to crash if the code in sc_main is dependent on some simulation state. +; Default is on. +ScMainFinishOnQuit = 1 + +; Set the SCV relationship name that will be used to identify phase +; relations. If the name given to a transactor relation matches this +; name, the transactions involved will be treated as phase transactions +ScvPhaseRelationName = mti_phase + +; Customize the vsim kernel shutdown behavior at the end of the simulation. +; Some common causes of the end of simulation are $finish (implicit or explicit), +; sc_stop(), tf_dofinish(), and assertion failures. +; This should be set to "ask", "exit", or "stop". The default is "ask". +; "ask" -- In batch mode, the vsim kernel will abruptly exit. +; In GUI mode, a dialog box will pop up and ask for user confirmation +; whether or not to quit the simulation. +; "stop" -- Cause the simulation to stay loaded in memory. This can make some +; post-simulation tasks easier. +; "exit" -- The simulation will abruptly exit without asking for any confirmation. +; "final" -- Run SystemVerilog final blocks then behave as "stop". +; Note: This variable can be overridden with the vsim "-onfinish" command line switch. +OnFinish = ask + +; Print pending deferred assertion messages. +; Deferred assertion messages may be scheduled after the $finish in the same +; time step. Deferred assertions scheduled to print after the $finish are +; printed before exiting with severity level NOTE since it's not known whether +; the assertion is still valid due to being printed in the active region +; instead of the reactive region where they are normally printed. +; OnFinishPendingAssert = 1; + +; Print "simstats" result +; 0 == do not print simstats +; 1 == print at end of simulation +; 2 == print at end of run +; 3 == print at end of run and end of simulation +; default == 0 +; PrintSimStats = 1 + + +; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages +; AssertFile = assert.log + +; Enable assertion counts. Default is off. +; AssertionCover = 1 + +; Run simulator in assertion debug mode. Default is off. +; AssertionDebug = 1 + +; Turn on/off PSL/SVA/VHDL assertion enable. Default is on. +; AssertionEnable = 0 + +; Set PSL/SVA/VHDL concurrent assertion fail limit. Default is -1. +; Any positive integer, -1 for infinity. +; AssertionLimit = 1 + +; Turn on/off concurrent assertion pass log. Default is off. +; Assertion pass logging is only enabled when assertion is browseable +; and assertion debug is enabled. +; AssertionPassLog = 1 + +; Turn on/off PSL concurrent assertion fail log. Default is on. +; The flag does not affect SVA +; AssertionFailLog = 0 + +; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on. +; AssertionFailLocalVarLog = 0 + +; Set action type for PSL/SVA concurrent assertion fail action. Default is continue. +; 0 = Continue 1 = Break 2 = Exit +; AssertionFailAction = 1 + +; Enable the active thread monitor in the waveform display when assertion debug is enabled. +; AssertionActiveThreadMonitor = 1 + +; Control how many waveform rows will be used for displaying the active threads. Default is 5. +; AssertionActiveThreadMonitorLimit = 5 + +; Assertion thread limit after which assertion would be killed/switched off. +; The default is -1 (unlimited). If the number of threads for an assertion go +; beyond this limit, the assertion would be either switched off or killed. This +; limit applies to only assert directives. +;AssertionThreadLimit = -1 + +; Action to be taken once the assertion thread limit is reached. Default +; is kill. It can have a value of off or kill. In case of kill, all the existing +; threads are terminated and no new attempts are started. In case of off, the +; existing attempts keep on evaluating but no new attempts are started. This +; variable applies to only assert directives. +;AssertionThreadLimitAction = kill + +; Cover thread limit after which cover would be killed/switched off. +; The default is -1 (unlimited). If the number of threads for a cover go +; beyond this limit, the cover would be either switched off or killed. This +; limit applies to only cover directives. +;CoverThreadLimit = -1 + +; Action to be taken once the cover thread limit is reached. Default +; is kill. It can have a value of off or kill. In case of kill, all the existing +; threads are terminated and no new attempts are started. In case of off, the +; existing attempts keep on evaluating but no new attempts are started. This +; variable applies to only cover directives. +;CoverThreadLimitAction = kill + + +; By default immediate assertions do not participate in Assertion Coverage calculations +; unless they are executed. This switch causes all immediate assertions in the design +; to participate in Assertion Coverage calculations, whether attempted or not. +; UnattemptedImmediateAssertions = 0 + +; By default immediate covers participate in Coverage calculations +; whether they are attempted or not. This switch causes all unattempted +; immediate covers in the design to stop participating in Coverage +; calculations. +; UnattemptedImmediateCovers = 0 + +; By default pass action block is not executed for assertions on vacuous +; success. The following variable is provided to enable execution of +; pass action block on vacuous success. The following variable is only effective +; if the user does not disable pass action block execution by using either +; system tasks or CLI. Also there is a performance penalty for enabling +; the following variable. +;AssertionEnableVacuousPassActionBlock = 1 + +; As per strict 1850-2005 PSL LRM, an always property can either pass +; or fail. However, by default, Questa reports multiple passes and +; multiple fails on top always/never property (always/never operator +; is the top operator under Verification Directive). The reason +; being that Questa reports passes and fails on per attempt of the +; top always/never property. Use the following flag to instruct +; Questa to strictly follow LRM. With this flag, all assert/never +; directives will start an attempt once at start of simulation. +; The attempt can either fail, match or match vacuously. +; For e.g. if always is the top operator under assert, the always will +; keep on checking the property at every clock. If the property under +; always fails, the directive will be considered failed and no more +; checking will be done for that directive. A top always property, +; if it does not fail, will show a pass at end of simulation. +; The default value is '0' (i.e. zero is off). For example: +; PslOneAttempt = 1 + +; Specify the number of clock ticks to represent infinite clock ticks. +; This affects eventually!, until! and until_!. If at End of Simulation +; (EOS) an active strong-property has not clocked this number of +; clock ticks then neither pass or fail (vacuous match) is returned +; else respective fail/pass is returned. The default value is '0' (zero) +; which effectively does not check for clock tick condition. For example: +; PslInfinityThreshold = 5000 + +; Control how many thread start times will be preserved for ATV viewing for a given assertion +; instance. Default is -1 (ALL). +; ATVStartTimeKeepCount = -1 + +; Turn on/off code coverage +; CodeCoverage = 0 + +; Count all code coverage condition and expression truth table rows that match. +; CoverCountAll = 1 + +; Turn off automatic inclusion of VHDL integers in toggle coverage. Default +; is to include them. +; ToggleNoIntegers = 1 + +; Set the maximum number of values that are collected for toggle coverage of +; VHDL integers. Default is 100; +; ToggleMaxIntValues = 100 + +; Set the maximum number of values that are collected for toggle coverage of +; Verilog real. Default is 100; +; ToggleMaxRealValues = 100 + +; Turn on automatic inclusion of Verilog integers in toggle coverage, except +; for enumeration types. Default is to include them. +; ToggleVlogIntegers = 0 + +; Turn on automatic inclusion of Verilog real type in toggle coverage, except +; for shortreal types. Default is to not include them. +; ToggleVlogReal = 1 + +; Turn on automatic inclusion of Verilog fixed-size unpacked arrays, VHDL multi-d arrays +; and VHDL arrays-of-arrays in toggle coverage. +; Default is to not include them. +; ToggleFixedSizeArray = 1 + +; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays, +; VHDL multi-d arrays and VHDL arrays-of-arrays that are included for toggle coverage. +; This leads to a longer simulation time with bigger arrays covered with toggle coverage. +; Default is 1024. +; ToggleMaxFixedSizeArray = 1024 + +; Treat Verilog multi-dimensional packed vectors and packed structures as equivalently sized +; one-dimensional packed vectors for toggle coverage. Default is 0. +; TogglePackedAsVec = 0 + +; Treat Verilog enumerated types as equivalently sized one-dimensional packed vectors for +; toggle coverage. Default is 0. +; ToggleVlogEnumBits = 0 + +; Limit the widths of registers automatically tracked for toggle coverage. Default is 128. +; For unlimited width, set to 0. +; ToggleWidthLimit = 128 + +; Limit the counts that are tracked for toggle coverage. When all edges for a bit have +; reached this count, further activity on the bit is ignored. Default is 1. +; For unlimited counts, set to 0. +; ToggleCountLimit = 1 + +; Change the mode of extended toggle coverage. Default is 3. Valid modes are 1, 2 and 3. +; Following is the toggle coverage calculation criteria based on extended toggle mode: +; Mode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z'). +; Mode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'. +; Mode 3: 0L->1H & 1H->0L & all 'Z' transitions. +; ExtendedToggleMode = 3 + +; Enable toggle statistics collection only for ports. Default is 0. +; TogglePortsOnly = 1 + +; Turn on/off all PSL/SVA cover directive enables. Default is on. +; CoverEnable = 0 + +; Turn on/off PSL/SVA cover log. Default is off "0". +; CoverLog = 1 + +; Set "at_least" value for all PSL/SVA cover directives. Default is 1. +; CoverAtLeast = 2 + +; Set "limit" value for all PSL/SVA cover directives. Default is -1. +; Any positive integer, -1 for infinity. +; CoverLimit = 1 + +; Specify the coverage database filename. +; Default is "" (i.e. database is NOT automatically saved on close). +; UCDBFilename = vsim.ucdb + +; Specify the maximum limit for the number of Cross (bin) products reported +; in XML and UCDB report against a Cross. A warning is issued if the limit +; is crossed. Default is zero. vsim switch -cvgmaxrptrhscross can override this +; setting. +; MaxReportRhsSVCrossProducts = 1000 + +; Specify the override for the "auto_bin_max" option for the Covergroups. +; If not specified then value from Covergroup "option" is used. +; SVCoverpointAutoBinMax = 64 + +; Specify the override for the value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then value +; specified in the "option.cross_num_print_missing" is used. This +; is a runtime option. NOTE: This overrides any "cross_num_print_missing" +; value specified by user in source file and any SVCrossNumPrintMissingDefault +; specified in modelsim.ini. +; SVCrossNumPrintMissing = 0 + +; Specify whether to use the value of "cross_num_print_missing" +; option in report and GUI for the Cross in Covergroups. If not specified then +; cross_num_print_missing is ignored for creating reports and displaying +; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing". +; UseSVCrossNumPrintMissing = 0 + +; Specify the threshold of Coverpoint wildcard bin value range size, above which +; a warning will be triggered. The default is 4K -- 12 wildcard bits. +; SVCoverpointWildCardBinValueSizeWarn = 4096 + +; Specify the override for the value of "strobe" option for the +; Covergroup Type. If not specified then value in "type_option.strobe" +; will be used. This is runtime option which forces "strobe" to +; user specified value and supersedes user specified values in the +; SystemVerilog Code. NOTE: This also overrides the compile time +; default value override specified using "SVCovergroupStrobeDefault" +; SVCovergroupStrobe = 0 + +; Override for explicit assignments in source code to "option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault". +; SVCovergroupGoal = 100 + +; Override for explicit assignments in source code to "type_option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "type_option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault". +; SVCovergroupTypeGoal = 100 + +; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage() +; builtin functions, and report. This setting changes the default values of +; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3 +; behavior if explicit assignments are not made on option.get_inst_coverage and +; type_option.merge_instances by the user. There are two vsim command line +; options, -cvg63 and -nocvg63 to override this setting from vsim command line. +; The default value of this variable from release 6.6 onwards is 0. This default +; drives compliance with the clarified behavior in the IEEE 1800-2009 standard. +; SVCovergroup63Compatibility = 0 + +; Enforce the 6.5 default behavior of covergroup get_coverage() builtin +; functions, GUI, and report. This setting changes the default values of +; type_option.merge_instances to ensure the 6.5 default behavior if explicit +; assignments are not made on type_option.merge_instances by the user. +; There are two vsim command line options, -cvgmergeinstances and +; -nocvgmergeinstances to override this setting from vsim command line. +; The default value of this variable from release 6.6 onwards is 0. This default +; drives compliance with the clarified behavior in the IEEE 1800-2009 standard. +; SvCovergroupMergeInstancesDefault = 1 + +; Enable or disable generation of more detailed information about the sampling +; of covergroup, cross, and coverpoints. It provides the details of the number +; of times the covergroup instance and type were sampled, as well as details +; about why covergroup, cross and coverpoint were not covered. A non-zero value +; is to enable this feature. 0 is to disable this feature. Default is 0 +; SVCovergroupSampleInfo = 0 + +; Specify the maximum number of Coverpoint bins in whole design for +; all Covergroups. +; MaxSVCoverpointBinsDesign = 2147483648 + +; Specify maximum number of Coverpoint bins in any instance of a Covergroup +; MaxSVCoverpointBinsInst = 2147483648 + +; Specify the maximum number of Cross bins in whole design for +; all Covergroups. +; MaxSVCrossBinsDesign = 2147483648 + +; Specify maximum number of Cross bins in any instance of a Covergroup +; MaxSVCrossBinsInst = 2147483648 + +; Specify a space delimited list of double quoted TCL style +; regular expressions which will be matched against the text of all messages. +; If any regular expression is found to be contained within any message, the +; status for that message will not be propagated to the UCDB TESTSTATUS. +; If no match is detected, then the status will be propagated to the +; UCDB TESTSTATUS. More than one such regular expression text is allowed, +; and each message text is compared for each regular expression in the list. +; UCDBTestStatusMessageFilter = "Done with Test Bench" "Ignore .* message" + +; Set weight for all PSL/SVA cover directives. Default is 1. +; CoverWeight = 2 + +; Check vsim plusargs. Default is 0 (off). +; 0 = Don't check plusargs +; 1 = Warning on unrecognized plusarg +; 2 = Error and exit on unrecognized plusarg +; CheckPlusargs = 1 + +; Load the specified shared objects with the RTLD_GLOBAL flag. +; This gives global visibility to all symbols in the shared objects, +; meaning that subsequently loaded shared objects can bind to symbols +; in the global shared objects. The list of shared objects should +; be whitespace delimited. This option is not supported on the +; Windows or AIX platforms. +; GlobalSharedObjectList = example1.so example2.so example3.so + +; Run the 0in tools from within the simulator. +; Default is off. +; ZeroIn = 1 + +; Set the options to be passed to the 0in runtime tool. +; Default value set to "". +; ZeroInOptions = "" + +; Initial seed for the random number generator of the root thread (SystemVerilog). +; NOTE: This variable can be overridden with the vsim "-sv_seed" command line switch. +; The default value is 0. +; Sv_Seed = 0 + +; Specify the solver "engine" that vsim will select for constrained random +; generation. +; Valid values are: +; "auto" - automatically select the best engine for the current +; constraint scenario +; "bdd" - evaluate all constraint scenarios using the BDD solver engine +; "act" - evaluate all constraint scenarios using the ACT solver engine +; While the BDD solver engine is generally efficient with constraint scenarios +; involving bitwise logical relationships, the ACT solver engine can exhibit +; superior performance with constraint scenarios involving large numbers of +; random variables related via arithmetic operators (+, *, etc). +; NOTE: This variable can be overridden with the vsim "-solveengine" command +; line switch. +; The default value is "auto". +; SolveEngine = auto + +; Specify if the solver should attempt to ignore overflow/underflow semantics +; for arithmetic constraints (multiply, addition, subtraction) in order to +; improve performance. The "solveignoreoverflow" attribute can be specified on +; a per-call basis to randomize() to override this setting. +; The default value is 0 (overflow/underflow is not ignored). Set to 1 to +; ignore overflow/underflow. +; SolveIgnoreOverflow = 0 + +; Specifies the maximum size that a dynamic array may be resized to by the +; solver. If the solver attempts to resize a dynamic array to a size greater +; than the specified limit, the solver will abort with an error. +; The default value is 2000. A value of 0 indicates no limit. +; SolveArrayResizeMax = 2000 + +; Error message severity when randomize() failure is detected (SystemVerilog). +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; The default is 0 (no error). +; SolveFailSeverity = 0 + +; Enable/disable debug information for randomize() failures. +; NOTE: This variable can be overridden with the vsim "-solvefaildbug" command +; line switch. +; The default is 0 (disabled). Set to 1 to enable. +; SolveFailDebug = 0 + +; Specify the maximum size of the solution graph generated by the BDD solver. +; This value can be used to force the BDD solver to abort the evaluation of a +; complex constraint scenario that cannot be evaluated with finite memory. +; This value is specified in 1000s of nodes. +; The default value is 10000. A value of 0 indicates no limit. +; SolveGraphMaxSize = 10000 + +; Specify the maximum number of evaluations that may be performed on the +; solution graph by the BDD solver. This value can be used to force the BDD +; solver to abort the evaluation of a complex constraint scenario that cannot +; be evaluated in finite time. This value is specified in 10000s of evaluations. +; The default value is 10000. A value of 0 indicates no limit. +; SolveGraphMaxEval = 10000 + +; Specify the maximum number of tests that the ACT solver may evaluate before +; abandoning an attempt to solve a particular constraint scenario. +; The default value is 20000000. A value of 0 indicates no limit. +; SolveACTMaxTests = 20000000 + +; Specify the maximum number of operations that the ACT solver may perform +; before abandoning an attempt to solve a particular constraint scenario. The +; value is specified in 1000000s of operations. The default value is 1000. A +; value of 0 indicates no limit. +; SolveACTMaxOps = 1000 + +; Specify the number of times the ACT solver will retry to evaluate a constraint +; scenario that fails due to the SolveACTMaxTests threshold. +; The default value is 0 (no retry). +; SolveACTRetryCount = 0 + +; SolveSpeculateLevel controls whether or not the solver performs speculation +; during the evaluation of a constraint scenario. +; Speculation is an attempt to partition complex constraint scenarios by +; choosing a 'speculation' subset of the variables and constraints. This +; 'speculation' set is solved independently of the remaining constraints. +; The solver then attempts to solve the remaining variables and constraints +; (the 'dependent' set). If this attempt fails, the solver backs up and +; re-solves the 'speculation' set, then retries the 'dependent' set. +; Valid values are: +; 0 - no speculation +; 1 - enable speculation that maintains LRM specified distribution +; 2 - enable other speculation - may yield non-LRM distribution +; Currently, distribution constraints and solve-before constraints are +; used in selecting the 'speculation' sets for speculation level 1. Non-LRM +; compliant speculation includes random variables in condition expressions. +; The default value is 0. +; SolveSpeculateLevel = 0 + +; By default, when speculation is enabled, the solver first tries to solve a +; constraint scenario *without* speculation. If the solver fails to evaluate +; the constraint scenario (due to time/memory limits) then the solver will +; re-evaluate the constraint scenario with speculation. If SolveSpeculateFirst +; is set to 1, the solver will skip the initial non-speculative attempt to +; evaluate the constraint scenario. (Only applies when SolveSpeculateLevel is +; non-zero) +; The default value is 0. +; SolveSpeculateFirst = 0 + +; Specify the maximum bit width of a variable in a conditional expression that +; may be considered as the basis for "conditional" speculation. (Only applies +; when SolveSpeculateLevel=2) +; The default value is 6. +; SolveSpeculateMaxCondWidth = 6 + +; Specify the maximum number of attempts to solve a speculative set of random +; variables and constraints. Exceeding this limit will cause the solver to +; abandon the current speculative set. (Only applies when SolveSpeculateLevel +; is non-zero) +; The default value is 100. +; SolveSpeculateMaxIterations = 100 + +; Specifies whether to attempt speculation on solve-before constraints or +; distribution constraints first. A value of 0 specifies that solve-before +; constraints are attempted first as the basis for speculative randomization. +; A value of 1 specifies that distribution constraints are attempted first +; as the basis for speculative randomization. +; The default value is 0. +; SolveSpeculateDistFirst = 0 + +; If the non-speculative BDD solver fails to evaluate a constraint scenario +; (due to time/memory limits) then the solver can be instructed to automatically +; re-evaluate the constraint scenario with the ACT solver engine. Set +; SolveACTbeforeSpeculate to 1 to enable this feature. +; The default value is 0 (do not re-evaluate with the ACT solver). +; SolveACTbeforeSpeculate = 0 + +; Use SolveFlags to specify options that will guide the behavior of the +; constraint solver. These options may improve the performance of the +; constraint solver for some testcases, and decrease the performance of the +; constraint solver for others. +; Valid flags are: +; i = disable bit interleaving for >, >=, <, <= constraints (BDD engine) +; n = disable bit interleaving for all constraints (BDD engine) +; r = reverse bit interleaving (BDD engine) +; The default value is "" (no options). +; SolveFlags = + +; Specify random sequence compatiblity with a prior letter release. This +; option is used to get the same random sequences during simulation as +; as a prior letter release. Only prior letter releases (of the current +; number release) are allowed. +; NOTE: Only those random sequence changes due to solver optimizations are +; reverted by this variable. Random sequence changes due to solver bugfixes +; cannot be un-done. +; NOTE: This variable can be overridden with the vsim "-solverev" command +; line switch. +; Default value set to "" (no compatibility). +; SolveRev = + +; Environment variable expansion of command line arguments has been depricated +; in favor shell level expansion. Universal environment variable expansion +; inside -f files is support and continued support for MGC Location Maps provide +; alternative methods for handling flexible pathnames. +; The following line may be uncommented and the value set to 1 to re-enable this +; deprecated behavior. The default value is 0. +; DeprecatedEnvironmentVariableExpansion = 0 + +; Turn on/off collapsing of bus ports in VCD dumpports output +DumpportsCollapse = 1 + +; Location of Multi-Level Verification Component (MVC) installation. +; The default location is the product installation directory. +; MvcHome = $MODEL_TECH/... + +; Initialize SystemVerilog enums using the base type's default value +; instead of the leftmost value. +; EnumBaseInit = 1 + +[lmc] +; The simulator's interface to Logic Modeling's SmartModel SWIFT software +libsm = $MODEL_TECH/libsm.sl +; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT) +; libsm = $MODEL_TECH/libsm.dll +; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700) +; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl +; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) +; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o +; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris) +; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Windows NT) +; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll +; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux) +; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux) +; libswift = $LMC_HOME/lib/linux.lib/libswift.so + +; The simulator's interface to Logic Modeling's hardware modeler SFI software +libhm = $MODEL_TECH/libhm.sl +; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT) +; libhm = $MODEL_TECH/libhm.dll +; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700) +; libsfi = /lib/hp700/libsfi.sl +; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000) +; libsfi = /lib/rs6000/libsfi.a +; Logic Modeling's hardware modeler SFI software (Sun4 Solaris) +; libsfi = /lib/sun4.solaris/libsfi.so +; Logic Modeling's hardware modeler SFI software (Windows NT) +; libsfi = /lib/pcnt/lm_sfi.dll +; Logic Modeling's hardware modeler SFI software (Linux) +; libsfi = /lib/linux/libsfi.so + +[msg_system] +; Change a message severity or suppress a message. +; The format is: = [,...] +; suppress can be used to achieve +nowarn

 functionality








    +; The format is: suppress = ,,[,,...]








    +; Examples:








    +suppress = 8780








    +;   note = 3009








    +;   warning = 3033








    +;   error = 3010,3016








    +;   fatal = 3016,3033








    +;   suppress = 3009,3016,3043








    +;   suppress = 3009,CNNODP,3043,TFMPC








    +;   suppress = 8683,8684








    +; The command verror  can be used to get the complete








    +; description of a message.








    +








    +; Control transcripting of Verilog display system task messages and








    +; PLI/FLI print function call messages.  The system tasks include








    +; $display[bho], $strobe[bho], $monitor[bho], and $write[bho].  They








    +; also include the analogous file I/O tasks that write to STDOUT








    +; (i.e. $fwrite or $fdisplay).  The PLI/FLI calls include io_printf,








    +; vpi_printf, mti_PrintMessage, and mti_PrintFormatted.  The default








    +; is to have messages appear only in the transcript.  The other








    +; settings are to send messages to the wlf file only (messages that








    +; are recorded in the wlf file can be viewed in the MsgViewer) or








    +; to both the transcript and the wlf file.  The valid values are








    +;    tran  {transcript only (default)}








    +;    wlf   {wlf file only}








    +;    both  {transcript and wlf file}








    +; displaymsgmode = tran








    +








    +; Control transcripting of elaboration/runtime messages not








    +; addressed by the displaymsgmode setting.  The default is to








    +; have messages appear in the transcript and recorded in the wlf








    +; file (messages that are recorded in the wlf file can be viewed








    +; in the MsgViewer).  The other settings are to send messages








    +; only to the transcript or only to the wlf file.  The valid








    +; values are








    +;    both  {default}








    +;    tran  {transcript only}








    +;    wlf   {wlf file only}








    +; msgmode = both








    Index: layer2/trunk/vhdl/intercon/bench/icon.do








    ===================================================================








    --- layer2/trunk/vhdl/intercon/bench/icon.do	(nonexistent)








    +++ layer2/trunk/vhdl/intercon/bench/icon.do	(revision 2)








    @@ -0,0 +1,201 @@








    +# == Synopsis








    +# 	 Modelsim simulation configuration file.








    +#








    +# == Usage








    +#	 Loads automatically with 'icon.bat'.








    +#








    +# == Autor








    +#   Mathias H�rtnagl 








    +#








    +# == Copyright








    +#   Copyright (C) 2011  Mathias H�rtnagl








    +#








    +#   This program is free software: you can redistribute it and/or modify








    +#   it under the terms of the GNU General Public License as published by








    +#   the Free Software Foundation, either version 3 of the License, or








    +#   (at your option) any later version.








    +#








    +#   This program is distributed in the hope that it will be useful,








    +#   but WITHOUT ANY WARRANTY; without even the implied warranty of








    +#   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the








    +#   GNU General Public License for more details.








    +#








    +#   You should have received a copy of the GNU General Public License








    +#   along with this program.  If not, see .








    +








    +# reference: http://wiki.tcl.tk/15598








    +proc binfmt1 {k {cnt 8}} {








    +    if {![string is integer $k]} {error "argument is not an integer"}








    +    #Compute minimum number of bits necessary








    +    #This is the integer ceiling of the log of the number to the base 2.








    +    if {$k == 0} {set bits 1} else {set bits [expr int(ceil((log(abs($k)))/(log(2))))]}








    +    if {$bits > $cnt} {set cnt $bits}








    +    #Now compute binary representation








    +    for {set i [expr $cnt -1]} {$i > -1} {incr i -1} {








    +        append s [expr ($k >> $i) & 1]








    +    }








    +    return $s








    + }








    +








    +








    +proc vga {} {








    +   variable line ""








    +   variable elem ""








    +   variable char ""








    +








    +   for {set y 0} {$y < 37} {incr y} {








    +      for {set x 0} {$x < 100} {incr x} {








    +         set char " "








    +         set elem [string range [binfmt1 [examine -radix unsigned -value /tb_icon/disp/video_ram/mem([expr $y*100+$x])] 16] 8 15]








    +         switch $elem {








    +				00100000 {set char "."}








    +				00100001 {set char "!"}








    +				00100010 {set char "\""}








    +				00100011 {set char "#"}








    +				00100100 {set char "\$"}








    +				00100101 {set char "%"}








    +				00100110 {set char "&"}








    +				00100111 {set char "'"}








    +				00101000 {set char "("}








    +				00101001 {set char ")"}








    +				00101010 {set char "*"}








    +				00101011 {set char "+"}








    +				00101100 {set char ","}








    +				00101101 {set char "-"}








    +				00101110 {set char "."}








    +				00101111 {set char "/"}








    +				00110000 {set char "0"}








    +				00110001 {set char "1"}








    +				00110010 {set char "2"}








    +				00110011 {set char "3"}








    +				00110100 {set char "4"}








    +				00110101 {set char "5"}








    +				00110110 {set char "6"}








    +				00110111 {set char "7"}








    +				00111000 {set char "8"}








    +				00111001 {set char "9"}








    +				00111010 {set char ":"}








    +				00111011 {set char ";"}








    +				00111100 {set char "<"}








    +				00111101 {set char "="}








    +				00111110 {set char ">"}








    +				00111111 {set char "?"}








    +				01000000 {set char "@"}








    +				01000001 {set char "A"}








    +				01000010 {set char "B"}








    +				01000011 {set char "C"}








    +				01000100 {set char "D"}








    +				01000101 {set char "E"}








    +				01000110 {set char "F"}








    +				01000111 {set char "G"}








    +				01001000 {set char "H"}








    +				01001001 {set char "I"}








    +				01001010 {set char "J"}








    +				01001011 {set char "K"}








    +				01001100 {set char "L"}








    +				01001101 {set char "M"}








    +				01001110 {set char "N"}








    +				01001111 {set char "O"}








    +				01010000 {set char "P"}








    +				01010001 {set char "Q"}








    +				01010010 {set char "R"}








    +				01010011 {set char "S"}








    +				01010100 {set char "T"}








    +				01010101 {set char "U"}








    +				01010110 {set char "V"}








    +				01010111 {set char "W"}








    +				01011000 {set char "X"}








    +				01011001 {set char "Y"}








    +				01011010 {set char "Z"}








    +				01011011 {set char "\["}








    +				01011100 {set char "\\"}








    +				01011101 {set char "\]"}








    +				01011110 {set char "^"}








    +				01011111 {set char "_"}








    +				01100000 {set char "`"}








    +				01100001 {set char "a"}








    +				01100010 {set char "b"}








    +				01100011 {set char "c"}








    +				01100100 {set char "d"}








    +				01100101 {set char "e"}








    +				01100110 {set char "f"}








    +				01100111 {set char "g"}








    +				01101000 {set char "h"}








    +				01101001 {set char "i"}








    +				01101010 {set char "j"}








    +				01101011 {set char "k"}








    +				01101100 {set char "l"}








    +				01101101 {set char "m"}








    +				01101110 {set char "n"}








    +				01101111 {set char "o"}








    +				01110000 {set char "p"}








    +				01110001 {set char "q"}








    +				01110010 {set char "r"}








    +				01110011 {set char "s"}








    +				01110100 {set char "t"}








    +				01110101 {set char "u"}








    +				01110110 {set char "v"}








    +				01110111 {set char "w"}








    +				01111000 {set char "x"}








    +				01111001 {set char "y"}








    +				01111010 {set char "z"}








    +				01111011 {set char "{"}








    +				01111100 {set char "|"}








    +				01111101 {set char "}"}








    +				01111110 {set char "~"}








    +				01111111 {set char ""}








    +            default  {set char "."}








    +         }








    +         set line [concat $line$char]








    +      }








    +      echo $line








    +      set line ""








    +   }








    +}








    +








    +delete wave *








    +








    +add wave -noupdate -color Gold -label CI -childformat {{/tb_icon/ci.ins -radix hexadecimal} {/tb_icon/ci.dat -radix hexadecimal}} -expand -subitemconfig {/tb_icon/ci.clk {-color #ffffd7d70000 -height 15} /tb_icon/ci.rst {-color #ffffd7d70000 -height 15} /tb_icon/ci.hld {-color #ffffd7d70000 -height 15} /tb_icon/ci.irq {-color #ffffd7d70000 -height 15} /tb_icon/ci.ins {-color #ffffd7d70000 -height 15 -radix hexadecimal} /tb_icon/ci.dat {-color #ffffd7d70000 -height 15 -radix hexadecimal}} /tb_icon/ci








    +add wave -noupdate -color Khaki -label CO -radix hexadecimal -childformat {{/tb_icon/co.iadr -radix hexadecimal} {/tb_icon/co.dadr -radix hexadecimal} {/tb_icon/co.dat -radix hexadecimal} {/tb_icon/co.cp0op -radix hexadecimal} {/tb_icon/co.cp0reg -radix hexadecimal} {/tb_icon/co.a -radix hexadecimal} {/tb_icon/co.b -radix hexadecimal}} -subitemconfig {/tb_icon/co.iadr {-color #f0f0e6e68c8c -height 15 -radix hexadecimal} /tb_icon/co.dadr {-color #f0f0e6e68c8c -height 15 -radix hexadecimal} /tb_icon/co.we {-color #f0f0e6e68c8c -height 15} /tb_icon/co.sel {-color #f0f0e6e68c8c -height 15} /tb_icon/co.dat {-color #f0f0e6e68c8c -height 15 -radix hexadecimal} /tb_icon/co.op {-color #f0f0e6e68c8c -height 15} /tb_icon/co.alu {-color #f0f0e6e68c8c -height 15} /tb_icon/co.rimm {-color #f0f0e6e68c8c -height 15} /tb_icon/co.cp0op {-color #f0f0e6e68c8c -height 15 -radix hexadecimal} /tb_icon/co.cp0reg {-color #f0f0e6e68c8c -height 15 -radix hexadecimal} /tb_icon/co.a {-color #f0f0e6e68c8c -height 15 -radix hexadecimal} /tb_icon/co.b {-color #f0f0e6e68c8c -height 15 -radix hexadecimal}} /tb_icon/co








    +add wave -noupdate -divider -height 30 








    +add wave -noupdate -radix hexadecimal /tb_icon/cpu0/fe/v








    +add wave -noupdate -radix hexadecimal -childformat {{/tb_icon/cpu0/de/v.ec -radix hexadecimal} {/tb_icon/cpu0/de/v.mc -radix hexadecimal} {/tb_icon/cpu0/de/v.wc -radix hexadecimal} {/tb_icon/cpu0/de/v.i -radix hexadecimal}} -subitemconfig {/tb_icon/cpu0/de/v.ec {-height 15 -radix hexadecimal} /tb_icon/cpu0/de/v.mc {-height 15 -radix hexadecimal} /tb_icon/cpu0/de/v.wc {-height 15 -radix hexadecimal} /tb_icon/cpu0/de/v.i {-height 15 -radix hexadecimal}} /tb_icon/cpu0/de/v








    +add wave -noupdate -radix hexadecimal -childformat {{/tb_icon/cpu0/ex/v.cor -radix hexadecimal} {/tb_icon/cpu0/ex/v.mc -radix hexadecimal} {/tb_icon/cpu0/ex/v.wc -radix hexadecimal} {/tb_icon/cpu0/ex/v.rd -radix unsigned} {/tb_icon/cpu0/ex/v.f -radix hexadecimal} {/tb_icon/cpu0/ex/v.str -radix hexadecimal} {/tb_icon/cpu0/ex/v.res -radix hexadecimal}} -subitemconfig {/tb_icon/cpu0/ex/v.cor {-height 15 -radix hexadecimal} /tb_icon/cpu0/ex/v.mc {-height 15 -radix hexadecimal} /tb_icon/cpu0/ex/v.wc {-height 15 -radix hexadecimal} /tb_icon/cpu0/ex/v.rd {-height 15 -radix unsigned} /tb_icon/cpu0/ex/v.f {-height 15 -radix hexadecimal} /tb_icon/cpu0/ex/v.str {-height 15 -radix hexadecimal} /tb_icon/cpu0/ex/v.res {-height 15 -radix hexadecimal}} /tb_icon/cpu0/ex/v








    +add wave -noupdate -radix hexadecimal -childformat {{/tb_icon/cpu0/me/v.wc -radix hexadecimal} {/tb_icon/cpu0/me/v.rd -radix hexadecimal} {/tb_icon/cpu0/me/v.res -radix hexadecimal}} -subitemconfig {/tb_icon/cpu0/me/v.wc {-height 15 -radix hexadecimal} /tb_icon/cpu0/me/v.rd {-height 15 -radix hexadecimal} /tb_icon/cpu0/me/v.res {-height 15 -radix hexadecimal}} /tb_icon/cpu0/me/v








    +add wave -noupdate -childformat {{/tb_icon/cpu0/cp.epc -radix hexadecimal}} -expand -subitemconfig {/tb_icon/cpu0/cp.sr -expand /tb_icon/cpu0/cp.epc {-height 15 -radix hexadecimal}} /tb_icon/cpu0/cp








    +#add wave -noupdate /tb_icon/cpu0/ccp








    +add wave -noupdate -divider -height 30 {CPU MASTER}








    +add wave -noupdate -radix hexadecimal -childformat {{/tb_icon/uut1/r.s -radix hexadecimal} {/tb_icon/uut1/r.i -radix hexadecimal} {/tb_icon/uut1/r.d -radix hexadecimal}} -subitemconfig {/tb_icon/uut1/r.s {-height 15 -radix hexadecimal} /tb_icon/uut1/r.i {-height 15 -radix hexadecimal} /tb_icon/uut1/r.d {-height 15 -radix hexadecimal}} /tb_icon/uut1/r








    +add wave -noupdate -color {Steel Blue} -label MI -childformat {{/tb_icon/mi.dat -radix hexadecimal}} -subitemconfig {/tb_icon/mi.clk {-color #46468282b4b4 -height 15} /tb_icon/mi.rst {-color #46468282b4b4 -height 15} /tb_icon/mi.dat {-color #46468282b4b4 -height 15 -radix hexadecimal} /tb_icon/mi.ack {-color #46468282b4b4 -height 15}} /tb_icon/mi








    +add wave -noupdate -color {Light Steel Blue} -label MO -radix hexadecimal -childformat {{/tb_icon/mo.dat -radix hexadecimal} {/tb_icon/mo.adr -radix hexadecimal}} -subitemconfig {/tb_icon/mo.dat {-color #b0b0c4c4dede -height 15 -radix hexadecimal} /tb_icon/mo.sel {-color #b0b0c4c4dede -height 15} /tb_icon/mo.adr {-color #b0b0c4c4dede -height 15 -radix hexadecimal} /tb_icon/mo.cyc {-color #b0b0c4c4dede -height 15} /tb_icon/mo.stb {-color #b0b0c4c4dede -height 15} /tb_icon/mo.we {-color #b0b0c4c4dede -height 15}} /tb_icon/mo








    +add wave -noupdate -divider -height 30 {MEMORY SLAVE}








    +add wave -noupdate -color {Lime Green} -label SI -radix hexadecimal -childformat {{/tb_icon/brami.dat -radix hexadecimal} {/tb_icon/brami.adr -radix hexadecimal -childformat {{/tb_icon/brami.adr(31) -radix hexadecimal} {/tb_icon/brami.adr(30) -radix hexadecimal} {/tb_icon/brami.adr(29) -radix hexadecimal} {/tb_icon/brami.adr(28) -radix hexadecimal} {/tb_icon/brami.adr(27) -radix hexadecimal} {/tb_icon/brami.adr(26) -radix hexadecimal} {/tb_icon/brami.adr(25) -radix hexadecimal} {/tb_icon/brami.adr(24) -radix hexadecimal} {/tb_icon/brami.adr(23) -radix hexadecimal} {/tb_icon/brami.adr(22) -radix hexadecimal} {/tb_icon/brami.adr(21) -radix hexadecimal} {/tb_icon/brami.adr(20) -radix hexadecimal} {/tb_icon/brami.adr(19) -radix hexadecimal} {/tb_icon/brami.adr(18) -radix hexadecimal} {/tb_icon/brami.adr(17) -radix hexadecimal} {/tb_icon/brami.adr(16) -radix hexadecimal} {/tb_icon/brami.adr(15) -radix hexadecimal} {/tb_icon/brami.adr(14) -radix hexadecimal} {/tb_icon/brami.adr(13) -radix hexadecimal} {/tb_icon/brami.adr(12) -radix hexadecimal} {/tb_icon/brami.adr(11) -radix hexadecimal} {/tb_icon/brami.adr(10) -radix hexadecimal} {/tb_icon/brami.adr(9) -radix hexadecimal} {/tb_icon/brami.adr(8) -radix hexadecimal} {/tb_icon/brami.adr(7) -radix hexadecimal} {/tb_icon/brami.adr(6) -radix hexadecimal} {/tb_icon/brami.adr(5) -radix hexadecimal} {/tb_icon/brami.adr(4) -radix hexadecimal} {/tb_icon/brami.adr(3) -radix hexadecimal} {/tb_icon/brami.adr(2) -radix hexadecimal} {/tb_icon/brami.adr(1) -radix hexadecimal} {/tb_icon/brami.adr(0) -radix hexadecimal}}}} -subitemconfig {/tb_icon/brami.clk {-color #3232cdcd3232 -height 15} /tb_icon/brami.rst {-color #3232cdcd3232 -height 15} /tb_icon/brami.dat {-color #3232cdcd3232 -height 15 -radix hexadecimal} /tb_icon/brami.sel {-color #3232cdcd3232 -height 15} /tb_icon/brami.sel(3) {-color #3232cdcd3232} /tb_icon/brami.sel(2) {-color #3232cdcd3232} /tb_icon/brami.sel(1) {-color #3232cdcd3232} /tb_icon/brami.sel(0) {-color #3232cdcd3232} /tb_icon/brami.adr {-color #3232cdcd3232 -height 15 -radix hexadecimal -childformat {{/tb_icon/brami.adr(31) -radix hexadecimal} {/tb_icon/brami.adr(30) -radix hexadecimal} {/tb_icon/brami.adr(29) -radix hexadecimal} {/tb_icon/brami.adr(28) -radix hexadecimal} {/tb_icon/brami.adr(27) -radix hexadecimal} {/tb_icon/brami.adr(26) -radix hexadecimal} {/tb_icon/brami.adr(25) -radix hexadecimal} {/tb_icon/brami.adr(24) -radix hexadecimal} {/tb_icon/brami.adr(23) -radix hexadecimal} {/tb_icon/brami.adr(22) -radix hexadecimal} {/tb_icon/brami.adr(21) -radix hexadecimal} {/tb_icon/brami.adr(20) -radix hexadecimal} {/tb_icon/brami.adr(19) -radix hexadecimal} {/tb_icon/brami.adr(18) -radix hexadecimal} {/tb_icon/brami.adr(17) -radix hexadecimal} {/tb_icon/brami.adr(16) -radix hexadecimal} {/tb_icon/brami.adr(15) -radix hexadecimal} {/tb_icon/brami.adr(14) -radix hexadecimal} {/tb_icon/brami.adr(13) -radix hexadecimal} {/tb_icon/brami.adr(12) -radix hexadecimal} {/tb_icon/brami.adr(11) -radix hexadecimal} {/tb_icon/brami.adr(10) -radix hexadecimal} {/tb_icon/brami.adr(9) -radix hexadecimal} {/tb_icon/brami.adr(8) -radix hexadecimal} {/tb_icon/brami.adr(7) -radix hexadecimal} {/tb_icon/brami.adr(6) -radix hexadecimal} {/tb_icon/brami.adr(5) -radix hexadecimal} {/tb_icon/brami.adr(4) -radix hexadecimal} {/tb_icon/brami.adr(3) -radix hexadecimal} {/tb_icon/brami.adr(2) -radix hexadecimal} {/tb_icon/brami.adr(1) -radix hexadecimal} {/tb_icon/brami.adr(0) -radix hexadecimal}}} /tb_icon/brami.adr(31) {-color #3232cdcd3232 -radix hexadecimal} /tb_icon/brami.adr(30) {-color #3232cdcd3232 -radix hexadecimal} /tb_icon/brami.adr(29) {-color #3232cdcd3232 -radix hexadecimal} /tb_icon/brami.adr(28) {-color #3232cdcd3232 -radix hexadecimal} /tb_icon/brami.adr(27) {-color #3232cdcd3232 -radix hexadecimal} /tb_icon/brami.adr(26) {-color #3232cdcd3232 -radix hexadecimal} /tb_icon/brami.adr(25) {-color #3232cdcd3232 -radix hexadecimal} /tb_icon/brami.adr(24) {-color #3232cdcd3232 -radix hexadecimal} /tb_icon/brami.adr(23) {-color #3232cdcd3232 -radix hexadecimal} /tb_icon/brami.adr(22) {-color #3232cdcd3232 -radix hexadecimal} /tb_icon/brami.adr(21) {-color #3232cdcd3232 -radix hexadecimal} /tb_icon/brami.adr(20) {-color #3232cdcd3232 -radix hexadecimal} /tb_icon/brami.adr(19) {-color #3232cdcd3232 -radix hexadecimal} /tb_icon/brami.adr(18) {-color #3232cdcd3232 -radix hexadecimal} /tb_icon/brami.adr(17) {-color #3232cdcd3232 -radix hexadecimal} /tb_icon/brami.adr(16) {-color #3232cdcd3232 -radix hexadecimal} /tb_icon/brami.adr(15) {-color #3232cdcd3232 -radix hexadecimal} /tb_icon/brami.adr(14) {-color #3232cdcd3232 -radix hexadecimal} /tb_icon/brami.adr(13) {-color #3232cdcd3232 -radix hexadecimal} /tb_icon/brami.adr(12) {-color #3232cdcd3232 -radix hexadecimal} /tb_icon/brami.adr(11) {-color #3232cdcd3232 -radix hexadecimal} /tb_icon/brami.adr(10) {-color #3232cdcd3232 -radix hexadecimal} /tb_icon/brami.adr(9) {-color #3232cdcd3232 -radix hexadecimal} /tb_icon/brami.adr(8) {-color #3232cdcd3232 -radix hexadecimal} /tb_icon/brami.adr(7) {-color #3232cdcd3232 -radix hexadecimal} /tb_icon/brami.adr(6) {-color #3232cdcd3232 -radix hexadecimal} /tb_icon/brami.adr(5) {-color #3232cdcd3232 -radix hexadecimal} /tb_icon/brami.adr(4) {-color #3232cdcd3232 -radix hexadecimal} /tb_icon/brami.adr(3) {-color #3232cdcd3232 -radix hexadecimal} /tb_icon/brami.adr(2) {-color #3232cdcd3232 -radix hexadecimal} /tb_icon/brami.adr(1) {-color #3232cdcd3232 -radix hexadecimal} /tb_icon/brami.adr(0) {-color #3232cdcd3232 -radix hexadecimal} /tb_icon/brami.cyc {-color #3232cdcd3232 -height 15} /tb_icon/brami.stb {-color #3232cdcd3232 -height 15} /tb_icon/brami.we {-color #3232cdcd3232 -height 15}} /tb_icon/brami








    +add wave -noupdate -color {Green Yellow} -label SO -radix hexadecimal -childformat {{/tb_icon/bramo.dat -radix hexadecimal}} -subitemconfig {/tb_icon/bramo.dat {-color #adadffff2f2f -height 15 -radix hexadecimal} /tb_icon/bramo.ack {-color #adadffff2f2f -height 15}} /tb_icon/bramo








    +add wave -noupdate -divider -height 30 PIT








    +add wave -noupdate /tb_icon/pit0/s








    +add wave -noupdate -radix unsigned /tb_icon/pit0/n








    +








    +TreeUpdate [SetDefaultTree]








    +WaveRestoreCursors {{Cursor 1} {55 ns} 0}








    +configure wave -namecolwidth 150








    +configure wave -valuecolwidth 100








    +configure wave -justifyvalue left








    +configure wave -signalnamewidth 0








    +configure wave -snapdistance 10








    +configure wave -datasetprefix 0








    +configure wave -rowmargin 4








    +configure wave -childrowmargin 2








    +configure wave -gridoffset 0








    +configure wave -gridperiod 1








    +configure wave -griddelta 40








    +configure wave -timeline 1








    +configure wave -timelineunits ns








    +update








    +WaveRestoreZoom {26 ns} {166 ns}








    +








    +# Add memory tabs to the UI








    +#add mem /tb_icon/cpu0/gp/gpr -a decimal -d hexadecimal -wo 1








    +#add mem /tb_icon/mem0/mem(3) -a hexadecimal -d hexadecimal -wo 1








    +#add mem /tb_icon/mem0/mem(2) -a hexadecimal -d hexadecimal -wo 1








    +#add mem /tb_icon/mem0/mem(1) -a hexadecimal -d hexadecimal -wo 1








    +#add mem /tb_icon/mem0/mem(0) -a hexadecimal -d hexadecimal -wo 1








    Index: layer2/trunk/vhdl/intercon/bench/tb_icon.vhd








    ===================================================================








    --- layer2/trunk/vhdl/intercon/bench/tb_icon.vhd	(nonexistent)








    +++ layer2/trunk/vhdl/intercon/bench/tb_icon.vhd	(revision 2)








    @@ -0,0 +1,291 @@








    +--------------------------------------------------------------------------------








    +-- layer[2] Testbench                                                         --








    +--------------------------------------------------------------------------------








    +-- Version: 1.0.0                                                             --








    +-- VHDL:    2002                                                              --








    +-- Sim:     Modelsim 10.0a PE Student Edition                                 --








    +--                                                                            --








    +--------------------------------------------------------------------------------








    +-- Copyright (C)2011  Mathias H�rtnagl          --








    +--                                                                            --








    +-- This program is free software: you can redistribute it and/or modify       --








    +-- it under the terms of the GNU General Public License as published by       --








    +-- the Free Software Foundation, either version 3 of the License, or          --








    +-- (at your option) any later version.                                        --








    +--                                                                            --








    +-- This program is distributed in the hope that it will be useful,            --








    +-- but WITHOUT ANY WARRANTY; without even the implied warranty of             --








    +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the              --








    +-- GNU General Public License for more details.                               --








    +--                                                                            --








    +-- You should have received a copy of the GNU General Public License          --








    +-- along with this program.  If not, see .      --








    +--------------------------------------------------------------------------------








    +library ieee;








    +use ieee.std_logic_1164.all;








    +use ieee.numeric_std.all;








    +








    +library work;








    +use work.iwb.all;








    +use work.iwbm.all;








    +use work.icon.all;








    +use work.icpu.all;








    +use work.imem.all;








    +use work.iflash.all;








    +-- use work.iddr.all;








    +use work.ivga.all;








    +use work.ikeyb.all;








    +use work.ipit.all;








    +use work.iuart.all;








    +








    +entity tb_icon is








    +end tb_icon;








    +








    +architecture tb of tb_icon is








    +








    +   constant SIZE : positive := 11;     -- address bus size








    +   constant BUSS : positive := 32;     -- address bus width








    +   constant GRAN : positive := 8;      -- granularity








    +








    +   signal SF_OE        : std_logic;








    +   signal SF_CE        : std_logic;








    +   signal SF_WE        : std_logic;








    +   signal SF_BYTE      : std_logic;








    +   -- signal SF_STS       : in    std_logic;








    +   signal SF_A         : std_logic_vector(23 downto 0);








    +   signal SF_D         : std_logic_vector(7 downto 0);








    +   signal PF_OE        : std_logic;








    +   signal LCD_RW       : std_logic;








    +   signal LCD_E        : std_logic;








    +   signal SPI_ROM_CS   : std_logic;








    +   signal SPI_ADC_CONV : std_logic;








    +   signal SPI_DAC_CS   : std_logic;








    +








    +   signal SD_CK_N  : std_logic;








    +   signal SD_CK_P  : std_logic;








    +   signal SD_CKE   : std_logic;








    +   signal SD_BA    : std_logic_vector(1 downto 0);








    +   signal SD_A     : std_logic_vector(12 downto 0);








    +   signal SD_CMD   : std_logic_vector(3 downto 0);








    +   signal SD_DM    : std_logic_vector(1 downto 0);








    +   signal SD_DQS   : std_logic_vector(1 downto 0);








    +   signal SD_DQ    : std_logic_vector(15 downto 0);








    +








    +   signal VGA_HSYNC : std_logic;








    +   signal VGA_VSYNC : std_logic;








    +   signal VGA_RED   : std_logic;








    +   signal VGA_GREEN : std_logic;








    +   signal VGA_BLUE  : std_logic;








    +








    +   signal PS2_CLK   : std_logic;








    +   signal PS2_DATA  : std_logic;








    +








    +   signal RS232_DCE_RXD : std_logic;








    +   signal RS232_DCE_TXD : std_logic;








    +








    +   signal ci : cpu_in_t;








    +   signal co : cpu_out_t;








    +   signal mi : master_in_t;








    +   signal mo : master_out_t;








    +








    +   signal irq      : std_logic_vector(7 downto 0);








    +   signal pit_intr : std_logic;








    +








    +   signal brami, flasi, ddri, dispi, keybi, piti, uartri, uartti : slave_in_t;








    +   signal bramo, flaso, ddro, dispo, keybo, pito, uartro, uartto : slave_out_t;








    +








    +   signal LED : std_logic_vector(7 downto 0);








    +








    +   signal CLK50_I : std_logic;








    +   signal CLK25_I : std_logic;








    +   signal CLK25P90_I : std_logic;








    +   constant clk50_period : time := 20 ns;








    +








    +   signal RST_I : std_logic;








    +begin








    +








    +   irq <= "0000000" & pit_intr;








    +








    +   clk50 : process








    +   begin








    +      CLK50_I <= '0';








    +      CLK25_I <= '0';








    +      CLK25P90_I <= '1';








    +      wait for clk50_period / 4;








    +      CLK50_I <= '1';








    +      CLK25_I <= '0';








    +      CLK25P90_I <= '0';








    +      wait for clk50_period / 4;








    +      CLK50_I <= '0';








    +      CLK25_I <= '1';








    +      CLK25P90_I <= '0';








    +      wait for clk50_period / 4;








    +      CLK50_I <= '1';








    +      CLK25_I <= '1';








    +      CLK25P90_I <= '1';








    +      wait for clk50_period / 4;








    +   end process;








    +








    +   -----------------------------------------------------------------------------








    +   -- MIPS I Cpu                                                              --








    +   -----------------------------------------------------------------------------








    +   cpu0 : cpu port map(








    +      ci => ci,








    +      co => co








    +   );








    +








    +   -----------------------------------------------------------------------------








    +   -- Cpu's Wishbone Master                                                   --








    +   -----------------------------------------------------------------------------








    +   uut1 : wbm port map(








    +      ci  => ci,








    +      co  => co,








    +      mi  => mi,








    +      mo  => mo,








    +      LED => LED,








    +      irq => irq








    +   );








    +








    +   -----------------------------------------------------------------------------








    +   -- Block Memory                                                            --








    +   -----------------------------------------------------------------------------








    +   -- NOTE: The starting point of execution.








    +   mem0 : mem








    +      port map(








    +         si => brami,








    +         so => bramo








    +      );








    +








    +   -----------------------------------------------------------------------------








    +   -- Flash Memory                                                            --








    +   -----------------------------------------------------------------------------








    +   flas : flash port map(








    +      si           => flasi,








    +      so           => flaso,








    +   -- Non Wishbone Signals








    +      SF_OE        => SF_OE,








    +      SF_CE        => SF_CE,








    +      SF_WE        => SF_WE,








    +      SF_BYTE      => SF_BYTE,








    +      --SF_STS       => SF_STS,








    +      SF_A         => SF_A,








    +      SF_D         => SF_D,








    +      PF_OE        => PF_OE,








    +      LCD_RW       => LCD_RW,








    +      LCD_E        => LCD_E,








    +      SPI_ROM_CS   => SPI_ROM_CS,








    +      SPI_ADC_CONV => SPI_ADC_CONV,








    +      SPI_DAC_CS   => SPI_DAC_CS








    +   );








    +








    +   -----------------------------------------------------------------------------








    +   -- DDR2 Memory                                                             --








    +   -----------------------------------------------------------------------------








    +   -- ddr2 : ddr port map(








    +      -- si       => ddri,








    +      -- so       => ddro,








    +   --Non Wishbone Signals








    +      -- clk0     => CLK25_I,








    +      -- clk90    => CLK25P90_I,








    +      -- SD_CK_N  => SD_CK_N,








    +      -- SD_CK_P  => SD_CK_P,








    +      -- SD_CKE   => SD_CKE,








    +      -- SD_BA    => SD_BA,








    +      -- SD_A     => SD_A,








    +      -- SD_CMD   => SD_CMD,








    +      -- SD_DM    => SD_DM,








    +      -- SD_DQS   => SD_DQS,








    +      -- SD_DQ    => SD_DQ








    +   -- );








    +








    +   -----------------------------------------------------------------------------








    +   -- VGA 100x37 Text Display                                                 --








    +   -----------------------------------------------------------------------------








    +   disp : vga port map(








    +      si        => dispi,








    +      so        => dispo,








    +   -- Non Wishbone Signals








    +      VGA_HSYNC => VGA_HSYNC,








    +      VGA_VSYNC => VGA_VSYNC,








    +      VGA_RED   => VGA_RED,








    +      VGA_GREEN => VGA_GREEN,








    +      VGA_BLUE  => VGA_BLUE








    +   );








    +








    +   -----------------------------------------------------------------------------








    +   -- Keyboard                                                                --








    +   -----------------------------------------------------------------------------








    +   key : keyb port map(








    +      si        => keybi,








    +      so        => keybo,








    +   -- Non-Wishbone Signals








    +      PS2_CLK   => PS2_CLK,








    +      PS2_DATA  => PS2_DATA,








    +      intr      => open








    +   );








    +








    +   -----------------------------------------------------------------------------








    +   -- Programmable Intervall Timer                                            --








    +   -----------------------------------------------------------------------------








    +   pit0 : pit port map(








    +      si   => piti,








    +      so   => pito,








    +   -- Non-Wishbone Signals








    +      intr => pit_intr








    +   );








    +








    +   -----------------------------------------------------------------------------








    +   -- RS-232 Receiver                                                         --








    +   -----------------------------------------------------------------------------








    +   recv : uartr port map(








    +      si            => uartri,








    +      so            => uartro,








    +   -- Non-Wishbone Signals








    +      RS232_DCE_RXD => RS232_DCE_RXD








    +   );








    +








    +   -----------------------------------------------------------------------------








    +   -- RS-232 Transmitter                                                      --








    +   -----------------------------------------------------------------------------








    +   send : uartt port map(








    +      si            => uartti,








    +      so            => uartto,








    +   -- Non-Wishbone Signals








    +      RS232_DCE_TXD => RS232_DCE_TXD








    +   );








    +








    +   -----------------------------------------------------------------------------








    +   -- Shared Bus                                                              --








    +   -----------------------------------------------------------------------------








    +   sbus : intercon port map(








    +      CLK50_I  => CLK50_I,








    +      CLK25_I  => CLK25_I,








    +      RST_I    => RST_I,








    +      mi       => mi,








    +      mo       => mo,








    +      brami    => brami,








    +      bramo    => bramo,








    +      flasi    => flasi,








    +      flaso    => flaso,








    +      ddri     => ddri,








    +      ddro     => ddro,








    +      dispi    => dispi,








    +      dispo    => dispo,








    +      keybi    => keybi,








    +      keybo    => keybo,








    +      piti     => piti,








    +      pito     => pito,








    +      uartri   => uartri,








    +      uartro   => uartro,








    +      uartti   => uartti,








    +      uartto   => uartto








    +   );








    +








    +   sti : process








    +   begin








    +      RST_I <= '1';








    +      wait for 3*clk50_period/2;








    +      RST_I <= '0';








    +      wait;                            -- Important: no wait, no simulation.








    +   end process;








    +end tb;








    \ No newline at end of file








    Index: layer2/trunk/vhdl/intercon/bench/icon.bat








    ===================================================================








    --- layer2/trunk/vhdl/intercon/bench/icon.bat	(nonexistent)








    +++ layer2/trunk/vhdl/intercon/bench/icon.bat	(revision 2)








    @@ -0,0 +1,33 @@








    +@echo off








    +








    +pushd ..








    +pushd ..








    +set xrisc=%cd%








    +set icon=%xrisc%\intercon








    +set cpu=%xrisc%\cpu\rtl








    +set mem=%xrisc%\mem\rtl








    +set flash=%xrisc%\flash\rtl








    +set ddr=%xrisc%\ddr\rtl








    +set vga=%xrisc%\vga\rtl








    +set keyb=%xrisc%\keyb\rtl








    +set pit=%xrisc%\pit\rtl








    +set uart=%xrisc%\rs232\rtl








    +set rtl=%icon%\rtl








    +set tb=%icon%\bench








    +popd








    +popd








    +








    +echo Compiling testbench for "cpu" ...








    +vlib work








    +vcom %cpu%\mips1.vhd %cpu%\tcpu.vhd %cpu%\icpu.vhd  %cpu%\fcpu.vhd %cpu%\gpr.vhd








    +vcom %cpu%\cpu.vhd %rtl%\iwb.vhd %cpu%\iwbm.vhd %cpu%\wbm.vhd








    +vcom %mem%\imem.vhd %xrisc%\sw\bin\data.vhd %mem%\mem.vhd








    +vcom %flash%\iflash.vhd %flash%\flash.vhd








    +REM vcom %ddr%\iddr.vhd %ddr%\ddr_init.vhd %ddr%\ddr.vhd








    +vcom %vga%\ivga.vhd %vga%\ram.vhd %vga%\rom.vhd %vga%\vga.vhd








    +vcom %keyb%\ikeyb.vhd %keyb%\keyb.vhd








    +vcom %pit%\ipit.vhd %pit%\pit.vhd








    +vcom %uart%\iuart.vhd %uart%\uartr.vhd %uart%\uartt.vhd








    +vcom %rtl%\icon.vhd %rtl%\intercon.vhd %tb%\tb_icon.vhd








    +








    +vsim -do icon.do tb_icon tb








    Index: layer2/trunk/vhdl/intercon/bench








    ===================================================================








    --- layer2/trunk/vhdl/intercon/bench	(nonexistent)








    +++ layer2/trunk/vhdl/intercon/bench	(revision 2)





    
    layer2/trunk/vhdl/intercon/bench














    Property changes :



    Added: bugtraq:number








    ## -0,0 +1 ##








    +true








    \ No newline at end of property








    Index: layer2/trunk/vhdl/intercon/rtl/iwb.vhd








    ===================================================================








    --- layer2/trunk/vhdl/intercon/rtl/iwb.vhd	(nonexistent)








    +++ layer2/trunk/vhdl/intercon/rtl/iwb.vhd	(revision 2)








    @@ -0,0 +1,78 @@








    +--------------------------------------------------------------------------------








    +-- Wishbone Interface                                                         --








    +--------------------------------------------------------------------------------








    +-- The WB interface specification types and some convinience functions.       --








    +-- This definition lacks the CYC and the tag signals.                         --








    +--                                                                            --








    +--------------------------------------------------------------------------------








    +-- Copyright (C)2011  Mathias H�rtnagl          --








    +--                                                                            --








    +-- This program is free software: you can redistribute it and/or modify       --








    +-- it under the terms of the GNU General Public License as published by       --








    +-- the Free Software Foundation, either version 3 of the License, or          --








    +-- (at your option) any later version.                                        --








    +--                                                                            --








    +-- This program is distributed in the hope that it will be useful,            --








    +-- but WITHOUT ANY WARRANTY; without even the implied warranty of             --








    +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the              --








    +-- GNU General Public License for more details.                               --








    +--                                                                            --








    +-- You should have received a copy of the GNU General Public License          --








    +-- along with this program.  If not, see .      --








    +--------------------------------------------------------------------------------








    +library ieee;








    +use ieee.std_logic_1164.all;








    +use ieee.numeric_std.all;








    +








    +package iwb is








    +








    +   -- WB MASTER








    +   type master_out_t is record








    +      dat : std_logic_vector(31 downto 0);   -- DAT_O








    +      sel : std_logic_vector(3 downto 0);    -- SEL_O








    +      adr : std_logic_vector(31 downto 0);   -- ADR_O








    +      stb : std_logic;                       -- STB_O








    +      we  : std_logic;                       -- WE_O








    +   end record;








    +








    +   type master_in_t is record








    +      clk : std_logic;                       -- CLK_I








    +      rst : std_logic;                       -- RST_I








    +      dat : std_logic_vector(31 downto 0);   -- DAT_I








    +      ack : std_logic;                       -- ACK_I








    +   end record;








    +








    +   -- WB SLAVE








    +   type slave_out_t is record








    +      dat : std_logic_vector(31 downto 0);   -- DAT_O








    +      ack : std_logic;                       -- ACK_O








    +   end record;








    +








    +   type slave_in_t is record








    +      clk : std_logic;                       -- CLK_I








    +      rst : std_logic;                       -- RST_I








    +      dat : std_logic_vector(31 downto 0);   -- DAT_I








    +      sel : std_logic_vector(3 downto 0);    -- SEL_I








    +      adr : std_logic_vector(31 downto 0);   -- ADR_I








    +      stb : std_logic;                       -- STB_I








    +      we  : std_logic;                       -- WE_I








    +   end record;








    +








    +   -- Indicates a Wb read or Wb write respectivly.








    +   function wb_read(si : slave_in_t) return boolean;








    +   function wb_write(si : slave_in_t) return boolean;








    +end iwb;








    +








    +package body iwb is








    +








    +   function wb_read(si : slave_in_t) return boolean is








    +   begin








    +      return (si.stb = '1') and (si.we = '0');








    +   end wb_read;








    +








    +   function wb_write(si : slave_in_t) return boolean is








    +   begin








    +      return (si.stb = '1') and (si.we = '1');








    +   end wb_write;








    +








    +end iwb;








    Index: layer2/trunk/vhdl/intercon/rtl/intercon.vhd








    ===================================================================








    --- layer2/trunk/vhdl/intercon/rtl/intercon.vhd	(nonexistent)








    +++ layer2/trunk/vhdl/intercon/rtl/intercon.vhd	(revision 2)








    @@ -0,0 +1,190 @@








    +--------------------------------------------------------------------------------








    +-- Wishbone Shared Bus Intercon                                               --








    +--------------------------------------------------------------------------------








    +-- Copyright (C)2011  Mathias H�rtnagl          --








    +--                                                                            --








    +-- This program is free software: you can redistribute it and/or modify       --








    +-- it under the terms of the GNU General Public License as published by       --








    +-- the Free Software Foundation, either version 3 of the License, or          --








    +-- (at your option) any later version.                                        --








    +--                                                                            --








    +-- This program is distributed in the hope that it will be useful,            --








    +-- but WITHOUT ANY WARRANTY; without even the implied warranty of             --








    +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the              --








    +-- GNU General Public License for more details.                               --








    +--                                                                            --








    +-- You should have received a copy of the GNU General Public License          --








    +-- along with this program.  If not, see .      --








    +--------------------------------------------------------------------------------








    +library ieee;








    +use ieee.std_logic_1164.all;








    +use ieee.numeric_std.all;








    +








    +library work;








    +use work.icon.all;








    +use work.iwb.all;








    +








    +entity intercon is








    +   port(








    +      CLK50_I  : in  std_logic;








    +      CLK25_I  : in  std_logic;








    +      RST_I    : in  std_logic;








    +      mi       : out master_in_t;








    +      mo       : in  master_out_t;








    +      brami    : out slave_in_t;








    +      bramo    : in  slave_out_t;








    +      flasi    : out slave_in_t;








    +      flaso    : in  slave_out_t;








    +      ddri     : out slave_in_t;








    +      ddro     : in  slave_out_t;








    +      dispi    : out slave_in_t;








    +      dispo    : in  slave_out_t;








    +      keybi    : out slave_in_t;








    +      keybo    : in  slave_out_t;








    +      piti     : out slave_in_t;








    +      pito     : in  slave_out_t;








    +      uartri   : out slave_in_t;








    +      uartro   : in  slave_out_t;








    +      uartti   : out slave_in_t;








    +      uartto   : in  slave_out_t








    +   );








    +end intercon;








    +








    +architecture sbus of intercon is








    +








    +   -- Set default slave signals.








    +   function setDefault(mo : master_out_t; CLK, RST : std_logic)








    +   return slave_in_t is








    +      variable v : slave_in_t;








    +   begin








    +      v.clk := CLK;








    +      v.rst := RST;








    +      v.stb := '0';








    +      v.we  := '0';








    +      v.dat := mo.dat;








    +      v.sel := mo.sel;








    +      v.adr := mo.adr;








    +      return v;








    +   end setDefault;








    +








    +begin








    +   mux : process(CLK50_I, RST_I, mo, bramo, dispo, keybo, pito, flaso, uartro,








    +                 uartto, ddro, CLK25_I)








    +








    +      variable padr : std_logic_vector(27 downto 0);








    +   begin








    +      mi.clk <= CLK50_I;








    +      mi.rst <= RST_I;








    +      mi.dat <= (others => '0');








    +








    +      -- NOTE: Set mi.ack = '1' if you want to continue execution outside the








    +      --       valid address space. If set to zero and your programm reads or








    +      --       writes outside the specified addresses the cpu waits infinitly








    +      --       for an acknolege.








    +      mi.ack <= '0';








    +








    +      brami  <= setDefault(mo, CLK50_I, RST_I);








    +      flasi  <= setDefault(mo, CLK50_I, RST_I);








    +      ddri   <= setDefault(mo, CLK50_I, RST_I);








    +      dispi  <= setDefault(mo, CLK50_I, RST_I);








    +      keybi  <= setDefault(mo, CLK50_I, RST_I);








    +      piti   <= setDefault(mo, CLK50_I, RST_I);








    +      uartri <= setDefault(mo, CLK50_I, RST_I);








    +      uartti <= setDefault(mo, CLK50_I, RST_I);








    +








    +      padr := mo.adr(27 downto 0);








    +








    +      case mo.adr(31 downto 28) is








    +








    +         -----------------------------------------------------------------------








    +         -- Block Memory                                                      --








    +         -----------------------------------------------------------------------








    +         when X"0" =>








    +         -- if (padr >= X"0000000") and (padr < X"0004000") then








    +            brami.stb <= mo.stb;








    +            brami.we  <= mo.we;








    +            mi.dat <= bramo.dat;








    +            mi.ack <= bramo.ack;








    +         -- end if;








    +








    +         -----------------------------------------------------------------------








    +         -- Flash Memory                                                      --








    +         -----------------------------------------------------------------------








    +         when X"1" =>








    +            --if (padr >= X"0000000") and (padr < X"1000000") then








    +            flasi.stb <= mo.stb;








    +            flasi.we  <= mo.we;








    +            mi.dat <= flaso.dat;








    +            mi.ack <= flaso.ack;








    +            --end if;








    +








    +         -----------------------------------------------------------------------








    +         -- DDR2 Memory                                                       --








    +         -----------------------------------------------------------------------








    +         when x"2" =>








    +            ddri.stb <= mo.stb;








    +            ddri.we  <= mo.we;








    +            mi.dat <= ddro.dat;








    +            mi.ack <= ddro.ack;








    +








    +         -----------------------------------------------------------------------








    +         -- Peripheral IO                                                     --








    +         -----------------------------------------------------------------------








    +         when X"F" =>








    +








    +            --------------------------------------------------------------------








    +            -- Display                                                        --








    +            --------------------------------------------------------------------








    +            -- 4096 blocks, 16bit per block = 8192 (0x2000)








    +            if (padr >= X"FFF0000") and (padr < X"FFF2000") then








    +               dispi.stb <= mo.stb;








    +               dispi.we  <= mo.we;








    +               mi.dat <= dispo.dat;








    +               mi.ack <= dispo.ack;








    +








    +            -- NOTE: The following addresses are strict. If you try to load or








    +            --       store a halfword or a byte, the addresses obviously do NOT








    +            --       match.








    +            --------------------------------------------------------------------








    +            -- Keyboard                                                       --








    +            --------------------------------------------------------------------








    +            -- 1 block, 32bit, read only








    +            elsif padr = X"FFF3000" then








    +               keybi.stb <= mo.stb;








    +               keybi.we  <= mo.we;








    +               mi.dat <= keybo.dat;








    +               mi.ack <= keybo.ack;








    +








    +            --------------------------------------------------------------------








    +            -- RS-232 Serial Port                                             --








    +            --------------------------------------------------------------------








    +            -- 1 block, 32bit, read only








    +            elsif padr = X"FFF4000" then








    +               uartri.stb <= mo.stb;








    +               uartri.we  <= mo.we;








    +               mi.dat <= uartro.dat;








    +               mi.ack <= uartro.ack;








    +








    +            -- 1 block, 32bit, write only








    +            elsif padr = X"FFF4004" then








    +               uartti.stb <= mo.stb;








    +               uartti.we  <= mo.we;








    +               mi.dat <= uartto.dat;








    +               mi.ack <= uartto.ack;








    +








    +            --------------------------------------------------------------------








    +            -- Timer                                                          --








    +            --------------------------------------------------------------------








    +            -- 1 block, 32bit, r/w








    +            elsif padr = X"FFFF000" then








    +               piti.stb <= mo.stb;








    +               piti.we  <= mo.we;








    +               mi.dat <= pito.dat;








    +               mi.ack <= pito.ack;








    +            end if;








    +








    +         when others =>








    +








    +      end case;








    +   end process;








    +end sbus;








    \ No newline at end of file








    Index: layer2/trunk/vhdl/intercon/rtl/icon.vhd








    ===================================================================








    --- layer2/trunk/vhdl/intercon/rtl/icon.vhd	(nonexistent)








    +++ layer2/trunk/vhdl/intercon/rtl/icon.vhd	(revision 2)








    @@ -0,0 +1,54 @@








    +--------------------------------------------------------------------------------








    +-- Wishbone Shared Bus Intercon                                               --








    +--------------------------------------------------------------------------------








    +-- Copyright (C)2011  Mathias H�rtnagl          --








    +--                                                                            --








    +-- This program is free software: you can redistribute it and/or modify       --








    +-- it under the terms of the GNU General Public License as published by       --








    +-- the Free Software Foundation, either version 3 of the License, or          --








    +-- (at your option) any later version.                                        --








    +--                                                                            --








    +-- This program is distributed in the hope that it will be useful,            --








    +-- but WITHOUT ANY WARRANTY; without even the implied warranty of             --








    +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the              --








    +-- GNU General Public License for more details.                               --








    +--                                                                            --








    +-- You should have received a copy of the GNU General Public License          --








    +-- along with this program.  If not, see .      --








    +--------------------------------------------------------------------------------








    +library ieee;








    +use ieee.std_logic_1164.all;








    +use ieee.numeric_std.all;








    +








    +library work;








    +use work.iwb.all;








    +








    +package icon is








    +








    +   component intercon is








    +      port(








    +         CLK50_I  : in  std_logic;








    +         CLK25_I  : in  std_logic;








    +         RST_I    : in  std_logic;








    +         mi       : out master_in_t;








    +         mo       : in  master_out_t;








    +         brami    : out slave_in_t;








    +         bramo    : in  slave_out_t;








    +         flasi    : out slave_in_t;








    +         flaso    : in  slave_out_t;








    +         ddri     : out slave_in_t;








    +         ddro     : in  slave_out_t;








    +         dispi    : out slave_in_t;








    +         dispo    : in  slave_out_t;








    +         keybi    : out slave_in_t;








    +         keybo    : in  slave_out_t;








    +         piti     : out slave_in_t;








    +         pito     : in  slave_out_t;








    +         uartri   : out slave_in_t;








    +         uartro   : in  slave_out_t;








    +         uartti   : out slave_in_t;








    +         uartto   : in  slave_out_t








    +      );








    +   end component;








    +








    +end icon;








    \ No newline at end of file








    Index: layer2/trunk/vhdl/intercon/rtl








    ===================================================================








    --- layer2/trunk/vhdl/intercon/rtl	(nonexistent)








    +++ layer2/trunk/vhdl/intercon/rtl	(revision 2)
















    
    layer2/trunk/vhdl/intercon/rtl














    Property changes :



    Added: bugtraq:number








    ## -0,0 +1 ##








    +true








    \ No newline at end of property








    Index: layer2/trunk/vhdl/intercon








    ===================================================================








    --- layer2/trunk/vhdl/intercon	(nonexistent)








    +++ layer2/trunk/vhdl/intercon	(revision 2)
















    
    layer2/trunk/vhdl/intercon














    Property changes :



    Added: bugtraq:number








    ## -0,0 +1 ##








    +true








    \ No newline at end of property








    Index: layer2/trunk/vhdl/cpu/rtl/icpu.vhd








    ===================================================================








    --- layer2/trunk/vhdl/cpu/rtl/icpu.vhd	(nonexistent)








    +++ layer2/trunk/vhdl/cpu/rtl/icpu.vhd	(revision 2)








    @@ -0,0 +1,76 @@








    +--------------------------------------------------------------------------------








    +-- MIPS� I CPU                                                                --








    +--------------------------------------------------------------------------------








    +--                                                                            --








    +-- REFERENCES                                                                 --








    +--                                                                            --








    +--  [1] David A. Patterson, John L. Hennessy,                                 --








    +--      Computer Organization and Design, The Hardware/Software Interface,    --








    +--      Morgan Kaufmann; 4 edition (November 10, 2008),                       --








    +--      ISBN 978-0123744937                                                   --








    +--                                                                            --








    +--  [2] IDT R30xx Family Software Reference Manual                            --








    +--      Revision 1.0, �1994 Integrated Device Technology, Inc.                --








    +--  [3] Ion - MIPS(tm) compatible CPU                                         --








    +--                                          --








    +--  [4] Plasma - most MIPS I(TM) opcodes                                      --








    +--                                       --








    +--                                                                            --








    +--------------------------------------------------------------------------------








    +-- Copyright (C)2011  Mathias H�rtnagl          --








    +--                                                                            --








    +-- This program is free software: you can redistribute it and/or modify       --








    +-- it under the terms of the GNU General Public License as published by       --








    +-- the Free Software Foundation, either version 3 of the License, or          --








    +-- (at your option) any later version.                                        --








    +--                                                                            --








    +-- This program is distributed in the hope that it will be useful,            --








    +-- but WITHOUT ANY WARRANTY; without even the implied warranty of             --








    +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the              --








    +-- GNU General Public License for more details.                               --








    +--                                                                            --








    +-- You should have received a copy of the GNU General Public License          --








    +-- along with this program.  If not, see .      --








    +--------------------------------------------------------------------------------








    +library ieee;








    +use ieee.std_logic_1164.all;








    +use ieee.numeric_std.all;








    +








    +library work;








    +use work.mips1.all;








    +use work.tcpu.all;








    +








    +package icpu is








    +








    +   type cpu_in_t is record








    +      clk : std_logic;








    +      rst : std_logic;








    +      hld : std_logic;








    +      irq : std_logic_vector(7 downto 0);








    +      ins : std_logic_vector(31 downto 0);








    +      dat : std_logic_vector(31 downto 0);








    +   end record;








    +








    +   type cpu_out_t is record








    +      iadr : std_logic_vector(31 downto 0);








    +      dadr : std_logic_vector(31 downto 0);








    +      we   : std_logic;








    +      sel  : std_logic_vector(3 downto 0);








    +      dat  : std_logic_vector(31 downto 0);








    +      -- synthesis translate_off








    +         op   : op_t;








    +         alu  : alu_op_t;








    +         rimm : rimm_op_t;








    +         cp0op : cp0_op_t;








    +         cp0reg : cp0_reg_t;








    +      -- synthesis translate_on








    +   end record;








    +








    +   component cpu is








    +      port(








    +         ci : in  cpu_in_t;








    +         co : out cpu_out_t








    +      );








    +   end component;








    +








    +end icpu;








    \ No newline at end of file








    Index: layer2/trunk/vhdl/cpu/rtl/wbm.vhd








    ===================================================================








    --- layer2/trunk/vhdl/cpu/rtl/wbm.vhd	(nonexistent)








    +++ layer2/trunk/vhdl/cpu/rtl/wbm.vhd	(revision 2)








    @@ -0,0 +1,206 @@








    +--------------------------------------------------------------------------------








    +-- MIPS� I CPU - Wishbone Master                                              --








    +--------------------------------------------------------------------------------








    +--                                                                            --








    +-- KNOWN BUGS:                                                                --








    +--                                                                            --








    +--  o The master cause some severe trouble when communicating with slave      --








    +--    interfaces that run on a different frequency than the master itself.    --








    +--       In order to get the DDR to work with a 50 MHz master, I added an     --








    +--    interface solely running at 50 MHz while the remaining DDR controller   --








    +--    runs at 25 MHz.                                                         --








    +--                                                                            --








    +--------------------------------------------------------------------------------








    +-- Copyright (C)2011  Mathias H�rtnagl          --








    +--                                                                            --








    +-- This program is free software: you can redistribute it and/or modify       --








    +-- it under the terms of the GNU General Public License as published by       --








    +-- the Free Software Foundation, either version 3 of the License, or          --








    +-- (at your option) any later version.                                        --








    +--                                                                            --








    +-- This program is distributed in the hope that it will be useful,            --








    +-- but WITHOUT ANY WARRANTY; without even the implied warranty of             --








    +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the              --








    +-- GNU General Public License for more details.                               --








    +--                                                                            --








    +-- You should have received a copy of the GNU General Public License          --








    +-- along with this program.  If not, see .      --








    +--------------------------------------------------------------------------------








    +library ieee;








    +use ieee.std_logic_1164.all;








    +use ieee.numeric_std.all;








    +








    +library work;








    +use work.iwb.all;








    +use work.icpu.all;








    +








    +entity wbm is








    +   port(








    +      mi  : in  master_in_t;








    +      mo  : out master_out_t;








    +   -- Non Wishbone Signals








    +      ci  : out cpu_in_t;








    +      co  : in  cpu_out_t;








    +      irq : in  std_logic_vector(7 downto 0)








    +   );








    +end wbm;








    +








    +architecture rtl of wbm is








    +








    +   type state_t is (Init, I0, I1, I2, D0, D1, D2, Cpu);








    +








    +   type regs_t is








    +   record








    +      s : state_t;








    +      i : std_logic_vector(31 downto 0);








    +      d : std_logic_vector(31 downto 0);








    +   end record;








    +








    +   constant regs_d : regs_t :=








    +      regs_t'( Init, (others => '0'), (others => '0') );








    +








    +   signal r, rin : regs_t := regs_d;








    +begin








    +








    +   ci.clk <= mi.clk;








    +   ci.rst <= mi.rst;








    +








    +   process(irq, r, co, mi.ack, mi.dat)








    +








    +      variable t2 : std_logic_vector(31 downto 0);








    +   begin








    +








    +      rin <= r;








    +








    +      t2 := (others => '0');








    +








    +      ci.hld <= '1';








    +      ci.ins <= (others => '0');       -- AREA: (others => '-');








    +      ci.dat <= (others => '0');       -- AREA: (others => '-');








    +      ci.irq <= irq;








    +








    +      mo.adr <= (others => '0');       -- AREA: (others => '-');








    +      mo.dat <= (others => '0');       -- AREA: (others => '-');








    +      mo.we  <= '0';








    +      mo.sel <= (others => '0');








    +      mo.stb <= '0';








    +








    +      case r.s is








    +








    +         when Init =>








    +            rin.s <= I0;








    +








    +         -----------------------------------------------------------------------








    +         -- Instruction                                                       --








    +         -----------------------------------------------------------------------








    +         -- First stage of instruction fetch. Wait for memory device to be done








    +         -- loading desired data.








    +         when I0 =>








    +            mo.adr <= co.iadr;








    +            mo.sel <= "1111";








    +            mo.stb <= '1';








    +            if mi.ack = '1' then








    +               --rin.i <= mi.dat;








    +               rin.s <= I1;








    +            end if;








    +








    +         -- Latch fetched instruction.








    +         -- If co.sel is not null, there is data to be processed from the memory








    +         -- stage. Else directly execute instruction.








    +         when I1 =>








    +            mo.adr <= co.iadr;








    +            mo.sel <= "1111";








    +            mo.stb <= '1';








    +            rin.i  <= mi.dat;








    +            rin.s  <= I2;








    +








    +         when I2 =>








    +            if mi.ack = '0' then








    +               if co.sel = x"0" then








    +                  rin.s <= Cpu;








    +               else








    +                  rin.s <= D0;








    +               end if;








    +            end if;








    +








    +         -----------------------------------------------------------------------








    +         -- Data                                                              --








    +         -----------------------------------------------------------------------








    +         -- Set data to be written to propper location on the 32bit bus,








    +         -- according to co.sel.








    +         -- Wait until I/O device is ready.








    +         when D0 =>








    +            mo.adr <= co.dadr;








    +            case co.sel is








    +               when "0001" => mo.dat(7 downto 0)   <= co.dat(7 downto 0);








    +               when "0010" => mo.dat(15 downto 8)  <= co.dat(7 downto 0);








    +               when "0100" => mo.dat(23 downto 16) <= co.dat(7 downto 0);








    +               when "1000" => mo.dat(31 downto 24) <= co.dat(7 downto 0);








    +               when "0011" => mo.dat(15 downto 0)  <= co.dat(15 downto 0);








    +               when "1100" => mo.dat(31 downto 16) <= co.dat(15 downto 0);








    +               when others => mo.dat               <= co.dat;








    +            end case;








    +            mo.we  <= co.we;








    +            mo.sel <= co.sel;








    +            mo.stb <= '1';








    +            if mi.ack = '1' then








    +               rin.s <= D1;








    +            end if;








    +








    +         -- Finish write cycle or latch read data.








    +         when D1 =>








    +            mo.adr <= co.dadr;








    +








    +            -- Read.








    +            case co.sel is








    +               when "0001" => t2(7 downto 0)  := mi.dat(7 downto 0);








    +               when "0010" => t2(7 downto 0)  := mi.dat(15 downto 8);








    +               when "0100" => t2(7 downto 0)  := mi.dat(23 downto 16);








    +               when "1000" => t2(7 downto 0)  := mi.dat(31 downto 24);








    +               when "0011" => t2(15 downto 0) := mi.dat(15 downto 0);








    +               when "1100" => t2(15 downto 0) := mi.dat(31 downto 16);








    +               when others => t2              := mi.dat;








    +            end case;








    +








    +            -- Write.








    +            case co.sel is








    +               when "0001" => mo.dat(7 downto 0)   <= co.dat(7 downto 0);








    +               when "0010" => mo.dat(15 downto 8)  <= co.dat(7 downto 0);








    +               when "0100" => mo.dat(23 downto 16) <= co.dat(7 downto 0);








    +               when "1000" => mo.dat(31 downto 24) <= co.dat(7 downto 0);








    +               when "0011" => mo.dat(15 downto 0)  <= co.dat(15 downto 0);








    +               when "1100" => mo.dat(31 downto 16) <= co.dat(15 downto 0);








    +               when others => mo.dat               <= co.dat;








    +            end case;








    +








    +            mo.we  <= co.we;








    +            mo.sel <= co.sel;








    +            mo.stb <= '1';








    +            rin.d  <= t2;








    +            rin.s  <= D2;








    +








    +         when D2 =>








    +            if mi.ack = '0' then








    +               rin.s <= Cpu;








    +            end if;








    +








    +         -----------------------------------------------------------------------








    +         -- Run CPU                                                           --








    +         -----------------------------------------------------------------------








    +         -- Enable CPU and run it for one cycle, then at least fetch the next








    +         -- instruction.








    +         when Cpu =>








    +            ci.hld <= '0';








    +            ci.ins <= r.i;








    +            ci.dat <= r.d;








    +            rin.s  <= I0;








    +      end case;








    +   end process;








    +








    +   reg : process(mi.clk)








    +   begin








    +      if rising_edge(mi.clk) then








    +         if mi.rst = '1' then r <= regs_d; else r <= rin; end if;








    +      end if;








    +   end process;








    +end architecture;








    \ No newline at end of file








    Index: layer2/trunk/vhdl/cpu/rtl/cpu.vhd








    ===================================================================








    --- layer2/trunk/vhdl/cpu/rtl/cpu.vhd	(nonexistent)








    +++ layer2/trunk/vhdl/cpu/rtl/cpu.vhd	(revision 2)








    @@ -0,0 +1,683 @@








    +--------------------------------------------------------------------------------








    +-- MIPS� I CPU                                                                --








    +--------------------------------------------------------------------------------








    +--                                                                            --








    +-- POSSIBLE FAULTS                                                            --








    +--                                                                            --








    +--  o The upper 4bits of a branch/jump instruction depend on the PC of the    --








    +--    branch delay slot. This special case has not been tested:               --








    +--                                                                            --








    +--                      PC           INSTRUCTION                              --








    +--                    +------------+-----------------+                        --








    +--                    | 0x0fffffff | some branch OP  |                        --








    +--                    | 0x10000000 | ADD $s1, $s1, 1 |                        --








    +--                    +------------+-----------------+                        --








    +--                                                                            --








    +--    Whenever the upper 4 PC bits of the jump instruction differs from the   --








    +--    delay slot instruction address, there might be a chance of incorrect    --








    +--    behavoir.                                                               --








    +--                                                                            --








    +--  o Interrupts are still experimental.                                      --








    +--                                                                            --








    +--------------------------------------------------------------------------------








    +-- Copyright (C)2011  Mathias H�rtnagl          --








    +--                                                                            --








    +-- This program is free software: you can redistribute it and/or modify       --








    +-- it under the terms of the GNU General Public License as published by       --








    +-- the Free Software Foundation, either version 3 of the License, or          --








    +-- (at your option) any later version.                                        --








    +--                                                                            --








    +-- This program is distributed in the hope that it will be useful,            --








    +-- but WITHOUT ANY WARRANTY; without even the implied warranty of             --








    +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the              --








    +-- GNU General Public License for more details.                               --








    +--                                                                            --








    +-- You should have received a copy of the GNU General Public License          --








    +-- along with this program.  If not, see .      --








    +--------------------------------------------------------------------------------








    +library ieee;








    +use ieee.std_logic_1164.all;








    +use ieee.numeric_std.all;








    +








    +library work;








    +use work.mips1.all;








    +use work.tcpu.all;








    +use work.icpu.all;








    +use work.fcpu.all;








    +








    +








    +entity cpu is








    +   port(








    +      ci : in  cpu_in_t;








    +      co : out cpu_out_t








    +   );








    +end cpu;








    +








    +architecture rtl of cpu is








    +








    +   signal f, fin     : fe_t;        -- FE: [FETCH STAGE]








    +   signal d, din     : de_t;        -- DE: [DECODE STAGE]








    +   signal e, ein     : ex_t;        -- EX: [EXECUTION STAGE]








    +   signal m, min     : me_t;        -- ME: [MEMORY STAGE]








    +   signal cp, cpin   : cp0_t;       -- Coprocessor 0 registers








    +








    +   -- Interrupt related signals.








    +   signal intr_bd    : boolean;              -- Branch delay flag.








    +   signal intr_bdd   : boolean;              -- Branch delay delay flag.








    +   signal intr_im    : std_logic_vector(7 downto 0);  -- Interrupt mask.








    +   signal intr_iec   : std_logic;            -- IEc: Interrupt enable current.








    +   signal intr_iep   : std_logic;            -- IEp: Interrupt enable previous.








    +   signal intr_ieo   : std_logic;            -- IEo: Interrupt enable old.








    +








    +   -- Aliases for the instruction's GPR RS and RT addresses.








    +   alias rs_a : std_logic_vector(4 downto 0) is ci.ins(25 downto 21);








    +   alias rt_a : std_logic_vector(4 downto 0) is ci.ins(20 downto 16);








    +








    +   signal rs_o, rt_o : std_logic_vector(31 downto 0);   -- GPR output data.








    +begin








    +








    +   -----------------------------------------------------------------------------








    +   -- FETCH STAGE                                                             --








    +   -----------------------------------------------------------------------------








    +   fe : process(f.pc, ci.irq, e.f, d.cc, cp.epc, cp.sr, intr_bd, intr_im,








    +                intr_iec, intr_iep, intr_ieo)








    +








    +      --------------------------------------------------------------------------








    +      -- EPC Address                                                          --








    +      --------------------------------------------------------------------------








    +      -- SETTING: Interrupt handler routine address.








    +      constant INTR_ADR : unsigned(31 downto 0) := x"200000c0";








    +








    +      variable v : fe_t;








    +      variable c : cp0_t;








    +








    +      variable intr : boolean;








    +   begin








    +      v := f;








    +      c := cp;








    +








    +      -- Address of the next instruction to be fetched.








    +      co.iadr <= std_logic_vector(f.pc) & "00";








    +








    +      -- Program Counter








    +      -- if e.f.jmp = '1' then








    +         -- v.pc := e.f.j;








    +      -- else if d.f.jmp = '1' then








    +         -- v.pc := d.f.j;








    +      -- else








    +         -- v.pc := f.pc + 1;








    +      -- end if;








    +








    +      -- Program Counter








    +      if e.f.jmp = '1' then v.pc := e.f.j; else v.pc := f.pc + 1; end if;








    +








    +      --------------------------------------------------------------------------








    +      -- INTR Interrupt                                                       --








    +      --------------------------------------------------------------------------








    +      -- The interrupt mechanism consists of several tasks:                   --








    +      --  o Push a '0' onto the IE stack to avoid further interrupt triggers. --








    +      --  o Set the EPC to the instruction following the current instruction. --








    +      --  o Jump to EPC_ADR, which is the hardcoded address of the interrupt  --








    +      --    dispatch routine.                                                 --








    +      --------------------------------------------------------------------------








    +








    +      -- Restore from exception.








    +      -- Do before interrupt handling, or else we might push the IE stack twice.








    +      if d.cc.rfe then c := pop_ie(c); end if;








    +








    +      -- Set SR of CP0. [DE]








    +      -- Set (Disable) SR before interrupt handling.








    +      if d.cc.mtsr then








    +         c.sr.im  := intr_im;








    +         c.sr.iec := intr_iec;








    +         c.sr.iep := intr_iep;








    +         c.sr.ieo := intr_ieo;








    +      end if;








    +








    +      -- Delay interrupt if we are in one of the to delay slots.








    +      -- Push the IE stack, Save return address and jump to the interrupt








    +      -- handler.








    +      intr := ( (cp.sr.im and ci.irq) /= x"00" ) and (cp.sr.iec = '1');








    +








    +      if (not intr_bd) and (not intr_bdd) and intr then








    +         c     := push_ie(c);








    +         -- Save PC weather it is from a jump or just incremented.








    +         c.epc := v.pc; -- e.f.j or f.pc + 1.








    +         v.pc  := INTR_ADR(31 downto 2);








    +      end if;








    +








    +      fin  <= v;








    +      cpin <= c;








    +   end process;








    +








    +








    +








    +   -----------------------------------------------------------------------------








    +   -- DECODE STAGE                                                            --








    +   -----------------------------------------------------------------------------








    +   de : process(ci.ins, d, m, m.wc, d.cc, d.dc, d.ec, d.ec.alu, d.ec.alu.src,








    +                d.ec.jmp, d.mc, d.mc.mem, d.wc)








    +








    +      variable v : de_t;








    +








    +      alias rgcp0 : std_logic_vector(4 downto 0)  is ci.ins(15 downto 11);








    +   begin








    +      v := d;








    +








    +      -- synthesis translate_off








    +         co.op   <= op(ci.ins);








    +         co.alu  <= aluop(ci.ins);








    +         co.rimm <= rimmop(ci.ins);








    +         co.cp0op <= cp0op(ci.ins);








    +         co.cp0reg <= cp0reg(ci.ins(4 downto 0));








    +      -- synthesis translate_on








    +








    +      --------------------------------------------------------------------------








    +      -- Decode                                                               --








    +      --------------------------------------------------------------------------








    +      -- Default values emulate a NOP [SLL $0, $0, 0] operation.








    +








    +      v.cc.mtsr      := false;   -- Move To Status Register. [INTR]








    +      v.cc.rfe       := false;   -- Restore from Exception.  [INTR]








    +      --v.f.jmp        := '0';








    +      --v.f.j          := (others => '-');








    +      v.ec.wbr       := RD;      -- Write back register.








    +      v.ec.alu.op    := SLL0;    -- ALU operation.          [ALU]








    +      v.ec.alu.src.a := REG;     -- Source for ALU input A. [ALU Source Choice]








    +      v.ec.alu.src.b := REG;     -- Source for ALU input B. [ALU Source Choice]








    +      v.ec.jmp.src   := REG;     -- Jump source.            [Branch/Jump]








    +      v.ec.jmp.op    := NOP;     -- Jump type.              [Branch/Jump]








    +      v.mc.mem.we    := '0';     -- Memory write enable.








    +      v.mc.mem.ext   := ZERO;    -- Memory data extension.  [Data Extension]








    +      v.mc.mem.byt   := NONE;    -- Number of data bytes.   [MEMORY STAGE]








    +      v.mc.src       := ALU;     -- ALU or MEM to GPR.      [MEMORY STAGE]








    +      v.wc.we        := '0';     -- GPR write enable.








    +








    +      intr_bd        <= false;     -- Marks a branch delay slot. [INTR]








    +








    +      case op(ci.ins) is








    +         when AD =>








    +            case aluop(ci.ins) is








    +               when JALR =>








    +                  v              := link(v);








    +                  v.ec.jmp.op    := JMP;








    +                  intr_bd        <= true;








    +               when JR =>








    +                  v.ec.jmp.op    := JMP;








    +                  intr_bd        <= true;








    +               when SLL0 | SRA0 | SRL0 =>








    +                  v.ec.alu.op    := aluop(ci.ins);








    +                  v.ec.alu.src.a := SH_CONST;








    +                  v.wc.we        := '1';








    +               when others =>








    +                  v.ec.alu.op    := aluop(ci.ins);








    +                  v.wc.we        := '1';








    +            end case;








    +








    +         -----------------------------------------------------------------------








    +         -- Immediate Branches                                                --








    +         -----------------------------------------------------------------------








    +         when RI =>








    +            case rimmop(ci.ins) is








    +               when BGEZ =>








    +                  v.ec.jmp.src   := BRA;








    +                  v.ec.jmp.op    := GEZ;








    +                  intr_bd        <= true;








    +               when BGEZAL =>








    +                  v              := link(v);








    +                  v.ec.wbr       := RA;








    +                  v.ec.jmp.src   := BRA;








    +                  v.ec.jmp.op    := GEZ;








    +                  intr_bd        <= true;








    +               when BLTZ =>








    +                  v.ec.jmp.src   := BRA;








    +                  v.ec.jmp.op    := LTZ;








    +                  intr_bd        <= true;








    +               when BLTZAL =>








    +                  v              := link(v);








    +                  v.ec.wbr       := RA;








    +                  v.ec.jmp.src   := BRA;








    +                  v.ec.jmp.op    := LTZ;








    +                  intr_bd        <= true;








    +               when ERR =>








    +            end case;








    +








    +         -----------------------------------------------------------------------








    +         -- Normal Jumps/Branches                                             --








    +         -----------------------------------------------------------------------








    +         when J =>








    +         -- v.f.jmp        := '1';








    +         -- v.f.j          := f.pc(31 downto 28) & unsigned(ci.ins);








    +            v.ec.jmp.src   := JMP;








    +            v.ec.jmp.op    := JMP;








    +            intr_bd        <= true;








    +         when JAL =>








    +            v              := link(v);








    +            v.ec.wbr       := RA;








    +         -- v.f.jmp        := '1';








    +         -- v.f.j          := f.pc(31 downto 28) & unsigned(ci.ins);








    +            v.ec.jmp.src   := JMP;








    +            v.ec.jmp.op    := JMP;








    +            intr_bd        <= true;








    +         when BEQ =>








    +            v.ec.jmp.src   := BRA;








    +            v.ec.jmp.op    := EQ;








    +            intr_bd        <= true;








    +         when BNE =>








    +            v.ec.jmp.src   := BRA;








    +            v.ec.jmp.op    := NEQ;








    +            intr_bd        <= true;








    +         when BLEZ =>








    +            v.ec.jmp.src   := BRA;








    +            v.ec.jmp.op    := LEZ;








    +            intr_bd        <= true;








    +         when BGTZ =>








    +            v.ec.jmp.src   := BRA;








    +            v.ec.jmp.op    := GTZ;








    +            intr_bd        <= true;








    +








    +         -----------------------------------------------------------------------








    +         -- Immediate Operations                                              --








    +         -----------------------------------------------------------------------








    +         when ADDI =>








    +            v              := simm(v);








    +            v.ec.alu.op    := ADD;








    +         when ADDIU =>








    +            v              := simm(v);








    +            v.ec.alu.op    := ADDU;








    +         when SLTI =>








    +            v              := simm(v);








    +            v.ec.alu.op    := SLT;








    +         when SLTIU =>








    +            v              := simm(v);








    +            v.ec.alu.op    := SLTU;








    +         when ANDI =>








    +            v              := zimm(v);








    +            v.ec.alu.op    := AND0;








    +         when ORI =>








    +            v              := zimm(v);








    +            v.ec.alu.op    := OR0;








    +         when XORI =>








    +            v              := zimm(v);








    +            v.ec.alu.op    := XOR0;








    +         when LUI =>








    +            v              := zimm(v);








    +            v.ec.alu.src.a := SH_16;








    +








    +         -----------------------------------------------------------------------








    +         -- Load And Store Data                                               --








    +         -----------------------------------------------------------------------








    +         when LB =>








    +            v              := load(v);








    +            v.mc.mem.ext   := SIGN;








    +            v.mc.mem.byt   := BYTE;








    +         when LH =>








    +            v              := load(v);








    +            v.mc.mem.ext   := SIGN;








    +            v.mc.mem.byt   := HALF;








    +         when LW =>








    +            v              := load(v);








    +            v.mc.mem.byt   := WORD;








    +         when LBU =>








    +            v              := load(v);








    +            v.mc.mem.byt   := BYTE;








    +         when LHU =>








    +            v              := load(v);








    +            v.mc.mem.byt   := HALF;








    +         when SB =>








    +            v              := store(v);








    +            v.mc.mem.byt   := BYTE;








    +         when SH =>








    +            v              := store(v);








    +            v.mc.mem.byt   := HALF;








    +         when SW =>








    +            v              := store(v);








    +            v.mc.mem.byt   := WORD;








    +








    +         -----------------------------------------------------------------------








    +         -- Co-Processor 0                                                    --








    +         -----------------------------------------------------------------------








    +         when CP0 =>








    +            case cp0op(ci.ins) is








    +               when MFCP0 =>








    +                  v.ec.wbr    := RT;








    +                  v.ec.alu.op := MFCP0;








    +                  v.wc.we     := '1';








    +               when MTCP0 =>








    +                  v.ec.alu.op := MTCP0;








    +                  if cp0reg(rgcp0) = SR then v.cc.mtsr := true; end if;








    +               when RFE   =>








    +                  v.ec.alu.op := RFE;








    +                  v.cc.rfe    := true;








    +               when ERR   =>








    +            end case;








    +         when ERR =>








    +      end case;








    +








    +      v.i     := ci.ins(25 downto 0);








    +      v.dc.we := m.wc.we;              -- Forward write enable.








    +      v.rd    := m.rd;                 -- Forward destination register.








    +      v.res   := m.res;                -- Forward data.








    +      din <= v;








    +   end process;








    +








    +   -----------------------------------------------------------------------------








    +   -- GPR General Purpose Registers                                           --








    +   -----------------------------------------------------------------------------








    +   gp : gpr port map(








    +      clk_i => ci.clk,        -- Clock.








    +      hld_i => ci.hld,        -- Hold register data.








    +      rs_a  => rs_a,          -- RS register address.








    +      rt_a  => rt_a,          -- RT register address.








    +      rd_a  => m.rd,          -- Write back register address.








    +      rd_we => m.wc.we,       -- Write back enable.








    +      rd_i  => m.res,         -- Write back register data.








    +      rs_o  => rs_o,          -- RS register data.








    +      rt_o  => rt_o           -- RT register data.








    +   );








    +








    +








    +








    +   -----------------------------------------------------------------------------








    +   -- EXECUTION STAGE                                                         --








    +   -----------------------------------------------------------------------------








    +   ex : process(ci.irq, rs_o, rt_o, cp, cp.sr, f, d, d.dc, d.ec, d.ec.alu,








    +                d.ec.alu.src, d.ec.jmp, d.mc, d.mc.mem, d.wc, e, e.f, e.mc,








    +                e.mc.mem, e.wc, m, m.wc)








    +








    +      variable v        : ex_t;








    +      variable a, b     : std_logic_vector(31 downto 0);    -- ALU input.








    +      variable fa, fb   : std_logic_vector(31 downto 0);    -- Forwarded data.








    +      variable equ, eqz : std_logic;                        -- fa=fb, fa=0








    +      variable atmp     : std_logic_vector(31 downto 0);    -- Temporary result.








    +








    +      --------------------------------------------------------------------------








    +      --   R-Type Register                                                    --








    +      --   +--------------------------------------------------------------+   --








    +      --   |              |   rgs   |   rgt   |   rgd   |  smt  |         |   --








    +      --   +--------------------------------------------------------------+   --








    +      --   I-Type Register                                                    --








    +      --   +--------------------------------------------------------------+   --








    +      --   |                             |             imm                |   --








    +      --   +--------------------------------------------------------------+   --








    +      --------------------------------------------------------------------------








    +      alias rgs : std_logic_vector(4 downto 0)  is d.i(25 downto 21);








    +      alias rgt : std_logic_vector(4 downto 0)  is d.i(20 downto 16);








    +      alias rgd : std_logic_vector(4 downto 0)  is d.i(15 downto 11);








    +      alias imm : std_logic_vector(15 downto 0) is d.i(15 downto 0);








    +      alias smt : std_logic_vector(4 downto 0)  is d.i(10 downto 6);








    +   begin








    +      v := e;








    +








    +      -- Choose the write back register.








    +      case d.ec.wbr is








    +         when RD => v.rd := rgd;








    +         when RT => v.rd := rgt;








    +         when RA => v.rd := b"11111";








    +      end case;








    +








    +      --------------------------------------------------------------------------








    +      -- Forwarding                                                           --








    +      --------------------------------------------------------------------------








    +      -- In a pipeline there can be data that has not been written into the   --








    +      -- GPR registers yet. For example see:                                  --








    +      --                                                                      --








    +      --          addu $t0, $t1, $t2 -+                                       --








    +      --          sll  $t3, $t0, 4   -+- $t0                                  --








    +      --                                                                      --








    +      -- Here GPR $t0 is not up to date, since the instruction addu           --








    +      -- manipulates $t0, but is available after EX, so we choose the newer   --








    +      -- data from after the EX stage instead of the GPR data.                --








    +      -- However, if we load data and use it in the next instruction, we get  --








    +      -- the wrong result. Loaded data is available two cycles after the load --








    +      -- instruction. The compiler solves this problem, since it inserts an   --








    +      -- independend instruction or a NOP operation.                          --








    +      -- Other problems arise when:                                           --








    +      --                                                                      --








    +      --          ori  $t0, $s1, 3   -+                                       --








    +      --          sw   $s2, 4($sp)    |                                       --








    +      --          subu $s2, $t0, $s3 -+- $t0                                  --








    +      --                                                                      --








    +      -- In the second example, the updated data is available after the ME    --








    +      -- stage. Up untill now we considered the situation from the viewpoint  --








    +      -- of the EX stage.                                                     --








    +      --                                                                      --








    +      --          andi $t0, $t0, 1   -+                                       --








    +      --          lui  $s1, 0xf4      |                                       --








    +      --          lw   $s2, 0($sp)    |                                       --








    +      --          sra  $t1, $t0, 3   -+- $t0                                  --








    +      --                                                                      --








    +      -- The third example shows a problem that arrises one cycle earlier.    --








    +      -- When we read the register contents. The data to be written is        --








    +      -- present as well but not available yet. One solution might be, to     --








    +      -- prefer write before read operations. the other way suggests to store --








    +      -- the write back data, address and write enable flag one more cycle.   --








    +      -- We can then decide in the EX stage again if the data is more recent. --








    +      --------------------------------------------------------------------------








    +      fa := rs_o;








    +      fb := rt_o;








    +








    +      -- Forward from Write Back Stage (Data stored in DE Stage).








    +      if (d.rd /= "00000") and (d.dc.we = '1') then








    +         if rgs = d.rd then fa := d.res; end if;








    +         if rgt = d.rd then fb := d.res; end if;








    +      end if;








    +








    +      -- Forward from Memory Stage.








    +      if (m.rd /= "00000") and (m.wc.we = '1') then








    +            if rgs = m.rd then fa := m.res; end if;








    +            if rgt = m.rd then fb := m.res; end if;








    +      end if;








    +








    +      -- Forward from Execution Stage.








    +      if (e.rd /= "00000") and (e.wc.we = '1') then








    +            if rgs = e.rd then fa := e.res; end if;








    +            if rgt = e.rd then fb := e.res; end if;








    +      end if;








    +








    +      --------------------------------------------------------------------------








    +      -- ALU Source Choice                                                    --








    +      --------------------------------------------------------------------------








    +      -- SH_CONST: Constant shift amount (SLL, SRL, SRA).                     --








    +      -- SH_16:    Shift 16-bit (LUI).                                        --








    +      -- ADD_4:    Plus 4.                                                    --








    +      -- REG:      Forwarded RS register value. [Forwarding]                  --








    +      --------------------------------------------------------------------------








    +      case d.ec.alu.src.a is








    +         when SH_CONST => a := zext(smt, 32);








    +         when SH_16    => a := zext(b"10000", 32);








    +         when ADD_4    => a := zext(b"00100", 32);








    +         when REG      => a := fa;








    +      end case;








    +








    +      --------------------------------------------------------------------------








    +      -- SIGN: Sign extend 16-bit immediate value according to MSB.           --








    +      -- ZERO: Zero extend 16-bit immediate value.                            --








    +      -- PC:   Current PC value.                                              --








    +      -- REG:  Forwarded RT register value. [Forwarding]                      --








    +      --------------------------------------------------------------------------








    +      case d.ec.alu.src.b is








    +         when SIGN => b := sext(imm, 32);








    +         when ZERO => b := zext(imm, 32);








    +         when PC   => b := std_logic_vector(f.pc) & "00";








    +         when REG  => b := fb;








    +      end case;








    +








    +      --------------------------------------------------------------------------








    +      -- ALU                                                                  --








    +      --------------------------------------------------------------------------








    +      -- IMPROVE: optimze SLT,SLTU.








    +      intr_iec <= b(0);            -- IEc: Interrupt enable current.   [INTR]








    +      intr_iep <= b(2);            -- IEp: Interrupt enable previous.  [INTR]








    +      intr_ieo <= b(4);            -- IEo: Interrupt enable old.       [INTR]








    +      intr_im  <= b(15 downto 8);  -- Interrupt mask.                  [INTR]








    +








    +      atmp  := addsub(a, b, d.ec.alu.op);








    +      v.res := (others => '0');








    +








    +      case d.ec.alu.op is








    +         when ADD  | ADDU |








    +              SUB  | SUBU => v.res := atmp;








    +         when SLT         => v.res := fslt(a, b);








    +         when SLTU        => v.res := fsltu(a, b);








    +         when SLL0 | SLLV => v.res := fsll(b, a(4 downto 0));








    +         when SRA0 | SRAV => v.res := fsra(b, a(4 downto 0));








    +         when SRL0 | SRLV => v.res := fsrl(b, a(4 downto 0));








    +         when AND0        => v.res := a and b;








    +         when OR0         => v.res := a or  b;








    +         when NOR0        => v.res := a nor b;








    +         when XOR0        => v.res := a xor b;








    +         when JALR | JR   =>








    +         when MFCP0       =>








    +            case cp0reg(rgd) is








    +               when SR    => v.res := get_sr(cp);








    +               when CAUSE => v.res(15 downto 8) := ci.irq;








    +               when EPC   => v.res := std_logic_vector(cp.epc) & "00";








    +               when ERR   =>








    +            end case;








    +         when MTCP0       =>     -- MTCP0 and RFE operations are handled at the








    +         when RFE         =>     -- IF stage.








    +         when ERR         =>








    +      end case;








    +








    +      --------------------------------------------------------------------------








    +      -- Branch/Jump                                                          --








    +      --------------------------------------------------------------------------








    +      -- IMPROVE: move jump to DE stage.








    +      if fa = fb then equ := '1'; else equ := '0'; end if;








    +      if fa = x"00000000" then eqz := '1'; else eqz := '0'; end if;








    +








    +      case d.ec.jmp.op is








    +         when NOP => v.f.jmp := '0';








    +         when JMP => v.f.jmp := '1';








    +         when EQ  => v.f.jmp := equ;








    +         when NEQ => v.f.jmp := not equ;








    +         when LTZ => v.f.jmp := fa(31);








    +         when GTZ => v.f.jmp := not (fa(31) or eqz);








    +         when LEZ => v.f.jmp := fa(31) or eqz;








    +         when GEZ => v.f.jmp := not fa(31);








    +      end case;








    +








    +      case d.ec.jmp.src is








    +         when REG => v.f.j := unsigned(fa(31 downto 2));








    +         when JMP => v.f.j := f.pc(31 downto 28) & unsigned(d.i);








    +         when BRA => v.f.j := unsigned(to_integer(f.pc) + signed(sext(imm,30)));








    +      end case;








    +








    +      v.mc  := d.mc;








    +      v.wc  := d.wc;








    +      v.str := fb;








    +      ein   <= v;








    +   end process;








    +








    +








    +








    +   -----------------------------------------------------------------------------








    +   -- MEMORY STAGE                                                            --








    +   -----------------------------------------------------------------------------








    +   me : process(ci.dat, e, e.mc, e.mc.mem, e.wc, m, m.wc)








    +      variable v   : me_t;








    +      variable dat : std_logic_vector(31 downto 0);   -- Fetched memory data








    +   begin








    +      v := m;








    +








    +      co.we   <= e.mc.mem.we;








    +      co.dadr <= e.res;








    +      co.dat  <= e.str;








    +








    +      --------------------------------------------------------------------------








    +      -- Address Decode                                                       --








    +      --------------------------------------------------------------------------








    +      -- Translate lower address bits to Wishbone Bus selection scheme.       --








    +      --------------------------------------------------------------------------








    +      case e.mc.mem.byt is








    +         when NONE => co.sel <= "0000";








    +         when BYTE =>








    +            case e.res(1 downto 0) is








    +               when "00"   => co.sel <= "1000";








    +               when "01"   => co.sel <= "0100";








    +               when "10"   => co.sel <= "0010";








    +               when "11"   => co.sel <= "0001";








    +               when others => co.sel <= "0000";








    +            end case;








    +         when HALF =>








    +            case e.res(1) is








    +               when '0'    => co.sel <= "1100";








    +               when '1'    => co.sel <= "0011";








    +               when others => co.sel <= "0000";








    +            end case;








    +         when WORD => co.sel <= "1111";








    +      end case;








    +








    +      --------------------------------------------------------------------------








    +      -- Data Extension                                                       --








    +      --------------------------------------------------------------------------








    +      -- Fetched data can be extended with zeros or according to its MSB.     --








    +      --------------------------------------------------------------------------








    +      case e.mc.mem.byt is








    +         when NONE => dat := (others => '0');   -- AREA: (others => '-');








    +         when BYTE =>








    +            case e.mc.mem.ext is








    +               when ZERO => dat := zext(ci.dat(7 downto 0), 32);








    +               when SIGN => dat := sext(ci.dat(7 downto 0), 32);








    +            end case;








    +         when HALF =>








    +            case e.mc.mem.ext is








    +               when ZERO => dat := zext(ci.dat(15 downto 0), 32);








    +               when SIGN => dat := sext(ci.dat(15 downto 0), 32);








    +            end case;








    +         when WORD => dat := ci.dat;








    +      end case;








    +








    +      case e.mc.src is








    +         when ALU => v.res := e.res;      -- Take either the result of the ALU








    +         when MEM => v.res := dat;        -- or the loaded data from memory.








    +      end case;








    +








    +      v.wc := e.wc;








    +      v.rd := e.rd;








    +      min  <= v;








    +   end process;








    +








    +








    +








    +   -----------------------------------------------------------------------------








    +   -- REGISTERS                                                               --








    +   -----------------------------------------------------------------------------








    +   reg : process(ci.clk)








    +   begin








    +      if rising_edge(ci.clk) then








    +         if ci.hld = '0' then








    +            f  <= fin;     -- IF








    +            d  <= din;     -- DE








    +            e  <= ein;     -- EX








    +            m  <= min;     -- ME








    +            cp <= cpin;    -- CP0








    +








    +            --------------------------------------------------------------------








    +            -- Branch Correction                                              --








    +            --------------------------------------------------------------------








    +            -- The simplest way one can think of, is to consider every branch --








    +            -- or jump to be NOT taken and to load instructions in sequence.  --








    +            -- If we actually do jump, we already loaded an incorrect         --








    +            -- instruction in the IF stage. To anihilate the effects of this  --








    +            -- instruction, we will clear the DE stage one cycle later.       --








    +            -- [fcpu.clear(v_i : de_t)]                                       --








    +            --------------------------------------------------------------------








    +            if e.f.jmp = '1' then d <= clear(d); end if;








    +








    +            -- Set Branch Delay Delay slot flag.








    +            intr_bdd <= intr_bd;








    +         end if;








    +








    +         -- On reset clear all relevant control signals.








    +         if ci.rst = '1' then








    +            f  <= clear(f);   -- IF








    +            d  <= clear(d);   -- DE








    +            e  <= clear(e);   -- EX








    +            m  <= clear(m);   -- ME








    +            cp <= clear(cp);  -- CP0








    +         end if;








    +      end if;








    +   end process;








    +end rtl;








    \ No newline at end of file








    Index: layer2/trunk/vhdl/cpu/rtl/gpr.vhd








    ===================================================================








    --- layer2/trunk/vhdl/cpu/rtl/gpr.vhd	(nonexistent)








    +++ layer2/trunk/vhdl/cpu/rtl/gpr.vhd	(revision 2)








    @@ -0,0 +1,61 @@








    +--------------------------------------------------------------------------------








    +-- MIPS� I CPU - General Purpose Register                                     --








    +--------------------------------------------------------------------------------








    +-- Copyright (C)2011  Mathias H�rtnagl          --








    +--                                                                            --








    +-- This program is free software: you can redistribute it and/or modify       --








    +-- it under the terms of the GNU General Public License as published by       --








    +-- the Free Software Foundation, either version 3 of the License, or          --








    +-- (at your option) any later version.                                        --








    +--                                                                            --








    +-- This program is distributed in the hope that it will be useful,            --








    +-- but WITHOUT ANY WARRANTY; without even the implied warranty of             --








    +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the              --








    +-- GNU General Public License for more details.                               --








    +--                                                                            --








    +-- You should have received a copy of the GNU General Public License          --








    +-- along with this program.  If not, see .      --








    +--------------------------------------------------------------------------------








    +library ieee;








    +use ieee.std_logic_1164.all;








    +use ieee.numeric_std.all;








    +








    +entity gpr is








    +   port(








    +      clk_i : in  std_logic;








    +      hld_i : in  std_logic;








    +      rs_a  : in  std_logic_vector(4 downto 0);








    +      rt_a  : in  std_logic_vector(4 downto 0);








    +      rd_a  : in  std_logic_vector(4 downto 0);








    +      rd_we : in  std_logic;








    +      rd_i  : in  std_logic_vector(31 downto 0);








    +      rs_o  : out std_logic_vector(31 downto 0);








    +      rt_o  : out std_logic_vector(31 downto 0)








    +   );








    +end gpr;








    +








    +architecture rtl of gpr is








    +








    +   type gpr_t is array (0 to 31) of std_logic_vector(31 downto 0);








    +   signal gpr : gpr_t := (others => (others => '0'));








    +








    +   attribute RAM_STYLE : string;








    +   attribute RAM_STYLE of gpr: signal is "BLOCK";








    +begin








    +








    +   reg : process(clk_i)








    +   begin








    +      if rising_edge(clk_i) then








    +         if (hld_i = '0') then








    +








    +            -- Save data only if it's register address is not zero.








    +            -- Keeps register $0 zero.








    +            if (rd_we = '1') and (rd_a /= "00000") then








    +               gpr( to_integer(unsigned(rd_a)) ) <= rd_i;








    +            end if;








    +            rs_o <= gpr( to_integer(unsigned(rs_a)) );








    +            rt_o <= gpr( to_integer(unsigned(rt_a)) );








    +         end if;








    +      end if;








    +   end process;








    +end rtl;








    \ No newline at end of file








    Index: layer2/trunk/vhdl/cpu/rtl/mips1.vhd








    ===================================================================








    --- layer2/trunk/vhdl/cpu/rtl/mips1.vhd	(nonexistent)








    +++ layer2/trunk/vhdl/cpu/rtl/mips1.vhd	(revision 2)








    @@ -0,0 +1,227 @@








    +--------------------------------------------------------------------------------








    +-- MIPS� I CPU - Instruction Set                                              --








    +--------------------------------------------------------------------------------








    +-- Type definitions of the MIPS� I instruction (sub-)set and some convenience --








    +-- functions to convert binary operation representations to symbolic          --








    +-- equivalents.                                                               --








    +--                                                                            --








    +--------------------------------------------------------------------------------








    +-- Copyright (C)2011  Mathias H�rtnagl          --








    +--                                                                            --








    +-- This program is free software: you can redistribute it and/or modify       --








    +-- it under the terms of the GNU General Public License as published by       --








    +-- the Free Software Foundation, either version 3 of the License, or          --








    +-- (at your option) any later version.                                        --








    +--                                                                            --








    +-- This program is distributed in the hope that it will be useful,            --








    +-- but WITHOUT ANY WARRANTY; without even the implied warranty of             --








    +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the              --








    +-- GNU General Public License for more details.                               --








    +--                                                                            --








    +-- You should have received a copy of the GNU General Public License          --








    +-- along with this program.  If not, see .      --








    +--------------------------------------------------------------------------------








    +library ieee;








    +use ieee.std_logic_1164.all;








    +use ieee.numeric_std.all;








    +








    +package mips1 is








    +








    +   -----------------------------------------------------------------------------








    +   -- OP Codes                                                                --








    +   -----------------------------------------------------------------------------








    +   type op_t is (








    +      AD,    -- Operations with AluOp








    +      RI,    -- Additional Branches








    +      J,     -- Jump








    +      JAL,   -- Jump And Link to $ra








    +      BEQ,   -- Branch On Equal








    +      BNE,   -- Branch On Not Equal








    +      BLEZ,  -- Branch Less Equal Zero








    +      BGTZ,  -- Branch Greater Than Zero








    +      ADDI,  -- Add Immediate








    +      ADDIU, -- Add Immediate Unsigned








    +      SLTI,  -- SLT Immediate








    +      SLTIU, -- SLT Immediate Unsigned








    +      ANDI,  -- And Immediate








    +      ORI,   -- Or Immediate








    +      XORI,  -- Xor Immediate








    +      LUI,   -- Load Upper Immediate








    +      LB,    -- Load Byte








    +      LH,    -- Load Half Word








    +      LW,    -- Load Word








    +      LBU,   -- Load Byte Unsigned








    +      LHU,   -- Load Half Word Unsigned








    +      SB,    -- Store Byte








    +      SH,    -- Store Half Word








    +      SW,    -- Store Word








    +      CP0,   -- Co-Processor 0 Operations








    +      ERR    -- Unknown OP








    +   );








    +








    +   function op(i : std_logic_vector) return op_t;








    +








    +   -----------------------------------------------------------------------------








    +   -- ALU OP Codes                                                            --








    +   -----------------------------------------------------------------------------








    +   -- In this implementation of the MIPS� I instruction set, ADD, ADDU and    --








    +   -- SUB, SUBU cause indentical behaviour. This means that ADDU and SUBU do  --








    +   -- NOT trap on overflow.                                                   --








    +   -----------------------------------------------------------------------------








    +   type alu_op_t is (








    +      ADD,   -- Addition








    +      ADDU,  -- Add Unsigned








    +      SUB,   -- Subtraction








    +      SUBU,  -- Subtract Unsigned








    +      AND0,  -- Logic and








    +      OR0,   -- Logic or








    +      NOR0,  -- Logic nor








    +      XOR0,  -- Logic xor








    +      SLT,   -- Set On Less Than








    +      SLTU,  -- SLT Unsigned








    +      SLL0,  -- Shift Left Logical








    +      SLLV,  -- SLL Variable








    +      SRA0,  -- Shift Right Arith








    +      SRAV,  -- SRA Variable








    +      SRL0,  -- Shift Right Logical








    +      SRLV,  -- SRL Variable








    +      JALR,  -- Jump And Link Reg








    +      JR,    -- Jump Reg








    +      MFCP0, -- Move From Co-Processor 0








    +      MTCP0, -- Move To Co-Processor 0








    +      RFE,   -- Restore From Exception








    +      ERR    -- Unknown ALU OP








    +   );








    +








    +   -- Convert ALU Op bit pattern into its symbolic representation.








    +   function aluop(i : std_logic_vector) return alu_op_t;








    +








    +   -----------------------------------------------------------------------------








    +   -- REGIMM Codes                                                            --








    +   -----------------------------------------------------------------------------








    +   type rimm_op_t is (








    +      BGEZ,   -- Branch Greater Equal 0








    +      BGEZAL, -- BGEZ And Link








    +      BLTZ,   -- Branch Less Than 0








    +      BLTZAL, -- BLTZ And Link








    +      ERR     -- Unknown RIMM OP








    +   );








    +








    +   -- Convert Reg Immediate Op bit pattern into its symbolic representation.








    +   function rimmop(i : std_logic_vector) return rimm_op_t;








    +








    +   -----------------------------------------------------------------------------








    +   -- CP0 Codes                                                               --








    +   -----------------------------------------------------------------------------








    +   type cp0_op_t is (








    +      MFCP0, -- Move From Co-Processor 0








    +      MTCP0, -- Move To Co-Processor 0








    +      RFE,   -- Restore From Exception








    +      ERR    -- Unknown CP0 OP








    +   );








    +








    +   type cp0_reg_t is (








    +      SR,    -- Status Register








    +      CAUSE, -- Cause Register








    +      EPC,   -- EPC








    +      ERR    -- Unknown CP0 REG








    +   );








    +








    +   -- Convert CP0 Op and Reg Addresses bit patterns into its symbolic








    +   -- representation.








    +   function cp0op(i : std_logic_vector) return cp0_op_t;








    +   function cp0reg(i : std_logic_vector) return cp0_reg_t;








    +








    +end mips1;








    +








    +package body mips1 is








    +








    +   function op(i : std_logic_vector) return op_t is








    +   begin








    +      case i(31 downto 26) is








    +         when "000000" => return AD;    -- Operations with AluOp








    +         when "000001" => return RI;    -- Additional Branches








    +         when "000010" => return J;     -- Jump








    +         when "000011" => return JAL;   -- Jump And Link to $ra








    +         when "000100" => return BEQ;   -- Branch On Equal








    +         when "000101" => return BNE;   -- Branch On Not Equal








    +         when "000110" => return BLEZ;  -- Branch Less Equal Zero








    +         when "000111" => return BGTZ;  -- Branch Greater Than Zero








    +         when "001000" => return ADDI;  -- Add Immediate








    +         when "001001" => return ADDIU; -- Add Immediate Unsigned








    +         when "001010" => return SLTI;  -- SLT Immediate








    +         when "001011" => return SLTIU; -- SLT Immediate Unsigned








    +         when "001100" => return ANDI;  -- And Immediate








    +         when "001101" => return ORI;   -- Or Immediate








    +         when "001110" => return XORI;  -- Xor Immediate








    +         when "001111" => return LUI;   -- Load Upper Immediate








    +         when "100000" => return LB;    -- Load Byte








    +         when "100001" => return LH;    -- Load Half Word








    +         when "100011" => return LW;    -- Load Word








    +         when "100100" => return LBU;   -- Load Byte Unsigned








    +         when "100101" => return LHU;   -- Load Half Word Unsigned








    +         when "101000" => return SB;    -- Store Byte








    +         when "101001" => return SH;    -- Store Half Word








    +         when "101011" => return SW;    -- Store Word








    +         when "010000" => return CP0;   -- Co-Processor 0 Operations








    +         when others   => return ERR;   -- Unknown OP








    +      end case;








    +   end op;








    +








    +   function aluop(i : std_logic_vector) return alu_op_t is








    +   begin








    +      case i(5 downto 0) is








    +         when "100000" => return ADD;  -- Addition








    +         when "100001" => return ADDU; -- Add Unsigned








    +         when "100010" => return SUB;  -- Subtract








    +         when "100011" => return SUBU; -- Subtract Unsigned








    +         when "100100" => return AND0; -- Logic and








    +         when "100101" => return OR0;  -- Logic or








    +         when "100111" => return NOR0; -- Logic nor








    +         when "100110" => return XOR0; -- Logic xor








    +         when "101010" => return SLT;  -- Set On Less Than








    +         when "101011" => return SLTU; -- SLT Unsigned








    +         when "000000" => return SLL0; -- Shift Left Logical








    +         when "000100" => return SLLV; -- SLL Variable








    +         when "000011" => return SRA0; -- Shift Right Arith








    +         when "000111" => return SRAV; -- SRA Variable








    +         when "000010" => return SRL0; -- Shift Right Logical








    +         when "000110" => return SRLV; -- SRL Variable








    +         when "001001" => return JALR; -- Jump And Link Reg








    +         when "001000" => return JR;   -- Jump Reg








    +         when others   => return ERR;  -- Unknown ALU OP








    +      end case;








    +   end aluop;








    +








    +   function rimmop(i : std_logic_vector) return rimm_op_t is








    +   begin








    +      case i(20 downto 16) is








    +      when "00001" => return BGEZ;   -- Branch Greater Equal 0








    +      when "10001" => return BGEZAL; -- BGEZ And Link








    +      when "00000" => return BLTZ;   -- Branch Less Than 0








    +      when "10000" => return BLTZAL; -- BLTZ And Link








    +      when others  => return ERR;    -- Unknown RIMM OP








    +      end case;








    +   end rimmop;








    +








    +   function cp0op(i : std_logic_vector) return cp0_op_t is








    +   begin








    +      case i(25 downto 21) is








    +      when "00000" => return MFCP0; -- Move From Co-Processor 0








    +      when "00100" => return MTCP0; -- Move To Co-Processor 0








    +      when "10000" => return RFE;   -- Restore From Exception








    +      when others  => return ERR;   -- Unknown CP0 OP








    +      end case;








    +   end cp0op;








    +








    +   function cp0reg(i : std_logic_vector) return cp0_reg_t is








    +   begin








    +      case i(4 downto 0) is








    +      when "01100" => return SR;    -- Status Register








    +      when "01101" => return CAUSE; -- Cause Register








    +      when "01110" => return EPC;   -- EPC








    +      when others  => return ERR;   -- Unknown CP0 REG








    +      end case;








    +   end cp0reg;








    +








    +end mips1;








    \ No newline at end of file








    Index: layer2/trunk/vhdl/cpu/rtl/tcpu.vhd








    ===================================================================








    --- layer2/trunk/vhdl/cpu/rtl/tcpu.vhd	(nonexistent)








    +++ layer2/trunk/vhdl/cpu/rtl/tcpu.vhd	(revision 2)








    @@ -0,0 +1,163 @@








    +--------------------------------------------------------------------------------








    +-- MIPS� I CPU - Type Definitions                                             --








    +--------------------------------------------------------------------------------








    +-- Copyright (C)2011  Mathias H�rtnagl          --








    +--                                                                            --








    +-- This program is free software: you can redistribute it and/or modify       --








    +-- it under the terms of the GNU General Public License as published by       --








    +-- the Free Software Foundation, either version 3 of the License, or          --








    +-- (at your option) any later version.                                        --








    +--                                                                            --








    +-- This program is distributed in the hope that it will be useful,            --








    +-- but WITHOUT ANY WARRANTY; without even the implied warranty of             --








    +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the              --








    +-- GNU General Public License for more details.                               --








    +--                                                                            --








    +-- You should have received a copy of the GNU General Public License          --








    +-- along with this program.  If not, see .      --








    +--------------------------------------------------------------------------------








    +library ieee;








    +use ieee.std_logic_1164.all;








    +use ieee.numeric_std.all;








    +








    +library work;








    +use work.mips1.all;








    +








    +package tcpu is








    +








    +   component gpr is








    +      port(








    +         clk_i : in  std_logic;








    +         hld_i : in  std_logic;








    +         rs_a  : in  std_logic_vector(4 downto 0);








    +         rt_a  : in  std_logic_vector(4 downto 0);








    +         rd_a  : in  std_logic_vector(4 downto 0);








    +         rd_we : in  std_logic;








    +         rd_i  : in  std_logic_vector(31 downto 0);








    +         rs_o  : out std_logic_vector(31 downto 0);








    +         rt_o  : out std_logic_vector(31 downto 0)








    +      );








    +   end component;








    +








    +   -----------------------------------------------------------------------------








    +   -- MEMORY STAGE                                                            --








    +   -----------------------------------------------------------------------------








    +   type wc_t is record








    +      we  : std_logic;                       -- Write back enable.








    +   end record;








    +








    +   type me_t is record








    +      wc  : wc_t;                            -- Write Back Stage control.








    +      rd  : std_logic_vector(4 downto 0);    -- Write back register address.








    +      res : std_logic_vector(31 downto 0);   -- Write back data (ALU or Memory).








    +   end record;








    +








    +   -----------------------------------------------------------------------------








    +   -- EXECUTION STAGE                                                         --








    +   -----------------------------------------------------------------------------








    +   type mem_ext_t is (ZERO, SIGN);








    +   type mem_byt_t is (NONE, BYTE, HALF, WORD);








    +








    +   type jadr_t is record








    +      j   : unsigned(31 downto 2);           -- Jump/Branch address.








    +      jmp : std_logic;                       -- Jump or don't jump. That's ...








    +   end record;








    +








    +   type mem_t is record








    +      we  : std_logic;                       -- Stored data write enable.








    +      ext : mem_ext_t;                       -- Loaded Data extension.








    +      byt : mem_byt_t;                       -- Data width.








    +   end record;








    +








    +   type ret_t is (ALU, MEM);








    +








    +   type mc_t is record








    +      src : ret_t;                           -- Either ALU or Memory result.








    +      mem : mem_t;                           -- Load/Store control signals.








    +   end record;








    +








    +   type ex_t is record








    +      mc  : mc_t;                            -- Memory Stage control.








    +      wc  : wc_t;                            -- Write Back Stage control.








    +      rd  : std_logic_vector(4 downto 0);    -- Write back register address.








    +      f   : jadr_t;                          -- Jump/Branch information for IF.








    +      str : std_logic_vector(31 downto 0);   -- ALU source B saved to memory.








    +      res : std_logic_vector(31 downto 0);   -- ALU result.








    +   end record;








    +








    +   -----------------------------------------------------------------------------








    +   -- DECODE STAGE                                                            --








    +   -----------------------------------------------------------------------------








    +   type jmp_op_t is (NOP, JMP, EQ, NEQ, GTZ, LTZ, GEZ, LEZ);








    +   type jmp_src_t is (REG, JMP, BRA);








    +








    +   type jmp_t is record








    +      op  : jmp_op_t;                        -- Possible branching conditions.








    +      src : jmp_src_t;                       -- Possile jump/branch sources.








    +   end record;








    +








    +   type alu_src_a_t is (SH_CONST, SH_16, ADD_4, REG);








    +   type alu_src_b_t is (ZERO, SIGN, PC, REG);








    +








    +   type alu_src_t is record








    +      a : alu_src_a_t;                       -- Sources for input A.








    +      b : alu_src_b_t;                       -- Sources for input B.








    +   end record;








    +








    +   type alu_t is record








    +      op  : alu_op_t;                        -- ALU Ops [Mips1.vhd]








    +      src : alu_src_t;                       -- ALU sources.








    +   end record;








    +








    +   type wbr_t is (RD, RT, RA);               -- Possible write back addresses.








    +








    +   type ec_t is record








    +      wbr : wbr_t;                           -- Write back register type.








    +      alu : alu_t;                           -- ALU control signals.








    +      jmp : jmp_t;                           -- Jump/Branch control signals.








    +   end record;








    +








    +   type cc_t is record








    +      mtsr : boolean;                        -- CP0 move to SR enable.








    +      rfe  : boolean;                        -- Restore from exception.








    +   end record;








    +








    +   type dc_t is record








    +      we  : std_logic;                       -- WB forward write enable.








    +   end record;








    +








    +   type de_t is record








    +      cc  : cc_t;                            -- CP0 control.








    +      dc  : dc_t;                            -- Decode Stage control.








    +      ec  : ec_t;                            -- Execution Stage control.








    +      mc  : mc_t;                            -- Memory Stage control.








    +      wc  : wc_t;                            -- Write Back Stage control.








    +      --f   : jadr_t;                        -- J, JAL control signals.








    +      rd  : std_logic_vector(4 downto 0);    -- WB forward destination address.








    +      res : std_logic_vector(31 downto 0);   -- WB forward data.








    +      i   : std_logic_vector(25 downto 0);   -- Instruction (without OP code).








    +   end record;








    +








    +   -----------------------------------------------------------------------------








    +   -- FETCH STAGE                                                             --








    +   -----------------------------------------------------------------------------








    +   type fe_t is record








    +      pc : unsigned(31 downto 2);            -- Program counter.








    +   end record;








    +








    +   -----------------------------------------------------------------------------








    +   -- CO-PROCESSOR 0                                                          --








    +   -----------------------------------------------------------------------------








    +   type sr_t is record








    +      im  : std_logic_vector(7 downto 0);    -- Interrupt mask.








    +      iec : std_logic;                       -- IEc: Interrupt enable current.








    +      iep : std_logic;                       -- IEp: Interrupt enable previous.








    +      ieo : std_logic;                       -- IEo: Interrupt enable old.








    +   end record;








    +








    +   type cp0_t is record








    +      sr  : sr_t;                            -- Status register.








    +      epc : unsigned(29 downto 0);           -- Exception program counter.








    +   end record;








    +








    +end tcpu;








    \ No newline at end of file








    Index: layer2/trunk/vhdl/cpu/rtl/fcpu.vhd








    ===================================================================








    --- layer2/trunk/vhdl/cpu/rtl/fcpu.vhd	(nonexistent)








    +++ layer2/trunk/vhdl/cpu/rtl/fcpu.vhd	(revision 2)








    @@ -0,0 +1,283 @@








    +--------------------------------------------------------------------------------








    +-- MIPS� I CPU - Functions                                                    --








    +--------------------------------------------------------------------------------








    +-- Copyright (C)2011  Mathias H�rtnagl          --








    +--                                                                            --








    +-- This program is free software: you can redistribute it and/or modify       --








    +-- it under the terms of the GNU General Public License as published by       --








    +-- the Free Software Foundation, either version 3 of the License, or          --








    +-- (at your option) any later version.                                        --








    +--                                                                            --








    +-- This program is distributed in the hope that it will be useful,            --








    +-- but WITHOUT ANY WARRANTY; without even the implied warranty of             --








    +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the              --








    +-- GNU General Public License for more details.                               --








    +--                                                                            --








    +-- You should have received a copy of the GNU General Public License          --








    +-- along with this program.  If not, see .      --








    +--------------------------------------------------------------------------------








    +library ieee;








    +use ieee.std_logic_1164.all;








    +use ieee.numeric_std.all;








    +








    +library work;








    +use work.mips1.all;








    +use work.tcpu.all;








    +








    +package fcpu is








    +








    +   -----------------------------------------------------------------------------








    +   -- ALU                                                                     --








    +   -----------------------------------------------------------------------------








    +   function addsub (l,r : std_logic_vector; op : alu_op_t)








    +      return std_logic_vector;








    +   function fslt (l,r : std_logic_vector) return std_logic_vector;








    +   function fsltu (l,r : std_logic_vector) return std_logic_vector;








    +   function fsll (l,s : std_logic_vector) return std_logic_vector;








    +   function fsrl (l,s : std_logic_vector) return std_logic_vector;








    +   function fsra (l,s : std_logic_vector) return std_logic_vector;








    +








    +   -----------------------------------------------------------------------------








    +   -- Extend                                                                  --








    +   -----------------------------------------------------------------------------








    +   function zext (a : std_logic_vector; l : integer) return std_logic_vector;








    +   function sext (a : std_logic_vector; l : integer) return std_logic_vector;








    +








    +   -----------------------------------------------------------------------------








    +   -- Decode                                                                  --








    +   -----------------------------------------------------------------------------








    +   function link (v_i : de_t) return de_t;








    +   function load (v_i : de_t) return de_t;








    +   function store (v_i : de_t) return de_t;








    +   function simm (v_i : de_t) return de_t;








    +   function zimm (v_i : de_t) return de_t;








    +








    +   -----------------------------------------------------------------------------








    +   -- Clear Pipeline                                                          --








    +   -----------------------------------------------------------------------------








    +   function clear (v_i : fe_t) return fe_t;








    +   function clear (v_i : de_t) return de_t;








    +   function clear (v_i : ex_t) return ex_t;








    +   function clear (v_i : me_t) return me_t;








    +








    +   -----------------------------------------------------------------------------








    +   -- Co-Processor 0                                                          --








    +   -----------------------------------------------------------------------------








    +   function clear (v_i : cp0_t) return cp0_t;








    +   function push_ie(v_i : cp0_t) return cp0_t;








    +   function pop_ie(v_i : cp0_t) return cp0_t;








    +   --function set_sr(v_i : cp0_t; v_j : comb_cp0_t) return cp0_t;








    +   function get_sr(v_i : cp0_t) return std_logic_vector;








    +end fcpu;








    +








    +package body fcpu is








    +








    +   -----------------------------------------------------------------------------








    +   -- Adder/Subtractor (signed)                                               --








    +   -----------------------------------------------------------------------------








    +   -- Compound Adder/Subtractor (saves LUTs).








    +   function addsub (l,r : std_logic_vector; op : alu_op_t)








    +   return std_logic_vector is








    +   begin








    +      case op is








    +         when ADD | ADDU => return std_logic_vector(signed(l) + signed(r));








    +         when others     => return std_logic_vector(signed(l) - signed(r));








    +      end case;








    +   end addsub;








    +








    +   -----------------------------------------------------------------------------








    +   -- Set Less Than Functions                                                 --








    +   -----------------------------------------------------------------------------








    +   function fslt (l,r : std_logic_vector) return std_logic_vector is








    +      variable o : std_logic_vector(l'length-1 downto 0) := (others => '0');








    +   begin








    +      if signed(l) < signed(r) then o(0) := '1'; end if;








    +      return o;








    +   end fslt;








    +








    +   function fsltu (l,r : std_logic_vector) return std_logic_vector is








    +      variable o : std_logic_vector(l'length-1 downto 0) := (others => '0');








    +   begin








    +      if unsigned(l) < unsigned(r) then o(0) := '1'; end if;








    +      return o;








    +   end fsltu;








    +








    +   -----------------------------------------------------------------------------








    +   -- Shift (Left, Right Logic, Right Arithmetic)                             --








    +   -----------------------------------------------------------------------------








    +   function fsll (l,s : std_logic_vector) return std_logic_vector is








    +      variable sh : natural range 0 to l'length-1;








    +   begin








    +      sh := to_integer(unsigned(s));








    +      return std_logic_vector(shift_left(unsigned(l), sh));








    +   end fsll;








    +








    +   function fsrl (l,s : std_logic_vector) return std_logic_vector is








    +      variable sh : natural range 0 to l'length-1;








    +   begin








    +      sh := to_integer(unsigned(s));








    +      return std_logic_vector(shift_right(unsigned(l), sh));








    +   end fsrl;








    +








    +   function fsra (l,s : std_logic_vector) return std_logic_vector is








    +      variable sh : natural range 0 to l'length-1;








    +   begin








    +      sh := to_integer(unsigned(s));








    +      return std_logic_vector(shift_right(signed(l), sh));








    +   end fsra;








    +








    +   -----------------------------------------------------------------------------








    +   -- Extend                                                                  --








    +   -----------------------------------------------------------------------------








    +   -- Zero extend vector.








    +   function zext (a : std_logic_vector; l : integer) return std_logic_vector is








    +   begin








    +      return std_logic_vector(resize(unsigned(a), l));








    +   end zext;








    +








    +   -- Sign extend vector.








    +   function sext (a : std_logic_vector; l : integer) return std_logic_vector is








    +   begin








    +      return std_logic_vector(resize(signed(a), l));








    +   end sext;








    +








    +   -----------------------------------------------------------------------------








    +   -- Decode                                                                  --








    +   -----------------------------------------------------------------------------








    +   -- JAL, JRAL, BGEZAL, BLTZAL operations.








    +   function link (v_i : de_t) return de_t is








    +      variable v : de_t := v_i;








    +   begin








    +      v.ec.alu.op    := ADDU;








    +      v.ec.alu.src.a := ADD_4;








    +      v.ec.alu.src.b := PC;








    +      v.wc.we        := '1';








    +      return v;








    +   end link;








    +








    +   -- Memory load operation setter.








    +   function load (v_i : de_t) return de_t is








    +      variable v : de_t := v_i;








    +   begin








    +      v.ec.wbr       := RT;








    +      v.ec.alu.op    := ADDU;








    +      v.ec.alu.src.b := SIGN;








    +      v.mc.src       := MEM;








    +      v.wc.we        := '1';








    +      return v;








    +   end load;








    +








    +   -- Memory store operation setter.








    +   function store (v_i : de_t) return de_t is








    +      variable v : de_t := v_i;








    +   begin








    +      v.ec.alu.op    := ADDU;








    +      v.ec.alu.src.b := SIGN;








    +      v.mc.mem.we    := '1';








    +      return v;








    +   end store;








    +








    +   -- Sign immediate operation setter.








    +   function simm (v_i : de_t) return de_t is








    +      variable v : de_t := v_i;








    +   begin








    +      v.ec.wbr       := RT;








    +      v.ec.alu.src.b := SIGN;








    +      v.wc.we        := '1';








    +      return v;








    +   end simm;








    +








    +   -- Zero immediate operation setter.








    +   function zimm (v_i : de_t) return de_t is








    +      variable v : de_t := v_i;








    +   begin








    +      v.ec.wbr       := RT;








    +      v.ec.alu.src.b := ZERO;








    +      v.wc.we        := '1';








    +      return v;








    +   end zimm;








    +








    +   -----------------------------------------------------------------------------








    +   -- Clear Pipeline                                                          --








    +   -----------------------------------------------------------------------------








    +   function clear (v_i : fe_t) return fe_t is








    +      variable v : fe_t := v_i;








    +   begin








    +      v.pc := (others => '0');








    +      return v;








    +   end clear;








    +








    +   function clear (v_i : de_t) return de_t is








    +      variable v : de_t := v_i;








    +   begin








    +      v.cc.mtsr    := false;








    +      v.cc.rfe     := false;








    +      v.ec.jmp.op  := NOP;








    +      v.mc.mem.we  := '0';








    +      v.mc.mem.byt := NONE;








    +      v.wc.we      := '0';








    +      return v;








    +   end clear;








    +








    +   function clear (v_i : ex_t) return ex_t is








    +      variable v : ex_t := v_i;








    +   begin








    +      v.f.jmp      := '0';








    +      v.mc.mem.we  := '0';








    +      v.mc.mem.byt := NONE;








    +      v.wc.we      := '0';








    +      return v;








    +   end clear;








    +








    +   function clear (v_i : me_t) return me_t is








    +      variable v : me_t := v_i;








    +   begin








    +      v.wc.we := '0';








    +      return v;








    +   end clear;








    +








    +   -----------------------------------------------------------------------------








    +   -- Co-Processor 0                                                          --








    +   -----------------------------------------------------------------------------








    +   -- Clear CP0 status register.








    +   function clear (v_i : cp0_t) return cp0_t is








    +      variable v : cp0_t := v_i;








    +   begin








    +      v.sr.im  := x"00";








    +      v.sr.iec := '0';








    +      v.sr.iep := '0';








    +      v.sr.ieo := '0';








    +      return v;








    +   end clear;








    +








    +   -- Push interrupt enable stack.








    +   function push_ie(v_i : cp0_t) return cp0_t is








    +      variable v : cp0_t := v_i;








    +   begin








    +      v.sr.ieo := v_i.sr.iep;








    +      v.sr.iep := v_i.sr.iec;








    +      v.sr.iec := '0';








    +      return v;








    +   end push_ie;








    +








    +   -- Pop interrupt enable stack.








    +   function pop_ie(v_i : cp0_t) return cp0_t is








    +      variable v : cp0_t := v_i;








    +   begin








    +      v.sr.iec := v_i.sr.iep;








    +      v.sr.iep := v_i.sr.ieo;








    +      return v;








    +   end pop_ie;








    +








    +   -- Get status register.








    +   function get_sr(v_i : cp0_t) return std_logic_vector is








    +      variable v : std_logic_vector(31 downto 0) := (others => '0');








    +   begin








    +      v(15 downto 8) := v_i.sr.im;








    +      v(0)           := v_i.sr.iec;








    +      v(2)           := v_i.sr.iep;








    +      v(4)           := v_i.sr.ieo;








    +      return v;








    +   end get_sr;








    +








    +end fcpu;








    \ No newline at end of file








    Index: layer2/trunk/vhdl/cpu/rtl/iwbm.vhd








    ===================================================================








    --- layer2/trunk/vhdl/cpu/rtl/iwbm.vhd	(nonexistent)








    +++ layer2/trunk/vhdl/cpu/rtl/iwbm.vhd	(revision 2)








    @@ -0,0 +1,40 @@








    +--------------------------------------------------------------------------------








    +-- MIPS� I CPU - Wishbone Master                                              --








    +--------------------------------------------------------------------------------








    +-- Copyright (C)2011  Mathias H�rtnagl          --








    +--                                                                            --








    +-- This program is free software: you can redistribute it and/or modify       --








    +-- it under the terms of the GNU General Public License as published by       --








    +-- the Free Software Foundation, either version 3 of the License, or          --








    +-- (at your option) any later version.                                        --








    +--                                                                            --








    +-- This program is distributed in the hope that it will be useful,            --








    +-- but WITHOUT ANY WARRANTY; without even the implied warranty of             --








    +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the              --








    +-- GNU General Public License for more details.                               --








    +--                                                                            --








    +-- You should have received a copy of the GNU General Public License          --








    +-- along with this program.  If not, see .      --








    +--------------------------------------------------------------------------------








    +library ieee;








    +use ieee.std_logic_1164.all;








    +use ieee.numeric_std.all;








    +








    +library work;








    +use work.icpu.all;








    +use work.iwb.all;








    +








    +package iwbm is








    +








    +   component wbm is








    +      port(








    +         mi  : in  master_in_t;








    +         mo  : out master_out_t;








    +      -- Non Wishbone Signals








    +         ci  : out cpu_in_t;








    +         co  : in  cpu_out_t;








    +         irq : in  std_logic_vector(7 downto 0)








    +      );








    +   end component;








    +








    +end iwbm;








    \ No newline at end of file








    Index: layer2/trunk/vhdl/cpu/rtl








    ===================================================================








    --- layer2/trunk/vhdl/cpu/rtl	(nonexistent)








    +++ layer2/trunk/vhdl/cpu/rtl	(revision 2)
















    
    layer2/trunk/vhdl/cpu/rtl














    Property changes :



    Added: bugtraq:number








    ## -0,0 +1 ##








    +true








    \ No newline at end of property








    Index: layer2/trunk/vhdl/cpu








    ===================================================================








    --- layer2/trunk/vhdl/cpu	(nonexistent)








    +++ layer2/trunk/vhdl/cpu	(revision 2)
















    
    layer2/trunk/vhdl/cpu














    Property changes :



    Added: bugtraq:number








    ## -0,0 +1 ##








    +true








    \ No newline at end of property








    Index: layer2/trunk/vhdl/ddr/bench/ddr_parameters.vh








    ===================================================================








    --- layer2/trunk/vhdl/ddr/bench/ddr_parameters.vh	(nonexistent)








    +++ layer2/trunk/vhdl/ddr/bench/ddr_parameters.vh	(revision 2)








    @@ -0,0 +1,133 @@








    +/****************************************************************************************








    +*








    +*   Disclaimer   This software code and all associated documentation, comments or other








    +*  of Warranty:  information (collectively "Software") is provided "AS IS" without








    +*                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY








    +*                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED








    +*                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES








    +*                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT








    +*                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE








    +*                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.








    +*                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR








    +*                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,








    +*                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE








    +*                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,








    +*                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,








    +*                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,








    +*                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,








    +*                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE








    +*                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH








    +*                DAMAGES. Because some jurisdictions prohibit the exclusion or








    +*                limitation of liability for consequential or incidental damages, the








    +*                above limitation may not apply to you.








    +*








    +*                Copyright 2003 Micron Technology, Inc. All rights reserved.








    +*








    +****************************************************************************************/








    +








    +    // Timing parameters based on Speed Grade 04/07








    +








    +                                          // SYMBOL UNITS DESCRIPTION








    +                                          // ------ ----- -----------








    +`ifdef sg5B                               //              Timing Parameters for -5B (CL = 3)








    +    parameter tCK              =     5.0; // tCK    ns    Nominal Clock Cycle Time








    +    parameter tDQSQ            =     0.4; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access








    +    parameter tMRD             =    10.0; // tMRD   ns    Load Mode Register command cycle time








    +    parameter tRAP             =    15.0; // tRAP   ns    ACTIVE to READ with Auto precharge command








    +    parameter tRAS             =    40.0; // tRAS   ns    Active to Precharge command time








    +    parameter tRC              =    55.0; // tRC    ns    Active to Active/Auto Refresh command time








    +    parameter tRFC             =    70.0; // tRFC   ns    Refresh to Refresh Command interval time








    +    parameter tRCD             =    15.0; // tRCD   ns    Active to Read/Write command time








    +    parameter tRP              =    15.0; // tRP    ns    Precharge command period








    +    parameter tRRD             =    10.0; // tRRD   ns    Active bank a to Active bank b command time








    +    parameter tWR              =    15.0; // tWR    ns    Write recovery time








    +`else `ifdef sg6T                         //              Timing Parameters for -6T (CL = 2.5)








    +    parameter tCK              =     6.0; // tCK    ns    Nominal Clock Cycle Time








    +    parameter tDQSQ            =    0.45; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access








    +    parameter tMRD             =    12.0; // tMRD   ns    Load Mode Register command cycle time








    +    parameter tRAP             =    15.0; // tRAP   ns    ACTIVE to READ with Auto precharge command








    +    parameter tRAS             =    42.0; // tRAS   ns    Active to Precharge command time








    +    parameter tRC              =    60.0; // tRC    ns    Active to Active/Auto Refresh command time








    +    parameter tRFC             =    72.0; // tRFC   ns    Refresh to Refresh Command interval time








    +    parameter tRCD             =    15.0; // tRCD   ns    Active to Read/Write command time








    +    parameter tRP              =    15.0; // tRP    ns    Precharge command period








    +    parameter tRRD             =    12.0; // tRRD   ns    Active bank a to Active bank b command time








    +    parameter tWR              =    15.0; // tWR    ns    Write recovery time








    +`else `ifdef sg6                          //              Timing Parameters for -6 (CL = 2.5)








    +    parameter tCK              =     6.0; // tCK    ns    Nominal Clock Cycle Time








    +    parameter tDQSQ            =     0.4; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access








    +    parameter tMRD             =    12.0; // tMRD   ns    Load Mode Register command cycle time








    +    parameter tRAP             =    15.0; // tRAP   ns    ACTIVE to READ with Auto precharge command








    +    parameter tRAS             =    42.0; // tRAS   ns    Active to Precharge command time








    +    parameter tRC              =    60.0; // tRC    ns    Active to Active/Auto Refresh command time








    +    parameter tRFC             =    72.0; // tRFC   ns    Refresh to Refresh Command interval time








    +    parameter tRCD             =    15.0; // tRCD   ns    Active to Read/Write command time








    +    parameter tRP              =    15.0; // tRP    ns    Precharge command period








    +    parameter tRRD             =    12.0; // tRRD   ns    Active bank a to Active bank b command time








    +    parameter tWR              =    15.0; // tWR    ns    Write recovery time








    +`else `ifdef sg75E                        //              Timing Parameters for -75E (CL = 2)








    +    parameter tCK              =     7.5; // tCK    ns    Nominal Clock Cycle Time








    +    parameter tDQSQ            =     0.5; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access








    +    parameter tMRD             =    15.0; // tMRD   ns    Load Mode Register command cycle time








    +    parameter tRAP             =    15.0; // tRAP   ns    ACTIVE to READ with Auto precharge command








    +    parameter tRAS             =    40.0; // tRAS   ns    Active to Precharge command time








    +    parameter tRC              =    60.0; // tRC    ns    Active to Active/Auto Refresh command time








    +    parameter tRFC             =    75.0; // tRFC   ns    Refresh to Refresh Command interval time








    +    parameter tRCD             =    15.0; // tRCD   ns    Active to Read/Write command time








    +    parameter tRP              =    15.0; // tRP    ns    Precharge command period








    +    parameter tRRD             =    15.0; // tRRD   ns    Active bank a to Active bank b command time








    +    parameter tWR              =    15.0; // tWR    ns    Write recovery time








    +`else `ifdef sg75Z                        //              Timing Parameters for -75Z (CL = 2)








    +    parameter tCK              =     7.5; // tCK    ns    Nominal Clock Cycle Time








    +    parameter tDQSQ            =     0.5; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access








    +    parameter tMRD             =    15.0; // tMRD   ns    Load Mode Register command cycle time








    +    parameter tRAP             =    20.0; // tRAP   ns    ACTIVE to READ with Auto precharge command








    +    parameter tRAS             =    40.0; // tRAS   ns    Active to Precharge command time








    +    parameter tRC              =    65.0; // tRC    ns    Active to Active/Auto Refresh command time








    +    parameter tRFC             =    75.0; // tRFC   ns    Refresh to Refresh Command interval time








    +    parameter tRCD             =    20.0; // tRCD   ns    Active to Read/Write command time








    +    parameter tRP              =    20.0; // tRP    ns    Precharge command period








    +    parameter tRRD             =    15.0; // tRRD   ns    Active bank a to Active bank b command time








    +    parameter tWR              =    15.0; // tWR    ns    Write recovery time








    +`else `define sg75                        //              Timing Parameters for -75 (CL = 2.5)








    +    parameter tCK              =     7.5; // tCK    ns    Nominal Clock Cycle Time








    +    parameter tDQSQ            =     0.5; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access








    +    parameter tMRD             =    15.0; // tMRD   ns    Load Mode Register command cycle time








    +    parameter tRAP             =    20.0; // tRAP   ns    ACTIVE to READ with Auto precharge command








    +    parameter tRAS             =    40.0; // tRAS   ns    Active to Precharge command time








    +    parameter tRC              =    65.0; // tRC    ns    Active to Active/Auto Refresh command time








    +    parameter tRFC             =    75.0; // tRFC   ns    Refresh to Refresh Command interval time








    +    parameter tRCD             =    20.0; // tRCD   ns    Active to Read/Write command time








    +    parameter tRP              =    20.0; // tRP    ns    Precharge command period








    +    parameter tRRD             =    15.0; // tRRD   ns    Active bank a to Active bank b command time








    +    parameter tWR              =    15.0; // tWR    ns    Write recovery time








    +`endif `endif `endif `endif `endif








    +








    +    // Size Parameters based on Part Width








    +








    +`ifdef x4








    +    parameter ADDR_BITS        =      13; // Set this parameter to control how many Address bits are used








    +    parameter DQ_BITS          =       4; // Set this parameter to control how many Data bits are used








    +    parameter DQS_BITS         =       1; // Set this parameter to control how many DQS bits are used








    +    parameter DM_BITS          =       1; // Set this parameter to control how many DM bits are used








    +    parameter COL_BITS         =      12; // Set this parameter to control how many Column bits are used








    +`else `ifdef x8








    +    parameter ADDR_BITS        =      13; // Set this parameter to control how many Address bits are used








    +    parameter DQ_BITS          =       8; // Set this parameter to control how many Data bits are used








    +    parameter DQS_BITS         =       1; // Set this parameter to control how many DQS bits are used








    +    parameter DM_BITS          =       1; // Set this parameter to control how many DM bits are used








    +    parameter COL_BITS         =      11; // Set this parameter to control how many Column bits are used








    +`else `define x16








    +    parameter ADDR_BITS        =      13; // Set this parameter to control how many Address bits are used








    +    parameter DQ_BITS          =      16; // Set this parameter to control how many Data bits are used








    +    parameter DQS_BITS         =       2; // Set this parameter to control how many DQS bits are used








    +    parameter DM_BITS          =       2; // Set this parameter to control how many DM bits are used








    +    parameter COL_BITS         =      10; // Set this parameter to control how many Column bits are used








    +`endif `endif








    +








    +    parameter BA_BITS          =       2; // Set this parmaeter to control how many Bank Address bits are used








    +    parameter full_mem_bits    = BA_BITS+ADDR_BITS+COL_BITS; // Set this parameter to control how many unique addresses are used








    +    parameter part_mem_bits    = 10;                   // Set this parameter to control how many unique addresses are used








    +








    +    parameter no_halt          =       1; // If set to 1, the model won't halt on command sequence/major errors








    +    parameter DEBUG            =       1; // Turn on DEBUG message








    Index: layer2/trunk/vhdl/ddr/bench/ddr.v








    ===================================================================








    --- layer2/trunk/vhdl/ddr/bench/ddr.v	(nonexistent)








    +++ layer2/trunk/vhdl/ddr/bench/ddr.v	(revision 2)








    @@ -0,0 +1,1438 @@








    +/****************************************************************************************








    +*








    +*    File Name:  ddr.v








    +*      Version:  6.00








    +*        Model:  BUS Functional








    +*








    +* Dependencies:  ddr_parameters.v








    +*








    +*  Description:  Micron SDRAM DDR (Double Data Rate)








    +*








    +*   Limitation:  - Doesn't check for 8K-cycle refresh.








    +*                - Doesn't check power-down entry/exit








    +*                - Doesn't check self-refresh entry/exit.








    +*








    +*         Note:  - Set simulator resolution to "ps" accuracy








    +*                - Set DEBUG = 0 to disable $display messages








    +*                - Model assume Clk and Clk# crossing at both edge








    +*








    +*   Disclaimer   This software code and all associated documentation, comments or other








    +*  of Warranty:  information (collectively "Software") is provided "AS IS" without








    +*                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY








    +*                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED








    +*                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES








    +*                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT








    +*                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE








    +*                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.








    +*                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR








    +*                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,








    +*                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE








    +*                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,








    +*                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,








    +*                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,








    +*                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,








    +*                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE








    +*                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH








    +*                DAMAGES. Because some jurisdictions prohibit the exclusion or








    +*                limitation of liability for consequential or incidental damages, the








    +*                above limitation may not apply to you.








    +*








    +*                Copyright 2003 Micron Technology, Inc. All rights reserved.








    +*








    +* Rev  Author Date        Changes








    +* ---  ------ ----------  ---------------------------------------








    +* 2.1   SPH    03/19/2002  - Second Release








    +*                          - Fix tWR and several incompatability








    +*                            between different simulators








    +* 3.0   TFK    02/18/2003  - Added tDSS and tDSH timing checks.








    +*                          - Added tDQSH and tDQSL timing checks.








    +* 3.1   CAH    05/28/2003  - update all models to release version 3.1








    +*                            (no changes to this model)








    +* 3.2   JMK    06/16/2003  - updated all DDR400 models to support CAS Latency 3








    +* 3.3   JMK    09/11/2003  - Added initialization sequence checks.








    +* 4.0   JMK    12/01/2003  - Grouped parameters into "ddr_parameters.v"








    +*                          - Fixed tWTR check








    +* 4.1   JMK    01/14/2004  - Grouped specify parameters by speed grade








    +*                          - Fixed mem_sizes parameter








    +* 4.2   JMK    03/19/2004  - Fixed pulse width checking on Dqs








    +* 4.3   JMK    04/27/2004  - Changed BL wire size in tb module








    +*                          - Changed Dq_buf size to [15:0]








    +* 5.0   JMK    06/16/2004  - Added read to write checking.








    +*                          - Added read with precharge truncation to write checking.








    +*                          - Added associative memory array to reduce memory consumption.








    +*                          - Added checking for required DQS edges during write.








    +* 5.1   JMK    08/16/2004  - Fixed checking for required DQS edges during write.








    +*                          - Fixed wdqs_valid window.








    +* 5.2   JMK    09/24/2004  - Read or Write without activate will be ignored.








    +* 5.3   JMK    10/27/2004  - Added tMRD checking during Auto Refresh and Activate.








    +*                          - Added tRFC checking during Load Mode and Precharge.








    +* 5.4   JMK    12/13/2004  - The model will not respond to illegal command sequences.








    +* 5.5   SPH    01/13/2005  - The model will issue a halt on illegal command sequences.








    +*       JMK    02/11/2005  - Changed the display format for numbers to hex.








    +* 5.6   JMK    04/22/2005  - Fixed Write with auto precharge calculation.








    +* 5.7   JMK    08/05/2005  - Changed conditions for read with precharge truncation error.








    +*                          - Renamed parameters file with .vh extension.








    +* 5.8   BAS    12/26/2006  - Added parameters for T46A part - 256Mb








    +*                          - Added x32 functionality








    +* 6.00  JMK    05/31/2007  - Added ddr_184_dimm module model








    +* 6.00  BAS    05/31/2007  - Updated 128Mb, 256Mb, 512Mb, and 1024Mb parameter sheets








    +****************************************************************************************/








    +`define sg6T








    +`define x16








    +








    +// DO NOT CHANGE THE TIMESCALE








    +// MAKE SURE YOUR SIMULATOR USE "PS" RESOLUTION








    +`timescale 1ns / 1ps








    +








    +module model_ddr (Clk, Clk_n, Cke, Cs_n, Ras_n, Cas_n, We_n, Ba , Addr, Dm, Dq, Dqs);








    +    `include "ddr_parameters.vh"








    +








    +    // Port Declarations








    +    input                         Clk;








    +    input                         Clk_n;








    +    input                         Cke;








    +    input                         Cs_n;








    +    input                         Ras_n;








    +    input                         Cas_n;








    +    input                         We_n;








    +    input                 [1 : 0] Ba;








    +    input     [ADDR_BITS - 1 : 0] Addr;








    +    input       [DM_BITS - 1 : 0] Dm;








    +    inout       [DQ_BITS - 1 : 0] Dq;








    +    inout      [DQS_BITS - 1 : 0] Dqs;








    +








    +    // Internal Wires (fixed width)








    +    wire                 [31 : 0] Dq_in;








    +    wire                  [3 : 0] Dqs_in;








    +    wire                  [3 : 0] Dm_in;








    +








    +    assign Dq_in   [DQ_BITS - 1 : 0] = Dq;








    +    assign Dqs_in [DQS_BITS - 1 : 0] = Dqs;








    +    assign Dm_in   [DM_BITS - 1 : 0] = Dm;








    +








    +    // Data pair








    +    reg                  [31 : 0] dq_rise;








    +    reg                   [3 : 0] dm_rise;








    +    reg                  [31 : 0] dq_fall;








    +    reg                   [3 : 0] dm_fall;








    +    reg                   [7 : 0] dm_pair;








    +    reg                  [31 : 0] Dq_buf;








    +








    +    // Mode Register








    +    reg       [ADDR_BITS - 1 : 0] Mode_reg;








    +








    +    // Internal System Clock








    +    reg                           CkeZ, Sys_clk;








    +








    +    // Internal Dqs initialize








    +    reg                           Dqs_int;








    +








    +    // Dqs buffer








    +    reg        [DQS_BITS - 1 : 0] Dqs_out;








    +








    +    // Dq buffer








    +    reg         [DQ_BITS - 1 : 0] Dq_out;








    +








    +    // Read pipeline variables








    +    reg                           Read_cmnd [0 : 6];








    +    reg                   [1 : 0] Read_bank [0 : 6];








    +    reg        [COL_BITS - 1 : 0] Read_cols [0 : 6];








    +








    +    // Write pipeline variables








    +    reg                           Write_cmnd [0 : 3];








    +    reg                   [1 : 0] Write_bank [0 : 3];








    +    reg        [COL_BITS - 1 : 0] Write_cols [0 : 3];








    +








    +    // Auto precharge variables








    +    reg                           Read_precharge  [0 : 3];








    +    reg                           Write_precharge [0 : 3];








    +    integer                       Count_precharge [0 : 3];








    +








    +    // Manual precharge variables








    +    reg                           A10_precharge  [0 : 6];








    +    reg                   [1 : 0] Bank_precharge [0 : 6];








    +    reg                           Cmnd_precharge [0 : 6];








    +








    +    // Burst terminate variables








    +    reg                           Cmnd_bst [0 : 6];








    +








    +    // Memory Banks








    +`ifdef FULL_MEM








    +    reg         [DQ_BITS - 1 : 0] mem_array  [0 : (1<= 2) begin








    +                            if (DEBUG) $display ("%m: at time %t MEMORY:  Power Up and Initialization Sequence is complete", $time);








    +                            power_up_done = 1;








    +                        end else begin








    +                            aref_count = 0;








    +                            @ (aref_count >= 2) begin








    +                                if (DEBUG) $display ("%m: at time %t MEMORY:  Power Up and Initialization Sequence is complete", $time);








    +                                power_up_done = 1;








    +                            end








    +                        end








    +                    end








    +                end








    +            end








    +        end








    +    end








    +








    +    // Write Memory








    +    task write_mem;








    +        input [full_mem_bits - 1 : 0] addr;








    +        input       [DQ_BITS - 1 : 0] data;








    +        reg       [part_mem_bits : 0] i;








    +        begin








    +`ifdef FULL_MEM








    +            mem_array[addr] = data;








    +`else








    +            begin : loop








    +                for (i = 0; i < mem_used; i = i + 1) begin








    +                    if (addr_array[i] === addr) begin








    +                        disable loop;








    +                    end








    +                end








    +            end








    +            if (i === mem_used) begin








    +                if (i === (1<= burst_length) begin








    +            Data_in_enable = 1'b0;








    +            Data_out_enable = 1'b0;








    +            read_precharge_truncation = 4'h0;








    +        end








    +








    +    end








    +    endtask








    +








    +    // Manual Precharge Pipeline








    +    task Manual_Precharge_Pipeline;








    +    begin








    +        // A10 Precharge Pipeline








    +        A10_precharge[0] = A10_precharge[1];








    +        A10_precharge[1] = A10_precharge[2];








    +        A10_precharge[2] = A10_precharge[3];








    +        A10_precharge[3] = A10_precharge[4];








    +        A10_precharge[4] = A10_precharge[5];








    +        A10_precharge[5] = A10_precharge[6];








    +        A10_precharge[6] = 1'b0;








    +








    +        // Bank Precharge Pipeline








    +        Bank_precharge[0] = Bank_precharge[1];








    +        Bank_precharge[1] = Bank_precharge[2];








    +        Bank_precharge[2] = Bank_precharge[3];








    +        Bank_precharge[3] = Bank_precharge[4];








    +        Bank_precharge[4] = Bank_precharge[5];








    +        Bank_precharge[5] = Bank_precharge[6];








    +        Bank_precharge[6] = 2'b0;








    +








    +        // Command Precharge Pipeline








    +        Cmnd_precharge[0] = Cmnd_precharge[1];








    +        Cmnd_precharge[1] = Cmnd_precharge[2];








    +        Cmnd_precharge[2] = Cmnd_precharge[3];








    +        Cmnd_precharge[3] = Cmnd_precharge[4];








    +        Cmnd_precharge[4] = Cmnd_precharge[5];








    +        Cmnd_precharge[5] = Cmnd_precharge[6];








    +        Cmnd_precharge[6] = 1'b0;








    +








    +        // Terminate a Read if same bank or all banks








    +        if (Cmnd_precharge[0] === 1'b1) begin








    +            if (Bank_precharge[0] === Bank_addr || A10_precharge[0] === 1'b1) begin








    +                if (Data_out_enable === 1'b1) begin








    +                    Data_out_enable = 1'b0;








    +                    read_precharge_truncation = 4'hF;








    +                end








    +            end








    +        end








    +    end








    +    endtask








    +








    +    // Burst Terminate Pipeline








    +    task Burst_Terminate_Pipeline;








    +    begin








    +        // Command Precharge Pipeline








    +        Cmnd_bst[0] = Cmnd_bst[1];








    +        Cmnd_bst[1] = Cmnd_bst[2];








    +        Cmnd_bst[2] = Cmnd_bst[3];








    +        Cmnd_bst[3] = Cmnd_bst[4];








    +        Cmnd_bst[4] = Cmnd_bst[5];








    +        Cmnd_bst[5] = Cmnd_bst[6];








    +        Cmnd_bst[6] = 1'b0;








    +








    +        // Terminate a Read regardless of banks








    +        if (Cmnd_bst[0] === 1'b1 && Data_out_enable === 1'b1) begin








    +            Data_out_enable = 1'b0;








    +        end








    +    end








    +    endtask








    +








    +    // Dq and Dqs Drivers








    +    task Dq_Dqs_Drivers;








    +    begin








    +        // read command pipeline








    +        Read_cmnd [0] = Read_cmnd [1];








    +        Read_cmnd [1] = Read_cmnd [2];








    +        Read_cmnd [2] = Read_cmnd [3];








    +        Read_cmnd [3] = Read_cmnd [4];








    +        Read_cmnd [4] = Read_cmnd [5];








    +        Read_cmnd [5] = Read_cmnd [6];








    +        Read_cmnd [6] = 1'b0;








    +








    +        // read bank pipeline








    +        Read_bank [0] = Read_bank [1];








    +        Read_bank [1] = Read_bank [2];








    +        Read_bank [2] = Read_bank [3];








    +        Read_bank [3] = Read_bank [4];








    +        Read_bank [4] = Read_bank [5];








    +        Read_bank [5] = Read_bank [6];








    +        Read_bank [6] = 2'b0;








    +








    +        // read column pipeline








    +        Read_cols [0] = Read_cols [1];








    +        Read_cols [1] = Read_cols [2];








    +        Read_cols [2] = Read_cols [3];








    +        Read_cols [3] = Read_cols [4];








    +        Read_cols [4] = Read_cols [5];








    +        Read_cols [5] = Read_cols [6];








    +        Read_cols [6] = 0;








    +








    +        // Initialize Read command








    +        if (Read_cmnd [0] === 1'b1) begin








    +            Data_out_enable = 1'b1;








    +            Bank_addr = Read_bank [0];








    +            Cols_addr = Read_cols [0];








    +            Cols_brst = Cols_addr [2 : 0];








    +            Burst_counter = 0;








    +








    +            // Row Address Mux








    +            case (Bank_addr)








    +                2'd0    : Rows_addr = B0_row_addr;








    +                2'd1    : Rows_addr = B1_row_addr;








    +                2'd2    : Rows_addr = B2_row_addr;








    +                2'd3    : Rows_addr = B3_row_addr;








    +                default : $display ("At time %t ERROR: Invalid Bank Address", $time);








    +            endcase








    +        end








    +








    +        // Toggle Dqs during Read command








    +        if (Data_out_enable === 1'b1) begin








    +            Dqs_int = 1'b0;








    +            if (Dqs_out === {DQS_BITS{1'b0}}) begin








    +                Dqs_out = {DQS_BITS{1'b1}};








    +            end else if (Dqs_out === {DQS_BITS{1'b1}}) begin








    +                Dqs_out = {DQS_BITS{1'b0}};








    +            end else begin








    +                Dqs_out = {DQS_BITS{1'b0}};








    +            end








    +        end else if (Data_out_enable === 1'b0 && Dqs_int === 1'b0) begin








    +            Dqs_out = {DQS_BITS{1'bz}};








    +        end








    +








    +        // Initialize dqs for Read command








    +        if (Read_cmnd [2] === 1'b1) begin








    +            if (Data_out_enable === 1'b0) begin








    +                Dqs_int = 1'b1;








    +                Dqs_out = {DQS_BITS{1'b0}};








    +            end








    +        end








    +








    +        // Read latch








    +        if (Data_out_enable === 1'b1) begin








    +            // output data








    +            read_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_out);








    +            if (DEBUG) begin








    +                $display ("At time %t READ : Bank = %h, Row = %h, Col = %h, Data = %h", $time, Bank_addr, Rows_addr, Cols_addr, Dq_out);








    +            end








    +        end else begin








    +            Dq_out = {DQ_BITS{1'bz}};








    +        end








    +    end








    +    endtask








    +








    +    // Write FIFO and DM Mask Logic








    +    task Write_FIFO_DM_Mask_Logic;








    +    begin








    +        // Write command pipeline








    +        Write_cmnd [0] = Write_cmnd [1];








    +        Write_cmnd [1] = Write_cmnd [2];








    +        Write_cmnd [2] = Write_cmnd [3];








    +        Write_cmnd [3] = 1'b0;








    +








    +        // Write command pipeline








    +        Write_bank [0] = Write_bank [1];








    +        Write_bank [1] = Write_bank [2];








    +        Write_bank [2] = Write_bank [3];








    +        Write_bank [3] = 2'b0;








    +








    +        // Write column pipeline








    +        Write_cols [0] = Write_cols [1];








    +        Write_cols [1] = Write_cols [2];








    +        Write_cols [2] = Write_cols [3];








    +        Write_cols [3] = {COL_BITS{1'b0}};








    +








    +        // Initialize Write command








    +        if (Write_cmnd [0] === 1'b1) begin








    +            Data_in_enable = 1'b1;








    +            Bank_addr = Write_bank [0];








    +            Cols_addr = Write_cols [0];








    +            Cols_brst = Cols_addr [2 : 0];








    +            Burst_counter = 0;








    +








    +            // Row address mux








    +            case (Bank_addr)








    +                2'd0    : Rows_addr = B0_row_addr;








    +                2'd1    : Rows_addr = B1_row_addr;








    +                2'd2    : Rows_addr = B2_row_addr;








    +                2'd3    : Rows_addr = B3_row_addr;








    +                default : $display ("At time %t ERROR: Invalid Row Address", $time);








    +            endcase








    +        end








    +








    +        // Write data








    +        if (Data_in_enable === 1'b1) begin








    +








    +            // Data Buffer








    +            read_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_buf);








    +








    +            // write negedge Dqs on posedge Sys_clk








    +            if (Sys_clk) begin








    +                if (!dm_fall[0]) begin








    +                    Dq_buf [ 7 : 0] = dq_fall [ 7 : 0];








    +                end








    +                if (!dm_fall[1]) begin








    +                    Dq_buf [15 : 8] = dq_fall [15 : 8];








    +                end








    +                if (!dm_fall[2]) begin








    +                    Dq_buf [23 : 16] = dq_fall [23 : 16];








    +                end








    +                if (!dm_fall[3]) begin








    +                    Dq_buf [31 : 24] = dq_fall [31 : 24];








    +                end








    +                if (~&dm_fall) begin








    +                    if (DEBUG) begin








    +                        $display ("At time %t WRITE: Bank = %h, Row = %h, Col = %h, Data = %h", $time, Bank_addr, Rows_addr, Cols_addr, Dq_buf[DQ_BITS-1:0]);








    +                    end








    +                end








    +            // write posedge Dqs on negedge Sys_clk








    +            end else begin








    +                if (!dm_rise[0]) begin








    +                    Dq_buf [ 7 : 0] = dq_rise [ 7 : 0];








    +                end








    +                if (!dm_rise[1]) begin








    +                    Dq_buf [15 : 8] = dq_rise [15 : 8];








    +                end








    +                if (!dm_rise[2]) begin








    +                    Dq_buf [23 : 16] = dq_rise [23 : 16];








    +                end








    +                if (!dm_rise[3]) begin








    +                    Dq_buf [31 : 24] = dq_rise [31 : 24];








    +                end








    +                if (~&dm_rise) begin








    +                    if (DEBUG) begin








    +                        $display ("At time %t WRITE: Bank = %h, Row = %h, Col = %h, Data = %h", $time, Bank_addr, Rows_addr, Cols_addr, Dq_buf[DQ_BITS-1:0]);








    +                    end








    +                end








    +            end








    +








    +            // Write Data








    +            write_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_buf);








    +








    +            // tWR start and tWTR check








    +            if (Sys_clk && &dm_pair === 1'b0)  begin








    +                case (Bank_addr)








    +                    2'd0    : WR_chk0 = $time;








    +                    2'd1    : WR_chk1 = $time;








    +                    2'd2    : WR_chk2 = $time;








    +                    2'd3    : WR_chk3 = $time;








    +                    default : $display ("At time %t ERROR: Invalid Bank Address (tWR)", $time);








    +                endcase








    +








    +                // tWTR check








    +                if (Read_enable === 1'b1) begin








    +                    $display ("At time %t ERROR: tWTR violation during Read", $time);








    +                end








    +            end








    +        end








    +    end








    +    endtask








    +








    +    // Auto Precharge Calculation








    +    task Auto_Precharge_Calculation;








    +    begin








    +        // Precharge counter








    +        if (Read_precharge [0] === 1'b1 || Write_precharge [0] === 1'b1) begin








    +            Count_precharge [0] = Count_precharge [0] + 1;








    +        end








    +        if (Read_precharge [1] === 1'b1 || Write_precharge [1] === 1'b1) begin








    +            Count_precharge [1] = Count_precharge [1] + 1;








    +        end








    +        if (Read_precharge [2] === 1'b1 || Write_precharge [2] === 1'b1) begin








    +            Count_precharge [2] = Count_precharge [2] + 1;








    +        end








    +        if (Read_precharge [3] === 1'b1 || Write_precharge [3] === 1'b1) begin








    +            Count_precharge [3] = Count_precharge [3] + 1;








    +        end








    +








    +        // Read with AutoPrecharge Calculation








    +        //      The device start internal precharge when:








    +        //          1.  Meet tRAS requirement








    +        //          2.  BL/2 cycles after command








    +        if ((Read_precharge[0] === 1'b1) && ($time - RAS_chk0 >= tRAS)) begin








    +            if (Count_precharge[0] >= burst_length/2) begin








    +                Pc_b0 = 1'b1;








    +                Act_b0 = 1'b0;








    +                RP_chk0 = $time;








    +                Read_precharge[0] = 1'b0;








    +            end








    +        end








    +        if ((Read_precharge[1] === 1'b1) && ($time - RAS_chk1 >= tRAS)) begin








    +            if (Count_precharge[1] >= burst_length/2) begin








    +                Pc_b1 = 1'b1;








    +                Act_b1 = 1'b0;








    +                RP_chk1 = $time;








    +                Read_precharge[1] = 1'b0;








    +            end








    +        end








    +        if ((Read_precharge[2] === 1'b1) && ($time - RAS_chk2 >= tRAS)) begin








    +            if (Count_precharge[2] >= burst_length/2) begin








    +                Pc_b2 = 1'b1;








    +                Act_b2 = 1'b0;








    +                RP_chk2 = $time;








    +                Read_precharge[2] = 1'b0;








    +            end








    +        end








    +        if ((Read_precharge[3] === 1'b1) && ($time - RAS_chk3 >= tRAS)) begin








    +            if (Count_precharge[3] >= burst_length/2) begin








    +                Pc_b3 = 1'b1;








    +                Act_b3 = 1'b0;








    +                RP_chk3 = $time;








    +                Read_precharge[3] = 1'b0;








    +            end








    +        end








    +








    +        // Write with AutoPrecharge Calculation








    +        //      The device start internal precharge when:








    +        //          1.  Meet tRAS requirement








    +        //          2.  Write Latency PLUS BL/2 cycles PLUS tWR after Write command








    +








    +        if ((Write_precharge[0] === 1'b1) && ($time - RAS_chk0 >= tRAS)) begin








    +            if ((Count_precharge[0] >= burst_length/2+1) && ($time - WR_chk0 >= tWR)) begin








    +                Pc_b0 = 1'b1;








    +                Act_b0 = 1'b0;








    +                RP_chk0 = $time;








    +                Write_precharge[0] = 1'b0;








    +            end








    +        end








    +        if ((Write_precharge[1] === 1'b1) && ($time - RAS_chk1 >= tRAS)) begin








    +            if ((Count_precharge[1] >= burst_length/2+1) && ($time - WR_chk1 >= tWR)) begin








    +                Pc_b1 = 1'b1;








    +                Act_b1 = 1'b0;








    +                RP_chk1 = $time;








    +                Write_precharge[1] = 1'b0;








    +            end








    +        end








    +        if ((Write_precharge[2] === 1'b1) && ($time - RAS_chk2 >= tRAS)) begin








    +            if ((Count_precharge[2] >= burst_length/2+1) && ($time - WR_chk2 >= tWR)) begin








    +                Pc_b2 = 1'b1;








    +                Act_b2 = 1'b0;








    +                RP_chk2 = $time;








    +                Write_precharge[2] = 1'b0;








    +            end








    +        end








    +        if ((Write_precharge[3] === 1'b1) && ($time - RAS_chk3 >= tRAS)) begin








    +            if ((Count_precharge[3] >= burst_length/2+1) && ($time - WR_chk3 >= tWR)) begin








    +                Pc_b3 = 1'b1;








    +                Act_b3 = 1'b0;








    +                RP_chk3 = $time;








    +                Write_precharge[3] = 1'b0;








    +            end








    +        end








    +    end








    +    endtask








    +








    +    // DLL Counter








    +    task DLL_Counter;








    +    begin








    +        if (DLL_reset === 1'b1 && DLL_done === 1'b0) begin








    +            DLL_count = DLL_count + 1;








    +            if (DLL_count >= 200) begin








    +                DLL_done = 1'b1;








    +            end








    +        end








    +    end








    +    endtask








    +








    +    // Control Logic








    +    task Control_Logic;








    +    begin








    +        // Auto Refresh








    +        if (Aref_enable === 1'b1) begin








    +            // Display DEBUG Message








    +            if (DEBUG) begin








    +                $display ("At time %t AREF : Auto Refresh", $time);








    +            end








    +








    +            // Precharge to Auto Refresh








    +            if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) ||








    +                ($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin








    +                $display ("At time %t ERROR: tRP violation during Auto Refresh", $time);








    +            end








    +








    +            // LMR/EMR to Auto Refresh








    +            if ($time - MRD_chk < tMRD) begin








    +                $display ("At time %t ERROR: tMRD violation during Auto Refresh", $time);








    +            end








    +








    +            // Auto Refresh to Auto Refresh








    +            if ($time - RFC_chk < tRFC) begin








    +                $display ("At time %t ERROR: tRFC violation during Auto Refresh", $time);








    +            end








    +








    +            // Precharge to Auto Refresh








    +            if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin








    +                $display ("At time %t ERROR: All banks must be Precharged before Auto Refresh", $time);








    +                if (!no_halt) $stop (0);








    +            end else begin








    +                aref_count = aref_count + 1;








    +                RFC_chk = $time;








    +            end








    +        end








    +








    +        // Extended Mode Register








    +        if (Ext_mode_enable === 1'b1) begin








    +            if (DEBUG) begin








    +                $display ("At time %t EMR  : Extended Mode Register", $time);








    +            end








    +








    +            // Precharge to LMR/EMR








    +            if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) ||








    +                ($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin








    +                $display ("At time %t ERROR: tRP violation during Extended Mode Register", $time);








    +            end








    +








    +            // LMR/EMR to LMR/EMR








    +            if ($time - MRD_chk < tMRD) begin








    +                $display ("At time %t ERROR: tMRD violation during Extended Mode Register", $time);








    +            end








    +








    +            // Auto Refresh to LMR/EMR








    +            if ($time - RFC_chk < tRFC) begin








    +                $display ("At time %t ERROR: tRFC violation during Extended Mode Register", $time);








    +            end








    +








    +            // Precharge to LMR/EMR








    +            if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin








    +                $display ("At time %t ERROR: all banks must be Precharged before Extended Mode Register", $time);








    +                if (!no_halt) $stop (0);








    +            end else begin








    +                if (Addr[0] === 1'b0) begin








    +                    DLL_enable = 1'b1;








    +                    if (DEBUG) begin








    +                        $display ("At time %t EMR  : Enable DLL", $time);








    +                    end








    +                end else begin








    +                    DLL_enable = 1'b0;








    +                    if (DEBUG) begin








    +                        $display ("At time %t EMR  : Disable DLL", $time);








    +                    end








    +                end








    +                MRD_chk = $time;








    +            end








    +        end








    +








    +        // Load Mode Register








    +        if (Mode_reg_enable === 1'b1) begin








    +            if (DEBUG) begin








    +                $display ("At time %t LMR  : Load Mode Register", $time);








    +            end








    +








    +            // Precharge to LMR/EMR








    +            if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) ||








    +                ($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin








    +                $display ("At time %t ERROR: tRP violation during Load Mode Register", $time);








    +            end








    +








    +            // LMR/EMR to LMR/EMR








    +            if ($time - MRD_chk < tMRD) begin








    +                $display ("At time %t ERROR: tMRD violation during Load Mode Register", $time);








    +            end








    +








    +            // Auto Refresh to LMR/EMR








    +            if ($time - RFC_chk < tRFC) begin








    +                $display ("At time %t ERROR: tRFC violation during Load Mode Register", $time);








    +            end








    +








    +            // Precharge to LMR/EMR








    +            if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin








    +                $display ("At time %t ERROR: all banks must be Precharged before Load Mode Register", $time);








    +            end else begin








    +                // Register Mode








    +                Mode_reg = Addr;








    +








    +                // DLL Reset








    +                if (DLL_enable === 1'b1 && Addr [8] === 1'b1) begin








    +                    DLL_reset = 1'b1;








    +                    DLL_done = 1'b0;








    +                    DLL_count = 0;








    +                end else if (DLL_enable === 1'b1 && DLL_reset === 1'b0 && Addr [8] === 1'b0) begin








    +                    $display ("At time %t ERROR: DLL is ENABLE: DLL RESET is required.", $time);








    +                end else if (DLL_enable === 1'b0 && Addr [8] === 1'b1) begin








    +                    $display ("At time %t ERROR: DLL is DISABLE: DLL RESET will be ignored.", $time);








    +                end








    +








    +                // Burst Length








    +                case (Addr [2 : 0])








    +                    3'b001  : $display ("At time %t LMR  : Burst Length = 2", $time);








    +                    3'b010  : $display ("At time %t LMR  : Burst Length = 4", $time);








    +                    3'b011  : $display ("At time %t LMR  : Burst Length = 8", $time);








    +                    default : $display ("At time %t ERROR: Burst Length not supported", $time);








    +                endcase








    +








    +                // CAS Latency








    +                case (Addr [6 : 4])








    +                    3'b010  : $display ("At time %t LMR  : CAS Latency = 2", $time);








    +                    3'b110  : $display ("At time %t LMR  : CAS Latency = 2.5", $time);








    +                    3'b011  : $display ("At time %t LMR  : CAS Latency = 3", $time);








    +                    default : $display ("At time %t ERROR: CAS Latency not supported", $time);








    +                endcase








    +








    +                // Record current tMRD time








    +                MRD_chk = $time;








    +            end








    +        end








    +








    +        // Activate Block








    +        if (Active_enable === 1'b1) begin








    +            if (!(power_up_done)) begin








    +                $display ("%m: at time %t ERROR: Power Up and Initialization Sequence not completed before executing Activate command", $time);








    +            end








    +            // Display DEBUG Message








    +            if (DEBUG) begin








    +                $display ("At time %t ACT  : Bank = %h, Row = %h", $time, Ba, Addr);








    +            end








    +








    +            // Activate to Activate (different bank)








    +            if ((Prev_bank != Ba) && ($time - RRD_chk < tRRD)) begin








    +                $display ("At time %t ERROR: tRRD violation during Activate bank %h", $time, Ba);








    +            end








    +








    +            // LMR/EMR to Activate








    +            if ($time - MRD_chk < tMRD) begin








    +                $display ("At time %t ERROR: tMRD violation during Activate bank %h", $time, Ba);








    +            end








    +








    +            // AutoRefresh to Activate








    +            if ($time - RFC_chk < tRFC) begin








    +                $display ("At time %t ERROR: tRFC violation during Activate bank %h", $time, Ba);








    +            end








    +








    +            // Precharge to Activate








    +            if ((Ba === 2'b00 && Pc_b0  === 1'b0) || (Ba === 2'b01 && Pc_b1  === 1'b0) ||








    +                (Ba === 2'b10 && Pc_b2  === 1'b0) || (Ba === 2'b11 && Pc_b3  === 1'b0)) begin








    +                $display ("At time %t ERROR: Bank = %h is already activated - Command Ignored", $time, Ba);








    +                if (!no_halt) $stop (0);








    +            end else begin








    +                // Activate Bank 0








    +                if (Ba === 2'b00 && Pc_b0 === 1'b1) begin








    +                    // Activate to Activate (same bank)








    +                    if ($time - RC_chk0 < tRC) begin








    +                        $display ("At time %t ERROR: tRC violation during Activate bank %h", $time, Ba);








    +                    end








    +








    +                    // Precharge to Activate








    +                    if ($time - RP_chk0 < tRP) begin








    +                        $display ("At time %t ERROR: tRP violation during Activate bank %h", $time, Ba);








    +                    end








    +








    +                    // Record variables for checking violation








    +                    Act_b0 = 1'b1;








    +                    Pc_b0 = 1'b0;








    +                    B0_row_addr = Addr;








    +                    RC_chk0  = $time;








    +                    RCD_chk0 = $time;








    +                    RAS_chk0 = $time;








    +                    RAP_chk0 = $time;








    +                end








    +








    +                // Activate Bank 1








    +                if (Ba === 2'b01 && Pc_b1 === 1'b1) begin








    +                    // Activate to Activate (same bank)








    +                    if ($time - RC_chk1 < tRC) begin








    +                        $display ("At time %t ERROR: tRC violation during Activate bank %h", $time, Ba);








    +                    end








    +








    +                    // Precharge to Activate








    +                    if ($time - RP_chk1 < tRP) begin








    +                        $display ("At time %t ERROR: tRP violation during Activate bank %h", $time, Ba);








    +                    end








    +








    +                    // Record variables for checking violation








    +                    Act_b1 = 1'b1;








    +                    Pc_b1 = 1'b0;








    +                    B1_row_addr = Addr;








    +                    RC_chk1  = $time;








    +                    RCD_chk1 = $time;








    +                    RAS_chk1 = $time;








    +                    RAP_chk1 = $time;








    +                end








    +








    +                // Activate Bank 2








    +                if (Ba === 2'b10 && Pc_b2 === 1'b1) begin








    +                    // Activate to Activate (same bank)








    +                    if ($time - RC_chk2 < tRC) begin








    +                        $display ("At time %t ERROR: tRC violation during Activate bank %h", $time, Ba);








    +                    end








    +








    +                    // Precharge to Activate








    +                    if ($time - RP_chk2 < tRP) begin








    +                        $display ("At time %t ERROR: tRP violation during Activate bank %h", $time, Ba);








    +                    end








    +








    +                    // Record variables for checking violation








    +                    Act_b2 = 1'b1;








    +                    Pc_b2 = 1'b0;








    +                    B2_row_addr = Addr;








    +                    RC_chk2  = $time;








    +                    RCD_chk2 = $time;








    +                    RAS_chk2 = $time;








    +                    RAP_chk2 = $time;








    +                end








    +








    +                // Activate Bank 3








    +                if (Ba === 2'b11 && Pc_b3 === 1'b1) begin








    +                    // Activate to Activate (same bank)








    +                    if ($time - RC_chk3 < tRC) begin








    +                        $display ("At time %t ERROR: tRC violation during Activate bank %h", $time, Ba);








    +                    end








    +








    +                    // Precharge to Activate








    +                    if ($time - RP_chk3 < tRP) begin








    +                        $display ("At time %t ERROR: tRP violation during Activate bank %h", $time, Ba);








    +                    end








    +








    +                    // Record variables for checking violation








    +                    Act_b3 = 1'b1;








    +                    Pc_b3 = 1'b0;








    +                    B3_row_addr = Addr;








    +                    RC_chk3  = $time;








    +                    RCD_chk3 = $time;








    +                    RAS_chk3 = $time;








    +                    RAP_chk3 = $time;








    +                end








    +                // Record variable for checking violation








    +                RRD_chk = $time;








    +                Prev_bank = Ba;








    +                read_precharge_truncation[Ba] = 1'b0;








    +            end








    +        end








    +








    +        // Precharge Block - consider NOP if bank already precharged or in process of precharging








    +        if (Prech_enable === 1'b1) begin








    +            // Display DEBUG Message








    +            if (DEBUG) begin








    +                $display ("At time %t PRE  : Addr[10] = %b, Bank = %b", $time, Addr[10], Ba);








    +            end








    +








    +            // LMR/EMR to Precharge








    +            if ($time - MRD_chk < tMRD) begin








    +                $display ("At time %t ERROR: tMRD violation during Precharge", $time);








    +            end








    +








    +            // AutoRefresh to Precharge








    +            if ($time - RFC_chk < tRFC) begin








    +                $display ("At time %t ERROR: tRFC violation during Precharge", $time);








    +            end








    +








    +            // Precharge bank 0








    +            if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b00)) && Act_b0 === 1'b1) begin








    +                Act_b0 = 1'b0;








    +                Pc_b0 = 1'b1;








    +                RP_chk0 = $time;








    +








    +                // Activate to Precharge Bank








    +                if ($time - RAS_chk0 < tRAS) begin








    +                    $display ("At time %t ERROR: tRAS violation during Precharge", $time);








    +                end








    +








    +                // tWR violation check for Write








    +                if ($time - WR_chk0 < tWR) begin








    +                    $display ("At time %t ERROR: tWR violation during Precharge", $time);








    +                end








    +            end








    +








    +            // Precharge bank 1








    +            if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b01)) && Act_b1 === 1'b1) begin








    +                Act_b1 = 1'b0;








    +                Pc_b1 = 1'b1;








    +                RP_chk1 = $time;








    +








    +                // Activate to Precharge Bank 1








    +                if ($time - RAS_chk1 < tRAS) begin








    +                    $display ("At time %t ERROR: tRAS violation during Precharge", $time);








    +                end








    +








    +                // tWR violation check for Write








    +                if ($time - WR_chk1 < tWR) begin








    +                    $display ("At time %t ERROR: tWR violation during Precharge", $time);








    +                end








    +            end








    +








    +            // Precharge bank 2








    +            if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b10)) && Act_b2 === 1'b1) begin








    +                Act_b2 = 1'b0;








    +                Pc_b2 = 1'b1;








    +                RP_chk2 = $time;








    +








    +                // Activate to Precharge Bank 2








    +                if ($time - RAS_chk2 < tRAS) begin








    +                    $display ("At time %t ERROR: tRAS violation during Precharge", $time);








    +                end








    +








    +                // tWR violation check for Write








    +                if ($time - WR_chk2 < tWR) begin








    +                    $display ("At time %t ERROR: tWR violation during Precharge", $time);








    +                end








    +            end








    +








    +            // Precharge bank 3








    +            if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b11)) && Act_b3 === 1'b1) begin








    +                Act_b3 = 1'b0;








    +                Pc_b3 = 1'b1;








    +                RP_chk3 = $time;








    +








    +                // Activate to Precharge Bank 3








    +                if ($time - RAS_chk3 < tRAS) begin








    +                    $display ("At time %t ERROR: tRAS violation during Precharge", $time);








    +                end








    +








    +                // tWR violation check for Write








    +                if ($time - WR_chk3 < tWR) begin








    +                    $display ("At time %t ERROR: tWR violation during Precharge", $time);








    +                end








    +            end








    +








    +            // Prech_count is to make sure we have met part of the initialization sequence








    +            Prech_count = Prech_count + 1;








    +








    +            // Pipeline for READ








    +            A10_precharge [cas_latency_x2] = Addr[10];








    +            Bank_precharge[cas_latency_x2] = Ba;








    +            Cmnd_precharge[cas_latency_x2] = 1'b1;








    +        end








    +








    +        // Burst terminate








    +        if (Burst_term === 1'b1) begin








    +            // Display DEBUG Message








    +            if (DEBUG) begin








    +                $display ("At time %t BST  : Burst Terminate",$time);








    +            end








    +








    +            if (Data_in_enable === 1'b1) begin








    +                // Illegal to burst terminate a Write








    +                $display ("At time %t ERROR: It's illegal to burst terminate a Write", $time);








    +                if (!no_halt) $stop (0);








    +            end else if (Read_precharge[0] === 1'b1 || Read_precharge[1] === 1'b1 ||








    +                // Illegal to burst terminate a Read with Auto Precharge








    +                Read_precharge[2] === 1'b1 || Read_precharge[3] === 1'b1) begin








    +                $display ("At time %t ERROR: It's illegal to burst terminate a Read with Auto Precharge", $time);








    +                if (!no_halt) $stop (0);








    +            end else begin








    +                // Burst Terminate Command Pipeline for Read








    +                Cmnd_bst[cas_latency_x2] = 1'b1;








    +            end








    +








    +        end








    +








    +        // Read Command








    +        if (Read_enable === 1'b1) begin








    +            if (!(power_up_done)) begin








    +                $display ("%m: at time %t ERROR: Power Up and Initialization Sequence not completed before executing Read Command", $time);








    +            end








    +            // Check for DLL reset before Read








    +            if (DLL_reset === 1 && DLL_done === 0) begin








    +                $display ("%m: at time %t ERROR: You need to wait 200 tCK after DLL Reset Enable to Read, Not %0d clocks.", $time, DLL_count);








    +            end








    +            // Display DEBUG Message








    +            if (DEBUG) begin








    +                $display ("At time %t READ : Bank = %h, Col = %h", $time, Ba, {Addr [11], Addr [9 : 0]});








    +            end








    +








    +            // Terminate a Write








    +            if (Data_in_enable === 1'b1) begin








    +                Data_in_enable = 1'b0;








    +            end








    +








    +            // Activate to Read without Auto Precharge








    +            if ((Addr [10] === 1'b0 && Ba === 2'b00 && $time - RCD_chk0 < tRCD) ||








    +                (Addr [10] === 1'b0 && Ba === 2'b01 && $time - RCD_chk1 < tRCD) ||








    +                (Addr [10] === 1'b0 && Ba === 2'b10 && $time - RCD_chk2 < tRCD) ||








    +                (Addr [10] === 1'b0 && Ba === 2'b11 && $time - RCD_chk3 < tRCD)) begin








    +                $display("At time %t ERROR: tRCD violation during Read", $time);








    +            end








    +








    +            // Activate to Read with Auto Precharge








    +            if ((Addr [10] === 1'b1 && Ba === 2'b00 && $time - RAP_chk0 < tRAP) ||








    +                (Addr [10] === 1'b1 && Ba === 2'b01 && $time - RAP_chk1 < tRAP) ||








    +                (Addr [10] === 1'b1 && Ba === 2'b10 && $time - RAP_chk2 < tRAP) ||








    +                (Addr [10] === 1'b1 && Ba === 2'b11 && $time - RAP_chk3 < tRAP)) begin








    +                $display ("At time %t ERROR: tRAP violation during Read", $time);








    +            end








    +








    +            // Interrupt a Read with Auto Precharge (same bank only)








    +            if (Read_precharge [Ba] === 1'b1) begin








    +                $display ("At time %t ERROR: It's illegal to interrupt a Read with Auto Precharge", $time);








    +                if (!no_halt) $stop (0);








    +                // Cancel Auto Precharge








    +                if (Addr[10] === 1'b0) begin








    +                    Read_precharge [Ba]= 1'b0;








    +                end








    +            end








    +            // Activate to Read








    +            if ((Ba === 2'b00 && Pc_b0 === 1'b1) || (Ba === 2'b01 && Pc_b1 === 1'b1) ||








    +                (Ba === 2'b10 && Pc_b2 === 1'b1) || (Ba === 2'b11 && Pc_b3 === 1'b1)) begin








    +                $display("At time %t ERROR: Bank is not Activated for Read", $time);








    +                if (!no_halt) $stop (0);








    +            end else begin








    +                // CAS Latency pipeline








    +                Read_cmnd[cas_latency_x2] = 1'b1;








    +                Read_bank[cas_latency_x2] = Ba;








    +                Read_cols[cas_latency_x2] = {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]};








    +                // Auto Precharge








    +                if (Addr[10] === 1'b1) begin








    +                    Read_precharge [Ba]= 1'b1;








    +                    Count_precharge [Ba]= 0;








    +                end








    +            end








    +        end








    +








    +        // Write Command








    +        if (Write_enable === 1'b1) begin








    +            if (!(power_up_done)) begin








    +                $display ("%m: at time %t ERROR: Power Up and Initialization Sequence not completed before executing Write Command", $time);








    +                if (!no_halt) $stop (0);








    +            end








    +            // display DEBUG message








    +            if (DEBUG) begin








    +                $display ("At time %t WRITE: Bank = %h, Col = %h", $time, Ba, {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]});








    +            end








    +








    +            // Activate to Write








    +            if ((Ba === 2'b00 && $time - RCD_chk0 < tRCD) ||








    +                (Ba === 2'b01 && $time - RCD_chk1 < tRCD) ||








    +                (Ba === 2'b10 && $time - RCD_chk2 < tRCD) ||








    +                (Ba === 2'b11 && $time - RCD_chk3 < tRCD)) begin








    +                $display("At time %t ERROR: tRCD violation during Write to Bank %h", $time, Ba);








    +            end








    +








    +            // Read to Write








    +            if (Read_cmnd[0] || Read_cmnd[1] || Read_cmnd[2] || Read_cmnd[3] ||








    +                Read_cmnd[4] || Read_cmnd[5] || Read_cmnd[6] || (Burst_counter < burst_length)) begin








    +                if (Data_out_enable || read_precharge_truncation[Ba]) begin








    +                    $display("At time %t ERROR: Read to Write violation", $time);








    +                end








    +            end








    +








    +            // Interrupt a Write with Auto Precharge (same bank only)








    +            if (Write_precharge [Ba] === 1'b1) begin








    +                $display ("At time %t ERROR: it's illegal to interrupt a Write with Auto Precharge", $time);








    +                if (!no_halt) $stop (0);








    +                // Cancel Auto Precharge








    +                if (Addr[10] === 1'b0) begin








    +                    Write_precharge [Ba]= 1'b0;








    +                end








    +            end








    +            // Activate to Write








    +            if ((Ba === 2'b00 && Pc_b0 === 1'b1) || (Ba === 2'b01 && Pc_b1 === 1'b1) ||








    +                (Ba === 2'b10 && Pc_b2 === 1'b1) || (Ba === 2'b11 && Pc_b3 === 1'b1)) begin








    +                $display("At time %t ERROR: Bank is not Activated for Write", $time);








    +                if (!no_halt) $stop (0);








    +            end else begin








    +                // Pipeline for Write








    +                Write_cmnd [3] = 1'b1;








    +                Write_bank [3] = Ba;








    +                Write_cols [3] = {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]};








    +                // Auto Precharge








    +                if (Addr[10] === 1'b1) begin








    +                    Write_precharge [Ba]= 1'b1;








    +                    Count_precharge [Ba]= 0;








    +                end








    +            end








    +        end








    +    end








    +    endtask








    +








    +    task check_neg_dqs;








    +    begin








    +        if (Write_cmnd[2] || Write_cmnd[1] || Data_in_enable) begin








    +            for (i=0; i         --








    +--                                                                            --








    +-- This program is free software: you can redistribute it and/or modify       --








    +-- it under the terms of the GNU General Public License as published by       --








    +-- the Free Software Foundation, either version 3 of the License, or          --








    +-- (at your option) any later version.                                        --








    +--                                                                            --








    +-- This program is distributed in the hope that it will be useful,            --








    +-- but WITHOUT ANY WARRANTY; without even the implied warranty of             --








    +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the              --








    +-- GNU General Public License for more details.                               --








    +--                                                                            --








    +-- You should have received a copy of the GNU General Public License          --








    +-- along with this program.  If not, see .      --








    +--------------------------------------------------------------------------------








    +library ieee;








    +use ieee.std_logic_1164.all;








    +use ieee.numeric_std.all;








    +








    +library UNISIM;








    +use UNISIM.vcomponents.all;








    +--








    +--library work;








    +--use work.iwb.all;








    +--use work.iddr.all;








    +








    +entity tb_ddr is








    +end tb_ddr;








    +








    +architecture tb of tb_ddr is








    +








    +   component ddr is








    +     port (








    +       so_ack : out STD_LOGIC;








    +       si_clk : in STD_LOGIC := 'X';








    +       SD_CK_N : out STD_LOGIC;








    +       SD_CK_P : out STD_LOGIC;








    +       si_rst : in STD_LOGIC := 'X';








    +       si_stb : in STD_LOGIC := 'X';








    +       clk0 : in STD_LOGIC := 'X';








    +       clk180 : in STD_LOGIC := 'X';








    +       SD_CKE : out STD_LOGIC;








    +       si_we : in STD_LOGIC := 'X';








    +       clk90 : in STD_LOGIC := 'X';








    +       clk270 : in STD_LOGIC := 'X';








    +       SD_DQ : inout STD_LOGIC_VECTOR ( 15 downto 0 );








    +       SD_DQS : inout STD_LOGIC_VECTOR ( 1 downto 0 );








    +       SD_BA : out STD_LOGIC_VECTOR ( 1 downto 0 );








    +       SD_DM : out STD_LOGIC_VECTOR ( 1 downto 0 );








    +       SD_A : out STD_LOGIC_VECTOR ( 12 downto 0 );








    +       so_dat : out STD_LOGIC_VECTOR ( 31 downto 0 );








    +       SD_CMD : out STD_LOGIC_VECTOR ( 3 downto 0 );








    +       si_dat : in STD_LOGIC_VECTOR ( 31 downto 0 );








    +       si_sel : in STD_LOGIC_VECTOR ( 3 downto 0 );








    +       si_adr : in STD_LOGIC_VECTOR ( 31 downto 0 )








    +     );








    +   end component;








    +








    +   component model_ddr








    +      port(








    +         Clk   : in    std_logic;








    +         Clk_n : in    std_logic;








    +         Cke   : in    std_logic;








    +         Cs_n  : in    std_logic;








    +         Ras_n : in    std_logic;








    +         Cas_n : in    std_logic;








    +         We_n  : in    std_logic;








    +         Ba    : in    std_logic_vector(1 downto 0);








    +         Addr  : in    std_logic_vector(12 downto 0);








    +         Dm    : in    std_logic_vector(1 downto 0);








    +         Dq    : inout std_logic_vector(15 downto 0);








    +         Dqs   : inout std_logic_vector(1 downto 0)








    +      );








    +   end component;








    +








    +   signal so_dat : STD_LOGIC_VECTOR ( 31 downto 0 );








    +   signal so_ack : STD_LOGIC;








    +   signal si_clk : STD_LOGIC;








    +   signal si_rst : STD_LOGIC;








    +   signal si_stb : STD_LOGIC;








    +   signal si_we  : STD_LOGIC;








    +   signal si_dat : STD_LOGIC_VECTOR ( 31 downto 0 );








    +   signal si_sel : STD_LOGIC_VECTOR ( 3 downto 0 );








    +   signal si_adr : STD_LOGIC_VECTOR ( 31 downto 0 );








    +








    +   signal SD_CK_N  : std_logic;








    +   signal SD_CK_P  : std_logic;








    +   signal SD_CKE   : std_logic;








    +   signal SD_BA    : std_logic_vector(1 downto 0);








    +   signal SD_A     : std_logic_vector(12 downto 0);








    +   signal SD_CMD   : std_logic_vector(3 downto 0);








    +   signal SD_DM    : std_logic_vector(1 downto 0);








    +   signal SD_DQS   : std_logic_vector(1 downto 0);








    +   signal SD_DQ    : std_logic_vector(15 downto 0);








    +








    +   --constant clk_period : time := 7.5 ns;








    +    constant clk_period : time := 25.0 ns;








    +








    +    signal clk0   : std_logic;








    +    signal clk90  : std_logic;








    +    signal clk180 : std_logic;








    +    signal clk270 : std_logic;








    +begin








    +








    +   clk000 : process








    +   begin








    +      clk0 <= '0';








    +      clk90 <= '0';








    +      wait for clk_period / 4;








    +      clk0 <= '1';








    +      clk90 <= '0';








    +      wait for clk_period / 4;








    +      clk0 <= '1';








    +      clk90 <= '1';








    +      wait for clk_period / 4;








    +      clk0 <= '0';








    +      clk90 <= '1';








    +      wait for clk_period / 4;








    +   end process;








    +








    +   clk180 <= not clk0;








    +   clk270 <= not clk90;








    +








    +--   uut : ddr








    +--      port map(








    +--         si       => si,








    +--         so       => so,








    +--         clk0     => clk0,








    +--         clk90    => clk90,








    +--         clk180   => clk180,








    +--         clk270   => clk270,








    +--      -- Non Wishbone Signals








    +--         SD_CK_N  => SD_CK_N,








    +--         SD_CK_P  => SD_CK_P,








    +--         SD_CKE   => SD_CKE,








    +--         SD_BA    => SD_BA,








    +--         SD_A     => SD_A,








    +--         SD_CMD   => SD_CMD,








    +--         SD_DM    => SD_DM,








    +--         SD_DQS   => SD_DQS,








    +--         SD_DQ    => SD_DQ








    +--      );








    +








    +








    +








    +uut : ddr








    +   port map(








    +      so_ack  => so_ack,








    +      si_clk  => si_clk,








    +      SD_CK_N => SD_CK_N,








    +      SD_CK_P => SD_CK_P,








    +      si_rst  => si_rst,








    +      si_stb  => si_stb,








    +      clk0    => clk0,








    +      clk180  => clk180,








    +      SD_CKE  => SD_CKE,








    +      si_we   => si_we,








    +      clk90   => clk90,








    +      clk270  => clk270,








    +      SD_DQ   => SD_DQ,








    +      SD_DQS  => SD_DQS,








    +      SD_BA   => SD_BA,








    +      SD_DM   => SD_DM,








    +      SD_A    => SD_A,








    +      so_dat  => so_dat,








    +      SD_CMD  => SD_CMD,








    +      si_dat  => si_dat,








    +      si_sel  => si_sel,








    +      si_adr  => si_adr








    +   );








    +








    +








    +   model : model_ddr








    +      port map(








    +         Clk   => SD_CK_P,








    +         Clk_n => SD_CK_N,








    +         Cke   => SD_CKE,








    +         Cs_n  => SD_CMD(3),








    +         Ras_n => SD_CMD(2),








    +         Cas_n => SD_CMD(1),








    +         We_n  => SD_CMD(0),








    +         Ba    => SD_BA,








    +         Addr  => SD_A,








    +         Dm    => SD_DM,








    +         Dq    => SD_DQ,








    +         Dqs   => SD_DQS








    +      );








    +








    +   sti : process








    +   begin








    +         si_rst <= '1';








    +      wait for 3*clk_period;








    +         si_rst <= '0';








    +








    +   -----------------------------------------------------------------------------








    +   -- Same Bank, Same Rows                                                    --








    +   -----------------------------------------------------------------------------








    +      -- Write 0x12xx5678 to 0x00000000








    +      -- Row 0, Col 0,1








    +         si_adr <= x"00000000";








    +         si_dat <= x"12345678";








    +         si_sel <= "1011";








    +         si_stb <= '1';








    +         si_we  <= '1';








    +      wait until so_ack = '1';








    +         si_stb <= '0';








    +         si_we  <= '0';








    +      wait until so_ack = '0';








    +








    +      -- Write 0x8765xx21 to 0x00000004








    +      -- Row 0, Col 2,3








    +         si_adr <= x"00000004";








    +         si_dat <= x"87654321";








    +         si_sel <= "1101";








    +         si_stb <= '1';








    +         si_we  <= '1';








    +      wait until so_ack = '1';








    +         si_stb <= '0';








    +         si_we  <= '0';








    +      wait until so_ack = '0';








    +








    +      -- Read 0x8765xx21 from 0x00000004








    +         si_adr <= x"00000004";








    +         si_sel <= "1111";








    +         si_stb <= '1';








    +         si_we  <= '0';








    +      wait until so_ack = '1';








    +         si_stb <= '0';








    +         si_we  <= '0';








    +      wait until so_ack = '0';








    +








    +      -- Read 0x12xx5678 from 0x00000000








    +         si_adr <= x"00000000";








    +         si_sel <= "1111";








    +         si_stb <= '1';








    +         si_we  <= '0';








    +      wait until so_ack = '1';








    +         si_stb <= '0';








    +         si_we  <= '0';








    +      wait until so_ack = '0';








    +








    +








    +   -----------------------------------------------------------------------------








    +   -- Same Bank, different Rows                                               --








    +   -----------------------------------------------------------------------------








    +      -- Write 0x12xxxx78 to 0x00001000








    +      -- Row 2, Col 0,1








    +          si_adr <= x"00001000";








    +          si_dat <= x"12345678";








    +          si_sel <= "1001";








    +          si_stb <= '1';








    +          si_we  <= '1';








    +       wait until so_ack = '1';








    +          si_stb <= '0';








    +          si_we  <= '0';








    +       wait until so_ack = '0';








    +








    +      -- Write 0xxx6543xx to 0x00002004








    +      -- Row 4, Col 2,3








    +          si_adr <= x"00002004";








    +          si_dat <= x"87654321";








    +          si_sel <= "0110";








    +          si_stb <= '1';








    +          si_we  <= '1';








    +       wait until so_ack = '1';








    +          si_stb <= '0';








    +          si_we  <= '0';








    +       wait until so_ack = '0';








    +








    +      -- Read 0x12xx5678 from 0x00001000








    +      -- Row 2, Col 0,1








    +          si_adr <= x"00001000";








    +          si_sel <= "1111";








    +          si_stb <= '1';








    +          si_we  <= '0';








    +       wait until so_ack = '1';








    +          si_stb <= '0';








    +          si_we  <= '0';








    +








    +      -- Read 0x8765xx21 from 0x00002004








    +      -- Row 4, Col 2,3








    +          si_adr <= x"00002004";








    +          si_sel <= "1111";








    +          si_stb <= '1';








    +          si_we  <= '0';








    +       wait until so_ack = '1';








    +          si_stb <= '0';








    +          si_we  <= '0';








    +       wait until so_ack = '0';








    +








    +








    +   -----------------------------------------------------------------------------








    +   -- Different Banks, different Rows                                         --








    +   -----------------------------------------------------------------------------








    +      -- Write 0x12xxxx78 to 0x00001000








    +      -- Bank 1, Row 2, Col 0,1








    +          si_adr <= x"01001000";








    +          si_dat <= x"12345678";








    +          si_sel <= "1001";








    +          si_stb <= '1';








    +          si_we  <= '1';








    +       wait until so_ack = '1';








    +          si_stb <= '0';








    +          si_we  <= '0';








    +       wait until so_ack = '0';








    +








    +      -- Write 0xxx6543xx to 0x00002004








    +      -- Bank 2, Row 4, Col 2,3








    +          si_adr <= x"02002004";








    +          si_dat <= x"87654321";








    +          si_sel <= "0110";








    +          si_stb <= '1';








    +          si_we  <= '1';








    +       wait until so_ack = '1';








    +          si_stb <= '0';








    +          si_we  <= '0';








    +       wait until so_ack = '0';








    +








    +      -- Read 0x12xx5678 from 0x00001000








    +      -- Bank 1, Row 2, Col 0,1








    +          si_adr <= x"01001000";








    +          si_sel <= "1111";








    +          si_stb <= '1';








    +          si_we  <= '0';








    +       wait until so_ack = '1';








    +          si_stb <= '0';








    +          si_we  <= '0';








    +       wait until so_ack = '0';








    +








    +      -- Read 0x8765xx21 from 0x00002004








    +      -- Bank 2, Row 4, Col 2,3








    +          si_adr <= x"02002004";








    +          si_sel <= "1111";








    +          si_stb <= '1';








    +          si_we  <= '0';








    +       wait until so_ack = '1';








    +          si_stb <= '0';








    +          si_we  <= '0';








    +       wait until so_ack = '0';








    +








    +      wait;                            -- Important: no wait, no simulation.








    +   end process;








    +end tb;








    \ No newline at end of file








    Index: layer2/trunk/vhdl/ddr/bench








    ===================================================================








    --- layer2/trunk/vhdl/ddr/bench	(nonexistent)








    +++ layer2/trunk/vhdl/ddr/bench	(revision 2)
















    
    layer2/trunk/vhdl/ddr/bench














    Property changes :



    Added: bugtraq:number








    ## -0,0 +1 ##








    +true








    \ No newline at end of property








    Index: layer2/trunk/vhdl/ddr/rtl/iddr.vhd








    ===================================================================








    --- layer2/trunk/vhdl/ddr/rtl/iddr.vhd	(nonexistent)








    +++ layer2/trunk/vhdl/ddr/rtl/iddr.vhd	(revision 2)








    @@ -0,0 +1,55 @@








    +--------------------------------------------------------------------------------








    +-- Mycron� DDR SDRAM - MT46V32M16 - 8 Meg x 16 x 4 banks                      --








    +--------------------------------------------------------------------------------








    +--                                                                            --








    +-- REFERENCES                                                                 --








    +--                                                                            --








    +--  [1] http://opencores.org/project,ddr2_sdram                               --








    +--  [2] http://opencores.org/project,sdram_controller                         --








    +--  [3] Spartan-3E Libraries Guide for HDL Designs                            --








    +--                                                                            --








    +--------------------------------------------------------------------------------








    +-- Copyright (C)2012  Mathias H�rtnagl          --








    +--                                                                            --








    +-- This program is free software: you can redistribute it and/or modify       --








    +-- it under the terms of the GNU General Public License as published by       --








    +-- the Free Software Foundation, either version 3 of the License, or          --








    +-- (at your option) any later version.                                        --








    +--                                                                            --








    +-- This program is distributed in the hope that it will be useful,            --








    +-- but WITHOUT ANY WARRANTY; without even the implied warranty of             --








    +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the              --








    +-- GNU General Public License for more details.                               --








    +--                                                                            --








    +-- You should have received a copy of the GNU General Public License          --








    +-- along with this program.  If not, see .      --








    +--------------------------------------------------------------------------------








    +library ieee;








    +use ieee.std_logic_1164.all;








    +use ieee.numeric_std.all;








    +








    +library work;








    +use work.iwb.all;








    +








    +package iddr is








    +








    +   component ddr is








    +      port (








    +         si       : in    slave_in_t;








    +         so       : out   slave_out_t;








    +      -- Non Wishbone Signals








    +         clk0     : in    std_logic;








    +         clk90    : in    std_logic;








    +         SD_CK_N  : out   std_logic;








    +         SD_CK_P  : out   std_logic;








    +         SD_CKE   : out   std_logic;








    +         SD_BA    : out   std_logic_vector(1 downto 0);








    +         SD_A     : out   std_logic_vector(12 downto 0);








    +         SD_CMD   : out   std_logic_vector(3 downto 0);








    +         SD_DM    : out   std_logic_vector(1 downto 0);








    +         SD_DQS   : inout std_logic_vector(1 downto 0);








    +         SD_DQ    : inout std_logic_vector(15 downto 0)








    +      );








    +   end component;








    +








    +end iddr;








    \ No newline at end of file








    Index: layer2/trunk/vhdl/ddr/rtl/ddr.vhd








    ===================================================================








    --- layer2/trunk/vhdl/ddr/rtl/ddr.vhd	(nonexistent)








    +++ layer2/trunk/vhdl/ddr/rtl/ddr.vhd	(revision 2)








    @@ -0,0 +1,517 @@








    +--------------------------------------------------------------------------------








    +-- Mycron� DDR SDRAM - MT46V32M16 - 8 Meg x 16 x 4 banks                      --








    +--------------------------------------------------------------------------------








    +-- Copyright (C)2012  Mathias H�rtnagl          --








    +--                                                                            --








    +-- This program is free software: you can redistribute it and/or modify       --








    +-- it under the terms of the GNU General Public License as published by       --








    +-- the Free Software Foundation, either version 3 of the License, or          --








    +-- (at your option) any later version.                                        --








    +--                                                                            --








    +-- This program is distributed in the hope that it will be useful,            --








    +-- but WITHOUT ANY WARRANTY; without even the implied warranty of             --








    +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the              --








    +-- GNU General Public License for more details.                               --








    +--                                                                            --








    +-- You should have received a copy of the GNU General Public License          --








    +-- along with this program.  If not, see .      --








    +--------------------------------------------------------------------------------








    +library ieee;








    +use ieee.std_logic_1164.all;








    +use ieee.numeric_std.all;








    +








    +library UNISIM;








    +use UNISIM.vcomponents.all;








    +








    +library work;








    +use work.iwb.all;








    +use work.iddr.all;








    +








    +entity ddr is








    +   port (








    +      si       : in    slave_in_t;








    +      so       : out   slave_out_t;








    +   -- Non Wishbone Signals








    +      clk0     : in    std_logic;








    +      clk90    : in    std_logic;








    +      SD_CK_N  : out   std_logic;








    +      SD_CK_P  : out   std_logic;








    +      SD_CKE   : out   std_logic;








    +      SD_BA    : out   std_logic_vector(1 downto 0);








    +      SD_A     : out   std_logic_vector(12 downto 0);








    +      SD_CMD   : out   std_logic_vector(3 downto 0);








    +      SD_DM    : out   std_logic_vector(1 downto 0);








    +      SD_DQS   : inout std_logic_vector(1 downto 0);








    +      SD_DQ    : inout std_logic_vector(15 downto 0)








    +   );








    +end ddr;








    +








    +architecture rtl of ddr is








    +








    +   -----------------------------------------------------------------------------








    +   -- General                                                                 --








    +   -----------------------------------------------------------------------------








    +   -- Average periodic refresh interval tREFI: 7.8 �s








    +   constant AR_RATE : natural := 160; -- x 40 ns = 5.8 �s.








    +








    +   -----------------------------------------------------------------------------








    +   -- Controller Commands                                                     --








    +   -----------------------------------------------------------------------------








    +   constant CMD_AUTO_REFRESH : std_logic_vector(3 downto 0) := "0001";








    +   constant CMD_PRECHARGE    : std_logic_vector(3 downto 0) := "0010";








    +   constant CMD_ACTIVE       : std_logic_vector(3 downto 0) := "0011";








    +   constant CMD_WRITE        : std_logic_vector(3 downto 0) := "0100";








    +   constant CMD_READ         : std_logic_vector(3 downto 0) := "0101";








    +   constant CMD_NOP          : std_logic_vector(3 downto 0) := "0111";








    +








    +   -----------------------------------------------------------------------------








    +   -- Wishbone Controller                                                     --








    +   -----------------------------------------------------------------------------








    +   type wb_state_t is (








    +      Initialize,                            -- Initialization.








    +      Idle,                                  -- Wait for user or autorefresh.








    +      Ack                                    -- WB wait for ack.








    +   );








    +








    +   signal w, win  : wb_state_t := Initialize;








    +








    +   signal ddr_done : boolean;                -- Successful read or wirte.








    +   signal read_wb  : boolean;                -- Pending WB read.








    +   signal write_wb : boolean;                -- Pending WB write.








    +








    +   -----------------------------------------------------------------------------








    +   -- Main Controller                                                         --








    +   -----------------------------------------------------------------------------








    +   type main_state_t is (








    +      Initialize,                            -- Initialization.








    +      Idle,                                  -- Wait for user or autorefresh.








    +      AutoRefresh, AutoRefreshWait,          -- Autorefresh when idle.








    +      Active, ActiveWait,                    -- Activate Row.








    +      Write, RecoverWrite,                   -- Write 32 bit.








    +      Read, WaitRead,                        -- Read 32 bit.








    +      PrechargeWait,                         -- Wait for precharge after Write.








    +      Ack                                    -- WB wait for ack.








    +   );








    +








    +   type main_t is record








    +      s    : main_state_t;








    +      c    : natural range 0 to 7;








    +      a    : natural range 0 to AR_RATE-1;    -- Auto refresh counter.








    +      rfsh : boolean;                         -- Pending autorefresh.








    +      cmd  : std_logic_vector(3 downto 0);    -- SD_CS SD_RAS SD_CAS SD_WE.








    +      ba   : std_logic_vector(1 downto 0);    -- DDR bank address.








    +      adr  : std_logic_vector(12 downto 0);   -- DDR address bus.








    +   end record;








    +








    +   constant main_d : main_t :=








    +      main_t'(Initialize, 0, 0, false, CMD_NOP, "00", (others => '0') );








    +








    +   signal m, min  : main_t := main_d;








    +








    +   signal dq      : std_logic_vector(15 downto 0);    -- Data tb be written.








    +   signal dqs     : std_logic_vector(1 downto 0);     -- Data strobe signal.








    +   signal dm      : std_logic_vector(1 downto 0);     -- Data mask signal.








    +   signal mask    : std_logic_vector(3 downto 0);








    +








    +   signal wr_en   : boolean;








    +   signal wr_en2  : boolean;








    +








    +   signal rd      : std_logic_vector(31 downto 0);    -- Read data latch.








    +   signal rd_en   : boolean;                          -- Read latch enable.








    +   signal rd_en2  : boolean;








    +








    +








    +   -----------------------------------------------------------------------------








    +   -- Initialization                                                          --








    +   -----------------------------------------------------------------------------








    +   component ddr_init is








    +      port (








    +         clk0      : in  std_logic;








    +         rst       : in  std_logic;








    +         SD_CKE    : out std_logic;








    +         SD_BA     : out std_logic_vector(1 downto 0);








    +         SD_A      : out std_logic_vector(12 downto 0);








    +         SD_CMD    : out std_logic_vector(3 downto 0);








    +         init_done : out boolean








    +      );








    +   end component;








    +








    +   type init_c is record








    +      cmd  : std_logic_vector(3 downto 0);   -- SD_CS | SD_RAS | SD_CAS | SD_WE.








    +      ba   : std_logic_vector(1 downto 0);   -- DDR bank address.








    +      adr  : std_logic_vector(12 downto 0);  -- DDR address bus.








    +      done : boolean;                        -- True on Init completion.








    +   end record;








    +








    +   signal init : init_c;








    +begin








    +








    +   SD_CK_P <= not clk0;








    +   SD_CK_N <= clk0;








    +








    +








    +   -----------------------------------------------------------------------------








    +   -- Initialization                                                          --








    +   -----------------------------------------------------------------------------








    +   init_fsm : ddr_init port map(








    +      clk0      => clk0,








    +      rst       => si.rst,








    +      SD_CKE    => SD_CKE,








    +      SD_BA     => init.ba,








    +      SD_A      => init.adr,








    +      SD_CMD    => init.cmd,








    +      init_done => init.done








    +   );








    +








    +   -----------------------------------------------------------------------------








    +   -- Wishbone Controller                                                     --








    +   -----------------------------------------------------------------------------








    +   -- NOTE: The Whishbone Controller runs at 50 MHz. There is a problem with the








    +   --       communication protocol implementation, which does not allow a master








    +   --       and a slave running at different frequencies.








    +   --       If this problem happens to be fixed someday, the following state








    +   --       machine can be deleted and the Wishbone signals can be tied directly








    +   --       into the main state machine.








    +   wbone : process(w, si, init.done)








    +   begin








    +








    +      win <= w;








    +








    +      so.ack   <= '0';








    +      read_wb  <= false;








    +      write_wb <= false;








    +








    +      case w is








    +         when Initialize =>








    +            if init.done then








    +               win <= Idle;








    +            end if;








    +








    +         when Idle =>








    +            if wb_read(si) then








    +               read_wb <= true;








    +            elsif wb_write(si) then








    +               write_wb <= true;








    +            end if;








    +            if ddr_done then








    +               win <= Ack;








    +            end if;








    +








    +         when Ack =>








    +            so.ack <= '1';








    +            if si.stb = '0' then








    +               win <= Idle;








    +            end if;








    +








    +      end case;








    +   end process;








    +








    +   wb_reg : process(si.clk)








    +   begin








    +      if rising_edge(si.clk) then








    +         if si.rst = '1' then w <= Initialize; else w <= win; end if;








    +      end if;








    +   end process;








    +








    +   -----------------------------------------------------------------------------








    +   -- Main Controller                                                         --








    +   -----------------------------------------------------------------------------








    +   -- main : process(m, si, init)








    +   main : process(m, init, read_wb, write_wb)








    +   begin








    +








    +      min <= m;








    +








    +      -- Refresh counter.








    +      if m.a = (AR_RATE-1) then








    +         min.rfsh <= true;








    +      else








    +         min.a <= m.a + 1;








    +      end if;








    +








    +      wr_en  <= false;                 -- Write state machine enable.








    +      rd_en  <= false;                 -- Read state machine enable.








    +      --so.ack <= '0';








    +      ddr_done <= false;               -- Indicates a successful read or wirte.








    +








    +      case m.s is








    +








    +         -----------------------------------------------------------------------








    +         -- Initialization (see process initial).                             --








    +         -----------------------------------------------------------------------








    +         when Initialize =>








    +            min.ba  <= init.ba;








    +            min.adr <= init.adr;








    +            min.cmd <= init.cmd;








    +            if init.done then








    +               min.a    <= 0;








    +               min.rfsh <= false;








    +               min.s    <= Idle;








    +            end if;








    +








    +         -----------------------------------------------------------------------








    +         -- Wait for memory operations or auto refresh.                       --








    +         -----------------------------------------------------------------------








    +         when Idle =>








    +            if m.rfsh then








    +               min.a    <= 0;








    +               min.rfsh <= false;








    +               min.s    <= AutoRefresh;








    +            -- elsif si.stb = '1' then








    +            elsif (read_wb or write_wb) then








    +               min.c <= 0;








    +               min.s <= Active;








    +            end if;








    +








    +         -----------------------------------------------------------------------








    +         -- Auto Refresh.                                                     --








    +         -----------------------------------------------------------------------








    +         when AutoRefresh =>








    +            min.cmd <= CMD_AUTO_REFRESH;








    +            min.c   <= 0;








    +            min.s   <= AutoRefreshWait;








    +








    +         -- AUTO REFRESH command period tRFC: 72ns








    +         -- Precharge command cycle + PRECHARGE command period tRP: 15ns








    +         when AutoRefreshWait =>








    +            min.cmd <= CMD_NOP;








    +            if m.c = 1 then








    +               min.c <= 0;








    +               min.s <= Idle;








    +            else








    +               min.c <= m.c + 1;








    +            end if;








    +








    +         -----------------------------------------------------------------------








    +         -- Activate bank and row.                                            --








    +         -----------------------------------------------------------------------








    +         when Active =>








    +            min.cmd <= CMD_ACTIVE;








    +            min.ba  <= si.adr(25 downto 24);     -- Select bank.








    +            min.adr <= si.adr(23 downto 11);     -- Select row.








    +            min.s   <= ActiveWait;








    +








    +         -- ACTIVE-to-READ or WRITE delay tRCD: 15ns








    +         when ActiveWait =>








    +            min.cmd <= CMD_NOP;








    +            min.ba  <= "00";                 -- Select bank.








    +            min.adr <= (others => '0');      -- Select row.








    +            -- if si.we = '0' then








    +               -- min.s <= Read;








    +            -- else








    +               -- min.s <= Write;








    +            -- end if;








    +            if read_wb then








    +               min.s <= Read;








    +            elsif write_wb then








    +               min.s <= Write;








    +            end if;








    +








    +         -----------------------------------------------------------------------








    +         -- Read.                                                             --








    +         -----------------------------------------------------------------------








    +         -- At burst length 2 and sequential type, SD_A(0) is zero and the








    +         -- ordering of the burst access is 0-1.








    +         when Read =>








    +            min.cmd             <= CMD_READ;








    +            min.ba              <= si.adr(25 downto 24);








    +            min.adr(10)         <= '1';                  -- Auto precharge.








    +            min.adr(9 downto 1) <= si.adr(10 downto 2);








    +            min.s               <= WaitRead;








    +








    +         -- CL=2








    +         when WaitRead =>








    +            min.cmd             <= CMD_NOP;








    +            min.ba              <= "00";








    +            min.adr(10)         <= '0';








    +            min.adr(9 downto 1) <= (others => '0');








    +            rd_en               <= true;








    +            min.s               <= PrechargeWait;








    +








    +         -----------------------------------------------------------------------








    +         -- Write.                                                            --








    +         -----------------------------------------------------------------------








    +         -- At burst length 2 and sequential type, SD_A(0) is fixed to zero and








    +         -- the ordering of the burst accesses is 0-1.








    +         when Write =>








    +            min.cmd             <= CMD_WRITE;








    +            min.ba              <= si.adr(25 downto 24);








    +            min.adr(10)         <= '1';                  -- Auto precharge.








    +            min.adr(9 downto 1) <= si.adr(10 downto 2);








    +            wr_en               <= true;








    +            min.s               <= RecoverWrite;








    +








    +         -- Write recovery time tWR: 15 ns








    +         when RecoverWrite =>








    +            min.cmd             <= CMD_NOP;








    +            min.ba              <= "00";








    +            min.adr(10)         <= '0';








    +            min.adr(9 downto 1) <= (others => '0');








    +            if m.c = 1 then








    +               min.c <= 0;








    +               min.s <= PrechargeWait;








    +            else








    +               min.c <= m.c + 1;








    +            end if;








    +








    +         -----------------------------------------------------------------------








    +         -- Auto Precharge.                                                   --








    +         -----------------------------------------------------------------------








    +         -- Precharge command cycle + PRECHARGE command period tRP: 15ns








    +         when PrechargeWait =>








    +            if m.c = 1 then








    +               min.c <= 0;








    +               min.s <= Ack;








    +            else








    +               min.c <= m.c + 1;








    +            end if;








    +








    +         -----------------------------------------------------------------------








    +         -- WB Ack                                                            --








    +         -----------------------------------------------------------------------








    +         -- NOTE: If the WB master needs too much time to pull strobe low, the








    +         --       DDR lacks an autorefresh as this only happens in Idle state!








    +         when Ack =>








    +            -- so.ack <= '1';








    +            -- if si.stb = '0' then








    +               -- min.s <= Idle;








    +            -- end if;








    +            ddr_done <= true;








    +            min.s    <= Idle;








    +      end case;








    +   end process;








    +








    +   SD_CMD <= m.cmd;








    +   SD_BA  <= m.ba;








    +   SD_A   <= m.adr;








    +








    +








    +   -----------------------------------------------------------------------------








    +   -- Read                                                                    --








    +   -----------------------------------------------------------------------------








    +   rds : process(clk0, rd_en)








    +      type s_t is (Idle, ReadPreamble, Read);








    +      variable s : s_t := Idle;








    +   begin








    +      if falling_edge(clk0) then








    +         if si.rst = '1' then








    +            s := Idle;








    +         else








    +            case s is








    +               when Idle =>








    +                  rd_en2 <= false;








    +                  if rd_en then s := ReadPreamble; end if;








    +








    +               when ReadPreamble =>








    +                  rd_en2 <= false;








    +                  s      := Read;








    +








    +               when Read =>








    +                  rd_en2 <= true;








    +                  s      := Idle;








    +            end case;








    +         end if;








    +      end if;








    +   end process;








    +








    +   process(clk0)








    +   begin








    +      if rising_edge(clk0) then








    +         if rd_en2 then rd(31 downto 16) <= SD_DQ; end if;








    +      end if;








    +   end process;








    +








    +   process(clk0)








    +   begin








    +      if falling_edge(clk0) then








    +         if rd_en2 then rd(15 downto 0) <= SD_DQ; end if;








    +      end if;








    +   end process;








    +








    +   so.dat <= rd;








    +








    +








    +   -----------------------------------------------------------------------------








    +   -- Write                                                                   --








    +   -----------------------------------------------------------------------------








    +   wrs : process(clk90, wr_en, si.dat, si.sel)








    +      type s_t is (Idle, WritePreamble, Write);








    +      variable s : s_t := Idle;








    +   begin








    +      if rising_edge(clk90) then








    +         if si.rst = '1' then








    +            s := Idle;








    +         else








    +            case s is








    +               when Idle =>








    +                  wr_en2 <= false;








    +                  if wr_en then s := WritePreamble; end if;








    +








    +               when WritePreamble =>








    +                  wr_en2 <= false;








    +                  s      := Write;








    +








    +               when Write =>








    +                  wr_en2 <= true;








    +                  s      := Idle;








    +            end case;








    +         end if;








    +      end if;








    +   end process;








    +








    +   -- This part is bad design practice! Direct usage of clock signals is








    +   -- discouraged. The data mask pins can't be populated with ODDR2s.








    +   -- DRC gives an error. Could be hacked manually probably.








    +   mask <= not si.sel;








    +   dm   <= mask(3 downto 2) when clk90 = '1' else mask(1 downto 0);








    +   -- dq   <= si.dat(31 downto 16) when clk90 = '1' else si.dat(15 downto 0);








    +   -- dqs  <= clk90 & clk90;








    +








    +   DQS_GEN : for i in 1 downto 0 generate begin DQS : ODDR2








    +      generic map( DDR_ALIGNMENT => "NONE", INIT => '0', SRTYPE => "SYNC" )








    +      port map (








    +         Q  => dqs(i),








    +         C0 => not clk0, C1 => clk0,








    +         CE => '1',








    +         D0 => '1', D1 => '0',








    +         R  => '0', S  => '0'








    +      );








    +   end generate;








    +








    +   -- DM_GEN : for i in 1 downto 0 generate begin DM : ODDR2








    +      -- generic map( DDR_ALIGNMENT => "NONE", INIT => '0', SRTYPE => "SYNC" )








    +      -- port map (








    +         -- Q  => dm(i),








    +         -- C0 => clk90, C1 => not clk90,








    +         -- CE => '1',








    +         -- D0 => mask(2 + i), D1 => mask(i),








    +         -- R  => '0', S  => '0'








    +      -- );








    +   -- end generate;








    +








    +   DQ_GEN : for i in 15 downto 0 generate begin DQ : ODDR2








    +      generic map( DDR_ALIGNMENT => "NONE", INIT => '0', SRTYPE => "SYNC" )








    +      port map (








    +         Q  => dq(i),








    +         C0 => clk90, C1 => not clk90,








    +         CE => '1',








    +         D0 => si.dat(16 + i), D1 => si.dat(i),








    +         R  => '0', S  => '0'








    +      );








    +   end generate;








    +








    +   SD_DQS <= dqs when wr_en2 else "ZZ";           -- Bi-directional data strobe.








    +   SD_DQ  <= dq when wr_en2 else (others => 'Z'); -- Bi-directional data bus.








    +   SD_DM  <= dm when wr_en2 else "11";








    +








    +








    +   -----------------------------------------------------------------------------








    +   -- Register                                                                --








    +   -----------------------------------------------------------------------------








    +   reg : process(clk0)








    +   begin








    +      if rising_edge(clk0) then








    +         if si.rst = '1' then m <= main_d; else m <= min; end if;








    +      end if;








    +   end process;








    +end rtl;








    \ No newline at end of file








    Index: layer2/trunk/vhdl/ddr/rtl/ddr_init.vhd








    ===================================================================








    --- layer2/trunk/vhdl/ddr/rtl/ddr_init.vhd	(nonexistent)








    +++ layer2/trunk/vhdl/ddr/rtl/ddr_init.vhd	(revision 2)








    @@ -0,0 +1,287 @@








    +--------------------------------------------------------------------------------








    +-- Mycron� DDR SDRAM - MT46V32M16 - 8 Meg x 16 x 4 banks                      --








    +--------------------------------------------------------------------------------








    +-- Copyright (C)2012  Mathias H�rtnagl          --








    +--                                                                            --








    +-- This program is free software: you can redistribute it and/or modify       --








    +-- it under the terms of the GNU General Public License as published by       --








    +-- the Free Software Foundation, either version 3 of the License, or          --








    +-- (at your option) any later version.                                        --








    +--                                                                            --








    +-- This program is distributed in the hope that it will be useful,            --








    +-- but WITHOUT ANY WARRANTY; without even the implied warranty of             --








    +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the              --








    +-- GNU General Public License for more details.                               --








    +--                                                                            --








    +-- You should have received a copy of the GNU General Public License          --








    +-- along with this program.  If not, see .      --








    +--------------------------------------------------------------------------------








    +library ieee;








    +use ieee.std_logic_1164.all;








    +use ieee.numeric_std.all;








    +








    +entity ddr_init is








    +   port (








    +      clk0      : in  std_logic;








    +      rst       : in  std_logic;








    +      SD_CKE    : out std_logic;








    +      SD_BA     : out std_logic_vector(1 downto 0);








    +      SD_A      : out std_logic_vector(12 downto 0);








    +      SD_CMD    : out std_logic_vector(3 downto 0);








    +      init_done : out boolean








    +   );








    +end ddr_init;








    +








    +architecture rtl of ddr_init is








    +








    +   -----------------------------------------------------------------------------








    +   -- Controller Commands                                                     --








    +   -----------------------------------------------------------------------------








    +   constant CMD_LMR          : std_logic_vector(3 downto 0) := "0000";








    +   constant CMD_AUTO_REFRESH : std_logic_vector(3 downto 0) := "0001";








    +   constant CMD_PRECHARGE    : std_logic_vector(3 downto 0) := "0010";








    +   constant CMD_NOP          : std_logic_vector(3 downto 0) := "0111";








    +








    +   -----------------------------------------------------------------------------








    +   -- Mode Rgister Addresses                                                  --








    +   -----------------------------------------------------------------------------








    +   -- Addresses for the two mode registers, selected via SD_BA.








    +   constant BMR_ADDR : std_logic_vector(1 downto 0) := "00";








    +   constant EMR_ADDR : std_logic_vector(1 downto 0) := "01";








    +








    +   -----------------------------------------------------------------------------








    +   -- Base Mode Rgister                                                       --








    +   -----------------------------------------------------------------------------








    +   -- Operating modes.








    +   constant OP_NORMAL  : std_logic_vector(5 downto 0) := "000000";








    +   constant OP_DLL_RST : std_logic_vector(5 downto 0) := "000010";








    +








    +   -- CAS latency.








    +   constant CAS_2  : std_logic_vector(2 downto 0) := "010";








    +








    +   -- Burst type.








    +   constant BT_S : std_logic := '0';      -- Sequential.








    +








    +   -- Burst lengths.








    +   constant BL_2 : std_logic_vector(2 downto 0) := "001";








    +








    +   -----------------------------------------------------------------------------








    +   -- Extended Mode Rgister                                                   --








    +   -----------------------------------------------------------------------------








    +   -- DLL.








    +   constant DLL_ENABLE  : std_logic := '0';








    +   constant DLL_DISABLE : std_logic := '1';








    +








    +   -- Drive strength.








    +   constant DS_NORMAL  : std_logic := '0';








    +








    +








    +   -----------------------------------------------------------------------------








    +   -- Initialization                                                          --








    +   -----------------------------------------------------------------------------








    +   type init_state_t is (








    +      Wait20000,                          -- Wait for 200�s.








    +      CKE_High,                           -- Assert CKE.








    +      Precharge0, Precharge0Wait,         -- First precharge.








    +      ProgramEMR, ProgramEMRWait,         -- Set Extended Mode Register.








    +      ProgramMR, ProgramMRWait,           -- Set Base Mode Register.








    +      Precharge1, Precharge1Wait,         -- second precharge.








    +      AutoRefresh0, AutoRefresh0Wait,     -- First autorefresh.








    +      AutoRefresh1, AutoRefresh1Wait,     -- Second autorefresh.








    +      ProgramMR1, ProgramMR1Wait,         -- Set Base Mode Register.








    +      Wait200,                            -- Wait for 200 cycles.








    +      Done                                -- Initialization done!








    +   );








    +








    +   type init_t is record








    +      s   : init_state_t;








    +      c   : natural range 0 to 19999;








    +   end record;








    +








    +   constant init_d  : init_t := init_t'( Wait20000, 0);








    +   signal i, iin    : init_t := init_d;








    +begin








    +








    +   -----------------------------------------------------------------------------








    +   -- Initialization                                                          --








    +   -----------------------------------------------------------------------------








    +   initial : process(i)








    +   begin








    +








    +      iin       <= i;








    +      SD_CKE    <= '1';








    +      SD_BA     <= "00";








    +      SD_CMD    <= CMD_NOP;








    +      SD_A      <= (others => '0');








    +      init_done <= false;








    +








    +      case i.s is








    +








    +         -----------------------------------------------------------------------








    +         -- 5. Wait for 200�s.                                                --








    +         -----------------------------------------------------------------------








    +         when Wait20000 =>








    +            SD_CKE <= '0';








    +            if i.c = 19999 then








    +               iin.c <= 0;








    +               iin.s <= CKE_High;








    +            else








    +               iin.c <= i.c + 1;








    +            end if;








    +








    +         -----------------------------------------------------------------------








    +         -- 6. Bring CKE high.                                                --








    +         -----------------------------------------------------------------------








    +         when CKE_High =>








    +            iin.s <= Precharge0;








    +








    +         -----------------------------------------------------------------------








    +         -- 7. Precharge all banks.                                           --








    +         -----------------------------------------------------------------------








    +         when Precharge0 =>








    +            SD_CMD      <= CMD_PRECHARGE;








    +            SD_A(10) <= '1';               -- Precharge all operation.








    +            iin.s       <= Precharge0Wait;








    +








    +         -- PRECHARGE command period tRP: 15ns








    +         when Precharge0Wait =>








    +            if i.c = 1 then








    +               iin.c <= 0;








    +               iin.s <= ProgramEMR;








    +            else








    +               iin.c <= i.c + 1;








    +            end if;








    +








    +         -----------------------------------------------------------------------








    +         -- 9. Program the Extended Mode Register.                            --








    +         -----------------------------------------------------------------------








    +         when ProgramEMR =>








    +            SD_CMD  <= CMD_LMR;








    +            SD_BA   <= EMR_ADDR;              -- Select Extended Mode Register.








    +            SD_A    <= "00000000000" & DS_NORMAL & DLL_DISABLE;








    +            iin.s   <= ProgramEMRWait;








    +








    +         -- LOAD MODE REGISTER command cycle time tMRD: 12ns








    +         when ProgramEMRWait =>








    +            if i.c = 1 then








    +               iin.c <= 0;








    +               iin.s <= ProgramMR;








    +            else








    +               iin.c <= i.c + 1;








    +            end if;








    +








    +         -----------------------------------------------------------------------








    +         -- 11. Program the Mode Rgister                                      --








    +         -----------------------------------------------------------------------








    +         when ProgramMR =>








    +            SD_CMD  <= CMD_LMR;








    +            SD_BA   <= BMR_ADDR;              -- Select Base Mode Register.








    +            SD_A    <= OP_NORMAL & CAS_2 & BT_S & BL_2;








    +            iin.s   <= ProgramMRWait;








    +








    +         -- LOAD MODE REGISTER command cycle time tMRD: 12ns








    +         when ProgramMRWait =>








    +            if i.c = 1 then








    +               iin.c <= 0;








    +               iin.s <= Precharge1;








    +            else








    +               iin.c <= i.c + 1;








    +            end if;








    +








    +         -----------------------------------------------------------------------








    +         -- 13. Precharge all banks.                                          --








    +         -----------------------------------------------------------------------








    +         when Precharge1 =>








    +            SD_CMD   <= CMD_PRECHARGE;








    +            SD_A(10) <= '1';               -- Precharge all operation.








    +            iin.s    <= Precharge1Wait;








    +








    +         -- PRECHARGE command period tRP: 15ns








    +         when Precharge1Wait =>








    +            if i.c = 1 then








    +               iin.c <= 0;








    +               iin.s <= AutoRefresh0;








    +            else








    +               iin.c <= i.c + 1;








    +            end if;








    +








    +         -----------------------------------------------------------------------








    +         -- 15. Auto Refresh.                                                 --








    +         -----------------------------------------------------------------------








    +         when AutoRefresh0 =>








    +            SD_CMD <= CMD_AUTO_REFRESH;








    +            iin.s  <= AutoRefresh0Wait;








    +








    +         -- AUTO REFRESH command period tRFC: 72ns








    +         when AutoRefresh0Wait =>








    +            if i.c = 7 then








    +               iin.c <= 0;








    +               iin.s <= AutoRefresh1;








    +            else








    +               iin.c <= i.c + 1;








    +            end if;








    +








    +         -----------------------------------------------------------------------








    +         -- 17. Auto Refresh.                                                 --








    +         -----------------------------------------------------------------------








    +         when AutoRefresh1 =>








    +            SD_CMD <= CMD_AUTO_REFRESH;








    +            iin.s  <= AutoRefresh1Wait;








    +








    +         -- AUTO REFRESH command period tRFC: 72ns








    +         when AutoRefresh1Wait =>








    +            if i.c = 7 then








    +               iin.c <= 0;








    +               iin.s <= ProgramMR1;








    +            else








    +               iin.c <= i.c + 1;








    +            end if;








    +








    +         -----------------------------------------------------------------------








    +         -- 19. Program the Mode Rgister (Clear DLL Bit)                      --








    +         -----------------------------------------------------------------------








    +         when ProgramMR1 =>








    +            SD_CMD  <= CMD_LMR;








    +            SD_BA   <= BMR_ADDR;              -- Select Base Mode Register.








    +            SD_A    <= OP_NORMAL & CAS_2 & BT_S & BL_2;








    +            iin.s   <= ProgramMR1Wait;








    +








    +         -- LOAD MODE REGISTER command cycle time tMRD: 12ns








    +         when ProgramMR1Wait =>








    +            if i.c = 1 then








    +               iin.c <= 0;








    +               iin.s <= Wait200;








    +            else








    +               iin.c <= i.c + 1;








    +            end if;








    +








    +         -----------------------------------------------------------------------








    +         -- 21. Wait for 200 cycles.                                          --








    +         -----------------------------------------------------------------------








    +         when Wait200 =>








    +            if i.c = 199 then








    +               iin.c <= 0;








    +               iin.s <= Done;








    +            else








    +               iin.c <= i.c + 1;








    +            end if;








    +








    +         -----------------------------------------------------------------------








    +         -- Initialization done.                                              --








    +         -----------------------------------------------------------------------








    +         when Done =>








    +            init_done <= true;








    +      end case;








    +   end process;








    +








    +








    +   -----------------------------------------------------------------------------








    +   -- Register                                                                --








    +   -----------------------------------------------------------------------------








    +   reg : process(clk0)








    +   begin








    +      if rising_edge(clk0) then








    +         if rst = '1' then i <= init_d; else i <= iin; end if;








    +      end if;








    +   end process;








    +end rtl;








    \ No newline at end of file








    Index: layer2/trunk/vhdl/ddr/rtl








    ===================================================================








    --- layer2/trunk/vhdl/ddr/rtl	(nonexistent)








    +++ layer2/trunk/vhdl/ddr/rtl	(revision 2)
















    
    layer2/trunk/vhdl/ddr/rtl














    Property changes :



    Added: bugtraq:number








    ## -0,0 +1 ##








    +true








    \ No newline at end of property








    Index: layer2/trunk/vhdl/ddr








    ===================================================================








    --- layer2/trunk/vhdl/ddr	(nonexistent)








    +++ layer2/trunk/vhdl/ddr	(revision 2)
















    
    layer2/trunk/vhdl/ddr














    Property changes :



    Added: bugtraq:number








    ## -0,0 +1 ##








    +true








    \ No newline at end of property








    Index: layer2/trunk/vhdl/keyb/bench/tb_keyb.vhd








    ===================================================================








    --- layer2/trunk/vhdl/keyb/bench/tb_keyb.vhd	(nonexistent)








    +++ layer2/trunk/vhdl/keyb/bench/tb_keyb.vhd	(revision 2)








    @@ -0,0 +1,64 @@








    +--------------------------------------------------------------------------------








    +--                                                                            --








    +--------------------------------------------------------------------------------








    +-- Version:  1.0                                                              --








    +-- Device:   Spartan 3E                                                       --








    +--                                                                            --








    +-- DESCRIPTION                                                                --








    +--                                                                            --








    +--                                                                            --








    +--------------------------------------------------------------------------------








    +-- Copyright (C)2011  Mathias H�rtnagl          --








    +--                                                                            --








    +-- This program is free software: you can redistribute it and/or modify       --








    +-- it under the terms of the GNU General Public License as published by       --








    +-- the Free Software Foundation, either version 3 of the License, or          --








    +-- (at your option) any later version.                                        --








    +--                                                                            --








    +-- This program is distributed in the hope that it will be useful,            --








    +-- but WITHOUT ANY WARRANTY; without even the implied warranty of             --








    +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the              --








    +-- GNU General Public License for more details.                               --








    +--                                                                            --








    +-- You should have received a copy of the GNU General Public License          --








    +-- along with this program.  If not, see .      --








    +--------------------------------------------------------------------------------








    +library ieee;








    +use ieee.std_logic_1164.all;








    +use ieee.numeric_std.all;








    +








    +library work;








    +use work.iwb.all;








    +use work.ikeyb.all;








    +








    +entity tb_keyb is








    +   port(








    +      CLK      : in  std_logic;








    +      PS2_CLK  : in  std_logic;








    +      PS2_DATA : in  std_logic;








    +      LED      : out std_logic_vector(7 downto 0)








    +   );








    +end tb_keyb;








    +








    +architecture tb of tb_keyb is








    +








    +   signal si   : slave_in_t;








    +   signal so   : slave_out_t;








    +   signal intr : std_logic;








    +begin








    +








    +   si.clk <= CLK;








    +   si.rst <= '0';








    +   si.we  <= '0';








    +   si.stb <= '1' when intr = '1' else '0';








    +








    +   uut0 : keyb port map(








    +      si       => si,








    +      so       => so,








    +      PS2_CLK  => PS2_CLK,








    +      PS2_DATA => PS2_DATA,








    +      intr     => intr








    +   );








    +








    +   LED <= so.dat(7 downto 0);








    +end tb;








    \ No newline at end of file








    Index: layer2/trunk/vhdl/keyb/bench/tb_ps2.vhd








    ===================================================================








    --- layer2/trunk/vhdl/keyb/bench/tb_ps2.vhd	(nonexistent)








    +++ layer2/trunk/vhdl/keyb/bench/tb_ps2.vhd	(revision 2)








    @@ -0,0 +1,62 @@








    +--------------------------------------------------------------------------------








    +--                                                                            --








    +--------------------------------------------------------------------------------








    +-- Version:  1.0                                                              --








    +-- Device:   Spartan 3E                                                       --








    +--                                                                            --








    +-- DESCRIPTION                                                                --








    +--                                                                            --








    +--                                                                            --








    +--------------------------------------------------------------------------------








    +-- Copyright (C)2011  Mathias H�rtnagl          --








    +--                                                                            --








    +-- This program is free software: you can redistribute it and/or modify       --








    +-- it under the terms of the GNU General Public License as published by       --








    +-- the Free Software Foundation, either version 3 of the License, or          --








    +-- (at your option) any later version.                                        --








    +--                                                                            --








    +-- This program is distributed in the hope that it will be useful,            --








    +-- but WITHOUT ANY WARRANTY; without even the implied warranty of             --








    +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the              --








    +-- GNU General Public License for more details.                               --








    +--                                                                            --








    +-- You should have received a copy of the GNU General Public License          --








    +-- along with this program.  If not, see .      --








    +--------------------------------------------------------------------------------








    +library ieee;








    +use ieee.std_logic_1164.all;








    +use ieee.numeric_std.all;








    +








    +entity tb_ps2 is








    +   port(








    +      CLK      : in  std_logic;








    +      PS2_CLK  : in  std_logic;








    +      PS2_DATA : in  std_logic;








    +      LED      : out std_logic_vector(7 downto 0)








    +   );








    +end tb_ps2;








    +








    +architecture tb of tb_ps2 is








    +








    +   component ps2 is








    +      port(








    +         clk      : in  std_logic;








    +         rst      : in  std_logic;








    +         PS2_CLK  : in  std_logic;








    +         PS2_DATA : in  std_logic;








    +         char     : out std_logic_vector(7 downto 0);








    +         rx_done  : out std_logic








    +      );








    +   end component;








    +








    +begin








    +








    +   uut0 : ps2 port map(








    +      clk      => CLK,








    +      rst      => '0',








    +      PS2_CLK  => PS2_CLK,








    +      PS2_DATA => PS2_DATA,








    +      char     => LED,








    +      rx_done  => open








    +   );








    +end tb;








    \ No newline at end of file








    Index: layer2/trunk/vhdl/keyb/bench/keyb_constr.ucf








    ===================================================================








    --- layer2/trunk/vhdl/keyb/bench/keyb_constr.ucf	(nonexistent)








    +++ layer2/trunk/vhdl/keyb/bench/keyb_constr.ucf	(revision 2)








    @@ -0,0 +1,16 @@








    +# On-Board Clock








    +NET "CLK" LOC = "C9" |IOSTANDARD = LVCMOS33 ;








    +NET "CLK" PERIOD = 20.0 ns HIGH 40%;








    +








    +NET "PS2_CLK"  LOC = "G14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;








    +NET "PS2_DATA" LOC = "G13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;








    +








    +# LED Connections








    +NET "LED<7>" LOC = "F9"  | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;








    +NET "LED<6>" LOC = "E9"  | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;








    +NET "LED<5>" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;








    +NET "LED<4>" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;








    +NET "LED<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;








    +NET "LED<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;








    +NET "LED<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;








    +NET "LED<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;








    \ No newline at end of file








    Index: layer2/trunk/vhdl/keyb/bench








    ===================================================================








    --- layer2/trunk/vhdl/keyb/bench	(nonexistent)








    +++ layer2/trunk/vhdl/keyb/bench	(revision 2)
















    
    layer2/trunk/vhdl/keyb/bench














    Property changes :



    Added: bugtraq:number








    ## -0,0 +1 ##








    +true








    \ No newline at end of property








    Index: layer2/trunk/vhdl/keyb/rtl/ikeyb.vhd








    ===================================================================








    --- layer2/trunk/vhdl/keyb/rtl/ikeyb.vhd	(nonexistent)








    +++ layer2/trunk/vhdl/keyb/rtl/ikeyb.vhd	(revision 2)








    @@ -0,0 +1,57 @@








    +--------------------------------------------------------------------------------








    +-- PS2 Keyboard Controller                                                    --








    +--------------------------------------------------------------------------------








    +-- The controller does not distinguish extended and normal keys. Most of the  --








    +-- practically relevant keys are without ambiguity. The controller ignores    --








    +-- all unmapped keys (see ascii.vhd).                                         --








    +--                                                                            --








    +-- REFERENCES                                                                 --








    +--                                                                            --








    +--  [1] Chu Pong P., FPGA Prototyping By VHDL Examples,                       --








    +--      John Wiley & Sons Inc., Hoboken, New Jersy, 2008,                     --








    +--      ISBN: 978-0470185315                                                  --








    +--                                                                            --








    +--  [2] Z80 System On A Chip                                                  --








    +--                           --








    +--  [3] Keyboard Scancode Table                                               --








    +--           --








    +--  [4] PS2 Protocol                                                          --








    +--                          --








    +--                                                                            --








    +--------------------------------------------------------------------------------








    +-- Copyright (C)2011  Mathias H�rtnagl          --








    +--                                                                            --








    +-- This program is free software: you can redistribute it and/or modify       --








    +-- it under the terms of the GNU General Public License as published by       --








    +-- the Free Software Foundation, either version 3 of the License, or          --








    +-- (at your option) any later version.                                        --








    +--                                                                            --








    +-- This program is distributed in the hope that it will be useful,            --








    +-- but WITHOUT ANY WARRANTY; without even the implied warranty of             --








    +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the              --








    +-- GNU General Public License for more details.                               --








    +--                                                                            --








    +-- You should have received a copy of the GNU General Public License          --








    +-- along with this program.  If not, see .      --








    +--------------------------------------------------------------------------------








    +library ieee;








    +use ieee.std_logic_1164.all;








    +use ieee.numeric_std.all;








    +








    +library work;








    +use work.iwb.all;








    +








    +package ikeyb is








    +








    +   component keyb is








    +      port(








    +         si        : in  slave_in_t;








    +         so        : out slave_out_t;








    +      -- Non-Wishbone Signals








    +         PS2_CLK   : in  std_logic;








    +         PS2_DATA  : in  std_logic;








    +         intr      : out std_logic








    +      );








    +   end component;








    +








    +end ikeyb;








    \ No newline at end of file








    Index: layer2/trunk/vhdl/keyb/rtl/ps2.vhd








    ===================================================================








    --- layer2/trunk/vhdl/keyb/rtl/ps2.vhd	(nonexistent)








    +++ layer2/trunk/vhdl/keyb/rtl/ps2.vhd	(revision 2)








    @@ -0,0 +1,136 @@








    +--------------------------------------------------------------------------------








    +-- PS2 Controller                                                             --








    +--------------------------------------------------------------------------------








    +-- Copyright (C)2011  Mathias H�rtnagl          --








    +--                                                                            --








    +-- This program is free software: you can redistribute it and/or modify       --








    +-- it under the terms of the GNU General Public License as published by       --








    +-- the Free Software Foundation, either version 3 of the License, or          --








    +-- (at your option) any later version.                                        --








    +--                                                                            --








    +-- This program is distributed in the hope that it will be useful,            --








    +-- but WITHOUT ANY WARRANTY; without even the implied warranty of             --








    +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the              --








    +-- GNU General Public License for more details.                               --








    +--                                                                            --








    +-- You should have received a copy of the GNU General Public License          --








    +-- along with this program.  If not, see .      --








    +--------------------------------------------------------------------------------








    +library ieee;








    +use ieee.std_logic_1164.all;








    +use ieee.numeric_std.all;








    +








    +entity ps2 is








    +   port(








    +      clk      : in  std_logic;








    +      rst      : in  std_logic;








    +      PS2_CLK  : in  std_logic;








    +      PS2_DATA : in  std_logic;








    +      char     : out std_logic_vector(7 downto 0);








    +      rx_done  : out std_logic








    +   );








    +end ps2;








    +








    +architecture rtl of ps2 is








    +








    +   type ps2_state_t is (Start, Data, Parity, Stop, Ack);








    +








    +   signal p, pin    : ps2_state_t := Start;








    +   signal s, sin    : std_logic_vector(7 downto 0);








    +   signal n, nin    : natural range 0 to 7;








    +   signal f, fin    : std_logic_vector(7 downto 0);








    +   signal t, tin    : std_logic;








    +   signal fall_edge : std_logic;








    +begin








    +








    +   -----------------------------------------------------------------------------








    +   -- Input Signal Debounce                                                   --








    +   -----------------------------------------------------------------------------








    +   -- the frequency of the PS2 clock signal is about 20 to 30 KHz. To avoid   --








    +   -- undesired glitches, wait 8 cycles for a stable signal.                  --








    +   -----------------------------------------------------------------------------








    +   fin <= PS2_CLK & f(7 downto 1);








    +








    +   tin <= '1' when f = x"FF" else








    +          '0' when f = x"00" else








    +          t;








    +








    +     filter : process(clk)








    +   begin








    +      if rising_edge(clk) then








    +         f <= fin;








    +         t <= tin;








    +      end if;








    +   end process;








    +








    +   fall_edge <= t and (not tin);








    +








    +   -----------------------------------------------------------------------------








    +   -- PS2 Read                                                               --








    +   -----------------------------------------------------------------------------








    +   fsm : process(p, s, n, fall_edge, PS2_DATA)








    +   begin








    +








    +      rx_done <= '0';








    +








    +      pin <= p;








    +      sin <= s;








    +      nin <= n;








    +








    +      case p is








    +








    +         -- Wait for first falling edge. The first bit is a start bit with








    +         -- value '0'. We do not check that.








    +         when Start =>








    +            if fall_edge = '1' then








    +               nin <= 0;








    +               pin <= Data;








    +            end if;








    +








    +         -- On the next 8 falling edges we shuffle data into the shift register.








    +         -- The keyboard sends the LSB first.








    +         when Data =>








    +            if fall_edge = '1' then








    +               sin <= PS2_DATA & s(7 downto 1);








    +               if n = 7 then








    +                  pin <= Parity;








    +               else








    +                  nin <= n + 1;








    +               end if;








    +            end if;








    +








    +         -- Fetch odd parity bit. No parity check here.








    +         when Parity =>








    +            if fall_edge = '1' then








    +               sin <= PS2_DATA & s(7 downto 1);    -- A mystery.








    +               pin <= Stop;








    +            end if;








    +








    +         -- Fetch stop bit. Always '1'.








    +         when Stop =>








    +            if fall_edge = '1' then








    +               pin <= Ack;








    +            end if;








    +








    +         -- One cycle tick to indicate a complete reception.








    +         when Ack =>








    +            rx_done <= '1';








    +            pin     <= Start;








    +








    +      end case;








    +   end process;








    +








    +     reg : process(clk)








    +   begin








    +      if rising_edge(clk) then








    +         p <= pin;








    +         s <= sin;








    +         n <= nin;








    +         f <= fin;








    +








    +         if rst = '1' then p <= Start; end if;








    +      end if;








    +   end process;








    +








    +   char <= s;








    +end rtl;








    Index: layer2/trunk/vhdl/keyb/rtl/ascii.vhd








    ===================================================================








    --- layer2/trunk/vhdl/keyb/rtl/ascii.vhd	(nonexistent)








    +++ layer2/trunk/vhdl/keyb/rtl/ascii.vhd	(revision 2)








    @@ -0,0 +1,171 @@








    +--------------------------------------------------------------------------------








    +-- PS2 Keyboard Controller - German Keyboard Layout                           --








    +--------------------------------------------------------------------------------








    +-- Copyright (C)2011  Mathias H�rtnagl          --








    +--                                                                            --








    +-- This program is free software: you can redistribute it and/or modify       --








    +-- it under the terms of the GNU General Public License as published by       --








    +-- the Free Software Foundation, either version 3 of the License, or          --








    +-- (at your option) any later version.                                        --








    +--                                                                            --








    +-- This program is distributed in the hope that it will be useful,            --








    +-- but WITHOUT ANY WARRANTY; without even the implied warranty of             --








    +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the              --








    +-- GNU General Public License for more details.                               --








    +--                                                                            --








    +-- You should have received a copy of the GNU General Public License          --








    +-- along with this program.  If not, see .      --








    +--------------------------------------------------------------------------------








    +library ieee;








    +use ieee.std_logic_1164.all;








    +use ieee.numeric_std.all;








    +








    +entity ascii is








    +   port(








    +      clk   : in  std_logic;








    +      shft  : in  std_logic;








    +      altgr : in  std_logic;








    +      code  : in  std_logic_vector(7 downto 0);








    +      char  : out std_logic_vector(7 downto 0)








    +   );








    +end ascii;








    +








    +architecture rtl of ascii is








    +begin








    +   conv : process(clk)








    +   begin








    +      if rising_edge(clk) then








    +         case code is








    +            --------------------------------------------------------------------








    +            -- Keys that are independend of the state of SHFT and ALTGR.      --








    +            --------------------------------------------------------------------








    +            when X"66" => char <= X"08"; -- BS  (BACKSPACE)








    +            when X"0d" => char <= X"09"; -- HT  (TAB)








    +            when X"5a" => char <= X"0d"; -- CR  (ENTER)








    +            when X"76" => char <= X"1b"; -- ESC (ESCAPE)








    +            when X"29" => char <= X"20"; -- SP  (SPACE)








    +            when X"71" => char <= X"7f"; -- DEL (DELETE)








    +            when X"7e" => char <= X"80"; -- SCROLL








    +            when X"75" => char <= X"f0"; -- UP ARROW








    +            when X"6b" => char <= X"f1"; -- LEFT ARROW








    +            when X"72" => char <= X"f2"; -- DOWN ARROW








    +            when X"74" => char <= X"f3"; -- RIGHT ARROW








    +            --when X"" => char <= X""








    +








    +            when others =>








    +               case (altgr & shft & code) is








    +                  --------------------------------------------------------------








    +                  -- SHFT and ALTGR not pressed.                              --








    +                  --------------------------------------------------------------








    +                  when "00" & X"0e" => char <= X"5e"; -- ^








    +                  when "00" & X"15" => char <= X"71"; -- q








    +                  when "00" & X"16" => char <= X"31"; -- 1








    +                  when "00" & X"1a" => char <= X"79"; -- y








    +                  when "00" & X"1b" => char <= X"73"; -- s








    +                  when "00" & X"1c" => char <= X"61"; -- a








    +                  when "00" & X"1d" => char <= X"77"; -- w








    +                  when "00" & X"1e" => char <= X"32"; -- 2








    +                  when "00" & X"21" => char <= X"63"; -- c








    +                  when "00" & X"22" => char <= X"78"; -- x








    +                  when "00" & X"23" => char <= X"64"; -- d








    +                  when "00" & X"24" => char <= X"65"; -- e








    +                  when "00" & X"25" => char <= X"34"; -- 4








    +                  when "00" & X"26" => char <= X"33"; -- 3








    +                  when "00" & X"2a" => char <= X"76"; -- v








    +                  when "00" & X"2b" => char <= X"66"; -- f








    +                  when "00" & X"2c" => char <= X"74"; -- t








    +                  when "00" & X"2d" => char <= X"72"; -- r








    +                  when "00" & X"2e" => char <= X"35"; -- 5








    +                  when "00" & X"31" => char <= X"6e"; -- n








    +                  when "00" & X"32" => char <= X"62"; -- b








    +                  when "00" & X"33" => char <= X"68"; -- h








    +                  when "00" & X"34" => char <= X"67"; -- g








    +                  when "00" & X"35" => char <= X"7a"; -- z








    +                  when "00" & X"36" => char <= X"36"; -- 6








    +                  when "00" & X"3a" => char <= X"6d"; -- m








    +                  when "00" & X"3b" => char <= X"6a"; -- j








    +                  when "00" & X"3c" => char <= X"75"; -- u








    +                  when "00" & X"3d" => char <= X"37"; -- 7








    +                  when "00" & X"3e" => char <= X"38"; -- 8








    +                  when "00" & X"41" => char <= X"2c"; -- ,








    +                  when "00" & X"42" => char <= X"6b"; -- k








    +                  when "00" & X"43" => char <= X"69"; -- i








    +                  when "00" & X"44" => char <= X"6f"; -- o








    +                  when "00" & X"45" => char <= X"30"; -- 0








    +                  when "00" & X"46" => char <= X"39"; -- 9








    +                  when "00" & X"49" => char <= X"2e"; -- .








    +                  when "00" & X"4a" => char <= X"2d"; -- -








    +                  when "00" & X"4b" => char <= X"6c"; -- l








    +                  when "00" & X"4d" => char <= X"70"; -- p








    +                  when "00" & X"5b" => char <= X"2b"; -- +








    +                  when "00" & X"5d" => char <= X"23"; -- #








    +                  when "00" & X"61" => char <= X"3c"; -- <








    +                  --------------------------------------------------------------








    +                  -- SHFT pressed.                                            --








    +                  --------------------------------------------------------------








    +                  when "01" & X"15" => char <= X"51"; -- Q








    +                  when "01" & X"16" => char <= X"21"; -- !








    +                  when "01" & X"1a" => char <= X"59"; -- Y








    +                  when "01" & X"1b" => char <= X"53"; -- S








    +                  when "01" & X"1c" => char <= X"41"; -- A








    +                  when "01" & X"1d" => char <= X"57"; -- W








    +                  when "01" & X"1e" => char <= X"22"; -- "








    +                  when "01" & X"21" => char <= X"43"; -- C








    +                  when "01" & X"22" => char <= X"58"; -- X








    +                  when "01" & X"23" => char <= X"44"; -- D








    +                  when "01" & X"24" => char <= X"45"; -- E








    +                  when "01" & X"25" => char <= X"24"; -- $








    +                  when "01" & X"2a" => char <= X"56"; -- V








    +                  when "01" & X"2b" => char <= X"46"; -- F








    +                  when "01" & X"2c" => char <= X"54"; -- T








    +                  when "01" & X"2d" => char <= X"52"; -- R








    +                  when "01" & X"2e" => char <= X"25"; -- %








    +                  when "01" & X"31" => char <= X"4e"; -- N








    +                  when "01" & X"32" => char <= X"42"; -- B








    +                  when "01" & X"33" => char <= X"48"; -- H








    +                  when "01" & X"34" => char <= X"47"; -- G








    +                  when "01" & X"35" => char <= X"5a"; -- Z








    +                  when "01" & X"36" => char <= X"26"; -- &








    +                  when "01" & X"3a" => char <= X"4d"; -- M








    +                  when "01" & X"3b" => char <= X"4a"; -- J








    +                  when "01" & X"3c" => char <= X"55"; -- U








    +                  when "01" & X"3d" => char <= X"2f"; -- /








    +                  when "01" & X"3e" => char <= X"28"; -- (








    +                  when "01" & X"41" => char <= X"3b"; -- ;








    +                  when "01" & X"42" => char <= X"4b"; -- K








    +                  when "01" & X"43" => char <= X"49"; -- I








    +                  when "01" & X"44" => char <= X"4f"; -- O








    +                  when "01" & X"45" => char <= X"3d"; -- =








    +                  when "01" & X"46" => char <= X"29"; -- )








    +                  when "01" & X"49" => char <= X"3a"; -- :








    +                  when "01" & X"4a" => char <= X"5f"; -- _








    +                  when "01" & X"4b" => char <= X"4c"; -- L








    +                  when "01" & X"4d" => char <= X"50"; -- P








    +                  when "01" & X"4e" => char <= X"3f"; -- ?








    +                  when "01" & X"55" => char <= X"60"; -- `








    +                  when "01" & X"5b" => char <= X"2a"; -- *








    +                  when "01" & X"5d" => char <= X"27"; -- '








    +                  when "01" & X"61" => char <= X"3e"; -- >








    +                  --------------------------------------------------------------








    +                  -- ALTGR pressed.                                           --








    +                  --------------------------------------------------------------








    +                  when "10" & X"15" => char <= X"40"; -- @








    +                  when "10" & X"3d" => char <= X"7b"; -- {








    +                  when "10" & X"3e" => char <= X"5b"; -- [








    +                  when "10" & X"45" => char <= X"7d"; -- }








    +                  when "10" & X"46" => char <= X"5d"; -- ]








    +                  when "10" & X"4e" => char <= X"5c"; -- \








    +                  when "10" & X"5b" => char <= X"7e"; -- ~








    +                  when "10" & X"61" => char <= X"7c"; -- |








    +                  --------------------------------------------------------------








    +                  -- SHFT and ALTGR pressed.                                  --








    +                  --------------------------------------------------------------








    +                  --------------------------------------------------------------








    +                  -- Everything else returns the empty key X"00".             --








    +                  --------------------------------------------------------------








    +                  when others => char <= X"00";








    +               end case;








    +         end case;








    +      end if;








    +   end process;








    +end rtl;








    \ No newline at end of file








    Index: layer2/trunk/vhdl/keyb/rtl/keyb.vhd








    ===================================================================








    --- layer2/trunk/vhdl/keyb/rtl/keyb.vhd	(nonexistent)








    +++ layer2/trunk/vhdl/keyb/rtl/keyb.vhd	(revision 2)








    @@ -0,0 +1,299 @@








    +--------------------------------------------------------------------------------








    +-- PS2 Keyboard Controller                                                    --








    +--------------------------------------------------------------------------------








    +-- Copyright (C)2011  Mathias H�rtnagl          --








    +--                                                                            --








    +-- This program is free software: you can redistribute it and/or modify       --








    +-- it under the terms of the GNU General Public License as published by       --








    +-- the Free Software Foundation, either version 3 of the License, or          --








    +-- (at your option) any later version.                                        --








    +--                                                                            --








    +-- This program is distributed in the hope that it will be useful,            --








    +-- but WITHOUT ANY WARRANTY; without even the implied warranty of             --








    +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the              --








    +-- GNU General Public License for more details.                               --








    +--                                                                            --








    +-- You should have received a copy of the GNU General Public License          --








    +-- along with this program.  If not, see .      --








    +--------------------------------------------------------------------------------








    +-- http://www.computer-engineering.org/ps2keyboard/








    +library ieee;








    +use ieee.std_logic_1164.all;








    +use ieee.numeric_std.all;








    +








    +library work;








    +use work.iwb.all;








    +








    +entity keyb is








    +   port(








    +      si        : in  slave_in_t;








    +      so        : out slave_out_t;








    +   -- Non-Wishbone Signals








    +      PS2_CLK   : in  std_logic;








    +      PS2_DATA  : in  std_logic;








    +      intr      : out std_logic








    +   );








    +end keyb;








    +








    +architecture rtl of keyb is








    +








    +   constant EXTENDED_CODE : std_logic_vector(7 downto 0) := x"E0";








    +   constant BREAK_CODE    : std_logic_vector(7 downto 0) := x"F0";








    +   constant CAPS          : std_logic_vector(7 downto 0) := x"58";








    +   constant LEFT_SHIFT    : std_logic_vector(7 downto 0) := x"12";








    +   constant RIGHT_SHIFT   : std_logic_vector(7 downto 0) := x"59";








    +   constant LEFT_CTRL     : std_logic_vector(7 downto 0) := x"14";








    +   constant LEFT_ALT      : std_logic_vector(7 downto 0) := x"11";








    +   constant RIGHT_CTRL    : std_logic_vector(7 downto 0) := x"14";








    +   constant RIGHT_ALT     : std_logic_vector(7 downto 0) := x"11";








    +








    +   component ps2 is








    +      port(








    +         clk      : in  std_logic;








    +         rst      : in  std_logic;








    +         PS2_CLK  : in  std_logic;








    +         PS2_DATA : in  std_logic;








    +         char     : out std_logic_vector(7 downto 0);








    +         rx_done  : out std_logic








    +      );








    +   end component;








    +








    +   component ascii is








    +      port(








    +         clk   : in  std_logic;








    +         shft  : in  std_logic;








    +         altgr : in std_logic;








    +         code  : in  std_logic_vector(7 downto 0);








    +         char  : out std_logic_vector(7 downto 0)








    +      );








    +   end component;








    +








    +   attribute RAM_STYLE : string;








    +   attribute RAM_STYLE of ascii : component is "BLOCK";








    +








    +   type state_t is (Idle, ExtCode, BrkCode, ExtRelease, Translate, Check,








    +                    Ack, Ack2);








    +








    +   type char_t is record








    +      shft  : std_logic;                           -- Shift key.








    +      cps   : std_logic;                           -- Caps key.








    +      ctrl  : std_logic;                           -- Control key.








    +      alt   : std_logic;                           -- Alt key.








    +      altgr : std_logic;                           -- Alt Gr key.








    +      m     : std_logic_vector(7 downto 0);        -- Scan code.








    +   end record;








    +








    +   signal k, kin   : state_t := Idle;              -- Keyboard controller state.








    +   signal c, cin   : char_t;                       -- Character structure.








    +   signal code     : std_logic_vector(7 downto 0); -- PS2 scan code.








    +   signal char     : std_logic_vector(7 downto 0); -- ASCII character.








    +   signal shftcps  : std_logic;                    -- SHIFT xor CAPS.








    +   signal rx_done  : std_logic;                    -- PS2 receive done tick.








    +   signal key_done : std_logic;                    -- Keyboard ctrl done tick.








    +begin








    +








    +   -----------------------------------------------------------------------------








    +   -- PS2 Controller                                                          --








    +   -----------------------------------------------------------------------------








    +   ps2_ctrl : ps2 port map(








    +      clk      => si.clk,








    +      rst      => si.rst,








    +      PS2_CLK  => PS2_CLK,








    +      PS2_DATA => PS2_DATA,








    +      char     => code,








    +      rx_done  => rx_done








    +   );








    +








    +   -----------------------------------------------------------------------------








    +   -- ScanCode To ASCII ROM                                                   --








    +   -----------------------------------------------------------------------------








    +   shftcps <= c.shft xor c.cps;     -- If both are set, turn to lower case.








    +








    +   ascii_rom : ascii port map(








    +      clk   => si.clk,








    +      shft  => shftcps,








    +      altgr => c.altgr,








    +      code  => c.m,








    +      char  => char








    +   );








    +








    +   -----------------------------------------------------------------------------








    +   -- Keyboard Control                                                        --








    +   -----------------------------------------------------------------------------








    +   key : process(k, c, rx_done, code, si.stb, si.we, si, char)








    +   begin








    +








    +      kin <= k;








    +      cin <= c;








    +








    +      intr   <= '0';








    +      so.ack <= '0';








    +      --key_done <= '0';








    +








    +      case k is








    +








    +         -- Wait for some key input.








    +         when Idle =>








    +            if rx_done = '1' then








    +               case code is








    +








    +                  when EXTENDED_CODE =>








    +                     kin   <= ExtCode;








    +








    +                  when BREAK_CODE =>








    +                     kin   <= BrkCode;








    +








    +                  -- User pressed a functional key. Just latch and then return








    +                  -- to Idle state. The CPU does not need to be bothered.








    +                  when LEFT_SHIFT | RIGHT_SHIFT =>








    +                     cin.shft <= '1';








    +                     kin      <= Idle;








    +                  when CAPS =>








    +                     cin.cps  <= not c.cps;








    +                     kin      <= Idle;








    +                  when LEFT_CTRL =>








    +                     cin.ctrl <= '1';








    +                     kin      <= Idle;








    +                  when LEFT_ALT =>








    +                     cin.alt  <= '1';








    +                     kin      <= Idle;








    +








    +                  -- The actual key code.








    +                  when others =>








    +                     cin.m <= code;








    +                     kin   <= Translate;








    +               end case;








    +            end if;








    +








    +         -- PREVIOUS STATE: Idle.








    +         when ExtCode =>








    +            if rx_done = '1' then








    +               case code is








    +








    +                  -- If we receive a BREAK CODE we know that the following








    +                  -- pressed key (represented by the next byte) has been








    +                  -- released.








    +                  when BREAK_CODE =>








    +                     kin   <= ExtRelease;








    +








    +                  -- The RIGHT CTRL and RIGHT ALT (ALT GR) are the same key








    +                  -- codes as LEFT CTRL and LEFT ALT plus an preceeding EXTENDED








    +                  -- CODE. RIGHT ALT (ALT GR) has a different functional








    +                  -- meaning.








    +                  when RIGHT_CTRL =>








    +                     cin.ctrl  <= '1';








    +                     kin       <= Idle;








    +                  when RIGHT_ALT =>








    +                     cin.altgr <= '1';








    +                     kin       <= Idle;








    +








    +                  -- Once more the actual key code.








    +                  when others =>








    +                     cin.m <= code;








    +                     kin   <= Translate;








    +               end case;








    +            end if;








    +








    +         -- PREVIOUS STATE: Idle.








    +         when BrkCode =>








    +            if rx_done = '1' then








    +               case code is








    +








    +                  -- A functional key has been released.








    +                  when LEFT_SHIFT | RIGHT_SHIFT =>








    +                     cin.shft <= '0';








    +                     kin      <= Idle;








    +                  when LEFT_CTRL =>








    +                     cin.ctrl <= '0';








    +                     kin      <= Idle;








    +                  when LEFT_ALT =>








    +                     cin.alt  <= '0';








    +                     kin      <= Idle;








    +








    +                  -- Do nothing when CAPS is released.








    +                  when CAPS =>








    +                     kin <= Idle;








    +








    +                  -- Do nothing on key release.








    +                  when others =>








    +                     kin <= Idle;








    +               end case;








    +            end if;








    +








    +         -- PREVIOUS STATE: ExtCode.








    +         -- Either turn off the RIGHT CTRL or RIGHT ALT flags, or receive a non








    +         -- functional key code release.








    +         when ExtRelease =>








    +            if rx_done = '1' then








    +               case code is








    +








    +                  -- The RIGHT CTRL and RIGHT ALT (ALT GR) are the same key








    +                  -- codes as LEFT CTRL and LEFT ALT plus an preceeding EXTENDED








    +                  -- CODE. RIGHT ALT (ALT GR) has a different functional








    +                  -- meaning.








    +                  when RIGHT_CTRL =>








    +                     cin.ctrl <= '0';








    +                     kin      <= Idle;








    +                  when RIGHT_ALT =>








    +                     cin.altgr <= '0';








    +                     kin       <= Idle;








    +








    +                  -- Do nothing on key release.








    +                  when others =>








    +                     kin   <= Idle;








    +               end case;








    +            end if;








    +








    +         -- PREVIOUS STATES: Idle, ExtCode.








    +         -- One cycle delay for the ASCII-ROM to translate the keyboard code.








    +         when Translate =>








    +            kin <= Check;








    +








    +         -- Ignore all undefined keys.








    +         when Check =>








    +            if char = x"00" then








    +               kin <= Idle;








    +            else








    +               kin <= Ack;








    +            end if;








    +








    +         -- Wait for a Wishbone read, set interrrupt meanwhile.








    +         when Ack =>








    +            intr <= '1';








    +            if wb_read(si) then








    +               so.ack <= '1';








    +               --key_done <= '1';








    +               kin      <= Ack2;








    +            end if;








    +








    +         -- Wait and hold done signal until master notices ack signal and pulls








    +         -- stb down.








    +         when Ack2 =>








    +            intr   <= '1';








    +            so.ack <= '1';








    +            --key_done <= '1';








    +            if si.stb = '0' then








    +               kin <= Idle;








    +            end if;








    +








    +      end case;








    +   end process;








    +








    +   so.dat <= x"0000" & c.shft & c.ctrl & c.alt & c.altgr & x"0" & char;








    +   --so.ack <= key_done;








    +








    +   -----------------------------------------------------------------------------








    +   -- Registers                                                               --








    +   -----------------------------------------------------------------------------








    +     reg : process(si.clk)








    +   begin








    +      if rising_edge(si.clk) then








    +         k <= kin;








    +         c <= cin;








    +         if si.rst = '1' then








    +            k <= Idle;








    +            c <= ('0','0','0','0','0',(others => '-'));








    +         end if;








    +      end if;








    +   end process;








    +end rtl;








    Index: layer2/trunk/vhdl/keyb/rtl








    ===================================================================








    --- layer2/trunk/vhdl/keyb/rtl	(nonexistent)








    +++ layer2/trunk/vhdl/keyb/rtl	(revision 2)
















    
    layer2/trunk/vhdl/keyb/rtl














    Property changes :



    Added: bugtraq:number








    ## -0,0 +1 ##








    +true








    \ No newline at end of property








    Index: layer2/trunk/vhdl/keyb








    ===================================================================








    --- layer2/trunk/vhdl/keyb	(nonexistent)








    +++ layer2/trunk/vhdl/keyb	(revision 2)
















    
    layer2/trunk/vhdl/keyb














    Property changes :



    Added: bugtraq:number








    ## -0,0 +1 ##








    +true








    \ No newline at end of property








    Index: layer2/trunk/vhdl/rs232/rtl/counter.vhd








    ===================================================================








    --- layer2/trunk/vhdl/rs232/rtl/counter.vhd	(nonexistent)








    +++ layer2/trunk/vhdl/rs232/rtl/counter.vhd	(revision 2)








    @@ -0,0 +1,55 @@








    +--------------------------------------------------------------------------------








    +-- Baud Rate Counter                                                          --








    +--------------------------------------------------------------------------------








    +-- Copyright (C)2011  Mathias H�rtnagl          --








    +--                                                                            --








    +-- This program is free software: you can redistribute it and/or modify       --








    +-- it under the terms of the GNU General Public License as published by       --








    +-- the Free Software Foundation, either version 3 of the License, or          --








    +-- (at your option) any later version.                                        --








    +--                                                                            --








    +-- This program is distributed in the hope that it will be useful,            --








    +-- but WITHOUT ANY WARRANTY; without even the implied warranty of             --








    +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the              --








    +-- GNU General Public License for more details.                               --








    +--                                                                            --








    +-- You should have received a copy of the GNU General Public License          --








    +-- along with this program.  If not, see .      --








    +--------------------------------------------------------------------------------








    +library ieee;








    +use ieee.std_logic_1164.all;








    +use ieee.numeric_std.all;








    +








    +entity counter is








    +   generic(








    +      FREQ : positive := 50;           -- Clock frequency in MHz.








    +      RATE : positive := 19200         -- Baud rate (times sampling rate).








    +   );








    +   port(








    +      clk    : in  std_logic;








    +      rst    : in  std_logic;








    +      tick   : out std_logic








    +   );








    +end counter;








    +








    +architecture rtl of counter is








    +








    +   constant MAX : positive := (FREQ*1000000)/(RATE*16);








    +








    +   signal c, cin : natural range 0 to MAX;








    +begin








    +








    +   tick <= '1' when c = MAX else '0';








    +   cin  <=  0  when c = MAX else c + 1;








    +








    +   reg : process (clk)








    +   begin








    +      if rising_edge(clk) then








    +         if rst = '1' then








    +            c <= 0;








    +         else








    +            c <= cin;








    +         end if;








    +      end if;








    +   end process;








    +end rtl;








    \ No newline at end of file








    Index: layer2/trunk/vhdl/rs232/rtl/uartt.vhd








    ===================================================================








    --- layer2/trunk/vhdl/rs232/rtl/uartt.vhd	(nonexistent)








    +++ layer2/trunk/vhdl/rs232/rtl/uartt.vhd	(revision 2)








    @@ -0,0 +1,152 @@








    +--------------------------------------------------------------------------------








    +-- UART Transmitter 19200/8N1                                                 --








    +--------------------------------------------------------------------------------








    +-- Copyright (C)2011  Mathias H�rtnagl          --








    +--                                                                            --








    +-- This program is free software: you can redistribute it and/or modify       --








    +-- it under the terms of the GNU General Public License as published by       --








    +-- the Free Software Foundation, either version 3 of the License, or          --








    +-- (at your option) any later version.                                        --








    +--                                                                            --








    +-- This program is distributed in the hope that it will be useful,            --








    +-- but WITHOUT ANY WARRANTY; without even the implied warranty of             --








    +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the              --








    +-- GNU General Public License for more details.                               --








    +--                                                                            --








    +-- You should have received a copy of the GNU General Public License          --








    +-- along with this program.  If not, see .      --








    +--------------------------------------------------------------------------------








    +library ieee;








    +use ieee.std_logic_1164.all;








    +use ieee.numeric_std.all;








    +








    +library work;








    +use work.iwb.all;








    +use work.iuart.all;








    +








    +entity uartt is








    +   port(








    +      si            : in  slave_in_t;








    +      so            : out slave_out_t;








    +   -- Non-Wishbone Signals








    +      RS232_DCE_TXD : out std_logic








    +   );








    +end uartt;








    +








    +architecture rtl of uartt is








    +








    +   type state_t is (Idle, Start, Data, Stop, Ack);








    +








    +   type sender_t is record








    +      s : state_t;                           -- Sender state.








    +      n : natural range 0 to 15;             -- Tick counter.








    +      m : natural range 0 to 7;              -- Data bits counter.








    +      d : std_logic_vector(7 downto 0);      -- Data bits shift register.








    +   end record;








    +








    +   type tx_t is record








    +      tick : std_logic;








    +      rst  : std_logic;








    +      ack  : std_logic;








    +   end record;








    +








    +   signal snd, sndin : sender_t;








    +   signal tx : tx_t;








    +begin








    +








    +   -----------------------------------------------------------------------------








    +   -- Transmitter Rate Generator                                              --








    +   -----------------------------------------------------------------------------








    +   tx_rate : counter








    +      generic map(








    +         FREQ => 50,








    +         RATE => 19200








    +      )








    +      port map(








    +         clk  => si.clk,








    +         rst  => tx.rst,








    +         tick => tx.tick








    +      );








    +








    +   -----------------------------------------------------------------------------








    +   -- Transmitter Controller                                                  --








    +   -----------------------------------------------------------------------------








    +   receiver : process(snd, tx.tick, si)








    +   begin








    +








    +      sndin         <= snd;








    +      tx.rst        <= '0';








    +      tx.ack        <= '0';








    +      RS232_DCE_TXD <= '1';                     -- Idle line is alwasys '1'.








    +








    +      case snd.s is








    +         when Idle =>








    +            tx.rst <= '1';








    +            if wb_write(si) then








    +               sndin.n <= 0;








    +               sndin.d <= si.dat(7 downto 0);








    +               sndin.s <= Start;








    +            end if;








    +








    +         when Start =>








    +            RS232_DCE_TXD <= '0';








    +            if tx.tick = '1' then








    +               if snd.n = 15 then








    +                  sndin.n <= 0;








    +                  sndin.m <= 0;








    +                  sndin.s <= Data;








    +               else








    +                  sndin.n <= snd.n + 1;








    +               end if;








    +            end if;








    +








    +         when Data =>








    +            RS232_DCE_TXD <= snd.d(0);








    +            if tx.tick = '1' then








    +               if snd.n = 15 then








    +                  sndin.n <= 0;








    +                  sndin.d <= '0' & snd.d(7 downto 1);








    +                  if snd.m = 7 then








    +                     sndin.s <= Stop;








    +                  else








    +                     sndin.m <= snd.m + 1;








    +                  end if;








    +               else








    +                  sndin.n <= snd.n + 1;








    +               end if;








    +            end if;








    +








    +         when Stop =>








    +            if tx.tick = '1' then








    +               if snd.n = 15 then








    +                  sndin.s <= Ack;








    +               else








    +                  sndin.n <= snd.n + 1;








    +               end if;








    +            end if;








    +








    +         when Ack =>








    +            tx.ack <= '1';








    +            if si.stb = '0' then








    +               sndin.s <= Idle;








    +            end if;








    +








    +      end case;








    +   end process;








    +








    +   so.dat <= (others => '-');








    +   so.ack <= tx.ack;








    +








    +   -----------------------------------------------------------------------------








    +   -- Registers                                                               --








    +   -----------------------------------------------------------------------------








    +   reg : process(si.clk)








    +   begin








    +      if rising_edge(si.clk) then








    +         snd <= sndin;








    +         if si.rst = '1' then








    +            snd.s <= Idle;








    +         end if;








    +      end if;








    +   end process;








    +end rtl;








    \ No newline at end of file








    Index: layer2/trunk/vhdl/rs232/rtl/iuart.vhd








    ===================================================================








    --- layer2/trunk/vhdl/rs232/rtl/iuart.vhd	(nonexistent)








    +++ layer2/trunk/vhdl/rs232/rtl/iuart.vhd	(revision 2)








    @@ -0,0 +1,69 @@








    +--------------------------------------------------------------------------------








    +-- UART Transceiver 19200/8N1                                                 --








    +--------------------------------------------------------------------------------








    +-- This minimal implementation of an Universal Asynchronous Receiver and      --








    +-- Transmitter (UART) suits a baud rate of 19200 baud/sec as well as 8 bits   --








    +-- of data, no parity bit and one stop bit configuration only. It comprises   --








    +-- two seperate baud generators to receive and transmit simultanously.        --








    +--                                                                            --








    +-- REFERENCES                                                                 --








    +--                                                                            --








    +--  [1] Chu Pong P., FPGA Prototyping By VHDL Examples,                       --








    +--      John Wiley & Sons Inc., Hoboken, New Jersy, 2008,                     --








    +--      ISBN: 978-0470185315                                                  --








    +--                                                                            --








    +--------------------------------------------------------------------------------








    +-- Copyright (C)2011  Mathias H�rtnagl          --








    +--                                                                            --








    +-- This program is free software: you can redistribute it and/or modify       --








    +-- it under the terms of the GNU General Public License as published by       --








    +-- the Free Software Foundation, either version 3 of the License, or          --








    +-- (at your option) any later version.                                        --








    +--                                                                            --








    +-- This program is distributed in the hope that it will be useful,            --








    +-- but WITHOUT ANY WARRANTY; without even the implied warranty of             --








    +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the              --








    +-- GNU General Public License for more details.                               --








    +--                                                                            --








    +-- You should have received a copy of the GNU General Public License          --








    +-- along with this program.  If not, see .      --








    +--------------------------------------------------------------------------------








    +library ieee;








    +use ieee.std_logic_1164.all;








    +use ieee.numeric_std.all;








    +








    +library work;








    +use work.iwb.all;








    +








    +package iuart is








    +








    +   component uartr is








    +      port(








    +         si            : in  slave_in_t;








    +         so            : out slave_out_t;








    +      -- Non-Wishbone Signals








    +         RS232_DCE_RXD : in  std_logic








    +      );








    +   end component;








    +








    +   component uartt is








    +      port(








    +         si            : in  slave_in_t;








    +         so            : out slave_out_t;








    +      -- Non-Wishbone Signals








    +         RS232_DCE_TXD : out std_logic








    +      );








    +   end component;








    +








    +   component counter is








    +      generic(








    +         FREQ : positive := 50;           -- Clock frequency in MHz.








    +         RATE : positive := 19200         -- Baud rate.








    +      );








    +      port(








    +         clk    : in  std_logic;








    +         rst    : in  std_logic;








    +         tick   : out std_logic








    +      );








    +   end component;








    +end iuart;








    \ No newline at end of file








    Index: layer2/trunk/vhdl/rs232/rtl/uartr.vhd








    ===================================================================








    --- layer2/trunk/vhdl/rs232/rtl/uartr.vhd	(nonexistent)








    +++ layer2/trunk/vhdl/rs232/rtl/uartr.vhd	(revision 2)








    @@ -0,0 +1,156 @@








    +--------------------------------------------------------------------------------








    +-- UART Receiver 19200/8N1                                                    --








    +--------------------------------------------------------------------------------








    +-- Copyright (C)2011  Mathias H�rtnagl          --








    +--                                                                            --








    +-- This program is free software: you can redistribute it and/or modify       --








    +-- it under the terms of the GNU General Public License as published by       --








    +-- the Free Software Foundation, either version 3 of the License, or          --








    +-- (at your option) any later version.                                        --








    +--                                                                            --








    +-- This program is distributed in the hope that it will be useful,            --








    +-- but WITHOUT ANY WARRANTY; without even the implied warranty of             --








    +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the              --








    +-- GNU General Public License for more details.                               --








    +--                                                                            --








    +-- You should have received a copy of the GNU General Public License          --








    +-- along with this program.  If not, see .      --








    +--------------------------------------------------------------------------------








    +library ieee;








    +use ieee.std_logic_1164.all;








    +use ieee.numeric_std.all;








    +








    +library work;








    +use work.iwb.all;








    +use work.iuart.all;








    +








    +entity uartr is








    +   port(








    +      si            : in  slave_in_t;








    +      so            : out slave_out_t;








    +   -- Non-Wishbone Signals








    +      RS232_DCE_RXD : in  std_logic








    +   );








    +end uartr;








    +








    +architecture rtl of uartr is








    +








    +   type state_t is (Idle, Start, Data, Stop, Ack, Ack2);








    +








    +   type receiver_t is record








    +      s : state_t;                           -- Receiver state.








    +      n : natural range 0 to 15;             -- Tick counter.








    +      m : natural range 0 to 7;              -- Data bits counter.








    +      d : std_logic_vector(7 downto 0);      -- Data bits shift register.








    +   end record;








    +








    +   type rx_t is record








    +      tick : std_logic;








    +      rst  : std_logic;








    +      ack  : std_logic;








    +   end record;








    +








    +   signal rcv, rcvin : receiver_t;








    +   signal rx : rx_t;








    +begin








    +








    +   -----------------------------------------------------------------------------








    +   -- Receiver Rate Generator                                                 --








    +   -----------------------------------------------------------------------------








    +   rx_rate : counter








    +      generic map(








    +         FREQ => 50,








    +         RATE => 19200








    +      )








    +      port map(








    +         clk  => si.clk,








    +         rst  => rx.rst,








    +         tick => rx.tick








    +      );








    +








    +   -----------------------------------------------------------------------------








    +   -- Receiver Controller                                                     --








    +   -----------------------------------------------------------------------------








    +   receiver : process(RS232_DCE_RXD, rcv, rx.tick, si)








    +   begin








    +








    +      rcvin  <= rcv;








    +      rx.rst <= '0';








    +      rx.ack <= '0';








    +








    +      case rcv.s is








    +








    +         -- Wait for receive signal to be set low - Start of new data package.








    +         when Idle =>








    +            rx.rst <= '1';








    +            if RS232_DCE_RXD = '0' then








    +               rcvin.n <= 0;








    +               rcvin.s <= Start;








    +            end if;








    +








    +         when Start =>








    +            if rx.tick = '1' then








    +               if rcv.n = 7 then








    +                  rcvin.n <= 0;








    +                  rcvin.m <= 0;








    +                  rcvin.s <= Data;








    +               else








    +                  rcvin.n <= rcv.n + 1;








    +               end if;








    +            end if;








    +








    +         -- Shift in all data bits. Least significant bit first.








    +         when Data =>








    +            if rx.tick = '1' then








    +               if rcv.n = 15 then








    +                  rcvin.n <= 0;








    +                  rcvin.d <= RS232_DCE_RXD & rcv.d(7 downto 1);








    +                  if rcv.m = 7 then








    +                     rcvin.s <= Stop;








    +                  else








    +                     rcvin.m <= rcv.m + 1;








    +                  end if;








    +               else








    +                  rcvin.n <= rcv.n + 1;








    +               end if;








    +            end if;








    +








    +         when Stop =>








    +            if rx.tick = '1' then








    +               if rcv.n = 15 then








    +                  rcvin.s <= Ack;








    +               else








    +                  rcvin.n <= rcv.n + 1;








    +               end if;








    +            end if;








    +








    +         when Ack =>








    +            if wb_read(si) then








    +               rx.ack <= '1';








    +               rcvin.s <= Ack2;








    +            end if;








    +








    +         when Ack2 =>








    +            rx.ack <= '1';








    +            if si.stb = '0' then








    +               rcvin.s <= Idle;








    +            end if;








    +      end case;








    +   end process;








    +








    +   so.dat <= x"0000" & rx.ack & "0000000" & rcv.d;








    +   so.ack <= rx.ack;








    +








    +   -----------------------------------------------------------------------------








    +   -- Registers                                                               --








    +   -----------------------------------------------------------------------------








    +   reg : process(si.clk)








    +   begin








    +      if rising_edge(si.clk) then








    +         rcv <= rcvin;








    +         if si.rst = '1' then








    +            rcv.s <= Idle;








    +         end if;








    +      end if;








    +   end process;








    +end rtl;








    \ No newline at end of file








    Index: layer2/trunk/vhdl/rs232/rtl








    ===================================================================








    --- layer2/trunk/vhdl/rs232/rtl	(nonexistent)








    +++ layer2/trunk/vhdl/rs232/rtl	(revision 2)
















    
    layer2/trunk/vhdl/rs232/rtl














    Property changes :



    Added: bugtraq:number








    ## -0,0 +1 ##








    +true








    \ No newline at end of property








    Index: layer2/trunk/vhdl/rs232








    ===================================================================








    --- layer2/trunk/vhdl/rs232	(nonexistent)








    +++ layer2/trunk/vhdl/rs232	(revision 2)
















    
    layer2/trunk/vhdl/rs232














    Property changes :



    Added: bugtraq:number








    ## -0,0 +1 ##








    +true








    \ No newline at end of property








    Index: layer2/trunk/vhdl/pit/rtl/ipit.vhd








    ===================================================================








    --- layer2/trunk/vhdl/pit/rtl/ipit.vhd	(nonexistent)








    +++ layer2/trunk/vhdl/pit/rtl/ipit.vhd	(revision 2)








    @@ -0,0 +1,50 @@








    +--------------------------------------------------------------------------------








    +-- Programmable Interval Timer                                                --








    +--------------------------------------------------------------------------------








    +-- Simplest implementation of a programmable interval timer. The timer is     --








    +-- Wishbone compliant and functions on two instructions:                      --








    +--                                                                            --








    +--  o Start the timer with a Wb write. The data to be sent contains the       --








    +--    inverall length.                                                        --








    +--                                                                            --








    +--  o After the set limit is reached, the timer issues an interrupt and waits --








    +--    for a WB write. It returns back to initial state afterwards and waits   --








    +--    for a new WB write.                                                     --








    +--                                                                            --








    +-- The timer supports pulse timing only.                                      --








    +--                                                                            --








    +--------------------------------------------------------------------------------








    +-- Copyright (C)2011  Mathias H�rtnagl          --








    +--                                                                            --








    +-- This program is free software: you can redistribute it and/or modify       --








    +-- it under the terms of the GNU General Public License as published by       --








    +-- the Free Software Foundation, either version 3 of the License, or          --








    +-- (at your option) any later version.                                        --








    +--                                                                            --








    +-- This program is distributed in the hope that it will be useful,            --








    +-- but WITHOUT ANY WARRANTY; without even the implied warranty of             --








    +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the              --








    +-- GNU General Public License for more details.                               --








    +--                                                                            --








    +-- You should have received a copy of the GNU General Public License          --








    +-- along with this program.  If not, see .      --








    +--------------------------------------------------------------------------------








    +library ieee;








    +use ieee.std_logic_1164.all;








    +use ieee.numeric_std.all;








    +








    +library work;








    +use work.iwb.all;








    +








    +package ipit is








    +








    +   component pit is








    +      port(








    +         si   : in  slave_in_t;








    +         so   : out slave_out_t;








    +      -- Non-Wishbone Signals








    +         intr : out std_logic








    +      );








    +   end component;








    +








    +end ipit;








    \ No newline at end of file








    Index: layer2/trunk/vhdl/pit/rtl/pit.vhd








    ===================================================================








    --- layer2/trunk/vhdl/pit/rtl/pit.vhd	(nonexistent)








    +++ layer2/trunk/vhdl/pit/rtl/pit.vhd	(revision 2)








    @@ -0,0 +1,110 @@








    +--------------------------------------------------------------------------------








    +-- Programmable Interval Timer                                                --








    +--------------------------------------------------------------------------------








    +-- Copyright (C)2011  Mathias H�rtnagl          --








    +--                                                                            --








    +-- This program is free software: you can redistribute it and/or modify       --








    +-- it under the terms of the GNU General Public License as published by       --








    +-- the Free Software Foundation, either version 3 of the License, or          --








    +-- (at your option) any later version.                                        --








    +--                                                                            --








    +-- This program is distributed in the hope that it will be useful,            --








    +-- but WITHOUT ANY WARRANTY; without even the implied warranty of             --








    +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the              --








    +-- GNU General Public License for more details.                               --








    +--                                                                            --








    +-- You should have received a copy of the GNU General Public License          --








    +-- along with this program.  If not, see .      --








    +--------------------------------------------------------------------------------








    +library ieee;








    +use ieee.std_logic_1164.all;








    +use ieee.numeric_std.all;








    +








    +








    +library work;








    +use work.iwb.all;








    +








    +entity pit is








    +   port(








    +      si   : in  slave_in_t;








    +      so   : out slave_out_t;








    +   -- Non-Wishbone Signals








    +      intr : out std_logic








    +   );








    +end pit;








    +








    +architecture rtl of pit is








    +








    +   type state_t is (Idle, Count, Ack, Ack2);








    +   signal s, sin : state_t;








    +








    +   signal n, nin : unsigned(31 downto 0);    -- Counter.








    +   signal l, lin : unsigned(31 downto 0);    -- Count limit set by the user.








    +begin








    +








    +   -----------------------------------------------------------------------------








    +   -- PIT Control                                                             --








    +   -----------------------------------------------------------------------------








    +   nsl : process(s, l, n, si.stb, si.we, si.dat, si)








    +   begin








    +








    +      sin  <= s;








    +      lin  <= l;








    +      nin  <= n;








    +








    +      intr <= '0';








    +








    +      case s is








    +








    +         -- Wait for a WB write operation to trigger a new timer loop. The








    +         -- timer starts at 1 to count in the Idle state cycle.








    +         when Idle =>








    +            if wb_write(si) then








    +               nin <= x"00000000";








    +               lin <= unsigned(si.dat);








    +               sin <= Count;








    +            end if;








    +








    +         when Count =>








    +            if n = l then








    +               sin <= Ack;








    +            else








    +               nin <= n + 1;








    +            end if;








    +








    +         -- Set interrupt signal and wait for a WB write operation to reset.








    +         when Ack =>








    +            intr <= '1';








    +            if wb_read(si) then








    +               sin <= Ack2;








    +            end if;








    +








    +         when Ack2 =>








    +            intr <= '1';








    +            if si.stb = '0' then








    +               sin <= Idle;








    +            end if;








    +








    +      end case;








    +   end process;








    +








    +   -- Reading while still counting returns the progress.








    +   so.dat <= std_logic_vector(n);








    +   so.ack <= si.stb;








    +








    +   -----------------------------------------------------------------------------








    +   -- Registers                                                               --








    +   -----------------------------------------------------------------------------








    +   reg : process(si.clk)








    +   begin








    +      if rising_edge(si.clk) then








    +         s <= sin;








    +         n <= nin;








    +         l <= lin;








    +








    +         if si.rst = '1' then








    +            s <= Idle;








    +         end if;








    +      end if;








    +   end process;








    +end rtl;








    \ No newline at end of file








    Index: layer2/trunk/vhdl/pit/rtl








    ===================================================================








    --- layer2/trunk/vhdl/pit/rtl	(nonexistent)








    +++ layer2/trunk/vhdl/pit/rtl	(revision 2)
















    
    layer2/trunk/vhdl/pit/rtl














    Property changes :



    Added: bugtraq:number








    ## -0,0 +1 ##








    +true








    \ No newline at end of property








    Index: layer2/trunk/vhdl/pit








    ===================================================================








    --- layer2/trunk/vhdl/pit	(nonexistent)








    +++ layer2/trunk/vhdl/pit	(revision 2)
















    
    layer2/trunk/vhdl/pit














    Property changes :



    Added: bugtraq:number








    ## -0,0 +1 ##








    +true








    \ No newline at end of property








    Index: layer2/trunk/vhdl/flash/rtl/iflash.vhd








    ===================================================================








    --- layer2/trunk/vhdl/flash/rtl/iflash.vhd	(nonexistent)








    +++ layer2/trunk/vhdl/flash/rtl/iflash.vhd	(revision 2)








    @@ -0,0 +1,58 @@








    +--------------------------------------------------------------------------------








    +-- Numonyx� 128 Mbit EMBEDDED FLASH MEMORY J3 Version D                       --








    +--------------------------------------------------------------------------------








    +-- See  and  for information on usage and bus interface.    --








    +--                                                                            --








    +-- REFERENCES                                                                 --








    +--                                                                            --








    +--  [1] Numonyx� Embedded Flash Memory(J3 v. D) Datasheet Revision 5          --








    +--  [2] Mihai Plesa - StrataFlash memory operations on a Spartan-3E           --








    +--                                                --








    +--                                                                            --








    +--------------------------------------------------------------------------------








    +-- Copyright (C)2011  Mathias H�rtnagl          --








    +--                                                                            --








    +-- This program is free software: you can redistribute it and/or modify       --








    +-- it under the terms of the GNU General Public License as published by       --








    +-- the Free Software Foundation, either version 3 of the License, or          --








    +-- (at your option) any later version.                                        --








    +--                                                                            --








    +-- This program is distributed in the hope that it will be useful,            --








    +-- but WITHOUT ANY WARRANTY; without even the implied warranty of             --








    +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the              --








    +-- GNU General Public License for more details.                               --








    +--                                                                            --








    +-- You should have received a copy of the GNU General Public License          --








    +-- along with this program.  If not, see .      --








    +--------------------------------------------------------------------------------








    +library ieee;








    +use ieee.std_logic_1164.all;








    +use ieee.numeric_std.all;








    +








    +library work;








    +use work.iwb.all;








    +








    +package iflash is








    +








    +   component flash








    +      port(








    +         si           : in    slave_in_t;








    +         so           : out   slave_out_t;








    +      -- Non Wishbone Signals








    +         SF_OE        : out   std_logic;








    +         SF_CE        : out   std_logic;








    +         SF_WE        : out   std_logic;








    +         SF_BYTE      : out   std_logic;








    +         --SF_STS       : in    std_logic;








    +         SF_A         : out   std_logic_vector(23 downto 0);








    +         SF_D         : inout std_logic_vector(7 downto 0);








    +         PF_OE        : out   std_logic;








    +         LCD_RW       : out   std_logic;








    +         LCD_E        : out   std_logic;








    +         SPI_ROM_CS   : out   std_logic;








    +         SPI_ADC_CONV : out   std_logic;








    +         SPI_DAC_CS   : out   std_logic








    +      );








    +   end component;








    +








    +end iflash;








    \ No newline at end of file








    Index: layer2/trunk/vhdl/flash/rtl/flash.vhd








    ===================================================================








    --- layer2/trunk/vhdl/flash/rtl/flash.vhd	(nonexistent)








    +++ layer2/trunk/vhdl/flash/rtl/flash.vhd	(revision 2)








    @@ -0,0 +1,208 @@








    +--------------------------------------------------------------------------------








    +-- Numonyx� 128 Mbit EMBEDDED FLASH MEMORY J3 Version D                       --








    +--------------------------------------------------------------------------------








    +-- Copyright (C)2011  Mathias H�rtnagl          --








    +--                                                                            --








    +-- This program is free software: you can redistribute it and/or modify       --








    +-- it under the terms of the GNU General Public License as published by       --








    +-- the Free Software Foundation, either version 3 of the License, or          --








    +-- (at your option) any later version.                                        --








    +--                                                                            --








    +-- This program is distributed in the hope that it will be useful,            --








    +-- but WITHOUT ANY WARRANTY; without even the implied warranty of             --








    +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the              --








    +-- GNU General Public License for more details.                               --








    +--                                                                            --








    +-- You should have received a copy of the GNU General Public License          --








    +-- along with this program.  If not, see .      --








    +--------------------------------------------------------------------------------








    +library ieee;








    +use ieee.std_logic_1164.all;








    +use ieee.numeric_std.all;








    +








    +library work;








    +use work.iwb.all;








    +








    +entity flash is








    +   port (








    +      si           : in    slave_in_t;








    +      so           : out   slave_out_t;








    +   -- Non Wishbone Signals








    +      SF_OE        : out   std_logic;








    +      SF_CE        : out   std_logic;








    +      SF_WE        : out   std_logic;








    +      SF_BYTE      : out   std_logic;








    +      --SF_STS       : in    std_logic;








    +      SF_A         : out   std_logic_vector(23 downto 0);








    +      SF_D         : inout std_logic_vector(7 downto 0);








    +      PF_OE        : out   std_logic;








    +      LCD_RW       : out   std_logic;








    +      LCD_E        : out   std_logic;








    +      SPI_ROM_CS   : out   std_logic;








    +      SPI_ADC_CONV : out   std_logic;








    +      SPI_DAC_CS   : out   std_logic








    +   );








    +end flash;








    +








    +architecture rtl of flash is








    +








    +   type state_t is (Init, Idle, SetupRead, DataRead, WaitRead, DataWrite,








    +                    Finish);








    +








    +   type reg_t is record








    +      s : state_t;                           -- State.








    +      n : natural range 0 to 49;             -- Period counter.








    +      a : natural range 0 to 3;              -- Address incrementer for read.








    +      d : std_logic_vector(31 downto 0);     -- Latched data for read.








    +      --w : std_logic_vector(7 downto 0);      -- Latched data for write.








    +   end record;








    +








    +   signal r, rin : reg_t;








    +begin








    +








    +   -- Disable shared components.








    +   PF_OE        <= '0';








    +   LCD_RW       <= '0';








    +   LCD_E        <= '0';








    +   SPI_ROM_CS   <= '1';








    +   SPI_ADC_CONV <= '0';








    +   SPI_DAC_CS   <= '1';








    +








    +   -----------------------------------------------------------------------------








    +   -- Read/Write Control                                                      --








    +   -----------------------------------------------------------------------------








    +   SF_A <= si.adr(23 downto 2) & std_logic_vector( to_unsigned(r.a, 2) );








    +








    +   nsl : process(si, r, SF_D)








    +   begin








    +








    +      rin <= r;








    +








    +      SF_OE   <= '1';








    +      SF_CE   <= '1';








    +      SF_WE   <= '1';








    +      SF_BYTE <= '0';








    +      SF_D    <= (others => 'Z');








    +








    +      so.ack <= '0';








    +








    +      case r.s is








    +








    +         -- Wait 1�s for the device to be ready at startup.








    +         -- [Datasheet timing: R12, R13]








    +         when Init =>








    +            if r.n = 49 then -- 1�s








    +               rin.n <= 0;








    +               rin.s <= Idle;








    +            else








    +               rin.n <= r.n + 1;








    +            end if;








    +








    +         -- Wait for incomming read or write commands.








    +         when Idle =>








    +            if wb_read(si) then








    +               rin.a <= 0;








    +               rin.s <= SetupRead;








    +            elsif wb_write(si) then








    +               rin.a <= to_integer( unsigned(si.adr(1 downto 0)) );








    +               -- case si.sel is








    +                  -- when "0001" => rin.w <= si.dat(7 downto 0);








    +                  -- when "0010" => rin.w <= si.dat(15 downto 8);








    +                  -- when "0100" => rin.w <= si.dat(23 downto 16);








    +                  -- when "1000" => rin.w <= si.dat(31 downto 24);








    +                  -- when others => rin.w <= si.dat(7 downto 0);








    +               -- end case;








    +               rin.s <= DataWrite;








    +            end if;








    +








    +         -- Set CE and OE low while waiting 80ns (75ns) for the first data byte








    +         -- ready to latch. [Datasheet timing: R2, R3]








    +         when SetupRead =>








    +            SF_CE <= '0';








    +            SF_OE <= '0';








    +            if r.n = 3 then -- 80ns








    +               rin.n <= 0;








    +               rin.s <= DataRead;








    +            else








    +               rin.n <= r.n + 1;








    +            end if;








    +








    +         -- Latch data word four times and increment SF_A[1:0]. After every








    +         -- read, jump to WaitRead and wait for the next data byte. On the








    +         -- last read go to FinishRead.








    +         when DataRead =>








    +            SF_CE <= '0';








    +            SF_OE <= '0';








    +            rin.d <= r.d(23 downto 0) & SF_D;








    +            if r.a = 3 then








    +               rin.a <= 0;








    +               rin.s <= Finish;








    +            else








    +               rin.a <= r.a + 1;








    +               rin.s <= WaitRead;








    +            end if;








    +








    +         -- Wait for 40ns (25ns) until the next data byte is ready.








    +         -- [Datasheet timing: R15]








    +         when WaitRead =>








    +            SF_CE <= '0';








    +            SF_OE <= '0';








    +            if r.n = 1 then -- 40ns








    +               rin.n <= 0;








    +               rin.s <= DataRead;








    +            else








    +               rin.n <= r.n + 1;








    +            end if;








    +








    +         -- Pull down CE and WE. Wait for 60ns (60ns).








    +         when DataWrite =>








    +            SF_CE <= '0';








    +            SF_WE <= '0';








    +            --SF_D  <= r.w;








    +            case si.sel is








    +               when "0001" => SF_D <= si.dat(7 downto 0);








    +               when "0010" => SF_D <= si.dat(15 downto 8);








    +               when "0100" => SF_D <= si.dat(23 downto 16);








    +               when "1000" => SF_D <= si.dat(31 downto 24);








    +               when others => SF_D <= si.dat(7 downto 0);








    +            end case;








    +            if r.n = 2 then -- 60ns








    +               rin.n <= 0;








    +               rin.s <= Finish;








    +            else








    +               rin.n <= r.n + 1;








    +            end if;








    +








    +         -- Set CE and OE high and wait 20ns (25ns). After that the next command








    +         -- can be processed. The remaining 5ns are compensated by the Idle








    +         -- state which takes another 20ns. Wait for si.stb to be low again as








    +         -- well. [Datasheet timing: R8]








    +         -- Write recovery before read is 40ns (35ns). Wait at least 20ns and








    +         -- then go to Idle state which waits for another 20ns.








    +         -- [Datasheet timing: W12]








    +         when Finish =>








    +            so.ack <= '1';








    +            if si.stb = '0' then








    +               rin.s <= Idle;








    +            end if;








    +








    +      end case;








    +   end process;








    +








    +   so.dat <= r.d;








    +








    +   -----------------------------------------------------------------------------








    +   -- Registers                                                               --








    +   -----------------------------------------------------------------------------








    +   reg : process(si.clk)








    +   begin








    +      if rising_edge(si.clk) then








    +         r <= rin;








    +








    +         if si.rst = '1' then








    +            r.s <= Init;








    +         end if;








    +      end if;








    +   end process;








    +end rtl;








    +








    Index: layer2/trunk/vhdl/flash/rtl








    ===================================================================








    --- layer2/trunk/vhdl/flash/rtl	(nonexistent)








    +++ layer2/trunk/vhdl/flash/rtl	(revision 2)
















    
    layer2/trunk/vhdl/flash/rtl














    Property changes :



    Added: bugtraq:number








    ## -0,0 +1 ##








    +true








    \ No newline at end of property








    Index: layer2/trunk/vhdl/flash








    ===================================================================








    --- layer2/trunk/vhdl/flash	(nonexistent)








    +++ layer2/trunk/vhdl/flash	(revision 2)
















    
    layer2/trunk/vhdl/flash














    Property changes :



    Added: bugtraq:number








    ## -0,0 +1 ##








    +true








    \ No newline at end of property








    Index: layer2/trunk/vhdl/vga/bench/vga_constr.ucf








    ===================================================================








    --- layer2/trunk/vhdl/vga/bench/vga_constr.ucf	(nonexistent)








    +++ layer2/trunk/vhdl/vga/bench/vga_constr.ucf	(revision 2)








    @@ -0,0 +1,10 @@








    +# Primary clock








    +NET "CLK" LOC = "C9" |IOSTANDARD = LVCMOS33 |TNM_NET = TNM_clk ;








    +TIMESPEC TS_clk = PERIOD "TNM_clk" 20 ns HIGH 50% ;








    +








    +# VGA Connections








    +NET "VGA_RED"   LOC = "H14" |IOSTANDARD = LVTTL |DRIVE = 8 |SLEW = FAST ;








    +NET "VGA_GREEN" LOC = "H15" |IOSTANDARD = LVTTL |DRIVE = 8 |SLEW = FAST ;








    +NET "VGA_BLUE"  LOC = "G15" |IOSTANDARD = LVTTL |DRIVE = 8 |SLEW = FAST ;








    +NET "VGA_HSYNC" LOC = "F15" |IOSTANDARD = LVTTL |DRIVE = 8 |SLEW = FAST ;








    +NET "VGA_VSYNC" LOC = "F14" |IOSTANDARD = LVTTL |DRIVE = 8 |SLEW = FAST ;








    Index: layer2/trunk/vhdl/vga/bench/tb_vga.vhd








    ===================================================================








    --- layer2/trunk/vhdl/vga/bench/tb_vga.vhd	(nonexistent)








    +++ layer2/trunk/vhdl/vga/bench/tb_vga.vhd	(revision 2)








    @@ -0,0 +1,81 @@








    +--------------------------------------------------------------------------------








    +--                                                                            --








    +--------------------------------------------------------------------------------








    +-- Version:  1.0                                                              --








    +-- Device:   Spartan 3E                                                       --








    +--                                                                            --








    +-- DESCRIPTION                                                                --








    +--                                                                            --








    +--                                                                            --








    +--------------------------------------------------------------------------------








    +-- Copyright (C)2011  Mathias H�rtnagl          --








    +--                                                                            --








    +-- This program is free software: you can redistribute it and/or modify       --








    +-- it under the terms of the GNU General Public License as published by       --








    +-- the Free Software Foundation, either version 3 of the License, or          --








    +-- (at your option) any later version.                                        --








    +--                                                                            --








    +-- This program is distributed in the hope that it will be useful,            --








    +-- but WITHOUT ANY WARRANTY; without even the implied warranty of             --








    +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the              --








    +-- GNU General Public License for more details.                               --








    +--                                                                            --








    +-- You should have received a copy of the GNU General Public License          --








    +-- along with this program.  If not, see .      --








    +--------------------------------------------------------------------------------








    +library ieee;








    +use ieee.std_logic_1164.all;








    +use ieee.numeric_std.all;








    +








    +library work;








    +use work.iwb.all;








    +use work.ivga.all;








    +








    +entity tb_vga is








    +   port(








    +      CLK       : in  std_logic;








    +      VGA_HSYNC : out std_logic;








    +      VGA_VSYNC : out std_logic;








    +      VGA_RED   : out std_logic;








    +      VGA_GREEN : out std_logic;








    +      VGA_BLUE  : out std_logic








    +   );








    +end tb_vga;








    +








    +architecture tb of tb_vga is








    +








    +   component global_clock








    +      port(








    +         clkin_in        : in std_logic;








    +         rst_in          : in std_logic;








    +         clkdv_out       : out std_logic;








    +         clkin_ibufg_out : out std_logic;








    +         clk0_out        : out std_logic








    +         );








    +   end component;








    +








    +   signal si : slave_in_t;








    +   signal so : slave_out_t;








    +begin








    +








    +   inst_clock: global_clock








    +      port map(








    +         clkin_in => CLK,








    +         rst_in => '0',








    +         clkdv_out => open, --si.clk,








    +         clkin_ibufg_out => open,








    +         clk0_out => si.clk--open








    +      );








    +








    +   disp : vga








    +   port map(








    +      si        => si,








    +      so        => so,








    +   -- Non Wishbone Signals








    +      VGA_HSYNC => VGA_HSYNC,








    +      VGA_VSYNC => VGA_VSYNC,








    +      VGA_RED   => VGA_RED,








    +      VGA_GREEN => VGA_GREEN,








    +      VGA_BLUE  => VGA_BLUE








    +   );








    +end tb;








    \ No newline at end of file








    Index: layer2/trunk/vhdl/vga/bench/global_clock.vhd








    ===================================================================








    --- layer2/trunk/vhdl/vga/bench/global_clock.vhd	(nonexistent)








    +++ layer2/trunk/vhdl/vga/bench/global_clock.vhd	(revision 2)








    @@ -0,0 +1,95 @@








    +--------------------------------------------------------------------------------








    +-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.








    +--------------------------------------------------------------------------------








    +--   ____  ____








    +--  /   /\/   /








    +-- /___/  \  /    Vendor: Xilinx








    +-- \   \   \/     Version : 12.2








    +--  \   \         Application : xaw2vhdl








    +--  /   /         Filename : global_clock.vhd








    +-- /___/   /\     Timestamp : 08/31/2010 15:23:33








    +-- \   \  /  \








    +--  \___\/\___\








    +--








    +--Command: xaw2vhdl-intstyle D:/IO One/vga/vga/ipcore_dir/global_clock.xaw -st global_clock.vhd








    +--Design Name: global_clock








    +--Device: xc3s500e-5fg320








    +--








    +-- Module global_clock








    +-- Generated by Xilinx Architecture Wizard








    +-- Written for synthesis tool: XST








    +








    +library ieee;








    +use ieee.std_logic_1164.ALL;








    +use ieee.numeric_std.ALL;








    +library UNISIM;








    +use UNISIM.Vcomponents.ALL;








    +








    +entity global_clock is








    +   port ( CLKIN_IN        : in    std_logic;








    +          RST_IN          : in    std_logic;








    +          CLKDV_OUT       : out   std_logic;








    +          CLKIN_IBUFG_OUT : out   std_logic;








    +          CLK0_OUT        : out   std_logic);








    +end global_clock;








    +








    +architecture BEHAVIORAL of global_clock is








    +   signal CLKDV_BUF       : std_logic;








    +   signal CLKFB_IN        : std_logic;








    +   signal CLKIN_IBUFG     : std_logic;








    +   signal CLK0_BUF        : std_logic;








    +   signal GND_BIT         : std_logic;








    +begin








    +   GND_BIT <= '0';








    +   CLKIN_IBUFG_OUT <= CLKIN_IBUFG;








    +   CLK0_OUT <= CLKFB_IN;








    +   CLKDV_BUFG_INST : BUFG








    +      port map (I=>CLKDV_BUF,








    +                O=>CLKDV_OUT);








    +








    +   CLKIN_IBUFG_INST : IBUFG








    +      port map (I=>CLKIN_IN,








    +                O=>CLKIN_IBUFG);








    +








    +   CLK0_BUFG_INST : BUFG








    +      port map (I=>CLK0_BUF,








    +                O=>CLKFB_IN);








    +








    +   DCM_SP_INST : DCM_SP








    +   generic map( CLK_FEEDBACK => "1X",








    +            CLKDV_DIVIDE => 2.0,








    +            CLKFX_DIVIDE => 1,








    +            CLKFX_MULTIPLY => 4,








    +            CLKIN_DIVIDE_BY_2 => FALSE,








    +            CLKIN_PERIOD => 20.000,








    +            CLKOUT_PHASE_SHIFT => "NONE",








    +            DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",








    +            DFS_FREQUENCY_MODE => "LOW",








    +            DLL_FREQUENCY_MODE => "LOW",








    +            DUTY_CYCLE_CORRECTION => TRUE,








    +            FACTORY_JF => x"C080",








    +            PHASE_SHIFT => 0,








    +            STARTUP_WAIT => FALSE)








    +      port map (CLKFB=>CLKFB_IN,








    +                CLKIN=>CLKIN_IBUFG,








    +                DSSEN=>GND_BIT,








    +                PSCLK=>GND_BIT,








    +                PSEN=>GND_BIT,








    +                PSINCDEC=>GND_BIT,








    +                RST=>RST_IN,








    +                CLKDV=>CLKDV_BUF,








    +                CLKFX=>open,








    +                CLKFX180=>open,








    +                CLK0=>CLK0_BUF,








    +                CLK2X=>open,








    +                CLK2X180=>open,








    +                CLK90=>open,








    +                CLK180=>open,








    +                CLK270=>open,








    +                LOCKED=>open,








    +                PSDONE=>open,








    +                STATUS=>open);








    +








    +end BEHAVIORAL;








    +








    +








    Index: layer2/trunk/vhdl/vga/bench








    ===================================================================








    --- layer2/trunk/vhdl/vga/bench	(nonexistent)








    +++ layer2/trunk/vhdl/vga/bench	(revision 2)
















    
    layer2/trunk/vhdl/vga/bench














    Property changes :



    Added: bugtraq:number








    ## -0,0 +1 ##








    +true








    \ No newline at end of property








    Index: layer2/trunk/vhdl/vga/rtl/ram.vhd








    ===================================================================








    --- layer2/trunk/vhdl/vga/rtl/ram.vhd	(nonexistent)








    +++ layer2/trunk/vhdl/vga/rtl/ram.vhd	(revision 2)








    @@ -0,0 +1,74 @@








    +--------------------------------------------------------------------------------








    +-- 8-Color 100x37 Textmode Video Controller                                   --








    +--------------------------------------------------------------------------------








    +-- Copyright (C)2011  Mathias H�rtnagl          --








    +--                                                                            --








    +-- This program is free software: you can redistribute it and/or modify       --








    +-- it under the terms of the GNU General Public License as published by       --








    +-- the Free Software Foundation, either version 3 of the License, or          --








    +-- (at your option) any later version.                                        --








    +--                                                                            --








    +-- This program is distributed in the hope that it will be useful,            --








    +-- but WITHOUT ANY WARRANTY; without even the implied warranty of             --








    +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the              --








    +-- GNU General Public License for more details.                               --








    +--                                                                            --








    +-- You should have received a copy of the GNU General Public License          --








    +-- along with this program.  If not, see .      --








    +--------------------------------------------------------------------------------








    +library ieee;








    +use ieee.std_logic_1164.all;








    +use ieee.numeric_std.all;








    +








    +entity ram is








    +   port(








    +      clk  : in  std_logic;








    +      adrs : in  std_logic_vector(11 downto 0);








    +      adru : in  std_logic_vector(11 downto 0);








    +      we   : in  std_logic;








    +      stb  : in  std_logic;








    +      din  : in  std_logic_vector(15 downto 0);








    +      chr  : out std_logic_vector(7 downto 0);








    +      fgc  : out std_logic_vector(2 downto 0);








    +      bgc  : out std_logic_vector(2 downto 0);








    +      datu : out std_logic_vector(15 downto 0);








    +      ack  : out std_logic








    +   );








    +end ram;








    +








    +architecture rtl of ram is








    +








    +   -- Two bits are obsolete, since character color is 6 bit information only.








    +   -- However, this will not reduce the number of block rams, so we stick to








    +   -- 8 bit color. The remaining 396 halfwords, can be used for something else.








    +   type mem_t is array (0 to 4095) of std_logic_vector(15 downto 0);








    +








    +   signal mem : mem_t := ( others => (others => '0') );








    +








    +   attribute RAM_STYLE : string;








    +   attribute RAM_STYLE of mem: signal is "BLOCK";








    +








    +   signal dat  : std_logic_vector(15 downto 0);








    +   signal acki : std_logic;








    +begin








    +








    +   reg : process(clk)








    +   begin








    +      if rising_edge(clk) then








    +         acki <= '0';








    +         if (stb = '1') and (we = '1') then








    +            mem( to_integer(unsigned(adru)) ) <= din;








    +            acki <= '1';








    +         elsif (stb = '1') and (we = '0') then








    +            acki <= '1';








    +         end if;








    +         dat  <= mem( to_integer(unsigned(adrs)) );








    +         datu <= mem( to_integer(unsigned(adru)) );








    +      end if;








    +   end process;








    +








    +   fgc <= dat(14 downto 12);








    +   bgc <= dat(10 downto 8);








    +   chr <= dat(7 downto 0);








    +   ack <= acki;








    +end rtl;








    \ No newline at end of file








    Index: layer2/trunk/vhdl/vga/rtl/ivga.vhd








    ===================================================================








    --- layer2/trunk/vhdl/vga/rtl/ivga.vhd	(nonexistent)








    +++ layer2/trunk/vhdl/vga/rtl/ivga.vhd	(revision 2)








    @@ -0,0 +1,71 @@








    +--------------------------------------------------------------------------------








    +-- 8-Color 100x37 Textmode Video Controller                                   --








    +--------------------------------------------------------------------------------








    +-- This controller features a 800x600@72Hz resolution Textmode VGA  with 100  --








    +-- characters per line and 37 lines. One out of 8 different colors can be     --








    +-- assigned to every single character and the character's background          --








    +-- respectivly.                                                               --








    +-- You can replace the character set with your own with . It takes  --








    +-- a <*.bdf> file and translates the character map into a            --








    +-- (Replaces the original!).                                                  --








    +--                                                                            --








    +-- For information about colors and usage consult  and .    --








    +--                                                                            --








    +-- REFERENCES                                                                 --








    +--                                                                            --








    +--  [1] VGA Display Adapter                                                   --








    +--                        --








    +--      Copyright 2007 by Javier Valcarce Garc�a                              --








    +--  [2] BDF Console Font File                                                 --








    +--                               --








    +--  [3] Z80 System On A Chip                                                  --








    +--                           --








    +--  [4] Yet Another VGA                                                       --








    +--                            --








    +--  [5] Xilinx Spartan 3E Starter Kit Board User Guide                        --








    +--                                 --








    +--  [6] Display resolution calculator                                         --








    +--                            --








    +--                                                                            --








    +--  [7] Chu Pong P., FPGA Prototyping By VHDL Examples,                       --








    +--      John Wiley & Sons Inc., Hoboken, New Jersy, 2008,                     --








    +--      ISBN: 978-0470185315                                                  --








    +--                                                                            --








    +--------------------------------------------------------------------------------








    +-- Copyright (C)2011  Mathias H�rtnagl          --








    +--                                                                            --








    +-- This program is free software: you can redistribute it and/or modify       --








    +-- it under the terms of the GNU General Public License as published by       --








    +-- the Free Software Foundation, either version 3 of the License, or          --








    +-- (at your option) any later version.                                        --








    +--                                                                            --








    +-- This program is distributed in the hope that it will be useful,            --








    +-- but WITHOUT ANY WARRANTY; without even the implied warranty of             --








    +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the              --








    +-- GNU General Public License for more details.                               --








    +--                                                                            --








    +-- You should have received a copy of the GNU General Public License          --








    +-- along with this program.  If not, see .      --








    +--------------------------------------------------------------------------------








    +library ieee;








    +use ieee.std_logic_1164.all;








    +use ieee.numeric_std.all;








    +








    +library work;








    +use work.iwb.all;








    +








    +package ivga is








    +








    +   component vga is








    +      port(








    +         si        : in  slave_in_t;








    +         so        : out slave_out_t;








    +         VGA_RED   : out std_logic;








    +         VGA_GREEN : out std_logic;








    +         VGA_BLUE  : out std_logic;








    +         VGA_HSYNC : out std_logic;








    +         VGA_VSYNC : out std_logic








    +      );








    +   end component;








    +end ivga;








    \ No newline at end of file








    Index: layer2/trunk/vhdl/vga/rtl/vga.vhd








    ===================================================================








    --- layer2/trunk/vhdl/vga/rtl/vga.vhd	(nonexistent)








    +++ layer2/trunk/vhdl/vga/rtl/vga.vhd	(revision 2)








    @@ -0,0 +1,257 @@








    +--------------------------------------------------------------------------------








    +-- 8-Color 100x37 Textmode Video Controller                                   --








    +--------------------------------------------------------------------------------








    +--                                                                            --








    +-- IMPORTANT NOTICE                                                           --








    +--                                                                            --








    +--    I've spent alot of time to get the controller to work correctly. For    --








    +--    all those who try to implement their own: be strict with the sync       --








    +--    timing and don't paint outside the display area. To avoid a blurry      --








    +--    image, paint all 100px per line. I've painted only 99px and some        --








    +--    characters startet blinking on the edges. This happend because I didn't --








    +--    latch the sync and visible signals to synchronize them with the         --








    +--    character output (2 additional cycles). Another reason, why a character --








    +--    binks is due to the fact that the color needs to latched one cycle as   --








    +--    well.                                                                   --








    +--    If you want to save registers however, you can set the display boundary --








    +--    comparators to '<= H_DISP' and '<= V_DISP'. The display then has        --








    +--    801x601px but you can delete the 'hsync', 'vsync' and 'vis' shift regs. --








    +--    Hard to explain. If you get problems just contact me :)                 --








    +--                                                                            --








    +--------------------------------------------------------------------------------








    +-- Copyright (C)2011  Mathias H�rtnagl          --








    +--                                                                            --








    +-- This program is free software: you can redistribute it and/or modify       --








    +-- it under the terms of the GNU General Public License as published by       --








    +-- the Free Software Foundation, either version 3 of the License, or          --








    +-- (at your option) any later version.                                        --








    +--                                                                            --








    +-- This program is distributed in the hope that it will be useful,            --








    +-- but WITHOUT ANY WARRANTY; without even the implied warranty of             --








    +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the              --








    +-- GNU General Public License for more details.                               --








    +--                                                                            --








    +-- You should have received a copy of the GNU General Public License          --








    +-- along with this program.  If not, see .      --








    +--------------------------------------------------------------------------------








    +library ieee;








    +use ieee.std_logic_1164.all;








    +use ieee.numeric_std.all;








    +








    +library work;








    +use work.iwb.all;








    +








    +entity vga is








    +   port(








    +      si        : in  slave_in_t;








    +      so        : out slave_out_t;








    +   -- Non Wishbone Signals








    +      VGA_HSYNC : out std_logic;








    +      VGA_VSYNC : out std_logic;








    +      VGA_RED   : out std_logic;








    +      VGA_GREEN : out std_logic;








    +      VGA_BLUE  : out std_logic








    +   );








    +end vga;








    +








    +architecture rtl of vga is








    +








    +   -----------------------------------------------------------------------------








    +   -- Display settingss for 800x600@72Hz.                                     --








    +   -----------------------------------------------------------------------------








    +   constant H_MAX       : natural := 1040;   -- Complete horizontal width.








    +   constant H_DISP      : natural := 800;    -- Visible Display size.








    +   constant H_LOW_START : natural := 856;    -- H_DISP + front porch.








    +   constant H_LOW_END   : natural := 976;    -- H_LOW_START + sync low.








    +








    +   constant V_MAX       : natural := 666;








    +   constant V_DISP      : natural := 600;








    +   constant V_LOW_START : natural := 637;








    +   constant V_LOW_END   : natural := 643;








    +








    +








    +   component rom is








    +      port(








    +         clk      : in  std_logic;








    +         rom_addr : in  std_logic_vector(11 downto 0);








    +         rom_word : out std_logic_vector(7 downto 0)








    +      );








    +   end component;








    +








    +   attribute RAM_STYLE : string;








    +   attribute RAM_STYLE of rom : component is "BLOCK";








    +








    +   component ram is








    +      port(








    +         clk  : in  std_logic;








    +         adrs : in  std_logic_vector(11 downto 0);








    +         adru : in  std_logic_vector(11 downto 0);








    +         we   : in  std_logic;








    +         stb  : in  std_logic;








    +         din  : in  std_logic_vector(15 downto 0);








    +         chr  : out std_logic_vector(7 downto 0);








    +         fgc  : out std_logic_vector(2 downto 0);








    +         bgc  : out std_logic_vector(2 downto 0);








    +         datu : out std_logic_vector(15 downto 0);








    +         ack  : out std_logic








    +      );








    +   end component;








    +








    +   type video_t is record








    +      h     : unsigned(10 downto 0);








    +      v     : unsigned(9 downto 0);








    +      hsync : std_logic_vector(1 downto 0);








    +      vsync : std_logic_vector(1 downto 0);








    +      vis   : std_logic_vector(1 downto 0);








    +      fgc   : std_logic_vector(2 downto 0);








    +      bgc   : std_logic_vector(2 downto 0);








    +   end record;








    +








    +   signal vidin, vid : video_t;








    +








    +   signal adrs : unsigned(11 downto 0);             -- VGA display address.








    +   signal dat  : std_logic_vector(15 downto 0);     -- User write data.








    +   signal datu : std_logic_vector(15 downto 0);     -- User read data.








    +   signal chr  : std_logic_vector(7 downto 0);      -- Character ISO code.








    +   signal cbit : std_logic;                         -- One bit of 'chr'.








    +








    +   signal rom_addr : std_logic_vector(11 downto 0); -- Character lines address.








    +   signal rom_word : std_logic_vector(7 downto 0);    -- One line of a character.








    +








    +   signal red   : std_logic;








    +   signal green : std_logic;








    +   signal blue  : std_logic;








    +








    +   -- Split up into ram and rom addresses for convinience.








    +   alias ah : unsigned(7 downto 0) is vid.h(10 downto 3);








    +   alias av : unsigned(5 downto 0) is vid.v(9 downto 4);








    +   alias ch : unsigned(2 downto 0) is vid.h(2 downto 0);








    +   alias cv : unsigned(3 downto 0) is vid.v(3 downto 0);








    +begin








    +








    +   -----------------------------------------------------------------------------








    +   -- SYNCHRONIZATION                                                         --








    +   -----------------------------------------------------------------------------








    +   reg : process(si.clk)








    +   begin








    +      if rising_edge(si.clk) then








    +         vid <= vidin;








    +         if si.rst = '1' then








    +            vid.h <= "00000000000";








    +            vid.v <= "0000000000";








    +         end if;








    +      end if;








    +   end process;








    +








    +   nsl : process(vid.h, vid.v, vid.hsync, vid.vsync, vid.vis)








    +   begin








    +








    +      -- Horizontal counter.








    +      if vid.h = H_MAX-1 then








    +         vidin.h <= "00000000000";








    +      else








    +         vidin.h <= vid.h + 1;








    +      end if;








    +








    +      -- Vertical counter.








    +      if (vid.v = V_MAX-1) and (vid.h >= H_LOW_START) then








    +         vidin.v <= "0000000000";








    +      elsif vid.h = H_MAX-1 then








    +         vidin.v <= vid.v + 1;








    +      else








    +         vidin.v <= vid.v;








    +      end if;








    +








    +      -- The following 3 signals are implemented as shift registers. A character








    +      -- read takes 2 cycles. To set the sync and visible signals in time, we








    +      -- shift them once.








    +








    +      -- Horizontal sync pulse.








    +      vidin.hsync(1) <= vid.hsync(0);








    +      if (vid.h >= H_LOW_START) and (vid.h < H_LOW_END) then








    +         vidin.hsync(0) <= '0';








    +      else








    +         vidin.hsync(0) <= '1';








    +      end if;








    +








    +      -- Vertical sync pulse.








    +      vidin.vsync(1) <= vid.vsync(0);








    +      if (vid.v >= V_LOW_START) and (vid.v < V_LOW_END)  then








    +         vidin.vsync(0) <= '0';








    +      else








    +         vidin.vsync(0) <= '1';








    +      end if;








    +








    +      -- Visible area is limited vertically and horizontally limited by V_DISP








    +      -- and H_DISP respectively. Drawing outside results in strange display








    +      -- behaviour.








    +      vidin.vis(1) <= vid.vis(0);








    +      if (vid.h < H_DISP) and (vid.v < V_DISP) then








    +         vidin.vis(0) <= '1';








    +      else








    +         vidin.vis(0) <= '0';








    +      end if;








    +   end process;








    +








    +   -- Horizontal and vertical synchronization signals.








    +   VGA_HSYNC <= vid.hsync(1);








    +   VGA_VSYNC <= vid.vsync(1);








    +








    +   -----------------------------------------------------------------------------








    +   -- DATAPATH                                                                --








    +   -----------------------------------------------------------------------------








    +   -- Calculate array loaction of a character the short way: y*100 + x.








    +   adrs <= (av&"000000") + (av&"00000") + (av&"00") + (ah);








    +








    +   -- NOTE: Select either upper or lower halfword according to si.sel signal.








    +   -- Other signals then "1100" will store lower 16 bits!








    +   dat <= si.dat(31 downto 16) when si.sel = "1100" else si.dat(15 downto 0);








    +








    +   video_ram : ram port map(








    +      clk  => si.clk,








    +      adrs => std_logic_vector(adrs),








    +      adru => si.adr(12 downto 1),








    +      we   => si.we,








    +      stb  => si.stb,








    +      din  => dat,








    +      chr  => chr,








    +      fgc  => vidin.fgc,








    +      bgc  => vidin.bgc,








    +      datu => datu,








    +      ack  => so.ack








    +   );








    +








    +   -- Read vga memory.








    +   so.dat <= datu & x"0000" when si.sel = "1100" else x"0000" & datu;








    +








    +   -- The current pixel row of a char is determined by its ASCII (or ISO) number








    +   -- and the row offset y (a character is 16 rows high).








    +   rom_addr <= chr & std_logic_vector(cv);








    +








    +   char_table : rom port map(








    +      clk      => si.clk,








    +      rom_addr => rom_addr,








    +      rom_word => rom_word








    +   );








    +








    +   -- The Python script  creates the  automatically by








    +   -- translating a <*.bdf> file. The resulting characters in  are








    +   -- in reverese order and rotated 2 positions forward.








    +   -- The reversal is necessary, since the letters would be printed vertically








    +   -- inverted. Because of the delay due to the two memory stages (video ram,








    +   -- character rom), the x position pointer is 2 cycles ahead. By permanently








    +   -- rotating the character data 2px to the left, we do not need to subtract








    +   -- the x index by 2.








    +   cbit <= rom_word( to_integer(ch) );








    +








    +   -- Determine color bit either foreground if cbit is set, background else.








    +   red   <= vid.fgc(2) when cbit = '1' else vid.bgc(2);








    +   green <= vid.fgc(1) when cbit = '1' else vid.bgc(1);








    +   blue  <= vid.fgc(0) when cbit = '1' else vid.bgc(0);








    +








    +   -- Check if we are whtin the display area, pull to '0' if not. Otherwise we








    +   -- get weird behavior.








    +   VGA_RED   <= red   when vid.vis(1) = '1' else '0';








    +   VGA_GREEN <= green when vid.vis(1) = '1' else '0';








    +   VGA_BLUE  <= blue  when vid.vis(1) = '1' else '0';








    +end rtl;








    \ No newline at end of file








    Index: layer2/trunk/vhdl/vga/rtl/rom.vhd








    ===================================================================








    --- layer2/trunk/vhdl/vga/rtl/rom.vhd	(nonexistent)








    +++ layer2/trunk/vhdl/vga/rtl/rom.vhd	(revision 2)








    @@ -0,0 +1,2375 @@








    +--------------------------------------------------------------------------------








    +-- 8-Color 100x37 Textmode Video Controller                                   --








    +--------------------------------------------------------------------------------








    +--                                                                            --








    +-- IMPORTANT NOTICE                                                           --








    +--                                                                            --








    +-- Data in reverse order and shifted to the left 2px. Saves LUTs. Use the     --








    +-- python script  to generate your customized character set.        --








    +--                                                                            --








    +--------------------------------------------------------------------------------








    +-- Copyright (C)2011  Mathias H�rtnagl          --








    +--                                                                            --








    +-- This program is free software: you can redistribute it and/or modify       --








    +-- it under the terms of the GNU General Public License as published by       --








    +-- the Free Software Foundation, either version 3 of the License, or          --








    +-- (at your option) any later version.                                        --








    +--                                                                            --








    +-- This program is distributed in the hope that it will be useful,            --








    +-- but WITHOUT ANY WARRANTY; without even the implied warranty of             --








    +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the              --








    +-- GNU General Public License for more details.                               --








    +--                                                                            --








    +-- You should have received a copy of the GNU General Public License          --








    +-- along with this program.  If not, see .      --








    +--------------------------------------------------------------------------------








    +library ieee;








    +use ieee.std_logic_1164.all;








    +use ieee.numeric_std.all;








    +








    +entity rom is








    +   port(








    +      clk      : in  std_logic;








    +      rom_addr : in  std_logic_vector(11 downto 0);








    +      rom_word : out std_logic_vector(7 downto 0)








    +   );








    +end rom;








    +








    +architecture rtl of rom is








    +begin








    +   chrs : process(clk)








    +   begin








    +      if rising_edge(clk) then








    +         case to_integer(unsigned(rom_addr)) is








    +            when   18 => rom_word <= "11111001";








    +            when   19 => rom_word <= "00000110";








    +            when   20 => rom_word <= "10010110";








    +            when   21 => rom_word <= "00000110";








    +            when   22 => rom_word <= "00000110";








    +            when   23 => rom_word <= "11110110";








    +            when   24 => rom_word <= "01100110";








    +            when   25 => rom_word <= "00000110";








    +            when   26 => rom_word <= "00000110";








    +            when   27 => rom_word <= "11111001";








    +            when   34 => rom_word <= "11111001";








    +            when   35 => rom_word <= "11111111";








    +            when   36 => rom_word <= "01101111";








    +            when   37 => rom_word <= "11111111";








    +            when   38 => rom_word <= "11111111";








    +            when   39 => rom_word <= "00001111";








    +            when   40 => rom_word <= "10011111";








    +            when   41 => rom_word <= "11111111";








    +            when   42 => rom_word <= "11111111";








    +            when   43 => rom_word <= "11111001";








    +            when   52 => rom_word <= "11011000";








    +            when   53 => rom_word <= "11111101";








    +            when   54 => rom_word <= "11111101";








    +            when   55 => rom_word <= "11111101";








    +            when   56 => rom_word <= "11111101";








    +            when   57 => rom_word <= "11111000";








    +            when   58 => rom_word <= "01110000";








    +            when   59 => rom_word <= "00100000";








    +            when   68 => rom_word <= "00100000";








    +            when   69 => rom_word <= "01110000";








    +            when   70 => rom_word <= "11111000";








    +            when   71 => rom_word <= "11111101";








    +            when   72 => rom_word <= "11111000";








    +            when   73 => rom_word <= "01110000";








    +            when   74 => rom_word <= "00100000";








    +            when   83 => rom_word <= "01100000";








    +            when   84 => rom_word <= "11110000";








    +            when   85 => rom_word <= "11110000";








    +            when   86 => rom_word <= "10011111";








    +            when   87 => rom_word <= "10011111";








    +            when   88 => rom_word <= "10011111";








    +            when   89 => rom_word <= "01100000";








    +            when   90 => rom_word <= "01100000";








    +            when   91 => rom_word <= "11110000";








    +            when   99 => rom_word <= "01100000";








    +            when  100 => rom_word <= "11110000";








    +            when  101 => rom_word <= "11111001";








    +            when  102 => rom_word <= "11111111";








    +            when  103 => rom_word <= "11111111";








    +            when  104 => rom_word <= "11111001";








    +            when  105 => rom_word <= "01100000";








    +            when  106 => rom_word <= "01100000";








    +            when  107 => rom_word <= "11110000";








    +            when  118 => rom_word <= "01100000";








    +            when  119 => rom_word <= "11110000";








    +            when  120 => rom_word <= "11110000";








    +            when  121 => rom_word <= "01100000";








    +            when  128 => rom_word <= "11111111";








    +            when  129 => rom_word <= "11111111";








    +            when  130 => rom_word <= "11111111";








    +            when  131 => rom_word <= "11111111";








    +            when  132 => rom_word <= "11111111";








    +            when  133 => rom_word <= "11111111";








    +            when  134 => rom_word <= "10011111";








    +            when  135 => rom_word <= "00001111";








    +            when  136 => rom_word <= "00001111";








    +            when  137 => rom_word <= "10011111";








    +            when  138 => rom_word <= "11111111";








    +            when  139 => rom_word <= "11111111";








    +            when  140 => rom_word <= "11111111";








    +            when  141 => rom_word <= "11111111";








    +            when  142 => rom_word <= "11111111";








    +            when  143 => rom_word <= "11111111";








    +            when  149 => rom_word <= "11110000";








    +            when  150 => rom_word <= "10011001";








    +            when  151 => rom_word <= "00001001";








    +            when  152 => rom_word <= "00001001";








    +            when  153 => rom_word <= "10011001";








    +            when  154 => rom_word <= "11110000";








    +            when  160 => rom_word <= "11111111";








    +            when  161 => rom_word <= "11111111";








    +            when  162 => rom_word <= "11111111";








    +            when  163 => rom_word <= "11111111";








    +            when  164 => rom_word <= "11111111";








    +            when  165 => rom_word <= "00001111";








    +            when  166 => rom_word <= "01100110";








    +            when  167 => rom_word <= "11110110";








    +            when  168 => rom_word <= "11110110";








    +            when  169 => rom_word <= "01100110";








    +            when  170 => rom_word <= "00001111";








    +            when  171 => rom_word <= "11111111";








    +            when  172 => rom_word <= "11111111";








    +            when  173 => rom_word <= "11111111";








    +            when  174 => rom_word <= "11111111";








    +            when  175 => rom_word <= "11111111";








    +            when  178 => rom_word <= "11100001";








    +            when  179 => rom_word <= "11000001";








    +            when  180 => rom_word <= "01100001";








    +            when  181 => rom_word <= "00110001";








    +            when  182 => rom_word <= "01111000";








    +            when  183 => rom_word <= "11001100";








    +            when  184 => rom_word <= "11001100";








    +            when  185 => rom_word <= "11001100";








    +            when  186 => rom_word <= "11001100";








    +            when  187 => rom_word <= "01111000";








    +            when  194 => rom_word <= "11110000";








    +            when  195 => rom_word <= "10011001";








    +            when  196 => rom_word <= "10011001";








    +            when  197 => rom_word <= "10011001";








    +            when  198 => rom_word <= "10011001";








    +            when  199 => rom_word <= "11110000";








    +            when  200 => rom_word <= "01100000";








    +            when  201 => rom_word <= "11111001";








    +            when  202 => rom_word <= "01100000";








    +            when  203 => rom_word <= "01100000";








    +            when  210 => rom_word <= "11110011";








    +            when  211 => rom_word <= "00110011";








    +            when  212 => rom_word <= "11110011";








    +            when  213 => rom_word <= "00110000";








    +            when  214 => rom_word <= "00110000";








    +            when  215 => rom_word <= "00110000";








    +            when  216 => rom_word <= "00110000";








    +            when  217 => rom_word <= "00111000";








    +            when  218 => rom_word <= "00111100";








    +            when  219 => rom_word <= "00011100";








    +            when  226 => rom_word <= "11111011";








    +            when  227 => rom_word <= "00011011";








    +            when  228 => rom_word <= "11111011";








    +            when  229 => rom_word <= "00011011";








    +            when  230 => rom_word <= "00011011";








    +            when  231 => rom_word <= "00011011";








    +            when  232 => rom_word <= "00011011";








    +            when  233 => rom_word <= "10011011";








    +            when  234 => rom_word <= "10011111";








    +            when  235 => rom_word <= "10011101";








    +            when  236 => rom_word <= "00001100";








    +            when  243 => rom_word <= "01100000";








    +            when  244 => rom_word <= "01100000";








    +            when  245 => rom_word <= "01101111";








    +            when  246 => rom_word <= "11110000";








    +            when  247 => rom_word <= "10011111";








    +            when  248 => rom_word <= "11110000";








    +            when  249 => rom_word <= "01101111";








    +            when  250 => rom_word <= "01100000";








    +            when  251 => rom_word <= "01100000";








    +            when  257 => rom_word <= "00000100";








    +            when  258 => rom_word <= "00001100";








    +            when  259 => rom_word <= "00011100";








    +            when  260 => rom_word <= "00111100";








    +            when  261 => rom_word <= "01111100";








    +            when  262 => rom_word <= "11111101";








    +            when  263 => rom_word <= "01111100";








    +            when  264 => rom_word <= "00111100";








    +            when  265 => rom_word <= "00011100";








    +            when  266 => rom_word <= "00001100";








    +            when  267 => rom_word <= "00000100";








    +            when  273 => rom_word <= "00000001";








    +            when  274 => rom_word <= "10000001";








    +            when  275 => rom_word <= "11000001";








    +            when  276 => rom_word <= "11100001";








    +            when  277 => rom_word <= "11110001";








    +            when  278 => rom_word <= "11111101";








    +            when  279 => rom_word <= "11110001";








    +            when  280 => rom_word <= "11100001";








    +            when  281 => rom_word <= "11000001";








    +            when  282 => rom_word <= "10000001";








    +            when  283 => rom_word <= "00000001";








    +            when  290 => rom_word <= "01100000";








    +            when  291 => rom_word <= "11110000";








    +            when  292 => rom_word <= "11111001";








    +            when  293 => rom_word <= "01100000";








    +            when  294 => rom_word <= "01100000";








    +            when  295 => rom_word <= "01100000";








    +            when  296 => rom_word <= "11111001";








    +            when  297 => rom_word <= "11110000";








    +            when  298 => rom_word <= "01100000";








    +            when  306 => rom_word <= "10011001";








    +            when  307 => rom_word <= "10011001";








    +            when  308 => rom_word <= "10011001";








    +            when  309 => rom_word <= "10011001";








    +            when  310 => rom_word <= "10011001";








    +            when  311 => rom_word <= "10011001";








    +            when  312 => rom_word <= "10011001";








    +            when  314 => rom_word <= "10011001";








    +            when  315 => rom_word <= "10011001";








    +            when  322 => rom_word <= "11111011";








    +            when  323 => rom_word <= "01101111";








    +            when  324 => rom_word <= "01101111";








    +            when  325 => rom_word <= "01101111";








    +            when  326 => rom_word <= "01111011";








    +            when  327 => rom_word <= "01100011";








    +            when  328 => rom_word <= "01100011";








    +            when  329 => rom_word <= "01100011";








    +            when  330 => rom_word <= "01100011";








    +            when  331 => rom_word <= "01100011";








    +            when  337 => rom_word <= "11111000";








    +            when  338 => rom_word <= "10001101";








    +            when  339 => rom_word <= "00011000";








    +            when  340 => rom_word <= "01110000";








    +            when  341 => rom_word <= "11011000";








    +            when  342 => rom_word <= "10001101";








    +            when  343 => rom_word <= "10001101";








    +            when  344 => rom_word <= "11011000";








    +            when  345 => rom_word <= "01110000";








    +            when  346 => rom_word <= "11000000";








    +            when  347 => rom_word <= "10001101";








    +            when  348 => rom_word <= "11111000";








    +            when  360 => rom_word <= "11111101";








    +            when  361 => rom_word <= "11111101";








    +            when  362 => rom_word <= "11111101";








    +            when  363 => rom_word <= "11111101";








    +            when  370 => rom_word <= "01100000";








    +            when  371 => rom_word <= "11110000";








    +            when  372 => rom_word <= "11111001";








    +            when  373 => rom_word <= "01100000";








    +            when  374 => rom_word <= "01100000";








    +            when  375 => rom_word <= "01100000";








    +            when  376 => rom_word <= "11111001";








    +            when  377 => rom_word <= "11110000";








    +            when  378 => rom_word <= "01100000";








    +            when  379 => rom_word <= "11111001";








    +            when  386 => rom_word <= "01100000";








    +            when  387 => rom_word <= "11110000";








    +            when  388 => rom_word <= "11111001";








    +            when  389 => rom_word <= "01100000";








    +            when  390 => rom_word <= "01100000";








    +            when  391 => rom_word <= "01100000";








    +            when  392 => rom_word <= "01100000";








    +            when  393 => rom_word <= "01100000";








    +            when  394 => rom_word <= "01100000";








    +            when  395 => rom_word <= "01100000";








    +            when  402 => rom_word <= "01100000";








    +            when  403 => rom_word <= "01100000";








    +            when  404 => rom_word <= "01100000";








    +            when  405 => rom_word <= "01100000";








    +            when  406 => rom_word <= "01100000";








    +            when  407 => rom_word <= "01100000";








    +            when  408 => rom_word <= "01100000";








    +            when  409 => rom_word <= "11111001";








    +            when  410 => rom_word <= "11110000";








    +            when  411 => rom_word <= "01100000";








    +            when  421 => rom_word <= "01100000";








    +            when  422 => rom_word <= "11000000";








    +            when  423 => rom_word <= "11111101";








    +            when  424 => rom_word <= "11000000";








    +            when  425 => rom_word <= "01100000";








    +            when  437 => rom_word <= "00110000";








    +            when  438 => rom_word <= "00011000";








    +            when  439 => rom_word <= "11111101";








    +            when  440 => rom_word <= "00011000";








    +            when  441 => rom_word <= "00110000";








    +            when  454 => rom_word <= "00001100";








    +            when  455 => rom_word <= "00001100";








    +            when  456 => rom_word <= "00001100";








    +            when  457 => rom_word <= "11111101";








    +            when  469 => rom_word <= "01010000";








    +            when  470 => rom_word <= "11011000";








    +            when  471 => rom_word <= "11111101";








    +            when  472 => rom_word <= "11011000";








    +            when  473 => rom_word <= "01010000";








    +            when  484 => rom_word <= "00100000";








    +            when  485 => rom_word <= "01110000";








    +            when  486 => rom_word <= "01110000";








    +            when  487 => rom_word <= "11111000";








    +            when  488 => rom_word <= "11111000";








    +            when  489 => rom_word <= "11111101";








    +            when  490 => rom_word <= "11111101";








    +            when  500 => rom_word <= "11111101";








    +            when  501 => rom_word <= "11111101";








    +            when  502 => rom_word <= "11111000";








    +            when  503 => rom_word <= "11111000";








    +            when  504 => rom_word <= "01110000";








    +            when  505 => rom_word <= "01110000";








    +            when  506 => rom_word <= "00100000";








    +            when  530 => rom_word <= "01100000";








    +            when  531 => rom_word <= "11110000";








    +            when  532 => rom_word <= "11110000";








    +            when  533 => rom_word <= "11110000";








    +            when  534 => rom_word <= "01100000";








    +            when  535 => rom_word <= "01100000";








    +            when  536 => rom_word <= "01100000";








    +            when  538 => rom_word <= "01100000";








    +            when  539 => rom_word <= "01100000";








    +            when  545 => rom_word <= "10011001";








    +            when  546 => rom_word <= "10011001";








    +            when  547 => rom_word <= "10011001";








    +            when  548 => rom_word <= "10010000";








    +            when  563 => rom_word <= "11011000";








    +            when  564 => rom_word <= "11011000";








    +            when  565 => rom_word <= "11111101";








    +            when  566 => rom_word <= "11011000";








    +            when  567 => rom_word <= "11011000";








    +            when  568 => rom_word <= "11011000";








    +            when  569 => rom_word <= "11111101";








    +            when  570 => rom_word <= "11011000";








    +            when  571 => rom_word <= "11011000";








    +            when  576 => rom_word <= "01100000";








    +            when  577 => rom_word <= "01100000";








    +            when  578 => rom_word <= "11111000";








    +            when  579 => rom_word <= "10001101";








    +            when  580 => rom_word <= "00001101";








    +            when  581 => rom_word <= "00001100";








    +            when  582 => rom_word <= "11111000";








    +            when  583 => rom_word <= "10000001";








    +            when  584 => rom_word <= "10000001";








    +            when  585 => rom_word <= "10000101";








    +            when  586 => rom_word <= "10001101";








    +            when  587 => rom_word <= "11111000";








    +            when  588 => rom_word <= "01100000";








    +            when  589 => rom_word <= "01100000";








    +            when  596 => rom_word <= "00001101";








    +            when  597 => rom_word <= "10001101";








    +            when  598 => rom_word <= "11000000";








    +            when  599 => rom_word <= "01100000";








    +            when  600 => rom_word <= "00110000";








    +            when  601 => rom_word <= "00011000";








    +            when  602 => rom_word <= "10001101";








    +            when  603 => rom_word <= "10000101";








    +            when  610 => rom_word <= "01110000";








    +            when  611 => rom_word <= "11011000";








    +            when  612 => rom_word <= "11011000";








    +            when  613 => rom_word <= "01110000";








    +            when  614 => rom_word <= "10111001";








    +            when  615 => rom_word <= "11101100";








    +            when  616 => rom_word <= "11001100";








    +            when  617 => rom_word <= "11001100";








    +            when  618 => rom_word <= "11001100";








    +            when  619 => rom_word <= "10111001";








    +            when  625 => rom_word <= "00110000";








    +            when  626 => rom_word <= "00110000";








    +            when  627 => rom_word <= "00110000";








    +            when  628 => rom_word <= "00011000";








    +            when  642 => rom_word <= "11000000";








    +            when  643 => rom_word <= "01100000";








    +            when  644 => rom_word <= "00110000";








    +            when  645 => rom_word <= "00110000";








    +            when  646 => rom_word <= "00110000";








    +            when  647 => rom_word <= "00110000";








    +            when  648 => rom_word <= "00110000";








    +            when  649 => rom_word <= "00110000";








    +            when  650 => rom_word <= "01100000";








    +            when  651 => rom_word <= "11000000";








    +            when  658 => rom_word <= "00110000";








    +            when  659 => rom_word <= "01100000";








    +            when  660 => rom_word <= "11000000";








    +            when  661 => rom_word <= "11000000";








    +            when  662 => rom_word <= "11000000";








    +            when  663 => rom_word <= "11000000";








    +            when  664 => rom_word <= "11000000";








    +            when  665 => rom_word <= "11000000";








    +            when  666 => rom_word <= "01100000";








    +            when  667 => rom_word <= "00110000";








    +            when  677 => rom_word <= "10011001";








    +            when  678 => rom_word <= "11110000";








    +            when  679 => rom_word <= "11111111";








    +            when  680 => rom_word <= "11110000";








    +            when  681 => rom_word <= "10011001";








    +            when  693 => rom_word <= "01100000";








    +            when  694 => rom_word <= "01100000";








    +            when  695 => rom_word <= "11111001";








    +            when  696 => rom_word <= "01100000";








    +            when  697 => rom_word <= "01100000";








    +            when  713 => rom_word <= "01100000";








    +            when  714 => rom_word <= "01100000";








    +            when  715 => rom_word <= "01100000";








    +            when  716 => rom_word <= "00110000";








    +            when  727 => rom_word <= "11111101";








    +            when  746 => rom_word <= "01100000";








    +            when  747 => rom_word <= "01100000";








    +            when  756 => rom_word <= "00000001";








    +            when  757 => rom_word <= "10000001";








    +            when  758 => rom_word <= "11000000";








    +            when  759 => rom_word <= "01100000";








    +            when  760 => rom_word <= "00110000";








    +            when  761 => rom_word <= "00011000";








    +            when  762 => rom_word <= "00001100";








    +            when  763 => rom_word <= "00000100";








    +            when  770 => rom_word <= "01110000";








    +            when  771 => rom_word <= "11011000";








    +            when  772 => rom_word <= "10001101";








    +            when  773 => rom_word <= "11001101";








    +            when  774 => rom_word <= "11101101";








    +            when  775 => rom_word <= "10111101";








    +            when  776 => rom_word <= "10011101";








    +            when  777 => rom_word <= "10001101";








    +            when  778 => rom_word <= "11011000";








    +            when  779 => rom_word <= "01110000";








    +            when  786 => rom_word <= "01100000";








    +            when  787 => rom_word <= "01110000";








    +            when  788 => rom_word <= "01111000";








    +            when  789 => rom_word <= "01100000";








    +            when  790 => rom_word <= "01100000";








    +            when  791 => rom_word <= "01100000";








    +            when  792 => rom_word <= "01100000";








    +            when  793 => rom_word <= "01100000";








    +            when  794 => rom_word <= "01100000";








    +            when  795 => rom_word <= "01100000";








    +            when  802 => rom_word <= "11111000";








    +            when  803 => rom_word <= "10001101";








    +            when  804 => rom_word <= "10000001";








    +            when  805 => rom_word <= "11000000";








    +            when  806 => rom_word <= "01100000";








    +            when  807 => rom_word <= "00110000";








    +            when  808 => rom_word <= "00011000";








    +            when  809 => rom_word <= "00001100";








    +            when  810 => rom_word <= "00001100";








    +            when  811 => rom_word <= "11111101";








    +            when  818 => rom_word <= "11111000";








    +            when  819 => rom_word <= "10000101";








    +            when  820 => rom_word <= "10000001";








    +            when  821 => rom_word <= "10000001";








    +            when  822 => rom_word <= "11110000";








    +            when  823 => rom_word <= "10000001";








    +            when  824 => rom_word <= "10000001";








    +            when  825 => rom_word <= "10000001";








    +            when  826 => rom_word <= "10000101";








    +            when  827 => rom_word <= "11111000";








    +            when  834 => rom_word <= "11000000";








    +            when  835 => rom_word <= "11100000";








    +            when  836 => rom_word <= "11110000";








    +            when  837 => rom_word <= "11011000";








    +            when  838 => rom_word <= "11001100";








    +            when  839 => rom_word <= "11111101";








    +            when  840 => rom_word <= "11000000";








    +            when  841 => rom_word <= "11000000";








    +            when  842 => rom_word <= "11000000";








    +            when  843 => rom_word <= "11000000";








    +            when  850 => rom_word <= "11111101";








    +            when  851 => rom_word <= "00001100";








    +            when  852 => rom_word <= "00001100";








    +            when  853 => rom_word <= "00001100";








    +            when  854 => rom_word <= "11111100";








    +            when  855 => rom_word <= "10000001";








    +            when  856 => rom_word <= "10000001";








    +            when  857 => rom_word <= "10000001";








    +            when  858 => rom_word <= "10000101";








    +            when  859 => rom_word <= "11111000";








    +            when  866 => rom_word <= "11110000";








    +            when  867 => rom_word <= "00011000";








    +            when  868 => rom_word <= "00001100";








    +            when  869 => rom_word <= "00001100";








    +            when  870 => rom_word <= "11101100";








    +            when  871 => rom_word <= "10011101";








    +            when  872 => rom_word <= "10001101";








    +            when  873 => rom_word <= "10001101";








    +            when  874 => rom_word <= "10001101";








    +            when  875 => rom_word <= "11111000";








    +            when  882 => rom_word <= "11111101";








    +            when  883 => rom_word <= "10000001";








    +            when  884 => rom_word <= "10000001";








    +            when  885 => rom_word <= "10000001";








    +            when  886 => rom_word <= "11000000";








    +            when  887 => rom_word <= "01100000";








    +            when  888 => rom_word <= "00110000";








    +            when  889 => rom_word <= "00110000";








    +            when  890 => rom_word <= "00110000";








    +            when  891 => rom_word <= "00110000";








    +            when  898 => rom_word <= "11111000";








    +            when  899 => rom_word <= "10001101";








    +            when  900 => rom_word <= "10001101";








    +            when  901 => rom_word <= "10001101";








    +            when  902 => rom_word <= "11111000";








    +            when  903 => rom_word <= "10001101";








    +            when  904 => rom_word <= "10001101";








    +            when  905 => rom_word <= "10001101";








    +            when  906 => rom_word <= "10001101";








    +            when  907 => rom_word <= "11111000";








    +            when  914 => rom_word <= "11111000";








    +            when  915 => rom_word <= "10001101";








    +            when  916 => rom_word <= "10001101";








    +            when  917 => rom_word <= "10001101";








    +            when  918 => rom_word <= "11111001";








    +            when  919 => rom_word <= "10000001";








    +            when  920 => rom_word <= "10000001";








    +            when  921 => rom_word <= "10000001";








    +            when  922 => rom_word <= "11000100";








    +            when  923 => rom_word <= "01111000";








    +            when  932 => rom_word <= "01100000";








    +            when  933 => rom_word <= "01100000";








    +            when  937 => rom_word <= "01100000";








    +            when  938 => rom_word <= "01100000";








    +            when  948 => rom_word <= "01100000";








    +            when  949 => rom_word <= "01100000";








    +            when  953 => rom_word <= "01100000";








    +            when  954 => rom_word <= "01100000";








    +            when  955 => rom_word <= "00110000";








    +            when  963 => rom_word <= "10000001";








    +            when  964 => rom_word <= "11000000";








    +            when  965 => rom_word <= "01100000";








    +            when  966 => rom_word <= "00110000";








    +            when  967 => rom_word <= "00011000";








    +            when  968 => rom_word <= "00110000";








    +            when  969 => rom_word <= "01100000";








    +            when  970 => rom_word <= "11000000";








    +            when  971 => rom_word <= "10000001";








    +            when  981 => rom_word <= "11111001";








    +            when  984 => rom_word <= "11111001";








    +            when  995 => rom_word <= "00011000";








    +            when  996 => rom_word <= "00110000";








    +            when  997 => rom_word <= "01100000";








    +            when  998 => rom_word <= "11000000";








    +            when  999 => rom_word <= "10000001";








    +            when 1000 => rom_word <= "11000000";








    +            when 1001 => rom_word <= "01100000";








    +            when 1002 => rom_word <= "00110000";








    +            when 1003 => rom_word <= "00011000";








    +            when 1010 => rom_word <= "11111000";








    +            when 1011 => rom_word <= "10001101";








    +            when 1012 => rom_word <= "10001101";








    +            when 1013 => rom_word <= "11000000";








    +            when 1014 => rom_word <= "01100000";








    +            when 1015 => rom_word <= "01100000";








    +            when 1016 => rom_word <= "01100000";








    +            when 1018 => rom_word <= "01100000";








    +            when 1019 => rom_word <= "01100000";








    +            when 1027 => rom_word <= "11111000";








    +            when 1028 => rom_word <= "10001101";








    +            when 1029 => rom_word <= "10001101";








    +            when 1030 => rom_word <= "11101101";








    +            when 1031 => rom_word <= "11101101";








    +            when 1032 => rom_word <= "11101101";








    +            when 1033 => rom_word <= "11101100";








    +            when 1034 => rom_word <= "00001100";








    +            when 1035 => rom_word <= "11111000";








    +            when 1042 => rom_word <= "00100000";








    +            when 1043 => rom_word <= "01110000";








    +            when 1044 => rom_word <= "11011000";








    +            when 1045 => rom_word <= "10001101";








    +            when 1046 => rom_word <= "10001101";








    +            when 1047 => rom_word <= "11111101";








    +            when 1048 => rom_word <= "10001101";








    +            when 1049 => rom_word <= "10001101";








    +            when 1050 => rom_word <= "10001101";








    +            when 1051 => rom_word <= "10001101";








    +            when 1058 => rom_word <= "11111100";








    +            when 1059 => rom_word <= "10001101";








    +            when 1060 => rom_word <= "10001101";








    +            when 1061 => rom_word <= "10001101";








    +            when 1062 => rom_word <= "11111100";








    +            when 1063 => rom_word <= "10001101";








    +            when 1064 => rom_word <= "10001101";








    +            when 1065 => rom_word <= "10001101";








    +            when 1066 => rom_word <= "10001101";








    +            when 1067 => rom_word <= "11111100";








    +            when 1074 => rom_word <= "11110000";








    +            when 1075 => rom_word <= "10011001";








    +            when 1076 => rom_word <= "00001101";








    +            when 1077 => rom_word <= "00001100";








    +            when 1078 => rom_word <= "00001100";








    +            when 1079 => rom_word <= "00001100";








    +            when 1080 => rom_word <= "00001100";








    +            when 1081 => rom_word <= "00001101";








    +            when 1082 => rom_word <= "10011001";








    +            when 1083 => rom_word <= "11110000";








    +            when 1090 => rom_word <= "01111100";








    +            when 1091 => rom_word <= "11101100";








    +            when 1092 => rom_word <= "11001101";








    +            when 1093 => rom_word <= "10001101";








    +            when 1094 => rom_word <= "10001101";








    +            when 1095 => rom_word <= "10001101";








    +            when 1096 => rom_word <= "10001101";








    +            when 1097 => rom_word <= "11001101";








    +            when 1098 => rom_word <= "11101100";








    +            when 1099 => rom_word <= "01111100";








    +            when 1106 => rom_word <= "11111100";








    +            when 1107 => rom_word <= "00001100";








    +            when 1108 => rom_word <= "00001100";








    +            when 1109 => rom_word <= "00001100";








    +            when 1110 => rom_word <= "01111100";








    +            when 1111 => rom_word <= "00001100";








    +            when 1112 => rom_word <= "00001100";








    +            when 1113 => rom_word <= "00001100";








    +            when 1114 => rom_word <= "00001100";








    +            when 1115 => rom_word <= "11111100";








    +            when 1122 => rom_word <= "11111100";








    +            when 1123 => rom_word <= "00001100";








    +            when 1124 => rom_word <= "00001100";








    +            when 1125 => rom_word <= "00001100";








    +            when 1126 => rom_word <= "01111100";








    +            when 1127 => rom_word <= "00001100";








    +            when 1128 => rom_word <= "00001100";








    +            when 1129 => rom_word <= "00001100";








    +            when 1130 => rom_word <= "00001100";








    +            when 1131 => rom_word <= "00001100";








    +            when 1138 => rom_word <= "11110000";








    +            when 1139 => rom_word <= "00011001";








    +            when 1140 => rom_word <= "00001100";








    +            when 1141 => rom_word <= "00001100";








    +            when 1142 => rom_word <= "00001100";








    +            when 1143 => rom_word <= "11101101";








    +            when 1144 => rom_word <= "10001101";








    +            when 1145 => rom_word <= "10001101";








    +            when 1146 => rom_word <= "10011001";








    +            when 1147 => rom_word <= "11110001";








    +            when 1154 => rom_word <= "10001101";








    +            when 1155 => rom_word <= "10001101";








    +            when 1156 => rom_word <= "10001101";








    +            when 1157 => rom_word <= "10001101";








    +            when 1158 => rom_word <= "11111101";








    +            when 1159 => rom_word <= "10001101";








    +            when 1160 => rom_word <= "10001101";








    +            when 1161 => rom_word <= "10001101";








    +            when 1162 => rom_word <= "10001101";








    +            when 1163 => rom_word <= "10001101";








    +            when 1170 => rom_word <= "01100000";








    +            when 1171 => rom_word <= "01100000";








    +            when 1172 => rom_word <= "01100000";








    +            when 1173 => rom_word <= "01100000";








    +            when 1174 => rom_word <= "01100000";








    +            when 1175 => rom_word <= "01100000";








    +            when 1176 => rom_word <= "01100000";








    +            when 1177 => rom_word <= "01100000";








    +            when 1178 => rom_word <= "01100000";








    +            when 1179 => rom_word <= "01100000";








    +            when 1186 => rom_word <= "11100001";








    +            when 1187 => rom_word <= "11000000";








    +            when 1188 => rom_word <= "11000000";








    +            when 1189 => rom_word <= "11000000";








    +            when 1190 => rom_word <= "11000000";








    +            when 1191 => rom_word <= "11000000";








    +            when 1192 => rom_word <= "11001100";








    +            when 1193 => rom_word <= "11001100";








    +            when 1194 => rom_word <= "11001100";








    +            when 1195 => rom_word <= "01111000";








    +            when 1202 => rom_word <= "00001101";








    +            when 1203 => rom_word <= "10001101";








    +            when 1204 => rom_word <= "11001100";








    +            when 1205 => rom_word <= "01101100";








    +            when 1206 => rom_word <= "00111100";








    +            when 1207 => rom_word <= "00111100";








    +            when 1208 => rom_word <= "01101100";








    +            when 1209 => rom_word <= "11001100";








    +            when 1210 => rom_word <= "10001101";








    +            when 1211 => rom_word <= "00001101";








    +            when 1218 => rom_word <= "00001100";








    +            when 1219 => rom_word <= "00001100";








    +            when 1220 => rom_word <= "00001100";








    +            when 1221 => rom_word <= "00001100";








    +            when 1222 => rom_word <= "00001100";








    +            when 1223 => rom_word <= "00001100";








    +            when 1224 => rom_word <= "00001100";








    +            when 1225 => rom_word <= "00001100";








    +            when 1226 => rom_word <= "00001100";








    +            when 1227 => rom_word <= "11111100";








    +            when 1234 => rom_word <= "10001101";








    +            when 1235 => rom_word <= "11011101";








    +            when 1236 => rom_word <= "11111101";








    +            when 1237 => rom_word <= "11111101";








    +            when 1238 => rom_word <= "10101101";








    +            when 1239 => rom_word <= "10001101";








    +            when 1240 => rom_word <= "10001101";








    +            when 1241 => rom_word <= "10001101";








    +            when 1242 => rom_word <= "10001101";








    +            when 1243 => rom_word <= "10001101";








    +            when 1250 => rom_word <= "10001101";








    +            when 1251 => rom_word <= "10011101";








    +            when 1252 => rom_word <= "10111101";








    +            when 1253 => rom_word <= "11111101";








    +            when 1254 => rom_word <= "11101101";








    +            when 1255 => rom_word <= "11001101";








    +            when 1256 => rom_word <= "10001101";








    +            when 1257 => rom_word <= "10001101";








    +            when 1258 => rom_word <= "10001101";








    +            when 1259 => rom_word <= "10001101";








    +            when 1266 => rom_word <= "11111000";








    +            when 1267 => rom_word <= "10001101";








    +            when 1268 => rom_word <= "10001101";








    +            when 1269 => rom_word <= "10001101";








    +            when 1270 => rom_word <= "10001101";








    +            when 1271 => rom_word <= "10001101";








    +            when 1272 => rom_word <= "10001101";








    +            when 1273 => rom_word <= "10001101";








    +            when 1274 => rom_word <= "10001101";








    +            when 1275 => rom_word <= "11111000";








    +            when 1282 => rom_word <= "11111100";








    +            when 1283 => rom_word <= "10001101";








    +            when 1284 => rom_word <= "10001101";








    +            when 1285 => rom_word <= "10001101";








    +            when 1286 => rom_word <= "11111100";








    +            when 1287 => rom_word <= "00001100";








    +            when 1288 => rom_word <= "00001100";








    +            when 1289 => rom_word <= "00001100";








    +            when 1290 => rom_word <= "00001100";








    +            when 1291 => rom_word <= "00001100";








    +            when 1298 => rom_word <= "11111000";








    +            when 1299 => rom_word <= "10001101";








    +            when 1300 => rom_word <= "10001101";








    +            when 1301 => rom_word <= "10001101";








    +            when 1302 => rom_word <= "10001101";








    +            when 1303 => rom_word <= "10001101";








    +            when 1304 => rom_word <= "10001101";








    +            when 1305 => rom_word <= "10101101";








    +            when 1306 => rom_word <= "11101101";








    +            when 1307 => rom_word <= "11111000";








    +            when 1308 => rom_word <= "11000000";








    +            when 1309 => rom_word <= "10000001";








    +            when 1314 => rom_word <= "11111100";








    +            when 1315 => rom_word <= "10001101";








    +            when 1316 => rom_word <= "10001101";








    +            when 1317 => rom_word <= "10001101";








    +            when 1318 => rom_word <= "11111100";








    +            when 1319 => rom_word <= "01101100";








    +            when 1320 => rom_word <= "11001100";








    +            when 1321 => rom_word <= "11001100";








    +            when 1322 => rom_word <= "10001101";








    +            when 1323 => rom_word <= "10001101";








    +            when 1330 => rom_word <= "11111000";








    +            when 1331 => rom_word <= "00001101";








    +            when 1332 => rom_word <= "00001100";








    +            when 1333 => rom_word <= "00011000";








    +            when 1334 => rom_word <= "01110000";








    +            when 1335 => rom_word <= "11000000";








    +            when 1336 => rom_word <= "10000001";








    +            when 1337 => rom_word <= "10000001";








    +            when 1338 => rom_word <= "10000101";








    +            when 1339 => rom_word <= "11111000";








    +            when 1346 => rom_word <= "11111001";








    +            when 1347 => rom_word <= "11111001";








    +            when 1348 => rom_word <= "01100000";








    +            when 1349 => rom_word <= "01100000";








    +            when 1350 => rom_word <= "01100000";








    +            when 1351 => rom_word <= "01100000";








    +            when 1352 => rom_word <= "01100000";








    +            when 1353 => rom_word <= "01100000";








    +            when 1354 => rom_word <= "01100000";








    +            when 1355 => rom_word <= "01100000";








    +            when 1362 => rom_word <= "10001101";








    +            when 1363 => rom_word <= "10001101";








    +            when 1364 => rom_word <= "10001101";








    +            when 1365 => rom_word <= "10001101";








    +            when 1366 => rom_word <= "10001101";








    +            when 1367 => rom_word <= "10001101";








    +            when 1368 => rom_word <= "10001101";








    +            when 1369 => rom_word <= "10001101";








    +            when 1370 => rom_word <= "10001101";








    +            when 1371 => rom_word <= "11111000";








    +            when 1378 => rom_word <= "10001101";








    +            when 1379 => rom_word <= "10001101";








    +            when 1380 => rom_word <= "10001101";








    +            when 1381 => rom_word <= "10001101";








    +            when 1382 => rom_word <= "10001101";








    +            when 1383 => rom_word <= "10001101";








    +            when 1384 => rom_word <= "10001101";








    +            when 1385 => rom_word <= "11011000";








    +            when 1386 => rom_word <= "01110000";








    +            when 1387 => rom_word <= "00100000";








    +            when 1394 => rom_word <= "10001101";








    +            when 1395 => rom_word <= "10001101";








    +            when 1396 => rom_word <= "10001101";








    +            when 1397 => rom_word <= "10001101";








    +            when 1398 => rom_word <= "10101101";








    +            when 1399 => rom_word <= "10101101";








    +            when 1400 => rom_word <= "10101101";








    +            when 1401 => rom_word <= "11111101";








    +            when 1402 => rom_word <= "11011101";








    +            when 1403 => rom_word <= "11011000";








    +            when 1410 => rom_word <= "10001101";








    +            when 1411 => rom_word <= "10001101";








    +            when 1412 => rom_word <= "11011000";








    +            when 1413 => rom_word <= "11111000";








    +            when 1414 => rom_word <= "01110000";








    +            when 1415 => rom_word <= "01110000";








    +            when 1416 => rom_word <= "11111000";








    +            when 1417 => rom_word <= "11011000";








    +            when 1418 => rom_word <= "10001101";








    +            when 1419 => rom_word <= "10001101";








    +            when 1426 => rom_word <= "10011001";








    +            when 1427 => rom_word <= "10011001";








    +            when 1428 => rom_word <= "10011001";








    +            when 1429 => rom_word <= "10011001";








    +            when 1430 => rom_word <= "11110000";








    +            when 1431 => rom_word <= "01100000";








    +            when 1432 => rom_word <= "01100000";








    +            when 1433 => rom_word <= "01100000";








    +            when 1434 => rom_word <= "01100000";








    +            when 1435 => rom_word <= "01100000";








    +            when 1442 => rom_word <= "11111101";








    +            when 1443 => rom_word <= "10000001";








    +            when 1444 => rom_word <= "10000001";








    +            when 1445 => rom_word <= "11000000";








    +            when 1446 => rom_word <= "01100000";








    +            when 1447 => rom_word <= "00110000";








    +            when 1448 => rom_word <= "00011000";








    +            when 1449 => rom_word <= "00001100";








    +            when 1450 => rom_word <= "00001100";








    +            when 1451 => rom_word <= "11111101";








    +            when 1458 => rom_word <= "11110000";








    +            when 1459 => rom_word <= "00110000";








    +            when 1460 => rom_word <= "00110000";








    +            when 1461 => rom_word <= "00110000";








    +            when 1462 => rom_word <= "00110000";








    +            when 1463 => rom_word <= "00110000";








    +            when 1464 => rom_word <= "00110000";








    +            when 1465 => rom_word <= "00110000";








    +            when 1466 => rom_word <= "00110000";








    +            when 1467 => rom_word <= "11110000";








    +            when 1475 => rom_word <= "00000100";








    +            when 1476 => rom_word <= "00001100";








    +            when 1477 => rom_word <= "00011100";








    +            when 1478 => rom_word <= "00111000";








    +            when 1479 => rom_word <= "01110000";








    +            when 1480 => rom_word <= "11100000";








    +            when 1481 => rom_word <= "11000001";








    +            when 1482 => rom_word <= "10000001";








    +            when 1483 => rom_word <= "00000001";








    +            when 1490 => rom_word <= "11110000";








    +            when 1491 => rom_word <= "11000000";








    +            when 1492 => rom_word <= "11000000";








    +            when 1493 => rom_word <= "11000000";








    +            when 1494 => rom_word <= "11000000";








    +            when 1495 => rom_word <= "11000000";








    +            when 1496 => rom_word <= "11000000";








    +            when 1497 => rom_word <= "11000000";








    +            when 1498 => rom_word <= "11000000";








    +            when 1499 => rom_word <= "11110000";








    +            when 1504 => rom_word <= "00100000";








    +            when 1505 => rom_word <= "01110000";








    +            when 1506 => rom_word <= "11011000";








    +            when 1507 => rom_word <= "10001101";








    +            when 1533 => rom_word <= "11111111";








    +            when 1537 => rom_word <= "00110000";








    +            when 1538 => rom_word <= "01100000";








    +            when 1539 => rom_word <= "11000000";








    +            when 1557 => rom_word <= "01111000";








    +            when 1558 => rom_word <= "11000000";








    +            when 1559 => rom_word <= "11111000";








    +            when 1560 => rom_word <= "11001100";








    +            when 1561 => rom_word <= "11001100";








    +            when 1562 => rom_word <= "11001100";








    +            when 1563 => rom_word <= "10111001";








    +            when 1570 => rom_word <= "00001100";








    +            when 1571 => rom_word <= "00001100";








    +            when 1572 => rom_word <= "00001100";








    +            when 1573 => rom_word <= "01111100";








    +            when 1574 => rom_word <= "11001100";








    +            when 1575 => rom_word <= "11001100";








    +            when 1576 => rom_word <= "11001100";








    +            when 1577 => rom_word <= "11001100";








    +            when 1578 => rom_word <= "11001100";








    +            when 1579 => rom_word <= "01111100";








    +            when 1589 => rom_word <= "01111000";








    +            when 1590 => rom_word <= "10001100";








    +            when 1591 => rom_word <= "00001100";








    +            when 1592 => rom_word <= "00001100";








    +            when 1593 => rom_word <= "00001100";








    +            when 1594 => rom_word <= "10001100";








    +            when 1595 => rom_word <= "01111000";








    +            when 1602 => rom_word <= "11000000";








    +            when 1603 => rom_word <= "11000000";








    +            when 1604 => rom_word <= "11000000";








    +            when 1605 => rom_word <= "11111000";








    +            when 1606 => rom_word <= "11001100";








    +            when 1607 => rom_word <= "11001100";








    +            when 1608 => rom_word <= "11001100";








    +            when 1609 => rom_word <= "11001100";








    +            when 1610 => rom_word <= "11001100";








    +            when 1611 => rom_word <= "11111000";








    +            when 1621 => rom_word <= "11111000";








    +            when 1622 => rom_word <= "10001101";








    +            when 1623 => rom_word <= "11111101";








    +            when 1624 => rom_word <= "00001100";








    +            when 1625 => rom_word <= "00001100";








    +            when 1626 => rom_word <= "00001101";








    +            when 1627 => rom_word <= "11111000";








    +            when 1634 => rom_word <= "11100000";








    +            when 1635 => rom_word <= "10110001";








    +            when 1636 => rom_word <= "00110001";








    +            when 1637 => rom_word <= "00110000";








    +            when 1638 => rom_word <= "01111000";








    +            when 1639 => rom_word <= "00110000";








    +            when 1640 => rom_word <= "00110000";








    +            when 1641 => rom_word <= "00110000";








    +            when 1642 => rom_word <= "00110000";








    +            when 1643 => rom_word <= "00110000";








    +            when 1653 => rom_word <= "11111000";








    +            when 1654 => rom_word <= "11001100";








    +            when 1655 => rom_word <= "11001100";








    +            when 1656 => rom_word <= "11001100";








    +            when 1657 => rom_word <= "11001100";








    +            when 1658 => rom_word <= "11001100";








    +            when 1659 => rom_word <= "11111000";








    +            when 1660 => rom_word <= "11000000";








    +            when 1661 => rom_word <= "11000100";








    +            when 1662 => rom_word <= "01111000";








    +            when 1666 => rom_word <= "00001100";








    +            when 1667 => rom_word <= "00001100";








    +            when 1668 => rom_word <= "00001100";








    +            when 1669 => rom_word <= "01101100";








    +            when 1670 => rom_word <= "11011100";








    +            when 1671 => rom_word <= "11001100";








    +            when 1672 => rom_word <= "11001100";








    +            when 1673 => rom_word <= "11001100";








    +            when 1674 => rom_word <= "11001100";








    +            when 1675 => rom_word <= "11001100";








    +            when 1682 => rom_word <= "01100000";








    +            when 1683 => rom_word <= "01100000";








    +            when 1685 => rom_word <= "01110000";








    +            when 1686 => rom_word <= "01100000";








    +            when 1687 => rom_word <= "01100000";








    +            when 1688 => rom_word <= "01100000";








    +            when 1689 => rom_word <= "01100000";








    +            when 1690 => rom_word <= "01100000";








    +            when 1691 => rom_word <= "01100000";








    +            when 1698 => rom_word <= "11000000";








    +            when 1699 => rom_word <= "11000000";








    +            when 1701 => rom_word <= "11000000";








    +            when 1702 => rom_word <= "11000000";








    +            when 1703 => rom_word <= "11000000";








    +            when 1704 => rom_word <= "11000000";








    +            when 1705 => rom_word <= "11000000";








    +            when 1706 => rom_word <= "11000000";








    +            when 1707 => rom_word <= "11000000";








    +            when 1708 => rom_word <= "11001100";








    +            when 1709 => rom_word <= "11001100";








    +            when 1710 => rom_word <= "01111000";








    +            when 1714 => rom_word <= "00001100";








    +            when 1715 => rom_word <= "00001100";








    +            when 1716 => rom_word <= "00001100";








    +            when 1717 => rom_word <= "11001100";








    +            when 1718 => rom_word <= "01101100";








    +            when 1719 => rom_word <= "00111100";








    +            when 1720 => rom_word <= "00111100";








    +            when 1721 => rom_word <= "01101100";








    +            when 1722 => rom_word <= "11001100";








    +            when 1723 => rom_word <= "11001100";








    +            when 1730 => rom_word <= "01110000";








    +            when 1731 => rom_word <= "01100000";








    +            when 1732 => rom_word <= "01100000";








    +            when 1733 => rom_word <= "01100000";








    +            when 1734 => rom_word <= "01100000";








    +            when 1735 => rom_word <= "01100000";








    +            when 1736 => rom_word <= "01100000";








    +            when 1737 => rom_word <= "01100000";








    +            when 1738 => rom_word <= "01100000";








    +            when 1739 => rom_word <= "01100000";








    +            when 1749 => rom_word <= "11011100";








    +            when 1750 => rom_word <= "11111101";








    +            when 1751 => rom_word <= "10101101";








    +            when 1752 => rom_word <= "10101101";








    +            when 1753 => rom_word <= "10101101";








    +            when 1754 => rom_word <= "10101101";








    +            when 1755 => rom_word <= "10001101";








    +            when 1765 => rom_word <= "01110100";








    +            when 1766 => rom_word <= "11001100";








    +            when 1767 => rom_word <= "11001100";








    +            when 1768 => rom_word <= "11001100";








    +            when 1769 => rom_word <= "11001100";








    +            when 1770 => rom_word <= "11001100";








    +            when 1771 => rom_word <= "11001100";








    +            when 1781 => rom_word <= "01111000";








    +            when 1782 => rom_word <= "11001100";








    +            when 1783 => rom_word <= "11001100";








    +            when 1784 => rom_word <= "11001100";








    +            when 1785 => rom_word <= "11001100";








    +            when 1786 => rom_word <= "11001100";








    +            when 1787 => rom_word <= "01111000";








    +            when 1797 => rom_word <= "01111100";








    +            when 1798 => rom_word <= "11001100";








    +            when 1799 => rom_word <= "11001100";








    +            when 1800 => rom_word <= "11001100";








    +            when 1801 => rom_word <= "11001100";








    +            when 1802 => rom_word <= "11001100";








    +            when 1803 => rom_word <= "01111100";








    +            when 1804 => rom_word <= "00001100";








    +            when 1805 => rom_word <= "00001100";








    +            when 1806 => rom_word <= "00001100";








    +            when 1813 => rom_word <= "11111000";








    +            when 1814 => rom_word <= "11001100";








    +            when 1815 => rom_word <= "11001100";








    +            when 1816 => rom_word <= "11001100";








    +            when 1817 => rom_word <= "11001100";








    +            when 1818 => rom_word <= "11001100";








    +            when 1819 => rom_word <= "11111000";








    +            when 1820 => rom_word <= "11000000";








    +            when 1821 => rom_word <= "11000000";








    +            when 1822 => rom_word <= "11000000";








    +            when 1829 => rom_word <= "01110100";








    +            when 1830 => rom_word <= "11011100";








    +            when 1831 => rom_word <= "11001100";








    +            when 1832 => rom_word <= "00001100";








    +            when 1833 => rom_word <= "00001100";








    +            when 1834 => rom_word <= "00001100";








    +            when 1835 => rom_word <= "00001100";








    +            when 1845 => rom_word <= "11111000";








    +            when 1846 => rom_word <= "00001101";








    +            when 1847 => rom_word <= "00111000";








    +            when 1848 => rom_word <= "11100000";








    +            when 1849 => rom_word <= "10000001";








    +            when 1850 => rom_word <= "10000101";








    +            when 1851 => rom_word <= "11111000";








    +            when 1858 => rom_word <= "00110000";








    +            when 1859 => rom_word <= "00110000";








    +            when 1860 => rom_word <= "00110000";








    +            when 1861 => rom_word <= "11111100";








    +            when 1862 => rom_word <= "00110000";








    +            when 1863 => rom_word <= "00110000";








    +            when 1864 => rom_word <= "00110000";








    +            when 1865 => rom_word <= "00110000";








    +            when 1866 => rom_word <= "00110000";








    +            when 1867 => rom_word <= "00110000";








    +            when 1877 => rom_word <= "11001100";








    +            when 1878 => rom_word <= "11001100";








    +            when 1879 => rom_word <= "11001100";








    +            when 1880 => rom_word <= "11001100";








    +            when 1881 => rom_word <= "11001100";








    +            when 1882 => rom_word <= "11001100";








    +            when 1883 => rom_word <= "01111000";








    +            when 1893 => rom_word <= "10001101";








    +            when 1894 => rom_word <= "10001101";








    +            when 1895 => rom_word <= "10001101";








    +            when 1896 => rom_word <= "10001101";








    +            when 1897 => rom_word <= "10001101";








    +            when 1898 => rom_word <= "11011000";








    +            when 1899 => rom_word <= "00100000";








    +            when 1909 => rom_word <= "10001101";








    +            when 1910 => rom_word <= "10001101";








    +            when 1911 => rom_word <= "10101101";








    +            when 1912 => rom_word <= "10101101";








    +            when 1913 => rom_word <= "10101101";








    +            when 1914 => rom_word <= "11111101";








    +            when 1915 => rom_word <= "11011000";








    +            when 1925 => rom_word <= "10001101";








    +            when 1926 => rom_word <= "11011000";








    +            when 1927 => rom_word <= "01110000";








    +            when 1928 => rom_word <= "01110000";








    +            when 1929 => rom_word <= "01110000";








    +            when 1930 => rom_word <= "11011000";








    +            when 1931 => rom_word <= "10001101";








    +            when 1941 => rom_word <= "10001101";








    +            when 1942 => rom_word <= "10001101";








    +            when 1943 => rom_word <= "10001101";








    +            when 1944 => rom_word <= "10001101";








    +            when 1945 => rom_word <= "10001101";








    +            when 1946 => rom_word <= "11001101";








    +            when 1947 => rom_word <= "10111001";








    +            when 1948 => rom_word <= "10000001";








    +            when 1949 => rom_word <= "11000100";








    +            when 1950 => rom_word <= "01111000";








    +            when 1957 => rom_word <= "11111101";








    +            when 1958 => rom_word <= "11000000";








    +            when 1959 => rom_word <= "01100000";








    +            when 1960 => rom_word <= "00110000";








    +            when 1961 => rom_word <= "00011000";








    +            when 1962 => rom_word <= "00001100";








    +            when 1963 => rom_word <= "11111101";








    +            when 1970 => rom_word <= "11000001";








    +            when 1971 => rom_word <= "01100000";








    +            when 1972 => rom_word <= "01100000";








    +            when 1973 => rom_word <= "01100000";








    +            when 1974 => rom_word <= "00111000";








    +            when 1975 => rom_word <= "01100000";








    +            when 1976 => rom_word <= "01100000";








    +            when 1977 => rom_word <= "01100000";








    +            when 1978 => rom_word <= "01100000";








    +            when 1979 => rom_word <= "11000001";








    +            when 1986 => rom_word <= "01100000";








    +            when 1987 => rom_word <= "01100000";








    +            when 1988 => rom_word <= "01100000";








    +            when 1989 => rom_word <= "01100000";








    +            when 1990 => rom_word <= "01100000";








    +            when 1991 => rom_word <= "01100000";








    +            when 1992 => rom_word <= "01100000";








    +            when 1993 => rom_word <= "01100000";








    +            when 1994 => rom_word <= "01100000";








    +            when 1995 => rom_word <= "01100000";








    +            when 2002 => rom_word <= "00111000";








    +            when 2003 => rom_word <= "01100000";








    +            when 2004 => rom_word <= "01100000";








    +            when 2005 => rom_word <= "01100000";








    +            when 2006 => rom_word <= "11000001";








    +            when 2007 => rom_word <= "01100000";








    +            when 2008 => rom_word <= "01100000";








    +            when 2009 => rom_word <= "01100000";








    +            when 2010 => rom_word <= "01100000";








    +            when 2011 => rom_word <= "00111000";








    +            when 2017 => rom_word <= "10111001";








    +            when 2018 => rom_word <= "11101100";








    +            when 2036 => rom_word <= "00100000";








    +            when 2037 => rom_word <= "01110000";








    +            when 2038 => rom_word <= "11011000";








    +            when 2039 => rom_word <= "10001101";








    +            when 2040 => rom_word <= "10001101";








    +            when 2041 => rom_word <= "10001101";








    +            when 2042 => rom_word <= "11111101";








    +            when 2051 => rom_word <= "11110000";








    +            when 2052 => rom_word <= "10011001";








    +            when 2053 => rom_word <= "00001100";








    +            when 2054 => rom_word <= "00001100";








    +            when 2055 => rom_word <= "00001100";








    +            when 2056 => rom_word <= "10001101";








    +            when 2057 => rom_word <= "10011001";








    +            when 2058 => rom_word <= "11110000";








    +            when 2059 => rom_word <= "01100000";








    +            when 2060 => rom_word <= "11001100";








    +            when 2061 => rom_word <= "01110000";








    +            when 2066 => rom_word <= "11001100";








    +            when 2067 => rom_word <= "11001100";








    +            when 2069 => rom_word <= "11001100";








    +            when 2070 => rom_word <= "11001100";








    +            when 2071 => rom_word <= "11001100";








    +            when 2072 => rom_word <= "11001100";








    +            when 2073 => rom_word <= "11001100";








    +            when 2074 => rom_word <= "11001100";








    +            when 2075 => rom_word <= "01111000";








    +            when 2081 => rom_word <= "11000000";








    +            when 2082 => rom_word <= "01100000";








    +            when 2083 => rom_word <= "00110000";








    +            when 2085 => rom_word <= "11111000";








    +            when 2086 => rom_word <= "10001101";








    +            when 2087 => rom_word <= "11111101";








    +            when 2088 => rom_word <= "00001100";








    +            when 2089 => rom_word <= "00001100";








    +            when 2090 => rom_word <= "00001101";








    +            when 2091 => rom_word <= "11111000";








    +            when 2097 => rom_word <= "00100000";








    +            when 2098 => rom_word <= "01110000";








    +            when 2099 => rom_word <= "11011000";








    +            when 2101 => rom_word <= "01111000";








    +            when 2102 => rom_word <= "11000000";








    +            when 2103 => rom_word <= "11111000";








    +            when 2104 => rom_word <= "11001100";








    +            when 2105 => rom_word <= "11001100";








    +            when 2106 => rom_word <= "11001100";








    +            when 2107 => rom_word <= "10111001";








    +            when 2114 => rom_word <= "11001100";








    +            when 2117 => rom_word <= "01111000";








    +            when 2118 => rom_word <= "11000000";








    +            when 2119 => rom_word <= "11111000";








    +            when 2120 => rom_word <= "11001100";








    +            when 2121 => rom_word <= "11001100";








    +            when 2122 => rom_word <= "11001100";








    +            when 2123 => rom_word <= "10111001";








    +            when 2129 => rom_word <= "00011000";








    +            when 2130 => rom_word <= "00110000";








    +            when 2131 => rom_word <= "01100000";








    +            when 2133 => rom_word <= "01111000";








    +            when 2134 => rom_word <= "11000000";








    +            when 2135 => rom_word <= "11111000";








    +            when 2136 => rom_word <= "11001100";








    +            when 2137 => rom_word <= "11001100";








    +            when 2138 => rom_word <= "11001100";








    +            when 2139 => rom_word <= "10111001";








    +            when 2145 => rom_word <= "01110000";








    +            when 2146 => rom_word <= "11011000";








    +            when 2147 => rom_word <= "01110000";








    +            when 2149 => rom_word <= "01111000";








    +            when 2150 => rom_word <= "11000000";








    +            when 2151 => rom_word <= "11111000";








    +            when 2152 => rom_word <= "11001100";








    +            when 2153 => rom_word <= "11001100";








    +            when 2154 => rom_word <= "11001100";








    +            when 2155 => rom_word <= "10111001";








    +            when 2165 => rom_word <= "11111000";








    +            when 2166 => rom_word <= "10001101";








    +            when 2167 => rom_word <= "00001100";








    +            when 2168 => rom_word <= "00001100";








    +            when 2169 => rom_word <= "00001100";








    +            when 2170 => rom_word <= "10001101";








    +            when 2171 => rom_word <= "11111000";








    +            when 2172 => rom_word <= "01100000";








    +            when 2173 => rom_word <= "00111000";








    +            when 2177 => rom_word <= "00100000";








    +            when 2178 => rom_word <= "01110000";








    +            when 2179 => rom_word <= "11011000";








    +            when 2181 => rom_word <= "11111000";








    +            when 2182 => rom_word <= "10001101";








    +            when 2183 => rom_word <= "11111101";








    +            when 2184 => rom_word <= "00001100";








    +            when 2185 => rom_word <= "00001100";








    +            when 2186 => rom_word <= "00001101";








    +            when 2187 => rom_word <= "11111000";








    +            when 2194 => rom_word <= "10001101";








    +            when 2197 => rom_word <= "11111000";








    +            when 2198 => rom_word <= "10001101";








    +            when 2199 => rom_word <= "11111101";








    +            when 2200 => rom_word <= "00001100";








    +            when 2201 => rom_word <= "00001100";








    +            when 2202 => rom_word <= "00001101";








    +            when 2203 => rom_word <= "11111000";








    +            when 2209 => rom_word <= "00011000";








    +            when 2210 => rom_word <= "00110000";








    +            when 2211 => rom_word <= "01100000";








    +            when 2213 => rom_word <= "11111000";








    +            when 2214 => rom_word <= "10001101";








    +            when 2215 => rom_word <= "11111101";








    +            when 2216 => rom_word <= "00001100";








    +            when 2217 => rom_word <= "00001100";








    +            when 2218 => rom_word <= "00001101";








    +            when 2219 => rom_word <= "11111000";








    +            when 2226 => rom_word <= "10011001";








    +            when 2229 => rom_word <= "01110000";








    +            when 2230 => rom_word <= "01100000";








    +            when 2231 => rom_word <= "01100000";








    +            when 2232 => rom_word <= "01100000";








    +            when 2233 => rom_word <= "01100000";








    +            when 2234 => rom_word <= "01100000";








    +            when 2235 => rom_word <= "01100000";








    +            when 2241 => rom_word <= "01100000";








    +            when 2242 => rom_word <= "11110000";








    +            when 2243 => rom_word <= "10011001";








    +            when 2245 => rom_word <= "01110000";








    +            when 2246 => rom_word <= "01100000";








    +            when 2247 => rom_word <= "01100000";








    +            when 2248 => rom_word <= "01100000";








    +            when 2249 => rom_word <= "01100000";








    +            when 2250 => rom_word <= "01100000";








    +            when 2251 => rom_word <= "01100000";








    +            when 2257 => rom_word <= "00011000";








    +            when 2258 => rom_word <= "00110000";








    +            when 2259 => rom_word <= "01100000";








    +            when 2261 => rom_word <= "01110000";








    +            when 2262 => rom_word <= "01100000";








    +            when 2263 => rom_word <= "01100000";








    +            when 2264 => rom_word <= "01100000";








    +            when 2265 => rom_word <= "01100000";








    +            when 2266 => rom_word <= "01100000";








    +            when 2267 => rom_word <= "01100000";








    +            when 2273 => rom_word <= "10001101";








    +            when 2275 => rom_word <= "00100000";








    +            when 2276 => rom_word <= "01110000";








    +            when 2277 => rom_word <= "11011000";








    +            when 2278 => rom_word <= "10001101";








    +            when 2279 => rom_word <= "10001101";








    +            when 2280 => rom_word <= "11111101";








    +            when 2281 => rom_word <= "10001101";








    +            when 2282 => rom_word <= "10001101";








    +            when 2283 => rom_word <= "10001101";








    +            when 2288 => rom_word <= "01110000";








    +            when 2289 => rom_word <= "11011000";








    +            when 2290 => rom_word <= "01110000";








    +            when 2291 => rom_word <= "00100000";








    +            when 2292 => rom_word <= "01110000";








    +            when 2293 => rom_word <= "11011000";








    +            when 2294 => rom_word <= "10001101";








    +            when 2295 => rom_word <= "11111101";








    +            when 2296 => rom_word <= "10001101";








    +            when 2297 => rom_word <= "10001101";








    +            when 2298 => rom_word <= "10001101";








    +            when 2299 => rom_word <= "10001101";








    +            when 2304 => rom_word <= "01100000";








    +            when 2305 => rom_word <= "00110000";








    +            when 2307 => rom_word <= "11111100";








    +            when 2308 => rom_word <= "00001100";








    +            when 2309 => rom_word <= "00001100";








    +            when 2310 => rom_word <= "00001100";








    +            when 2311 => rom_word <= "00111100";








    +            when 2312 => rom_word <= "00001100";








    +            when 2313 => rom_word <= "00001100";








    +            when 2314 => rom_word <= "00001100";








    +            when 2315 => rom_word <= "11111100";








    +            when 2325 => rom_word <= "11011100";








    +            when 2326 => rom_word <= "10110001";








    +            when 2327 => rom_word <= "10110001";








    +            when 2328 => rom_word <= "11111001";








    +            when 2329 => rom_word <= "01101100";








    +            when 2330 => rom_word <= "01101100";








    +            when 2331 => rom_word <= "11011001";








    +            when 2338 => rom_word <= "11110001";








    +            when 2339 => rom_word <= "11011000";








    +            when 2340 => rom_word <= "11001100";








    +            when 2341 => rom_word <= "11001100";








    +            when 2342 => rom_word <= "11111101";








    +            when 2343 => rom_word <= "11001100";








    +            when 2344 => rom_word <= "11001100";








    +            when 2345 => rom_word <= "11001100";








    +            when 2346 => rom_word <= "11001100";








    +            when 2347 => rom_word <= "11001101";








    +            when 2353 => rom_word <= "00100000";








    +            when 2354 => rom_word <= "01110000";








    +            when 2355 => rom_word <= "11011000";








    +            when 2357 => rom_word <= "11111000";








    +            when 2358 => rom_word <= "10001101";








    +            when 2359 => rom_word <= "10001101";








    +            when 2360 => rom_word <= "10001101";








    +            when 2361 => rom_word <= "10001101";








    +            when 2362 => rom_word <= "10001101";








    +            when 2363 => rom_word <= "11111000";








    +            when 2370 => rom_word <= "10001101";








    +            when 2373 => rom_word <= "11111000";








    +            when 2374 => rom_word <= "10001101";








    +            when 2375 => rom_word <= "10001101";








    +            when 2376 => rom_word <= "10001101";








    +            when 2377 => rom_word <= "10001101";








    +            when 2378 => rom_word <= "10001101";








    +            when 2379 => rom_word <= "11111000";








    +            when 2385 => rom_word <= "00011000";








    +            when 2386 => rom_word <= "00110000";








    +            when 2387 => rom_word <= "01100000";








    +            when 2389 => rom_word <= "11111000";








    +            when 2390 => rom_word <= "10001101";








    +            when 2391 => rom_word <= "10001101";








    +            when 2392 => rom_word <= "10001101";








    +            when 2393 => rom_word <= "10001101";








    +            when 2394 => rom_word <= "10001101";








    +            when 2395 => rom_word <= "11111000";








    +            when 2401 => rom_word <= "00110000";








    +            when 2402 => rom_word <= "01111000";








    +            when 2403 => rom_word <= "11001100";








    +            when 2405 => rom_word <= "11001100";








    +            when 2406 => rom_word <= "11001100";








    +            when 2407 => rom_word <= "11001100";








    +            when 2408 => rom_word <= "11001100";








    +            when 2409 => rom_word <= "11001100";








    +            when 2410 => rom_word <= "11001100";








    +            when 2411 => rom_word <= "01111000";








    +            when 2417 => rom_word <= "00011000";








    +            when 2418 => rom_word <= "00110000";








    +            when 2419 => rom_word <= "01100000";








    +            when 2421 => rom_word <= "11001100";








    +            when 2422 => rom_word <= "11001100";








    +            when 2423 => rom_word <= "11001100";








    +            when 2424 => rom_word <= "11001100";








    +            when 2425 => rom_word <= "11001100";








    +            when 2426 => rom_word <= "11001100";








    +            when 2427 => rom_word <= "01111000";








    +            when 2434 => rom_word <= "10001101";








    +            when 2437 => rom_word <= "10001101";








    +            when 2438 => rom_word <= "10001101";








    +            when 2439 => rom_word <= "10001101";








    +            when 2440 => rom_word <= "10001101";








    +            when 2441 => rom_word <= "10001101";








    +            when 2442 => rom_word <= "11001101";








    +            when 2443 => rom_word <= "10111001";








    +            when 2444 => rom_word <= "10000001";








    +            when 2445 => rom_word <= "11000100";








    +            when 2446 => rom_word <= "01111000";








    +            when 2449 => rom_word <= "10001101";








    +            when 2451 => rom_word <= "11111000";








    +            when 2452 => rom_word <= "10001101";








    +            when 2453 => rom_word <= "10001101";








    +            when 2454 => rom_word <= "10001101";








    +            when 2455 => rom_word <= "10001101";








    +            when 2456 => rom_word <= "10001101";








    +            when 2457 => rom_word <= "10001101";








    +            when 2458 => rom_word <= "10001101";








    +            when 2459 => rom_word <= "11111000";








    +            when 2465 => rom_word <= "10001101";








    +            when 2467 => rom_word <= "10001101";








    +            when 2468 => rom_word <= "10001101";








    +            when 2469 => rom_word <= "10001101";








    +            when 2470 => rom_word <= "10001101";








    +            when 2471 => rom_word <= "10001101";








    +            when 2472 => rom_word <= "10001101";








    +            when 2473 => rom_word <= "10001101";








    +            when 2474 => rom_word <= "10001101";








    +            when 2475 => rom_word <= "11111000";








    +            when 2481 => rom_word <= "01100000";








    +            when 2482 => rom_word <= "01100000";








    +            when 2483 => rom_word <= "11111000";








    +            when 2484 => rom_word <= "10001101";








    +            when 2485 => rom_word <= "00001100";








    +            when 2486 => rom_word <= "00001100";








    +            when 2487 => rom_word <= "00001100";








    +            when 2488 => rom_word <= "10001101";








    +            when 2489 => rom_word <= "11111000";








    +            when 2490 => rom_word <= "01100000";








    +            when 2491 => rom_word <= "01100000";








    +            when 2497 => rom_word <= "11110000";








    +            when 2498 => rom_word <= "00001001";








    +            when 2499 => rom_word <= "01100110";








    +            when 2500 => rom_word <= "10010110";








    +            when 2501 => rom_word <= "10010110";








    +            when 2502 => rom_word <= "00010110";








    +            when 2503 => rom_word <= "00010110";








    +            when 2504 => rom_word <= "10010110";








    +            when 2505 => rom_word <= "10010110";








    +            when 2506 => rom_word <= "01110110";








    +            when 2507 => rom_word <= "00001001";








    +            when 2508 => rom_word <= "11110000";








    +            when 2513 => rom_word <= "11110000";








    +            when 2514 => rom_word <= "00001001";








    +            when 2515 => rom_word <= "01110110";








    +            when 2516 => rom_word <= "10010110";








    +            when 2517 => rom_word <= "10010110";








    +            when 2518 => rom_word <= "01110110";








    +            when 2519 => rom_word <= "00110110";








    +            when 2520 => rom_word <= "01010110";








    +            when 2521 => rom_word <= "10010110";








    +            when 2522 => rom_word <= "10010110";








    +            when 2523 => rom_word <= "00001001";








    +            when 2524 => rom_word <= "11110000";








    +            when 2529 => rom_word <= "01111100";








    +            when 2530 => rom_word <= "11001100";








    +            when 2531 => rom_word <= "11001100";








    +            when 2532 => rom_word <= "01111100";








    +            when 2533 => rom_word <= "10001100";








    +            when 2534 => rom_word <= "11001100";








    +            when 2535 => rom_word <= "11101101";








    +            when 2536 => rom_word <= "11001100";








    +            when 2537 => rom_word <= "11001100";








    +            when 2538 => rom_word <= "11001100";








    +            when 2539 => rom_word <= "10001101";








    +            when 2545 => rom_word <= "11000001";








    +            when 2546 => rom_word <= "01100011";








    +            when 2547 => rom_word <= "01100000";








    +            when 2548 => rom_word <= "01100000";








    +            when 2549 => rom_word <= "01100000";








    +            when 2550 => rom_word <= "11111001";








    +            when 2551 => rom_word <= "01100000";








    +            when 2552 => rom_word <= "01100000";








    +            when 2553 => rom_word <= "01100000";








    +            when 2554 => rom_word <= "01101100";








    +            when 2555 => rom_word <= "00111000";








    +            when 2561 => rom_word <= "01100000";








    +            when 2562 => rom_word <= "00110000";








    +            when 2563 => rom_word <= "00011000";








    +            when 2565 => rom_word <= "01111000";








    +            when 2566 => rom_word <= "11000000";








    +            when 2567 => rom_word <= "11111000";








    +            when 2568 => rom_word <= "11001100";








    +            when 2569 => rom_word <= "11001100";








    +            when 2570 => rom_word <= "11001100";








    +            when 2571 => rom_word <= "10111001";








    +            when 2577 => rom_word <= "11000000";








    +            when 2578 => rom_word <= "01100000";








    +            when 2579 => rom_word <= "00110000";








    +            when 2581 => rom_word <= "01110000";








    +            when 2582 => rom_word <= "01100000";








    +            when 2583 => rom_word <= "01100000";








    +            when 2584 => rom_word <= "01100000";








    +            when 2585 => rom_word <= "01100000";








    +            when 2586 => rom_word <= "01100000";








    +            when 2587 => rom_word <= "01100000";








    +            when 2593 => rom_word <= "01100000";








    +            when 2594 => rom_word <= "00110000";








    +            when 2595 => rom_word <= "00011000";








    +            when 2597 => rom_word <= "11111000";








    +            when 2598 => rom_word <= "10001101";








    +            when 2599 => rom_word <= "10001101";








    +            when 2600 => rom_word <= "10001101";








    +            when 2601 => rom_word <= "10001101";








    +            when 2602 => rom_word <= "10001101";








    +            when 2603 => rom_word <= "11111000";








    +            when 2609 => rom_word <= "01100000";








    +            when 2610 => rom_word <= "00110000";








    +            when 2611 => rom_word <= "00011000";








    +            when 2613 => rom_word <= "11001100";








    +            when 2614 => rom_word <= "11001100";








    +            when 2615 => rom_word <= "11001100";








    +            when 2616 => rom_word <= "11001100";








    +            when 2617 => rom_word <= "11001100";








    +            when 2618 => rom_word <= "11001100";








    +            when 2619 => rom_word <= "01111000";








    +            when 2626 => rom_word <= "10111001";








    +            when 2627 => rom_word <= "11101100";








    +            when 2629 => rom_word <= "11101000";








    +            when 2630 => rom_word <= "10011001";








    +            when 2631 => rom_word <= "10011001";








    +            when 2632 => rom_word <= "10011001";








    +            when 2633 => rom_word <= "10011001";








    +            when 2634 => rom_word <= "10011001";








    +            when 2635 => rom_word <= "10011001";








    +            when 2640 => rom_word <= "10111001";








    +            when 2641 => rom_word <= "11101100";








    +            when 2643 => rom_word <= "10001101";








    +            when 2644 => rom_word <= "10011101";








    +            when 2645 => rom_word <= "10111101";








    +            when 2646 => rom_word <= "11111101";








    +            when 2647 => rom_word <= "11101101";








    +            when 2648 => rom_word <= "11001101";








    +            when 2649 => rom_word <= "10001101";








    +            when 2650 => rom_word <= "10001101";








    +            when 2651 => rom_word <= "10001101";








    +            when 2658 => rom_word <= "11110000";








    +            when 2659 => rom_word <= "11011000";








    +            when 2660 => rom_word <= "11011000";








    +            when 2661 => rom_word <= "11110001";








    +            when 2663 => rom_word <= "11111001";








    +            when 2674 => rom_word <= "01110000";








    +            when 2675 => rom_word <= "11011000";








    +            when 2676 => rom_word <= "11011000";








    +            when 2677 => rom_word <= "01110000";








    +            when 2679 => rom_word <= "11111000";








    +            when 2690 => rom_word <= "00110000";








    +            when 2691 => rom_word <= "00110000";








    +            when 2693 => rom_word <= "00110000";








    +            when 2694 => rom_word <= "00110000";








    +            when 2695 => rom_word <= "00011000";








    +            when 2696 => rom_word <= "00001100";








    +            when 2697 => rom_word <= "10001101";








    +            when 2698 => rom_word <= "10001101";








    +            when 2699 => rom_word <= "11111000";








    +            when 2710 => rom_word <= "11111101";








    +            when 2711 => rom_word <= "00001100";








    +            when 2712 => rom_word <= "00001100";








    +            when 2713 => rom_word <= "00001100";








    +            when 2714 => rom_word <= "00001100";








    +            when 2726 => rom_word <= "11111101";








    +            when 2727 => rom_word <= "10000001";








    +            when 2728 => rom_word <= "10000001";








    +            when 2729 => rom_word <= "10000001";








    +            when 2730 => rom_word <= "10000001";








    +            when 2737 => rom_word <= "00011000";








    +            when 2738 => rom_word <= "00011100";








    +            when 2739 => rom_word <= "00011001";








    +            when 2740 => rom_word <= "10011001";








    +            when 2741 => rom_word <= "11011000";








    +            when 2742 => rom_word <= "01100000";








    +            when 2743 => rom_word <= "00110000";








    +            when 2744 => rom_word <= "00011000";








    +            when 2745 => rom_word <= "11101100";








    +            when 2746 => rom_word <= "10000101";








    +            when 2747 => rom_word <= "11000000";








    +            when 2748 => rom_word <= "01100000";








    +            when 2749 => rom_word <= "11110001";








    +            when 2753 => rom_word <= "00011000";








    +            when 2754 => rom_word <= "00011100";








    +            when 2755 => rom_word <= "00011001";








    +            when 2756 => rom_word <= "10011001";








    +            when 2757 => rom_word <= "11011000";








    +            when 2758 => rom_word <= "01100000";








    +            when 2759 => rom_word <= "00110000";








    +            when 2760 => rom_word <= "10011001";








    +            when 2761 => rom_word <= "11001101";








    +            when 2762 => rom_word <= "01100101";








    +            when 2763 => rom_word <= "11110011";








    +            when 2764 => rom_word <= "10000001";








    +            when 2765 => rom_word <= "10000001";








    +            when 2770 => rom_word <= "01100000";








    +            when 2771 => rom_word <= "01100000";








    +            when 2773 => rom_word <= "01100000";








    +            when 2774 => rom_word <= "01100000";








    +            when 2775 => rom_word <= "01100000";








    +            when 2776 => rom_word <= "11110000";








    +            when 2777 => rom_word <= "11110000";








    +            when 2778 => rom_word <= "11110000";








    +            when 2779 => rom_word <= "01100000";








    +            when 2789 => rom_word <= "10110001";








    +            when 2790 => rom_word <= "11011000";








    +            when 2791 => rom_word <= "01101100";








    +            when 2792 => rom_word <= "11011000";








    +            when 2793 => rom_word <= "10110001";








    +            when 2805 => rom_word <= "01101100";








    +            when 2806 => rom_word <= "11011000";








    +            when 2807 => rom_word <= "10110001";








    +            when 2808 => rom_word <= "11011000";








    +            when 2809 => rom_word <= "01101100";








    +            when 2816 => rom_word <= "00100010";








    +            when 2817 => rom_word <= "10001000";








    +            when 2818 => rom_word <= "00100010";








    +            when 2819 => rom_word <= "10001000";








    +            when 2820 => rom_word <= "00100010";








    +            when 2821 => rom_word <= "10001000";








    +            when 2822 => rom_word <= "00100010";








    +            when 2823 => rom_word <= "10001000";








    +            when 2824 => rom_word <= "00100010";








    +            when 2825 => rom_word <= "10001000";








    +            when 2826 => rom_word <= "00100010";








    +            when 2827 => rom_word <= "10001000";








    +            when 2828 => rom_word <= "00100010";








    +            when 2829 => rom_word <= "10001000";








    +            when 2830 => rom_word <= "00100010";








    +            when 2831 => rom_word <= "10001000";








    +            when 2832 => rom_word <= "10101010";








    +            when 2833 => rom_word <= "01010101";








    +            when 2834 => rom_word <= "10101010";








    +            when 2835 => rom_word <= "01010101";








    +            when 2836 => rom_word <= "10101010";








    +            when 2837 => rom_word <= "01010101";








    +            when 2838 => rom_word <= "10101010";








    +            when 2839 => rom_word <= "01010101";








    +            when 2840 => rom_word <= "10101010";








    +            when 2841 => rom_word <= "01010101";








    +            when 2842 => rom_word <= "10101010";








    +            when 2843 => rom_word <= "01010101";








    +            when 2844 => rom_word <= "10101010";








    +            when 2845 => rom_word <= "01010101";








    +            when 2846 => rom_word <= "10101010";








    +            when 2847 => rom_word <= "01010101";








    +            when 2848 => rom_word <= "11101110";








    +            when 2849 => rom_word <= "10111011";








    +            when 2850 => rom_word <= "11101110";








    +            when 2851 => rom_word <= "10111011";








    +            when 2852 => rom_word <= "11101110";








    +            when 2853 => rom_word <= "10111011";








    +            when 2854 => rom_word <= "11101110";








    +            when 2855 => rom_word <= "10111011";








    +            when 2856 => rom_word <= "11101110";








    +            when 2857 => rom_word <= "10111011";








    +            when 2858 => rom_word <= "11101110";








    +            when 2859 => rom_word <= "10111011";








    +            when 2860 => rom_word <= "11101110";








    +            when 2861 => rom_word <= "10111011";








    +            when 2862 => rom_word <= "11101110";








    +            when 2863 => rom_word <= "10111011";








    +            when 2864 => rom_word <= "01100000";








    +            when 2865 => rom_word <= "01100000";








    +            when 2866 => rom_word <= "01100000";








    +            when 2867 => rom_word <= "01100000";








    +            when 2868 => rom_word <= "01100000";








    +            when 2869 => rom_word <= "01100000";








    +            when 2870 => rom_word <= "01100000";








    +            when 2871 => rom_word <= "01100000";








    +            when 2872 => rom_word <= "01100000";








    +            when 2873 => rom_word <= "01100000";








    +            when 2874 => rom_word <= "01100000";








    +            when 2875 => rom_word <= "01100000";








    +            when 2876 => rom_word <= "01100000";








    +            when 2877 => rom_word <= "01100000";








    +            when 2878 => rom_word <= "01100000";








    +            when 2879 => rom_word <= "01100000";








    +            when 2880 => rom_word <= "01100000";








    +            when 2881 => rom_word <= "01100000";








    +            when 2882 => rom_word <= "01100000";








    +            when 2883 => rom_word <= "01100000";








    +            when 2884 => rom_word <= "01100000";








    +            when 2885 => rom_word <= "01100000";








    +            when 2886 => rom_word <= "01100000";








    +            when 2887 => rom_word <= "01111100";








    +            when 2888 => rom_word <= "01100000";








    +            when 2889 => rom_word <= "01100000";








    +            when 2890 => rom_word <= "01100000";








    +            when 2891 => rom_word <= "01100000";








    +            when 2892 => rom_word <= "01100000";








    +            when 2893 => rom_word <= "01100000";








    +            when 2894 => rom_word <= "01100000";








    +            when 2895 => rom_word <= "01100000";








    +            when 2896 => rom_word <= "01100000";








    +            when 2897 => rom_word <= "01100000";








    +            when 2898 => rom_word <= "01100000";








    +            when 2899 => rom_word <= "01100000";








    +            when 2900 => rom_word <= "01100000";








    +            when 2901 => rom_word <= "01111100";








    +            when 2902 => rom_word <= "01100000";








    +            when 2903 => rom_word <= "01111100";








    +            when 2904 => rom_word <= "01100000";








    +            when 2905 => rom_word <= "01100000";








    +            when 2906 => rom_word <= "01100000";








    +            when 2907 => rom_word <= "01100000";








    +            when 2908 => rom_word <= "01100000";








    +            when 2909 => rom_word <= "01100000";








    +            when 2910 => rom_word <= "01100000";








    +            when 2911 => rom_word <= "01100000";








    +            when 2912 => rom_word <= "10110001";








    +            when 2913 => rom_word <= "10110001";








    +            when 2914 => rom_word <= "10110001";








    +            when 2915 => rom_word <= "10110001";








    +            when 2916 => rom_word <= "10110001";








    +            when 2917 => rom_word <= "10110001";








    +            when 2918 => rom_word <= "10110001";








    +            when 2919 => rom_word <= "10111101";








    +            when 2920 => rom_word <= "10110001";








    +            when 2921 => rom_word <= "10110001";








    +            when 2922 => rom_word <= "10110001";








    +            when 2923 => rom_word <= "10110001";








    +            when 2924 => rom_word <= "10110001";








    +            when 2925 => rom_word <= "10110001";








    +            when 2926 => rom_word <= "10110001";








    +            when 2927 => rom_word <= "10110001";








    +            when 2935 => rom_word <= "11111101";








    +            when 2936 => rom_word <= "10110001";








    +            when 2937 => rom_word <= "10110001";








    +            when 2938 => rom_word <= "10110001";








    +            when 2939 => rom_word <= "10110001";








    +            when 2940 => rom_word <= "10110001";








    +            when 2941 => rom_word <= "10110001";








    +            when 2942 => rom_word <= "10110001";








    +            when 2943 => rom_word <= "10110001";








    +            when 2949 => rom_word <= "01111100";








    +            when 2950 => rom_word <= "01100000";








    +            when 2951 => rom_word <= "01111100";








    +            when 2952 => rom_word <= "01100000";








    +            when 2953 => rom_word <= "01100000";








    +            when 2954 => rom_word <= "01100000";








    +            when 2955 => rom_word <= "01100000";








    +            when 2956 => rom_word <= "01100000";








    +            when 2957 => rom_word <= "01100000";








    +            when 2958 => rom_word <= "01100000";








    +            when 2959 => rom_word <= "01100000";








    +            when 2960 => rom_word <= "10110001";








    +            when 2961 => rom_word <= "10110001";








    +            when 2962 => rom_word <= "10110001";








    +            when 2963 => rom_word <= "10110001";








    +            when 2964 => rom_word <= "10110001";








    +            when 2965 => rom_word <= "10111101";








    +            when 2966 => rom_word <= "10000001";








    +            when 2967 => rom_word <= "10111101";








    +            when 2968 => rom_word <= "10110001";








    +            when 2969 => rom_word <= "10110001";








    +            when 2970 => rom_word <= "10110001";








    +            when 2971 => rom_word <= "10110001";








    +            when 2972 => rom_word <= "10110001";








    +            when 2973 => rom_word <= "10110001";








    +            when 2974 => rom_word <= "10110001";








    +            when 2975 => rom_word <= "10110001";








    +            when 2976 => rom_word <= "10110001";








    +            when 2977 => rom_word <= "10110001";








    +            when 2978 => rom_word <= "10110001";








    +            when 2979 => rom_word <= "10110001";








    +            when 2980 => rom_word <= "10110001";








    +            when 2981 => rom_word <= "10110001";








    +            when 2982 => rom_word <= "10110001";








    +            when 2983 => rom_word <= "10110001";








    +            when 2984 => rom_word <= "10110001";








    +            when 2985 => rom_word <= "10110001";








    +            when 2986 => rom_word <= "10110001";








    +            when 2987 => rom_word <= "10110001";








    +            when 2988 => rom_word <= "10110001";








    +            when 2989 => rom_word <= "10110001";








    +            when 2990 => rom_word <= "10110001";








    +            when 2991 => rom_word <= "10110001";








    +            when 2997 => rom_word <= "11111101";








    +            when 2998 => rom_word <= "10000001";








    +            when 2999 => rom_word <= "10111101";








    +            when 3000 => rom_word <= "10110001";








    +            when 3001 => rom_word <= "10110001";








    +            when 3002 => rom_word <= "10110001";








    +            when 3003 => rom_word <= "10110001";








    +            when 3004 => rom_word <= "10110001";








    +            when 3005 => rom_word <= "10110001";








    +            when 3006 => rom_word <= "10110001";








    +            when 3007 => rom_word <= "10110001";








    +            when 3008 => rom_word <= "10110001";








    +            when 3009 => rom_word <= "10110001";








    +            when 3010 => rom_word <= "10110001";








    +            when 3011 => rom_word <= "10110001";








    +            when 3012 => rom_word <= "10110001";








    +            when 3013 => rom_word <= "10111101";








    +            when 3014 => rom_word <= "10000001";








    +            when 3015 => rom_word <= "11111101";








    +            when 3024 => rom_word <= "10110001";








    +            when 3025 => rom_word <= "10110001";








    +            when 3026 => rom_word <= "10110001";








    +            when 3027 => rom_word <= "10110001";








    +            when 3028 => rom_word <= "10110001";








    +            when 3029 => rom_word <= "10110001";








    +            when 3030 => rom_word <= "10110001";








    +            when 3031 => rom_word <= "11111101";








    +            when 3040 => rom_word <= "01100000";








    +            when 3041 => rom_word <= "01100000";








    +            when 3042 => rom_word <= "01100000";








    +            when 3043 => rom_word <= "01100000";








    +            when 3044 => rom_word <= "01100000";








    +            when 3045 => rom_word <= "01111100";








    +            when 3046 => rom_word <= "01100000";








    +            when 3047 => rom_word <= "01111100";








    +            when 3063 => rom_word <= "01111100";








    +            when 3064 => rom_word <= "01100000";








    +            when 3065 => rom_word <= "01100000";








    +            when 3066 => rom_word <= "01100000";








    +            when 3067 => rom_word <= "01100000";








    +            when 3068 => rom_word <= "01100000";








    +            when 3069 => rom_word <= "01100000";








    +            when 3070 => rom_word <= "01100000";








    +            when 3071 => rom_word <= "01100000";








    +            when 3072 => rom_word <= "01100000";








    +            when 3073 => rom_word <= "01100000";








    +            when 3074 => rom_word <= "01100000";








    +            when 3075 => rom_word <= "01100000";








    +            when 3076 => rom_word <= "01100000";








    +            when 3077 => rom_word <= "01100000";








    +            when 3078 => rom_word <= "01100000";








    +            when 3079 => rom_word <= "11100011";








    +            when 3088 => rom_word <= "01100000";








    +            when 3089 => rom_word <= "01100000";








    +            when 3090 => rom_word <= "01100000";








    +            when 3091 => rom_word <= "01100000";








    +            when 3092 => rom_word <= "01100000";








    +            when 3093 => rom_word <= "01100000";








    +            when 3094 => rom_word <= "01100000";








    +            when 3095 => rom_word <= "11111111";








    +            when 3111 => rom_word <= "11111111";








    +            when 3112 => rom_word <= "01100000";








    +            when 3113 => rom_word <= "01100000";








    +            when 3114 => rom_word <= "01100000";








    +            when 3115 => rom_word <= "01100000";








    +            when 3116 => rom_word <= "01100000";








    +            when 3117 => rom_word <= "01100000";








    +            when 3118 => rom_word <= "01100000";








    +            when 3119 => rom_word <= "01100000";








    +            when 3120 => rom_word <= "01100000";








    +            when 3121 => rom_word <= "01100000";








    +            when 3122 => rom_word <= "01100000";








    +            when 3123 => rom_word <= "01100000";








    +            when 3124 => rom_word <= "01100000";








    +            when 3125 => rom_word <= "01100000";








    +            when 3126 => rom_word <= "01100000";








    +            when 3127 => rom_word <= "11100011";








    +            when 3128 => rom_word <= "01100000";








    +            when 3129 => rom_word <= "01100000";








    +            when 3130 => rom_word <= "01100000";








    +            when 3131 => rom_word <= "01100000";








    +            when 3132 => rom_word <= "01100000";








    +            when 3133 => rom_word <= "01100000";








    +            when 3134 => rom_word <= "01100000";








    +            when 3135 => rom_word <= "01100000";








    +            when 3143 => rom_word <= "11111111";








    +            when 3152 => rom_word <= "01100000";








    +            when 3153 => rom_word <= "01100000";








    +            when 3154 => rom_word <= "01100000";








    +            when 3155 => rom_word <= "01100000";








    +            when 3156 => rom_word <= "01100000";








    +            when 3157 => rom_word <= "01100000";








    +            when 3158 => rom_word <= "01100000";








    +            when 3159 => rom_word <= "11111111";








    +            when 3160 => rom_word <= "01100000";








    +            when 3161 => rom_word <= "01100000";








    +            when 3162 => rom_word <= "01100000";








    +            when 3163 => rom_word <= "01100000";








    +            when 3164 => rom_word <= "01100000";








    +            when 3165 => rom_word <= "01100000";








    +            when 3166 => rom_word <= "01100000";








    +            when 3167 => rom_word <= "01100000";








    +            when 3168 => rom_word <= "01100000";








    +            when 3169 => rom_word <= "01100000";








    +            when 3170 => rom_word <= "01100000";








    +            when 3171 => rom_word <= "01100000";








    +            when 3172 => rom_word <= "01100000";








    +            when 3173 => rom_word <= "11100011";








    +            when 3174 => rom_word <= "01100000";








    +            when 3175 => rom_word <= "11100011";








    +            when 3176 => rom_word <= "01100000";








    +            when 3177 => rom_word <= "01100000";








    +            when 3178 => rom_word <= "01100000";








    +            when 3179 => rom_word <= "01100000";








    +            when 3180 => rom_word <= "01100000";








    +            when 3181 => rom_word <= "01100000";








    +            when 3182 => rom_word <= "01100000";








    +            when 3183 => rom_word <= "01100000";








    +            when 3184 => rom_word <= "10110001";








    +            when 3185 => rom_word <= "10110001";








    +            when 3186 => rom_word <= "10110001";








    +            when 3187 => rom_word <= "10110001";








    +            when 3188 => rom_word <= "10110001";








    +            when 3189 => rom_word <= "10110001";








    +            when 3190 => rom_word <= "10110001";








    +            when 3191 => rom_word <= "10110011";








    +            when 3192 => rom_word <= "10110001";








    +            when 3193 => rom_word <= "10110001";








    +            when 3194 => rom_word <= "10110001";








    +            when 3195 => rom_word <= "10110001";








    +            when 3196 => rom_word <= "10110001";








    +            when 3197 => rom_word <= "10110001";








    +            when 3198 => rom_word <= "10110001";








    +            when 3199 => rom_word <= "10110001";








    +            when 3200 => rom_word <= "10110001";








    +            when 3201 => rom_word <= "10110001";








    +            when 3202 => rom_word <= "10110001";








    +            when 3203 => rom_word <= "10110001";








    +            when 3204 => rom_word <= "10110001";








    +            when 3205 => rom_word <= "10110011";








    +            when 3206 => rom_word <= "00110000";








    +            when 3207 => rom_word <= "11110011";








    +            when 3221 => rom_word <= "11110011";








    +            when 3222 => rom_word <= "00110000";








    +            when 3223 => rom_word <= "10110011";








    +            when 3224 => rom_word <= "10110001";








    +            when 3225 => rom_word <= "10110001";








    +            when 3226 => rom_word <= "10110001";








    +            when 3227 => rom_word <= "10110001";








    +            when 3228 => rom_word <= "10110001";








    +            when 3229 => rom_word <= "10110001";








    +            when 3230 => rom_word <= "10110001";








    +            when 3231 => rom_word <= "10110001";








    +            when 3232 => rom_word <= "10110001";








    +            when 3233 => rom_word <= "10110001";








    +            when 3234 => rom_word <= "10110001";








    +            when 3235 => rom_word <= "10110001";








    +            when 3236 => rom_word <= "10110001";








    +            when 3237 => rom_word <= "10111111";








    +            when 3239 => rom_word <= "11111111";








    +            when 3253 => rom_word <= "11111111";








    +            when 3255 => rom_word <= "10111111";








    +            when 3256 => rom_word <= "10110001";








    +            when 3257 => rom_word <= "10110001";








    +            when 3258 => rom_word <= "10110001";








    +            when 3259 => rom_word <= "10110001";








    +            when 3260 => rom_word <= "10110001";








    +            when 3261 => rom_word <= "10110001";








    +            when 3262 => rom_word <= "10110001";








    +            when 3263 => rom_word <= "10110001";








    +            when 3264 => rom_word <= "10110001";








    +            when 3265 => rom_word <= "10110001";








    +            when 3266 => rom_word <= "10110001";








    +            when 3267 => rom_word <= "10110001";








    +            when 3268 => rom_word <= "10110001";








    +            when 3269 => rom_word <= "10110011";








    +            when 3270 => rom_word <= "00110000";








    +            when 3271 => rom_word <= "10110011";








    +            when 3272 => rom_word <= "10110001";








    +            when 3273 => rom_word <= "10110001";








    +            when 3274 => rom_word <= "10110001";








    +            when 3275 => rom_word <= "10110001";








    +            when 3276 => rom_word <= "10110001";








    +            when 3277 => rom_word <= "10110001";








    +            when 3278 => rom_word <= "10110001";








    +            when 3279 => rom_word <= "10110001";








    +            when 3285 => rom_word <= "11111111";








    +            when 3287 => rom_word <= "11111111";








    +            when 3296 => rom_word <= "10110001";








    +            when 3297 => rom_word <= "10110001";








    +            when 3298 => rom_word <= "10110001";








    +            when 3299 => rom_word <= "10110001";








    +            when 3300 => rom_word <= "10110001";








    +            when 3301 => rom_word <= "10111111";








    +            when 3303 => rom_word <= "10111111";








    +            when 3304 => rom_word <= "10110001";








    +            when 3305 => rom_word <= "10110001";








    +            when 3306 => rom_word <= "10110001";








    +            when 3307 => rom_word <= "10110001";








    +            when 3308 => rom_word <= "10110001";








    +            when 3309 => rom_word <= "10110001";








    +            when 3310 => rom_word <= "10110001";








    +            when 3311 => rom_word <= "10110001";








    +            when 3312 => rom_word <= "01100000";








    +            when 3313 => rom_word <= "01100000";








    +            when 3314 => rom_word <= "01100000";








    +            when 3315 => rom_word <= "01100000";








    +            when 3316 => rom_word <= "01100000";








    +            when 3317 => rom_word <= "11111111";








    +            when 3319 => rom_word <= "11111111";








    +            when 3328 => rom_word <= "10110001";








    +            when 3329 => rom_word <= "10110001";








    +            when 3330 => rom_word <= "10110001";








    +            when 3331 => rom_word <= "10110001";








    +            when 3332 => rom_word <= "10110001";








    +            when 3333 => rom_word <= "10110001";








    +            when 3334 => rom_word <= "10110001";








    +            when 3335 => rom_word <= "11111111";








    +            when 3349 => rom_word <= "11111111";








    +            when 3351 => rom_word <= "11111111";








    +            when 3352 => rom_word <= "01100000";








    +            when 3353 => rom_word <= "01100000";








    +            when 3354 => rom_word <= "01100000";








    +            when 3355 => rom_word <= "01100000";








    +            when 3356 => rom_word <= "01100000";








    +            when 3357 => rom_word <= "01100000";








    +            when 3358 => rom_word <= "01100000";








    +            when 3359 => rom_word <= "01100000";








    +            when 3367 => rom_word <= "11111111";








    +            when 3368 => rom_word <= "10110001";








    +            when 3369 => rom_word <= "10110001";








    +            when 3370 => rom_word <= "10110001";








    +            when 3371 => rom_word <= "10110001";








    +            when 3372 => rom_word <= "10110001";








    +            when 3373 => rom_word <= "10110001";








    +            when 3374 => rom_word <= "10110001";








    +            when 3375 => rom_word <= "10110001";








    +            when 3376 => rom_word <= "10110001";








    +            when 3377 => rom_word <= "10110001";








    +            when 3378 => rom_word <= "10110001";








    +            when 3379 => rom_word <= "10110001";








    +            when 3380 => rom_word <= "10110001";








    +            when 3381 => rom_word <= "10110001";








    +            when 3382 => rom_word <= "10110001";








    +            when 3383 => rom_word <= "11110011";








    +            when 3392 => rom_word <= "01100000";








    +            when 3393 => rom_word <= "01100000";








    +            when 3394 => rom_word <= "01100000";








    +            when 3395 => rom_word <= "01100000";








    +            when 3396 => rom_word <= "01100000";








    +            when 3397 => rom_word <= "11100011";








    +            when 3398 => rom_word <= "01100000";








    +            when 3399 => rom_word <= "11100011";








    +            when 3413 => rom_word <= "11100011";








    +            when 3414 => rom_word <= "01100000";








    +            when 3415 => rom_word <= "11100011";








    +            when 3416 => rom_word <= "01100000";








    +            when 3417 => rom_word <= "01100000";








    +            when 3418 => rom_word <= "01100000";








    +            when 3419 => rom_word <= "01100000";








    +            when 3420 => rom_word <= "01100000";








    +            when 3421 => rom_word <= "01100000";








    +            when 3422 => rom_word <= "01100000";








    +            when 3423 => rom_word <= "01100000";








    +            when 3431 => rom_word <= "11110011";








    +            when 3432 => rom_word <= "10110001";








    +            when 3433 => rom_word <= "10110001";








    +            when 3434 => rom_word <= "10110001";








    +            when 3435 => rom_word <= "10110001";








    +            when 3436 => rom_word <= "10110001";








    +            when 3437 => rom_word <= "10110001";








    +            when 3438 => rom_word <= "10110001";








    +            when 3439 => rom_word <= "10110001";








    +            when 3440 => rom_word <= "10110001";








    +            when 3441 => rom_word <= "10110001";








    +            when 3442 => rom_word <= "10110001";








    +            when 3443 => rom_word <= "10110001";








    +            when 3444 => rom_word <= "10110001";








    +            when 3445 => rom_word <= "10110001";








    +            when 3446 => rom_word <= "10110001";








    +            when 3447 => rom_word <= "11111111";








    +            when 3448 => rom_word <= "10110001";








    +            when 3449 => rom_word <= "10110001";








    +            when 3450 => rom_word <= "10110001";








    +            when 3451 => rom_word <= "10110001";








    +            when 3452 => rom_word <= "10110001";








    +            when 3453 => rom_word <= "10110001";








    +            when 3454 => rom_word <= "10110001";








    +            when 3455 => rom_word <= "10110001";








    +            when 3456 => rom_word <= "01100000";








    +            when 3457 => rom_word <= "01100000";








    +            when 3458 => rom_word <= "01100000";








    +            when 3459 => rom_word <= "01100000";








    +            when 3460 => rom_word <= "01100000";








    +            when 3461 => rom_word <= "11111111";








    +            when 3462 => rom_word <= "01100000";








    +            when 3463 => rom_word <= "11111111";








    +            when 3464 => rom_word <= "01100000";








    +            when 3465 => rom_word <= "01100000";








    +            when 3466 => rom_word <= "01100000";








    +            when 3467 => rom_word <= "01100000";








    +            when 3468 => rom_word <= "01100000";








    +            when 3469 => rom_word <= "01100000";








    +            when 3470 => rom_word <= "01100000";








    +            when 3471 => rom_word <= "01100000";








    +            when 3472 => rom_word <= "01100000";








    +            when 3473 => rom_word <= "01100000";








    +            when 3474 => rom_word <= "01100000";








    +            when 3475 => rom_word <= "01100000";








    +            when 3476 => rom_word <= "01100000";








    +            when 3477 => rom_word <= "01100000";








    +            when 3478 => rom_word <= "01100000";








    +            when 3479 => rom_word <= "01111100";








    +            when 3495 => rom_word <= "11100011";








    +            when 3496 => rom_word <= "01100000";








    +            when 3497 => rom_word <= "01100000";








    +            when 3498 => rom_word <= "01100000";








    +            when 3499 => rom_word <= "01100000";








    +            when 3500 => rom_word <= "01100000";








    +            when 3501 => rom_word <= "01100000";








    +            when 3502 => rom_word <= "01100000";








    +            when 3503 => rom_word <= "01100000";








    +            when 3504 => rom_word <= "11111111";








    +            when 3505 => rom_word <= "11111111";








    +            when 3506 => rom_word <= "11111111";








    +            when 3507 => rom_word <= "11111111";








    +            when 3508 => rom_word <= "11111111";








    +            when 3509 => rom_word <= "11111111";








    +            when 3510 => rom_word <= "11111111";








    +            when 3511 => rom_word <= "11111111";








    +            when 3512 => rom_word <= "11111111";








    +            when 3513 => rom_word <= "11111111";








    +            when 3514 => rom_word <= "11111111";








    +            when 3515 => rom_word <= "11111111";








    +            when 3516 => rom_word <= "11111111";








    +            when 3517 => rom_word <= "11111111";








    +            when 3518 => rom_word <= "11111111";








    +            when 3519 => rom_word <= "11111111";








    +            when 3527 => rom_word <= "11111111";








    +            when 3528 => rom_word <= "11111111";








    +            when 3529 => rom_word <= "11111111";








    +            when 3530 => rom_word <= "11111111";








    +            when 3531 => rom_word <= "11111111";








    +            when 3532 => rom_word <= "11111111";








    +            when 3533 => rom_word <= "11111111";








    +            when 3534 => rom_word <= "11111111";








    +            when 3535 => rom_word <= "11111111";








    +            when 3536 => rom_word <= "00111100";








    +            when 3537 => rom_word <= "00111100";








    +            when 3538 => rom_word <= "00111100";








    +            when 3539 => rom_word <= "00111100";








    +            when 3540 => rom_word <= "00111100";








    +            when 3541 => rom_word <= "00111100";








    +            when 3542 => rom_word <= "00111100";








    +            when 3543 => rom_word <= "00111100";








    +            when 3544 => rom_word <= "00111100";








    +            when 3545 => rom_word <= "00111100";








    +            when 3546 => rom_word <= "00111100";








    +            when 3547 => rom_word <= "00111100";








    +            when 3548 => rom_word <= "00111100";








    +            when 3549 => rom_word <= "00111100";








    +            when 3550 => rom_word <= "00111100";








    +            when 3551 => rom_word <= "00111100";








    +            when 3552 => rom_word <= "11000011";








    +            when 3553 => rom_word <= "11000011";








    +            when 3554 => rom_word <= "11000011";








    +            when 3555 => rom_word <= "11000011";








    +            when 3556 => rom_word <= "11000011";








    +            when 3557 => rom_word <= "11000011";








    +            when 3558 => rom_word <= "11000011";








    +            when 3559 => rom_word <= "11000011";








    +            when 3560 => rom_word <= "11000011";








    +            when 3561 => rom_word <= "11000011";








    +            when 3562 => rom_word <= "11000011";








    +            when 3563 => rom_word <= "11000011";








    +            when 3564 => rom_word <= "11000011";








    +            when 3565 => rom_word <= "11000011";








    +            when 3566 => rom_word <= "11000011";








    +            when 3567 => rom_word <= "11000011";








    +            when 3568 => rom_word <= "11111111";








    +            when 3569 => rom_word <= "11111111";








    +            when 3570 => rom_word <= "11111111";








    +            when 3571 => rom_word <= "11111111";








    +            when 3572 => rom_word <= "11111111";








    +            when 3573 => rom_word <= "11111111";








    +            when 3574 => rom_word <= "11111111";








    +            when 3589 => rom_word <= "10111001";








    +            when 3590 => rom_word <= "11101100";








    +            when 3591 => rom_word <= "01101100";








    +            when 3592 => rom_word <= "01101100";








    +            when 3593 => rom_word <= "01101100";








    +            when 3594 => rom_word <= "11101100";








    +            when 3595 => rom_word <= "10111001";








    +            when 3602 => rom_word <= "11111000";








    +            when 3603 => rom_word <= "11001101";








    +            when 3604 => rom_word <= "10001101";








    +            when 3605 => rom_word <= "11001101";








    +            when 3606 => rom_word <= "11101100";








    +            when 3607 => rom_word <= "01001100";








    +            when 3608 => rom_word <= "11001100";








    +            when 3609 => rom_word <= "11001100";








    +            when 3610 => rom_word <= "11001100";








    +            when 3611 => rom_word <= "01111100";








    +            when 3612 => rom_word <= "00001100";








    +            when 3613 => rom_word <= "00001100";








    +            when 3618 => rom_word <= "11111101";








    +            when 3619 => rom_word <= "10001101";








    +            when 3620 => rom_word <= "10001101";








    +            when 3621 => rom_word <= "00001100";








    +            when 3622 => rom_word <= "00001100";








    +            when 3623 => rom_word <= "00001100";








    +            when 3624 => rom_word <= "00001100";








    +            when 3625 => rom_word <= "00001100";








    +            when 3626 => rom_word <= "00001100";








    +            when 3627 => rom_word <= "00001100";








    +            when 3637 => rom_word <= "11111101";








    +            when 3638 => rom_word <= "11011000";








    +            when 3639 => rom_word <= "11011000";








    +            when 3640 => rom_word <= "11011000";








    +            when 3641 => rom_word <= "11011000";








    +            when 3642 => rom_word <= "11011000";








    +            when 3643 => rom_word <= "11011000";








    +            when 3650 => rom_word <= "11111101";








    +            when 3651 => rom_word <= "10001101";








    +            when 3652 => rom_word <= "00011000";








    +            when 3653 => rom_word <= "00110000";








    +            when 3654 => rom_word <= "01100000";








    +            when 3655 => rom_word <= "01100000";








    +            when 3656 => rom_word <= "00110000";








    +            when 3657 => rom_word <= "00011000";








    +            when 3658 => rom_word <= "10001101";








    +            when 3659 => rom_word <= "11111101";








    +            when 3669 => rom_word <= "11111001";








    +            when 3670 => rom_word <= "01101100";








    +            when 3671 => rom_word <= "01101100";








    +            when 3672 => rom_word <= "01101100";








    +            when 3673 => rom_word <= "01101100";








    +            when 3674 => rom_word <= "01101100";








    +            when 3675 => rom_word <= "00111000";








    +            when 3685 => rom_word <= "10011001";








    +            when 3686 => rom_word <= "10011001";








    +            when 3687 => rom_word <= "10011001";








    +            when 3688 => rom_word <= "10011001";








    +            when 3689 => rom_word <= "10011001";








    +            when 3690 => rom_word <= "10011001";








    +            when 3691 => rom_word <= "11111000";








    +            when 3692 => rom_word <= "00011000";








    +            when 3693 => rom_word <= "00011000";








    +            when 3694 => rom_word <= "00001100";








    +            when 3700 => rom_word <= "10111001";








    +            when 3701 => rom_word <= "11101100";








    +            when 3702 => rom_word <= "01100000";








    +            when 3703 => rom_word <= "01100000";








    +            when 3704 => rom_word <= "01100000";








    +            when 3705 => rom_word <= "01100000";








    +            when 3706 => rom_word <= "01100000";








    +            when 3707 => rom_word <= "01100000";








    +            when 3714 => rom_word <= "11111001";








    +            when 3715 => rom_word <= "01100000";








    +            when 3716 => rom_word <= "11110000";








    +            when 3717 => rom_word <= "10011001";








    +            when 3718 => rom_word <= "10011001";








    +            when 3719 => rom_word <= "10011001";








    +            when 3720 => rom_word <= "10011001";








    +            when 3721 => rom_word <= "11110000";








    +            when 3722 => rom_word <= "01100000";








    +            when 3723 => rom_word <= "11111001";








    +            when 3730 => rom_word <= "01110000";








    +            when 3731 => rom_word <= "11011000";








    +            when 3732 => rom_word <= "10001101";








    +            when 3733 => rom_word <= "10001101";








    +            when 3734 => rom_word <= "11111101";








    +            when 3735 => rom_word <= "10001101";








    +            when 3736 => rom_word <= "10001101";








    +            when 3737 => rom_word <= "10001101";








    +            when 3738 => rom_word <= "11011000";








    +            when 3739 => rom_word <= "01110000";








    +            when 3746 => rom_word <= "01110000";








    +            when 3747 => rom_word <= "11011000";








    +            when 3748 => rom_word <= "10001101";








    +            when 3749 => rom_word <= "10001101";








    +            when 3750 => rom_word <= "10001101";








    +            when 3751 => rom_word <= "11011000";








    +            when 3752 => rom_word <= "11011000";








    +            when 3753 => rom_word <= "11011000";








    +            when 3754 => rom_word <= "11011000";








    +            when 3755 => rom_word <= "11011101";








    +            when 3762 => rom_word <= "11100001";








    +            when 3763 => rom_word <= "00110000";








    +            when 3764 => rom_word <= "01100000";








    +            when 3765 => rom_word <= "11000000";








    +            when 3766 => rom_word <= "11110001";








    +            when 3767 => rom_word <= "10011001";








    +            when 3768 => rom_word <= "10011001";








    +            when 3769 => rom_word <= "10011001";








    +            when 3770 => rom_word <= "10011001";








    +            when 3771 => rom_word <= "11110000";








    +            when 3781 => rom_word <= "11111001";








    +            when 3782 => rom_word <= "01101111";








    +            when 3783 => rom_word <= "01101111";








    +            when 3784 => rom_word <= "01101111";








    +            when 3785 => rom_word <= "11111001";








    +            when 3795 => rom_word <= "00000011";








    +            when 3796 => rom_word <= "10000001";








    +            when 3797 => rom_word <= "11111001";








    +            when 3798 => rom_word <= "01101111";








    +            when 3799 => rom_word <= "01101111";








    +            when 3800 => rom_word <= "00111111";








    +            when 3801 => rom_word <= "11111001";








    +            when 3802 => rom_word <= "00011000";








    +            when 3803 => rom_word <= "00001100";








    +            when 3810 => rom_word <= "11100000";








    +            when 3811 => rom_word <= "00110000";








    +            when 3812 => rom_word <= "00011000";








    +            when 3813 => rom_word <= "00011000";








    +            when 3814 => rom_word <= "11111000";








    +            when 3815 => rom_word <= "00011000";








    +            when 3816 => rom_word <= "00011000";








    +            when 3817 => rom_word <= "00011000";








    +            when 3818 => rom_word <= "00110000";








    +            when 3819 => rom_word <= "11100000";








    +            when 3827 => rom_word <= "11111000";








    +            when 3828 => rom_word <= "10001101";








    +            when 3829 => rom_word <= "10001101";








    +            when 3830 => rom_word <= "10001101";








    +            when 3831 => rom_word <= "10001101";








    +            when 3832 => rom_word <= "10001101";








    +            when 3833 => rom_word <= "10001101";








    +            when 3834 => rom_word <= "10001101";








    +            when 3835 => rom_word <= "10001101";








    +            when 3844 => rom_word <= "11111101";








    +            when 3847 => rom_word <= "11111101";








    +            when 3850 => rom_word <= "11111101";








    +            when 3860 => rom_word <= "01100000";








    +            when 3861 => rom_word <= "01100000";








    +            when 3862 => rom_word <= "11111001";








    +            when 3863 => rom_word <= "01100000";








    +            when 3864 => rom_word <= "01100000";








    +            when 3867 => rom_word <= "11111001";








    +            when 3875 => rom_word <= "00110000";








    +            when 3876 => rom_word <= "01100000";








    +            when 3877 => rom_word <= "11000000";








    +            when 3878 => rom_word <= "10000001";








    +            when 3879 => rom_word <= "11000000";








    +            when 3880 => rom_word <= "01100000";








    +            when 3881 => rom_word <= "00110000";








    +            when 3883 => rom_word <= "11111001";








    +            when 3891 => rom_word <= "11000000";








    +            when 3892 => rom_word <= "01100000";








    +            when 3893 => rom_word <= "00110000";








    +            when 3894 => rom_word <= "00011000";








    +            when 3895 => rom_word <= "00110000";








    +            when 3896 => rom_word <= "01100000";








    +            when 3897 => rom_word <= "11000000";








    +            when 3899 => rom_word <= "11111001";








    +            when 3906 => rom_word <= "11000001";








    +            when 3907 => rom_word <= "01100011";








    +            when 3908 => rom_word <= "01100011";








    +            when 3909 => rom_word <= "01100000";








    +            when 3910 => rom_word <= "01100000";








    +            when 3911 => rom_word <= "01100000";








    +            when 3912 => rom_word <= "01100000";








    +            when 3913 => rom_word <= "01100000";








    +            when 3914 => rom_word <= "01100000";








    +            when 3915 => rom_word <= "01100000";








    +            when 3916 => rom_word <= "01100000";








    +            when 3917 => rom_word <= "01100000";








    +            when 3918 => rom_word <= "01100000";








    +            when 3919 => rom_word <= "01100000";








    +            when 3920 => rom_word <= "01100000";








    +            when 3921 => rom_word <= "01100000";








    +            when 3922 => rom_word <= "01100000";








    +            when 3923 => rom_word <= "01100000";








    +            when 3924 => rom_word <= "01100000";








    +            when 3925 => rom_word <= "01100000";








    +            when 3926 => rom_word <= "01100000";








    +            when 3927 => rom_word <= "01100000";








    +            when 3928 => rom_word <= "01100000";








    +            when 3929 => rom_word <= "01101100";








    +            when 3930 => rom_word <= "01101100";








    +            when 3931 => rom_word <= "01101100";








    +            when 3932 => rom_word <= "00111000";








    +            when 3941 => rom_word <= "01100000";








    +            when 3943 => rom_word <= "11111001";








    +            when 3945 => rom_word <= "01100000";








    +            when 3957 => rom_word <= "10111001";








    +            when 3958 => rom_word <= "11101100";








    +            when 3960 => rom_word <= "10111001";








    +            when 3961 => rom_word <= "11101100";








    +            when 3969 => rom_word <= "01110000";








    +            when 3970 => rom_word <= "11011000";








    +            when 3971 => rom_word <= "11011000";








    +            when 3972 => rom_word <= "01110000";








    +            when 3991 => rom_word <= "01100000";








    +            when 3992 => rom_word <= "01100000";








    +            when 4007 => rom_word <= "01100000";








    +            when 4017 => rom_word <= "11000011";








    +            when 4018 => rom_word <= "11000000";








    +            when 4019 => rom_word <= "11000000";








    +            when 4020 => rom_word <= "11000000";








    +            when 4021 => rom_word <= "11000000";








    +            when 4022 => rom_word <= "11000000";








    +            when 4023 => rom_word <= "11011100";








    +            when 4024 => rom_word <= "11011000";








    +            when 4025 => rom_word <= "11011000";








    +            when 4026 => rom_word <= "11110000";








    +            when 4027 => rom_word <= "11100000";








    +            when 4033 => rom_word <= "11011000";








    +            when 4034 => rom_word <= "10110001";








    +            when 4035 => rom_word <= "10110001";








    +            when 4036 => rom_word <= "10110001";








    +            when 4037 => rom_word <= "10110001";








    +            when 4038 => rom_word <= "10110001";








    +            when 4049 => rom_word <= "11110000";








    +            when 4050 => rom_word <= "10011001";








    +            when 4051 => rom_word <= "11000000";








    +            when 4052 => rom_word <= "01100000";








    +            when 4053 => rom_word <= "00110001";








    +            when 4054 => rom_word <= "11111001";








    +            when 4068 => rom_word <= "11111001";








    +            when 4069 => rom_word <= "11111001";








    +            when 4070 => rom_word <= "11111001";








    +            when 4071 => rom_word <= "11111001";








    +            when 4072 => rom_word <= "11111001";








    +            when 4073 => rom_word <= "11111001";








    +            when 4074 => rom_word <= "11111001";








    +            when others => rom_word <= X"00";








    +         end case;








    +      end if;








    +   end process;








    +end rtl;








    \ No newline at end of file








    Index: layer2/trunk/vhdl/vga/rtl








    ===================================================================








    --- layer2/trunk/vhdl/vga/rtl	(nonexistent)








    +++ layer2/trunk/vhdl/vga/rtl	(revision 2)
















    
    layer2/trunk/vhdl/vga/rtl














    Property changes :



    Added: bugtraq:number








    ## -0,0 +1 ##








    +true








    \ No newline at end of property








    Index: layer2/trunk/vhdl/vga/pc8x16s.bdf








    ===================================================================








    --- layer2/trunk/vhdl/vga/pc8x16s.bdf	(nonexistent)








    +++ layer2/trunk/vhdl/vga/pc8x16s.bdf	(revision 2)








    @@ -0,0 +1,5899 @@








    +STARTFONT 2.1








    +FONT PC8x16S








    +SIZE 16 100 100








    +FONTBOUNDINGBOX 8 16 0 -4








    +STARTPROPERTIES 3








    +DEFAULT_CHAR 32








    +FONT_DESCENT 4








    +FONT_ASCENT 12








    +ENDPROPERTIES








    +CHARS 256








    +STARTCHAR C0








    +ENCODING 0








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C1








    +ENCODING 1








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +7E








    +81








    +A5








    +81








    +81








    +BD








    +99








    +81








    +81








    +7E








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C2








    +ENCODING 2








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +7E








    +FF








    +DB








    +FF








    +FF








    +C3








    +E7








    +FF








    +FF








    +7E








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C3








    +ENCODING 3








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +6C








    +FE








    +FE








    +FE








    +FE








    +7C








    +38








    +10








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C4








    +ENCODING 4








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +10








    +38








    +7C








    +FE








    +7C








    +38








    +10








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C5








    +ENCODING 5








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +18








    +3C








    +3C








    +E7








    +E7








    +E7








    +18








    +18








    +3C








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C6








    +ENCODING 6








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +18








    +3C








    +7E








    +FF








    +FF








    +7E








    +18








    +18








    +3C








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C7








    +ENCODING 7








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +00








    +18








    +3C








    +3C








    +18








    +00








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C8








    +ENCODING 8








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +FF








    +FF








    +FF








    +FF








    +FF








    +FF








    +E7








    +C3








    +C3








    +E7








    +FF








    +FF








    +FF








    +FF








    +FF








    +FF








    +ENDCHAR








    +STARTCHAR C9








    +ENCODING 9








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +3C








    +66








    +42








    +42








    +66








    +3C








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CA








    +ENCODING 10








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +FF








    +FF








    +FF








    +FF








    +FF








    +C3








    +99








    +BD








    +BD








    +99








    +C3








    +FF








    +FF








    +FF








    +FF








    +FF








    +ENDCHAR








    +STARTCHAR CB








    +ENCODING 11








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +1E








    +0E








    +1A








    +32








    +78








    +CC








    +CC








    +CC








    +CC








    +78








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CC








    +ENCODING 12








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +3C








    +66








    +66








    +66








    +66








    +3C








    +18








    +7E








    +18








    +18








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CD








    +ENCODING 13








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +3F








    +33








    +3F








    +30








    +30








    +30








    +30








    +70








    +F0








    +E0








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CE








    +ENCODING 14








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +7F








    +63








    +7F








    +63








    +63








    +63








    +63








    +67








    +E7








    +E6








    +C0








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CF








    +ENCODING 15








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +18








    +18








    +DB








    +3C








    +E7








    +3C








    +DB








    +18








    +18








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C10








    +ENCODING 16








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +80








    +C0








    +E0








    +F0








    +F8








    +FE








    +F8








    +F0








    +E0








    +C0








    +80








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C11








    +ENCODING 17








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +02








    +06








    +0E








    +1E








    +3E








    +FE








    +3E








    +1E








    +0E








    +06








    +02








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C12








    +ENCODING 18








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +18








    +3C








    +7E








    +18








    +18








    +18








    +7E








    +3C








    +18








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C13








    +ENCODING 19








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +66








    +66








    +66








    +66








    +66








    +66








    +66








    +00








    +66








    +66








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C14








    +ENCODING 20








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +7F








    +DB








    +DB








    +DB








    +7B








    +1B








    +1B








    +1B








    +1B








    +1B








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C15








    +ENCODING 21








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +7C








    +C6








    +60








    +38








    +6C








    +C6








    +C6








    +6C








    +38








    +0C








    +C6








    +7C








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C16








    +ENCODING 22








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +FE








    +FE








    +FE








    +FE








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C17








    +ENCODING 23








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +18








    +3C








    +7E








    +18








    +18








    +18








    +7E








    +3C








    +18








    +7E








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C18








    +ENCODING 24








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +18








    +3C








    +7E








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C19








    +ENCODING 25








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +7E








    +3C








    +18








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C1A








    +ENCODING 26








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +18








    +0C








    +FE








    +0C








    +18








    +00








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C1B








    +ENCODING 27








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +30








    +60








    +FE








    +60








    +30








    +00








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C1C








    +ENCODING 28








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +00








    +C0








    +C0








    +C0








    +FE








    +00








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C1D








    +ENCODING 29








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +28








    +6C








    +FE








    +6C








    +28








    +00








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C1E








    +ENCODING 30








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +10








    +38








    +38








    +7C








    +7C








    +FE








    +FE








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C1F








    +ENCODING 31








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +FE








    +FE








    +7C








    +7C








    +38








    +38








    +10








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C20








    +ENCODING 32








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C21








    +ENCODING 33








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +18








    +3C








    +3C








    +3C








    +18








    +18








    +18








    +00








    +18








    +18








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C22








    +ENCODING 34








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +66








    +66








    +66








    +24








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C23








    +ENCODING 35








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +6C








    +6C








    +FE








    +6C








    +6C








    +6C








    +FE








    +6C








    +6C








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C24








    +ENCODING 36








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +18








    +18








    +7C








    +C6








    +C2








    +C0








    +7C








    +06








    +06








    +86








    +C6








    +7C








    +18








    +18








    +00








    +00








    +ENDCHAR








    +STARTCHAR C25








    +ENCODING 37








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +C2








    +C6








    +0C








    +18








    +30








    +60








    +C6








    +86








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C26








    +ENCODING 38








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +38








    +6C








    +6C








    +38








    +76








    +DC








    +CC








    +CC








    +CC








    +76








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C27








    +ENCODING 39








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +30








    +30








    +30








    +60








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C28








    +ENCODING 40








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +0C








    +18








    +30








    +30








    +30








    +30








    +30








    +30








    +18








    +0C








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C29








    +ENCODING 41








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +30








    +18








    +0C








    +0C








    +0C








    +0C








    +0C








    +0C








    +18








    +30








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C2A








    +ENCODING 42








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +66








    +3C








    +FF








    +3C








    +66








    +00








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C2B








    +ENCODING 43








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +18








    +18








    +7E








    +18








    +18








    +00








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C2C








    +ENCODING 44








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +18








    +18








    +18








    +30








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C2D








    +ENCODING 45








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +FE








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C2E








    +ENCODING 46








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +18








    +18








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C2F








    +ENCODING 47








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +02








    +06








    +0C








    +18








    +30








    +60








    +C0








    +80








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C30








    +ENCODING 48








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +38








    +6C








    +C6








    +CE








    +DE








    +F6








    +E6








    +C6








    +6C








    +38








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C31








    +ENCODING 49








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +18








    +38








    +78








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C32








    +ENCODING 50








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +7C








    +C6








    +06








    +0C








    +18








    +30








    +60








    +C0








    +C0








    +FE








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C33








    +ENCODING 51








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +7C








    +86








    +06








    +06








    +3C








    +06








    +06








    +06








    +86








    +7C








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C34








    +ENCODING 52








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +0C








    +1C








    +3C








    +6C








    +CC








    +FE








    +0C








    +0C








    +0C








    +0C








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C35








    +ENCODING 53








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +FE








    +C0








    +C0








    +C0








    +FC








    +06








    +06








    +06








    +86








    +7C








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C36








    +ENCODING 54








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +3C








    +60








    +C0








    +C0








    +DC








    +E6








    +C6








    +C6








    +C6








    +7C








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C37








    +ENCODING 55








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +FE








    +06








    +06








    +06








    +0C








    +18








    +30








    +30








    +30








    +30








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C38








    +ENCODING 56








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +7C








    +C6








    +C6








    +C6








    +7C








    +C6








    +C6








    +C6








    +C6








    +7C








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C39








    +ENCODING 57








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +7C








    +C6








    +C6








    +C6








    +7E








    +06








    +06








    +06








    +8C








    +78








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C3A








    +ENCODING 58








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +18








    +18








    +00








    +00








    +00








    +18








    +18








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C3B








    +ENCODING 59








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +18








    +18








    +00








    +00








    +00








    +18








    +18








    +30








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C3C








    +ENCODING 60








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +06








    +0C








    +18








    +30








    +60








    +30








    +18








    +0C








    +06








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C3D








    +ENCODING 61








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +7E








    +00








    +00








    +7E








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C3E








    +ENCODING 62








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +60








    +30








    +18








    +0C








    +06








    +0C








    +18








    +30








    +60








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C3F








    +ENCODING 63








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +7C








    +C6








    +C6








    +0C








    +18








    +18








    +18








    +00








    +18








    +18








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C40








    +ENCODING 64








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +7C








    +C6








    +C6








    +DE








    +DE








    +DE








    +DC








    +C0








    +7C








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C41








    +ENCODING 65








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +10








    +38








    +6C








    +C6








    +C6








    +FE








    +C6








    +C6








    +C6








    +C6








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C42








    +ENCODING 66








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +FC








    +C6








    +C6








    +C6








    +FC








    +C6








    +C6








    +C6








    +C6








    +FC








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C43








    +ENCODING 67








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +3C








    +66








    +C2








    +C0








    +C0








    +C0








    +C0








    +C2








    +66








    +3C








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C44








    +ENCODING 68








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +F8








    +DC








    +CE








    +C6








    +C6








    +C6








    +C6








    +CE








    +DC








    +F8








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C45








    +ENCODING 69








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +FC








    +C0








    +C0








    +C0








    +F8








    +C0








    +C0








    +C0








    +C0








    +FC








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C46








    +ENCODING 70








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +FC








    +C0








    +C0








    +C0








    +F8








    +C0








    +C0








    +C0








    +C0








    +C0








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C47








    +ENCODING 71








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +3C








    +62








    +C0








    +C0








    +C0








    +DE








    +C6








    +C6








    +66








    +3E








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C48








    +ENCODING 72








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +C6








    +C6








    +C6








    +C6








    +FE








    +C6








    +C6








    +C6








    +C6








    +C6








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C49








    +ENCODING 73








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C4A








    +ENCODING 74








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +1E








    +0C








    +0C








    +0C








    +0C








    +0C








    +CC








    +CC








    +CC








    +78








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C4B








    +ENCODING 75








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +C2








    +C6








    +CC








    +D8








    +F0








    +F0








    +D8








    +CC








    +C6








    +C2








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C4C








    +ENCODING 76








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +C0








    +C0








    +C0








    +C0








    +C0








    +C0








    +C0








    +C0








    +C0








    +FC








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C4D








    +ENCODING 77








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +C6








    +EE








    +FE








    +FE








    +D6








    +C6








    +C6








    +C6








    +C6








    +C6








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C4E








    +ENCODING 78








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +C6








    +E6








    +F6








    +FE








    +DE








    +CE








    +C6








    +C6








    +C6








    +C6








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C4F








    +ENCODING 79








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +7C








    +C6








    +C6








    +C6








    +C6








    +C6








    +C6








    +C6








    +C6








    +7C








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C50








    +ENCODING 80








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +FC








    +C6








    +C6








    +C6








    +FC








    +C0








    +C0








    +C0








    +C0








    +C0








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C51








    +ENCODING 81








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +7C








    +C6








    +C6








    +C6








    +C6








    +C6








    +C6








    +D6








    +DE








    +7C








    +0C








    +06








    +00








    +00








    +ENDCHAR








    +STARTCHAR C52








    +ENCODING 82








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +FC








    +C6








    +C6








    +C6








    +FC








    +D8








    +CC








    +CC








    +C6








    +C6








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C53








    +ENCODING 83








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +7C








    +C2








    +C0








    +60








    +38








    +0C








    +06








    +06








    +86








    +7C








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C54








    +ENCODING 84








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +7E








    +7E








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C55








    +ENCODING 85








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +C6








    +C6








    +C6








    +C6








    +C6








    +C6








    +C6








    +C6








    +C6








    +7C








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C56








    +ENCODING 86








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +C6








    +C6








    +C6








    +C6








    +C6








    +C6








    +C6








    +6C








    +38








    +10








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C57








    +ENCODING 87








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +C6








    +C6








    +C6








    +C6








    +D6








    +D6








    +D6








    +FE








    +EE








    +6C








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C58








    +ENCODING 88








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +C6








    +C6








    +6C








    +7C








    +38








    +38








    +7C








    +6C








    +C6








    +C6








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C59








    +ENCODING 89








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +66








    +66








    +66








    +66








    +3C








    +18








    +18








    +18








    +18








    +18








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C5A








    +ENCODING 90








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +FE








    +06








    +06








    +0C








    +18








    +30








    +60








    +C0








    +C0








    +FE








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C5B








    +ENCODING 91








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +3C








    +30








    +30








    +30








    +30








    +30








    +30








    +30








    +30








    +3C








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C5C








    +ENCODING 92








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +80








    +C0








    +E0








    +70








    +38








    +1C








    +0E








    +06








    +02








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C5D








    +ENCODING 93








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +3C








    +0C








    +0C








    +0C








    +0C








    +0C








    +0C








    +0C








    +0C








    +3C








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C5E








    +ENCODING 94








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +10








    +38








    +6C








    +C6








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C5F








    +ENCODING 95








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +FF








    +00








    +00








    +ENDCHAR








    +STARTCHAR C60








    +ENCODING 96








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +30








    +18








    +0C








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C61








    +ENCODING 97








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +78








    +0C








    +7C








    +CC








    +CC








    +CC








    +76








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C62








    +ENCODING 98








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +C0








    +C0








    +C0








    +F8








    +CC








    +CC








    +CC








    +CC








    +CC








    +F8








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C63








    +ENCODING 99








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +78








    +C4








    +C0








    +C0








    +C0








    +C4








    +78








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C64








    +ENCODING 100








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +0C








    +0C








    +0C








    +7C








    +CC








    +CC








    +CC








    +CC








    +CC








    +7C








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C65








    +ENCODING 101








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +7C








    +C6








    +FE








    +C0








    +C0








    +C2








    +7C








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C66








    +ENCODING 102








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +1C








    +36








    +32








    +30








    +78








    +30








    +30








    +30








    +30








    +30








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C67








    +ENCODING 103








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +7C








    +CC








    +CC








    +CC








    +CC








    +CC








    +7C








    +0C








    +8C








    +78








    +00








    +ENDCHAR








    +STARTCHAR C68








    +ENCODING 104








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +C0








    +C0








    +C0








    +D8








    +EC








    +CC








    +CC








    +CC








    +CC








    +CC








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C69








    +ENCODING 105








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +18








    +18








    +00








    +38








    +18








    +18








    +18








    +18








    +18








    +18








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C6A








    +ENCODING 106








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +0C








    +0C








    +00








    +0C








    +0C








    +0C








    +0C








    +0C








    +0C








    +0C








    +CC








    +CC








    +78








    +00








    +ENDCHAR








    +STARTCHAR C6B








    +ENCODING 107








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +C0








    +C0








    +C0








    +CC








    +D8








    +F0








    +F0








    +D8








    +CC








    +CC








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C6C








    +ENCODING 108








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +38








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C6D








    +ENCODING 109








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +EC








    +FE








    +D6








    +D6








    +D6








    +D6








    +C6








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C6E








    +ENCODING 110








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +B8








    +CC








    +CC








    +CC








    +CC








    +CC








    +CC








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C6F








    +ENCODING 111








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +78








    +CC








    +CC








    +CC








    +CC








    +CC








    +78








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C70








    +ENCODING 112








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +F8








    +CC








    +CC








    +CC








    +CC








    +CC








    +F8








    +C0








    +C0








    +C0








    +00








    +ENDCHAR








    +STARTCHAR C71








    +ENCODING 113








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +7C








    +CC








    +CC








    +CC








    +CC








    +CC








    +7C








    +0C








    +0C








    +0C








    +00








    +ENDCHAR








    +STARTCHAR C72








    +ENCODING 114








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +B8








    +EC








    +CC








    +C0








    +C0








    +C0








    +C0








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C73








    +ENCODING 115








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +7C








    +C2








    +70








    +1C








    +06








    +86








    +7C








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C74








    +ENCODING 116








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +30








    +30








    +30








    +FC








    +30








    +30








    +30








    +30








    +30








    +30








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C75








    +ENCODING 117








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +CC








    +CC








    +CC








    +CC








    +CC








    +CC








    +78








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C76








    +ENCODING 118








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +C6








    +C6








    +C6








    +C6








    +C6








    +6C








    +10








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C77








    +ENCODING 119








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +C6








    +C6








    +D6








    +D6








    +D6








    +FE








    +6C








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C78








    +ENCODING 120








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +C6








    +6C








    +38








    +38








    +38








    +6C








    +C6








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C79








    +ENCODING 121








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +C6








    +C6








    +C6








    +C6








    +C6








    +CE








    +76








    +06








    +8C








    +78








    +00








    +ENDCHAR








    +STARTCHAR C7A








    +ENCODING 122








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +FE








    +0C








    +18








    +30








    +60








    +C0








    +FE








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C7B








    +ENCODING 123








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +0E








    +18








    +18








    +18








    +70








    +18








    +18








    +18








    +18








    +0E








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C7C








    +ENCODING 124








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C7D








    +ENCODING 125








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +70








    +18








    +18








    +18








    +0E








    +18








    +18








    +18








    +18








    +70








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C7E








    +ENCODING 126








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +76








    +DC








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C7F








    +ENCODING 127








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +10








    +38








    +6C








    +C6








    +C6








    +C6








    +FE








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C80








    +ENCODING 128








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +3C








    +66








    +C0








    +C0








    +C0








    +C6








    +66








    +3C








    +18








    +CC








    +38








    +00








    +00








    +ENDCHAR








    +STARTCHAR C81








    +ENCODING 129








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +CC








    +CC








    +00








    +CC








    +CC








    +CC








    +CC








    +CC








    +CC








    +78








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C82








    +ENCODING 130








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +0C








    +18








    +30








    +00








    +7C








    +C6








    +FE








    +C0








    +C0








    +C2








    +7C








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C83








    +ENCODING 131








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +10








    +38








    +6C








    +00








    +78








    +0C








    +7C








    +CC








    +CC








    +CC








    +76








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C84








    +ENCODING 132








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +CC








    +00








    +00








    +78








    +0C








    +7C








    +CC








    +CC








    +CC








    +76








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C85








    +ENCODING 133








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +60








    +30








    +18








    +00








    +78








    +0C








    +7C








    +CC








    +CC








    +CC








    +76








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C86








    +ENCODING 134








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +38








    +6C








    +38








    +00








    +78








    +0C








    +7C








    +CC








    +CC








    +CC








    +76








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C87








    +ENCODING 135








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +7C








    +C6








    +C0








    +C0








    +C0








    +C6








    +7C








    +18








    +70








    +00








    +00








    +ENDCHAR








    +STARTCHAR C88








    +ENCODING 136








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +10








    +38








    +6C








    +00








    +7C








    +C6








    +FE








    +C0








    +C0








    +C2








    +7C








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C89








    +ENCODING 137








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +C6








    +00








    +00








    +7C








    +C6








    +FE








    +C0








    +C0








    +C2








    +7C








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C8A








    +ENCODING 138








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +60








    +30








    +18








    +00








    +7C








    +C6








    +FE








    +C0








    +C0








    +C2








    +7C








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C8B








    +ENCODING 139








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +66








    +00








    +00








    +38








    +18








    +18








    +18








    +18








    +18








    +18








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C8C








    +ENCODING 140








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +18








    +3C








    +66








    +00








    +38








    +18








    +18








    +18








    +18








    +18








    +18








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C8D








    +ENCODING 141








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +60








    +30








    +18








    +00








    +38








    +18








    +18








    +18








    +18








    +18








    +18








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C8E








    +ENCODING 142








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +C6








    +00








    +10








    +38








    +6C








    +C6








    +C6








    +FE








    +C6








    +C6








    +C6








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C8F








    +ENCODING 143








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +38








    +6C








    +38








    +10








    +38








    +6C








    +C6








    +FE








    +C6








    +C6








    +C6








    +C6








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C90








    +ENCODING 144








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +18








    +30








    +00








    +FC








    +C0








    +C0








    +C0








    +F0








    +C0








    +C0








    +C0








    +FC








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C91








    +ENCODING 145








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +EC








    +36








    +36








    +7E








    +D8








    +D8








    +6E








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C92








    +ENCODING 146








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +3E








    +6C








    +CC








    +CC








    +FE








    +CC








    +CC








    +CC








    +CC








    +CE








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C93








    +ENCODING 147








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +10








    +38








    +6C








    +00








    +7C








    +C6








    +C6








    +C6








    +C6








    +C6








    +7C








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C94








    +ENCODING 148








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +C6








    +00








    +00








    +7C








    +C6








    +C6








    +C6








    +C6








    +C6








    +7C








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C95








    +ENCODING 149








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +60








    +30








    +18








    +00








    +7C








    +C6








    +C6








    +C6








    +C6








    +C6








    +7C








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C96








    +ENCODING 150








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +30








    +78








    +CC








    +00








    +CC








    +CC








    +CC








    +CC








    +CC








    +CC








    +78








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C97








    +ENCODING 151








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +60








    +30








    +18








    +00








    +CC








    +CC








    +CC








    +CC








    +CC








    +CC








    +78








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C98








    +ENCODING 152








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +C6








    +00








    +00








    +C6








    +C6








    +C6








    +C6








    +C6








    +CE








    +76








    +06








    +8C








    +78








    +00








    +ENDCHAR








    +STARTCHAR C99








    +ENCODING 153








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +C6








    +00








    +7C








    +C6








    +C6








    +C6








    +C6








    +C6








    +C6








    +C6








    +7C








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C9A








    +ENCODING 154








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +C6








    +00








    +C6








    +C6








    +C6








    +C6








    +C6








    +C6








    +C6








    +C6








    +7C








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C9B








    +ENCODING 155








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +18








    +18








    +7C








    +C6








    +C0








    +C0








    +C0








    +C6








    +7C








    +18








    +18








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C9C








    +ENCODING 156








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +3C








    +42








    +99








    +A5








    +A5








    +A1








    +A1








    +A5








    +A5








    +B9








    +42








    +3C








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C9D








    +ENCODING 157








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +3C








    +42








    +B9








    +A5








    +A5








    +B9








    +B1








    +A9








    +A5








    +A5








    +42








    +3C








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C9E








    +ENCODING 158








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +F8








    +CC








    +CC








    +F8








    +C4








    +CC








    +DE








    +CC








    +CC








    +CC








    +C6








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR C9F








    +ENCODING 159








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +0E








    +1B








    +18








    +18








    +18








    +7E








    +18








    +18








    +18








    +D8








    +70








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CA0








    +ENCODING 160








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +18








    +30








    +60








    +00








    +78








    +0C








    +7C








    +CC








    +CC








    +CC








    +76








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CA1








    +ENCODING 161








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +0C








    +18








    +30








    +00








    +38








    +18








    +18








    +18








    +18








    +18








    +18








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CA2








    +ENCODING 162








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +18








    +30








    +60








    +00








    +7C








    +C6








    +C6








    +C6








    +C6








    +C6








    +7C








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CA3








    +ENCODING 163








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +18








    +30








    +60








    +00








    +CC








    +CC








    +CC








    +CC








    +CC








    +CC








    +78








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CA4








    +ENCODING 164








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +76








    +DC








    +00








    +5C








    +66








    +66








    +66








    +66








    +66








    +66








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CA5








    +ENCODING 165








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +76








    +DC








    +00








    +C6








    +E6








    +F6








    +FE








    +DE








    +CE








    +C6








    +C6








    +C6








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CA6








    +ENCODING 166








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +3C








    +6C








    +6C








    +3E








    +00








    +7E








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CA7








    +ENCODING 167








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +38








    +6C








    +6C








    +38








    +00








    +7C








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CA8








    +ENCODING 168








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +30








    +30








    +00








    +30








    +30








    +60








    +C0








    +C6








    +C6








    +7C








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CA9








    +ENCODING 169








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +00








    +FE








    +C0








    +C0








    +C0








    +C0








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CAA








    +ENCODING 170








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +00








    +FE








    +06








    +06








    +06








    +06








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CAB








    +ENCODING 171








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +60








    +E0








    +62








    +66








    +6C








    +18








    +30








    +60








    +DC








    +86








    +0C








    +18








    +3E








    +00








    +00








    +ENDCHAR








    +STARTCHAR CAC








    +ENCODING 172








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +60








    +E0








    +62








    +66








    +6C








    +18








    +30








    +66








    +CE








    +9A








    +3F








    +06








    +06








    +00








    +00








    +ENDCHAR








    +STARTCHAR CAD








    +ENCODING 173








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +18








    +18








    +00








    +18








    +18








    +18








    +3C








    +3C








    +3C








    +18








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CAE








    +ENCODING 174








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +36








    +6C








    +D8








    +6C








    +36








    +00








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CAF








    +ENCODING 175








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +D8








    +6C








    +36








    +6C








    +D8








    +00








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CB0








    +ENCODING 176








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +11








    +44








    +11








    +44








    +11








    +44








    +11








    +44








    +11








    +44








    +11








    +44








    +11








    +44








    +11








    +44








    +ENDCHAR








    +STARTCHAR CB1








    +ENCODING 177








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +55








    +AA








    +55








    +AA








    +55








    +AA








    +55








    +AA








    +55








    +AA








    +55








    +AA








    +55








    +AA








    +55








    +AA








    +ENDCHAR








    +STARTCHAR CB2








    +ENCODING 178








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +DD








    +77








    +DD








    +77








    +DD








    +77








    +DD








    +77








    +DD








    +77








    +DD








    +77








    +DD








    +77








    +DD








    +77








    +ENDCHAR








    +STARTCHAR CB3








    +ENCODING 179








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +ENDCHAR








    +STARTCHAR CB4








    +ENCODING 180








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +F8








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +ENDCHAR








    +STARTCHAR CB5








    +ENCODING 181








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +18








    +18








    +18








    +18








    +18








    +F8








    +18








    +F8








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +ENDCHAR








    +STARTCHAR CB6








    +ENCODING 182








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +36








    +36








    +36








    +36








    +36








    +36








    +36








    +F6








    +36








    +36








    +36








    +36








    +36








    +36








    +36








    +36








    +ENDCHAR








    +STARTCHAR CB7








    +ENCODING 183








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +FE








    +36








    +36








    +36








    +36








    +36








    +36








    +36








    +36








    +ENDCHAR








    +STARTCHAR CB8








    +ENCODING 184








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +F8








    +18








    +F8








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +ENDCHAR








    +STARTCHAR CB9








    +ENCODING 185








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +36








    +36








    +36








    +36








    +36








    +F6








    +06








    +F6








    +36








    +36








    +36








    +36








    +36








    +36








    +36








    +36








    +ENDCHAR








    +STARTCHAR CBA








    +ENCODING 186








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +36








    +36








    +36








    +36








    +36








    +36








    +36








    +36








    +36








    +36








    +36








    +36








    +36








    +36








    +36








    +36








    +ENDCHAR








    +STARTCHAR CBB








    +ENCODING 187








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +FE








    +06








    +F6








    +36








    +36








    +36








    +36








    +36








    +36








    +36








    +36








    +ENDCHAR








    +STARTCHAR CBC








    +ENCODING 188








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +36








    +36








    +36








    +36








    +36








    +F6








    +06








    +FE








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CBD








    +ENCODING 189








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +36








    +36








    +36








    +36








    +36








    +36








    +36








    +FE








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CBE








    +ENCODING 190








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +18








    +18








    +18








    +18








    +18








    +F8








    +18








    +F8








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CBF








    +ENCODING 191








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +F8








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +ENDCHAR








    +STARTCHAR CC0








    +ENCODING 192








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +1F








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CC1








    +ENCODING 193








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +FF








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CC2








    +ENCODING 194








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +FF








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +ENDCHAR








    +STARTCHAR CC3








    +ENCODING 195








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +1F








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +ENDCHAR








    +STARTCHAR CC4








    +ENCODING 196








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +FF








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CC5








    +ENCODING 197








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +FF








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +ENDCHAR








    +STARTCHAR CC6








    +ENCODING 198








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +18








    +18








    +18








    +18








    +18








    +1F








    +18








    +1F








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +ENDCHAR








    +STARTCHAR CC7








    +ENCODING 199








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +36








    +36








    +36








    +36








    +36








    +36








    +36








    +37








    +36








    +36








    +36








    +36








    +36








    +36








    +36








    +36








    +ENDCHAR








    +STARTCHAR CC8








    +ENCODING 200








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +36








    +36








    +36








    +36








    +36








    +37








    +30








    +3F








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CC9








    +ENCODING 201








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +3F








    +30








    +37








    +36








    +36








    +36








    +36








    +36








    +36








    +36








    +36








    +ENDCHAR








    +STARTCHAR CCA








    +ENCODING 202








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +36








    +36








    +36








    +36








    +36








    +F7








    +00








    +FF








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CCB








    +ENCODING 203








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +FF








    +00








    +F7








    +36








    +36








    +36








    +36








    +36








    +36








    +36








    +36








    +ENDCHAR








    +STARTCHAR CCC








    +ENCODING 204








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +36








    +36








    +36








    +36








    +36








    +37








    +30








    +37








    +36








    +36








    +36








    +36








    +36








    +36








    +36








    +36








    +ENDCHAR








    +STARTCHAR CCD








    +ENCODING 205








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +FF








    +00








    +FF








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CCE








    +ENCODING 206








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +36








    +36








    +36








    +36








    +36








    +F7








    +00








    +F7








    +36








    +36








    +36








    +36








    +36








    +36








    +36








    +36








    +ENDCHAR








    +STARTCHAR CCF








    +ENCODING 207








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +18








    +18








    +18








    +18








    +18








    +FF








    +00








    +FF








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CD0








    +ENCODING 208








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +36








    +36








    +36








    +36








    +36








    +36








    +36








    +FF








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CD1








    +ENCODING 209








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +FF








    +00








    +FF








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +ENDCHAR








    +STARTCHAR CD2








    +ENCODING 210








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +FF








    +36








    +36








    +36








    +36








    +36








    +36








    +36








    +36








    +ENDCHAR








    +STARTCHAR CD3








    +ENCODING 211








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +36








    +36








    +36








    +36








    +36








    +36








    +36








    +3F








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CD4








    +ENCODING 212








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +18








    +18








    +18








    +18








    +18








    +1F








    +18








    +1F








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CD5








    +ENCODING 213








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +1F








    +18








    +1F








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +ENDCHAR








    +STARTCHAR CD6








    +ENCODING 214








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +3F








    +36








    +36








    +36








    +36








    +36








    +36








    +36








    +36








    +ENDCHAR








    +STARTCHAR CD7








    +ENCODING 215








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +36








    +36








    +36








    +36








    +36








    +36








    +36








    +FF








    +36








    +36








    +36








    +36








    +36








    +36








    +36








    +36








    +ENDCHAR








    +STARTCHAR CD8








    +ENCODING 216








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +18








    +18








    +18








    +18








    +18








    +FF








    +18








    +FF








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +ENDCHAR








    +STARTCHAR CD9








    +ENCODING 217








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +F8








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CDA








    +ENCODING 218








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +1F








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +ENDCHAR








    +STARTCHAR CDB








    +ENCODING 219








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +FF








    +FF








    +FF








    +FF








    +FF








    +FF








    +FF








    +FF








    +FF








    +FF








    +FF








    +FF








    +FF








    +FF








    +FF








    +FF








    +ENDCHAR








    +STARTCHAR CDC








    +ENCODING 220








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +FF








    +FF








    +FF








    +FF








    +FF








    +FF








    +FF








    +FF








    +FF








    +ENDCHAR








    +STARTCHAR CDD








    +ENCODING 221








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +F0








    +F0








    +F0








    +F0








    +F0








    +F0








    +F0








    +F0








    +F0








    +F0








    +F0








    +F0








    +F0








    +F0








    +F0








    +F0








    +ENDCHAR








    +STARTCHAR CDE








    +ENCODING 222








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +0F








    +0F








    +0F








    +0F








    +0F








    +0F








    +0F








    +0F








    +0F








    +0F








    +0F








    +0F








    +0F








    +0F








    +0F








    +0F








    +ENDCHAR








    +STARTCHAR CDF








    +ENCODING 223








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +FF








    +FF








    +FF








    +FF








    +FF








    +FF








    +FF








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CE0








    +ENCODING 224








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +76








    +DC








    +D8








    +D8








    +D8








    +DC








    +76








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CE1








    +ENCODING 225








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +7C








    +CE








    +C6








    +CE








    +DC








    +C8








    +CC








    +CC








    +CC








    +F8








    +C0








    +C0








    +00








    +00








    +ENDCHAR








    +STARTCHAR CE2








    +ENCODING 226








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +FE








    +C6








    +C6








    +C0








    +C0








    +C0








    +C0








    +C0








    +C0








    +C0








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CE3








    +ENCODING 227








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +FE








    +6C








    +6C








    +6C








    +6C








    +6C








    +6C








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CE4








    +ENCODING 228








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +FE








    +C6








    +60








    +30








    +18








    +18








    +30








    +60








    +C6








    +FE








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CE5








    +ENCODING 229








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +7E








    +D8








    +D8








    +D8








    +D8








    +D8








    +70








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CE6








    +ENCODING 230








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +66








    +66








    +66








    +66








    +66








    +66








    +7C








    +60








    +60








    +C0








    +00








    +ENDCHAR








    +STARTCHAR CE7








    +ENCODING 231








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +76








    +DC








    +18








    +18








    +18








    +18








    +18








    +18








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CE8








    +ENCODING 232








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +7E








    +18








    +3C








    +66








    +66








    +66








    +66








    +3C








    +18








    +7E








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CE9








    +ENCODING 233








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +38








    +6C








    +C6








    +C6








    +FE








    +C6








    +C6








    +C6








    +6C








    +38








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CEA








    +ENCODING 234








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +38








    +6C








    +C6








    +C6








    +C6








    +6C








    +6C








    +6C








    +6C








    +EE








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CEB








    +ENCODING 235








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +1E








    +30








    +18








    +0C








    +3E








    +66








    +66








    +66








    +66








    +3C








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CEC








    +ENCODING 236








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +7E








    +DB








    +DB








    +DB








    +7E








    +00








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CED








    +ENCODING 237








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +03








    +06








    +7E








    +DB








    +DB








    +F3








    +7E








    +60








    +C0








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CEE








    +ENCODING 238








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +1C








    +30








    +60








    +60








    +7C








    +60








    +60








    +60








    +30








    +1C








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CEF








    +ENCODING 239








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +7C








    +C6








    +C6








    +C6








    +C6








    +C6








    +C6








    +C6








    +C6








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CF0








    +ENCODING 240








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +FE








    +00








    +00








    +FE








    +00








    +00








    +FE








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CF1








    +ENCODING 241








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +18








    +18








    +7E








    +18








    +18








    +00








    +00








    +7E








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CF2








    +ENCODING 242








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +30








    +18








    +0C








    +06








    +0C








    +18








    +30








    +00








    +7E








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CF3








    +ENCODING 243








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +0C








    +18








    +30








    +60








    +30








    +18








    +0C








    +00








    +7E








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CF4








    +ENCODING 244








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +0E








    +1B








    +1B








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +ENDCHAR








    +STARTCHAR CF5








    +ENCODING 245








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +18








    +D8








    +D8








    +D8








    +70








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CF6








    +ENCODING 246








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +18








    +00








    +7E








    +00








    +18








    +00








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CF7








    +ENCODING 247








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +76








    +DC








    +00








    +76








    +DC








    +00








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CF8








    +ENCODING 248








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +38








    +6C








    +6C








    +38








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CF9








    +ENCODING 249








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +18








    +18








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CFA








    +ENCODING 250








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +18








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CFB








    +ENCODING 251








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +0F








    +0C








    +0C








    +0C








    +0C








    +0C








    +EC








    +6C








    +6C








    +3C








    +1C








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CFC








    +ENCODING 252








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +6C








    +36








    +36








    +36








    +36








    +36








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CFD








    +ENCODING 253








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +3C








    +66








    +0C








    +18








    +32








    +7E








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CFE








    +ENCODING 254








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +7E








    +7E








    +7E








    +7E








    +7E








    +7E








    +7E








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +STARTCHAR CFF








    +ENCODING 255








    +SWIDTH 480 0








    +DWIDTH 8 0








    +BBX 8 16 0 -4








    +BITMAP








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +00








    +ENDCHAR








    +ENDFONT








    Index: layer2/trunk/vhdl/vga/chars.py








    ===================================================================








    --- layer2/trunk/vhdl/vga/chars.py	(nonexistent)








    +++ layer2/trunk/vhdl/vga/chars.py	(revision 2)








    @@ -0,0 +1,77 @@








    +#!/usr/bin/env python








    +#------------------------------------------------------------------------------#








    +# BDF character set to VHDL converter                                          #








    +#------------------------------------------------------------------------------#








    +# Copyright (C) 2011 Mathias Hoertnagl,  #








    +#                                                                              #








    +# This program is free software; you can redistribute it and/or modify it      #








    +# under the terms of the GNU General Public License as published by the Free   #








    +# Software Foundation; either version 3 of the License, or (at your option)    #








    +# any later version.                                                           #








    +# This program is distributed in the hope that it will be useful, but WITHOUT  #








    +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or        #








    +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for     #








    +# more details.                                                                #








    +# You should have received a copy of the GNU General Public License along with #








    +# this program; if not, see .                    #








    +#------------------------------------------------------------------------------#








    +import sys








    +import string








    +








    +if len(sys.argv) == 2:








    +








    +   inp = open(sys.argv[1], 'r')








    +   outp = open('./rtl/rom.vhd', 'w')








    +








    +   i = 0








    +   b = 0








    +








    +   outp.write('library ieee;\n')








    +   outp.write('use ieee.std_logic_1164.all;\n')








    +   outp.write('use ieee.numeric_std.all;\n\n')








    +








    +   outp.write('entity rom is\n')








    +   outp.write('   port(\n')








    +   outp.write('      clk      : in  std_logic;\n')








    +   outp.write('      rom_addr : in  std_logic_vector(11 downto 0);\n')








    +   outp.write('      rom_word : out std_logic_vector(7 downto 0)\n')








    +   outp.write('   );\n')








    +   outp.write('end rom;\n\n')








    +








    +   outp.write('architecture rtl of rom is\n')








    +   outp.write('begin\n')








    +   outp.write('   chrs : process(clk)\n')








    +   outp.write('   begin\n')








    +   outp.write('      if rising_edge(clk) then\n')








    +   outp.write('         case to_integer(unsigned(rom_addr)) is\n')








    +








    +   for l in inp:








    +      l2 = string.strip(l)








    +      if l2 == 'ENDCHAR':








    +         b = 0








    +      if b == 1:








    +         if l2 != '00':








    +            # Transform hex-string into 8bit zero padded bin-string without








    +            # preceeding 'b0'.








    +            s = bin(int(l2, 16))[2:].zfill(8)








    +            # Reverse binary number. [not x(2 downto 0)]








    +            s = s[::-1]








    +            # Rotate binary number 2 digits to the right. [x(2 downto 0) - 2]








    +            s = s[2:] + s[:2]








    +            outp.write( '            ' )








    +            outp.write( 'when %4d => rom_word <= "%8s";\n' % (i, s) )








    +         i = i+1








    +      if l2 == 'BITMAP':








    +         b = 1








    +








    +   outp.write('            when others => rom_word <= X"00";\n')








    +   outp.write('         end case;\n')








    +   outp.write('      end if;\n')








    +   outp.write('   end process;\n')








    +   outp.write('end rtl;')








    +








    +   outp.close()








    +   inp.close()








    +








    +else:








    +   print "Usage: python", sys.argv[0], "<*.bdf file>"








    \ No newline at end of file








    Index: layer2/trunk/vhdl/vga








    ===================================================================








    --- layer2/trunk/vhdl/vga	(nonexistent)








    +++ layer2/trunk/vhdl/vga	(revision 2)
















    
    layer2/trunk/vhdl/vga














    Property changes :



    Added: bugtraq:number








    ## -0,0 +1 ##








    +true








    \ No newline at end of property








    Index: layer2/trunk/vhdl/mem/rtl/imem.vhd








    ===================================================================








    --- layer2/trunk/vhdl/mem/rtl/imem.vhd	(nonexistent)








    +++ layer2/trunk/vhdl/mem/rtl/imem.vhd	(revision 2)








    @@ -0,0 +1,43 @@








    +--------------------------------------------------------------------------------








    +-- WB Memory Controller                                                       --








    +--------------------------------------------------------------------------------








    +-- Memory with a bus width of 32bit and a granularity of 8bit.                --








    +--                                                                            --








    +--------------------------------------------------------------------------------








    +-- Copyright (C)2011  Mathias H�rtnagl          --








    +--                                                                            --








    +-- This program is free software: you can redistribute it and/or modify       --








    +-- it under the terms of the GNU General Public License as published by       --








    +-- the Free Software Foundation, either version 3 of the License, or          --








    +-- (at your option) any later version.                                        --








    +--                                                                            --








    +-- This program is distributed in the hope that it will be useful,            --








    +-- but WITHOUT ANY WARRANTY; without even the implied warranty of             --








    +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the              --








    +-- GNU General Public License for more details.                               --








    +--                                                                            --








    +-- You should have received a copy of the GNU General Public License          --








    +-- along with this program.  If not, see .      --








    +--------------------------------------------------------------------------------








    +library ieee;








    +use ieee.std_logic_1164.all;








    +use ieee.numeric_std.all;








    +








    +library work;








    +use work.iwb.all;








    +








    +package imem is








    +








    +   type mem_t is array ( 0 to 4095 )








    +      of std_logic_vector(7 downto 0);








    +








    +   type mem_block_t is array ( 0 to 3 ) of mem_t;








    +








    +   component mem is








    +      port(








    +         si : in  slave_in_t;








    +         so : out slave_out_t








    +      );








    +   end component;








    +








    +end imem;








    \ No newline at end of file








    Index: layer2/trunk/vhdl/mem/rtl/mem.vhd








    ===================================================================








    --- layer2/trunk/vhdl/mem/rtl/mem.vhd	(nonexistent)








    +++ layer2/trunk/vhdl/mem/rtl/mem.vhd	(revision 2)








    @@ -0,0 +1,65 @@








    +--------------------------------------------------------------------------------








    +-- WB Memory Controller                                                       --








    +--------------------------------------------------------------------------------








    +-- Copyright (C)2011  Mathias H�rtnagl          --








    +--                                                                            --








    +-- This program is free software: you can redistribute it and/or modify       --








    +-- it under the terms of the GNU General Public License as published by       --








    +-- the Free Software Foundation, either version 3 of the License, or          --








    +-- (at your option) any later version.                                        --








    +--                                                                            --








    +-- This program is distributed in the hope that it will be useful,            --








    +-- but WITHOUT ANY WARRANTY; without even the implied warranty of             --








    +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the              --








    +-- GNU General Public License for more details.                               --








    +--                                                                            --








    +-- You should have received a copy of the GNU General Public License          --








    +-- along with this program.  If not, see .      --








    +--------------------------------------------------------------------------------








    +library ieee;








    +use ieee.std_logic_1164.all;








    +use ieee.numeric_std.all;








    +








    +library work;








    +use work.iwb.all;








    +use work.imem.all;








    +use work.data.all;








    +








    +entity mem is








    +   port(








    +      si : in  slave_in_t;








    +      so : out slave_out_t








    +   );








    +end mem;








    +








    +architecture rtl of mem is








    +








    +   signal mem : mem_block_t := data;








    +








    +   attribute RAM_STYLE : string;








    +   attribute RAM_STYLE of mem: signal is "BLOCK";








    +








    +   signal a : integer range 0 to 4095;








    +begin








    +   a <= to_integer( unsigned(si.adr(13 downto 2)) );








    +   mem0 : process(si.clk)








    +   begin








    +      for i in 0 to 3 loop








    +         if rising_edge(si.clk) then








    +            if si.stb = '1' then








    +               if (si.sel(i) = '1') and (si.we = '1') then








    +                  mem(i)( a ) <= si.dat(8*(i+1)-1 downto 8*i);








    +               end if;








    +               so.dat(8*(i+1)-1 downto 8*i) <= mem(i)( a );








    +            end if;








    +         end if;








    +      end loop;








    +   end process;








    +








    +   -- process(si.clk)








    +   -- begin








    +      -- if rising_edge(si.clk) then








    +         so.ack <= si.stb;








    +      -- end if;








    +   -- end process;








    +end architecture;








    \ No newline at end of file








    Index: layer2/trunk/vhdl/mem/rtl








    ===================================================================








    --- layer2/trunk/vhdl/mem/rtl	(nonexistent)








    +++ layer2/trunk/vhdl/mem/rtl	(revision 2)
















    
    layer2/trunk/vhdl/mem/rtl














    Property changes :



    Added: bugtraq:number








    ## -0,0 +1 ##








    +true








    \ No newline at end of property








    Index: layer2/trunk/vhdl/mem








    ===================================================================








    --- layer2/trunk/vhdl/mem	(nonexistent)








    +++ layer2/trunk/vhdl/mem	(revision 2)
















    
    layer2/trunk/vhdl/mem














    Property changes :



    Added: bugtraq:number








    ## -0,0 +1 ##








    +true








    \ No newline at end of property








    Index: layer2/trunk/vhdl








    ===================================================================








    --- layer2/trunk/vhdl	(nonexistent)








    +++ layer2/trunk/vhdl	(revision 2)
















    
    layer2/trunk/vhdl














    Property changes :



    Added: bugtraq:number








    ## -0,0 +1 ##








    +true








    \ No newline at end of property








    Index: layer2/trunk/README








    ===================================================================








    --- layer2/trunk/README	(nonexistent)








    +++ layer2/trunk/README	(revision 2)








    @@ -0,0 +1,4 @@








    ++------------------------------------------------------------------------------+








    +|                 layer[2] SoC for Spartan-3E Starter Kit                      |








    ++------------------------------------------------------------------------------+








    +Comming soon...








    \ No newline at end of file



    powered by: WebSVN 2.1.0


    
        © copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.

Browse

Tools

Subversion Repositories layer2

Compare Revisions

Rev 1 → Rev 2