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/trunk/bench/vhdl/smlt_ami_dec.vhd
0,0 → 1,42
-- smlttion for AMI decoder.
 
entity smlt_ami_dec is
end smlt_ami_dec;
 
architecture behaviour of smlt_ami_dec is
--data type:
component ami_dec
port (
clr_bar,
e0, e1: in bit;
s : out bit);
end component;
--binding:
for a: ami_dec use entity work.ami_dec;
 
--declaring the signals present in this architecture:
signal CLK, S, E0, E1, clrb: bit;
signal input0, input1: bit_vector(0 to 26);
 
begin --architecture.
a: ami_dec port map
( clr_bar => clrb, e0 => E0, e1 => E1, s => S );
 
input0 <= "000100010000100100001000010";
input1 <= "000001001000001000100000101";
 
process begin
clrb <= '1';
for i in 0 to 26 loop
E0 <= input0(i);
E1 <= input1(i);
CLK <= '0';
wait for 9 ns;
CLK <= '1';
wait for 1 ns;
end loop;
wait;
end process;
 
 
end behaviour;
/trunk/bench/vhdl/smlt_hdb1_enc.vhd
0,0 → 1,43
 
-- smlttion for HDB1 encoder.
 
entity smlt_hdb1_enc is
end smlt_hdb1_enc;
 
architecture behaviour of smlt_hdb1_enc is
--data type:
component hdb1_enc
port (
clr_bar,
clk : in bit;
e : in bit;
s0, s1: out bit);
end component;
--binding:
for a: hdb1_enc use entity work.hdb1_enc;
 
--declaring the signals present in this architecture:
signal CLK, E, S0, S1, clrb: bit;
signal inpute: bit_vector(0 to 24);
 
begin --architecture.
a: hdb1_enc port map
( clr_bar => clrb, clk => CLK, e => E, s0 => S0,
s1 => S1 );
 
inpute <= "0101011000101100101000011";
 
process begin
clrb <= '1';
for i in 0 to 24 loop
E <= inpute(i);
CLK <= '0';
wait for 9 ns;
CLK <= '1';
wait for 1 ns;
end loop;
wait;
end process;
 
 
end behaviour;
/trunk/bench/vhdl/smlt_hdb1_dec.vhd
0,0 → 1,43
-- smlttion for HDB1 decoder.
 
entity smlt_hdb1_dec is
end smlt_hdb1_dec;
 
architecture behaviour of smlt_hdb1_dec is
--data type:
component hdb1_dec
port (
clr_bar,
clk, e0, e1 : in bit;
s : out bit);
end component;
--binding:
for a: hdb1_dec use entity work.hdb1_dec;
 
--declaring the signals present in this architecture:
signal CLK, S, E0, E1, clrb: bit;
signal input0, input1: bit_vector(0 to 24);
 
begin --architecture.
a: hdb1_dec port map
( clr_bar => clrb, clk=> CLK, e0 => E0, e1 => E1,
s => S );
 
input0 <= "0100010110001011001001101";
input1 <= "0001001000100100100110010";
 
process begin
clrb <= '1';
for i in 0 to 24 loop
E0 <= input0(i);
E1 <= input1(i);
CLK <= '0';
wait for 9 ns;
CLK <= '1';
wait for 1 ns;
end loop;
wait;
end process;
 
 
end behaviour;
/trunk/bench/vhdl/smlt_ami_enc.vhd
0,0 → 1,43
 
-- smlttion for AMI encoder.
 
entity smlt_ami_enc is
end smlt_ami_enc;
 
architecture behaviour of smlt_ami_enc is
--data type:
component ami_enc
port (
clr_bar,
clk : in bit;
e : in bit;
s0, s1: out bit);
end component;
--binding:
for a: ami_enc use entity work.ami_enc;
 
--declaring the signals present in this architecture:
signal CLK, E, S0, S1, clrb: bit;
signal inpute: bit_vector(0 to 26);
 
begin --architecture.
a: ami_enc port map
( clr_bar => clrb, clk => CLK, e => E, s0 => S0,
s1 => S1 );
 
inpute <= "000101011000101100101000111";
 
process begin
clrb <= '1';
for i in 0 to 26 loop
E <= inpute(i);
CLK <= '0';
wait for 9 ns;
CLK <= '1';
wait for 1 ns;
end loop;
wait;
end process;
 
 
end behaviour;

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