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/mult_booth_array/trunk/doc/booth_array_multiplier.bib
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% Encoding: UTF-8 |
|
@InProceedings{kaz15, |
author = {Kumm, M and Abbas, Shahid and Zipf, Peter}, |
title = {{An Efficient Softcore Multiplier Architecture for Xilinx FPGAs}}, |
booktitle = {IEEE Symposium on Computer Arithmetic (ARITH)}, |
year = {2015}, |
pages = {18--25}, |
} |
|
@Comment{jabref-meta: databaseType:bibtex;} |
/mult_booth_array/trunk/doc/booth_array_multiplier.pdf
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Index: mult_booth_array/trunk/doc/booth_array_multiplier.tex
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+\documentclass[a4paper,BCOR7mm,12pt,pointlessnumbers,bibtotoc]{scrartcl}
+
+\usepackage{amsmath,epsfig}
+\usepackage{amssymb,amsfonts}
+\usepackage{color}
+\usepackage{array,booktabs}
+\usepackage{graphicx}
+\usepackage{caption}
+\usepackage[hypcap=true,labelformat=simple]{subcaption}
+\renewcommand{\thesubfigure}{(\alph{subfigure})}
+\usepackage{tikz}
+\usetikzlibrary{arrows,automata}
+\usepackage{listings}
+\usepackage{hyperref}
+\usepackage{enumitem}
+
+\newcolumntype{C}[1]{>{\centering\arraybackslash}p{#1}} % centering column type with fixed width
+\newcolumntype{R}[1]{>{\raggedleft\arraybackslash}p{#1}} % right aligned column type with fixed width
+\newcolumntype{L}[1]{>{\raggedright\arraybackslash}p{#1}} % left aligned column type with fixed width
+
+\newcommand{\ceil}[1]{\left\lceil #1 \right\rceil} %\left\lceil #1 \right\rceil
+
+\begin{document}
+%\maketitle
+\begin{center}
+\Large Efficient Booth Array Multiplier for Xilinx FPGAs\\[0.4cm]
+\large Martin Kumm \\[0.5cm]
+\large \today \\[0.5cm]
+\end{center}
+
+\section{Introduction}
+
+This IP core provides a resource efficient implementation of a Booth Array Multiplier for Xilinx FPGAs. For details about the architecture see \cite{kaz15}.
+
+\section{Interface}
+
+The top level entity is found in \verb|mult_booth_array.vhd|. The generics as well as the portare described in Table~\ref{tab:generics} and Table~\ref{tab:port}, respectively.
+
+\begin{table}[!h]
+ \renewcommand{\arraystretch}{1.1}
+ \caption{Description of the generics}
+ \label{tab:generics}
+ \centering
+ \begin{tabular}{lccL{7cm}}
+ \toprule
+ Generic & Type & Default & Description\\
+ \cmidrule(rl){1-1} \cmidrule(rl){2-2} \cmidrule(rl){3-3} \cmidrule(rl){4-4}
+ \verb|word_size_a| & integer & 8 & Input word size operand $A$\\
+ \verb|word_size_b| & integer & 8 & Input word size operand $B$\\
+ \verb|sync_in_out| & boolean & false & If true, registers are placed at inputs and outputs (for timing results)\\
+ \verb|use_pipelining| & boolean & true & If true, the multiplier is internally pipelined (highly recommented)\\
+ \bottomrule
+ \end{tabular}
+\end{table}
+
+\begin{table}[!h]
+ \renewcommand{\arraystretch}{1.1}
+ \caption{Description of the port}
+ \label{tab:port}
+ \centering
+ \begin{tabular}{lcccL{5cm}}
+ \toprule
+ Generic & Direction & Type & Word Size & Description\\
+ \cmidrule(rl){1-1} \cmidrule(rl){2-2} \cmidrule(rl){3-3} \cmidrule(rl){4-4} \cmidrule(rl){5-5}
+ \verb|clk_i| & in & \verb|sl| & 1 & Clock input (used when \verb|use_pipelining=true| or \verb|sync_in_out=true|)\\
+ \verb|rst_i| & in & \verb|sl| & 1 & Reset input (used when \verb|use_pipelining=true| or \verb|sync_in_out=true|)\\
+ \verb|ce_i| & in & \verb|sl| & 1 & Clock enable input (used when \verb|use_pipelining=true| or \verb|sync_in_out=true|)\\
+ \verb|a_i| & in & \verb|slv| & \verb|input_word_size| & Input operand $A$\\
+ \verb|b_i| & in & \verb|slv| & \verb|input_word_size| & Input operand $B$\\
+ \verb|p_o| & out & \verb|slv| & \verb|input_word_size + 2| & Product output $P=A \times B$\\
+ \bottomrule
+ \end{tabular}
+\end{table}
+
+
+\section{Simulation \& Test}
+
+For simulation and test, the testbench (\verb|tb_mult_booth_array.vhd|) was created which uses a random number generator together with assert statements to verify the designs (against a naive VHDL multiplication).
+
+\bibliographystyle{alpha}
+\bibliography{booth_array_multiplier}
+
+\end{document}
+
+
+
mult_booth_array/trunk/doc/booth_array_multiplier.tex
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Index: mult_booth_array/trunk/vhdl/bd_mult_slice.vhd
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mult_booth_array/trunk/vhdl/bd_mult_slice.vhd
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Index: mult_booth_array/trunk/vhdl/mult_booth_array.vhd
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Index: mult_booth_array/trunk/vhdl/mult_booth_array.vhd
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Index: mult_booth_array/trunk/vhdl/register_chain.vhd
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--- mult_booth_array/trunk/vhdl/register_chain.vhd (nonexistent)
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+---------------------------------------------------------------------------------------------
+-- Author: Martin Kumm
+-- Contact: kumm@uni-kassel.de
+-- License: LGPL
+-- Date: 31.10.2014
+-- Compatibility: Xilinx FPGAs of Virtex 5-7, Spartan 6 and Series 7 architectures
+--
+-- Description:
+-- Simple register chain for a delay with arbitrary length (set by generic delay)
+---------------------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+entity register_chain is
+ generic(
+ word_size : integer;
+ delay : integer
+ );
+ port(
+ clk_i : in std_logic;
+ rst_i : in std_logic;
+ ce_i : in std_logic;
+ d_i : in std_logic_vector(word_size-1 downto 0);
+ q_o : out std_logic_vector(word_size-1 downto 0)
+ );
+end register_chain;
+
+architecture register_chain_arch of register_chain is
+
+type register_line is array(0 to delay-1) of std_logic_vector(word_size-1 downto 0);
+
+signal d_delayed : register_line;
+
+begin
+
+implement_register_chain: if delay > 0 generate
+ process (clk_i, rst_i)
+ begin
+ if rst_i = '1' then
+ for i in 0 to delay-1 loop
+ d_delayed(i) <= (others => '0');
+ end loop;
+ elsif clk_i'event and clk_i = '1' then
+ if ce_i = '1' then
+ d_delayed(0) <= d_i;
+
+ for i in 0 to delay-2 loop
+ d_delayed(i+1) <= d_delayed(i);
+ end loop;
+ end if;
+ end if;
+ end process;
+ q_o <= d_delayed(delay-1);
+end generate;
+
+implement_wire: if delay = 0 generate
+ q_o <= d_i;
+end generate;
+
+end register_chain_arch;
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mult_booth_array/trunk/vhdl/register_chain.vhd
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Index: mult_booth_array/trunk/vhdl/tb_mult_booth_array.vhd
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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+
+entity tb_mult_booth_array is
+ generic(
+ word_size_a : integer := 8;
+ word_size_b : integer := 8;
+ use_pipelining : boolean := true
+ );
+end tb_mult_booth_array;
+
+architecture tb_arch of tb_mult_booth_array is
+
+ constant no_of_rows : integer := integer(floor(real(word_size_b+2)/2.0));
+
+ signal clk : std_logic := '1';
+ signal rst : std_logic;
+
+ signal a : std_logic_vector(word_size_a-1 downto 0);
+ signal b : std_logic_vector(word_size_b-1 downto 0);
+ signal p_dut,p_ref,p_refd : std_logic_vector(word_size_a+word_size_b-1 downto 0);
+
+begin
+
+ clk <= not clk after 5 ns;
+ rst <= '1', '0' after 10 ns;
+
+ mult_booth_array_inst : entity work.mult_booth_array
+ generic map (
+ word_size_a => word_size_a,
+ word_size_b => word_size_b,
+ use_pipelining => use_pipelining
+ )
+ port map (
+ clk_i => clk,
+ rst_i => rst,
+ ce_i => '1',
+ a_i => a,
+ b_i => b,
+ p_o => p_dut
+ );
+
+
+ process
+ variable seed1, seed2: positive;
+ variable rand : real;
+ begin
+ a <= (others => '0');
+ b <= (others => '0');
+ loop
+ uniform(seed1, seed2, rand);
+ wait until clk'event and clk='0';
+ a <= std_logic_vector(to_unsigned(integer(trunc(rand*real(2**word_size_a-1))),word_size_a));
+ uniform(seed1, seed2, rand);
+ b <= std_logic_vector(to_unsigned(integer(trunc(rand*real(2**word_size_b-1))),word_size_b));
+ p_ref <= std_logic_vector(unsigned(a) * unsigned(b));
+ end loop;
+ end process;
+
+ delay_ref: if use_pipelining generate
+ ref_delay : entity work.register_chain generic map(word_size => word_size_a+word_size_b, delay => no_of_rows-1) port map(clk_i => clk, rst_i => rst, ce_i => '1', d_i => p_ref, q_o => p_refd);
+ end generate;
+
+ forward_ref: if not use_pipelining generate
+ p_refd <= p_ref;
+ end generate;
+
+ process
+ variable seed1, seed2: positive;
+ variable rand : real;
+ begin
+ wait until rst'event and rst='0';
+ for i in 0 to no_of_rows-1 loop
+ wait until clk'event and clk='0';
+ end loop;
+ loop
+ wait until clk'event and clk='0';
+ assert (p_dut = p_refd) report "Test failure" severity warning;
+ end loop;
+ end process;
+
+end architecture;
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mult_booth_array/trunk/vhdl/tb_mult_booth_array.vhd
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Index: mult_booth_array/trunk/copying
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+ GNU GENERAL PUBLIC LICENSE
+ Version 3, 29 June 2007
+
+ Copyright (C) 2007 Free Software Foundation, Inc.
+ Copyright (C)
+
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see Copyright (C)
+ This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+ This is free software, and you are welcome to redistribute it
+ under certain conditions; type `show c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate
+parts of the General Public License. Of course, your program's commands
+might be different; for a GUI interface, you would use an "about box".
+
+ You should also get your employer (if you work as a programmer) or school,
+if any, to sign a "copyright disclaimer" for the program, if necessary.
+For more information on this, and how to apply and follow the GNU GPL, see
+.
mult_booth_array/trunk/copying
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