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Index: numbert_sort_device/trunk/test_vga.v
===================================================================
--- numbert_sort_device/trunk/test_vga.v (nonexistent)
+++ numbert_sort_device/trunk/test_vga.v (revision 2)
@@ -0,0 +1,224 @@
+
+
+module VGA_Pattern ( // Read Out Side
+ oRed,
+ oGreen,
+ oBlue,
+ iVGA_X,
+ iVGA_Y,
+ iVGA_CLK,
+ // Control Signals
+ iRST_n,
+
+ iColor_SW,
+ endFrame,
+ dbg_val );
+
+parameter R_SZ= 64;
+
+ // Read Out Side
+output reg [9:0] oRed;
+output reg [9:0] oGreen;
+output reg [9:0] oBlue;
+input [11:0] iVGA_X;
+input [11:0] iVGA_Y;
+input iVGA_CLK;
+// Control Signals
+input iRST_n;
+input [9:0] iColor_SW;
+input endFrame;
+
+output wire [63:0] dbg_val;
+wire [63:0] dbg_val_i;
+
+parameter ENABLE_HEAVIES= 1;
+
+reg [15:0] chrono;
+reg endFrame2;
+reg endFrame3;
+
+wire [3:0] x;
+wire [3:0] y;
+
+
+wire [7:0] rv_a_2;
+wire [7:0] gv_a_2;
+wire [7:0] bv_a_2;
+
+
+Test_Sorting_Stack #( 15, R_SZ ) high_end_2( .clk( iVGA_CLK ), .rst( ~iRST_n ),
+ .iX_video( iVGA_X ), .iY_video( iVGA_Y ),
+ .oR_video( rv_a_2 ), .oG_video( gv_a_2 ), .oB_video( bv_a_2 ),
+ .tumblers( iColor_SW ), .endFrame(endFrame3),
+ .dbg_val(_)
+ );
+
+
+wire [7:0] mp_test_out;
+
+assign dbg_val= iColor_SW[7] ? dbg_val_i:chrono;
+
+always@(posedge iVGA_CLK or negedge iRST_n)
+begin
+ if(!iRST_n)
+ begin
+ oRed <= 0;
+ oGreen <= 0;
+ oBlue <= 0;
+ chrono <= 0;
+ end
+ else
+ begin
+ if ( endFrame2==0 && endFrame==1 )
+ begin
+ chrono<= chrono +1;
+ endFrame3<= 1;
+ end
+ else
+ begin
+ endFrame3<= 0;
+ end
+ endFrame2<= endFrame;
+
+
+ begin
+// oBlue <= iVGA_X[4] ? -1: iVGA_X;
+// oGreen <= iVGA_X[5] ? -1: iVGA_X;
+// oRed <= iVGA_X[6] ? -1: iVGA_Y;
+ oBlue <= bv_a_2;
+ oGreen <= gv_a_2;
+ oRed <= rv_a_2;
+ end
+ end
+end
+
+endmodule
+
+
+
+module Test_Sorting_Stack ( clk, rst,
+ iX_video, iY_video,
+ oR_video, oG_video, oB_video,
+ tumblers, endFrame, dbg_val );
+
+parameter HBIT= 15;
+parameter R_SZ= 64;
+
+input clk;
+input rst;
+
+input signed [11:0] iX_video;
+input signed [11:0] iY_video;
+output reg [7:0] oR_video;
+output reg [7:0] oG_video;
+output reg [7:0] oB_video;
+input [9:0] tumblers;
+input endFrame;
+output wire [63:0] dbg_val= count;
+
+reg [HBIT*3+2:0]generator;
+reg [HBIT*3+2:0]prev_generator;
+reg prev_btn;
+
+wire cell_rst= ( iX_video==1 && iY_video==1);
+wire cell_clk= ( iX_video==1 );
+
+reg err_unsorted;
+reg err_checksum;
+reg err_disagreement;
+
+wire [HBIT:0] data_in= generator;
+wire [HBIT:0] _data_out;
+wire [HBIT:0] _d_out_3;
+
+reg [HBIT:0] last_data;
+reg [31:0] stack_sum;
+reg [15:0] stack_pos_count;
+reg [31:0] old_sum;
+
+// tumblers[4] ? increasing order : decreasing order
+ wire [HBIT:0] _data_in= tumblers[4] ? -1-data_in : data_in;
+ Sorting_Tree #(HBIT,R_SZ) ctree ( clk, ~cell_clk, is_input, _data_in, _d_out_3 );
+ wire [HBIT:0] d_out_3 = tumblers[4] ? -1-_d_out_3 : _d_out_3;
+ Sorting_Tree #(HBIT,R_SZ) cstack ( clk, ~cell_clk, is_input, _data_in, _data_out );
+ wire [HBIT:0] data_out= tumblers[4] ? -1-_data_out : _data_out;
+
+reg [11:0]count;
+wire is_input= !cell_rst && count data_out ))|
+ ( ~tumblers[4] && ( last_data < data_out ));
+ err_disagreement<= ( tumblers[0] & err_disagreement) | ( data_out != d_out_3 );
+ end
+ generator<= generator*11 + ( generator >> 16 );
+ count<= count +1;
+ end
+
+// oR_video<= (is_input ? data_in[HBIT:HBIT-9] : data_out[HBIT:HBIT-9]) > iX_video && !err_unsorted ? -1:0;
+// oG_video<= stack_sum[HBIT:HBIT-9] > iX_video ? -1:0;
+ oR_video<= (is_input ? show_data_in : show_d_out_3 ) > iX_video ? -1:(8'h0-err_unsorted);
+ oG_video<= (is_input ? show_data_in : show_data_out) > iX_video ? -1:(8'h0-err_checksum);
+ oB_video<= (is_input ? 0 : show_data_out) > iX_video ? -1:(8'h0-err_disagreement);
+ end
+end
+
+wire [9:0] show_data_in = tumblers[3] ? data_in [9:0] : data_in [HBIT:HBIT-9];
+wire [9:0] show_data_out= tumblers[3] ? data_out[9:0] : data_out[HBIT:HBIT-9];
+wire [9:0] show_d_out_3 = tumblers[3] ? d_out_3 [9:0] : d_out_3 [HBIT:HBIT-9];
+
+endmodule
+
+
+
Index: numbert_sort_device/trunk/utility/VGA_Ctrl.v
===================================================================
--- numbert_sort_device/trunk/utility/VGA_Ctrl.v (nonexistent)
+++ numbert_sort_device/trunk/utility/VGA_Ctrl.v (revision 2)
@@ -0,0 +1,130 @@
+module VGA_Ctrl ( // Host Side
+ iRed,
+ iGreen,
+ iBlue,
+ oCurrent_X,
+ oCurrent_Y,
+ // VGA Side
+ oVGA_R,
+ oVGA_G,
+ oVGA_B,
+ oVGA_HS,
+ oVGA_VS,
+ oVGA_SYNC,
+ oVGA_BLANK,
+ oVGA_CLOCK,
+ // Control Signal
+ iCLK,
+ iRST_N,
+
+ les_btn );
+input wire les_btn;
+// Host Side
+input [9:0] iRed;
+input [9:0] iGreen;
+input [9:0] iBlue;
+output [10:0] oCurrent_X;
+output [10:0] oCurrent_Y;
+// VGA Side
+output [9:0] oVGA_R;
+output [9:0] oVGA_G;
+output [9:0] oVGA_B;
+output reg oVGA_HS;
+output reg oVGA_VS;
+output oVGA_SYNC;
+output oVGA_BLANK;
+output oVGA_CLOCK;
+// Control Signal
+input iCLK;
+input iRST_N;
+// Internal Registers
+reg [10:0] H_Cont;
+reg [10:0] V_Cont;
+////////////////////////////////////////////////////////////
+
+// Horizontal Parameter
+parameter H_FRONT = 16;
+parameter H_SYNC = 96;
+parameter H_BACK = 48;
+parameter H_ACT = 640;
+// Vertical Parameter
+parameter V_FRONT = 10;
+parameter V_SYNC = 2;
+parameter V_BACK = 33;
+parameter V_ACT = 480;
+////////////////////////////////////////////////////////////
+parameter H_BLANK = H_FRONT+H_SYNC+H_BACK;
+parameter H_TOTAL = H_FRONT+H_SYNC+H_BACK+H_ACT;
+parameter V_BLANK = V_FRONT+V_SYNC+V_BACK;
+parameter V_TOTAL = V_FRONT+V_SYNC+V_BACK+V_ACT;
+////////////////////////////////////////////////////////////
+assign oVGA_SYNC = 1'b1; // This pin is unused.
+assign oVGA_BLANK = ~((H_Cont 0) ? iRed : 0 ;
+assign oVGA_G = (oCurrent_X > 0) ? iGreen : 0 ;
+assign oVGA_B = (oCurrent_X > 0) ? iBlue : 0 ;
+
+assign oCurrent_X = (H_Cont>=H_BLANK) ? H_Cont-H_BLANK : 11'h0 ;
+assign oCurrent_Y = (V_Cont>=V_BLANK) ? V_Cont-V_BLANK : 11'h0 ;
+
+//reg [9:0] V_ACT;
+//reg [9:0] V_TOTAL;
+
+reg [7:0] btn_cnt;
+
+always@(posedge les_btn)
+begin
+ btn_cnt= btn_cnt +8'h1;
+end
+
+// Horizontal Generator: Refer to the pixel clock
+always@(posedge iCLK or negedge iRST_N)
+begin
+ if(!iRST_N)
+ begin
+ H_Cont <= 0;
+ oVGA_HS <= 1;
+// V_ACT <= 480 +btn_cnt;
+ // V_TOTAL = V_FRONT+V_SYNC+V_BACK+V_ACT;
+ end
+ else
+ begin
+// if(H_Cont0 )
+begin
+ TreeTemplate #( TREE_LEVEL-1 ) leftSubtree ( );
+ TreeTemplate #( TREE_LEVEL-1 ) rightSubtree ( );
+end
+endgenerate
+
+endmodule
+
+
+// here is the real implementation
+
+module Sorting_Tree ( clk, hold, is_input, data_in, data_out );
+
+parameter HBIT= 15;
+
+parameter R_SZ= 256;
+parameter TREE_LEVEL= 4;
+
+input clk;
+input hold;
+input is_input;
+
+input [HBIT:0] data_in;
+output [HBIT:0] data_out;
+wire [HBIT:0] in_next= lead_1 ? d_out1 : d_out2;
+
+wire [HBIT:0] d_out1;
+wire [HBIT:0] d_out2;
+
+generate
+if ( TREE_LEVEL >0 )
+begin
+ Cell_Compare #( HBIT ) top_buf ( clk, hold, is_input, data_in, in_next, data_out );
+ Sorting_Tree #( HBIT, R_SZ/2, TREE_LEVEL-1 ) cstack1 ( clk, hold1, is_input, data_out, d_out1 );
+ Sorting_Tree #( HBIT, (R_SZ-1)/2, TREE_LEVEL-1 ) cstack2 ( clk, hold2, is_input, data_out, d_out2 );
+end
+else
+begin
+ Sorting_Stack #( HBIT, R_SZ ) leaf ( clk, hold, is_input, data_in, data_out );
+end
+endgenerate
+
+bit flipper;
+
+wire lead_1= ( d_out1 > d_out2 );
+wire hold1= hold | ~( is_input ? flipper : lead_1 );
+wire hold2= hold | ( is_input ? flipper : lead_1 );
+
+always@(posedge clk )
+if (~hold)
+begin
+ if (is_input)
+ begin
+ flipper <= ~flipper;
+ end
+end
+
+endmodule
+
+
+
Index: numbert_sort_device/trunk/main/dynamic_tree.sv
===================================================================
--- numbert_sort_device/trunk/main/dynamic_tree.sv (nonexistent)
+++ numbert_sort_device/trunk/main/dynamic_tree.sv (revision 2)
@@ -0,0 +1,114 @@
+//
+//
+//module Dynamic_Tree ( clk, glob_com, data_in, data_out );
+//
+//parameter HBIT= 15;
+//
+//parameter X_SZ= 8;
+//parameter Y_SZ= 8;
+//
+//input clk;
+//input [1:0]glob_com;
+//
+//input [HBIT:0] data_in;
+//output [HBIT:0] data_out;
+//
+//wire [HBIT:0] in_prev;
+//wire [HBIT:0] in_next;
+//wire [HBIT:0] out;
+//
+//
+//
+//endmodule
+//
+//
+//
+//typedef struct {
+//bit [1] com;
+//bit [15:0] dat;
+//} CDT_port;
+//
+//module Cell_Dyna_Tree ( clk, glob_com, stageGlb, is_input, in_prev, in_next, out );
+//
+//parameter HBIT= 15;
+//
+//
+//input clk;
+//input glob_com;
+//
+//input stageGlb[3:0];
+//input candidateActive[3:0];
+//
+//input parentPtr[3:0];
+//input [HBIT:0] pntInQuestMsg [3:0];
+//input [HBIT:0] cldInQuestMsg [3:0];
+//output active = |parentPtr;
+//output [HBIT:0] message;
+//
+//output bit leftPtr [3:0];
+//output bit rightPtr[3:0];
+//
+//wire leftRq; // have left subtree
+//wire rightRq; // have right subtree
+//
+////wire parentMsg= pntInQuestMsg[];
+//
+//Cell_DT_Inner #( HBIT ) inner ( clk, glob_com, parentMsg, leftMsg, rightMsg, message );
+//
+//always@(posedge clk )
+//begin
+// if ( leftRq )
+// begin
+// if ( leftPtr==0 ) // new child required
+// begin
+// if ( stageGlb & ~candidateActive )
+// begin
+// leftPtr<= stageGlb;
+// end
+// end
+// end
+// else
+// begin
+// leftPtr<= 0;
+// end
+// if (~hold)
+// begin
+// higher <= ( cand_h > cand_l ) ? cand_h : cand_l;
+// lower <= ( cand_h > cand_l ) ? cand_l : cand_h;
+// end
+//end
+//endmodule
+//
+//
+//module Cell_DT_Inner ( clk, glob_com, parentMsg, leftMsg, rightMsg, message );
+//parameter HBIT= 15;
+//
+//input clk;
+//input [1:0]glob_com;
+//
+//input [HBIT:0] parentMsg;
+//input [HBIT:0] leftMsg;
+//input [HBIT:0] rightMsg;
+//output [HBIT:0] message;
+//
+//reg [HBIT:0] store;
+//reg [HBIT:0] tmp;
+//
+//always@(posedge clk )
+//begin
+// case( glob_com )
+// 2'h0: ;
+// 2'h1: ;
+// 2'h2:
+// begin
+// higher <= ( cand_h > cand_l ) ? cand_h : cand_l;
+// lower <= ( cand_h > cand_l ) ? cand_l : cand_h;
+// end
+// 2'h3: ;
+// endcase
+//end
+//
+//endmodule
+//
+//
+//
Index: numbert_sort_device/trunk/main/stack_sorter.sv
===================================================================
--- numbert_sort_device/trunk/main/stack_sorter.sv (nonexistent)
+++ numbert_sort_device/trunk/main/stack_sorter.sv (revision 2)
@@ -0,0 +1,105 @@
+
+////////////////////////////////////////////////////////////
+//
+// number sorting device, sequential, O(N)
+//
+// autor: Alexey Birukov, leshabirukov@opencores.org
+// license: LGPL
+//
+// notes:
+// reset signal is not implemented, to make reset wait R_SZ clocks
+// while hold==0 and is_input==0 to empty the buffer
+// or implement reset signal by yourself
+//
+// to make sorting in increasing order, use module call like this:
+// Sorting_Stack #(HBIT,R_SZ) cstack ( clk, hold, is_input, -1-data_in, _data_out );
+// wire [HBIT:0] data_out= -1-_data_out;
+//
+////////////////////////////////////////////////////////////
+
+// linear buffer implementation
+// sequential, stable, can be partly readed, decreasing order
+// reset signal is not implemented, to make reset wait R_SZ clocks
+// while hold==0 and is_input==0
+
+// see sort_stack_algorithm.png to catch the idea
+
+
+
+module Sorting_Stack ( clk, hold, is_input, data_in, data_out );
+
+parameter HBIT= 15; // size of number in bits
+parameter R_SZ= 256; // capacity, max sequence size
+
+parameter _R_SZ= (R_SZ+1)/2; // not to modify
+
+input clk;
+input hold; // 1 - to freeze state
+input is_input; // 1 - while loading
+
+input [HBIT:0] data_in; // load one number at a clock
+output [HBIT:0] data_out; // while is_input==0, max value popping out here
+
+wire [HBIT:0] in_prev[_R_SZ];
+wire [HBIT:0] in_next[_R_SZ];
+wire [HBIT:0] out[_R_SZ];
+
+// storage
+Cell_Compare #(HBIT) ribbon[_R_SZ] ( clk, hold, is_input, in_prev, in_next, out );
+
+// wiring
+generate
+ genvar i,j;
+ for (i=0; i<_R_SZ-1; i=i+1)
+ begin : block_name01
+ assign in_prev[i+1]= out[i];
+ assign in_next[i]= out[i+1];
+ end
+ assign in_prev[0]= data_in;
+ assign data_out= out[0];
+ assign in_next[_R_SZ-1]= 0;
+endgenerate
+
+endmodule
+
+
+
+
+
+
+
+
+module Cell_Compare ( clk, hold, is_input, in_prev, in_next, out );
+
+parameter HBIT= 15;
+
+
+input clk;
+input hold;
+
+input is_input;
+
+input [HBIT:0] in_prev;
+input [HBIT:0] in_next;
+
+output [HBIT:0] out= is_input ? lower : higher;
+
+bit [HBIT:0] higher;
+bit [HBIT:0] lower;
+
+wire [HBIT:0] cand_h= is_input ? higher : lower;
+wire [HBIT:0] cand_l= is_input ? in_prev : in_next;
+
+always@(posedge clk )
+if (~hold)
+begin
+ higher <= ( cand_h >= cand_l ) ? cand_h : cand_l;
+ lower <= ( cand_h >= cand_l ) ? cand_l : cand_h;
+end
+endmodule
+
+
+
+
+
+
Index: numbert_sort_device/trunk/main/high_end.sv
===================================================================
--- numbert_sort_device/trunk/main/high_end.sv (nonexistent)
+++ numbert_sort_device/trunk/main/high_end.sv (revision 2)
@@ -0,0 +1,317 @@
+
+
+
+module Cell_life ( clk, cell_rst, in_mm, in_m0, in_mp,
+ in_0m, in_0p,
+ in_pm, in_p0, in_pp, init,
+ state );
+
+input clk;
+input cell_rst;
+
+input in_mm;
+input in_m0;
+input in_mp;
+input in_0m;
+input in_0p;
+input in_pm;
+input in_p0;
+input in_pp;
+input init;
+
+output reg state;
+
+
+always@(posedge clk )
+begin
+ if ( cell_rst )
+ begin
+ state<= init;
+ end
+ else
+ begin
+ state <= (state | ( in_mm+ in_m0+ in_mp+
+ in_0m+ in_0p+
+ in_pm+ in_p0+ in_pp ))==3;
+ end
+end
+endmodule
+
+
+
+
+module VGA_HighEnd ( clk, rst,
+ iX_video, iY_video,
+ oR_video, oG_video, oB_video,
+ tumblers, endFrame, dbg_val );
+
+parameter RES_X_H= 1240;
+parameter RES_Y_H= 1024;
+parameter XY_STEP_H= 7;
+parameter RES_X_L= 640;
+parameter RES_Y_L= 480;
+parameter XY_STEP_L= 8;
+
+input clk;
+input rst;
+
+input signed [11:0] iX_video;
+input signed [11:0] iY_video;
+output reg [7:0] oR_video;
+output reg [7:0] oG_video;
+output reg [7:0] oB_video;
+input [9:0] tumblers;
+input endFrame;
+output wire [63:0] dbg_val= count;
+
+wire [31:0] V_out2;
+
+wire high_res= 1;
+
+reg [31:0] count;
+reg [31:0] count_py;
+
+
+parameter R_SZ= 27;
+parameter R_SZp= R_SZ +1;
+
+wire cell_out[R_SZ:0][R_SZ:0];
+
+wire cell_in_mm[R_SZ:0][R_SZ:0];
+wire cell_in_m0[R_SZ:0][R_SZ:0];
+wire cell_in_mp[R_SZ:0][R_SZ:0];
+
+wire cell_in_0m[R_SZ:0][R_SZ:0];
+wire cell_in_0p[R_SZ:0][R_SZ:0];
+
+wire cell_in_pm[R_SZ:0][R_SZ:0];
+wire cell_in_p0[R_SZ:0][R_SZ:0];
+wire cell_in_pp[R_SZ:0][R_SZ:0];
+
+wire ribbon_init[R_SZ:0][R_SZ:0];
+//wire [R_SZ:0] token_in;
+//wire [R_SZ:0] token_out;
+wire cell_rst= (iY_video==1);
+wire cell_clk= (iX_video==1 && iY_video %R_SZp==1);
+
+Cell_life ribbon[R_SZ:0][R_SZ:0] ( cell_clk, cell_rst, cell_in_mm, cell_in_m0, cell_in_mp,
+ cell_in_0m, cell_in_0p,
+ cell_in_pm, cell_in_p0, cell_in_pp, ribbon_init, cell_out );
+
+generate
+ genvar i,j;
+ for (i=0; i<=R_SZ; i=i+1)
+ begin : block_name01
+ for (j=0; j<=R_SZ; j=j+1)
+ begin : block_name02
+ if ( i==R_SZp/2 && j>=8 && j<24 )
+ assign ribbon_init[i][j]= 1;
+ else if ( i==R_SZp/2 && j>=3 && j<24 )
+ assign ribbon_init[i][j]= tumblers[j-3];
+ else
+ assign ribbon_init[i][j]= 0;
+ end
+ end
+
+ for (i=0; i<=R_SZ; i=i+1)
+ begin : block_name1
+ for (j=0; j
numbert_sort_device/trunk/sort_stack_algorithm.png
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: numbert_sort_device/trunk/altera/VGA_CLK.v
===================================================================
--- numbert_sort_device/trunk/altera/VGA_CLK.v (nonexistent)
+++ numbert_sort_device/trunk/altera/VGA_CLK.v (revision 2)
@@ -0,0 +1,306 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll
+
+// ============================================================
+// File Name: VGA_CLK.v
+// Megafunction Name(s):
+// altpll
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 8.0 Build 231 07/10/2008 SP 1 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2008 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module VGA_CLK (
+ inclk0,
+ c0);
+
+ parameter PLL_MUL = 1;
+ parameter PLL_DIV = 2;
+
+ input inclk0;
+ output c0;
+
+ wire [4:0] sub_wire0;
+ wire [0:0] sub_wire4 = 1'h0;
+ wire [0:0] sub_wire1 = sub_wire0[0:0];
+ wire c0 = sub_wire1;
+ wire sub_wire2 = inclk0;
+ wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
+
+ altpll altpll_component (
+ .inclk (sub_wire3),
+ .clk (sub_wire0),
+ .activeclock (),
+ .areset (1'b0),
+ .clkbad (),
+ .clkena ({6{1'b1}}),
+ .clkloss (),
+ .clkswitch (1'b0),
+ .configupdate (1'b0),
+ .enable0 (),
+ .enable1 (),
+ .extclk (),
+ .extclkena ({4{1'b1}}),
+ .fbin (1'b1),
+ .fbmimicbidir (),
+ .fbout (),
+ .locked (),
+ .pfdena (1'b1),
+ .phasecounterselect ({4{1'b1}}),
+ .phasedone (),
+ .phasestep (1'b1),
+ .phaseupdown (1'b1),
+ .pllena (1'b1),
+ .scanaclr (1'b0),
+ .scanclk (1'b0),
+ .scanclkena (1'b1),
+ .scandata (1'b0),
+ .scandataout (),
+ .scandone (),
+ .scanread (1'b0),
+ .scanwrite (1'b0),
+ .sclkout0 (),
+ .sclkout1 (),
+ .vcooverrange (),
+ .vcounderrange ());
+ defparam
+ altpll_component.bandwidth_type = "AUTO",
+ altpll_component.clk0_divide_by = PLL_DIV,
+ altpll_component.clk0_duty_cycle = 50,
+ altpll_component.clk0_multiply_by = PLL_MUL,
+// altpll_component.clk0_divide_by = 25, // äëÿ 1280õ1024
+// altpll_component.clk0_duty_cycle = 50,
+// altpll_component.clk0_multiply_by = 54,
+ altpll_component.clk0_phase_shift = "0",
+ altpll_component.compensate_clock = "CLK0",
+ altpll_component.inclk0_input_frequency = 20000,
+ altpll_component.intended_device_family = "Cyclone III",
+ altpll_component.lpm_hint = "CBX_MODULE_PREFIX=VGA_CLK",
+ altpll_component.lpm_type = "altpll",
+ altpll_component.operation_mode = "NORMAL",
+ altpll_component.pll_type = "Fast",
+ altpll_component.port_activeclock = "PORT_UNUSED",
+ altpll_component.port_areset = "PORT_UNUSED",
+ altpll_component.port_clkbad0 = "PORT_UNUSED",
+ altpll_component.port_clkbad1 = "PORT_UNUSED",
+ altpll_component.port_clkloss = "PORT_UNUSED",
+ altpll_component.port_clkswitch = "PORT_UNUSED",
+ altpll_component.port_configupdate = "PORT_UNUSED",
+ altpll_component.port_fbin = "PORT_UNUSED",
+ altpll_component.port_inclk0 = "PORT_USED",
+ altpll_component.port_inclk1 = "PORT_UNUSED",
+ altpll_component.port_locked = "PORT_UNUSED",
+ altpll_component.port_pfdena = "PORT_UNUSED",
+ altpll_component.port_phasecounterselect = "PORT_UNUSED",
+ altpll_component.port_phasedone = "PORT_UNUSED",
+ altpll_component.port_phasestep = "PORT_UNUSED",
+ altpll_component.port_phaseupdown = "PORT_UNUSED",
+ altpll_component.port_pllena = "PORT_UNUSED",
+ altpll_component.port_scanaclr = "PORT_UNUSED",
+ altpll_component.port_scanclk = "PORT_UNUSED",
+ altpll_component.port_scanclkena = "PORT_UNUSED",
+ altpll_component.port_scandata = "PORT_UNUSED",
+ altpll_component.port_scandataout = "PORT_UNUSED",
+ altpll_component.port_scandone = "PORT_UNUSED",
+ altpll_component.port_scanread = "PORT_UNUSED",
+ altpll_component.port_scanwrite = "PORT_UNUSED",
+ altpll_component.port_clk0 = "PORT_USED",
+ altpll_component.port_clk1 = "PORT_UNUSED",
+ altpll_component.port_clk2 = "PORT_UNUSED",
+ altpll_component.port_clk3 = "PORT_UNUSED",
+ altpll_component.port_clk4 = "PORT_UNUSED",
+ altpll_component.port_clk5 = "PORT_UNUSED",
+ altpll_component.port_clkena0 = "PORT_UNUSED",
+ altpll_component.port_clkena1 = "PORT_UNUSED",
+ altpll_component.port_clkena2 = "PORT_UNUSED",
+ altpll_component.port_clkena3 = "PORT_UNUSED",
+ altpll_component.port_clkena4 = "PORT_UNUSED",
+ altpll_component.port_clkena5 = "PORT_UNUSED",
+ altpll_component.port_extclk0 = "PORT_UNUSED",
+ altpll_component.port_extclk1 = "PORT_UNUSED",
+ altpll_component.port_extclk2 = "PORT_UNUSED",
+ altpll_component.port_extclk3 = "PORT_UNUSED",
+ altpll_component.width_clock = 5;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "2"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "VGA_CLK.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "Fast"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL VGA_CLK.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL VGA_CLK.ppf TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL VGA_CLK.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL VGA_CLK.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL VGA_CLK.bsf TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL VGA_CLK_inst.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL VGA_CLK_bb.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL VGA_CLK_waveforms.html TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL VGA_CLK_wave*.jpg FALSE FALSE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: CBX_MODULE_PREFIX: ON
Index: numbert_sort_device/trunk/boards/DE0/DE0_VGA.v
===================================================================
--- numbert_sort_device/trunk/boards/DE0/DE0_VGA.v (nonexistent)
+++ numbert_sort_device/trunk/boards/DE0/DE0_VGA.v (revision 2)
@@ -0,0 +1,328 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2009 by Terasic Technologies Inc.
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+// Terasic grants permission to use and modify this code for use
+// in synthesis for all Terasic Development Boards and Altera Development
+// Kits made by Terasic. Other use of this code, including the selling
+// ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+// This VHDL/Verilog or C/C++ source code is intended as a design reference
+// which illustrates how these types of functions can be implemented.
+// It is the user's responsibility to verify their design for
+// consistency and functionality through the use of formal
+// verification methods. Terasic provides no warranty regarding the use
+// or functionality of this code.
+//
+// --------------------------------------------------------------------
+//
+// Terasic Technologies Inc
+// 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+// HsinChu County, Taiwan
+// 302
+//
+// web: http://www.terasic.com/
+// email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions: DE0 VGA
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+// Ver :| Author :| Mod. Date :| Changes Made:
+
+// --------------------------------------------------------------------
+
+
+module DE0_VGA
+ (
+ //////////////////// Clock Input ////////////////////
+ CLOCK_50, // 50 MHz
+ CLOCK_50_2, // 50 MHz
+ //////////////////// Push Button ////////////////////
+ BUTTON, // Pushbutton[2:0]
+ //////////////////// DPDT Switch ////////////////////
+ SW, // Toggle Switch[9:0]
+ //////////////////// 7-SEG Dispaly ////////////////////
+ HEX0_D, // Seven Segment Digit 0
+ HEX0_DP, // Seven Segment Digit DP 0
+ HEX1_D, // Seven Segment Digit 1
+ HEX1_DP, // Seven Segment Digit DP 1
+ HEX2_D, // Seven Segment Digit 2
+ HEX2_DP, // Seven Segment Digit DP 2
+ HEX3_D, // Seven Segment Digit 3
+ HEX3_DP, // Seven Segment Digit DP 3
+ //////////////////////// LED ////////////////////////
+ LEDG, // LED Green[9:0]
+ //////////////////////// UART ////////////////////////
+ UART_TXD, // UART Transmitter
+ UART_RXD, // UART Receiver
+ UART_CTS, // UART Clear To Send
+ UART_RTS, // UART Request To Send
+ ///////////////////// SDRAM Interface ////////////////
+ DRAM_DQ, // SDRAM Data bus 16 Bits
+ DRAM_ADDR, // SDRAM Address bus 13 Bits
+ DRAM_LDQM, // SDRAM Low-byte Data Mask
+ DRAM_UDQM, // SDRAM High-byte Data Mask
+ DRAM_WE_N, // SDRAM Write Enable
+ DRAM_CAS_N, // SDRAM Column Address Strobe
+ DRAM_RAS_N, // SDRAM Row Address Strobe
+ DRAM_CS_N, // SDRAM Chip Select
+ DRAM_BA_0, // SDRAM Bank Address 0
+ DRAM_BA_1, // SDRAM Bank Address 1
+ DRAM_CLK, // SDRAM Clock
+ DRAM_CKE, // SDRAM Clock Enable
+ //////////////////// Flash Interface ////////////////
+ FL_DQ, // FLASH Data bus 15 Bits
+ FL_DQ15_AM1, // FLASH Data bus Bit 15 or Address A-1
+ FL_ADDR, // FLASH Address bus 22 Bits
+ FL_WE_N, // FLASH Write Enable
+ FL_RST_N, // FLASH Reset
+ FL_OE_N, // FLASH Output Enable
+ FL_CE_N, // FLASH Chip Enable
+ FL_WP_N, // FLASH Hardware Write Protect
+ FL_BYTE_N, // FLASH Selects 8/16-bit mode
+ FL_RY, // FLASH Ready/Busy
+ //////////////////// LCD Module 16X2 ////////////////
+ LCD_BLON, // LCD Back Light ON/OFF
+ LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
+ LCD_EN, // LCD Enable
+ LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
+ LCD_DATA, // LCD Data bus 8 bits
+ //////////////////// SD_Card Interface ////////////////
+ SD_DAT0, // SD Card Data 0
+ SD_DAT3, // SD Card Data 3
+ SD_CMD, // SD Card Command Signal
+ SD_CLK, // SD Card Clock
+ SD_WP_N, // SD Card Write Protect
+ //////////////////// PS2 ////////////////////////////
+ PS2_KBDAT, // PS2 Keyboard Data
+ PS2_KBCLK, // PS2 Keyboard Clock
+ PS2_MSDAT, // PS2 Mouse Data
+ PS2_MSCLK, // PS2 Mouse Clock
+ //////////////////// VGA ////////////////////////////
+ VGA_HS, // VGA H_SYNC
+ VGA_VS, // VGA V_SYNC
+ VGA_R, // VGA Red[3:0]
+ VGA_G, // VGA Green[3:0]
+ VGA_B, // VGA Blue[3:0]
+ //////////////////// GPIO ////////////////////////////
+ GPIO0_CLKIN, // GPIO Connection 0 Clock In Bus
+ GPIO0_CLKOUT, // GPIO Connection 0 Clock Out Bus
+ GPIO0_D, // GPIO Connection 0 Data Bus
+ GPIO1_CLKIN, // GPIO Connection 1 Clock In Bus
+ GPIO1_CLKOUT, // GPIO Connection 1 Clock Out Bus
+ GPIO1_D // GPIO Connection 1 Data Bus
+ );
+
+parameter R_SZ= 128;
+
+
+//////////////////////// Clock Input ////////////////////////
+input CLOCK_50; // 50 MHz
+input CLOCK_50_2; // 50 MHz
+//////////////////////// Push Button ////////////////////////
+input [2:0] BUTTON; // Pushbutton[2:0]
+//////////////////////// DPDT Switch ////////////////////////
+input [9:0] SW; // Toggle Switch[9:0]
+//////////////////////// 7-SEG Dispaly ////////////////////////
+output [6:0] HEX0_D; // Seven Segment Digit 0
+output HEX0_DP; // Seven Segment Digit DP 0
+output [6:0] HEX1_D; // Seven Segment Digit 1
+output HEX1_DP; // Seven Segment Digit DP 1
+output [6:0] HEX2_D; // Seven Segment Digit 2
+output HEX2_DP; // Seven Segment Digit DP 2
+output [6:0] HEX3_D; // Seven Segment Digit 3
+output HEX3_DP; // Seven Segment Digit DP 3
+//////////////////////////// LED ////////////////////////////
+output [9:0] LEDG; // LED Green[9:0]
+//////////////////////////// UART ////////////////////////////
+output UART_TXD; // UART Transmitter
+input UART_RXD; // UART Receiver
+output UART_CTS; // UART Clear To Send
+input UART_RTS; // UART Request To Send
+/////////////////////// SDRAM Interface ////////////////////////
+inout [15:0] DRAM_DQ; // SDRAM Data bus 16 Bits
+output [12:0] DRAM_ADDR; // SDRAM Address bus 13 Bits
+output DRAM_LDQM; // SDRAM Low-byte Data Mask
+output DRAM_UDQM; // SDRAM High-byte Data Mask
+output DRAM_WE_N; // SDRAM Write Enable
+output DRAM_CAS_N; // SDRAM Column Address Strobe
+output DRAM_RAS_N; // SDRAM Row Address Strobe
+output DRAM_CS_N; // SDRAM Chip Select
+output DRAM_BA_0; // SDRAM Bank Address 0
+output DRAM_BA_1; // SDRAM Bank Address 1
+output DRAM_CLK; // SDRAM Clock
+output DRAM_CKE; // SDRAM Clock Enable
+//////////////////////// Flash Interface ////////////////////////
+inout [14:0] FL_DQ; // FLASH Data bus 15 Bits
+inout FL_DQ15_AM1; // FLASH Data bus Bit 15 or Address A-1
+output [21:0] FL_ADDR; // FLASH Address bus 22 Bits
+output FL_WE_N; // FLASH Write Enable
+output FL_RST_N; // FLASH Reset
+output FL_OE_N; // FLASH Output Enable
+output FL_CE_N; // FLASH Chip Enable
+output FL_WP_N; // FLASH Hardware Write Protect
+output FL_BYTE_N; // FLASH Selects 8/16-bit mode
+input FL_RY; // FLASH Ready/Busy
+//////////////////// LCD Module 16X2 ////////////////////////////
+inout [7:0] LCD_DATA; // LCD Data bus 8 bits
+output LCD_BLON; // LCD Back Light ON/OFF
+output LCD_RW; // LCD Read/Write Select, 0 = Write, 1 = Read
+output LCD_EN; // LCD Enable
+output LCD_RS; // LCD Command/Data Select, 0 = Command, 1 = Data
+//////////////////// SD Card Interface ////////////////////////
+inout SD_DAT0; // SD Card Data 0
+inout SD_DAT3; // SD Card Data 3
+inout SD_CMD; // SD Card Command Signal
+output SD_CLK; // SD Card Clock
+input SD_WP_N; // SD Card Write Protect
+//////////////////////// PS2 ////////////////////////////////
+inout PS2_KBDAT; // PS2 Keyboard Data
+inout PS2_KBCLK; // PS2 Keyboard Clock
+inout PS2_MSDAT; // PS2 Mouse Data
+inout PS2_MSCLK; // PS2 Mouse Clock
+//////////////////////// VGA ////////////////////////////
+output VGA_HS; // VGA H_SYNC
+output VGA_VS; // VGA V_SYNC
+output [3:0] VGA_R; // VGA Red[3:0]
+output [3:0] VGA_G; // VGA Green[3:0]
+output [3:0] VGA_B; // VGA Blue[3:0]
+//////////////////////// GPIO ////////////////////////////////
+input [1:0] GPIO0_CLKIN; // GPIO Connection 0 Clock In Bus
+output [1:0] GPIO0_CLKOUT; // GPIO Connection 0 Clock Out Bus
+inout [31:0] GPIO0_D; // GPIO Connection 0 Data Bus
+input [1:0] GPIO1_CLKIN; // GPIO Connection 1 Clock In Bus
+output [1:0] GPIO1_CLKOUT; // GPIO Connection 1 Clock Out Bus
+inout [31:0] GPIO1_D; // GPIO Connection 1 Data Bus
+
+//=======================================================
+// REG/WIRE declarations
+//=======================================================
+// All inout port turn to tri-state
+assign DRAM_DQ = 16'hzzzz;
+assign FL_DQ = 16'hzzzz;
+assign LCD_DATA = 8'hzz;
+assign SD_DAT0 = 1'hz;
+assign SD_DAT3 = 1'hz;
+assign SD_CMD = 1'hz;
+assign PS2_KBDAT = 1'hz;
+assign PS2_KBCLK = 1'hz;
+assign PS2_MSDAT = 1'hz;
+assign PS2_MSCLK = 1'hz;
+assign GPIO0_D = 32'hzzzzzzzz;
+assign GPIO1_D = 32'hzzzzzzzz;
+
+//assign HEX0_D = 7'h7F;
+assign HEX0_DP = ~seg_first;
+//assign HEX1_D = 7'h7F;
+assign HEX1_DP = ~seg_first;
+//assign HEX2_D = 7'h7F;
+assign HEX2_DP = ~seg_first;
+//assign HEX3_D = 7'h7F;
+assign HEX3_DP = ~seg_first;
+
+assign LEDG = 10'h000;
+//////////////////////// VGA ////////////////////////////
+wire VGA_CTRL_CLK;
+wire [11:0] mVGA_X;
+wire [11:0] mVGA_Y;
+wire [9:0] mVGA_R;
+wire [9:0] mVGA_G;
+wire [9:0] mVGA_B;
+
+wire [9:0] sVGA_R;
+wire [9:0] sVGA_G;
+wire [9:0] sVGA_B;
+assign VGA_R = sVGA_R[7:4];
+assign VGA_G = sVGA_G[7:4];
+assign VGA_B = sVGA_B[7:4];
+
+//=======================================================
+// Structural coding
+//=======================================================
+
+//////////////////////// VGA ////////////////////////////
+
+
+VGA_CLK u1_1240x1024
+ ( .inclk0(CLOCK_50),
+ .c0(VGA_CTRL_CLK)
+ );
+ defparam u1_1240x1024.PLL_MUL= 54;
+ defparam u1_1240x1024.PLL_DIV= 25;
+
+
+VGA_Ctrl u2_1240x1024
+ ( // Host Side
+ .oCurrent_X(mVGA_X),
+ .oCurrent_Y(mVGA_Y),
+ .iRed(mVGA_R),
+ .iGreen(mVGA_G),
+ .iBlue(mVGA_B),
+ // VGA Side
+ .oVGA_R(sVGA_R),
+ .oVGA_G(sVGA_G),
+ .oVGA_B(sVGA_B),
+ .oVGA_HS(VGA_HS),
+ .oVGA_VS(VGA_VS),
+ .oVGA_SYNC(),
+ .oVGA_BLANK(),
+ .oVGA_CLOCK(),
+ // Control Signal
+ .iCLK(VGA_CTRL_CLK),
+ .iRST_N(BUTTON[0]),
+ .les_btn(BUTTON[1])
+ );
+ defparam u2_1240x1024.H_FRONT = 48;
+ defparam u2_1240x1024.H_SYNC = 112;
+ defparam u2_1240x1024.H_BACK = 248;
+ defparam u2_1240x1024.H_ACT = 1280;
+ defparam u2_1240x1024.V_FRONT = 1;
+ defparam u2_1240x1024.V_SYNC = 3;
+ defparam u2_1240x1024.V_BACK = 38;
+ defparam u2_1240x1024.V_ACT = 1024;
+
+wire [63:0] dbg_val;
+
+VGA_Pattern #( R_SZ ) u3
+ ( // Read Out Side
+ .oRed(mVGA_R),
+ .oGreen(mVGA_G),
+ .oBlue(mVGA_B),
+ .iVGA_X(mVGA_X),
+ .iVGA_Y(mVGA_Y),
+ .iVGA_CLK(VGA_CTRL_CLK),
+ // Control Signals
+ .iRST_n(BUTTON[0]),
+ .iColor_SW(SW),
+ .endFrame(VGA_VS),
+ .dbg_val(dbg_val)
+ );
+
+wire [15:0] indicated_part;
+wire seg_first;
+
+dbg_7seg dbg_num
+ ( .val( dbg_val ),
+ .show_next(BUTTON[1]),
+ .part( indicated_part ),
+ .is_first( seg_first ) );
+
+SEG7_LUT_4 u0
+ ( .oSEG0(HEX0_D),
+ .oSEG1(HEX1_D),
+ .oSEG2(HEX2_D),
+ .oSEG3(HEX3_D),
+ .iDIG( indicated_part )
+ );
+
+
+endmodule
\ No newline at end of file
Index: numbert_sort_device/trunk/boards/DE0/DE0_VGA.qpf
===================================================================
--- numbert_sort_device/trunk/boards/DE0/DE0_VGA.qpf (nonexistent)
+++ numbert_sort_device/trunk/boards/DE0/DE0_VGA.qpf (revision 2)
@@ -0,0 +1,23 @@
+# Copyright (C) 1991-2008 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+
+
+
+QUARTUS_VERSION = "8.0"
+DATE = "07:49:21 May 01, 2009"
+
+
+# Revisions
+
+PROJECT_REVISION = "DE0_VGA"
Index: numbert_sort_device/trunk/boards/DE0/DE0_VGA.sof
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: numbert_sort_device/trunk/boards/DE0/DE0_VGA.sof
===================================================================
--- numbert_sort_device/trunk/boards/DE0/DE0_VGA.sof (nonexistent)
+++ numbert_sort_device/trunk/boards/DE0/DE0_VGA.sof (revision 2)
numbert_sort_device/trunk/boards/DE0/DE0_VGA.sof
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: numbert_sort_device/trunk/boards/DE0/DE0_VGA.qsf
===================================================================
--- numbert_sort_device/trunk/boards/DE0/DE0_VGA.qsf (nonexistent)
+++ numbert_sort_device/trunk/boards/DE0/DE0_VGA.qsf (revision 2)
@@ -0,0 +1,563 @@
+# Copyright (C) 1991-2008 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+
+
+# The default values for assignments are stored in the file
+# DE0_VGA_assignment_defaults.qdf
+# If this file doesn't exist, and for assignments not listed, see file
+# assignment_defaults.qdf
+
+# Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C16F484C6
+set_global_assignment -name TOP_LEVEL_ENTITY DE0_VGA
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "07:49:21 MAY 01, 2009"
+set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 14622752 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_B1 -to LEDG[9]
+set_location_assignment PIN_B2 -to LEDG[8]
+set_location_assignment PIN_C2 -to LEDG[7]
+set_location_assignment PIN_C1 -to LEDG[6]
+set_location_assignment PIN_E1 -to LEDG[5]
+set_location_assignment PIN_F2 -to LEDG[4]
+set_location_assignment PIN_H1 -to LEDG[3]
+set_location_assignment PIN_J3 -to LEDG[2]
+set_location_assignment PIN_J2 -to LEDG[1]
+set_location_assignment PIN_J1 -to LEDG[0]
+set_location_assignment PIN_D2 -to SW[9]
+set_location_assignment PIN_E4 -to SW[8]
+set_location_assignment PIN_E3 -to SW[7]
+set_location_assignment PIN_H7 -to SW[6]
+set_location_assignment PIN_J7 -to SW[5]
+set_location_assignment PIN_G5 -to SW[4]
+set_location_assignment PIN_G4 -to SW[3]
+set_location_assignment PIN_H6 -to SW[2]
+set_location_assignment PIN_H5 -to SW[1]
+set_location_assignment PIN_J6 -to SW[0]
+set_location_assignment PIN_F1 -to BUTTON[2]
+set_location_assignment PIN_G3 -to BUTTON[1]
+set_location_assignment PIN_H2 -to BUTTON[0]
+set_location_assignment PIN_R2 -to FL_ADDR[21]
+set_location_assignment PIN_P3 -to FL_ADDR[20]
+set_location_assignment PIN_P1 -to FL_ADDR[19]
+set_location_assignment PIN_M6 -to FL_ADDR[18]
+set_location_assignment PIN_M5 -to FL_ADDR[17]
+set_location_assignment PIN_AA2 -to FL_ADDR[16]
+set_location_assignment PIN_L6 -to FL_ADDR[15]
+set_location_assignment PIN_L7 -to FL_ADDR[14]
+set_location_assignment PIN_M1 -to FL_ADDR[13]
+set_location_assignment PIN_M2 -to FL_ADDR[12]
+set_location_assignment PIN_M3 -to FL_ADDR[11]
+set_location_assignment PIN_N1 -to FL_ADDR[10]
+set_location_assignment PIN_N2 -to FL_ADDR[9]
+set_location_assignment PIN_P2 -to FL_ADDR[8]
+set_location_assignment PIN_M4 -to FL_ADDR[7]
+set_location_assignment PIN_M8 -to FL_ADDR[6]
+set_location_assignment PIN_N6 -to FL_ADDR[5]
+set_location_assignment PIN_N5 -to FL_ADDR[4]
+set_location_assignment PIN_N7 -to FL_ADDR[3]
+set_location_assignment PIN_P6 -to FL_ADDR[2]
+set_location_assignment PIN_P5 -to FL_ADDR[1]
+set_location_assignment PIN_P7 -to FL_ADDR[0]
+set_location_assignment PIN_AA1 -to FL_BYTE_N
+set_location_assignment PIN_N8 -to FL_CE_N
+set_location_assignment PIN_R7 -to FL_DQ[0]
+set_location_assignment PIN_P8 -to FL_DQ[1]
+set_location_assignment PIN_R8 -to FL_DQ[2]
+set_location_assignment PIN_U1 -to FL_DQ[3]
+set_location_assignment PIN_V2 -to FL_DQ[4]
+set_location_assignment PIN_V3 -to FL_DQ[5]
+set_location_assignment PIN_W1 -to FL_DQ[6]
+set_location_assignment PIN_Y1 -to FL_DQ[7]
+set_location_assignment PIN_T5 -to FL_DQ[8]
+set_location_assignment PIN_T7 -to FL_DQ[9]
+set_location_assignment PIN_T4 -to FL_DQ[10]
+set_location_assignment PIN_U2 -to FL_DQ[11]
+set_location_assignment PIN_V1 -to FL_DQ[12]
+set_location_assignment PIN_V4 -to FL_DQ[13]
+set_location_assignment PIN_W2 -to FL_DQ[14]
+set_location_assignment PIN_R6 -to FL_OE_N
+set_location_assignment PIN_R1 -to FL_RST_N
+set_location_assignment PIN_M7 -to FL_RY
+set_location_assignment PIN_P4 -to FL_WE_N
+set_location_assignment PIN_T3 -to FL_WP_N
+set_location_assignment PIN_Y2 -to FL_DQ15_AM1
+set_location_assignment PIN_U7 -to GPIO0_D[31]
+set_location_assignment PIN_V5 -to GPIO0_D[30]
+set_location_assignment PIN_W6 -to GPIO0_D[29]
+set_location_assignment PIN_W7 -to GPIO0_D[28]
+set_location_assignment PIN_V8 -to GPIO0_D[27]
+set_location_assignment PIN_T8 -to GPIO0_D[26]
+set_location_assignment PIN_W10 -to GPIO0_D[25]
+set_location_assignment PIN_Y10 -to GPIO0_D[24]
+set_location_assignment PIN_V11 -to GPIO0_D[23]
+set_location_assignment PIN_R10 -to GPIO0_D[22]
+set_location_assignment PIN_V12 -to GPIO0_D[21]
+set_location_assignment PIN_U13 -to GPIO0_D[20]
+set_location_assignment PIN_W13 -to GPIO0_D[19]
+set_location_assignment PIN_Y13 -to GPIO0_D[18]
+set_location_assignment PIN_U14 -to GPIO0_D[17]
+set_location_assignment PIN_V14 -to GPIO0_D[16]
+set_location_assignment PIN_AA4 -to GPIO0_D[15]
+set_location_assignment PIN_AB4 -to GPIO0_D[14]
+set_location_assignment PIN_AA5 -to GPIO0_D[13]
+set_location_assignment PIN_AB5 -to GPIO0_D[12]
+set_location_assignment PIN_AA8 -to GPIO0_D[11]
+set_location_assignment PIN_AB8 -to GPIO0_D[10]
+set_location_assignment PIN_AA10 -to GPIO0_D[9]
+set_location_assignment PIN_AB10 -to GPIO0_D[8]
+set_location_assignment PIN_AA13 -to GPIO0_D[7]
+set_location_assignment PIN_AB13 -to GPIO0_D[6]
+set_location_assignment PIN_AB14 -to GPIO0_D[5]
+set_location_assignment PIN_AA14 -to GPIO0_D[4]
+set_location_assignment PIN_AB15 -to GPIO0_D[3]
+set_location_assignment PIN_AA15 -to GPIO0_D[2]
+set_location_assignment PIN_AA16 -to GPIO0_D[1]
+set_location_assignment PIN_AB16 -to GPIO0_D[0]
+set_location_assignment PIN_AB12 -to GPIO0_CLKIN[0]
+set_location_assignment PIN_AA12 -to GPIO0_CLKIN[1]
+set_location_assignment PIN_AB3 -to GPIO0_CLKOUT[0]
+set_location_assignment PIN_AA3 -to GPIO0_CLKOUT[1]
+set_location_assignment PIN_AA11 -to GPIO1_CLKIN[1]
+set_location_assignment PIN_AB11 -to GPIO1_CLKIN[0]
+set_location_assignment PIN_T16 -to GPIO1_CLKOUT[1]
+set_location_assignment PIN_R16 -to GPIO1_CLKOUT[0]
+set_location_assignment PIN_V7 -to GPIO1_D[31]
+set_location_assignment PIN_V6 -to GPIO1_D[30]
+set_location_assignment PIN_U8 -to GPIO1_D[29]
+set_location_assignment PIN_Y7 -to GPIO1_D[28]
+set_location_assignment PIN_T9 -to GPIO1_D[27]
+set_location_assignment PIN_U9 -to GPIO1_D[26]
+set_location_assignment PIN_T10 -to GPIO1_D[25]
+set_location_assignment PIN_U10 -to GPIO1_D[24]
+set_location_assignment PIN_R12 -to GPIO1_D[23]
+set_location_assignment PIN_R11 -to GPIO1_D[22]
+set_location_assignment PIN_T12 -to GPIO1_D[21]
+set_location_assignment PIN_U12 -to GPIO1_D[20]
+set_location_assignment PIN_R14 -to GPIO1_D[19]
+set_location_assignment PIN_T14 -to GPIO1_D[18]
+set_location_assignment PIN_AB7 -to GPIO1_D[17]
+set_location_assignment PIN_AA7 -to GPIO1_D[16]
+set_location_assignment PIN_AA9 -to GPIO1_D[15]
+set_location_assignment PIN_AB9 -to GPIO1_D[14]
+set_location_assignment PIN_V15 -to GPIO1_D[13]
+set_location_assignment PIN_W15 -to GPIO1_D[12]
+set_location_assignment PIN_T15 -to GPIO1_D[11]
+set_location_assignment PIN_U15 -to GPIO1_D[10]
+set_location_assignment PIN_W17 -to GPIO1_D[9]
+set_location_assignment PIN_Y17 -to GPIO1_D[8]
+set_location_assignment PIN_AB17 -to GPIO1_D[7]
+set_location_assignment PIN_AA17 -to GPIO1_D[6]
+set_location_assignment PIN_AA18 -to GPIO1_D[5]
+set_location_assignment PIN_AB18 -to GPIO1_D[4]
+set_location_assignment PIN_AB19 -to GPIO1_D[3]
+set_location_assignment PIN_AA19 -to GPIO1_D[2]
+set_location_assignment PIN_AB20 -to GPIO1_D[1]
+set_location_assignment PIN_AA20 -to GPIO1_D[0]
+set_location_assignment PIN_P22 -to PS2_KBCLK
+set_location_assignment PIN_P21 -to PS2_KBDAT
+set_location_assignment PIN_R21 -to PS2_MSCLK
+set_location_assignment PIN_R22 -to PS2_MSDAT
+set_location_assignment PIN_U22 -to UART_RXD
+set_location_assignment PIN_U21 -to UART_TXD
+set_location_assignment PIN_V22 -to UART_RTS
+set_location_assignment PIN_V21 -to UART_CTS
+set_location_assignment PIN_Y21 -to SD_CLK
+set_location_assignment PIN_Y22 -to SD_CMD
+set_location_assignment PIN_AA22 -to SD_DAT0
+set_location_assignment PIN_W21 -to SD_DAT3
+set_location_assignment PIN_W20 -to SD_WP_N
+set_location_assignment PIN_C20 -to LCD_DATA[7]
+set_location_assignment PIN_D20 -to LCD_DATA[6]
+set_location_assignment PIN_B21 -to LCD_DATA[5]
+set_location_assignment PIN_B22 -to LCD_DATA[4]
+set_location_assignment PIN_C21 -to LCD_DATA[3]
+set_location_assignment PIN_C22 -to LCD_DATA[2]
+set_location_assignment PIN_D21 -to LCD_DATA[1]
+set_location_assignment PIN_D22 -to LCD_DATA[0]
+set_location_assignment PIN_E22 -to LCD_RW
+set_location_assignment PIN_F22 -to LCD_RS
+set_location_assignment PIN_E21 -to LCD_EN
+set_location_assignment PIN_F21 -to LCD_BLON
+set_location_assignment PIN_J21 -to VGA_G[3]
+set_location_assignment PIN_K17 -to VGA_G[2]
+set_location_assignment PIN_J17 -to VGA_G[1]
+set_location_assignment PIN_H22 -to VGA_G[0]
+set_location_assignment PIN_L21 -to VGA_HS
+set_location_assignment PIN_L22 -to VGA_VS
+set_location_assignment PIN_H21 -to VGA_R[3]
+set_location_assignment PIN_H20 -to VGA_R[2]
+set_location_assignment PIN_H17 -to VGA_R[1]
+set_location_assignment PIN_H19 -to VGA_R[0]
+set_location_assignment PIN_K18 -to VGA_B[3]
+set_location_assignment PIN_J22 -to VGA_B[2]
+set_location_assignment PIN_K21 -to VGA_B[1]
+set_location_assignment PIN_K22 -to VGA_B[0]
+set_location_assignment PIN_G21 -to CLOCK_50
+set_location_assignment PIN_E11 -to HEX0_D[0]
+set_location_assignment PIN_F11 -to HEX0_D[1]
+set_location_assignment PIN_H12 -to HEX0_D[2]
+set_location_assignment PIN_H13 -to HEX0_D[3]
+set_location_assignment PIN_G12 -to HEX0_D[4]
+set_location_assignment PIN_F12 -to HEX0_D[5]
+set_location_assignment PIN_F13 -to HEX0_D[6]
+set_location_assignment PIN_D13 -to HEX0_DP
+set_location_assignment PIN_A15 -to HEX1_D[6]
+set_location_assignment PIN_E14 -to HEX1_D[5]
+set_location_assignment PIN_B14 -to HEX1_D[4]
+set_location_assignment PIN_A14 -to HEX1_D[3]
+set_location_assignment PIN_C13 -to HEX1_D[2]
+set_location_assignment PIN_B13 -to HEX1_D[1]
+set_location_assignment PIN_A13 -to HEX1_D[0]
+set_location_assignment PIN_B15 -to HEX1_DP
+set_location_assignment PIN_F14 -to HEX2_D[6]
+set_location_assignment PIN_B17 -to HEX2_D[5]
+set_location_assignment PIN_A17 -to HEX2_D[4]
+set_location_assignment PIN_E15 -to HEX2_D[3]
+set_location_assignment PIN_B16 -to HEX2_D[2]
+set_location_assignment PIN_A16 -to HEX2_D[1]
+set_location_assignment PIN_D15 -to HEX2_D[0]
+set_location_assignment PIN_A18 -to HEX2_DP
+set_location_assignment PIN_G15 -to HEX3_D[6]
+set_location_assignment PIN_D19 -to HEX3_D[5]
+set_location_assignment PIN_C19 -to HEX3_D[4]
+set_location_assignment PIN_B19 -to HEX3_D[3]
+set_location_assignment PIN_A19 -to HEX3_D[2]
+set_location_assignment PIN_F15 -to HEX3_D[1]
+set_location_assignment PIN_B18 -to HEX3_D[0]
+set_location_assignment PIN_G16 -to HEX3_DP
+set_location_assignment PIN_G8 -to DRAM_CAS_N
+set_location_assignment PIN_G7 -to DRAM_CS_N
+set_location_assignment PIN_E5 -to DRAM_CLK
+set_location_assignment PIN_E6 -to DRAM_CKE
+set_location_assignment PIN_B5 -to DRAM_BA_0
+set_location_assignment PIN_A4 -to DRAM_BA_1
+set_location_assignment PIN_F10 -to DRAM_DQ[15]
+set_location_assignment PIN_E10 -to DRAM_DQ[14]
+set_location_assignment PIN_A10 -to DRAM_DQ[13]
+set_location_assignment PIN_B10 -to DRAM_DQ[12]
+set_location_assignment PIN_C10 -to DRAM_DQ[11]
+set_location_assignment PIN_A9 -to DRAM_DQ[10]
+set_location_assignment PIN_B9 -to DRAM_DQ[9]
+set_location_assignment PIN_A8 -to DRAM_DQ[8]
+set_location_assignment PIN_F8 -to DRAM_DQ[7]
+set_location_assignment PIN_H9 -to DRAM_DQ[6]
+set_location_assignment PIN_G9 -to DRAM_DQ[5]
+set_location_assignment PIN_F9 -to DRAM_DQ[4]
+set_location_assignment PIN_E9 -to DRAM_DQ[3]
+set_location_assignment PIN_H10 -to DRAM_DQ[2]
+set_location_assignment PIN_G10 -to DRAM_DQ[1]
+set_location_assignment PIN_D10 -to DRAM_DQ[0]
+set_location_assignment PIN_E7 -to DRAM_LDQM
+set_location_assignment PIN_B8 -to DRAM_UDQM
+set_location_assignment PIN_F7 -to DRAM_RAS_N
+set_location_assignment PIN_D6 -to DRAM_WE_N
+set_location_assignment PIN_B12 -to CLOCK_50_2
+set_location_assignment PIN_C8 -to DRAM_ADDR[12]
+set_location_assignment PIN_A7 -to DRAM_ADDR[11]
+set_location_assignment PIN_B4 -to DRAM_ADDR[10]
+set_location_assignment PIN_B7 -to DRAM_ADDR[9]
+set_location_assignment PIN_C7 -to DRAM_ADDR[8]
+set_location_assignment PIN_A6 -to DRAM_ADDR[7]
+set_location_assignment PIN_B6 -to DRAM_ADDR[6]
+set_location_assignment PIN_C6 -to DRAM_ADDR[5]
+set_location_assignment PIN_A5 -to DRAM_ADDR[4]
+set_location_assignment PIN_C3 -to DRAM_ADDR[3]
+set_location_assignment PIN_B3 -to DRAM_ADDR[2]
+set_location_assignment PIN_A3 -to DRAM_ADDR[1]
+set_location_assignment PIN_C4 -to DRAM_ADDR[0]
+
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_CE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_BYTE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[29]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[30]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[31]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKOUT[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKOUT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKIN[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKIN[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[24]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[26]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[27]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[29]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[30]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[31]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKOUT[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKOUT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKIN[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKIN[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WP_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RY
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RST_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_OE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ15_AM1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[24]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[26]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[27]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_BLON
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_CTS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_WP_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CMD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_MSDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_MSCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RW
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_EN
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RTS
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
+set_global_assignment -name MISC_FILE "E:/DE0/DE0_VGA/DE0_VGA.dpf"
+set_global_assignment -name MISC_FILE "D:/TERASIC_TEST/DE0/DE0_VGA/DE0_VGA.dpf"
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
+set_global_assignment -name VERILOG_FILE ../../test_vga.v
+set_global_assignment -name SYSTEMVERILOG_FILE ../../main/tree_sorter.sv
+set_global_assignment -name SYSTEMVERILOG_FILE ../../main/stack_sorter.sv
+set_global_assignment -name SYSTEMVERILOG_FILE ../../main/high_end.sv
+set_global_assignment -name SYSTEMVERILOG_FILE ../../main/dynamic_tree.sv
+set_global_assignment -name VERILOG_FILE ../../utility/VGA_Ctrl.v
+set_global_assignment -name VERILOG_FILE ../../utility/SEG7_LUT.v
+set_global_assignment -name VERILOG_FILE ../../altera/VGA_CLK.v
+set_global_assignment -name VERILOG_FILE DE0_VGA.v
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
Index: numbert_sort_device/trunk/boards/DE0/DE0_VGA.sdc
===================================================================
--- numbert_sort_device/trunk/boards/DE0/DE0_VGA.sdc (nonexistent)
+++ numbert_sort_device/trunk/boards/DE0/DE0_VGA.sdc (revision 2)
@@ -0,0 +1,86 @@
+#**************************************************************
+# This .sdc file is created by Terasic Tool.
+# Users are recommended to modify this file to match users logic.
+#**************************************************************
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+create_clock -period 20 [get_ports CLOCK_50]
+create_clock -period 20 [get_ports CLOCK2_50]
+create_clock -period 20 [get_ports CLOCK3_50]
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+derive_pll_clocks
+
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+derive_clock_uncertainty
+
+
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Load
+#**************************************************************
+
+
+
Index: numbert_sort_device/trunk/boards/DE2-115/DE2_115_VGA.v
===================================================================
--- numbert_sort_device/trunk/boards/DE2-115/DE2_115_VGA.v (nonexistent)
+++ numbert_sort_device/trunk/boards/DE2-115/DE2_115_VGA.v (revision 2)
@@ -0,0 +1,202 @@
+
+//=======================================================
+// This code is generated by Terasic System Builder
+//=======================================================
+
+module DE2_115_VGA(
+
+ //////////// CLOCK //////////
+ CLOCK_50,
+ CLOCK2_50,
+ CLOCK3_50,
+
+ //////////// KEY //////////
+ KEY,
+
+ //////////// SW //////////
+ SW,
+
+ //////////// SEG7 //////////
+ HEX0,
+ HEX1,
+ HEX2,
+ HEX3,
+ HEX4,
+ HEX5,
+ HEX6,
+ HEX7,
+
+ //////////// VGA //////////
+ VGA_B,
+ VGA_BLANK_N,
+ VGA_CLK,
+ VGA_G,
+ VGA_HS,
+ VGA_R,
+ VGA_SYNC_N,
+ VGA_VS
+);
+
+//=======================================================
+// PARAMETER declarations
+//=======================================================
+
+parameter R_SZ= 512;
+
+
+//=======================================================
+// PORT declarations
+//=======================================================
+
+//////////// CLOCK //////////
+input CLOCK_50;
+input CLOCK2_50;
+input CLOCK3_50;
+
+//////////// KEY //////////
+input [3:0] KEY;
+
+//////////// SW //////////
+input [17:0] SW;
+
+//////////// SEG7 //////////
+output [6:0] HEX0;
+output [6:0] HEX1;
+output [6:0] HEX2;
+output [6:0] HEX3;
+output [6:0] HEX4;
+output [6:0] HEX5;
+output [6:0] HEX6;
+output [6:0] HEX7;
+
+//////////// VGA //////////
+output [7:0] VGA_B;
+output VGA_BLANK_N;
+output VGA_CLK;
+output [7:0] VGA_G;
+output VGA_HS;
+output [7:0] VGA_R;
+output VGA_SYNC_N;
+output VGA_VS;
+
+
+//=======================================================
+// REG/WIRE declarations
+//=======================================================
+
+wire VGA_CTRL_CLK_1240x1024;
+wire VGA_CTRL_CLK= VGA_CTRL_CLK_1240x1024;
+assign VGA_CLK= VGA_CTRL_CLK;
+
+wire VGA_HS_1240x1024;
+wire VGA_VS_1240x1024;
+assign VGA_HS= VGA_HS_1240x1024; // VGA H_SYNC
+assign VGA_VS= VGA_VS_1240x1024; // VGA V_SYNC
+
+wire [11:0] mVGA_X;
+wire [11:0] mVGA_Y;
+
+wire [9:0] mVGA_R;
+wire [9:0] mVGA_G;
+wire [9:0] mVGA_B;
+
+wire [9:0] sVGA_R_1240x1024;
+wire [9:0] sVGA_G_1240x1024;
+wire [9:0] sVGA_B_1240x1024;
+wire [9:0] sVGA_R= sVGA_R_1240x1024;
+wire [9:0] sVGA_G= sVGA_G_1240x1024;
+wire [9:0] sVGA_B= sVGA_B_1240x1024;
+
+
+assign VGA_R = sVGA_R[7:0];
+assign VGA_G = sVGA_G[7:0];
+assign VGA_B = sVGA_B[7:0];
+
+//=======================================================
+// Structural coding
+//=======================================================
+
+VGA_CLK u1_1240x1024
+ ( .inclk0(CLOCK_50),
+ .c0( VGA_CTRL_CLK_1240x1024 )
+ );
+ defparam u1_1240x1024.PLL_MUL= 54;
+ defparam u1_1240x1024.PLL_DIV= 25;
+
+
+VGA_Ctrl u2_1240x1024
+ ( // Host Side
+ .oCurrent_X( mVGA_X),
+ .oCurrent_Y( mVGA_Y),
+ .iRed( mVGA_R),
+ .iGreen( mVGA_G),
+ .iBlue( mVGA_B),
+ // VGA Side
+ .oVGA_R( sVGA_R_1240x1024 ),
+ .oVGA_G( sVGA_G_1240x1024 ),
+ .oVGA_B( sVGA_B_1240x1024 ),
+ .oVGA_HS( VGA_HS_1240x1024 ),
+ .oVGA_VS( VGA_VS_1240x1024 ),
+ .oVGA_SYNC( VGA_SYNC_N ),
+ .oVGA_BLANK( VGA_BLANK_N ),
+ .oVGA_CLOCK(),
+ // Control Signal
+ .iCLK( VGA_CTRL_CLK),
+ .iRST_N( KEY[0]),
+ .les_btn( KEY[2])
+ );
+ defparam u2_1240x1024.H_FRONT = 48;
+ defparam u2_1240x1024.H_SYNC = 112;
+ defparam u2_1240x1024.H_BACK = 248;
+ defparam u2_1240x1024.H_ACT = 1280;
+ defparam u2_1240x1024.V_FRONT = 1;
+ defparam u2_1240x1024.V_SYNC = 3;
+ defparam u2_1240x1024.V_BACK = 38;
+ defparam u2_1240x1024.V_ACT = 1024;
+
+wire [31:0]VGenOut;
+parameter RES_X_H= 1240;
+parameter RES_Y_H= 1024;
+parameter XY_STEP_H= 7;
+wire signed [11:0] x;
+wire signed [11:0] y;
+assign x= (mVGA_X- RES_X_H/2);
+assign y= (mVGA_Y- RES_Y_H/2);
+wire [31:0] X_in= x<<
numbert_sort_device/trunk/boards/marsohod2/cyclone3.sof
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: numbert_sort_device/trunk/boards/marsohod2/cyclone3.qsf
===================================================================
--- numbert_sort_device/trunk/boards/marsohod2/cyclone3.qsf (nonexistent)
+++ numbert_sort_device/trunk/boards/marsohod2/cyclone3.qsf (revision 2)
@@ -0,0 +1,212 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2011 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 32-bit
+# Version 11.1 Build 259 01/25/2012 Service Pack 2 SJ Web Edition
+# Date created = 13:54:01 September 03, 2012
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# cyclone3_assignment_defaults.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "11.1 SP2"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:58:05 SEPTEMBER 03, 2012"
+set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
+
+# Classic Timing Assignments
+# ==========================
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name TOP_LEVEL_ENTITY MARS_VGA
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP3C10E144C8
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED"
+
+set_location_assignment PIN_24 -to FTDI_BD0
+set_location_assignment PIN_28 -to FTDI_BD1
+set_location_assignment PIN_11 -to FTDI_BD2
+set_location_assignment PIN_10 -to FTDI_BD3
+
+set_location_assignment PIN_25 -to CLK100MHZ
+set_location_assignment PIN_23 -to KEY0
+set_location_assignment PIN_22 -to KEY1
+
+set_location_assignment PIN_30 -to SDRAM_DQ[15]
+set_location_assignment PIN_31 -to SDRAM_DQ[14]
+set_location_assignment PIN_32 -to SDRAM_DQ[13]
+set_location_assignment PIN_33 -to SDRAM_DQ[12]
+set_location_assignment PIN_34 -to SDRAM_DQ[11]
+set_location_assignment PIN_38 -to SDRAM_DQ[10]
+set_location_assignment PIN_39 -to SDRAM_DQ[9]
+set_location_assignment PIN_42 -to SDRAM_DQ[8]
+
+set_location_assignment PIN_71 -to SDRAM_DQ[7]
+set_location_assignment PIN_72 -to SDRAM_DQ[6]
+set_location_assignment PIN_73 -to SDRAM_DQ[5]
+set_location_assignment PIN_74 -to SDRAM_DQ[4]
+set_location_assignment PIN_75 -to SDRAM_DQ[3]
+set_location_assignment PIN_76 -to SDRAM_DQ[2]
+set_location_assignment PIN_77 -to SDRAM_DQ[1]
+set_location_assignment PIN_80 -to SDRAM_DQ[0]
+
+set_location_assignment PIN_60 -to SDRAM_A[0]
+set_location_assignment PIN_64 -to SDRAM_A[1]
+set_location_assignment PIN_65 -to SDRAM_A[2]
+set_location_assignment PIN_66 -to SDRAM_A[3]
+set_location_assignment PIN_46 -to SDRAM_A[4]
+set_location_assignment PIN_49 -to SDRAM_A[5]
+set_location_assignment PIN_50 -to SDRAM_A[6]
+set_location_assignment PIN_51 -to SDRAM_A[7]
+set_location_assignment PIN_52 -to SDRAM_A[8]
+set_location_assignment PIN_53 -to SDRAM_A[9]
+set_location_assignment PIN_59 -to SDRAM_A[10]
+set_location_assignment PIN_54 -to SDRAM_A[11]
+
+set_location_assignment PIN_70 -to SDRAM_LDQM
+set_location_assignment PIN_43 -to SDRAM_UDQM
+
+set_location_assignment PIN_55 -to SDRAM_BA0
+set_location_assignment PIN_58 -to SDRAM_BA1
+
+set_location_assignment PIN_67 -to SDRAM_RAS
+set_location_assignment PIN_68 -to SDRAM_CAS
+set_location_assignment PIN_69 -to SDRAM_WE
+set_location_assignment PIN_44 -to SDRAM_CLK
+
+set_location_assignment PIN_79 -to LED[3]
+set_location_assignment PIN_83 -to LED[2]
+set_location_assignment PIN_84 -to LED[1]
+set_location_assignment PIN_85 -to LED[0]
+
+set_location_assignment PIN_144 -to VGA_RED[4]
+set_location_assignment PIN_1 -to VGA_RED[3]
+set_location_assignment PIN_2 -to VGA_RED[2]
+set_location_assignment PIN_3 -to VGA_RED[1]
+set_location_assignment PIN_7 -to VGA_RED[0]
+set_location_assignment PIN_136 -to VGA_GREEN[5]
+set_location_assignment PIN_137 -to VGA_GREEN[4]
+set_location_assignment PIN_138 -to VGA_GREEN[3]
+set_location_assignment PIN_141 -to VGA_GREEN[2]
+set_location_assignment PIN_142 -to VGA_GREEN[1]
+set_location_assignment PIN_143 -to VGA_GREEN[0]
+set_location_assignment PIN_128 -to VGA_BLUE[4]
+set_location_assignment PIN_129 -to VGA_BLUE[3]
+set_location_assignment PIN_132 -to VGA_BLUE[2]
+set_location_assignment PIN_133 -to VGA_BLUE[1]
+set_location_assignment PIN_135 -to VGA_BLUE[0]
+set_location_assignment PIN_127 -to VGA_HSYNC
+set_location_assignment PIN_126 -to VGA_VSYNC
+
+set_location_assignment PIN_100 -to ADC_D[0]
+set_location_assignment PIN_99 -to ADC_D[1]
+set_location_assignment PIN_98 -to ADC_D[2]
+set_location_assignment PIN_91 -to ADC_D[3]
+set_location_assignment PIN_90 -to ADC_D[4]
+set_location_assignment PIN_89 -to ADC_D[5]
+set_location_assignment PIN_88 -to ADC_D[6]
+set_location_assignment PIN_87 -to ADC_D[7]
+set_location_assignment PIN_86 -to ADC_CLK
+
+set_location_assignment PIN_101 -to IO[0]
+set_location_assignment PIN_103 -to IO[1]
+set_location_assignment PIN_104 -to IO[2]
+set_location_assignment PIN_105 -to IO[3]
+set_location_assignment PIN_106 -to IO[4]
+set_location_assignment PIN_110 -to IO[5]
+set_location_assignment PIN_111 -to IO[6]
+set_location_assignment PIN_112 -to IO[7]
+
+set_location_assignment PIN_113 -to IO[8]
+set_location_assignment PIN_114 -to IO[9]
+set_location_assignment PIN_115 -to IO[10]
+set_location_assignment PIN_119 -to IO[11]
+set_location_assignment PIN_120 -to IO[12]
+set_location_assignment PIN_121 -to IO[13]
+set_location_assignment PIN_124 -to IO[14]
+set_location_assignment PIN_125 -to IO[15]
+
+set_location_assignment PIN_12 -to DCLK
+set_location_assignment PIN_13 -to DATA0
+set_location_assignment PIN_8 -to NCSO
+set_location_assignment PIN_6 -to ASDO
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+
+# Advanced I/O Timing Assignments
+# ===============================
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+# ----------------------
+# start ENTITY(cyclone3)
+
+ # start DESIGN_PARTITION(Top)
+ # ---------------------------
+
+ # Incremental Compilation Assignments
+ # ===================================
+
+ # end DESIGN_PARTITION(Top)
+ # -------------------------
+
+# end ENTITY(cyclone3)
+# --------------------
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name VERILOG_FILE ../../altera/VGA_CLK.v
+set_global_assignment -name SYSTEMVERILOG_FILE ../../main/tree_sorter.sv
+set_global_assignment -name SYSTEMVERILOG_FILE ../../main/stack_sorter.sv
+set_global_assignment -name VERILOG_FILE ../../utility/VGA_Ctrl.v
+set_global_assignment -name VERILOG_FILE ../../test_vga.v
+set_global_assignment -name VERILOG_FILE MARS_VGA.v
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
Index: numbert_sort_device/trunk/boards/marsohod2/cyclone3.sdc
===================================================================
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