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/pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/comp_11b_equal.xco
0,0 → 1,59
##############################################################
#
# Xilinx Core Generator version K.39
# Date: Thu Feb 04 10:01:48 2010
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = False
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc3s200
SET devicefamily = spartan3
SET flowvendor = Other
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = ft256
SET removerpms = False
SET simulationfiles = Structural
SET speedgrade = -4
SET verilogsim = False
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT Comparator family Xilinx,_Inc. 9.0
# END Select
# BEGIN Parameters
CSET aclr=false
CSET ainitval=0
CSET aset=false
CSET ce=false
CSET cepriority=Sync_Overrides_CE
CSET component_name=comp_11b_equal
CSET constantbport=false
CSET constantbportvalue=0000000000000000
CSET datatype=Unsigned
CSET nonregisteredoutput=false
CSET operation=eq
CSET pipelinestages=0
CSET radix=2
CSET registeredoutput=true
CSET sclr=false
CSET sset=false
CSET syncctrlpriority=Reset_Overrides_Set
CSET width=11
# END Parameters
GENERATE
# CRC: 40267d7f
 
/pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/PACKET_RECEIVER_FSM.vhd
0,0 → 1,238
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03:48:34 02/07/2010
-- Design Name:
-- Module Name: PACKET_RECEIVER_FSM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity PACKET_RECEIVER_FSM is
Port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
-- Signals from EMAC
rx_sof: in STD_LOGIC; -- active low input
rx_eof: in STD_LOGIC; -- active low input
-- Signals to Counter and Comparator
sel_comp_Bval: out STD_LOGIC;
comp_Bval: out STD_LOGIC_VECTOR(10 downto 0);
rst_count : out STD_LOGIC;
en_count : out STD_LOGIC;
-- Signal from Comparator
comp_eq: in STD_LOGIC;
-- Signals to Length Register
wren_MSbyte: out STD_LOGIC;
wren_LSbyte: out STD_LOGIC;
-- Signal to user interface
valid_out_usr_data: out STD_LOGIC);
end PACKET_RECEIVER_FSM;
 
architecture Behavioral of PACKET_RECEIVER_FSM is
 
TYPE state is (rst_state,
idle_state,
detect_n_store_usr_length_MSbyte_state,
store_usr_length_LSbyte_state,
checksum_gap_state,
receive_usr_data_state);
signal current_st,next_st: state;
 
constant udp_length_match_cycle : std_logic_vector(10 downto 0):="00000100100"; -- UDP length MSbyte - 2
constant udp_checksum_skip : std_logic_vector(10 downto 0):="00000000001";
constant gnd_vec : std_logic_vector(10 downto 0):="00000000000";
begin
 
process(current_st,rx_sof,rx_eof,comp_eq)
begin
case current_st is
 
 
when rst_state =>
 
sel_comp_Bval<='0';
comp_Bval<=gnd_vec;
rst_count<='1';
en_count<='0';
wren_MSbyte<='0';
wren_LSbyte<='0';
valid_out_usr_data<='0';
next_st<=idle_state;
 
when idle_state =>
if rx_sof='0' then -- rx_sof is active low
sel_comp_Bval<='0';
comp_Bval<=udp_length_match_cycle;
rst_count<='1';
en_count<='0';
wren_MSbyte<='0';
wren_LSbyte<='0';
valid_out_usr_data<='0';
next_st<=detect_n_store_usr_length_MSbyte_state;
else
sel_comp_Bval<='0';
comp_Bval<=gnd_vec;
rst_count<='0';
en_count<='0';
wren_MSbyte<='0';
wren_LSbyte<='0';
valid_out_usr_data<='0';
next_st<=idle_state;
end if;
when detect_n_store_usr_length_MSbyte_state =>
if comp_eq='1' then -- comp_eq is active high
sel_comp_Bval<='0';
comp_Bval<=udp_checksum_skip; -- Just to skip the UDP checksum field
rst_count<='1';
en_count<='0';
wren_MSbyte<='1';
wren_LSbyte<='0';
valid_out_usr_data<='0';
next_st<=store_usr_length_LSbyte_state;
else
sel_comp_Bval<='0';
comp_Bval<=udp_length_match_cycle;
rst_count<='0';
en_count<='1';
wren_MSbyte<='0';
wren_LSbyte<='0';
valid_out_usr_data<='0';
next_st<=detect_n_store_usr_length_MSbyte_state;
end if;
when store_usr_length_LSbyte_state =>
sel_comp_Bval<='0';
comp_Bval<=udp_checksum_skip; -- Just to skip the UDP checksum field
rst_count<='0';
en_count<='1';
wren_MSbyte<='0';
wren_LSbyte<='1';
valid_out_usr_data<='0';
next_st<=checksum_gap_state;
when checksum_gap_state =>
if comp_eq='1' then -- comp_eq is active high
sel_comp_Bval<='1';
comp_Bval<=gnd_vec;
rst_count<='1';
en_count<='0';
wren_MSbyte<='0';
wren_LSbyte<='0';
valid_out_usr_data<='0';
next_st<=receive_usr_data_state;
else
sel_comp_Bval<='0';
comp_Bval<=udp_checksum_skip;
rst_count<='0';
en_count<='1';
wren_MSbyte<='0';
wren_LSbyte<='0';
valid_out_usr_data<='0';
next_st<=checksum_gap_state;
end if;
when receive_usr_data_state =>
if (comp_eq='1' or rx_eof='0') then -- comp_eq is active high rx_eof is active-low
sel_comp_Bval<='0';
comp_Bval<=udp_length_match_cycle;
rst_count<='1';
en_count<='0';
wren_MSbyte<='0';
wren_LSbyte<='0';
valid_out_usr_data<='1';
next_st<=idle_state;
else
sel_comp_Bval<='1';
comp_Bval<=gnd_vec;
rst_count<='0';
en_count<='1';
wren_MSbyte<='0';
wren_LSbyte<='0';
valid_out_usr_data<='1';
next_st<=receive_usr_data_state;
end if;
end case;
end process;
 
 
 
 
process(clk)
begin
if (rst='1') then
current_st<= rst_state;
elsif (clk'event and clk='1') then
current_st <= next_st;
end if;
end process;
end Behavioral;
 
/pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/REG_8b_wren.vhd
0,0 → 1,56
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:40:03 02/07/2010
-- Design Name:
-- Module Name: REG_8b_wren - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity REG_8b_wren is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
wren : in STD_LOGIC;
input_val : in STD_LOGIC_VECTOR (7 downto 0);
output_val : inout STD_LOGIC_VECTOR(7 downto 0));
end REG_8b_wren;
 
architecture Behavioral of REG_8b_wren is
 
begin
 
process(clk)
begin
if rst='1' then
output_val<="00000000";
else
if clk'event and clk='1' then
if wren='1' then
output_val<=input_val;
end if;
end if;
end if;
end process;
 
end Behavioral;
 
/pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/COUNTER_6B_LUT_FIFO_MODE.vhd
0,0 → 1,63
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 02:30:12 11/30/2009
-- Design Name:
-- Module Name: COUNTER_6B_LUT_FIFO_MODE - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity COUNTER_6B_LUT_FIFO_MODE is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
funct_sel : in STD_LOGIC; -- 0 for lut addressing, 1 for fifo addressing
count_en : in STD_LOGIC;
value_O : inout STD_LOGIC_VECTOR (5 downto 0));
end COUNTER_6B_LUT_FIFO_MODE;
 
architecture Behavioral of COUNTER_6B_LUT_FIFO_MODE is
 
begin
 
process(clk)
begin
if rst='1' then
if funct_sel='0' then
value_O<=(others=>'0');
else
value_O<="100111";
end if;
else
if clk'event and clk='1' then
if count_en='1' then
value_O<=value_O+"000001";
else
value_O<=value_O;
end if;
end if;
end if;
end process;
 
 
end Behavioral;
 
/pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/COUNTER_11B_EN_RECEIV.vhd
0,0 → 1,58
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:16:57 11/30/2009
-- Design Name:
-- Module Name: COUNTER_11B_EN_RECEIV - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity COUNTER_11B_EN_RECEIV is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
count_en : in STD_LOGIC;
value_O : inout STD_LOGIC_VECTOR (10 downto 0));
end COUNTER_11B_EN_RECEIV;
 
architecture Behavioral of COUNTER_11B_EN_RECEIV is
 
begin
 
process(clk)
begin
if rst='1' then
value_O<="00000000000";
else
if clk'event and clk='1' then
if count_en='1' then
value_O<=value_O+"00000000001";
else
value_O<=value_O;
end if;
end if;
end if;
end process;
 
 
end Behavioral;
 
/pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/dist_mem_64x8.xco
0,0 → 1,63
##############################################################
#
# Xilinx Core Generator version K.39
# Date: Mon May 09 12:16:57 2011
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = False
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc3s200
SET devicefamily = spartan3
SET flowvendor = Other
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = pq208
SET removerpms = False
SET simulationfiles = Structural
SET speedgrade = -4
SET verilogsim = False
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT Distributed_Memory_Generator family Xilinx,_Inc. 3.4
# END Select
# BEGIN Parameters
CSET ce_overrides=ce_overrides_sync_controls
CSET coefficient_file="C:/VERIFICATION PLATFORM/UDP_IP_FLEX/COREGEN/ipv4_lut.coe"
CSET common_output_ce=false
CSET common_output_clk=false
CSET component_name=dist_mem_64x8
CSET data_width=8
CSET default_data=0
CSET default_data_radix=16
CSET depth=64
CSET dual_port_address=non_registered
CSET dual_port_output_clock_enable=false
CSET input_clock_enable=false
CSET input_options=non_registered
CSET memory_type=single_port_ram
CSET output_options=registered
CSET pipeline_stages=0
CSET qualify_we_with_i_ce=false
CSET reset_qdpo=false
CSET reset_qspo=false
CSET single_port_output_clock_enable=false
CSET sync_reset_qdpo=false
CSET sync_reset_qspo=false
# END Parameters
GENERATE
# CRC: cfec1b72
 
/pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/comp_6b_equal.ngc
0,0 → 1,3
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.4e
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/pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/OVERRIDE_LUT_CONTROL.vhd
0,0 → 1,108
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:09:25 11/30/2009
-- Design Name:
-- Module Name: OVERRIDE_LUT_CONTROL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity OVERRIDE_LUT_CONTROL is
Port ( clk : in STD_LOGIC;
input_addr : in STD_LOGIC_VECTOR (5 downto 0);
sel_total_length_MSBs : out STD_LOGIC;
sel_total_length_LSBs : out STD_LOGIC;
sel_header_checksum_MSBs : out STD_LOGIC;
sel_header_checksum_LSBs : out STD_LOGIC;
sel_length_MSBs : out STD_LOGIC;
sel_length_LSBs : out STD_LOGIC
);
end OVERRIDE_LUT_CONTROL;
 
architecture Behavioral of OVERRIDE_LUT_CONTROL is
 
component comp_6b_equal is
port (
qa_eq_b : out STD_LOGIC;
clk : in STD_LOGIC := 'X';
a : in STD_LOGIC_VECTOR ( 5 downto 0 );
b : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
end component;
 
constant total_length_addr1 : std_logic_vector(5 downto 0):="010000";
constant total_length_addr2 : std_logic_vector(5 downto 0):="010001";
 
constant header_checksum_addr1 : std_logic_vector(5 downto 0):="011000";
constant header_checksum_addr2 : std_logic_vector(5 downto 0):="011001";
 
constant length_addr1 : std_logic_vector(5 downto 0):="100110";
constant length_addr2 : std_logic_vector(5 downto 0):="100111";
 
 
signal sel_header_checksum_MSBs_tmp : std_logic;
signal sel_total_length_MSBs_tmp : std_logic;
signal sel_length_MSBs_tmp : std_logic;
 
begin
 
TARGET_TOTAL_LENGTH_1 : comp_6b_equal port map (sel_total_length_MSBs_tmp,clk,input_addr,total_length_addr1);
 
process(clk)
begin
if clk'event and clk='1' then
sel_total_length_LSBs<=sel_total_length_MSBs_tmp;
end if;
end process;
sel_total_length_MSBs<=sel_total_length_MSBs_tmp;
 
--TARGET_TOTAL_LENGTH_2 : comp_6b_equal port map (sel_total_length_LSBs,clk,input_addr,total_length_addr2);
 
TARGET_HEADER_CHECKSUM_1 : comp_6b_equal port map (sel_header_checksum_MSBs_tmp,clk,input_addr,header_checksum_addr1);
process(clk)
begin
if clk'event and clk='1' then
sel_header_checksum_LSBs<=sel_header_checksum_MSBs_tmp;
end if;
end process;
 
sel_header_checksum_MSBs<=sel_header_checksum_MSBs_tmp;
 
 
 
--TARGET_HEADER_CHECKSUM_2 : comp_6b_equal port map (sel_header_checksum_LSBs,clk,input_addr,header_checksum_addr2);
 
TARGET_LENGTH_1 : comp_6b_equal port map (sel_length_MSBs_tmp,clk,input_addr,length_addr1);
 
process(clk)
begin
if clk'event and clk='1' then
sel_length_LSBs<=sel_length_MSBs_tmp;
end if;
end process;
 
sel_length_MSBs<=sel_length_MSBs_tmp;
--TARGET_LENGTH_2 : comp_6b_equal port map (sel_length_LSBs,clk,input_addr,length_addr2);
 
end Behavioral;
 
/pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/wraddr_lut_mem.vhd
0,0 → 1,346
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: K.39
-- \ \ Application: netgen
-- / / Filename: wraddr_lut_mem.vhd
-- /___/ /\ Timestamp: Mon May 09 14:17:18 2011
-- \ \ / \
-- \___\/\___\
--
-- Command : -intstyle ise -w -sim -ofmt vhdl "C:\VERIFICATION PLATFORM\UDP_IP_FLEX\COREGEN\tmp\_cg\wraddr_lut_mem.ngc" "C:\VERIFICATION PLATFORM\UDP_IP_FLEX\COREGEN\tmp\_cg\wraddr_lut_mem.vhd"
-- Device : 3s200pq208-4
-- Input file : C:/VERIFICATION PLATFORM/UDP_IP_FLEX/COREGEN/tmp/_cg/wraddr_lut_mem.ngc
-- Output file : C:/VERIFICATION PLATFORM/UDP_IP_FLEX/COREGEN/tmp/_cg/wraddr_lut_mem.vhd
-- # of Entities : 1
-- Design Name : wraddr_lut_mem
-- Xilinx : C:\Xilinx\10.1\ISE
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Development System Reference Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
 
 
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
 
entity wraddr_lut_mem is
port (
clk : in STD_LOGIC := 'X';
a : in STD_LOGIC_VECTOR ( 5 downto 0 );
qspo : out STD_LOGIC_VECTOR ( 5 downto 0 )
);
end wraddr_lut_mem;
 
architecture STRUCTURE of wraddr_lut_mem is
signal N0 : STD_LOGIC;
signal N1 : STD_LOGIC;
signal BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom0000311 : STD_LOGIC;
signal BU2_N35 : STD_LOGIC;
signal BU2_N34 : STD_LOGIC;
signal BU2_N33 : STD_LOGIC;
signal BU2_N32 : STD_LOGIC;
signal BU2_N31 : STD_LOGIC;
signal BU2_N30 : STD_LOGIC;
signal BU2_N29 : STD_LOGIC;
signal BU2_N28 : STD_LOGIC;
signal BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000031 : STD_LOGIC;
signal BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom0000_f51 : STD_LOGIC;
signal BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom00002_22 : STD_LOGIC;
signal BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom00001_21 : STD_LOGIC;
signal BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom0000_f5_20 : STD_LOGIC;
signal BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom0000 : STD_LOGIC;
signal BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom00005_18 : STD_LOGIC;
signal BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom00004_17 : STD_LOGIC;
signal BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000021_16 : STD_LOGIC;
signal BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000011_15 : STD_LOGIC;
signal BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom0000_f6_14 : STD_LOGIC;
signal a_2 : STD_LOGIC_VECTOR ( 5 downto 0 );
signal qspo_3 : STD_LOGIC_VECTOR ( 5 downto 0 );
signal BU2_qdpo : STD_LOGIC_VECTOR ( 0 downto 0 );
begin
a_2(5) <= a(5);
a_2(4) <= a(4);
a_2(3) <= a(3);
a_2(2) <= a(2);
a_2(1) <= a(1);
a_2(0) <= a(0);
qspo(5) <= qspo_3(5);
qspo(4) <= qspo_3(4);
qspo(3) <= qspo_3(3);
qspo(2) <= qspo_3(2);
qspo(1) <= qspo_3(1);
qspo(0) <= qspo_3(0);
VCC_0 : VCC
port map (
P => N1
);
GND_1 : GND
port map (
G => N0
);
BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom0000311_f5 : MUXF5
port map (
I0 => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom0000311,
I1 => BU2_qdpo(0),
S => a_2(5),
O => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000031
);
BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom00003111 : LUT4
generic map(
INIT => X"101C"
)
port map (
I0 => a_2(4),
I1 => a_2(1),
I2 => a_2(2),
I3 => a_2(3),
O => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom0000311
);
BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000011_G : LUT4
generic map(
INIT => X"0B3D"
)
port map (
I0 => a_2(1),
I1 => a_2(4),
I2 => a_2(5),
I3 => a_2(3),
O => BU2_N35
);
BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000011_F : LUT4
generic map(
INIT => X"5351"
)
port map (
I0 => a_2(5),
I1 => a_2(1),
I2 => a_2(4),
I3 => a_2(3),
O => BU2_N34
);
BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000011 : MUXF5
port map (
I0 => BU2_N34,
I1 => BU2_N35,
S => a_2(2),
O => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000011_15
);
BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom00004_G : LUT4
generic map(
INIT => X"0B2C"
)
port map (
I0 => a_2(1),
I1 => a_2(4),
I2 => a_2(5),
I3 => a_2(3),
O => BU2_N33
);
BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom00004_F : LUT3
generic map(
INIT => X"26"
)
port map (
I0 => a_2(4),
I1 => a_2(5),
I2 => a_2(1),
O => BU2_N32
);
BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom00004 : MUXF5
port map (
I0 => BU2_N32,
I1 => BU2_N33,
S => a_2(2),
O => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom00004_17
);
BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom00005_G : LUT4
generic map(
INIT => X"1656"
)
port map (
I0 => a_2(5),
I1 => a_2(3),
I2 => a_2(4),
I3 => a_2(1),
O => BU2_N31
);
BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom00005_F : LUT4
generic map(
INIT => X"1528"
)
port map (
I0 => a_2(5),
I1 => a_2(3),
I2 => a_2(1),
I3 => a_2(4),
O => BU2_N30
);
BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom00005 : MUXF5
port map (
I0 => BU2_N30,
I1 => BU2_N31,
S => a_2(2),
O => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom00005_18
);
BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000021_G : LUT4
generic map(
INIT => X"1656"
)
port map (
I0 => a_2(5),
I1 => a_2(3),
I2 => a_2(4),
I3 => a_2(2),
O => BU2_N29
);
BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000021_F : LUT4
generic map(
INIT => X"1653"
)
port map (
I0 => a_2(5),
I1 => a_2(2),
I2 => a_2(4),
I3 => a_2(3),
O => BU2_N28
);
BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000021 : MUXF5
port map (
I0 => BU2_N28,
I1 => BU2_N29,
S => a_2(1),
O => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000021_16
);
BU2_U0_gen_rom_rom_inst_qspo_int_3 : FDS
generic map(
INIT => '0'
)
port map (
C => clk,
D => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000031,
S => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom00004_17,
Q => qspo_3(3)
);
BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom0000_f6 : MUXF6
port map (
I0 => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom0000_f51,
I1 => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom0000_f5_20,
S => a_2(5),
O => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom0000_f6_14
);
BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom0000_f5_0 : MUXF5
port map (
I0 => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom00002_22,
I1 => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom00001_21,
S => a_2(4),
O => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom0000_f51
);
BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom00003 : LUT3
generic map(
INIT => X"F8"
)
port map (
I0 => a_2(3),
I1 => a_2(2),
I2 => a_2(0),
O => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom00002_22
);
BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom00002 : LUT4
generic map(
INIT => X"9DDF"
)
port map (
I0 => a_2(3),
I1 => a_2(0),
I2 => a_2(2),
I3 => a_2(1),
O => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom00001_21
);
BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom0000_f5 : MUXF5
port map (
I0 => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom0000,
I1 => BU2_qdpo(0),
S => a_2(4),
O => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom0000_f5_20
);
BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom00001 : LUT4
generic map(
INIT => X"544E"
)
port map (
I0 => a_2(3),
I1 => a_2(0),
I2 => a_2(2),
I3 => a_2(1),
O => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom0000
);
BU2_U0_gen_rom_rom_inst_qspo_int_5 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom00005_18,
Q => qspo_3(5)
);
BU2_U0_gen_rom_rom_inst_qspo_int_4 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom00004_17,
Q => qspo_3(4)
);
BU2_U0_gen_rom_rom_inst_qspo_int_2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000021_16,
Q => qspo_3(2)
);
BU2_U0_gen_rom_rom_inst_qspo_int_1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000011_15,
Q => qspo_3(1)
);
BU2_U0_gen_rom_rom_inst_qspo_int_0 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom0000_f6_14,
Q => qspo_3(0)
);
BU2_XST_GND : GND
port map (
G => BU2_qdpo(0)
);
 
end STRUCTURE;
 
-- synthesis translate_on
/pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/IPV4_PACKET_TRANSMITTER.vhd
0,0 → 1,478
-----------------------------------------------------------------------------------------
-- Copyright (C) 2010 Nikolaos Ch. Alachiotis --
-- --
-- Engineer: Nikolaos Ch. Alachiotis --
-- --
-- Contact: alachiot@cs.tum.edu --
-- n.alachiotis@gmail.com --
-- --
-- Create Date: 14:45:39 11/27/2009 --
-- Module Name: IPV4_PACKET_TRANSMITTER --
-- Target Devices: Virtex 5 FPGAs --
-- Tool versions: ISE 10.1 --
-- Description: This component can be used to send IPv4 Ethernet Packets. --
-- Additional Comments: The look-up table contains the header fields of the IP packet, --
-- so please keep in mind that you have to reinitialize this LUT. --
-- --
-----------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity IPV4_PACKET_TRANSMITTER is
Port ( rst : in STD_LOGIC;
clk_125MHz : in STD_LOGIC;
transmit_start_enable : in STD_LOGIC;
transmit_data_length : in STD_LOGIC_VECTOR (15 downto 0);
usr_data_trans_phase_on : out STD_LOGIC;
transmit_data_input_bus : in STD_LOGIC_VECTOR (7 downto 0);
start_of_frame_O : out STD_LOGIC;
end_of_frame_O : out STD_LOGIC;
source_ready : out STD_LOGIC;
transmit_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0);
 
flex_wren: in STD_LOGIC;
flex_wraddr: in STD_LOGIC_VECTOR(5 downto 0);
flex_wrdata: in STD_LOGIC_VECTOR(7 downto 0);
flex_checksum_baseval: in std_logic_vector(15 downto 0)
);
end IPV4_PACKET_TRANSMITTER;
 
architecture Behavioral of IPV4_PACKET_TRANSMITTER is
 
 
-----------------------------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------------------------
-- IPv4 PACKET STRUCTURE : --
-- Size | Description | Transmission Order | Position --
-- -----------------------------------------------------------------------------------------------------------
-- 6 bytes | Destin MAC Address (PC) | 0 1 2 3 4 5 | LUT --
-- | X-X-X-X-X-X | | --
-- | | | --
-- 6 bytes | Source MAC Address (FPGA) | 6 7 8 9 10 11 | LUT --
-- | 11111111-11111111-11111111-11111111-... | | --
-- 2 bytes | Ethernet Type * | 12 13 | LUT --
-- | (fixed to 00001000-00000000 :=> | | --
-- | Internet Protocol, Version 4 (IPv4)) | | --
-- -- Start of IPv4 Packet ** - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- | --
-- 1 byte | 4 MSBs = Version , 4 LSBs = Header Length | 14 | LUT --
-- | 0100 0101 | | --
-- 1 byte | Differentiated Services | 15 | LUT --
-- | 00000000 | | --
-- 2 bytes | Total Length | 16 17 | REG --
-- | 00000000-00100100 (base: 20 + 8 + datalength)| | --
-- 2 bytes | Identification | 18 19 | LUT --
-- | 00000000-00000000 | | --
-- 2 bytes | 3 MSBs = Flags , 13 LSBs = Fragment Offset | 20 21 | LUT --
-- | 010 - 0000000000000 | | --
-- 1 byte | Time to Live | 22 | LUT --
-- | 01000000 | | --
-- 1 byte | Protocol | 23 | LUT --
-- | 00010001 | | --
-- 2 bytes | Header Checksum | 24 25 | REG --
-- | 10110111 01111101 (base value) | | --
-- 4 bytes | Source IP Address | 26 27 28 29 | LUT --
-- | X-X-X-X - FPGA | | --
-- 4 bytes | Destin IP Address | 30 31 32 33 | LUT --
-- | X-X-X-X - PC | | --
-- -- Start of UDP Packet *** - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- | --
-- 2 bytes | Source Port | 34 35 | LUT --
-- | X-X | | --
-- 2 bytes | Destination Port | 36 37 | LUT --
-- | X-X | | --
-- 2 bytes | Length | 38 39 | REG --
-- | 00000000 - 00010000 (8 + # data bytes) | | --
-- 2 bytes | Checksum | 40 41 | LUT --
-- | 00000000 - 00000000 | | --
-- X bytes | Data | 42 .. X | from input --
-- | | | --
-----------------------------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------------------------
 
-- * More details about the Ethernet Type value you can find here:
-- http://en.wikipedia.org/wiki/Ethertype
 
-- ** More details about the Internet Protocol, Version 4 (IPv4) you can find here:
-- http://en.wikipedia.org/wiki/IPv4
 
-- *** More details about the Internet Protocol, Version 4 (IPv4) you can find here:
-- http://en.wikipedia.org/wiki/User_Datagram_Protocol
-----------------------------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------------------------
 
 
 
--------------------------------------------------------------------------------------
-- COMPONENT DECLARATION
--------------------------------------------------------------------------------------
 
component REG_16B_WREN is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
wren : in STD_LOGIC;
input : in STD_LOGIC_VECTOR (15 downto 0);
output : out STD_LOGIC_VECTOR (15 downto 0));
end component;
 
component IPV4_LUT_INDEXER is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
transmit_enable : in STD_LOGIC;
LUT_index : out STD_LOGIC_VECTOR (5 downto 0));
end component;
 
--component dist_mem_64x8 is
-- port (
-- clk : in STD_LOGIC := 'X';
-- a : in STD_LOGIC_VECTOR ( 5 downto 0 );
-- qspo : out STD_LOGIC_VECTOR ( 7 downto 0 )
-- );
--end component;
 
component dist_mem_64x8 is
port (
clk : in STD_LOGIC := 'X';
we : in STD_LOGIC := 'X';
a : in STD_LOGIC_VECTOR ( 5 downto 0 );
d : in STD_LOGIC_VECTOR ( 7 downto 0 );
qspo : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component;
 
component OVERRIDE_LUT_CONTROL is
Port ( clk : in STD_LOGIC;
input_addr : in STD_LOGIC_VECTOR (5 downto 0);
sel_total_length_MSBs : out STD_LOGIC;
sel_total_length_LSBs : out STD_LOGIC;
sel_header_checksum_MSBs : out STD_LOGIC;
sel_header_checksum_LSBs : out STD_LOGIC;
sel_length_MSBs : out STD_LOGIC;
sel_length_LSBs : out STD_LOGIC
);
end component;
 
component TARGET_EOF is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
start : in STD_LOGIC;
total_length_from_reg : in STD_LOGIC_VECTOR(15 downto 0);
eof_O : out STD_LOGIC);
end component;
 
component ENABLE_USER_DATA_TRANSMISSION is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
start_usr_data_trans : in STD_LOGIC;
stop_usr_data_trans : in STD_LOGIC;
usr_data_sel : out STD_LOGIC);
end component;
 
component ALLOW_ZERO_UDP_CHECKSUM is
Port ( clk : in STD_LOGIC;
input : in STD_LOGIC;
output_to_readen : out STD_LOGIC;
output_to_datasel : out STD_LOGIC);
end component;
 
 
--------------------------------------------------------------------------------------
-- SIGNAL DECLARATION
--------------------------------------------------------------------------------------
 
signal transmit_start_enable_tmp,
sel_total_length_MSBs,
sel_total_length_LSBs,
sel_header_checksum_MSBs,
sel_header_checksum_LSBs,
sel_length_MSBs,
sel_length_LSBs,
lut_out_sel,
source_ready_previous_value,
end_of_frame_O_tmp,
transmit_start_enable_reg,
usr_data_sel_sig,
start_usr_data_read,
start_usr_data_trans : STD_LOGIC;
 
signal LUT_addr,
LUT_addr_dual,
sel_rd,
sel_wr: STD_LOGIC_VECTOR(5 downto 0);
 
signal transmit_data_input_bus_tmp,
transmit_data_output_bus_tmp,
sel_total_length_MSBs_vec,
sel_total_length_LSBs_vec,
sel_header_checksum_MSBs_vec,
sel_header_checksum_LSBs_vec,
sel_length_MSBs_vec,
sel_length_LSBs_vec,
lut_out_sel_vec,
transmit_data_output_bus_no_usr_data,
usr_data_not_sel_vec,
usr_data_sel_vec : STD_LOGIC_VECTOR(7 downto 0);
 
signal transmit_data_length_tmp,
data_length_regout,
tmp_total_length,
tmp_header_checksum,
tmp_header_checksum_baseval,
tmp_length : STD_LOGIC_VECTOR(15 downto 0);
 
begin
 
transmit_start_enable_tmp<=transmit_start_enable;
 
transmit_data_length_tmp<=transmit_data_length;
 
transmit_data_input_bus_tmp<=transmit_data_input_bus;
 
----------------------------------------------------------------------------------------------------
-- start_of_frame_O signal
----------------------------------------------------------------------------------------------------
-- Description: start_of_frame_O is active low
-- We connect it to the delayed for one clock cycle transmit_start_enable input signal
-- through a NOT gate since transmit_start_enable is active high.
 
process(clk_125MHz)
begin
if clk_125MHz'event and clk_125MHz='1' then
transmit_start_enable_reg<=transmit_start_enable_tmp; -- Delay transmit_start_enable one cycle.
end if;
end process;
 
start_of_frame_O<=not transmit_start_enable_reg;
 
----------------------------------------------------------------------------------------------------
-- end_of_frame_O signal
----------------------------------------------------------------------------------------------------
-- Description: end_of_frame_O is active low
-- The TARGET_EOF module targets the last byte of the packet that is being transmitted
-- based on a counter that counts the number of transmitted bytes and a comparator that
-- detects the last byte which is the <tmp_total_length>th byte.
 
TARGET_EOF_port_map: TARGET_EOF port map
(
rst =>rst,
clk =>clk_125MHz,
start =>transmit_start_enable_reg,
total_length_from_reg =>tmp_total_length,
eof_O =>end_of_frame_O_tmp
);
--* The counter in TARGET_EOF starts from -X, where X is the number of bytes transmitted before the
-- IPv4 packet. (MAC addresses + Ethernet Type)
end_of_frame_O<=end_of_frame_O_tmp;
 
----------------------------------------------------------------------------------------------------
-- source_ready signal
----------------------------------------------------------------------------------------------------
-- Description: source_ready is active low
-- This signal is idle(high). (based on rst and end_of_frame_O_tmp).
-- This signal is active(low). (based on transmit_start_enable and end_of_frame_O_tmp).
 
process(clk_125MHz)
begin
if rst='1' then
source_ready<='1';
source_ready_previous_value<='1';
else
if clk_125MHz'event and clk_125MHz='1' then
if (transmit_start_enable_tmp='1' and source_ready_previous_value='1') then
source_ready<='0';
source_ready_previous_value<='0';
else
if (end_of_frame_O_tmp='0' and source_ready_previous_value='0') then
source_ready<='1';
source_ready_previous_value<='1';
end if;
end if;
end if;
end if;
end process;
 
----------------------------------------------------------------------------------------------------
-- transmit_data_output_bus
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- Component Name: REG_16B_WREN
-- Instance Name: NUMBER_OR_DATA_IN_BYTES_REGISTER
-- Description: Register that holds the number of bytes of input data
-- that will be transmitted in the packet.
----------------------------------------------------------------------------------------------------
NUMBER_OR_DATA_IN_BYTES_REGISTER : REG_16B_WREN port map
(
rst =>rst,
clk =>clk_125MHz,
wren =>transmit_start_enable_tmp, -- The transmit_start_enable input signal can be used as wren.
input =>transmit_data_length_tmp,
output =>data_length_regout
);
----------------------------------------------------------------------------------------------------
 
tmp_total_length<="0000000000011100" + data_length_regout;
 
 
tmp_header_checksum_baseval<=flex_checksum_baseval;
--tmp_header_checksum_baseval<="1011011101111101"; -- CHANGE VALUE! : You have to change this value!
tmp_header_checksum<=tmp_header_checksum_baseval - data_length_regout;
 
tmp_length<="0000000000001000" + data_length_regout;
 
----------------------------------------------------------------------------------------------------
 
----------------------------------------------------------------------------------------------------
-- Component Name: IPV4_LUT_INDEXER
-- Instance Name: IPV4_LUT_INDEXER_port_map
-- Description: When transmit_enable is high for one cycle IPV4_LUT_INDEXER generates the
-- addresses to the LUT that contains the header section of the IP packet.
----------------------------------------------------------------------------------------------------
IPV4_LUT_INDEXER_port_map : IPV4_LUT_INDEXER port map
(
rst =>rst,
clk =>clk_125MHz,
transmit_enable =>transmit_start_enable_tmp,
LUT_index =>LUT_addr
);
----------------------------------------------------------------------------------------------------
 
----------------------------------------------------------------------------------------------------
-- Component Name: dist_mem_64x8
-- Instance Name: LUT_MEM
-- Description: LUT that contains the header section.
----------------------------------------------------------------------------------------------------
LUT_addr_dual <= (LUT_addr and sel_rd) or (flex_wraddr and sel_wr);
 
sel_rd <= (others=> not flex_wren);
sel_wr <= (others=> flex_wren);
 
LUT_MEM : dist_mem_64x8 port map
(
--clk =>clk_125MHz,
--a =>LUT_addr_dual,
--qspo =>transmit_data_output_bus_tmp
 
clk =>clk_125MHz,
we =>flex_wren,
a => LUT_addr_dual,
d => flex_wrdata,
qspo =>transmit_data_output_bus_tmp
);
 
 
 
 
 
----------------------------------------------------------------------------------------------------
 
----------------------------------------------------------------------------------------------------
-- Component Name: OVERRIDE_LUT_CONTROL
-- Instance Name: OVERRIDE_LUT_CONTROL_port_map
-- Description: Decides whether the output byte will come from the LUT or not.
----------------------------------------------------------------------------------------------------
OVERRIDE_LUT_CONTROL_port_map : OVERRIDE_LUT_CONTROL port map
(
clk =>clk_125MHz,
input_addr =>LUT_addr,
sel_total_length_MSBs =>sel_total_length_MSBs,
sel_total_length_LSBs =>sel_total_length_LSBs,
sel_header_checksum_MSBs =>sel_header_checksum_MSBs,
sel_header_checksum_LSBs =>sel_header_checksum_LSBs,
sel_length_MSBs =>sel_length_MSBs,
sel_length_LSBs =>sel_length_LSBs
);
----------------------------------------------------------------------------------------------------
 
----------------------------------------------------------------------------------------------------
-- MUX 7 to 1
sel_total_length_MSBs_vec<=(others=>sel_total_length_MSBs);
sel_total_length_LSBs_vec<=(others=>sel_total_length_LSBs);
sel_header_checksum_MSBs_vec<=(others=>sel_header_checksum_MSBs);
sel_header_checksum_LSBs_vec<=(others=>sel_header_checksum_LSBs);
sel_length_MSBs_vec<=(others=>sel_length_MSBs);
sel_length_LSBs_vec<=(others=>sel_length_LSBs);
lut_out_sel_vec <= (others=>lut_out_sel);
lut_out_sel<=(not sel_total_length_MSBs) and (not sel_total_length_LSBs) and
(not sel_header_checksum_MSBs) and (not sel_header_checksum_LSBs) and
(not sel_length_MSBs) and (not sel_length_LSBs);
 
-- MUX output
transmit_data_output_bus_no_usr_data<= (transmit_data_output_bus_tmp and lut_out_sel_vec) or
(tmp_total_length(15 downto 8) and sel_total_length_MSBs_vec) or
(tmp_total_length(7 downto 0) and sel_total_length_LSBs_vec) or
(tmp_header_checksum(15 downto 8) and sel_header_checksum_MSBs_vec) or
(tmp_header_checksum(7 downto 0) and sel_header_checksum_LSBs_vec) or
(tmp_length(15 downto 8) and sel_length_MSBs_vec) or
(tmp_length(7 downto 0) and sel_length_LSBs_vec);
----------------------------------------------------------------------------------------------------
 
----------------------------------------------------------------------------------------------------
-- Component Name: ALLOW_ZERO_UDP_CHECKSUM
-- Instance Name: ALLOW_ZERO_UDP_CHECKSUM_port_map
-- Description: Delays the user data transmition phase in order to transmit two bytes with zero
-- first.
----------------------------------------------------------------------------------------------------
ALLOW_ZERO_UDP_CHECKSUM_port_map: ALLOW_ZERO_UDP_CHECKSUM port map
(
clk =>clk_125MHz,
input =>sel_length_LSBs,
output_to_readen =>start_usr_data_read,
output_to_datasel =>start_usr_data_trans
);
----------------------------------------------------------------------------------------------------
 
----------------------------------------------------------------------------------------------------
-- Component Name: ENABLE_USER_DATA_TRANSMISSION
-- Instance Name: ENABLE_USER_DATA_READ_port_map
-- Description: Sets usr_data_trans_phase_on signal one cycle before the transmittion of the
-- first user byte.
----------------------------------------------------------------------------------------------------
ENABLE_USER_DATA_READ_port_map: ENABLE_USER_DATA_TRANSMISSION port map
( rst =>rst,
clk =>clk_125MHz,
start_usr_data_trans =>start_usr_data_read,
stop_usr_data_trans =>end_of_frame_O_tmp,
usr_data_sel =>usr_data_trans_phase_on
);
----------------------------------------------------------------------------------------------------
 
----------------------------------------------------------------------------------------------------
-- Component Name: ENABLE_USER_DATA_TRANSMISSION
-- Instance Name: ENABLE_USER_DATA_TRANSMISSION_port_map
-- Description: Sets usr_data_sel_sig signal to select user data for transmittion.
----------------------------------------------------------------------------------------------------
ENABLE_USER_DATA_TRANSMISSION_port_map: ENABLE_USER_DATA_TRANSMISSION port map
( rst =>rst,
clk =>clk_125MHz,
start_usr_data_trans =>start_usr_data_trans,
stop_usr_data_trans =>end_of_frame_O_tmp,
usr_data_sel =>usr_data_sel_sig
);
----------------------------------------------------------------------------------------------------
 
----------------------------------------------------------------------------------------------------
-- MUX 2 to 1
usr_data_not_sel_vec<=(others=>not usr_data_sel_sig);
usr_data_sel_vec<=(others=>usr_data_sel_sig);
 
-- MUX output
transmit_data_output_bus<=(transmit_data_output_bus_no_usr_data and usr_data_not_sel_vec) or
(transmit_data_input_bus and usr_data_sel_vec);
----------------------------------------------------------------------------------------------------
 
end Behavioral;
/pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/CONFIG_CONTROL.vhd
0,0 → 1,215
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:28:06 01/11/2011
-- Design Name:
-- Module Name: CONFIG_CONTROL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity CONFIG_CONTROL is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
config_en : in STD_LOGIC;
nxt_sof : in STD_LOGIC;
wren : out STD_LOGIC;
addr : out STD_LOGIC_VECTOR (5 downto 0);
ulock_en : in STD_LOGIC;
wren_checksum_1 : out STD_LOGIC;
wren_checksum_2 : out STD_LOGIC;
locked : out STD_LOGIC
);
end CONFIG_CONTROL;
 
architecture Behavioral of CONFIG_CONTROL is
 
TYPE state is (rst_state,
idle_state,
pre_config_state,
config_state,
lock_state
);
signal current_st,next_st: state;
 
signal rst_count, en_count, stop_s, wren_checksum_1_t: std_logic;
signal counter: std_logic_vector(5 downto 0);
 
 
 
 
component wraddr_lut_mem is
port (
clk : in STD_LOGIC := 'X';
a : in STD_LOGIC_VECTOR ( 5 downto 0 );
qspo : out STD_LOGIC_VECTOR ( 5 downto 0 )
);
end component;
 
begin
 
process(clk)
begin
if (rst='1') then
current_st<= rst_state;
elsif (clk'event and clk='1') then
current_st <= next_st;
end if;
end process;
 
 
process(current_st,config_en,nxt_sof,ulock_en,stop_s)
begin
case current_st is
 
when rst_state =>
 
rst_count <='1';
en_count <='0';
wren <='0';
locked<='0';
next_st<=idle_state;
when idle_state =>
 
rst_count <='0';
en_count <='0';
 
wren <='0';
locked<='0';
if config_en='1' then
next_st <= pre_config_state;
else
next_st <= idle_state;
end if;
 
when pre_config_state =>
 
rst_count <='0';
en_count <='0';
wren <='0';
locked<='0';
if nxt_sof='0' then
en_count <='1';
next_st <= config_state;
else
en_count <='0';
next_st <= pre_config_state;
end if;
 
 
when config_state =>
 
rst_count <='0';
en_count <='1';
wren <='1';
locked<='0';
if stop_s='1' then
next_st <= lock_state;
else
next_st <= config_state;
end if;
when lock_state =>
 
rst_count <='1';
en_count <='0';
wren <='0';
locked<='1';
if ulock_en='1' then
next_st <= rst_state;
else
next_st <= lock_state;
end if;
 
end case;
end process;
 
process(clk)
begin
if rst_count='1' then
counter <= "000000";
else
if clk'event and clk='1' then
if en_count='1' then
counter <= counter + "000001";
end if;
end if;
end if;
end process;
 
process(clk)
begin
if clk'event and clk='1' then
if counter = "100101" then
stop_s <='1';
else
stop_s <='0';
end if;
end if;
end process;
 
process(clk)
begin
if clk'event and clk='1' then
if counter = "010111" then
wren_checksum_1_t <='1';
else
wren_checksum_1_t <='0';
end if;
end if;
end process;
 
wren_checksum_1 <= wren_checksum_1_t;
 
process(clk)
begin
if clk'event and clk='1' then
wren_checksum_2 <= wren_checksum_1_t;
end if;
end process;
 
 
 
wraddrlutmem: wraddr_lut_mem Port Map
(
clk => clk,
a=> counter,
qspo=> addr);
end Behavioral;
 
/pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/ALLOW_ZERO_UDP_CHECKSUM.vhd
0,0 → 1,60
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:46:33 12/04/2009
-- Design Name:
-- Module Name: ALLOW_ZERO_UDP_CHECKSUM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity ALLOW_ZERO_UDP_CHECKSUM is
Port ( clk : in STD_LOGIC;
input : in STD_LOGIC;
output_to_readen : out STD_LOGIC;
output_to_datasel : out STD_LOGIC);
end ALLOW_ZERO_UDP_CHECKSUM;
 
architecture Behavioral of ALLOW_ZERO_UDP_CHECKSUM is
 
signal input_reg : std_logic;
 
begin
 
process(clk)
begin
if clk'event and clk='1' then
input_reg<=input;
end if;
end process;
 
output_to_readen<=input_reg;
 
process(clk)
begin
if clk'event and clk='1' then
output_to_datasel<=input_reg;
end if;
end process;
 
end Behavioral;
 
/pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/COUNTER_11B_EN_TRANS.vhd
0,0 → 1,58
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:16:57 11/30/2009
-- Design Name:
-- Module Name: COUNTER_11B_EN_TRANS - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity COUNTER_11B_EN_TRANS is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
count_en : in STD_LOGIC;
value_O : inout STD_LOGIC_VECTOR (10 downto 0));
end COUNTER_11B_EN_TRANS;
 
architecture Behavioral of COUNTER_11B_EN_TRANS is
 
begin
 
process(clk)
begin
if rst='1' then
value_O<="11111110110";
else
if clk'event and clk='1' then
if count_en='1' then
value_O<=value_O+"00000000001";
else
value_O<=value_O;
end if;
end if;
end if;
end process;
 
 
end Behavioral;
 
/pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/comp_6b_equal.vhd
0,0 → 1,161
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: K.39
-- \ \ Application: netgen
-- / / Filename: comp_6b_equal.vhd
-- /___/ /\ Timestamp: Thu Feb 04 11:02:26 2010
-- \ \ / \
-- \___\/\___\
--
-- Command : -intstyle ise -w -sim -ofmt vhdl C:\PHd_Projects\The_Felsenstein_CoProcessor\COREGEN_Design\tmp\_cg\comp_6b_equal.ngc C:\PHd_Projects\The_Felsenstein_CoProcessor\COREGEN_Design\tmp\_cg\comp_6b_equal.vhd
-- Device : 3s200ft256-4
-- Input file : C:/PHd_Projects/The_Felsenstein_CoProcessor/COREGEN_Design/tmp/_cg/comp_6b_equal.ngc
-- Output file : C:/PHd_Projects/The_Felsenstein_CoProcessor/COREGEN_Design/tmp/_cg/comp_6b_equal.vhd
-- # of Entities : 1
-- Design Name : comp_6b_equal
-- Xilinx : C:\Xilinx\10.1\ISE
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Development System Reference Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
 
 
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
 
entity comp_6b_equal is
port (
qa_eq_b : out STD_LOGIC;
clk : in STD_LOGIC := 'X';
a : in STD_LOGIC_VECTOR ( 5 downto 0 );
b : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
end comp_6b_equal;
 
architecture STRUCTURE of comp_6b_equal is
signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o80_18 : STD_LOGIC;
signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o53_17 : STD_LOGIC;
signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o26_16 : STD_LOGIC;
signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_temp_result : STD_LOGIC;
signal BU2_a_ge_b : STD_LOGIC;
signal NLW_VCC_P_UNCONNECTED : STD_LOGIC;
signal NLW_GND_G_UNCONNECTED : STD_LOGIC;
signal a_2 : STD_LOGIC_VECTOR ( 5 downto 0 );
signal b_3 : STD_LOGIC_VECTOR ( 5 downto 0 );
begin
a_2(5) <= a(5);
a_2(4) <= a(4);
a_2(3) <= a(3);
a_2(2) <= a(2);
a_2(1) <= a(1);
a_2(0) <= a(0);
b_3(5) <= b(5);
b_3(4) <= b(4);
b_3(3) <= b(3);
b_3(2) <= b(2);
b_3(1) <= b(1);
b_3(0) <= b(0);
VCC_0 : VCC
port map (
P => NLW_VCC_P_UNCONNECTED
);
GND_1 : GND
port map (
G => NLW_GND_G_UNCONNECTED
);
BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o95 :
LUT3
generic map(
INIT => X"80"
)
port map (
I0 =>
BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o26_16
,
I1 =>
BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o53_17
,
I2 =>
BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o80_18
,
O => BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_temp_result
);
BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o80 :
LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => a_2(1),
I1 => b_3(1),
I2 => a_2(0),
I3 => b_3(0),
O =>
BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o80_18
 
);
BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o53 :
LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => a_2(3),
I1 => b_3(3),
I2 => a_2(2),
I3 => b_3(2),
O =>
BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o53_17
 
);
BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o26 :
LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => a_2(5),
I1 => b_3(5),
I2 => a_2(4),
I3 => b_3(4),
O =>
BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o26_16
 
);
BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_gen_output_reg_output_reg_fd_output_1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_temp_result,
Q => qa_eq_b
);
BU2_XST_GND : GND
port map (
G => BU2_a_ge_b
);
 
end STRUCTURE;
 
-- synthesis translate_on
/pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/wraddr_lut_mem.xco
0,0 → 1,63
##############################################################
#
# Xilinx Core Generator version K.39
# Date: Mon May 09 12:17:18 2011
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = False
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc3s200
SET devicefamily = spartan3
SET flowvendor = Other
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = pq208
SET removerpms = False
SET simulationfiles = Structural
SET speedgrade = -4
SET verilogsim = False
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT Distributed_Memory_Generator family Xilinx,_Inc. 3.4
# END Select
# BEGIN Parameters
CSET ce_overrides=ce_overrides_sync_controls
CSET coefficient_file="C:/VERIFICATION PLATFORM/UDP_IP_FLEX/THE_FELSENSTEIN_COPROCESSOR/wraddr_lut.coe"
CSET common_output_ce=false
CSET common_output_clk=false
CSET component_name=wraddr_lut_mem
CSET data_width=6
CSET default_data=0
CSET default_data_radix=16
CSET depth=64
CSET dual_port_address=non_registered
CSET dual_port_output_clock_enable=false
CSET input_clock_enable=false
CSET input_options=non_registered
CSET memory_type=rom
CSET output_options=registered
CSET pipeline_stages=0
CSET qualify_we_with_i_ce=false
CSET reset_qdpo=false
CSET reset_qspo=false
CSET single_port_output_clock_enable=false
CSET sync_reset_qdpo=false
CSET sync_reset_qspo=false
# END Parameters
GENERATE
# CRC: 5b35cec9
 
/pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/comp_11b_equal.ngc
0,0 → 1,3
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.4e
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/pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/TARGET_EOF.vhd
0,0 → 1,106
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:22:56 11/30/2009
-- Design Name:
-- Module Name: TARGET_EOF - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity TARGET_EOF is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
start : in STD_LOGIC;
total_length_from_reg : in STD_LOGIC_VECTOR(15 downto 0);
eof_O : out STD_LOGIC);
end TARGET_EOF;
 
architecture Behavioral of TARGET_EOF is
 
signal count_end : std_logic:='0';
signal count_en_sig : std_logic:='0';
signal rst_counter : std_logic:='0';
 
component COUNTER_11B_EN_TRANS is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
count_en : in STD_LOGIC;
value_O : inout STD_LOGIC_VECTOR (10 downto 0));
end component;
 
signal value_O_tmp : std_logic_vector(10 downto 0);
 
component comp_11b_equal is
port (
qa_eq_b : out STD_LOGIC;
clk : in STD_LOGIC := 'X';
a : in STD_LOGIC_VECTOR ( 10 downto 0 );
b : in STD_LOGIC_VECTOR ( 10 downto 0 )
);
end component;
 
signal last_byte,last_byte_reg_in,last_byte_reg_out : std_logic;
 
begin
 
process(clk)
begin
if (rst='1' or count_end='1') then
count_en_sig<='0';
rst_counter<='1';
else
rst_counter<='0';
if clk'event and clk='1' then
if (start='1' and count_en_sig='0') then
count_en_sig<='1';
end if;
end if;
end if;
end process;
 
 
COUNT_TRANFERED_BYTES : COUNTER_11B_EN_TRANS port map
( rst =>rst_counter,
clk =>clk,
count_en => count_en_sig,
value_O =>value_O_tmp
);
 
COMP_TO_TARGET_LAST_BYTE : comp_11b_equal port map
(
qa_eq_b =>last_byte_reg_in,
clk =>clk,
a =>value_O_tmp,
b =>total_length_from_reg(10 downto 0)
);
 
process(clk)
begin
if clk'event and clk='1' then
last_byte_reg_out<=last_byte_reg_in;
end if;
end process;
eof_O<=not last_byte_reg_out;
count_end<=last_byte_reg_out;
end Behavioral;
 
/pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/MATCH_CMD.vhd
0,0 → 1,111
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:01:28 01/18/2011
-- Design Name:
-- Module Name: MATCH_CMD - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity MATCH_CMD is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
sof : in STD_LOGIC;
vld_i : in STD_LOGIC;
val_i : in STD_LOGIC_VECTOR (7 downto 0);
cmd_to_match : in STD_LOGIC_VECTOR(7 downto 0);
cmd_match : out STD_LOGIC);
end MATCH_CMD;
 
architecture Behavioral of MATCH_CMD is
 
TYPE state is (rst_state,
idle_state,
header_state
);
signal current_st,next_st: state;
 
signal allow_match, match_s: std_logic;
signal allow_match_v, val_i_to_match: std_logic_vector(7 downto 0);
 
begin
 
process(clk)
begin
if (rst='1') then
current_st<= rst_state;
elsif (clk'event and clk='1') then
current_st <= next_st;
end if;
end process;
 
process(current_st,sof,vld_i)
begin
case current_st is
 
when rst_state =>
 
allow_match<='0';
next_st<=idle_state;
when idle_state =>
 
allow_match<='0';
if sof='0' then
next_st <= header_state;
else
next_st <= idle_state;
end if;
 
when header_state =>
if vld_i='1' then
allow_match<='1';
next_st <= rst_state;
else
allow_match<='0';
next_st <= header_state;
end if;
 
end case;
end process;
 
allow_match_v <=(others=>allow_match);
val_i_to_match <= val_i and allow_match_v;
 
process(clk)
begin
if clk'event and clk='1' then
if val_i_to_match = cmd_to_match then
cmd_match <='1';
else
cmd_match <='0';
end if;
end if;
end process;
 
end Behavioral;
 
/pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/dist_mem_64x8.ngc
0,0 → 1,3
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.4e
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01=:m1Cm<5G9c9'6d<e3`8<6=44i3:94?=h<l0;66s|b483>4?|Vk?018h59d9>1a<>m27>o77j;<7f><c<5<k15h52588:a>;2j33n7089:8g8933=1l16::46e:?57??b34<964k4=769=`=:>802i6390;;f?83?20o015951b9><3<6k27397?l;<:7>4e<5191=n528382g>;?93;h706?:0a8yv7693:1?vP>109>=4<50272<7<7;|qf3?6=90qU==64^024?[77>2T:<85Q1168Z4643W;;>6P>009]`6=Yl;1Uh<5Qd19]gc=Ykl1Uoi5Qcb9]a3=Ym<1Ui95Qe29]a7=Ym81Ui=5Qdg9>e7<5=2wx544?:3y]b1=:0>0>86s|9983>7}Yn:164;4:4:p=2<72;qUj?5284860>{t1?0;6?uQf09><1<2<2wx584?:3y]b5=:0:0>86s|9583>7}Ymo164?4:4:p=6<72;qUih5280860>{t1;0;6?uQee9><5<2<2wxn94?:cy]ea=:?109;6389;04?81f2;=01:l5269>3f<5?27<h7<8;<5f>71<5>l1>:5290813>;>838<7p}m2;2954}Yij169k4>9:?6`?7>34?h6<74=4g95<=:=h0:563:9;3:?83e28301;85189>20<6127=;7?6;<40>4?<5?81=4526582=>;193;2708?:0;890>=901vo?50;32[ge34?m6<64=4f95==:=j0:463:e;3;?83f28201875199>1g<6027=:7?7;<46>4><5?=1=5526282<>;1:3;3708;:0:8937=9116:=4>8:?6<?7?3tyi<7>510y]ed=:=o0:;63:d;34?83d28=018k5169>1d<6?27>57?8;<7a>41<5?<1=:5264823>;1?3;<708<:058934=9>16:94>7:?55?7034<;6<94=4:952=z{hl1<7?>{_c:?83a28<018j5179>1f<6>27>i7?9;<7b>40<5<31=;525c822>;1>3;=708::048931=9?16:>4>6:?56?7134<?6<84=73953=:>90::63:8;35?xufm3:1=<uQa99>1c<6=27>h7?:;<7`>43<5<o1=8525`821>;213;>70;m:078930=9<16:84>5:?53?7234<86<;4=70950=:>=0:96391;36?80728?01865149~wf0=839pRoj4=4d967=:=l09>6s|c583>6}Yjj169i4=2:?6g?453tyh?7>53z\af>;2i38970;m:308yve52908wSln;<7:>74<5?=1>?5rsb394?5|Vk301;85239>20<5:2wxo=4?:2y]f==:>:09>6394;01?xuen3:1?vPm7:?56?4534<:6?<4}r`f>5<4sWh=708?:30890>=:;1v;j50;0x92>=:116954;e:p30<72;q6;54=9:?54?2b3ty347>52z?4<?2b342;6?<4}r55>5<5s4=26?64=7390`=z{>=1<7<t=6;96<=:>;0?i6s|8883>7}:?00?i6371;01?xu103:1>v38a;0;?8042=o0q~86:18181f2;301;:54d9~w=g=838p1:o54d9><7<5:2wx:l4?:3y>3g<5027=97:j;|q5f?6=:r7<n7<6;<45>1c<uz2i6=4={<5a>1c<5191>?5rs7a94?4|5>i1>5526687a>{t>l0;6?u27b81=>;213>n7p}7c;296~;0k3>n706;:308yv0a2909w09k:3:890g=<l1v:>50;0x92b=:0169o4;e:p<a<72;q6;i4;e:?;1?453ty<=7>52z?4a?4?34?h69k4}r51>5<5s4=n6?74=4f90`=z{1o1<7<t=6g90`=:0?09>6s|7283>7}:?o09463:e;6f?xu0<3:1>v38f;0:?83a2=o0q~6i:18181a2=o01595239~w<7=833p18h59g9>1a<>n27>577i;<7a><`<5?<15k52638:b>;1<33m708?:8d89<7=<l1v4>50;;x90e=1o169h46f:?6e??a34<>64h4=759=c=:>:02j6391;;e?83?20l014>54d9~yv56290:>v3=6;06?87f2mk01<o5d89>5d<c027:m7j8;<3b>a0<58k1h8521`824c=:9h0:<h521`824a=:9h0:<n521`824g=:9h0:<l521`8fe>;6i3lm70?n:d`894g=99:01<o5eb9~w64=83>p14m5519>5d<cl27:m7hj;<3b>`?<uzh?6=4={_cg?87f2hn0(4o5329~wg4=838pRlm4=0c9ef=#1h0886s|b083>7}Yik16=l4nb:&:e?523tyi<7>52z\be>;6i3kj7)7n:248yvga2909wSo6;<3b>d?<,0k1?:5rs`g94?4|Vh201<o5a99'=d<402wxo;4?:3y]fa=:9h0ih6*6a;1:?xud<3:1>vPmc:?2e?dd3-3j6>o4}ra0>5<5sWhi70?n:c`8 <g=;k1vn<50;0xZgg<58k1nl5+9`80g>{tk80;6?uQb89>5d<e12.2m7=k;|q`4?6=:rTi463>a;`;?!?f2:o0q~li:181[d034;j6o94$8c97c=z{ko1<7<t^c4894g=j?1/5l4;0:pf0<72;qUn8521`8a1>">i3>:7p}>1083>7}Y98;01<o51038 <g=<;1vkj50;0xZc2<58k1j95+9`877>{tnk0;6?uQf29>5d<a;2.2m7:;;|qee?6=:rTm>63>a;d1?!?f2=?0q~h6:181[`634;j6k?4$8c903=z{o21<7<t^g2894g=n91/5l4;7:pb2<72;qUik521`8fb>">i3>37p}i6;296~Xbm27:m7kj;%;b>1?<uzl>6=4={_gg?87f2ln0(4o54`9~yk7>93:1=vF6b:m5<4=83;pD4l4}o3:7?6=:rB2n6sa18694?4|@0h0qc?65;296~N>j2we=4850;0xL<d<ug;2;7>52zJ:f>{i9021<7<tH8`8yk7>13:1>vF6b:m5<g=838pD4l4}o3:f?6=:rB2n6sa18a94?4|@0h0qc?6d;296~N>j2we=4k50;0xL<d<ug;2j7>52zJ:f>{i9h:1<7<tH8`8yk7f93:1>vF6b:m5d4=838pD4l4}o3b7?6=:rB2n6F;d:m5d2=838pD4l4H5f8yk7f=3:1>vF6b:J7`>{i9h<1<7<tH8`8L1b<ug;j;7>52zJ:f>N3l2we=l650;0xL<d<@=n0qc?n9;296~N>j2B?h6sa1`c94?4|@0h0D9j4}o354?6=9rB2n6sa16594?7|@0h0qc?88;295~N>j2we=:750;3xL<d<ug;<m7>51zJ:f>{i9>h1<7?tH8`8yk70k3:1=vF6b:m52b=83;pD4l4}o34a?6=9rB2n6sa16d94?7|@0h0qc?70;295~N>j2we=5?50;3xL<d<ug;3>7>51zJ:f>{i9191<7?tH8`8yk7?<3:1=vF6b:m5=3=83;pD4l4}o3;2?6=9rB2n6sa19594?7|@0h0qc?78;295~N>j2we=5750;3xL<d<ug;3m7>51zJ:f>{i91h1<7?tH8`8yk7?k3:1=vF6b:m5=b=83;pD4l4}o3;a?6=9rB2n6sa19d94?7|@0h0qc?60;295~N>j2wvqpNOCz3f4?b1?l334pNOBz2~DEV|uIJ
/pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/REG_16B_WREN.vhd
0,0 → 1,56
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:15:16 11/27/2009
-- Design Name:
-- Module Name: REG_16B_WREN - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: 16bit wide Register with write enable option.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity REG_16B_WREN is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
wren : in STD_LOGIC;
input : in STD_LOGIC_VECTOR (15 downto 0);
output : out STD_LOGIC_VECTOR (15 downto 0));
end REG_16B_WREN;
 
architecture Behavioral of REG_16B_WREN is
 
begin
 
process(clk)
begin
if rst='1' then
output<="0000000000000000";
else
if clk'event and clk='1' then
if wren='1' then
output<=input;
end if;
end if;
end if;
end process;
 
end Behavioral;
 
/pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/IPV4_LUT_INDEXER.vhd
0,0 → 1,110
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:11:55 11/27/2009
-- Design Name:
-- Module Name: IPV4_LUT_INDEXER - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity IPV4_LUT_INDEXER is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
transmit_enable : in STD_LOGIC;
LUT_index : out STD_LOGIC_VECTOR (5 downto 0));
end IPV4_LUT_INDEXER;
 
architecture Behavioral of IPV4_LUT_INDEXER is
 
component dist_mem_64x8 is
port (
clk : in STD_LOGIC := 'X';
a : in STD_LOGIC_VECTOR ( 5 downto 0 );
qspo : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component;
 
component COUNTER_6B_LUT_FIFO_MODE is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
funct_sel : in STD_LOGIC; -- 0 for lut addressing, 1 for fifo addressing -- only LUT support is used
count_en : in STD_LOGIC;
value_O : inout STD_LOGIC_VECTOR (5 downto 0));
end component;
 
component comp_6b_equal is
port (
qa_eq_b : out STD_LOGIC;
clk : in STD_LOGIC := 'X';
a : in STD_LOGIC_VECTOR ( 5 downto 0 );
b : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
end component;
 
signal count_en_sig , count_end , rst_counter: std_logic :='0';
signal count_val: std_logic_Vector(5 downto 0):=(others=>'0');
signal count_en_sig_comb : std_logic;
constant lut_upper_address :std_logic_vector(5 downto 0):="100110"; -- position 38
 
begin
 
process(clk)
begin
if (rst='1' or count_end='1') then
count_en_sig<='0';
rst_counter<='1';
else
rst_counter<='0';
if clk'event and clk='1' then
if (transmit_enable='1' and count_en_sig='0') then
count_en_sig<='1';
end if;
end if;
end if;
end process;
 
LUT_END_CHECK : comp_6b_equal port map (
qa_eq_b =>count_end,
clk =>clk,
a =>count_val,
b =>lut_upper_address
 
);
 
count_en_sig_comb <=count_en_sig or transmit_enable;
 
 
 
LUT_INDEXER_MODULE : COUNTER_6B_LUT_FIFO_MODE port map (
rst => rst_counter,
clk => clk,
funct_sel =>'0', -- for now only one function is supported
count_en =>count_en_sig_comb,
value_O =>count_val
);
 
LUT_index<=count_val;
 
 
end Behavioral;
 
/pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/comp_6b_equal.xco
0,0 → 1,59
##############################################################
#
# Xilinx Core Generator version K.39
# Date: Thu Feb 04 10:02:26 2010
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = False
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc3s200
SET devicefamily = spartan3
SET flowvendor = Other
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = ft256
SET removerpms = False
SET simulationfiles = Structural
SET speedgrade = -4
SET verilogsim = False
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT Comparator family Xilinx,_Inc. 9.0
# END Select
# BEGIN Parameters
CSET aclr=false
CSET ainitval=0
CSET aset=false
CSET ce=false
CSET cepriority=Sync_Overrides_CE
CSET component_name=comp_6b_equal
CSET constantbport=false
CSET constantbportvalue=0000000000000000
CSET datatype=Unsigned
CSET nonregisteredoutput=false
CSET operation=eq
CSET pipelinestages=0
CSET radix=2
CSET registeredoutput=true
CSET sclr=false
CSET sset=false
CSET syncctrlpriority=Reset_Overrides_Set
CSET width=6
# END Parameters
GENERATE
# CRC: dc354663
 
/pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/ENABLE_USER_DATA_TRANSMISSION.vhd
0,0 → 1,64
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:05:48 12/04/2009
-- Design Name:
-- Module Name: ENABLE_USER_DATA_TRANSMISSION - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity ENABLE_USER_DATA_TRANSMISSION is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
start_usr_data_trans : in STD_LOGIC;
stop_usr_data_trans : in STD_LOGIC;
usr_data_sel : out STD_LOGIC);
end ENABLE_USER_DATA_TRANSMISSION;
 
architecture Behavioral of ENABLE_USER_DATA_TRANSMISSION is
 
signal usr_data_sel_prev : std_logic :='0';
 
begin
 
process(clk)
begin
if rst='1' then
usr_data_sel<='0';
usr_data_sel_prev<='0';
else
if clk'event and clk='1' then
if (start_usr_data_trans='1' and usr_data_sel_prev='0') then
usr_data_sel<='1';
usr_data_sel_prev<='1';
end if;
if (stop_usr_data_trans='0' and usr_data_sel_prev='1') then -- stop_usr_data_trans is active low
usr_data_sel<='0';
usr_data_sel_prev<='0';
end if;
end if;
end if;
end process;
 
end Behavioral;
 
/pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/UDP_IP_Core.vhd
0,0 → 1,188
-----------------------------------------------------------------------------------------
-- Copyright (C) 2010 Nikolaos Ch. Alachiotis --
-- --
-- Engineer: Nikolaos Ch. Alachiotis --
-- --
-- Contact: n.alachiotis@gmail.com --
-- --
-- Create Date: 04/03/2011 --
-- Module Name: UDP_IP_Core --
-- Target Devices: Virtex 5 FPGAs --
-- Tool versions: ISE 10.1 --
-- Description: This component can be used to transmit and receive UDP/IP --
-- Ethernet Packets (IPv4). --
-- Additional Comments: The core has been area-optimized and is suitable for direct --
-- PC-FPGA communication at Gigabit speed. --
-- --
-----------------------------------------------------------------------------------------
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity UDP_IP_Core is
Port ( rst : in STD_LOGIC; -- active-high
clk_125MHz : in STD_LOGIC;
-- Transmit signals
transmit_start_enable : in STD_LOGIC;
transmit_data_length : in STD_LOGIC_VECTOR (15 downto 0);
usr_data_trans_phase_on : out STD_LOGIC;
transmit_data_input_bus : in STD_LOGIC_VECTOR (7 downto 0);
start_of_frame_O : out STD_LOGIC;
end_of_frame_O : out STD_LOGIC;
source_ready : out STD_LOGIC;
transmit_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0);
--Receive Signals
rx_sof : in STD_LOGIC;
rx_eof : in STD_LOGIC;
input_bus : in STD_LOGIC_VECTOR(7 downto 0);
valid_out_usr_data : out STD_LOGIC;
usr_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0);
locked : out STD_LOGIC
);
end UDP_IP_Core;
 
architecture Behavioral of UDP_IP_Core is
 
component IPV4_PACKET_TRANSMITTER is
Port ( rst : in STD_LOGIC;
clk_125MHz : in STD_LOGIC;
transmit_start_enable : in STD_LOGIC;
transmit_data_length : in STD_LOGIC_VECTOR (15 downto 0);
usr_data_trans_phase_on : out STD_LOGIC;
transmit_data_input_bus : in STD_LOGIC_VECTOR (7 downto 0);
start_of_frame_O : out STD_LOGIC;
end_of_frame_O : out STD_LOGIC;
source_ready : out STD_LOGIC;
transmit_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0);
 
flex_wren: in STD_LOGIC;
flex_wraddr: in STD_LOGIC_VECTOR(5 downto 0);
flex_wrdata: in STD_LOGIC_VECTOR(7 downto 0);
flex_checksum_baseval: in std_logic_vector(15 downto 0)
);
end component;
 
component IPv4_PACKET_RECEIVER is
Port ( rst : in STD_LOGIC;
clk_125Mhz : in STD_LOGIC;
rx_sof : in STD_LOGIC;
rx_eof : in STD_LOGIC;
input_bus : in STD_LOGIC_VECTOR(7 downto 0);
valid_out_usr_data : out STD_LOGIC;
usr_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0));
end component;
 
component FLEX_CONTROL is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
r_sof : in STD_LOGIC;
r_usrvld : in STD_LOGIC;
r_data : in STD_LOGIC_VECTOR (7 downto 0);
r_usrdata: in STD_LOGIC_VECTOR (7 downto 0);
r_eof : in STD_LOGIC;
l_wren : out STD_LOGIC;
l_addr : out STD_LOGIC_VECTOR (5 downto 0);
l_data : out STD_LOGIC_VECTOR (7 downto 0);
checksum_baseval : out STD_LOGIC_VECTOR(15 downto 0);
locked : out STD_LOGIC
);
end component;
 
signal valid_out_usr_data_t : STD_LOGIC;
signal usr_data_output_bus_t : STD_LOGIC_VECTOR (7 downto 0);
 
signal flex_wren: STD_LOGIC;
signal flex_wraddr: STD_LOGIC_VECTOR(5 downto 0);
signal flex_wrdata: STD_LOGIC_VECTOR(7 downto 0);
signal flex_checksum_baseval: std_logic_vector(15 downto 0);
 
signal core_rst: std_logic;
 
component MATCH_CMD is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
sof : in STD_LOGIC;
vld_i : in STD_LOGIC;
val_i : in STD_LOGIC_VECTOR (7 downto 0);
cmd_to_match : in STD_LOGIC_VECTOR(7 downto 0);
cmd_match : out STD_LOGIC);
end component;
 
begin
 
MATCH_RST_CODE: MATCH_CMD Port Map
( rst => rst,
clk => clk_125MHz,
sof => rx_sof,
vld_i => valid_out_usr_data_t,
val_i => usr_data_output_bus_t,
cmd_to_match => "11111111",
cmd_match => core_rst
);
 
IPV4_PACKET_TRANSMITTER_port_map: IPV4_PACKET_TRANSMITTER
Port Map
( rst => core_rst,
clk_125MHz => clk_125MHz,
transmit_start_enable => transmit_start_enable,
transmit_data_length => transmit_data_length,
usr_data_trans_phase_on => usr_data_trans_phase_on,
transmit_data_input_bus => transmit_data_input_bus,
start_of_frame_O => start_of_frame_O,
end_of_frame_O => end_of_frame_O,
source_ready => source_ready,
transmit_data_output_bus => transmit_data_output_bus,
flex_wren => flex_wren,
flex_wraddr => flex_wraddr,
flex_wrdata => flex_wrdata,
flex_checksum_baseval => flex_checksum_baseval
);
 
 
IPv4_PACKET_RECEIVER_port_map: IPv4_PACKET_RECEIVER
Port Map
( rst => core_rst,
clk_125Mhz => clk_125Mhz,
rx_sof => rx_sof,
rx_eof => rx_eof,
input_bus => input_bus,
valid_out_usr_data => valid_out_usr_data_t,
usr_data_output_bus => usr_data_output_bus_t
);
valid_out_usr_data <= valid_out_usr_data_t;
usr_data_output_bus <= usr_data_output_bus_t;
FLEX_CONTROL_port_map: FLEX_CONTROL
Port Map
( rst => core_rst,
clk => clk_125Mhz,
r_sof => rx_sof,
r_usrvld => valid_out_usr_data_t,
r_data => input_bus,
r_usrdata => usr_data_output_bus_t,
r_eof => rx_eof,
l_wren => flex_wren,
l_addr => flex_wraddr,
l_data => flex_wrdata,
checksum_baseval => flex_checksum_baseval,
locked => locked
);
 
 
end Behavioral;
 
/pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/comp_11b_equal.vhd
0,0 → 1,249
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: K.39
-- \ \ Application: netgen
-- / / Filename: comp_11b_equal.vhd
-- /___/ /\ Timestamp: Thu Feb 04 11:01:48 2010
-- \ \ / \
-- \___\/\___\
--
-- Command : -intstyle ise -w -sim -ofmt vhdl C:\PHd_Projects\The_Felsenstein_CoProcessor\COREGEN_Design\tmp\_cg\comp_11b_equal.ngc C:\PHd_Projects\The_Felsenstein_CoProcessor\COREGEN_Design\tmp\_cg\comp_11b_equal.vhd
-- Device : 3s200ft256-4
-- Input file : C:/PHd_Projects/The_Felsenstein_CoProcessor/COREGEN_Design/tmp/_cg/comp_11b_equal.ngc
-- Output file : C:/PHd_Projects/The_Felsenstein_CoProcessor/COREGEN_Design/tmp/_cg/comp_11b_equal.vhd
-- # of Entities : 1
-- Design Name : comp_11b_equal
-- Xilinx : C:\Xilinx\10.1\ISE
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Development System Reference Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
 
 
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
 
entity comp_11b_equal is
port (
qa_eq_b : out STD_LOGIC;
clk : in STD_LOGIC := 'X';
a : in STD_LOGIC_VECTOR ( 10 downto 0 );
b : in STD_LOGIC_VECTOR ( 10 downto 0 )
);
end comp_11b_equal;
 
architecture STRUCTURE of comp_11b_equal is
signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and0000120_34 : STD_LOGIC;
signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and000093_33 : STD_LOGIC;
signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and000053_32 : STD_LOGIC;
signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and000026_31 : STD_LOGIC;
signal BU2_N01 : STD_LOGIC;
signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_temp_result : STD_LOGIC;
signal BU2_N1 : STD_LOGIC;
signal BU2_a_ge_b : STD_LOGIC;
signal NLW_VCC_P_UNCONNECTED : STD_LOGIC;
signal NLW_GND_G_UNCONNECTED : STD_LOGIC;
signal a_2 : STD_LOGIC_VECTOR ( 10 downto 0 );
signal b_3 : STD_LOGIC_VECTOR ( 10 downto 0 );
signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o : STD_LOGIC_VECTOR ( 1 downto 0 );
signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_async_o : STD_LOGIC_VECTOR ( 1 downto 1 );
begin
a_2(10) <= a(10);
a_2(9) <= a(9);
a_2(8) <= a(8);
a_2(7) <= a(7);
a_2(6) <= a(6);
a_2(5) <= a(5);
a_2(4) <= a(4);
a_2(3) <= a(3);
a_2(2) <= a(2);
a_2(1) <= a(1);
a_2(0) <= a(0);
b_3(10) <= b(10);
b_3(9) <= b(9);
b_3(8) <= b(8);
b_3(7) <= b(7);
b_3(6) <= b(6);
b_3(5) <= b(5);
b_3(4) <= b(4);
b_3(3) <= b(3);
b_3(2) <= b(2);
b_3(1) <= b(1);
b_3(0) <= b(0);
VCC_0 : VCC
port map (
P => NLW_VCC_P_UNCONNECTED
);
GND_1 : GND
port map (
G => NLW_GND_G_UNCONNECTED
);
BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and0000136 :
LUT4
generic map(
INIT => X"8000"
)
port map (
I0 =>
BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and000026_31
,
I1 =>
BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and000053_32
,
I2 =>
BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and000093_33
,
I3 =>
BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and0000120_34
,
O =>
BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o(0)
 
);
BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and0000120 :
LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => a_2(6),
I1 => b_3(6),
I2 => a_2(7),
I3 => b_3(7),
O =>
BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and0000120_34
 
);
BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and000093 :
LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => a_2(4),
I1 => b_3(4),
I2 => a_2(5),
I3 => b_3(5),
O =>
BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and000093_33
 
);
BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and000053 :
LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => a_2(2),
I1 => b_3(2),
I2 => a_2(3),
I3 => b_3(3),
O =>
BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and000053_32
 
);
BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and000026 :
LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => a_2(0),
I1 => b_3(0),
I2 => a_2(1),
I3 => b_3(1),
O =>
BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and000026_31
 
);
BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_1_and0000 :
LUT3
generic map(
INIT => X"09"
)
port map (
I0 => b_3(9),
I1 => a_2(9),
I2 => BU2_N01,
O =>
BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o(1)
 
);
BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_1_and0000_SW0 :
LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => a_2(10),
I1 => b_3(10),
I2 => a_2(8),
I3 => b_3(8),
O => BU2_N01
);
BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_opt_carry_tile_and_or_carry_muxs_0_i_mux :
MUXCY
port map (
CI =>
BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_async_o(1)
,
DI => BU2_a_ge_b,
S =>
BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o(0)
,
O => BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_temp_result
);
BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_opt_carry_tile_and_or_carry_muxs_1_i_mux :
MUXCY
port map (
CI => BU2_N1,
DI => BU2_a_ge_b,
S =>
BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o(1)
,
O =>
BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_async_o(1)
 
);
BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_gen_output_reg_output_reg_fd_output_1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_temp_result,
Q => qa_eq_b
);
BU2_XST_VCC : VCC
port map (
P => BU2_N1
);
BU2_XST_GND : GND
port map (
G => BU2_a_ge_b
);
 
end STRUCTURE;
 
-- synthesis translate_on
/pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/dist_mem_64x8.vhd
0,0 → 1,527
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: K.39
-- \ \ Application: netgen
-- / / Filename: dist_mem_64x8.vhd
-- /___/ /\ Timestamp: Mon May 09 14:16:57 2011
-- \ \ / \
-- \___\/\___\
--
-- Command : -intstyle ise -w -sim -ofmt vhdl "C:\VERIFICATION PLATFORM\UDP_IP_FLEX\COREGEN\tmp\_cg\dist_mem_64x8.ngc" "C:\VERIFICATION PLATFORM\UDP_IP_FLEX\COREGEN\tmp\_cg\dist_mem_64x8.vhd"
-- Device : 3s200pq208-4
-- Input file : C:/VERIFICATION PLATFORM/UDP_IP_FLEX/COREGEN/tmp/_cg/dist_mem_64x8.ngc
-- Output file : C:/VERIFICATION PLATFORM/UDP_IP_FLEX/COREGEN/tmp/_cg/dist_mem_64x8.vhd
-- # of Entities : 1
-- Design Name : dist_mem_64x8
-- Xilinx : C:\Xilinx\10.1\ISE
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Development System Reference Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
 
 
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
 
entity dist_mem_64x8 is
port (
clk : in STD_LOGIC := 'X';
we : in STD_LOGIC := 'X';
a : in STD_LOGIC_VECTOR ( 5 downto 0 );
d : in STD_LOGIC_VECTOR ( 7 downto 0 );
qspo : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end dist_mem_64x8;
 
architecture STRUCTURE of dist_mem_64x8 is
signal N0 : STD_LOGIC;
signal N1 : STD_LOGIC;
signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl_50 : STD_LOGIC;
signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl1_49 : STD_LOGIC;
signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N32 : STD_LOGIC;
signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N30 : STD_LOGIC;
signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N28 : STD_LOGIC;
signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N26 : STD_LOGIC;
signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N24 : STD_LOGIC;
signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N22 : STD_LOGIC;
signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N20 : STD_LOGIC;
signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N18 : STD_LOGIC;
signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N16 : STD_LOGIC;
signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N14 : STD_LOGIC;
signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N12 : STD_LOGIC;
signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N10 : STD_LOGIC;
signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N8 : STD_LOGIC;
signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N6 : STD_LOGIC;
signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N4 : STD_LOGIC;
signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N2 : STD_LOGIC;
signal a_2 : STD_LOGIC_VECTOR ( 5 downto 0 );
signal d_3 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal qspo_4 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int : STD_LOGIC_VECTOR ( 7 downto 0 );
signal BU2_qdpo : STD_LOGIC_VECTOR ( 0 downto 0 );
begin
a_2(5) <= a(5);
a_2(4) <= a(4);
a_2(3) <= a(3);
a_2(2) <= a(2);
a_2(1) <= a(1);
a_2(0) <= a(0);
d_3(7) <= d(7);
d_3(6) <= d(6);
d_3(5) <= d(5);
d_3(4) <= d(4);
d_3(3) <= d(3);
d_3(2) <= d(2);
d_3(1) <= d(1);
d_3(0) <= d(0);
qspo(7) <= qspo_4(7);
qspo(6) <= qspo_4(6);
qspo(5) <= qspo_4(5);
qspo(4) <= qspo_4(4);
qspo(3) <= qspo_4(3);
qspo(2) <= qspo_4(2);
qspo(1) <= qspo_4(1);
qspo(0) <= qspo_4(0);
VCC_0 : VCC
port map (
P => N1
);
GND_1 : GND
port map (
G => N0
);
BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => a_2(5),
I1 => we,
O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl_50
);
BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_qspo_int_0 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(0),
Q => qspo_4(0)
);
BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_qspo_int_1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(1),
Q => qspo_4(1)
);
BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_qspo_int_2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(2),
Q => qspo_4(2)
);
BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_qspo_int_3 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(3),
Q => qspo_4(3)
);
BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_qspo_int_4 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(4),
Q => qspo_4(4)
);
BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_qspo_int_5 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(5),
Q => qspo_4(5)
);
BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_qspo_int_6 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(6),
Q => qspo_4(6)
);
BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_qspo_int_7 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(7),
Q => qspo_4(7)
);
BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl1 : LUT2
generic map(
INIT => X"8"
)
port map (
I0 => a_2(5),
I1 => we,
O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl1_49
);
BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram1 : RAM32X1S
generic map(
INIT => X"00804000"
)
port map (
A0 => a_2(0),
A1 => a_2(1),
A2 => a_2(2),
A3 => a_2(3),
A4 => a_2(4),
D => d_3(0),
WCLK => clk,
WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl_50,
O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N2
);
BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram2 : RAM32X1S
generic map(
INIT => X"00000000"
)
port map (
A0 => a_2(0),
A1 => a_2(1),
A2 => a_2(2),
A3 => a_2(3),
A4 => a_2(4),
D => d_3(0),
WCLK => clk,
WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl1_49,
O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N4
);
BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram3 : RAM32X1S
generic map(
INIT => X"00000000"
)
port map (
A0 => a_2(0),
A1 => a_2(1),
A2 => a_2(2),
A3 => a_2(3),
A4 => a_2(4),
D => d_3(1),
WCLK => clk,
WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl_50,
O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N6
);
BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram6 : RAM32X1S
generic map(
INIT => X"00000000"
)
port map (
A0 => a_2(0),
A1 => a_2(1),
A2 => a_2(2),
A3 => a_2(3),
A4 => a_2(4),
D => d_3(2),
WCLK => clk,
WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl1_49,
O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N12
);
BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram4 : RAM32X1S
generic map(
INIT => X"00000000"
)
port map (
A0 => a_2(0),
A1 => a_2(1),
A2 => a_2(2),
A3 => a_2(3),
A4 => a_2(4),
D => d_3(1),
WCLK => clk,
WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl1_49,
O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N8
);
BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram5 : RAM32X1S
generic map(
INIT => X"00014000"
)
port map (
A0 => a_2(0),
A1 => a_2(1),
A2 => a_2(2),
A3 => a_2(3),
A4 => a_2(4),
D => d_3(2),
WCLK => clk,
WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl_50,
O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N10
);
BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram9 : RAM32X1S
generic map(
INIT => X"00800000"
)
port map (
A0 => a_2(0),
A1 => a_2(1),
A2 => a_2(2),
A3 => a_2(3),
A4 => a_2(4),
D => d_3(4),
WCLK => clk,
WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl_50,
O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N18
);
BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram7 : RAM32X1S
generic map(
INIT => X"00001000"
)
port map (
A0 => a_2(0),
A1 => a_2(1),
A2 => a_2(2),
A3 => a_2(3),
A4 => a_2(4),
D => d_3(3),
WCLK => clk,
WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl_50,
O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N14
);
BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram8 : RAM32X1S
generic map(
INIT => X"00000000"
)
port map (
A0 => a_2(0),
A1 => a_2(1),
A2 => a_2(2),
A3 => a_2(3),
A4 => a_2(4),
D => d_3(3),
WCLK => clk,
WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl1_49,
O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N16
);
BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram12 : RAM32X1S
generic map(
INIT => X"00000000"
)
port map (
A0 => a_2(0),
A1 => a_2(1),
A2 => a_2(2),
A3 => a_2(3),
A4 => a_2(4),
D => d_3(5),
WCLK => clk,
WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl1_49,
O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N24
);
BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram10 : RAM32X1S
generic map(
INIT => X"00000000"
)
port map (
A0 => a_2(0),
A1 => a_2(1),
A2 => a_2(2),
A3 => a_2(3),
A4 => a_2(4),
D => d_3(4),
WCLK => clk,
WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl1_49,
O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N20
);
BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram11 : RAM32X1S
generic map(
INIT => X"00010000"
)
port map (
A0 => a_2(0),
A1 => a_2(1),
A2 => a_2(2),
A3 => a_2(3),
A4 => a_2(4),
D => d_3(5),
WCLK => clk,
WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl_50,
O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N22
);
BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram15 : RAM32X1S
generic map(
INIT => X"00000000"
)
port map (
A0 => a_2(0),
A1 => a_2(1),
A2 => a_2(2),
A3 => a_2(3),
A4 => a_2(4),
D => d_3(7),
WCLK => clk,
WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl_50,
O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N30
);
BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram13 : RAM32X1S
generic map(
INIT => X"00504000"
)
port map (
A0 => a_2(0),
A1 => a_2(1),
A2 => a_2(2),
A3 => a_2(3),
A4 => a_2(4),
D => d_3(6),
WCLK => clk,
WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl_50,
O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N26
);
BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram14 : RAM32X1S
generic map(
INIT => X"00000000"
)
port map (
A0 => a_2(0),
A1 => a_2(1),
A2 => a_2(2),
A3 => a_2(3),
A4 => a_2(4),
D => d_3(6),
WCLK => clk,
WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl1_49,
O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N28
);
BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_Mram_ram16 : RAM32X1S
generic map(
INIT => X"00000000"
)
port map (
A0 => a_2(0),
A1 => a_2(1),
A2 => a_2(2),
A3 => a_2(3),
A4 => a_2(4),
D => d_3(7),
WCLK => clk,
WE => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_write_ctrl1_49,
O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N32
);
BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_inst_LPM_MUX711 : LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => a_2(5),
I1 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N30,
I2 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N32,
O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(7)
);
BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_inst_LPM_MUX611 : LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => a_2(5),
I1 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N26,
I2 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N28,
O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(6)
);
BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_inst_LPM_MUX511 : LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => a_2(5),
I1 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N22,
I2 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N24,
O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(5)
);
BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_inst_LPM_MUX411 : LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => a_2(5),
I1 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N18,
I2 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N20,
O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(4)
);
BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_inst_LPM_MUX311 : LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => a_2(5),
I1 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N14,
I2 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N16,
O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(3)
);
BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_inst_LPM_MUX211 : LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => a_2(5),
I1 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N10,
I2 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N12,
O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(2)
);
BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_inst_LPM_MUX111 : LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => a_2(5),
I1 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N6,
I2 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N8,
O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(1)
);
BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_inst_LPM_MUX11 : LUT3
generic map(
INIT => X"E4"
)
port map (
I0 => a_2(5),
I1 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N2,
I2 => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_N4,
O => BU2_U0_gen_sp_ram_spram_inst_PipeRAM_1_spo_int(0)
);
BU2_XST_GND : GND
port map (
G => BU2_qdpo(0)
);
 
end STRUCTURE;
 
-- synthesis translate_on
/pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/wraddr_lut_mem.ngc
0,0 → 1,3
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.4e
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/pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/IPv4_PACKET_RECEIVER.vhd
0,0 → 1,182
-----------------------------------------------------------------------------------------
-- Copyright (C) 2010 Nikolaos Ch. Alachiotis --
-- --
-- Engineer: Nikolaos Ch. Alachiotis --
-- --
-- Contact: alachiot@cs.tum.edu --
-- n.alachiotis@gmail.com --
-- --
-- Create Date: 14:32:06 02/07/2010 --
-- Module Name: IPv4_PACKET_RECEIVER --
-- Target Devices: Virtex 5 FPGAs --
-- Tool versions: ISE 10.1 --
-- Description: This component can be used to receive IPv4 Ethernet Packets. --
-- Additional Comments: --
-- --
-- The receiver does not operate properly for data section of 1 or 2 bytes only. --
-- --
-----------------------------------------------------------------------------------------
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity IPv4_PACKET_RECEIVER is
Port ( rst : in STD_LOGIC;
clk_125Mhz : in STD_LOGIC;
rx_sof : in STD_LOGIC;
rx_eof : in STD_LOGIC;
input_bus : in STD_LOGIC_VECTOR(7 downto 0);
valid_out_usr_data : out STD_LOGIC;
usr_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0));
end IPv4_PACKET_RECEIVER;
 
architecture Behavioral of IPv4_PACKET_RECEIVER is
 
component PACKET_RECEIVER_FSM is
Port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
-- Signals from EMAC
rx_sof: in STD_LOGIC; -- active low input
rx_eof: in STD_LOGIC; -- active low input
-- Signals to Counter and Comparator
sel_comp_Bval: out STD_LOGIC;
comp_Bval: out STD_LOGIC_VECTOR(10 downto 0);
rst_count : out STD_LOGIC;
en_count : out STD_LOGIC;
-- Signal from Comparator
comp_eq: in STD_LOGIC;
-- Signals to Length Register
wren_MSbyte: out STD_LOGIC;
wren_LSbyte: out STD_LOGIC;
-- Signal to user interface
valid_out_usr_data : out STD_LOGIC);
end component;
 
component REG_8b_wren is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
wren : in STD_LOGIC;
input_val : in STD_LOGIC_VECTOR (7 downto 0);
output_val : inout STD_LOGIC_VECTOR(7 downto 0));
end component;
 
component COUNTER_11B_EN_RECEIV is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
count_en : in STD_LOGIC;
value_O : inout STD_LOGIC_VECTOR (10 downto 0));
end component;
 
component comp_11b_equal is
port (
qa_eq_b : out STD_LOGIC;
clk : in STD_LOGIC := 'X';
a : in STD_LOGIC_VECTOR ( 10 downto 0 );
b : in STD_LOGIC_VECTOR ( 10 downto 0 )
);
end component;
 
signal sel_comp_Bval,
rst_count,
en_count,
comp_eq,
wren_MSbyte,
wren_LSbyte: STD_LOGIC;
signal MSbyte_reg_val_out,
LSbyte_reg_val_out : STD_LOGIC_VECTOR(7 downto 0);
signal counter_val,
match_val,
comp_Bval,
comp_sel_val_vec,
comp_n_sel_val_vec,
length_val: STD_LOGIC_VECTOR(10 downto 0);
 
constant length_offest : STD_LOGIC_VECTOR(7 downto 0):="00001010";
-- This value is formed as 2 (1 clock the latency of comparator and 1 clock fro changing the FSM state) + 8 (number of bytes of UDP header section)
 
begin
 
usr_data_output_bus<=input_bus;
 
PACKET_RECEIVER_FSM_port_map: PACKET_RECEIVER_FSM Port Map
(
rst => rst,
clk => clk_125MHz,
 
rx_sof => rx_sof,
rx_eof => rx_eof,
sel_comp_Bval => sel_comp_Bval,
comp_Bval => comp_Bval,
rst_count => rst_count,
en_count => en_count,
comp_eq => comp_eq,
 
wren_MSbyte => wren_MSbyte,
wren_LSbyte => wren_LSbyte,
 
valid_out_usr_data => valid_out_usr_data
);
 
MSbyte_REG: REG_8b_wren Port Map
(
rst => rst,
clk => clk_125MHz,
wren => wren_MSbyte,
input_val => input_bus,
output_val =>MSbyte_reg_val_out
);
 
LSbyte_REG: REG_8b_wren Port Map
(
rst => rst,
clk => clk_125MHz,
wren => wren_LSbyte,
input_val => input_bus,
output_val =>LSbyte_reg_val_out
);
COUNTER_11B_EN_port_map: COUNTER_11B_EN_RECEIV Port Map
(
rst => rst_count,
clk => clk_125MHz,
count_en => en_count,
value_O => counter_val
);
 
Comp_11b_equal_port_map: Comp_11b_equal Port Map
(
qa_eq_b => comp_eq,
clk => clk_125MHz,
a => counter_val,
b => match_val
);
length_val(7 downto 0)<= LSbyte_reg_val_out-length_offest;
length_val(10 downto 8)<= MSbyte_reg_val_out (2 downto 0);
comp_sel_val_vec<=(others=> sel_comp_Bval);
comp_n_sel_val_vec<= (others=> not sel_comp_Bval);
 
match_val<= (comp_sel_val_vec and length_val) or (comp_n_sel_val_vec and comp_Bval);
 
end Behavioral;
 
/pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Spartan3/FLEX_CONTROL.vhd
0,0 → 1,138
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:06:05 01/12/2011
-- Design Name:
-- Module Name: FLEX_CONTROL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity FLEX_CONTROL is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
r_sof : in STD_LOGIC;
r_usrvld : in STD_LOGIC;
r_data : in STD_LOGIC_VECTOR (7 downto 0);
r_usrdata: in STD_LOGIC_VECTOR (7 downto 0);
r_eof : in STD_LOGIC;
l_wren : out STD_LOGIC;
l_addr : out STD_LOGIC_VECTOR (5 downto 0);
l_data : out STD_LOGIC_VECTOR (7 downto 0);
checksum_baseval : out STD_LOGIC_VECTOR(15 downto 0);
locked : out STD_LOGIC
);
end FLEX_CONTROL;
 
architecture Behavioral of FLEX_CONTROL is
 
component MATCH_CMD_CODE is
Port ( clk : in STD_LOGIC;
vld : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(7 downto 0);
eof : in STD_LOGIC;
cmd_code : in STD_LOGIC_VECTOR (7 downto 0);
sig_out : out STD_LOGIC);
end component;
 
component MATCH_CMD is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
sof : in STD_LOGIC;
vld_i : in STD_LOGIC;
val_i : in STD_LOGIC_VECTOR (7 downto 0);
cmd_to_match : in STD_LOGIC_VECTOR(7 downto 0);
cmd_match : out STD_LOGIC);
end component;
 
signal config_en, ulock_en, wren_checksum_1, wren_checksum_2,local_rst: std_logic;
 
component CONFIG_CONTROL is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
config_en : in STD_LOGIC;
nxt_sof : in STD_LOGIC;
wren : out STD_LOGIC;
addr : out STD_LOGIC_VECTOR (5 downto 0);
ulock_en : in STD_LOGIC;
wren_checksum_1 : out STD_LOGIC;
wren_checksum_2 : out STD_LOGIC;
locked : out STD_LOGIC
);
end component;
 
signal checksum_baseval_t: std_logic_vector(15 downto 0);
 
begin
 
MATCH_RST_CODE: MATCH_CMD Port Map
( rst => rst,
clk => clk,
sof => r_sof,
vld_i => r_usrvld,
val_i => r_usrdata,
cmd_to_match => "00001111",
cmd_match => config_en
);
 
ulock_en <= '0';
 
CONFIG_CONTROL_FSM: CONFIG_CONTROL Port Map
( rst => rst,
clk => clk,
config_en => config_en,
nxt_sof => r_sof,
wren => l_wren,
addr => l_addr,
ulock_en => ulock_en,
wren_checksum_1 => wren_checksum_1,
wren_checksum_2 => wren_checksum_2,
locked => locked
);
 
process(clk)
begin
if rst = '1' then
checksum_baseval_t <= (others=>'0');
else
if clk'event and clk='1' then
if wren_checksum_1='1' then
checksum_baseval_t(15 downto 8) <= r_data;
end if;
if wren_checksum_2='1' then
checksum_baseval_t(7 downto 0) <= r_data;
end if;
end if;
end if;
end process;
 
checksum_baseval <= checksum_baseval_t;
 
process(clk)
begin
if clk'event and clk='1' then
l_data <= r_data;
end if;
end process;
 
end Behavioral;
 
/pc_fpga_com/trunk/PC_FPGA_PLATFPORM/SOFTWARE/fpga_com.h
0,0 → 1,65
/*
* Copyright (C) 2011 Simon A. Berger
*
* This program is free software; you may redistribute it and/or modify its
* under the terms of the GNU Lesser General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*/
 
#include <arpa/inet.h>
#include <stdint.h>
 
#ifdef __cplusplus
extern "C" {
#endif
const static int FPC_CODE_CHAR = 1;
const static int FPC_CODE_SHORT = 2;
const static int FPC_CODE_INT = 3;
const static int FPC_CODE_LONG = 5;
const static int FPC_CODE_FLOAT = 4;
const static int FPC_CODE_DOUBLE = 6;
 
typedef struct {
/* local and remote socket addresses */
struct sockaddr_in l_sockaddr;
struct sockaddr_in d_sockaddr;
/* my socket */
int s;
size_t mtu;
} fpga_con_t;
 
 
void fpga_con_init( fpga_con_t *con, const void *daddr, int lport, int dport );
ssize_t fpga_con_send( fpga_con_t *con, const void *buf, size_t len );
void fpga_con_send_init_packet( fpga_con_t *con );
ssize_t fpga_con_block_recv( fpga_con_t *con, void *dbuf, size_t dsize );
 
 
 
int fpga_con_send_charv( fpga_con_t *con, char *buf, size_t n );
int fpga_con_send_shortv( fpga_con_t *con, int16_t *buf, size_t n );
int fpga_con_send_intv( fpga_con_t *con, int32_t *buf, size_t n );
int fpga_con_send_longv( fpga_con_t *con, int64_t *buf, size_t n );
int fpga_con_send_floatv( fpga_con_t *con, float *buf, size_t n );
int fpga_con_send_doublev( fpga_con_t *con, double *buf, size_t n );
 
 
void fpga_con_rpack_char( fpga_con_t *con, int size );
void fpga_con_rpack_short( fpga_con_t *con, int size );
void fpga_con_rpack_int( fpga_con_t *con, int size );
void fpga_con_rpack_long( fpga_con_t *con, int size );
void fpga_con_rpack_float( fpga_con_t *con, int size );
void fpga_con_rpack_double( fpga_con_t *con, int size );
 
#ifdef __cplusplus
}
#endif
/pc_fpga_com/trunk/PC_FPGA_PLATFPORM/SOFTWARE/background_reader.cpp
0,0 → 1,551
/*
* Copyright (C) 2011 Simon A. Berger
*
* This program is free software; you may redistribute it and/or modify its
* under the terms of the GNU Lesser General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*/
 
#include <cstdio>
#include <csignal>
#include <sys/socket.h>
#include <boost/thread/locks.hpp>
#include <endian.h>
 
#include "background_reader.h"
#include "fpga_com.h"
 
static void handler( int signal ) {
//printf( "signal: %d\n", signal );
}
 
background_reader::background_reader(int s, size_t size)
: m_stop(false),
m_socket(s),
m_max_size(size),
m_pq_mem(0),
m_pq_max_mem(0),
m_pq_max_depth(0),
N_THREADS(1),
m_run_barrier(N_THREADS + 1),
m_threads_joined(false)
//m_native_handle(0)
{
 
}
 
background_reader::~background_reader()
{
if( !m_threads_joined ) {
printf( "WARNING: background_reader::~background_reader(): threads not joined!\n" );
}
}
 
 
void background_reader::start() {
/// m_thread.reset( new boost::thread( boost::bind(&background_reader::run, this)));
printf( "starting %zd background reader threads\n", N_THREADS );
//boost::barrier run_barrier( N_THREADS + 1 );
while( m_thread_group.size() < N_THREADS ) {
m_thread_group.create_thread(boost::bind(&background_reader::run, this ));
}
m_run_barrier.wait();
}
 
void background_reader::run()
{
// BIG-UGLY-KLUDGE-WARNING!
// we have to install a signal handler, in order to disable the auto-restart behaviour of the recv call...
// This is necessary to make the recv call interuptable (= return -1 on interrupt). Otherwise the
// bg threads would either wait forever, or we would need at least two syscalls per recv (any solution that involves select).
//
// the 'handler' does nothing, as we are only interested in interrupting the recv...
 
struct sigaction sa;
sa.sa_handler = handler;
sigemptyset(&sa.sa_mask);
sa.sa_flags = 0;
 
sigaction( SIGUSR1, &sa, 0 );
 
//m_native_handle = pthread_self();
{
lock_guard_t lock( m_nh_mtx );
m_native_handles.push_back( pthread_self() );
}
const size_t MTU = 64 * 1024;
 
std::vector<char>bufs(MTU);
char *buf = bufs.data();
 
//run_barrier->wait();
//run_barrier = 0;
m_run_barrier.wait();
while ( !m_stop ) {
ssize_t s = recv( m_socket, buf, MTU, 0 );
// if( s < 1024 && s != -1 ) {
// printf( "recved term packet %p\n", (void*)pthread_self() );
// }
//printf( "recv: %zd\n", s );
if ( s == -1 && errno == EINTR ) {
printf( "interrupted\n" );
} else {
lock_guard_t lock( m_pq_mtx );
m_pq.push_back(std::string(buf, buf+s));
m_pq_mem += s;
m_pq_max_mem = std::max( m_pq_mem, m_pq_max_mem );
m_pq_max_depth = std::max( m_pq.size(), m_pq_max_depth );
}
// printf( "notify\n" );
m_can_read_condition.notify_one();
}
printf( "background reader thread exit\n" );
}
 
ssize_t background_reader::block_recv(void* buf, size_t size)
{
boost::unique_lock<mutex_t> lock( m_pq_mtx );
 
while ( ! m_pq.size() > 0 && !m_stop ) {
// printf( "cond_wait\n" );
m_can_read_condition.wait(lock);
}
 
if( m_pq.size() == 0 ) {
return -1;
}
std::string &pbuf = m_pq.front();
 
m_pq_mem -= pbuf.size();
ssize_t s = std::min( size, pbuf.size() );
std::copy( pbuf.begin(), pbuf.end(), (char *)buf );
m_pq.pop_front();
 
return s;
}
 
 
ssize_t background_reader::poll()
{
lock_guard_t lock( m_pq_mtx );
if( m_pq.size() > 0 ) {
return m_pq.front().size();
} else {
return -1;
}
}
 
 
void background_reader::interrupt() {
//boost::thread::native_handle_type h = m_thread->native_handle();
// pthread_kill( m_native_handle, SIGUSR1 );
lock_guard_t lock( m_nh_mtx );
for( std::vector<pthread_t>::iterator it = m_native_handles.begin(); it != m_native_handles.end(); ++it ) {
pthread_kill( *it, SIGUSR1 );
}
}
 
void background_reader::join() {
// m_thread->join();
m_thread_group.join_all();
 
printf( "pq max size (bytes): %zd\n", m_pq_max_mem );
printf( "pq max depth (#packets): %zd\n", m_pq_max_depth );
m_threads_joined = true;
}
 
ssize_t background_reader::purge()
{
lock_guard_t lock( m_pq_mtx );
ssize_t s = m_pq.size();
m_pq.clear();
 
return s;
}
 
 
 
// int mainx() {
// fpga_con_t fc;
//
// fpga_con_init( &fc, "131.159.28.113", 12340, 12350 );
//
//
//
// background_reader bgr( fc.s, 1024 * 1024 * 10 );
//
// bgr.start();
//
// char buf[1024];
// memset( buf, 0, 1024 );
//
//
// const size_t rbuf_size = 10 * 1024;
// char rbuf[rbuf_size];
//
// printf( "sleep\n" );
// // usleep( 2000000 );
// printf( "close\n" );
// //close( fc.s );
//
// //bgr.stop();
// //bgr.interrupt();
// //getchar();
//
// // bgr.join();
//
// printf( "joined\n" );
// size_t n = 0;
// for ( int i = 0; i < 10; i++ ) {
// fpga_con_send( &fc, buf, 1024 );
// printf( "sent\n" );
//
//
//
// while (true) {
// size_t s = bgr.block_recv( rbuf, rbuf_size );
// n++;
// // printf( "recv: %zd\n", s );
// if ( s < 1024 ) {
// break;
// }
// }
//
// printf( "recved: %zd\n", n );
// }
//
// bgr.stop();
// bgr.interrupt();
// bgr.join();
// printf( "bg reader joined. exit.\n" );
// }
 
 
 
static inline background_reader &get_bgr( fpga_bgr_t *cbgr ) {
assert( cbgr != 0 );
assert( cbgr->bgr_cpp != 0 );
return *(static_cast<background_reader*>(cbgr->bgr_cpp));
}
 
void fpga_bgr_init( fpga_bgr_t *cbgr, int socket, size_t size ) {
memset( cbgr, 0, sizeof( fpga_bgr_t ));
background_reader *bgr = new background_reader(socket, size);
cbgr->bgr_cpp = bgr;
}
 
void fpga_bgr_delete( fpga_bgr_t *cbgr ) {
 
background_reader *bgr = static_cast<background_reader*>(cbgr->bgr_cpp);
delete bgr;
}
 
void fpga_bgr_start( fpga_bgr_t *cbgr) {
background_reader &bgr = get_bgr(cbgr);
bgr.start();
}
ssize_t fpga_bgr_block_recv( fpga_bgr_t *cbgr, void *buf, size_t size ) {
background_reader &bgr = get_bgr(cbgr);
return bgr.block_recv(buf, size);
}
ssize_t fpga_bgr_poll( fpga_bgr_t *cbgr ) {
background_reader &bgr = get_bgr(cbgr);
return bgr.poll();
}
void fpga_bgr_stop_interrupt_join( fpga_bgr_t *cbgr) {
background_reader &bgr = get_bgr(cbgr);
bgr.stop();
bgr.interrupt();
bgr.join();
}
 
 
// template <typename T>
// inline static T swap_endian( T &v ) {
//
// T vo = v;
// uint8_t *vb = (uint8_t*) &vo;
//
// for( size_t i = 0; i < sizeof(T) / 2; i++ ) {
// std::swap(vb[i], vb[sizeof(T) - i - 1]);
//
// }
// return vo;
// }
 
 
template<typename T,size_t N>
struct swap_endian {
inline T operator()( T &v ) {
T vo = v;
uint8_t *vb = (uint8_t*) &vo;
for( size_t i = 0; i < sizeof(T) / 2; i++ ) {
std::swap(vb[i], vb[sizeof(T) - i - 1]);
}
return vo;
}
};
 
 
template<typename T>
struct swap_endian<T,2> {
inline T operator()( T &v ) {
uint16_t t = __bswap_16(*((uint16_t*)&v));
T* r = (T*)&t; // we don't want to dereference a type-punned pointer, do we?
return *r;
}
};
 
 
template<typename T>
struct swap_endian<T,4> {
inline T operator()( T &v ) {
uint32_t t = __bswap_32(*((uint32_t*)&v));
T* r = (T*)&t;
return *r;
}
};
 
template<typename T>
struct swap_endian<T,8> {
inline T operator()( T &v ) {
uint64_t t = __bswap_64(*((uint64_t*)&v));
T* r = (T*)&t;
return *r;
}
};
 
 
 
 
 
template<typename T>
struct swappy_au {
const static size_t N = sizeof(T);
swap_endian<T,N> swap;
inline void operator()( void * dest, void * src, size_t n ) {
std::copy( (char *)src, ((char *)src) + n * N, (char *)dest );
//std::memcpy( dest, src, n * N );
T * ptr = (T *)dest;
T * end = ptr + n;
// do the endian swapping in place in the aligned buffer
while( ptr < end ) {
*ptr = swap( *ptr );
ptr++;
}
}
 
};
 
template<typename T>
struct swappy_aa {
const static size_t N = sizeof(T);
swap_endian<T,N> swap;
inline void operator()( void * dest, void * src, size_t n ) {
T * sptr = (T *)src;
T * ptr = (T *)dest;
T * end = ptr + n;
// copy and swap on the fly, assuming that both buffers are aligned
while( ptr < end ) {
*ptr = swap( *sptr );
ptr++;
sptr++;
}
}
 
};
 
 
template<typename T>
struct xerox_plain {
const static size_t N = sizeof(T);
inline void operator()( void * dest, void * src, size_t n ) {
std::copy( (char*)src, ((char*)src) + n * N, (char*)dest ); // using char* here to prevent std;:copy form making any assumptions about th alignment of src/dest
//std::copy( (T*)src, ((T*)src) + n, (T*)dest );
}
};
 
 
// template <typename T>
// inline T passthrough( T &v ) {
//
// return v;
// }
//
 
template <typename T,class CopyF>
static bool fpga_bgr_recv_genv( fpga_bgr_t *cbgr, T *buf, size_t n, char ht ) {
background_reader &bgr = get_bgr(cbgr);
T *buf_end = buf + n;
T *ptr = buf;
const size_t MPU = 9000;
uint8_t rbuf[MPU];
CopyF xerox;
while( ptr < buf_end ) {
ssize_t raw_size = bgr.block_recv(rbuf, MPU);
// printf( "ptr: %p %zd %d %d %d %d\n", ptr, size, rbuf[0], rbuf[1], rbuf[2], rbuf[3] );
assert( raw_size > 1 );
if( rbuf[0] != ht ) {
printf( "drop wrong packet type: %d %d\n", rbuf[0], ht );
}
ssize_t size = raw_size - 1;
uint8_t *rptr = rbuf + 1;
ssize_t ne = size / sizeof(T);
ssize_t left = buf_end - buf;
ssize_t to_copy = std::min( ne, left );
xerox( ptr, rptr, to_copy );
ptr += to_copy;
}
return true;
}
 
int fpga_bgr_recv_charv( fpga_bgr_t *bgr, char *buf, size_t n ) {
return fpga_bgr_recv_genv<char,xerox_plain<char> >( bgr, buf, n, FPC_CODE_CHAR );
}
 
int fpga_bgr_recv_shortv( fpga_bgr_t *bgr, int16_t *buf, size_t n ) {
return fpga_bgr_recv_genv<int16_t,swappy_au<int16_t> >( bgr, buf, n, FPC_CODE_SHORT );
}
int fpga_bgr_recv_intv( fpga_bgr_t *bgr, int32_t *buf, size_t n ) {
return fpga_bgr_recv_genv<int32_t,swappy_au<int32_t> >( bgr, buf, n, FPC_CODE_INT );
}
 
int fpga_bgr_recv_longv( fpga_bgr_t *bgr, int64_t *buf, size_t n ) {
return fpga_bgr_recv_genv<int64_t,swappy_au<int64_t> >( bgr, buf, n, FPC_CODE_LONG );
}
 
int fpga_bgr_recv_floatv( fpga_bgr_t *bgr, float *buf, size_t n ) {
return fpga_bgr_recv_genv<float,swappy_au<float> >( bgr, buf, n, FPC_CODE_FLOAT );
}
 
int fpga_bgr_recv_doublev( fpga_bgr_t *bgr, double *buf, size_t n ) {
//return fpga_bgr_recv_genv<double,xerox_plain<double,8> >( bgr, buf, n );
return fpga_bgr_recv_genv<double,swappy_au<double> >( bgr, buf, n, FPC_CODE_DOUBLE );
}
 
#if 0
 
 
int main() {
fpga_con_t fc;
 
fpga_con_init( &fc, "131.159.28.113", 12340, 12350 );
 
fpga_bgr_t bgr;
 
fpga_bgr_init( &bgr, fc.s, 1024 * 1024 * 10 );
fpga_bgr_start( &bgr );
char buf[1024];
memset( buf, 0, 1024 );
int ibuf[1000];
std::fill( ibuf, ibuf + 1000, 666 );
const size_t rbuf_size = 10 * 1024;
char rbuf[rbuf_size];
 
// printf( "sleep\n" );
// usleep( 2000000 );
// printf( "close\n" );
//close( fc.s );
 
//bgr.stop();
//bgr.interrupt();
//getchar();
 
// bgr.join();
 
// printf( "joined\n" );
size_t n = 0;
for ( int i = 0; i < 1; i++ ) {
//fpga_con_send( &fc, buf, 1024 );
fpga_con_send_intv( &fc, ibuf, 1000 );
printf( "sent\n" );
 
double iv[1000];
bool succ = fpga_bgr_recv_doublev( &bgr, iv, 1000 );
for( int i = 0; i < 1000; i++ ) {
printf( "%.2f ", iv[i] );
if( i % 20 == 19 ) {
printf( "\n" );
}
}
printf( "\n" );
 
printf( "recved: %d\n", succ );
}
fpga_bgr_stop_interrupt_join( &bgr );
printf( "bg reader joined. exit.\n" );
fpga_bgr_delete( &bgr );
}
#endif
/pc_fpga_com/trunk/PC_FPGA_PLATFPORM/SOFTWARE/background_reader.h
0,0 → 1,115
/*
* Copyright (C) 2011 Simon A. Berger
*
* This program is free software; you may redistribute it and/or modify its
* under the terms of the GNU Lesser General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*/
 
 
#ifndef BACKGROUND_READER_H
#define BACKGROUND_READER_H
 
 
#ifdef __cplusplus
 
#include <boost/thread/mutex.hpp>
#include <boost/thread/thread.hpp>
#include <boost/thread/barrier.hpp>
#include <boost/scoped_ptr.hpp>
 
#include <deque>
#include <vector>
 
#include <pthread.h>
#include <stdint.h>
// the all singing, all dancing background reader, written in shiny new c++
 
class background_reader
{
typedef boost::mutex mutex_t;
//typedef boost::unique_lock<mutex_t> unique_lock_t;
typedef boost::lock_guard<mutex_t> lock_guard_t;
boost::condition_variable m_can_read_condition;
boost::mutex m_pq_mtx;
//boost::scoped_ptr<boost::thread> m_thread;
boost::thread_group m_thread_group;
volatile bool m_stop; // FIXME: use atomic var
int m_socket;
size_t m_max_size;
std::deque<std::string> m_pq;
size_t m_pq_mem;
size_t m_pq_max_mem;
size_t m_pq_max_depth;
//pthread_t m_native_handle;
boost::mutex m_nh_mtx;
std::vector<pthread_t> m_native_handles;
const size_t N_THREADS;
boost::barrier m_run_barrier;
bool m_threads_joined;
void run();
public:
background_reader( int s, size_t size );
virtual ~background_reader();
void start();
void interrupt();
void stop() { m_stop = true; __sync_synchronize(); } // try to make sure that the new value of m_stop is visible to all bg threads before interrupt is called.
void join();
ssize_t block_recv( void* buf, size_t size );
ssize_t poll();
ssize_t purge();
 
 
};
#endif
 
// the boring old ansi c interface
 
#ifdef __cplusplus
extern "C" {
#endif
 
typedef struct fpga_bgr_s {
void *bgr_cpp;
} fpga_bgr_t;
 
 
void fpga_bgr_init( fpga_bgr_t *bgr, int socket, size_t size );
void fpga_bgr_delete( fpga_bgr_t *bgr );
 
void fpga_bgr_start( fpga_bgr_t *bgr);
ssize_t fpga_bgr_block_recv( fpga_bgr_t *bgr, void *buf, size_t size );
ssize_t fpga_bgr_poll();
void fpga_bgr_stop_interrupt_join( fpga_bgr_t *bgr);
 
// high level functions
int fpga_bgr_recv_charv( fpga_bgr_t *bgr, char *buf, size_t n );
int fpga_bgr_recv_shortv( fpga_bgr_t *bgr, int16_t *buf, size_t n );
int fpga_bgr_recv_intv( fpga_bgr_t *bgr, int32_t *buf, size_t n );
int fpga_bgr_recv_longv( fpga_bgr_t *bgr, int64_t *buf, size_t n );
int fpga_bgr_recv_floatv( fpga_bgr_t *bgr, float *buf, size_t n );
int fpga_bgr_recv_doublev( fpga_bgr_t *bgr, double *buf, size_t n );
 
#ifdef __cplusplus
}
#endif
 
 
 
#endif // BACKGROUND_READER_H
/pc_fpga_com/trunk/PC_FPGA_PLATFPORM/SOFTWARE/build.sh
0,0 → 1,2
gcc -std=c99 -Wall -O2 -c fpga_com.c
g++ -Wall -O2 -o testcase1 testcase1.cpp background_reader.cpp fpga_com.o -lboost_thread
/pc_fpga_com/trunk/PC_FPGA_PLATFPORM/SOFTWARE/fpga_com.c
0,0 → 1,370
/*
* Copyright (C) 2011 Simon A. Berger
*
* This program is free software; you may redistribute it and/or modify its
* under the terms of the GNU Lesser General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*/
 
 
#include <stdio.h>
 
#include <unistd.h>
#include <stdlib.h>
#include <string.h>
#include <assert.h>
 
#include "fpga_com.h"
#include <sys/socket.h>
#include <netinet/in.h>
#include <arpa/inet.h>
 
const size_t MAX_MTU = 64 * 1024;
 
static void die_perror( const char *call ) {
perror( call );
exit(-1);
}
 
 
void fpga_con_init( fpga_con_t *con, const void *daddr, int lport, int dport ) {
 
/*set up local socket address*/
memset( &con->l_sockaddr, 0, sizeof( con->l_sockaddr ));
con->l_sockaddr.sin_family = AF_INET;
con->l_sockaddr.sin_addr.s_addr = INADDR_ANY;
con->l_sockaddr.sin_port = htons(lport);
/*setup dest socket address*/
memset( &con->d_sockaddr, 0, sizeof( con->d_sockaddr ));
con->d_sockaddr.sin_family = AF_INET;
con->d_sockaddr.sin_addr.s_addr = inet_addr( daddr );
con->d_sockaddr.sin_port = htons(dport);
/* create my socket*/
con->s = socket( AF_INET, SOCK_DGRAM, IPPROTO_UDP );
if( con->s < 0 ) {
die_perror( "socket" );
}
/* bind it to local socket*/
int r = bind( con->s, (struct sockaddr *)&con->l_sockaddr, sizeof(con->l_sockaddr));
if( r < 0 ) {
die_perror( "bind" );
}
con->mtu = 1500;
}
 
size_t fpga_con_get_mtu( fpga_con_t *con ) {
return con->mtu;
}
 
void fpga_con_set_mtu( fpga_con_t *con, size_t mtu ) {
if( mtu > MAX_MTU ) {
printf( "fpga_con_set_mtu: mtu > MAX_MTU\n" );
exit(-1);
}
con->mtu = mtu;
}
 
 
ssize_t fpga_con_send( fpga_con_t *con, const void *buf, size_t len ) {
ssize_t rsend = sendto( con->s, buf, len, 0, (struct sockaddr*)&con->d_sockaddr, sizeof(con->d_sockaddr));
if( rsend < 0 ) {
die_perror( "sendto" );
}
return rsend;
}
 
 
/* send lut initialization packet sequence: rst, conf, empty*/
void fpga_con_send_init_packet( fpga_con_t *con ) {
uint8_t buf[4];
buf[0] = 255;
fpga_con_send( con, buf, 1);
buf[0] = 15;
fpga_con_send( con, buf, 1);
fpga_con_send( con, buf, 0);
}
 
/*blocking receive: this call will block until a packet is received*/
ssize_t fpga_con_block_recv( fpga_con_t *con, void *dbuf, size_t dsize ) {
ssize_t rrecv = recv( con->s, dbuf, dsize, 0 );
if( rrecv < 0 ) {
die_perror( "recv" );
}
return rrecv;
}
 
 
static __inline size_t mymin( size_t a, size_t b ) {
return a < b ? a : b;
}
 
//const static size_t MTU = 1500;
const static size_t PH_SIZE = 1;
 
 
// static __inline size_t pack( uint8_t *buf, uint8_t ht, size_t buf_size, void *src, size_t src_size ) {
// assert( src_size + PH_SIZR <= buf_size );
//
// buf[0] = ht;
// memcpy( buf + PH_SIZE, src, src_size );
//
// return src_size + PH_SIZE;
// }
 
// TODO; check how large the impact of doing the byte swappin on unaligned values really is
// there is no simple way around it (like in the receiving direction).
static __inline void swappy_16( void *dest, void *src, size_t n ) {
uint16_t *idest = (uint16_t*)dest;
uint16_t *isrc = (uint16_t*)src;
for( size_t i = 0; i < n / 2; i++ ) {
idest[i] = __bswap_16(isrc[i]);
}
}
 
static __inline void swappy_32( void *dest, void *src, size_t n ) {
uint32_t *idest = (uint32_t*)dest;
uint32_t *isrc = (uint32_t*)src;
for( size_t i = 0; i < n / 4; i++ ) {
idest[i] = __bswap_32(isrc[i]);
}
}
 
 
static __inline void swappy_64( void *dest, void *src, size_t n ) {
uint64_t *idest = (uint64_t*)dest;
uint64_t *isrc = (uint64_t*)src;
for( size_t i = 0; i < n / 8; i++ ) {
idest[i] = __bswap_64(isrc[i]);
}
}
 
#define BS_NONE (0)
#define BS_16 (1)
#define BS_32 (2)
#define BS_64 (3)
 
static __inline size_t pack_and_send( fpga_con_t *con, uint8_t *buf, size_t buf_size, uint8_t ht, void *src, size_t src_size, int swap ) {
const size_t pack_size = src_size + PH_SIZE;
assert( pack_size <= buf_size );
buf[0] = ht;
switch( swap ) {
case BS_NONE:
memcpy( buf + PH_SIZE, src, src_size );
break;
case BS_16:
swappy_16( buf + PH_SIZE, src, src_size );
break;
case BS_32:
swappy_32( buf + PH_SIZE, src, src_size );
break;
case BS_64:
swappy_64( buf + PH_SIZE, src, src_size );
break;
default:
assert(0);
}
fpga_con_send( con, buf, pack_size );
return src_size + PH_SIZE;
}
 
 
 
 
int fpga_con_send_charv( fpga_con_t *con, char *buf, size_t n ) {
const size_t blocksize = (con->mtu - PH_SIZE);
uint8_t sb[MAX_MTU];
size_t sent = 0;
while( sent < n ) {
const size_t to_copy = mymin( blocksize, n - sent );
pack_and_send( con, sb, con->mtu, FPC_CODE_CHAR, (void*) &buf[sent], to_copy, BS_NONE );
sent += to_copy;
}
return 1;
}
 
int fpga_con_send_shortv( fpga_con_t *con, int16_t *buf, size_t n ) {
const size_t TSIZE = sizeof( short );
const size_t blocksize = (con->mtu - PH_SIZE) / TSIZE;
uint8_t sb[MAX_MTU];
size_t sent = 0;
while( sent < n ) {
const size_t to_copy = mymin( blocksize, n - sent );
//fpga_con_send( con, (void*) &buf[sent], to_copy * TSIZE );
pack_and_send( con, sb, con->mtu, FPC_CODE_SHORT, (void*) &buf[sent], to_copy * TSIZE, BS_16 );
sent += to_copy;
}
return 1;
}
int fpga_con_send_intv( fpga_con_t *con, int32_t *buf, size_t n ) {
const size_t TSIZE = sizeof( int );
const size_t blocksize = (con->mtu - PH_SIZE) / TSIZE;
uint8_t sb[MAX_MTU];
size_t sent = 0;
while( sent < n ) {
const size_t to_copy = mymin( blocksize, n - sent );
// fpga_con_send( con, (void*) &buf[sent], to_copy * TSIZE );
pack_and_send( con, sb, con->mtu, FPC_CODE_INT, (void*) &buf[sent], to_copy * TSIZE, BS_32 );
sent += to_copy;
}
return 1;
}
 
 
int fpga_con_send_longv( fpga_con_t *con, int64_t *buf, size_t n ) {
const size_t TSIZE = sizeof( int64_t );
const size_t blocksize = (con->mtu - PH_SIZE) / TSIZE;
uint8_t sb[MAX_MTU];
size_t sent = 0;
while( sent < n ) {
const size_t to_copy = mymin( blocksize, n - sent );
// fpga_con_send( con, (void*) &buf[sent], to_copy * TSIZE );
pack_and_send( con, sb, con->mtu, FPC_CODE_LONG, (void*) &buf[sent], to_copy * TSIZE, BS_64 );
sent += to_copy;
}
return 1;
}
 
int fpga_con_send_floatv( fpga_con_t *con, float *buf, size_t n ) {
const size_t TSIZE = sizeof( int );
const size_t blocksize = (con->mtu - PH_SIZE) / TSIZE;
uint8_t sb[MAX_MTU];
size_t sent = 0;
while( sent < n ) {
const size_t to_copy = mymin( blocksize, n - sent );
// fpga_con_send( con, (void*) &buf[sent], to_copy * TSIZE );
pack_and_send( con, sb, con->mtu, FPC_CODE_FLOAT, (void*) &buf[sent], to_copy * TSIZE, BS_32 );
sent += to_copy;
}
return 1;
}
 
int fpga_con_send_doublev( fpga_con_t *con, double *buf, size_t n ) {
const size_t TSIZE = sizeof( double );
const size_t blocksize = (con->mtu - PH_SIZE) / TSIZE;
uint8_t sb[MAX_MTU];
size_t sent = 0;
while( sent < n ) {
const size_t to_copy = mymin( blocksize, n - sent );
// fpga_con_send( con, (void*) &buf[sent], to_copy * TSIZE );
pack_and_send( con, sb, con->mtu, FPC_CODE_DOUBLE, (void*) &buf[sent], to_copy * TSIZE, BS_64 );
sent += to_copy;
}
return 1;
}
 
static void fpga_con_rpack( fpga_con_t *con, int code, int size ) {
char buf[3] = { 120, 0, 0 };
buf[0] += code;
assert( size > 0 && size < 0xffff );
unsigned short ssize = size;
swappy_16( &buf[1], &ssize, 2);
fpga_con_send(con, buf, 3);
}
 
void fpga_con_rpack_char( fpga_con_t *con, int size ) {
fpga_con_rpack( con, FPC_CODE_CHAR, size );
}
void fpga_con_rpack_short( fpga_con_t *con, int size ) {
fpga_con_rpack( con, FPC_CODE_SHORT, size );
}
void fpga_con_rpack_int( fpga_con_t *con, int size ) {
fpga_con_rpack( con, FPC_CODE_INT, size);
}
void fpga_con_rpack_long( fpga_con_t *con, int size ) {
fpga_con_rpack( con, FPC_CODE_LONG, size);
}
 
void fpga_con_rpack_float( fpga_con_t *con, int size ) {
fpga_con_rpack( con, FPC_CODE_FLOAT, size );
}
void fpga_con_rpack_double( fpga_con_t *con, int size ) {
fpga_con_rpack( con, FPC_CODE_DOUBLE, size );
}
 
/pc_fpga_com/trunk/PC_FPGA_PLATFPORM/SOFTWARE/testcase1.cpp
0,0 → 1,195
/*
* Copyright (C) 2011 Simon A. Berger
*
* This program is free software; you may redistribute it and/or modify its
* under the terms of the GNU Lesser General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*/
 
#include <stdio.h>
 
#include <unistd.h>
#include <stdlib.h>
#include <string.h>
#include <cmath>
#include <iostream>
#include "fpga_com.h"
#include "background_reader.h"
 
int main() {
 
fpga_con_t fc;
fpga_con_init( &fc, "192.168.1.1", 21844, 21845 );
fpga_bgr_t bgr;
 
fpga_bgr_init( &bgr, fc.s, 1024 * 1024 * 10 );
fpga_bgr_start( &bgr );
fpga_con_send_init_packet( &fc );
bool do_char = !false;
bool do_short = !false;
bool do_int = true;
bool do_long = true;
bool do_float = true;
bool do_double = true;
const int N = 127;
if(do_char)
{
char test[N];
for( int i = 0; i < N; i++ ) {
test[i] = i;// + 'a';
}
 
fpga_con_send_charv( &fc, test, N);
char rec[N];
fpga_con_rpack_char(&fc,N);
fpga_bgr_recv_charv(&bgr, rec, N );
 
printf( "recv char: \n" );
for( int i = 0; i < N; i++ ) {
printf( " recv: %d %d\n", test[i], rec[i] );
}
}
if(do_short)
{
short test[N];
for( int i = 0; i < N; i++ ) {
test[i] = i;
}
 
fpga_con_send_shortv( &fc, test, N);
short rec[N];
fpga_con_rpack_short(&fc,N);
fpga_bgr_recv_shortv(&bgr, rec, N );
 
printf( "recv short: \n" );
for( int i = 0; i < N; i++ ) {
printf( " recv: %d %d\n", test[i], rec[i] );
 
}
}
if( do_int )
{
int test[N];
for( int i = 0; i < N; i++ ) {
test[i] = i;
}
 
fpga_con_send_intv( &fc, test, N);
int rec[N];
fpga_con_rpack_int(&fc,N);
fpga_bgr_recv_intv(&bgr, rec, N );
 
printf( "recv int: \n" );
for( int i = 0; i < N; i++ ) {
printf( " recv: %d %d\n", test[i], rec[i] );
}
}
if( do_long )
{
int64_t test[N];
for( int i = 0; i < N; i++ ) {
test[i] = i * int64_t(1024) * 1024 * 1024;
}
 
fpga_con_send_longv( &fc, test, N);
int64_t rec[N];
fpga_con_rpack_long(&fc,N);
fpga_bgr_recv_longv(&bgr, rec, N );
 
printf( "recv long: \n" );
for( int i = 0; i < N; i++ ) {
std::cout << " recv " << test[i] << " " << rec[i] << std::endl;
}
}
if( do_float )
{
float test[N];
for( int i = 0; i < N; i++ ) {
test[i] = i * 100000;
}
 
fpga_con_send_floatv( &fc, test, N);
float rec[N];
fpga_con_rpack_float(&fc,N);
fpga_bgr_recv_floatv(&bgr, rec, N );
 
printf( "recv float: \n" );
for( int i = 0; i < N; i++ ) {
printf( " recv: %f %f\n", test[i], rec[i] );
}
}
if(do_double)
{
double test[N];
for( int i = 0; i < N; i++ ) {
test[i] = i * 1000000;
}
 
fpga_con_send_doublev( &fc, test, N);
double rec[N];
fpga_con_rpack_double(&fc,N);
fpga_bgr_recv_doublev(&bgr, rec, N );
 
printf( "recv double: \n" );
for( int i = 0; i < N; i++ ) {
printf( " recv: %f %f\n", test[i], rec[i] );
}
}
fpga_bgr_stop_interrupt_join(&bgr);
fpga_bgr_delete(&bgr);
}
/pc_fpga_com/trunk/PC_FPGA_PLATFPORM/SOFTWARE/README
0,0 → 1,11
Use the build script (build.sh) to compile the simple test program (testcase1.cpp).
In this test case we send an array of 10 floats, after which the program waits
for a reply consisting of 10 float from the FPGA. The software interface depends
on a working installation of the boost libraries (www.boost.org) and a resonable
c++ compiler and STL implementation.
 
The example also serves as the official documentation for the software interface,
as far as the initilization of the fpga_con_t and fpga_bgr_t objects is concerned.
 
Visit https://github.com/sim82/c_tools/tree/master/fpga_com for the latest version
of this library.
/pc_fpga_com/trunk/PC_FPGA_PLATFPORM/HARDWARE/MATCH_CMD.vhd
0,0 → 1,111
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:01:28 01/18/2011
-- Design Name:
-- Module Name: MATCH_CMD - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity MATCH_CMD is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
sof : in STD_LOGIC;
vld_i : in STD_LOGIC;
val_i : in STD_LOGIC_VECTOR (7 downto 0);
cmd_to_match : in STD_LOGIC_VECTOR(7 downto 0);
cmd_match : out STD_LOGIC);
end MATCH_CMD;
 
architecture Behavioral of MATCH_CMD is
 
TYPE state is (rst_state,
idle_state,
header_state
);
signal current_st,next_st: state;
 
signal allow_match, match_s: std_logic;
signal allow_match_v, val_i_to_match: std_logic_vector(7 downto 0);
 
begin
 
process(clk)
begin
if (rst='1') then
current_st<= rst_state;
elsif (clk'event and clk='1') then
current_st <= next_st;
end if;
end process;
 
process(current_st,sof,vld_i)
begin
case current_st is
 
when rst_state =>
 
allow_match<='0';
next_st<=idle_state;
when idle_state =>
 
allow_match<='0';
if sof='0' then
next_st <= header_state;
else
next_st <= idle_state;
end if;
 
when header_state =>
if vld_i='1' then
allow_match<='1';
next_st <= rst_state;
else
allow_match<='0';
next_st <= header_state;
end if;
 
end case;
end process;
 
allow_match_v <=(others=>allow_match);
val_i_to_match <= val_i and allow_match_v;
 
process(clk)
begin
if clk'event and clk='1' then
if val_i_to_match = cmd_to_match then
cmd_match <='1';
else
cmd_match <='0';
end if;
end if;
end process;
 
end Behavioral;
 
/pc_fpga_com/trunk/PC_FPGA_PLATFPORM/HARDWARE/FSM_SEL_HEADER.vhd
0,0 → 1,98
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:59:05 05/03/2011
-- Design Name:
-- Module Name: FSM_SEL_HEADER - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity FSM_SEL_HEADER is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
usr_phase_en : in STD_LOGIC;
sel : out STD_LOGIC);
end FSM_SEL_HEADER;
 
architecture Behavioral of FSM_SEL_HEADER is
 
TYPE state is (rst_state,
idle_state,
header_state,
data_state
);
signal current_st,next_st: state;
 
begin
 
process(clk)
begin
if (rst='1') then
current_st<= rst_state;
elsif (clk'event and clk='1') then
current_st <= next_st;
end if;
end process;
 
process(current_st,usr_phase_en)
begin
case current_st is
 
when rst_state =>
 
sel<='0';
next_st<=idle_state;
when idle_state =>
 
sel<='0';
if usr_phase_en='1' then
next_st <= header_state;
else
next_st <= idle_state;
end if;
 
when header_state =>
 
sel<='1';
next_st <= data_state;
when data_state =>
 
sel<='0';
if usr_phase_en='1' then
next_st <= data_state;
else
next_st <= rst_state;
end if;
 
end case;
end process;
 
end Behavioral;
 
/pc_fpga_com/trunk/PC_FPGA_PLATFPORM/HARDWARE/PC_COM.vhd
0,0 → 1,283
-----------------------------------------------------------------------------------------
-- Copyright (C) 2010 Nikolaos Ch. Alachiotis --
-- --
-- Engineer: Nikolaos Ch. Alachiotis --
-- --
-- Contact: n.alachiotis@gmail.com --
-- --
-- Create Date: 04/03/2011 --
-- Project Name: PC-FPGA Communication Platform --
-- Module Name: PC_COM --
-- Target Devices: Virtex 5 FPGAs --
-- --
-----------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity PC_COM is
Port (
rst : in STD_LOGIC; -- active high
clk : in STD_LOGIC; -- emac clk
UDP_IP_Core_locked : out STD_LOGIC;
-- FPGA to PC
FPGA2PC_transmission_enable : in STD_LOGIC;
FPGA2PC_transmission_type : in STD_LOGIC_VECTOR(2 downto 0);
FPGA2PC_transmission_length : in STD_LOGIC_VECTOR(15 downto 0);
FPGA2PC_transmission_read_address : out STD_LOGIC_VECTOR(31 downto 0);
FPGA2PC_transmission_bus8 : in STD_LOGIC_VECTOR (7 downto 0);
FPGA2PC_transmission_bus16 : in STD_LOGIC_VECTOR (15 downto 0);
FPGA2PC_transmission_bus32 : in STD_LOGIC_VECTOR (31 downto 0);
FPGA2PC_transmission_bus64 : in STD_LOGIC_VECTOR (63 downto 0);
FPGA2PC_transmission_over : out STD_LOGIC;
-- PC to FPGA
PC2FPGA_tranmission_start_of_data : out STD_LOGIC;
PC2FPGA_tranmission_end_of_data : out STD_LOGIC;
PC2FPGA_tranmission_valid_data : out STD_LOGIC;
PC2FPGA_transmission_type : out STD_LOGIC_VECTOR(2 downto 0);
PC2FPGA_transmission_bus8 : out STD_LOGIC_VECTOR(7 downto 0);
PC2FPGA_transmission_bus16 : out STD_LOGIC_VECTOR(15 downto 0);
PC2FPGA_transmission_bus32 : out STD_LOGIC_VECTOR(31 downto 0);
PC2FPGA_transmission_bus64 : out STD_LOGIC_VECTOR(63 downto 0);
-- TX INTERFACE
tx_sof : out STD_LOGIC;
tx_eof : out STD_LOGIC;
tx_src_rdy : out STD_LOGIC;
tx_dst_rdy : in STD_LOGIC;
tx_data : out STD_LOGIC_VECTOR(7 downto 0);
-- RX INTERFACE
rx_sof : in STD_LOGIC;
rx_eof : in STD_LOGIC;
rx_src_rdy : in STD_LOGIC;
rx_dst_rdy : out STD_LOGIC;
rx_data : in STD_LOGIC_VECTOR(7 downto 0)
);
end PC_COM;
 
architecture Behavioral of PC_COM is
 
component UDP_IP_Core is
Port ( rst : in STD_LOGIC;
clk_125MHz : in STD_LOGIC;
-- Transmit signals
transmit_start_enable : in STD_LOGIC;
transmit_data_length : in STD_LOGIC_VECTOR (15 downto 0);
usr_data_trans_phase_on : out STD_LOGIC;
transmit_data_input_bus : in STD_LOGIC_VECTOR (7 downto 0);
start_of_frame_O : out STD_LOGIC;
end_of_frame_O : out STD_LOGIC;
source_ready : out STD_LOGIC;
transmit_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0);
--Receive Signals
rx_sof : in STD_LOGIC;
rx_eof : in STD_LOGIC;
input_bus : in STD_LOGIC_VECTOR(7 downto 0);
valid_out_usr_data : out STD_LOGIC;
usr_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0);
locked : out STD_LOGIC
);
end component;
 
component PC2FPGA is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
locked : in STD_LOGIC;
rx_sof : in STD_LOGIC;
rx_eof : in STD_LOGIC;
vld_i : in STD_LOGIC;
val_i : in STD_LOGIC_VECTOR(7 downto 0);
sod_o : out STD_LOGIC;
eod_o : out STD_LOGIC;
type_o : out STD_LOGIC_VECTOR(2 downto 0); -- 000: no transmission
-- 001: receiving characters
-- 010: receiving short integers
-- 011: receiving integers
-- 100: receiving floats
-- 101: receiving doubles
vld_o : out STD_LOGIC;
 
val_o_char : out STD_LOGIC_VECTOR(7 downto 0);
val_o_short : out STD_LOGIC_VECTOR(15 downto 0);
val_o_int_float : out STD_LOGIC_VECTOR(31 downto 0);
val_o_long_double : out STD_LOGIC_VECTOR(63 downto 0)
);
end component;
 
component FPGA2PC is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
locked : in STD_LOGIC;
trans_en : in STD_LOGIC;
d_type : in STD_LOGIC_VECTOR (2 downto 0);
d_len : in STD_LOGIC_VECTOR (15 downto 0);
rd_addr : out STD_LOGIC_VECTOR (31 downto 0);
data_in_8 : in STD_LOGIC_VECTOR (7 downto 0); -- type 001
data_in_16 : in STD_LOGIC_VECTOR (15 downto 0); -- type 010
data_in_32 : in STD_LOGIC_VECTOR (31 downto 0); -- type 011 or 100
data_in_64 : in STD_LOGIC_VECTOR (63 downto 0); -- type 101
start_trans : out STD_LOGIC;
trans_length : out STD_LOGIC_VECTOR(15 downto 0);
usr_data_phase_on : in STD_LOGIC;
usr_data_to_trasmit : out STD_LOGIC_VECTOR(7 downto 0);
tx_eof_in: in STD_LOGIC;
trans_ov : out STD_LOGIC);
end component;
 
component MATCH_CMD is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
sof : in STD_LOGIC;
vld_i : in STD_LOGIC;
val_i : in STD_LOGIC_VECTOR (7 downto 0);
cmd_to_match : in STD_LOGIC_VECTOR(7 downto 0);
cmd_match : out STD_LOGIC);
end component;
 
signal locked: std_logic;
signal vld_in_usr_data: std_logic;
signal val_in_usr_data,val_in_usr_data_reg: std_logic_vector(7 downto 0);
signal loc_st_trans: std_logic;
signal loc_le_trans: std_logic_vector(15 downto 0);
signal usr_out_type_t: std_logic_vector(1 downto 0);
signal usr_o_data_en: std_logic;
signal usr_o_data, usr_o_data_reg1: std_logic_Vector(7 downto 0);
signal test_en: std_logic;
signal tx_eof_t, sel_op: std_logic;
signal selected_data, sel_def, sel_stat, status_next: std_logic_vector(7 downto 0);
signal selected_length: std_logic_Vector(15 downto 0);
signal selected_start,status_enable_r, status_enable_t: std_logic;
signal start_transmission, rreq_en, loc_trans_en, rreq_en_reg: std_logic;
signal transmission_data, cmd_to_match_rreq, val_in_usr_data_reg_2: std_logic_Vector(7 downto 0);
signal transmission_length, tmplength: std_logic_vector(15 downto 0);
signal loc_trans_type: std_logic_Vector(2 downto 0);
signal loc_trans_length: std_logic_vector(15 downto 0);
 
begin
 
cmd_to_match_rreq(7 downto 3) <= val_in_usr_data(7 downto 3);
cmd_to_match_rreq(2 downto 0) <= "000";
 
MATCH_RREQ_CODE: MATCH_CMD Port Map
( rst => rst,
clk => clk,
sof => rx_sof,
vld_i => vld_in_usr_data,
val_i => cmd_to_match_rreq,
cmd_to_match => "01111000",
cmd_match => rreq_en
);
 
process(clk)
begin
if clk'event and clk='1' then
val_in_usr_data_reg <= val_in_usr_data;
val_in_usr_data_reg_2 <= val_in_usr_data_reg;
rreq_en_reg <= rreq_en;
end if;
end process;
 
tmplength(15 downto 8) <= val_in_usr_data_reg;
tmplength(7 downto 0) <= val_in_usr_data;
 
loc_trans_en <= FPGA2PC_transmission_enable or rreq_en_reg;
loc_trans_length <= FPGA2PC_transmission_length or tmplength;
loc_trans_type <= FPGA2PC_transmission_type or val_in_usr_data_reg_2(2 downto 0);
 
 
UDP_IP_CORE_INST: UDP_IP_Core Port Map
(
rst => rst,
clk_125MHz => clk,
transmit_start_enable => start_transmission,
transmit_data_length => transmission_length,
usr_data_trans_phase_on => usr_o_data_en,
transmit_data_input_bus => transmission_data,
start_of_frame_O => tx_sof,
end_of_frame_O => tx_eof_t,
source_ready => tx_src_rdy,
transmit_data_output_bus =>tx_data,
rx_sof => rx_sof,
rx_eof => rx_eof,
input_bus => rx_data,
valid_out_usr_data => vld_in_usr_data,
usr_data_output_bus => val_in_usr_data,
locked => locked
);
 
tx_eof <=tx_eof_t;
 
UDP_IP_Core_locked <= locked;
 
rx_dst_rdy <= tx_dst_rdy;
 
PC2FPGA_C: PC2FPGA Port Map
(
rst => rst,
clk => clk,
locked => locked,
rx_sof => rx_sof,
rx_eof => rx_eof,
vld_i => vld_in_usr_data,
val_i => val_in_usr_data,
sod_o => PC2FPGA_tranmission_start_of_data,
eod_o => PC2FPGA_tranmission_end_of_data,
type_o => PC2FPGA_transmission_type,
vld_o => PC2FPGA_tranmission_valid_data,
val_o_char => PC2FPGA_transmission_bus8,
val_o_short => PC2FPGA_transmission_bus16,
val_o_int_float => PC2FPGA_transmission_bus32,
val_o_long_double => PC2FPGA_transmission_bus64
);
 
FPGA2PC_C: FPGA2PC Port Map
(
rst => rst,
clk => clk,
locked => locked,
trans_en => loc_trans_en,
d_type => loc_trans_type,
d_len => loc_trans_length,
rd_addr => FPGA2PC_transmission_read_address,
data_in_8 => FPGA2PC_transmission_bus8,
data_in_16 => FPGA2PC_transmission_bus16,
data_in_32 => FPGA2PC_transmission_bus32,
data_in_64 => FPGA2PC_transmission_bus64,
start_trans => start_transmission,
trans_length => transmission_length,
usr_data_phase_on => usr_o_data_en,
usr_data_to_trasmit => transmission_data,
tx_eof_in => tx_eof_t,
trans_ov => FPGA2PC_transmission_over
);
 
end Behavioral;
 
/pc_fpga_com/trunk/PC_FPGA_PLATFPORM/HARDWARE/FPGA2PC.vhd
0,0 → 1,235
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:19:53 05/03/2011
-- Design Name:
-- Module Name: FPGA2PC - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity FPGA2PC is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
locked : in STD_LOGIC;
trans_en : in STD_LOGIC;
d_type : in STD_LOGIC_VECTOR (2 downto 0);
d_len : in STD_LOGIC_VECTOR (15 downto 0);
rd_addr : out STD_LOGIC_VECTOR (31 downto 0);
data_in_8 : in STD_LOGIC_VECTOR (7 downto 0); -- type 001
data_in_16 : in STD_LOGIC_VECTOR (15 downto 0); -- type 010
data_in_32 : in STD_LOGIC_VECTOR (31 downto 0); -- type 011 or 100
data_in_64 : in STD_LOGIC_VECTOR (63 downto 0); -- type 101
start_trans : out STD_LOGIC;
trans_length : out STD_LOGIC_VECTOR(15 downto 0);
usr_data_phase_on : in STD_LOGIC;
usr_data_to_trasmit : out STD_LOGIC_VECTOR(7 downto 0);
tx_eof_in: in STD_LOGIC;
trans_ov : out STD_LOGIC);
end FPGA2PC;
 
architecture Behavioral of FPGA2PC is
 
component D_TYPE_LEN_CNTRL is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
locked : in STD_LOGIC;
trans_en : in STD_LOGIC;
d_type : in STD_LOGIC_VECTOR (2 downto 0);
d_len : in STD_LOGIC_VECTOR (15 downto 0);
d_type_byte : out STD_LOGIC_VECTOR (7 downto 0);
d_length_out : out STD_LOGIC_VECTOR (15 downto 0));
end component;
 
component FSM_SEL_HEADER is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
usr_phase_en : in STD_LOGIC;
sel : out STD_LOGIC);
end component;
 
signal header_byte, usr_data_to_trasmit_t, usr_data_to_trasmit_tt, sel_char_v, sel_rest_v, selected_usr_data_to_transmit: std_logic_vector(7 downto 0);
signal packet_size: std_logic_Vector(15 downto 0);
signal rst_count, en_count, start_trans_tmp,
sel_header, rst_addrgen, en_addrgen,
en_addrgen_t, sel_char, sel_rest : std_logic;
signal counter, counter_r, d_type_loc: std_logic_Vector(2 downto 0);
signal rdaddr_t: std_logic_vector(31 downto 0);
 
component DATA_OUT_MUX is
Port ( status : in STD_LOGIC_VECTOR (2 downto 0);
addr : in STD_LOGIC_VECTOR (2 downto 0);
usr_d_on: in STD_LOGIC;
data_8 : in STD_LOGIC_VECTOR (7 downto 0);
data_16 : in STD_LOGIC_VECTOR (15 downto 0);
data_32 : in STD_LOGIC_VECTOR (31 downto 0);
data_64 : in STD_LOGIC_VECTOR (63 downto 0);
data_out : out STD_LOGIC_VECTOR (7 downto 0));
end component;
 
signal select_header_v, select_data_v : std_logic_Vector(7 downto 0);
 
begin
 
start_trans_tmp <= trans_en and locked;
 
process(clk)
begin
if clk'event and clk='1' then
usr_data_to_trasmit_tt <= usr_data_to_trasmit_t;
start_trans <= start_trans_tmp;
counter_r <= counter;
end if;
end process;
 
D_TYPE_LEN_CNTRL_C: D_TYPE_LEN_CNTRL Port Map
( rst => rst,
clk => clk,
locked => locked,
trans_en => trans_en,
d_type => d_type,
d_len => d_len,
d_type_byte => header_byte,
d_length_out => packet_size
);
 
trans_length <= packet_size;
 
en_count <= usr_data_phase_on;
 
rst_count <= rst or start_trans_tmp;
 
process(clk)
begin
if rst_count='1' then
counter <= "000";
else
if clk'event and clk='1' then
if en_count='1' then
counter <= counter + "001";
end if;
end if;
end if;
end process;
 
 
process(clk)
begin
if clk'event and clk='1' then
if header_byte(2 downto 0)="001" then -- char
en_addrgen_t <= usr_data_phase_on;
elsif header_byte(2 downto 0)="010" then -- short
if usr_data_phase_on='1' then
if counter="000" or counter="010" or counter="100" or counter="110" then
en_addrgen_t <= '1';
else
en_addrgen_t <= '0';
end if;
else
en_addrgen_t <= '0';
end if;
elsif header_byte(2 downto 0)="011" or header_byte(2 downto 0)="100" then -- int/float
if usr_data_phase_on='1' then
if counter="010" or counter="110" then
en_addrgen_t <= '1';
else
en_addrgen_t <= '0';
end if;
else
en_addrgen_t <= '0';
end if;
else -- d_type="00": double
if usr_data_phase_on='1' then
if counter="110" then
en_addrgen_t <= '1';
else
en_addrgen_t <= '0';
end if;
else
en_addrgen_t <= '0';
end if;
end if;
end if;
end process;
 
sel_char <= (not header_byte(2)) and (not header_byte(1)) and (header_byte(0));
sel_rest <= not sel_char;
 
sel_char_v <= (others=> sel_char);
sel_rest_v <= (others=> sel_rest);
 
 
en_addrgen <= (sel_char and usr_data_phase_on) or (sel_rest and en_addrgen_t);
 
rst_addrgen <= rst or start_trans_tmp;
 
process(clk)
begin
if rst_addrgen='1' then
rdaddr_t <= (others=>'0');
else
if clk'event and clk='1' then
if en_addrgen='1' then
rdaddr_t <= rdaddr_t + "00000000000000000000000000000001";
end if;
end if;
end if;
end process;
 
rd_addr<=rdaddr_t;
 
 
FSM_SEL_HEADER_C: FSM_SEL_HEADER Port Map
( rst => rst,
clk => clk,
usr_phase_en => usr_data_phase_on,
sel => sel_header
);
 
select_header_v <= (others=> sel_header);
select_data_v <= (others=> not sel_header);
 
 
DATA_OUT_MUX_C: DATA_OUT_MUX Port Map
( status => header_byte(2 downto 0),
addr => counter_r,
usr_d_on => usr_data_phase_on,
data_8 => data_in_8,
data_16 => data_in_16,
data_32 => data_in_32,
data_64 => data_in_64,
data_out => usr_data_to_trasmit_t
);
 
usr_data_to_trasmit <= (select_header_v and header_byte) or (select_data_v and usr_data_to_trasmit_tt);
 
trans_ov <= not tx_eof_in;
 
end Behavioral;
 
/pc_fpga_com/trunk/PC_FPGA_PLATFPORM/HARDWARE/PC2FPGA.vhd
0,0 → 1,317
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:29:11 03/02/2011
-- Design Name:
-- Module Name: PC2FPGA - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity PC2FPGA is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
locked : in STD_LOGIC;
rx_sof : in STD_LOGIC;
rx_eof : in STD_LOGIC;
vld_i : in STD_LOGIC;
val_i : in STD_LOGIC_VECTOR(7 downto 0);
sod_o : out STD_LOGIC;
eod_o : out STD_LOGIC;
type_o : out STD_LOGIC_VECTOR(2 downto 0); -- 000: no transmission
-- 001: receiving characters
-- 010: receiving short integers
-- 011: receiving integers
-- 100: receiving floats
-- 101: receiving doubles
vld_o : out STD_LOGIC;
 
val_o_char : out STD_LOGIC_VECTOR(7 downto 0);
val_o_short : out STD_LOGIC_VECTOR(15 downto 0);
val_o_int_float : out STD_LOGIC_VECTOR(31 downto 0);
val_o_long_double : out STD_LOGIC_VECTOR(63 downto 0)
);
end PC2FPGA;
 
architecture Behavioral of PC2FPGA is
 
component MATCH_CMD is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
sof : in STD_LOGIC;
vld_i : in STD_LOGIC;
val_i : in STD_LOGIC_VECTOR (7 downto 0);
cmd_to_match : in STD_LOGIC_VECTOR(7 downto 0);
cmd_match : out STD_LOGIC);
end component;
 
component MODE_SEL_REGISTER is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
rx_sof : in STD_LOGIC;
rx_eof : in STD_LOGIC;
en : in STD_LOGIC;
sel : out STD_LOGIC);
end component;
 
signal pack_is_chars, pack_is_shorts, pack_is_ints, pack_is_floats, pack_is_longs, pack_is_doubles,
select_chars, select_shorts, select_ints, select_floats, select_longs, select_doubles,
vld_o_t, en_counter, en_counter_r, sod_o_t, vld_i_r, set_eod, rx_eof_reg: std_logic;
signal select_chars_v, select_shorts_v, select_ints_v, select_floats_v, select_ints_floats_v, select_longs_v, select_doubles_v, select_longs_doubles_v,
type_o_t, type_o_t_r, match_t_1, match_t_2, match_t_3, match_t_4, counter_value: std_logic_vector(2 downto 0);
 
signal sel_val_o_chars_v: std_logic_vector(7 downto 0);
signal short_res, sel_val_o_shorts_v: std_logic_vector(15 downto 0);
signal int_float_res, sel_val_o_ints_floats_v: std_logic_vector(31 downto 0);
signal long_double_res, sel_val_o_longs_doubles_v: std_logic_vector(63 downto 0);
 
signal val_i_r2, val_i_r3, val_i_r4, val_i_r5, val_i_r6, val_i_r7, val_i_r8: std_logic_vector(7 downto 0);
signal user_length, user_counter: std_logic_vector(15 downto 0);
 
begin
 
sod_o_t <= (pack_is_chars or pack_is_shorts or pack_is_ints or pack_is_floats or pack_is_longs or pack_is_doubles) and locked;
 
sod_o <= sod_o_t;
 
eod_o <= (not rx_eof_reg) and locked;
 
MATCH_CHAR: MATCH_CMD Port Map
( rst => rst,
clk => clk,
sof => rx_sof,
vld_i => vld_i,
val_i => val_i,
cmd_to_match => "00000001",
cmd_match => pack_is_chars
);
 
MATCH_SHORT: MATCH_CMD Port Map
( rst => rst,
clk => clk,
sof => rx_sof,
vld_i => vld_i,
val_i => val_i,
cmd_to_match => "00000010",
cmd_match => pack_is_shorts
);
 
MATCH_INT: MATCH_CMD Port Map
( rst => rst,
clk => clk,
sof => rx_sof,
vld_i => vld_i,
val_i => val_i,
cmd_to_match => "00000011",
cmd_match => pack_is_ints
);
 
MATCH_FLOAT: MATCH_CMD Port Map
( rst => rst,
clk => clk,
sof => rx_sof,
vld_i => vld_i,
val_i => val_i,
cmd_to_match => "00000100",
cmd_match => pack_is_floats
);
 
MATCH_LONG: MATCH_CMD Port Map
( rst => rst,
clk => clk,
sof => rx_sof,
vld_i => vld_i,
val_i => val_i,
cmd_to_match => "00000101",
cmd_match => pack_is_longs
);
 
MATCH_DOUBLE: MATCH_CMD Port Map
( rst => rst,
clk => clk,
sof => rx_sof,
vld_i => vld_i,
val_i => val_i,
cmd_to_match => "00000110",
cmd_match => pack_is_doubles
);
 
SELECT_CHAR: MODE_SEL_REGISTER Port map
( rst => rst,
clk => clk,
rx_sof => rx_sof,
rx_eof => rx_eof_reg,
en => pack_is_chars,
sel => select_chars
);
 
SELECT_SHORT: MODE_SEL_REGISTER Port map
( rst => rst,
clk => clk,
rx_sof => rx_sof,
rx_eof => rx_eof_reg,
en => pack_is_shorts,
sel => select_shorts
);
 
SELECT_INT: MODE_SEL_REGISTER Port map
( rst => rst,
clk => clk,
rx_sof => rx_sof,
rx_eof => rx_eof_reg,
en => pack_is_ints,
sel => select_ints
);
 
SELECT_FLOAT: MODE_SEL_REGISTER Port map
( rst => rst,
clk => clk,
rx_sof => rx_sof,
rx_eof => rx_eof_reg,
en => pack_is_floats,
sel => select_floats
);
 
SELECT_LONG: MODE_SEL_REGISTER Port map
( rst => rst,
clk => clk,
rx_sof => rx_sof,
rx_eof => rx_eof_reg,
en => pack_is_longs,
sel => select_longs
);
 
SELECT_DOUBLE: MODE_SEL_REGISTER Port map
( rst => rst,
clk => clk,
rx_sof => rx_sof,
rx_eof => rx_eof_reg,
en => pack_is_doubles,
sel => select_doubles
);
 
select_chars_v <= (others=> select_chars and locked);
select_shorts_v <= (others=> select_shorts and locked);
select_ints_v <= (others=> select_ints and locked);
select_floats_v <= (others=> select_floats and locked);
select_ints_floats_v <= (others=> (select_ints or select_floats) and locked);
select_longs_v <= (others=> select_longs and locked);
select_doubles_v <= (others=> select_doubles and locked);
select_longs_doubles_v <= (others=> (select_longs or select_doubles) and locked);
 
 
sel_val_o_chars_v <= (others=> select_chars and locked);
sel_val_o_shorts_v <= (others=> select_shorts and locked);
sel_val_o_ints_floats_v <= (others=> (select_ints or select_floats) and locked);
sel_val_o_longs_doubles_v <= (others=> (select_longs or select_doubles) and locked);
 
type_o_t <= (select_chars_v and "001") or
(select_shorts_v and "010") or
(select_ints_v and "011") or
(select_floats_v and "100") or
(select_longs_v and "101") or
(select_doubles_v and "110") ;
 
type_o <= type_o_t or type_o_t_r;
 
en_counter <= select_chars or
select_shorts or
select_ints or
select_floats or
select_longs or
select_doubles;
process(clk)
begin
if clk'event and clk='1' then
rx_eof_reg <= rx_eof;
if en_counter='0' then
counter_value <= "000";
else
counter_value <= counter_value + "001";
end if;
end if;
end process;
 
match_t_1 <= (select_shorts_v and "000") or (select_ints_floats_v and "010") or (select_longs_doubles_v and "110");
match_t_2 <= (select_shorts_v and "010") or (select_ints_floats_v and "010") or (select_longs_doubles_v and "110");
match_t_3 <= (select_shorts_v and "100") or (select_ints_floats_v and "110") or (select_longs_doubles_v and "110");
match_t_4 <= (select_shorts_v and "110") or (select_ints_floats_v and "110") or (select_longs_doubles_v and "110");
 
process(clk)
begin
if clk'event and clk='1' then
en_counter_r <= en_counter;
type_o_t_r <= type_o_t;
if counter_value = match_t_1 or counter_value = match_t_2 or counter_value = match_t_3 or counter_value = match_t_4 then
vld_o_t <= '1';
else
vld_o_t <= '0';
end if;
end if;
end process;
 
process(clk)
begin
if clk'event and clk='1' then
val_i_r2 <= val_i;
val_i_r3 <= val_i_r2;
val_i_r4 <= val_i_r3;
val_i_r5 <= val_i_r4;
val_i_r6 <= val_i_r5;
val_i_r7 <= val_i_r6;
val_i_r8 <= val_i_r7;
end if;
end process;
 
short_res(15 downto 8) <= val_i_r2;
short_res(7 downto 0) <= val_i;
 
int_float_res(31 downto 24) <= val_i_r4;
int_float_res(23 downto 16) <= val_i_r3;
int_float_res(15 downto 0) <= short_res;
 
long_double_res(63 downto 56) <= val_i_r8;
long_double_res(55 downto 48) <= val_i_r7;
long_double_res(47 downto 40) <= val_i_r6;
long_double_res(39 downto 32) <= val_i_r5;
long_double_res(31 downto 0) <= int_float_res;
 
process(clk)
begin
if clk'event and clk='1' then
vld_o <= (select_chars or ((select_shorts or select_ints or select_floats or select_longs or select_doubles) and vld_o_t and en_counter_r)) and locked;
val_o_char <= val_i and sel_val_o_chars_v;
val_o_short <= short_res and sel_val_o_shorts_v;
val_o_int_float <= int_float_res and sel_val_o_ints_floats_v;
val_o_long_double <= long_double_res and sel_val_o_longs_doubles_v;
end if;
end process;
 
end Behavioral;
 
/pc_fpga_com/trunk/PC_FPGA_PLATFPORM/HARDWARE/D_TYPE_LEN_CNTRL.vhd
0,0 → 1,92
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:37:32 05/03/2011
-- Design Name:
-- Module Name: D_TYPE_LEN_CNTRL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity D_TYPE_LEN_CNTRL is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
locked : in STD_LOGIC;
trans_en : in STD_LOGIC;
d_type : in STD_LOGIC_VECTOR (2 downto 0);
d_len : in STD_LOGIC_VECTOR (15 downto 0);
d_type_byte : out STD_LOGIC_VECTOR (7 downto 0);
d_length_out : out STD_LOGIC_VECTOR (15 downto 0));
end D_TYPE_LEN_CNTRL;
 
architecture Behavioral of D_TYPE_LEN_CNTRL is
 
begin
 
process(clk)
begin
if rst='1' then
d_type_byte <= "00000000";
d_length_out <= "0000000000000000";
else
if clk'event and clk='1' then
if locked='1' then
if trans_en = '1' then
if d_type="001" then
d_type_byte(2 downto 0) <= d_type;
d_length_out <= d_len+ "0000000000000001";
elsif d_type="010" then
d_type_byte(2 downto 0) <= d_type;
d_length_out(15 downto 1) <= d_len(14 downto 0);
d_length_out(0)<='1';
elsif d_type="011" then
d_type_byte(2 downto 0) <= d_type;
d_length_out(15 downto 2) <= d_len(13 downto 0);
d_length_out(1 downto 0)<="01";
elsif d_type="100" then
d_type_byte(2 downto 0) <= d_type;
d_length_out(15 downto 2) <= d_len(13 downto 0);
d_length_out(1 downto 0)<="01";
elsif d_type="101" then
d_type_byte(2 downto 0) <= d_type;
d_length_out(15 downto 3) <= d_len(12 downto 0);
d_length_out(2 downto 0)<="001";
elsif d_type="110" then
d_type_byte(2 downto 0) <= d_type;
d_length_out(15 downto 3) <= d_len(12 downto 0);
d_length_out(2 downto 0)<="001";
else
d_type_byte <= "00000000";
d_length_out <= "0000000000000001";
end if;
end if;
else
d_type_byte <= "00000000";
d_length_out <= "0000000000000001";
end if;
end if;
end if;
end process;
 
 
end Behavioral;
 
/pc_fpga_com/trunk/PC_FPGA_PLATFPORM/HARDWARE/DATA_OUT_MUX.vhd
0,0 → 1,133
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:25:55 03/21/2011
-- Design Name:
-- Module Name: DATA_OUT_MUX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity DATA_OUT_MUX is
Port ( status : in STD_LOGIC_VECTOR (2 downto 0);
addr : in STD_LOGIC_VECTOR (2 downto 0);
usr_d_on: in STD_LOGIC;
data_8 : in STD_LOGIC_VECTOR (7 downto 0);
data_16 : in STD_LOGIC_VECTOR (15 downto 0);
data_32 : in STD_LOGIC_VECTOR (31 downto 0);
data_64 : in STD_LOGIC_VECTOR (63 downto 0);
data_out : out STD_LOGIC_VECTOR (7 downto 0));
end DATA_OUT_MUX;
 
architecture Behavioral of DATA_OUT_MUX is
 
signal sel_char, sel_short, sel_int, sel_float, sel_long, sel_double: std_logic;
signal sel_char_v, sel_short_v, sel_int_v, sel_double_v: std_logic_vector(7 downto 0);
signal char_data, short_data, int_data, double_data: std_logic_vector(7 downto 0);
signal sel_shortA, sel_shortB: std_logic;
signal sel_intA, sel_intB, sel_intC, sel_intD: std_logic;
signal sel_doubleA_v, sel_doubleB_v, sel_doubleC_v, sel_doubleD_v,
sel_doubleE_v, sel_doubleF_v, sel_doubleG_v, sel_doubleH_v: std_logic_vector(7 downto 0);
signal sel_shortA_v, sel_shortB_v: std_logic_vector(7 downto 0);
signal sel_intA_v, sel_intB_v, sel_intC_v, sel_intD_v: std_logic_vector(7 downto 0);
signal sel1, sel2, sel3, sel4, sel5, sel6, sel7, sel8: std_logic;
 
begin
 
sel_char <= (not status(2)) and (not status(1)) and ( status(0));
sel_short <= (not status(2)) and ( status(1)) and (not status(0));
sel_int <= (not status(2)) and ( status(1)) and ( status(0));
sel_float <= ( status(2)) and (not status(1)) and (not status(0));
sel_long <= ( status(2)) and (not status(1)) and ( status(0));
sel_double <= ( status(2)) and ( status(1)) and (not status(0));
 
sel_char_v <= (others=> sel_char);
sel_short_v <= (others=> sel_short);
sel_int_v <= (others=> sel_int or sel_float);
sel_double_v <= (others=> sel_long or sel_double);
 
char_data <= data_8;
 
 
sel1 <= (not addr(2)) and (not addr(1)) and (not addr(0));
sel2 <= (not addr(2)) and (not addr(1)) and ( addr(0));
sel3 <= (not addr(2)) and ( addr(1)) and (not addr(0));
sel4 <= (not addr(2)) and ( addr(1)) and ( addr(0));
sel5 <= ( addr(2)) and (not addr(1)) and (not addr(0));
sel6 <= ( addr(2)) and (not addr(1)) and ( addr(0));
sel7 <= ( addr(2)) and ( addr(1)) and (not addr(0));
sel8 <= ( addr(2)) and ( addr(1)) and ( addr(0));
 
 
sel_shortA <= sel1 or sel3 or sel5 or sel7;
sel_shortB <= sel2 or sel4 or sel6 or sel8;
 
sel_shortA_v <=(others=> sel_shortA);
sel_shortB_v <=(others=> sel_shortB);
 
short_data <= (sel_shortA_v and data_16(15 downto 8)) or ((sel_shortB_v and data_16(7 downto 0)));
 
 
 
sel_intA <= sel1 or sel5;
sel_intB <= sel2 or sel6;
sel_intC <= sel3 or sel7;
sel_intD <= sel4 or sel8;
 
sel_intA_v <= (others=> sel_intA);
sel_intB_v <= (others=> sel_intB);
sel_intC_v <= (others=> sel_intC);
sel_intD_v <= (others=> sel_intD);
 
 
int_data <= (sel_intA_v and data_32(31 downto 24)) or
(sel_intB_v and data_32(23 downto 16)) or
(sel_intC_v and data_32(15 downto 8)) or
(sel_intD_v and data_32(7 downto 0)) ;
sel_doubleA_v <= (others=> sel1);
sel_doubleB_v <= (others=> sel2);
sel_doubleC_v <= (others=> sel3);
sel_doubleD_v <= (others=> sel4);
sel_doubleE_v <= (others=> sel5);
sel_doubleF_v <= (others=> sel6);
sel_doubleG_v <= (others=> sel7);
sel_doubleH_v <= (others=> sel8);
 
double_data <= (sel_doubleA_v and data_64(63 downto 56)) or
(sel_doubleB_v and data_64(55 downto 48)) or
(sel_doubleC_v and data_64(47 downto 40)) or
(sel_doubleD_v and data_64(39 downto 32)) or
(sel_doubleE_v and data_64(31 downto 24)) or
(sel_doubleF_v and data_64(23 downto 16)) or
(sel_doubleG_v and data_64(15 downto 8)) or
(sel_doubleH_v and data_64(7 downto 0)) ;
 
data_out <= (sel_char_v and char_data) or
(sel_short_v and short_data) or
(sel_int_v and int_data) or
(sel_double_v and double_data) ;
 
end Behavioral;
 
/pc_fpga_com/trunk/PC_FPGA_PLATFPORM/HARDWARE/MODE_SEL_REGISTER.vhd
0,0 → 1,64
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:38:55 03/02/2011
-- Design Name:
-- Module Name: MODE_SEL_REGISTER - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity MODE_SEL_REGISTER is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
rx_sof : in STD_LOGIC;
rx_eof : in STD_LOGIC;
en : in STD_LOGIC;
sel : out STD_LOGIC);
end MODE_SEL_REGISTER;
 
architecture Behavioral of MODE_SEL_REGISTER is
 
signal sel_t: std_logic;
 
begin
 
process(clk)
begin
 
if rst='1' or rx_sof='0' or rx_eof='0' then
sel_t <= '0';
else
if clk'event and clk='1' then
if en='1' then
sel_t <= '1';
else
sel_t <= sel_t;
end if;
end if;
end if;
end process;
 
sel <= (en or sel_t) and rx_eof;
 
end Behavioral;
 
/pc_fpga_com/trunk/PAPER/pc_fpga_com.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/pc_fpga_com/trunk/PAPER/pc_fpga_com.pdf
pc_fpga_com/trunk/PAPER/pc_fpga_com.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: pc_fpga_com/trunk/fpga_com/fpga_com.h =================================================================== --- pc_fpga_com/trunk/fpga_com/fpga_com.h (nonexistent) +++ pc_fpga_com/trunk/fpga_com/fpga_com.h (revision 2) @@ -0,0 +1,65 @@ +/* + * Copyright (C) 2011 Simon A. Berger + * + * This program is free software; you may redistribute it and/or modify its + * under the terms of the GNU Lesser General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +const static int FPC_CODE_CHAR = 1; +const static int FPC_CODE_SHORT = 2; +const static int FPC_CODE_INT = 3; +const static int FPC_CODE_LONG = 5; +const static int FPC_CODE_FLOAT = 4; +const static int FPC_CODE_DOUBLE = 6; + +typedef struct { + /* local and remote socket addresses */ + struct sockaddr_in l_sockaddr; + struct sockaddr_in d_sockaddr; + + /* my socket */ + int s; + size_t mtu; +} fpga_con_t; + + +void fpga_con_init( fpga_con_t *con, const void *daddr, int lport, int dport ); +ssize_t fpga_con_send( fpga_con_t *con, const void *buf, size_t len ); +void fpga_con_send_init_packet( fpga_con_t *con ); +ssize_t fpga_con_block_recv( fpga_con_t *con, void *dbuf, size_t dsize ); + + + +int fpga_con_send_charv( fpga_con_t *con, char *buf, size_t n ); +int fpga_con_send_shortv( fpga_con_t *con, int16_t *buf, size_t n ); +int fpga_con_send_intv( fpga_con_t *con, int32_t *buf, size_t n ); +int fpga_con_send_longv( fpga_con_t *con, int64_t *buf, size_t n ); +int fpga_con_send_floatv( fpga_con_t *con, float *buf, size_t n ); +int fpga_con_send_doublev( fpga_con_t *con, double *buf, size_t n ); + + +void fpga_con_rpack_char( fpga_con_t *con, int size ); +void fpga_con_rpack_short( fpga_con_t *con, int size ); +void fpga_con_rpack_int( fpga_con_t *con, int size ); +void fpga_con_rpack_long( fpga_con_t *con, int size ); +void fpga_con_rpack_float( fpga_con_t *con, int size ); +void fpga_con_rpack_double( fpga_con_t *con, int size ); + +#ifdef __cplusplus +} +#endif Index: pc_fpga_com/trunk/fpga_com/background_reader.cpp =================================================================== --- pc_fpga_com/trunk/fpga_com/background_reader.cpp (nonexistent) +++ pc_fpga_com/trunk/fpga_com/background_reader.cpp (revision 2) @@ -0,0 +1,551 @@ +/* + * Copyright (C) 2011 Simon A. Berger + * + * This program is free software; you may redistribute it and/or modify its + * under the terms of the GNU Lesser General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include +#include +#include +#include +#include + +#include "background_reader.h" +#include "fpga_com.h" + +static void handler( int signal ) { + //printf( "signal: %d\n", signal ); +} + +background_reader::background_reader(int s, size_t size) + : m_stop(false), + m_socket(s), + m_max_size(size), + m_pq_mem(0), + m_pq_max_mem(0), + m_pq_max_depth(0), + N_THREADS(1), + m_run_barrier(N_THREADS + 1), + m_threads_joined(false) + //m_native_handle(0) +{ + +} + +background_reader::~background_reader() +{ + if( !m_threads_joined ) { + printf( "WARNING: background_reader::~background_reader(): threads not joined!\n" ); + } +} + + +void background_reader::start() { + /// m_thread.reset( new boost::thread( boost::bind(&background_reader::run, this))); + + + + printf( "starting %zd background reader threads\n", N_THREADS ); + //boost::barrier run_barrier( N_THREADS + 1 ); + + while( m_thread_group.size() < N_THREADS ) { + m_thread_group.create_thread(boost::bind(&background_reader::run, this )); + } + + m_run_barrier.wait(); +} + +void background_reader::run() +{ + // BIG-UGLY-KLUDGE-WARNING! + // we have to install a signal handler, in order to disable the auto-restart behaviour of the recv call... + // This is necessary to make the recv call interuptable (= return -1 on interrupt). Otherwise the + // bg threads would either wait forever, or we would need at least two syscalls per recv (any solution that involves select). + // + // the 'handler' does nothing, as we are only interested in interrupting the recv... + + struct sigaction sa; + sa.sa_handler = handler; + sigemptyset(&sa.sa_mask); + sa.sa_flags = 0; + + sigaction( SIGUSR1, &sa, 0 ); + + //m_native_handle = pthread_self(); + + { + lock_guard_t lock( m_nh_mtx ); + m_native_handles.push_back( pthread_self() ); + + } + + const size_t MTU = 64 * 1024; + + std::vectorbufs(MTU); + char *buf = bufs.data(); + + //run_barrier->wait(); + //run_barrier = 0; + m_run_barrier.wait(); + + while ( !m_stop ) { + ssize_t s = recv( m_socket, buf, MTU, 0 ); + +// if( s < 1024 && s != -1 ) { +// printf( "recved term packet %p\n", (void*)pthread_self() ); +// } + //printf( "recv: %zd\n", s ); + if ( s == -1 && errno == EINTR ) { + printf( "interrupted\n" ); + + } else { + lock_guard_t lock( m_pq_mtx ); + m_pq.push_back(std::string(buf, buf+s)); + m_pq_mem += s; + m_pq_max_mem = std::max( m_pq_mem, m_pq_max_mem ); + + + m_pq_max_depth = std::max( m_pq.size(), m_pq_max_depth ); + } +// printf( "notify\n" ); + m_can_read_condition.notify_one(); + } + + printf( "background reader thread exit\n" ); +} + +ssize_t background_reader::block_recv(void* buf, size_t size) +{ + boost::unique_lock lock( m_pq_mtx ); + + while ( ! m_pq.size() > 0 && !m_stop ) { +// printf( "cond_wait\n" ); + m_can_read_condition.wait(lock); + } + + if( m_pq.size() == 0 ) { + return -1; + } + + std::string &pbuf = m_pq.front(); + + m_pq_mem -= pbuf.size(); + + + ssize_t s = std::min( size, pbuf.size() ); + std::copy( pbuf.begin(), pbuf.end(), (char *)buf ); + m_pq.pop_front(); + + return s; +} + + +ssize_t background_reader::poll() +{ + lock_guard_t lock( m_pq_mtx ); + if( m_pq.size() > 0 ) { + return m_pq.front().size(); + } else { + return -1; + } +} + + +void background_reader::interrupt() { + //boost::thread::native_handle_type h = m_thread->native_handle(); + // pthread_kill( m_native_handle, SIGUSR1 ); + + lock_guard_t lock( m_nh_mtx ); + for( std::vector::iterator it = m_native_handles.begin(); it != m_native_handles.end(); ++it ) { + pthread_kill( *it, SIGUSR1 ); + } + +} + +void background_reader::join() { + // m_thread->join(); + m_thread_group.join_all(); + + printf( "pq max size (bytes): %zd\n", m_pq_max_mem ); + printf( "pq max depth (#packets): %zd\n", m_pq_max_depth ); + + m_threads_joined = true; +} + +ssize_t background_reader::purge() +{ + lock_guard_t lock( m_pq_mtx ); + + ssize_t s = m_pq.size(); + m_pq.clear(); + + return s; +} + + + +// int mainx() { +// fpga_con_t fc; +// +// fpga_con_init( &fc, "131.159.28.113", 12340, 12350 ); +// +// +// +// background_reader bgr( fc.s, 1024 * 1024 * 10 ); +// +// bgr.start(); +// +// char buf[1024]; +// memset( buf, 0, 1024 ); +// +// +// const size_t rbuf_size = 10 * 1024; +// char rbuf[rbuf_size]; +// +// printf( "sleep\n" ); +// // usleep( 2000000 ); +// printf( "close\n" ); +// //close( fc.s ); +// +// //bgr.stop(); +// //bgr.interrupt(); +// //getchar(); +// +// // bgr.join(); +// +// printf( "joined\n" ); +// size_t n = 0; +// for ( int i = 0; i < 10; i++ ) { +// fpga_con_send( &fc, buf, 1024 ); +// printf( "sent\n" ); +// +// +// +// while (true) { +// size_t s = bgr.block_recv( rbuf, rbuf_size ); +// n++; +// // printf( "recv: %zd\n", s ); +// if ( s < 1024 ) { +// break; +// } +// } +// +// printf( "recved: %zd\n", n ); +// } +// +// bgr.stop(); +// bgr.interrupt(); +// bgr.join(); +// printf( "bg reader joined. exit.\n" ); +// } + + + +static inline background_reader &get_bgr( fpga_bgr_t *cbgr ) { + assert( cbgr != 0 ); + assert( cbgr->bgr_cpp != 0 ); + return *(static_cast(cbgr->bgr_cpp)); +} + +void fpga_bgr_init( fpga_bgr_t *cbgr, int socket, size_t size ) { + memset( cbgr, 0, sizeof( fpga_bgr_t )); + + background_reader *bgr = new background_reader(socket, size); + cbgr->bgr_cpp = bgr; +} + +void fpga_bgr_delete( fpga_bgr_t *cbgr ) { + + background_reader *bgr = static_cast(cbgr->bgr_cpp); + delete bgr; + +} + +void fpga_bgr_start( fpga_bgr_t *cbgr) { + background_reader &bgr = get_bgr(cbgr); + bgr.start(); +} +ssize_t fpga_bgr_block_recv( fpga_bgr_t *cbgr, void *buf, size_t size ) { + background_reader &bgr = get_bgr(cbgr); + + return bgr.block_recv(buf, size); +} +ssize_t fpga_bgr_poll( fpga_bgr_t *cbgr ) { + background_reader &bgr = get_bgr(cbgr); + + return bgr.poll(); + +} +void fpga_bgr_stop_interrupt_join( fpga_bgr_t *cbgr) { + background_reader &bgr = get_bgr(cbgr); + + bgr.stop(); + bgr.interrupt(); + bgr.join(); +} + + +// template +// inline static T swap_endian( T &v ) { +// +// T vo = v; +// uint8_t *vb = (uint8_t*) &vo; +// +// for( size_t i = 0; i < sizeof(T) / 2; i++ ) { +// std::swap(vb[i], vb[sizeof(T) - i - 1]); +// +// } +// return vo; +// } + + +template +struct swap_endian { + inline T operator()( T &v ) { + + T vo = v; + uint8_t *vb = (uint8_t*) &vo; + + for( size_t i = 0; i < sizeof(T) / 2; i++ ) { + std::swap(vb[i], vb[sizeof(T) - i - 1]); + } + return vo; + } +}; + + +template +struct swap_endian { + inline T operator()( T &v ) { + uint16_t t = __bswap_16(*((uint16_t*)&v)); + + T* r = (T*)&t; // we don't want to dereference a type-punned pointer, do we? + return *r; + + } +}; + + +template +struct swap_endian { + inline T operator()( T &v ) { + uint32_t t = __bswap_32(*((uint32_t*)&v)); + + T* r = (T*)&t; + return *r; + } +}; + +template +struct swap_endian { + inline T operator()( T &v ) { + uint64_t t = __bswap_64(*((uint64_t*)&v)); + + T* r = (T*)&t; + return *r; + } +}; + + + + + +template +struct swappy_au { + const static size_t N = sizeof(T); + + + swap_endian swap; + inline void operator()( void * dest, void * src, size_t n ) { + std::copy( (char *)src, ((char *)src) + n * N, (char *)dest ); + //std::memcpy( dest, src, n * N ); + + T * ptr = (T *)dest; + T * end = ptr + n; + + // do the endian swapping in place in the aligned buffer + while( ptr < end ) { + *ptr = swap( *ptr ); + ptr++; + } + + } + +}; + +template +struct swappy_aa { + const static size_t N = sizeof(T); + swap_endian swap; + inline void operator()( void * dest, void * src, size_t n ) { + + + T * sptr = (T *)src; + T * ptr = (T *)dest; + T * end = ptr + n; + + // copy and swap on the fly, assuming that both buffers are aligned + while( ptr < end ) { + *ptr = swap( *sptr ); + ptr++; + sptr++; + } + + } + +}; + + +template +struct xerox_plain { + const static size_t N = sizeof(T); + inline void operator()( void * dest, void * src, size_t n ) { + std::copy( (char*)src, ((char*)src) + n * N, (char*)dest ); // using char* here to prevent std;:copy form making any assumptions about th alignment of src/dest + //std::copy( (T*)src, ((T*)src) + n, (T*)dest ); + } +}; + + +// template +// inline T passthrough( T &v ) { +// +// return v; +// } +// + +template +static bool fpga_bgr_recv_genv( fpga_bgr_t *cbgr, T *buf, size_t n, char ht ) { + background_reader &bgr = get_bgr(cbgr); + + + + T *buf_end = buf + n; + T *ptr = buf; + + const size_t MPU = 9000; + uint8_t rbuf[MPU]; + + CopyF xerox; + + while( ptr < buf_end ) { + + + ssize_t raw_size = bgr.block_recv(rbuf, MPU); +// printf( "ptr: %p %zd %d %d %d %d\n", ptr, size, rbuf[0], rbuf[1], rbuf[2], rbuf[3] ); + assert( raw_size > 1 ); + + if( rbuf[0] != ht ) { + printf( "drop wrong packet type: %d %d\n", rbuf[0], ht ); + } + + ssize_t size = raw_size - 1; + uint8_t *rptr = rbuf + 1; + + ssize_t ne = size / sizeof(T); + ssize_t left = buf_end - buf; + + ssize_t to_copy = std::min( ne, left ); + xerox( ptr, rptr, to_copy ); + + + ptr += to_copy; + } + + return true; +} + + +int fpga_bgr_recv_charv( fpga_bgr_t *bgr, char *buf, size_t n ) { + return fpga_bgr_recv_genv >( bgr, buf, n, FPC_CODE_CHAR ); +} + +int fpga_bgr_recv_shortv( fpga_bgr_t *bgr, int16_t *buf, size_t n ) { + return fpga_bgr_recv_genv >( bgr, buf, n, FPC_CODE_SHORT ); +} + +int fpga_bgr_recv_intv( fpga_bgr_t *bgr, int32_t *buf, size_t n ) { + return fpga_bgr_recv_genv >( bgr, buf, n, FPC_CODE_INT ); +} + +int fpga_bgr_recv_longv( fpga_bgr_t *bgr, int64_t *buf, size_t n ) { + return fpga_bgr_recv_genv >( bgr, buf, n, FPC_CODE_LONG ); +} + +int fpga_bgr_recv_floatv( fpga_bgr_t *bgr, float *buf, size_t n ) { + return fpga_bgr_recv_genv >( bgr, buf, n, FPC_CODE_FLOAT ); +} + +int fpga_bgr_recv_doublev( fpga_bgr_t *bgr, double *buf, size_t n ) { + //return fpga_bgr_recv_genv >( bgr, buf, n ); + return fpga_bgr_recv_genv >( bgr, buf, n, FPC_CODE_DOUBLE ); +} + +#if 0 + + +int main() { + fpga_con_t fc; + + fpga_con_init( &fc, "131.159.28.113", 12340, 12350 ); + + fpga_bgr_t bgr; + + fpga_bgr_init( &bgr, fc.s, 1024 * 1024 * 10 ); + + fpga_bgr_start( &bgr ); + + char buf[1024]; + memset( buf, 0, 1024 ); + int ibuf[1000]; + std::fill( ibuf, ibuf + 1000, 666 ); + + + const size_t rbuf_size = 10 * 1024; + char rbuf[rbuf_size]; + +// printf( "sleep\n" ); + // usleep( 2000000 ); +// printf( "close\n" ); + //close( fc.s ); + + //bgr.stop(); + //bgr.interrupt(); + //getchar(); + + // bgr.join(); + +// printf( "joined\n" ); + size_t n = 0; + for ( int i = 0; i < 1; i++ ) { + //fpga_con_send( &fc, buf, 1024 ); + fpga_con_send_intv( &fc, ibuf, 1000 ); + printf( "sent\n" ); + + double iv[1000]; + bool succ = fpga_bgr_recv_doublev( &bgr, iv, 1000 ); + + for( int i = 0; i < 1000; i++ ) { + printf( "%.2f ", iv[i] ); + if( i % 20 == 19 ) { + printf( "\n" ); + } + } + printf( "\n" ); + + printf( "recved: %d\n", succ ); + } + + fpga_bgr_stop_interrupt_join( &bgr ); + printf( "bg reader joined. exit.\n" ); + + fpga_bgr_delete( &bgr ); +} +#endif Index: pc_fpga_com/trunk/fpga_com/background_reader.h =================================================================== --- pc_fpga_com/trunk/fpga_com/background_reader.h (nonexistent) +++ pc_fpga_com/trunk/fpga_com/background_reader.h (revision 2) @@ -0,0 +1,115 @@ +/* + * Copyright (C) 2011 Simon A. Berger + * + * This program is free software; you may redistribute it and/or modify its + * under the terms of the GNU Lesser General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + + +#ifndef BACKGROUND_READER_H +#define BACKGROUND_READER_H + + +#ifdef __cplusplus + +#include +#include +#include +#include + +#include +#include + +#include +#include +// the all singing, all dancing background reader, written in shiny new c++ + +class background_reader +{ + typedef boost::mutex mutex_t; + //typedef boost::unique_lock unique_lock_t; + typedef boost::lock_guard lock_guard_t; + + boost::condition_variable m_can_read_condition; + boost::mutex m_pq_mtx; + //boost::scoped_ptr m_thread; + boost::thread_group m_thread_group; + + volatile bool m_stop; // FIXME: use atomic var + int m_socket; + + size_t m_max_size; + + std::deque m_pq; + size_t m_pq_mem; + size_t m_pq_max_mem; + + size_t m_pq_max_depth; + + + //pthread_t m_native_handle; + boost::mutex m_nh_mtx; + std::vector m_native_handles; + const size_t N_THREADS; + boost::barrier m_run_barrier; + bool m_threads_joined; + + void run(); +public: + background_reader( int s, size_t size ); + virtual ~background_reader(); + + void start(); + void interrupt(); + void stop() { m_stop = true; __sync_synchronize(); } // try to make sure that the new value of m_stop is visible to all bg threads before interrupt is called. + void join(); + + ssize_t block_recv( void* buf, size_t size ); + ssize_t poll(); + ssize_t purge(); + + +}; +#endif + +// the boring old ansi c interface + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct fpga_bgr_s { + void *bgr_cpp; +} fpga_bgr_t; + + +void fpga_bgr_init( fpga_bgr_t *bgr, int socket, size_t size ); +void fpga_bgr_delete( fpga_bgr_t *bgr ); + +void fpga_bgr_start( fpga_bgr_t *bgr); +ssize_t fpga_bgr_block_recv( fpga_bgr_t *bgr, void *buf, size_t size ); +ssize_t fpga_bgr_poll(); +void fpga_bgr_stop_interrupt_join( fpga_bgr_t *bgr); + +// high level functions +int fpga_bgr_recv_charv( fpga_bgr_t *bgr, char *buf, size_t n ); +int fpga_bgr_recv_shortv( fpga_bgr_t *bgr, int16_t *buf, size_t n ); +int fpga_bgr_recv_intv( fpga_bgr_t *bgr, int32_t *buf, size_t n ); +int fpga_bgr_recv_longv( fpga_bgr_t *bgr, int64_t *buf, size_t n ); +int fpga_bgr_recv_floatv( fpga_bgr_t *bgr, float *buf, size_t n ); +int fpga_bgr_recv_doublev( fpga_bgr_t *bgr, double *buf, size_t n ); + +#ifdef __cplusplus +} +#endif + + + +#endif // BACKGROUND_READER_H Index: pc_fpga_com/trunk/fpga_com/build.sh =================================================================== --- pc_fpga_com/trunk/fpga_com/build.sh (nonexistent) +++ pc_fpga_com/trunk/fpga_com/build.sh (revision 2) @@ -0,0 +1,2 @@ +gcc -std=c99 -Wall -O2 -c fpga_com.c +g++ -Wall -O2 -o testcase1 testcase1.cpp background_reader.cpp fpga_com.o -lboost_thread Index: pc_fpga_com/trunk/fpga_com/fpga_com.c =================================================================== --- pc_fpga_com/trunk/fpga_com/fpga_com.c (nonexistent) +++ pc_fpga_com/trunk/fpga_com/fpga_com.c (revision 2) @@ -0,0 +1,370 @@ +/* + * Copyright (C) 2011 Simon A. Berger + * + * This program is free software; you may redistribute it and/or modify its + * under the terms of the GNU Lesser General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + + +#include + +#include +#include +#include +#include + +#include "fpga_com.h" +#include +#include +#include + +const size_t MAX_MTU = 64 * 1024; + +static void die_perror( const char *call ) { + perror( call ); + exit(-1); +} + + +void fpga_con_init( fpga_con_t *con, const void *daddr, int lport, int dport ) { + + + + /*set up local socket address*/ + memset( &con->l_sockaddr, 0, sizeof( con->l_sockaddr )); + con->l_sockaddr.sin_family = AF_INET; + con->l_sockaddr.sin_addr.s_addr = INADDR_ANY; + con->l_sockaddr.sin_port = htons(lport); + + /*setup dest socket address*/ + memset( &con->d_sockaddr, 0, sizeof( con->d_sockaddr )); + con->d_sockaddr.sin_family = AF_INET; + con->d_sockaddr.sin_addr.s_addr = inet_addr( daddr ); + con->d_sockaddr.sin_port = htons(dport); + +/* create my socket*/ + con->s = socket( AF_INET, SOCK_DGRAM, IPPROTO_UDP ); + if( con->s < 0 ) { + die_perror( "socket" ); + } + +/* bind it to local socket*/ + int r = bind( con->s, (struct sockaddr *)&con->l_sockaddr, sizeof(con->l_sockaddr)); + if( r < 0 ) { + die_perror( "bind" ); + } + con->mtu = 1500; +} + +size_t fpga_con_get_mtu( fpga_con_t *con ) { + + return con->mtu; +} + +void fpga_con_set_mtu( fpga_con_t *con, size_t mtu ) { + + if( mtu > MAX_MTU ) { + printf( "fpga_con_set_mtu: mtu > MAX_MTU\n" ); + exit(-1); + } + con->mtu = mtu; +} + + +ssize_t fpga_con_send( fpga_con_t *con, const void *buf, size_t len ) { + + + ssize_t rsend = sendto( con->s, buf, len, 0, (struct sockaddr*)&con->d_sockaddr, sizeof(con->d_sockaddr)); + if( rsend < 0 ) { + die_perror( "sendto" ); + } + + return rsend; +} + + +/* send lut initialization packet sequence: rst, conf, empty*/ +void fpga_con_send_init_packet( fpga_con_t *con ) { + uint8_t buf[4]; + + buf[0] = 255; + fpga_con_send( con, buf, 1); + + buf[0] = 15; + fpga_con_send( con, buf, 1); + + fpga_con_send( con, buf, 0); +} + +/*blocking receive: this call will block until a packet is received*/ +ssize_t fpga_con_block_recv( fpga_con_t *con, void *dbuf, size_t dsize ) { + + ssize_t rrecv = recv( con->s, dbuf, dsize, 0 ); + + if( rrecv < 0 ) { + die_perror( "recv" ); + } + + return rrecv; +} + + +static __inline size_t mymin( size_t a, size_t b ) { + return a < b ? a : b; +} + +//const static size_t MTU = 1500; +const static size_t PH_SIZE = 1; + + +// static __inline size_t pack( uint8_t *buf, uint8_t ht, size_t buf_size, void *src, size_t src_size ) { +// assert( src_size + PH_SIZR <= buf_size ); +// +// buf[0] = ht; +// memcpy( buf + PH_SIZE, src, src_size ); +// +// return src_size + PH_SIZE; +// } + +// TODO; check how large the impact of doing the byte swappin on unaligned values really is +// there is no simple way around it (like in the receiving direction). +static __inline void swappy_16( void *dest, void *src, size_t n ) { + uint16_t *idest = (uint16_t*)dest; + uint16_t *isrc = (uint16_t*)src; + + for( size_t i = 0; i < n / 2; i++ ) { + idest[i] = __bswap_16(isrc[i]); + } +} + +static __inline void swappy_32( void *dest, void *src, size_t n ) { + uint32_t *idest = (uint32_t*)dest; + uint32_t *isrc = (uint32_t*)src; + + for( size_t i = 0; i < n / 4; i++ ) { + idest[i] = __bswap_32(isrc[i]); + } + +} + + +static __inline void swappy_64( void *dest, void *src, size_t n ) { + uint64_t *idest = (uint64_t*)dest; + uint64_t *isrc = (uint64_t*)src; + + for( size_t i = 0; i < n / 8; i++ ) { + idest[i] = __bswap_64(isrc[i]); + } +} + +#define BS_NONE (0) +#define BS_16 (1) +#define BS_32 (2) +#define BS_64 (3) + +static __inline size_t pack_and_send( fpga_con_t *con, uint8_t *buf, size_t buf_size, uint8_t ht, void *src, size_t src_size, int swap ) { + const size_t pack_size = src_size + PH_SIZE; + + assert( pack_size <= buf_size ); + + buf[0] = ht; + + switch( swap ) { + case BS_NONE: + memcpy( buf + PH_SIZE, src, src_size ); + break; + + case BS_16: + swappy_16( buf + PH_SIZE, src, src_size ); + break; + + case BS_32: + swappy_32( buf + PH_SIZE, src, src_size ); + break; + + + case BS_64: + swappy_64( buf + PH_SIZE, src, src_size ); + break; + + default: + assert(0); + } + + fpga_con_send( con, buf, pack_size ); + + return src_size + PH_SIZE; +} + + + + +int fpga_con_send_charv( fpga_con_t *con, char *buf, size_t n ) { + + + const size_t blocksize = (con->mtu - PH_SIZE); + uint8_t sb[MAX_MTU]; + + size_t sent = 0; + while( sent < n ) { + const size_t to_copy = mymin( blocksize, n - sent ); + + pack_and_send( con, sb, con->mtu, FPC_CODE_CHAR, (void*) &buf[sent], to_copy, BS_NONE ); + sent += to_copy; + } + + return 1; + +} + +int fpga_con_send_shortv( fpga_con_t *con, int16_t *buf, size_t n ) { + + + const size_t TSIZE = sizeof( short ); + + const size_t blocksize = (con->mtu - PH_SIZE) / TSIZE; + uint8_t sb[MAX_MTU]; + + size_t sent = 0; + while( sent < n ) { + const size_t to_copy = mymin( blocksize, n - sent ); + + //fpga_con_send( con, (void*) &buf[sent], to_copy * TSIZE ); + pack_and_send( con, sb, con->mtu, FPC_CODE_SHORT, (void*) &buf[sent], to_copy * TSIZE, BS_16 ); + + sent += to_copy; + + } + return 1; + +} +int fpga_con_send_intv( fpga_con_t *con, int32_t *buf, size_t n ) { + + + const size_t TSIZE = sizeof( int ); + + const size_t blocksize = (con->mtu - PH_SIZE) / TSIZE; + + uint8_t sb[MAX_MTU]; + + size_t sent = 0; + while( sent < n ) { + const size_t to_copy = mymin( blocksize, n - sent ); + +// fpga_con_send( con, (void*) &buf[sent], to_copy * TSIZE ); + pack_and_send( con, sb, con->mtu, FPC_CODE_INT, (void*) &buf[sent], to_copy * TSIZE, BS_32 ); + + sent += to_copy; + + } + + return 1; +} + + +int fpga_con_send_longv( fpga_con_t *con, int64_t *buf, size_t n ) { + + + const size_t TSIZE = sizeof( int64_t ); + + const size_t blocksize = (con->mtu - PH_SIZE) / TSIZE; + + uint8_t sb[MAX_MTU]; + + size_t sent = 0; + while( sent < n ) { + const size_t to_copy = mymin( blocksize, n - sent ); + +// fpga_con_send( con, (void*) &buf[sent], to_copy * TSIZE ); + pack_and_send( con, sb, con->mtu, FPC_CODE_LONG, (void*) &buf[sent], to_copy * TSIZE, BS_64 ); + + sent += to_copy; + + } + + return 1; +} + +int fpga_con_send_floatv( fpga_con_t *con, float *buf, size_t n ) { + const size_t TSIZE = sizeof( int ); + + const size_t blocksize = (con->mtu - PH_SIZE) / TSIZE; + + uint8_t sb[MAX_MTU]; + + size_t sent = 0; + while( sent < n ) { + const size_t to_copy = mymin( blocksize, n - sent ); + +// fpga_con_send( con, (void*) &buf[sent], to_copy * TSIZE ); + pack_and_send( con, sb, con->mtu, FPC_CODE_FLOAT, (void*) &buf[sent], to_copy * TSIZE, BS_32 ); + + sent += to_copy; + + } + + return 1; +} + +int fpga_con_send_doublev( fpga_con_t *con, double *buf, size_t n ) { + + + const size_t TSIZE = sizeof( double ); + + const size_t blocksize = (con->mtu - PH_SIZE) / TSIZE; + + uint8_t sb[MAX_MTU]; + + + size_t sent = 0; + while( sent < n ) { + const size_t to_copy = mymin( blocksize, n - sent ); + +// fpga_con_send( con, (void*) &buf[sent], to_copy * TSIZE ); + pack_and_send( con, sb, con->mtu, FPC_CODE_DOUBLE, (void*) &buf[sent], to_copy * TSIZE, BS_64 ); + sent += to_copy; + } + + return 1; +} + +static void fpga_con_rpack( fpga_con_t *con, int code, int size ) { + char buf[3] = { 120, 0, 0 }; + buf[0] += code; + + + assert( size > 0 && size < 0xffff ); + unsigned short ssize = size; + + swappy_16( &buf[1], &ssize, 2); + + fpga_con_send(con, buf, 3); +} + +void fpga_con_rpack_char( fpga_con_t *con, int size ) { + fpga_con_rpack( con, FPC_CODE_CHAR, size ); +} +void fpga_con_rpack_short( fpga_con_t *con, int size ) { + fpga_con_rpack( con, FPC_CODE_SHORT, size ); +} +void fpga_con_rpack_int( fpga_con_t *con, int size ) { + fpga_con_rpack( con, FPC_CODE_INT, size); +} +void fpga_con_rpack_long( fpga_con_t *con, int size ) { + fpga_con_rpack( con, FPC_CODE_LONG, size); +} + +void fpga_con_rpack_float( fpga_con_t *con, int size ) { + fpga_con_rpack( con, FPC_CODE_FLOAT, size ); +} +void fpga_con_rpack_double( fpga_con_t *con, int size ) { + fpga_con_rpack( con, FPC_CODE_DOUBLE, size ); +} + Index: pc_fpga_com/trunk/fpga_com/testcase1.cpp =================================================================== --- pc_fpga_com/trunk/fpga_com/testcase1.cpp (nonexistent) +++ pc_fpga_com/trunk/fpga_com/testcase1.cpp (revision 2) @@ -0,0 +1,195 @@ +/* + * Copyright (C) 2011 Simon A. Berger + * + * This program is free software; you may redistribute it and/or modify its + * under the terms of the GNU Lesser General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include + +#include +#include +#include +#include +#include +#include "fpga_com.h" +#include "background_reader.h" + +int main() { + + fpga_con_t fc; + + fpga_con_init( &fc, "192.168.1.1", 21844, 21845 ); + + fpga_bgr_t bgr; + + fpga_bgr_init( &bgr, fc.s, 1024 * 1024 * 10 ); + + fpga_bgr_start( &bgr ); + + + fpga_con_send_init_packet( &fc ); + + bool do_char = !false; + bool do_short = !false; + bool do_int = true; + bool do_long = true; + bool do_float = true; + bool do_double = true; + const int N = 127; + if(do_char) + { + char test[N]; + for( int i = 0; i < N; i++ ) { + + test[i] = i;// + 'a'; + + } + + fpga_con_send_charv( &fc, test, N); + + + char rec[N]; + fpga_con_rpack_char(&fc,N); + fpga_bgr_recv_charv(&bgr, rec, N ); + + + printf( "recv char: \n" ); + for( int i = 0; i < N; i++ ) { + printf( " recv: %d %d\n", test[i], rec[i] ); + } + + } + if(do_short) + { + + short test[N]; + for( int i = 0; i < N; i++ ) { + + test[i] = i; + + } + + fpga_con_send_shortv( &fc, test, N); + + + short rec[N]; + fpga_con_rpack_short(&fc,N); + fpga_bgr_recv_shortv(&bgr, rec, N ); + + + printf( "recv short: \n" ); + for( int i = 0; i < N; i++ ) { + printf( " recv: %d %d\n", test[i], rec[i] ); + + + } + + + + } + if( do_int ) + { + int test[N]; + for( int i = 0; i < N; i++ ) { + + test[i] = i; + + } + + fpga_con_send_intv( &fc, test, N); + + + + + int rec[N]; + fpga_con_rpack_int(&fc,N); + fpga_bgr_recv_intv(&bgr, rec, N ); + + + printf( "recv int: \n" ); + for( int i = 0; i < N; i++ ) { + printf( " recv: %d %d\n", test[i], rec[i] ); + } + + } + if( do_long ) + { + int64_t test[N]; + for( int i = 0; i < N; i++ ) { + + test[i] = i * int64_t(1024) * 1024 * 1024; + + } + + fpga_con_send_longv( &fc, test, N); + + + int64_t rec[N]; + fpga_con_rpack_long(&fc,N); + fpga_bgr_recv_longv(&bgr, rec, N ); + + + printf( "recv long: \n" ); + for( int i = 0; i < N; i++ ) { + std::cout << " recv " << test[i] << " " << rec[i] << std::endl; + } + } + + if( do_float ) + { + float test[N]; + for( int i = 0; i < N; i++ ) { + + test[i] = i * 100000; + + } + + fpga_con_send_floatv( &fc, test, N); + + + float rec[N]; + fpga_con_rpack_float(&fc,N); + fpga_bgr_recv_floatv(&bgr, rec, N ); + + + printf( "recv float: \n" ); + for( int i = 0; i < N; i++ ) { + printf( " recv: %f %f\n", test[i], rec[i] ); + } + } + + if(do_double) + { + double test[N]; + for( int i = 0; i < N; i++ ) { + + test[i] = i * 1000000; + + } + + fpga_con_send_doublev( &fc, test, N); + + double rec[N]; + fpga_con_rpack_double(&fc,N); + fpga_bgr_recv_doublev(&bgr, rec, N ); + + + printf( "recv double: \n" ); + for( int i = 0; i < N; i++ ) { + printf( " recv: %f %f\n", test[i], rec[i] ); + } + } + + fpga_bgr_stop_interrupt_join(&bgr); + fpga_bgr_delete(&bgr); + + +} Index: pc_fpga_com/trunk/fpga_com/README =================================================================== --- pc_fpga_com/trunk/fpga_com/README (nonexistent) +++ pc_fpga_com/trunk/fpga_com/README (revision 2) @@ -0,0 +1,11 @@ +Use the build script (build.sh) to compile the simple test program (testcase1.cpp). +In this test case we send an array of 10 floats, after which the program waits +for a reply consisting of 10 float from the FPGA. The software interface depends +on a working installation of the boost libraries (www.boost.org) and a resonable +c++ compiler and STL implementation. + +The example also serves as the official documentation for the software interface, +as far as the initilization of the fpga_con_t and fpga_bgr_t objects is concerned. + +Visit https://github.com/sim82/c_tools/tree/master/fpga_com for the latest version +of this library. Index: pc_fpga_com/trunk/README.txt =================================================================== --- pc_fpga_com/trunk/README.txt (nonexistent) +++ pc_fpga_com/trunk/README.txt (revision 2) @@ -0,0 +1,83 @@ +================================================================================= +PC-FPGA COMMUNICATION PLATFORM and VERSATILE UDP/IP CORE IMPLEMENTATION FOR FPGAs +================================================================================= + +Release date: March 21th, 2011 + + +Description +----------- + +This package provides an open-source VHDL implementation of a UDP/IP core architecture +and a PC-FPGA interface for transmission of basic C types (chars, 16/32/64-bit integers, floats and doubles). + + +Package Structure +----------------- + +This package contains the following files and folder: + +-README : This file + +-UDP_IP_CORE_FLEX_Spartan3 : This folder contains VHDL, XCO and NGC files for Spartan3 devices. + +-UDP_IP_CORE_FLEX_Virtex5 : This folder contains VHDL, XCO and NGC files for Virtex5 devices. + +-PC_FPGA_PLATFPORM : This folder contains VHDL, XCO and NGC files for Virtex5 devices as well as C/C++ files. + +-PAPER : This folder contains a paper that describes in detail the design and implementation of the core and the platform. + + + +Verification Details +-------------------- + +The development board HTG-V5-PCIE by HiTech Global populated with a V5SX95T-1 FPGA was used to verify the correct behavior of the platform and the core. + + +Citation +-------- + +By using this component in any architecture design and associated publication, you agree to cite it as: +"A Versatile UDP/IP based PC-FPGA Communication Platform", by Nikolaos Alachiotis, Simon A. Berger and Alexandros Stamatakis, +submitted to FPL2011. + + +Authors and Contact Details +--------------------------- + +Nikos Alachiotis n.alachiotis@gmail.com, nikolaos.alachiotis@h-its.org +Simon A. Berger simon.berger@h-its.org +Alexandros Stamatakis alexandros.stamatakis@h-its.org + + +Scientific Computing Group (Exelixis Lab) +Heidelberg Institute for Theoretical Studies (HITS gGmbH) + +Schloss-Wolfsbrunnenweg 35 +D-69118 Heidelberg +Germany + + +Copyright +--------- + +This component is free. In case you use it for any purpose, particularly +when publishing work relying on this component you must cite it as: N. Alachiotis, S.A. Berger, A. Stamatakis: "A Versatile UDP/IP based PC-FPGA Communication Platform". + +You can redistribute it and/or modify +it under the terms of the GNU Lesser General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This component is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + + +Release Notes +------------- + +Release date: March 21th, 2011 Index: pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/PACKET_RECEIVER_FSM.vhd =================================================================== --- pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/PACKET_RECEIVER_FSM.vhd (nonexistent) +++ pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/PACKET_RECEIVER_FSM.vhd (revision 2) @@ -0,0 +1,238 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 03:48:34 02/07/2010 +-- Design Name: +-- Module Name: PACKET_RECEIVER_FSM - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity PACKET_RECEIVER_FSM is + Port ( + rst : in STD_LOGIC; + clk : in STD_LOGIC; + + -- Signals from EMAC + rx_sof: in STD_LOGIC; -- active low input + rx_eof: in STD_LOGIC; -- active low input + + -- Signals to Counter and Comparator + sel_comp_Bval: out STD_LOGIC; + comp_Bval: out STD_LOGIC_VECTOR(10 downto 0); + rst_count : out STD_LOGIC; + en_count : out STD_LOGIC; + + -- Signal from Comparator + comp_eq: in STD_LOGIC; + + -- Signals to Length Register + wren_MSbyte: out STD_LOGIC; + wren_LSbyte: out STD_LOGIC; + + -- Signal to user interface + valid_out_usr_data: out STD_LOGIC); +end PACKET_RECEIVER_FSM; + +architecture Behavioral of PACKET_RECEIVER_FSM is + +TYPE state is (rst_state, + idle_state, + detect_n_store_usr_length_MSbyte_state, + store_usr_length_LSbyte_state, + checksum_gap_state, + receive_usr_data_state); + +signal current_st,next_st: state; + +constant udp_length_match_cycle : std_logic_vector(10 downto 0):="00000100100"; -- UDP length MSbyte - 2 +constant udp_checksum_skip : std_logic_vector(10 downto 0):="00000000001"; +constant gnd_vec : std_logic_vector(10 downto 0):="00000000000"; +begin + +process(current_st,rx_sof,rx_eof,comp_eq) +begin +case current_st is + + +when rst_state => + + sel_comp_Bval<='0'; + comp_Bval<=gnd_vec; + rst_count<='1'; + en_count<='0'; + + wren_MSbyte<='0'; + wren_LSbyte<='0'; + + valid_out_usr_data<='0'; + + next_st<=idle_state; + +when idle_state => + + if rx_sof='0' then -- rx_sof is active low + sel_comp_Bval<='0'; + comp_Bval<=udp_length_match_cycle; + rst_count<='1'; + en_count<='0'; + + wren_MSbyte<='0'; + wren_LSbyte<='0'; + + valid_out_usr_data<='0'; + + next_st<=detect_n_store_usr_length_MSbyte_state; + + else + sel_comp_Bval<='0'; + comp_Bval<=gnd_vec; + rst_count<='0'; + en_count<='0'; + + wren_MSbyte<='0'; + wren_LSbyte<='0'; + + valid_out_usr_data<='0'; + + next_st<=idle_state; + end if; + +when detect_n_store_usr_length_MSbyte_state => + + if comp_eq='1' then -- comp_eq is active high + sel_comp_Bval<='0'; + comp_Bval<=udp_checksum_skip; -- Just to skip the UDP checksum field + rst_count<='1'; + en_count<='0'; + + wren_MSbyte<='1'; + wren_LSbyte<='0'; + + valid_out_usr_data<='0'; + + next_st<=store_usr_length_LSbyte_state; + + else + sel_comp_Bval<='0'; + comp_Bval<=udp_length_match_cycle; + rst_count<='0'; + en_count<='1'; + + wren_MSbyte<='0'; + wren_LSbyte<='0'; + + valid_out_usr_data<='0'; + + next_st<=detect_n_store_usr_length_MSbyte_state; + end if; + +when store_usr_length_LSbyte_state => + + sel_comp_Bval<='0'; + comp_Bval<=udp_checksum_skip; -- Just to skip the UDP checksum field + rst_count<='0'; + en_count<='1'; + + wren_MSbyte<='0'; + wren_LSbyte<='1'; + + valid_out_usr_data<='0'; + + next_st<=checksum_gap_state; + +when checksum_gap_state => + + if comp_eq='1' then -- comp_eq is active high + sel_comp_Bval<='1'; + comp_Bval<=gnd_vec; + rst_count<='1'; + en_count<='0'; + + wren_MSbyte<='0'; + wren_LSbyte<='0'; + + valid_out_usr_data<='0'; + + next_st<=receive_usr_data_state; + + else + sel_comp_Bval<='0'; + comp_Bval<=udp_checksum_skip; + rst_count<='0'; + en_count<='1'; + + wren_MSbyte<='0'; + wren_LSbyte<='0'; + + valid_out_usr_data<='0'; + + next_st<=checksum_gap_state; + end if; + +when receive_usr_data_state => + + if (comp_eq='1' or rx_eof='0') then -- comp_eq is active high rx_eof is active-low + sel_comp_Bval<='0'; + comp_Bval<=udp_length_match_cycle; + rst_count<='1'; + en_count<='0'; + + wren_MSbyte<='0'; + wren_LSbyte<='0'; + + valid_out_usr_data<='1'; + + next_st<=idle_state; + + else + sel_comp_Bval<='1'; + comp_Bval<=gnd_vec; + rst_count<='0'; + en_count<='1'; + + wren_MSbyte<='0'; + wren_LSbyte<='0'; + + valid_out_usr_data<='1'; + + next_st<=receive_usr_data_state; + end if; + + +end case; +end process; + + + + +process(clk) +begin +if (rst='1') then + current_st<= rst_state; +elsif (clk'event and clk='1') then + current_st <= next_st; +end if; +end process; + +end Behavioral; + Index: pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/comp_11b_equal.xco =================================================================== --- pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/comp_11b_equal.xco (nonexistent) +++ pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/comp_11b_equal.xco (revision 2) @@ -0,0 +1,59 @@ +############################################################## +# +# Xilinx Core Generator version K.39 +# Date: Mon Nov 30 15:37:25 2009 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = False +SET asysymbol = False +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = VHDL +SET device = xc5vsx95t +SET devicefamily = virtex5 +SET flowvendor = Other +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = ff1136 +SET removerpms = False +SET simulationfiles = Structural +SET speedgrade = -1 +SET verilogsim = False +SET vhdlsim = True +# END Project Options +# BEGIN Select +SELECT Comparator family Xilinx,_Inc. 9.0 +# END Select +# BEGIN Parameters +CSET aclr=false +CSET ainitval=0 +CSET aset=false +CSET ce=false +CSET cepriority=Sync_Overrides_CE +CSET component_name=comp_11b_equal +CSET constantbport=false +CSET constantbportvalue=0000000000000000 +CSET datatype=Unsigned +CSET nonregisteredoutput=false +CSET operation=eq +CSET pipelinestages=0 +CSET radix=2 +CSET registeredoutput=true +CSET sclr=false +CSET sset=false +CSET syncctrlpriority=Reset_Overrides_Set +CSET width=11 +# END Parameters +GENERATE +# CRC: 6f28c282 + Index: pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/REG_8b_wren.vhd =================================================================== --- pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/REG_8b_wren.vhd (nonexistent) +++ pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/REG_8b_wren.vhd (revision 2) @@ -0,0 +1,56 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 14:40:03 02/07/2010 +-- Design Name: +-- Module Name: REG_8b_wren - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity REG_8b_wren is + Port ( rst : in STD_LOGIC; + clk : in STD_LOGIC; + wren : in STD_LOGIC; + input_val : in STD_LOGIC_VECTOR (7 downto 0); + output_val : inout STD_LOGIC_VECTOR(7 downto 0)); +end REG_8b_wren; + +architecture Behavioral of REG_8b_wren is + +begin + +process(clk) +begin +if rst='1' then + output_val<="00000000"; +else + if clk'event and clk='1' then + if wren='1' then + output_val<=input_val; + end if; + end if; +end if; +end process; + +end Behavioral; + Index: pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/COUNTER_11B_EN_RECEIV.vhd =================================================================== --- pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/COUNTER_11B_EN_RECEIV.vhd (nonexistent) +++ pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/COUNTER_11B_EN_RECEIV.vhd (revision 2) @@ -0,0 +1,58 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 16:16:57 11/30/2009 +-- Design Name: +-- Module Name: COUNTER_11B_EN_RECEIV - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity COUNTER_11B_EN_RECEIV is + Port ( rst : in STD_LOGIC; + clk : in STD_LOGIC; + count_en : in STD_LOGIC; + value_O : inout STD_LOGIC_VECTOR (10 downto 0)); +end COUNTER_11B_EN_RECEIV; + +architecture Behavioral of COUNTER_11B_EN_RECEIV is + +begin + +process(clk) +begin +if rst='1' then + value_O<="00000000000"; +else + if clk'event and clk='1' then + if count_en='1' then + value_O<=value_O+"00000000001"; + else + value_O<=value_O; + end if; + end if; +end if; +end process; + + +end Behavioral; + Index: pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/COUNTER_6B_LUT_FIFO_MODE.vhd =================================================================== --- pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/COUNTER_6B_LUT_FIFO_MODE.vhd (nonexistent) +++ pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/COUNTER_6B_LUT_FIFO_MODE.vhd (revision 2) @@ -0,0 +1,63 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 02:30:12 11/30/2009 +-- Design Name: +-- Module Name: COUNTER_6B_LUT_FIFO_MODE - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity COUNTER_6B_LUT_FIFO_MODE is + Port ( rst : in STD_LOGIC; + clk : in STD_LOGIC; + funct_sel : in STD_LOGIC; -- 0 for lut addressing, 1 for fifo addressing + count_en : in STD_LOGIC; + value_O : inout STD_LOGIC_VECTOR (5 downto 0)); +end COUNTER_6B_LUT_FIFO_MODE; + +architecture Behavioral of COUNTER_6B_LUT_FIFO_MODE is + +begin + +process(clk) +begin +if rst='1' then + if funct_sel='0' then + value_O<=(others=>'0'); + else + value_O<="100111"; + end if; +else + if clk'event and clk='1' then + if count_en='1' then + value_O<=value_O+"000001"; + else + value_O<=value_O; + end if; + end if; +end if; +end process; + + +end Behavioral; + Index: pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/comp_6b_equal.ngc =================================================================== --- pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/comp_6b_equal.ngc (nonexistent) +++ pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/comp_6b_equal.ngc (revision 2) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4e +$92x5d=#Zl|bdaa:!3-522):'?%8#?/$09355=789:;<=>70323<54438$;j6;ysy;6pc`69:<&=h59:HLSQQ86M5/QJg[Uthbli"Zge^Dfhvci{}obbRM`Psm`avuhz&ID^HIJN^Ffwlai'}g{#Rmh/bmntZ0eWl{~ma agn31?FNBKBUGENKASD]W]UC>3JEFADZ[EE37?FIUMVMNBH\NTHMM[LHAG>1H^HO[EE38@7=AL81L?6IAD39J47=N9;1B>?5F339J07=N=01BBDZ\T@VF2>JHIMOO;6B@GHABH1=K]]>?7A[[6b9Neoiu^lxxeb`l;LkmkwPbzzcdb>5A0018J4643G;:?6@>229M56597C<<;O056>H4:2D?>6@:2:L56>H0:2D3>6@6f:LA[GSTX@DT\_A_S69MAQQHZB;0C?5@K09S0>VFZ]k0\D@PBTQJ@]dS7'noeS~z}ubvvv`Ykgnch"jka_ommtlvbd`dnh#oPepwbhZhh|l{~maQm.h]b[`wXflUi#dQzsd]`ewt~Wyf~Rbztr,oqqYffm$bSjo{e^`jp*rnm{UlicU>]/k\plcu'eed|RzfldqX4X(nW}cgi"a>06c3?P6(oldTy|zcuwqaZjho`i%kh`Pnnlsmuckagoo"lQjqtco[kismxj`Rl!i^c\atYimVh$eR{|e^abvwXxexSa{{s/nvpZgil'cTklzj_ckw+qobzVmnbV?R.h]wm`t(dfe{SygcerY3Y+oX|`fn#b??7^QT4S7'noeS~z}ubvvv`Ykgnch"jka_ommtlvbd`dnh#oPepwbhZhh|l{~maQm.h]b[`wXflUi#ykbp^pfwpjsi2_XI_QNLHCPg>STM[U]E^GMLD18RFE>3_CN[RZVPD3g?]OKAGR&TIL/0/3#WQSE(9$:,L]LIH48\VRKAK=0T^ZPGOFa?]YDG[OTECH@6:ZgfZOcn2RodR^}ilTfvvohf8:0TicPM`hlvScu{`ee==5Wdl]Nmkiu^lxxeb`;;`*3-1=f 8#?7l&=)59b,6/33h"?%95n(4+7?d:76=1j0<0;;`>1:1=f4:4?7l2;>79b80<76=1j0809;`]fuZd13hUliRl9;`]dpZd13hUgiRl9;`]opZd13hUeiRl;;`aov1=f{l~?7o&?)59a,4/33k"9%95m(2+7?g.3!=1i$8';;c>3:1=e484?7o2=>59a86833k6?2;5m<483:1=e4<48=6mPcnosewcX~0U; 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It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = False +SET asysymbol = False +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = VHDL +SET device = xc5vsx95t +SET devicefamily = virtex5 +SET flowvendor = Other +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = ff1136 +SET removerpms = False +SET simulationfiles = Structural +SET speedgrade = -1 +SET verilogsim = False +SET vhdlsim = True +# END Project Options +# BEGIN Select +SELECT Distributed_Memory_Generator family Xilinx,_Inc. 3.4 +# END Select +# BEGIN Parameters +CSET ce_overrides=ce_overrides_sync_controls +CSET coefficient_file="C:/VERIFICATION PLATFORM/UDP_IP_FLEX/COREGEN/ipv4_lut.coe" +CSET common_output_ce=false +CSET common_output_clk=false +CSET component_name=dist_mem_64x8 +CSET data_width=8 +CSET default_data=0 +CSET default_data_radix=16 +CSET depth=64 +CSET dual_port_address=non_registered +CSET dual_port_output_clock_enable=false +CSET input_clock_enable=false +CSET input_options=non_registered +CSET memory_type=single_port_ram +CSET output_options=registered +CSET pipeline_stages=0 +CSET qualify_we_with_i_ce=false +CSET reset_qdpo=false +CSET reset_qspo=false +CSET single_port_output_clock_enable=false +CSET sync_reset_qdpo=false +CSET sync_reset_qspo=false +# END Parameters +GENERATE +# CRC: b55d2f1c + Index: pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/OVERRIDE_LUT_CONTROL.vhd =================================================================== --- pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/OVERRIDE_LUT_CONTROL.vhd (nonexistent) +++ pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/OVERRIDE_LUT_CONTROL.vhd (revision 2) @@ -0,0 +1,108 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 15:09:25 11/30/2009 +-- Design Name: +-- Module Name: OVERRIDE_LUT_CONTROL - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity OVERRIDE_LUT_CONTROL is + Port ( clk : in STD_LOGIC; + input_addr : in STD_LOGIC_VECTOR (5 downto 0); + sel_total_length_MSBs : out STD_LOGIC; + sel_total_length_LSBs : out STD_LOGIC; + sel_header_checksum_MSBs : out STD_LOGIC; + sel_header_checksum_LSBs : out STD_LOGIC; + sel_length_MSBs : out STD_LOGIC; + sel_length_LSBs : out STD_LOGIC + ); +end OVERRIDE_LUT_CONTROL; + +architecture Behavioral of OVERRIDE_LUT_CONTROL is + +component comp_6b_equal is + port ( + qa_eq_b : out STD_LOGIC; + clk : in STD_LOGIC := 'X'; + a : in STD_LOGIC_VECTOR ( 5 downto 0 ); + b : in STD_LOGIC_VECTOR ( 5 downto 0 ) + ); +end component; + +constant total_length_addr1 : std_logic_vector(5 downto 0):="010000"; +constant total_length_addr2 : std_logic_vector(5 downto 0):="010001"; + +constant header_checksum_addr1 : std_logic_vector(5 downto 0):="011000"; +constant header_checksum_addr2 : std_logic_vector(5 downto 0):="011001"; + +constant length_addr1 : std_logic_vector(5 downto 0):="100110"; +constant length_addr2 : std_logic_vector(5 downto 0):="100111"; + + +signal sel_header_checksum_MSBs_tmp : std_logic; +signal sel_total_length_MSBs_tmp : std_logic; +signal sel_length_MSBs_tmp : std_logic; + +begin + +TARGET_TOTAL_LENGTH_1 : comp_6b_equal port map (sel_total_length_MSBs_tmp,clk,input_addr,total_length_addr1); + +process(clk) +begin +if clk'event and clk='1' then + sel_total_length_LSBs<=sel_total_length_MSBs_tmp; +end if; +end process; +sel_total_length_MSBs<=sel_total_length_MSBs_tmp; + +--TARGET_TOTAL_LENGTH_2 : comp_6b_equal port map (sel_total_length_LSBs,clk,input_addr,total_length_addr2); + +TARGET_HEADER_CHECKSUM_1 : comp_6b_equal port map (sel_header_checksum_MSBs_tmp,clk,input_addr,header_checksum_addr1); +process(clk) +begin +if clk'event and clk='1' then + sel_header_checksum_LSBs<=sel_header_checksum_MSBs_tmp; +end if; +end process; + +sel_header_checksum_MSBs<=sel_header_checksum_MSBs_tmp; + + + +--TARGET_HEADER_CHECKSUM_2 : comp_6b_equal port map (sel_header_checksum_LSBs,clk,input_addr,header_checksum_addr2); + +TARGET_LENGTH_1 : comp_6b_equal port map (sel_length_MSBs_tmp,clk,input_addr,length_addr1); + +process(clk) +begin +if clk'event and clk='1' then + sel_length_LSBs<=sel_length_MSBs_tmp; +end if; +end process; + +sel_length_MSBs<=sel_length_MSBs_tmp; +--TARGET_LENGTH_2 : comp_6b_equal port map (sel_length_LSBs,clk,input_addr,length_addr2); + +end Behavioral; + Index: pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/CONFIG_CONTROL.vhd =================================================================== --- pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/CONFIG_CONTROL.vhd (nonexistent) +++ pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/CONFIG_CONTROL.vhd (revision 2) @@ -0,0 +1,215 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 14:28:06 01/11/2011 +-- Design Name: +-- Module Name: CONFIG_CONTROL - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity CONFIG_CONTROL is + Port ( rst : in STD_LOGIC; + clk : in STD_LOGIC; + config_en : in STD_LOGIC; + nxt_sof : in STD_LOGIC; + wren : out STD_LOGIC; + addr : out STD_LOGIC_VECTOR (5 downto 0); + ulock_en : in STD_LOGIC; + wren_checksum_1 : out STD_LOGIC; + wren_checksum_2 : out STD_LOGIC; + locked : out STD_LOGIC + ); +end CONFIG_CONTROL; + +architecture Behavioral of CONFIG_CONTROL is + +TYPE state is (rst_state, + idle_state, + pre_config_state, + config_state, + lock_state + ); + +signal current_st,next_st: state; + +signal rst_count, en_count, stop_s, wren_checksum_1_t: std_logic; +signal counter: std_logic_vector(5 downto 0); + + + + +component wraddr_lut_mem is + port ( + clk : in STD_LOGIC := 'X'; + a : in STD_LOGIC_VECTOR ( 5 downto 0 ); + qspo : out STD_LOGIC_VECTOR ( 5 downto 0 ) + ); +end component; + +begin + +process(clk) +begin +if (rst='1') then + current_st<= rst_state; +elsif (clk'event and clk='1') then + current_st <= next_st; +end if; +end process; + + +process(current_st,config_en,nxt_sof,ulock_en,stop_s) +begin +case current_st is + +when rst_state => + + rst_count <='1'; + en_count <='0'; + + wren <='0'; + + locked<='0'; + + next_st<=idle_state; + +when idle_state => + + rst_count <='0'; + en_count <='0'; + + wren <='0'; + + locked<='0'; + + if config_en='1' then + next_st <= pre_config_state; + else + next_st <= idle_state; + end if; + +when pre_config_state => + + rst_count <='0'; + en_count <='0'; + + wren <='0'; + + locked<='0'; + + if nxt_sof='0' then + en_count <='1'; + next_st <= config_state; + else + en_count <='0'; + next_st <= pre_config_state; + end if; + + +when config_state => + + rst_count <='0'; + en_count <='1'; + + wren <='1'; + + locked<='0'; + + if stop_s='1' then + next_st <= lock_state; + else + next_st <= config_state; + end if; + +when lock_state => + + rst_count <='1'; + en_count <='0'; + + wren <='0'; + + locked<='1'; + + if ulock_en='1' then + next_st <= rst_state; + else + next_st <= lock_state; + end if; + +end case; +end process; + +process(clk) +begin +if rst_count='1' then + counter <= "000000"; +else + if clk'event and clk='1' then + if en_count='1' then + counter <= counter + "000001"; + end if; + end if; +end if; +end process; + +process(clk) +begin +if clk'event and clk='1' then + if counter = "100101" then + stop_s <='1'; + else + stop_s <='0'; + end if; +end if; +end process; + +process(clk) +begin +if clk'event and clk='1' then + if counter = "010111" then + wren_checksum_1_t <='1'; + else + wren_checksum_1_t <='0'; + end if; +end if; +end process; + +wren_checksum_1 <= wren_checksum_1_t; + +process(clk) +begin +if clk'event and clk='1' then + wren_checksum_2 <= wren_checksum_1_t; +end if; +end process; + + + +wraddrlutmem: wraddr_lut_mem Port Map + ( + clk => clk, + a=> counter, + qspo=> addr); + +end Behavioral; + Index: pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/IPV4_PACKET_TRANSMITTER.vhd =================================================================== --- pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/IPV4_PACKET_TRANSMITTER.vhd (nonexistent) +++ pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/IPV4_PACKET_TRANSMITTER.vhd (revision 2) @@ -0,0 +1,478 @@ +----------------------------------------------------------------------------------------- +-- Copyright (C) 2010 Nikolaos Ch. Alachiotis -- +-- -- +-- Engineer: Nikolaos Ch. Alachiotis -- +-- -- +-- Contact: alachiot@cs.tum.edu -- +-- n.alachiotis@gmail.com -- +-- -- +-- Create Date: 14:45:39 11/27/2009 -- +-- Module Name: IPV4_PACKET_TRANSMITTER -- +-- Target Devices: Virtex 5 FPGAs -- +-- Tool versions: ISE 10.1 -- +-- Description: This component can be used to send IPv4 Ethernet Packets. -- +-- Additional Comments: The look-up table contains the header fields of the IP packet, -- +-- so please keep in mind that you have to reinitialize this LUT. -- +-- -- +----------------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity IPV4_PACKET_TRANSMITTER is + Port ( rst : in STD_LOGIC; + clk_125MHz : in STD_LOGIC; + transmit_start_enable : in STD_LOGIC; + transmit_data_length : in STD_LOGIC_VECTOR (15 downto 0); + usr_data_trans_phase_on : out STD_LOGIC; + transmit_data_input_bus : in STD_LOGIC_VECTOR (7 downto 0); + start_of_frame_O : out STD_LOGIC; + end_of_frame_O : out STD_LOGIC; + source_ready : out STD_LOGIC; + transmit_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0); + + flex_wren: in STD_LOGIC; + flex_wraddr: in STD_LOGIC_VECTOR(5 downto 0); + flex_wrdata: in STD_LOGIC_VECTOR(7 downto 0); + + flex_checksum_baseval: in std_logic_vector(15 downto 0) + ); +end IPV4_PACKET_TRANSMITTER; + +architecture Behavioral of IPV4_PACKET_TRANSMITTER is + + +----------------------------------------------------------------------------------------------------------------------------------------- +----------------------------------------------------------------------------------------------------------------------------------------- +-- IPv4 PACKET STRUCTURE : -- +-- Size | Description | Transmission Order | Position -- +-- ----------------------------------------------------------------------------------------------------------- +-- 6 bytes | Destin MAC Address (PC) | 0 1 2 3 4 5 | LUT -- +-- | X-X-X-X-X-X | | -- +-- | | | -- +-- 6 bytes | Source MAC Address (FPGA) | 6 7 8 9 10 11 | LUT -- +-- | 11111111-11111111-11111111-11111111-... | | -- +-- 2 bytes | Ethernet Type * | 12 13 | LUT -- +-- | (fixed to 00001000-00000000 :=> | | -- +-- | Internet Protocol, Version 4 (IPv4)) | | -- +-- -- Start of IPv4 Packet ** - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- | -- +-- 1 byte | 4 MSBs = Version , 4 LSBs = Header Length | 14 | LUT -- +-- | 0100 0101 | | -- +-- 1 byte | Differentiated Services | 15 | LUT -- +-- | 00000000 | | -- +-- 2 bytes | Total Length | 16 17 | REG -- +-- | 00000000-00100100 (base: 20 + 8 + datalength)| | -- +-- 2 bytes | Identification | 18 19 | LUT -- +-- | 00000000-00000000 | | -- +-- 2 bytes | 3 MSBs = Flags , 13 LSBs = Fragment Offset | 20 21 | LUT -- +-- | 010 - 0000000000000 | | -- +-- 1 byte | Time to Live | 22 | LUT -- +-- | 01000000 | | -- +-- 1 byte | Protocol | 23 | LUT -- +-- | 00010001 | | -- +-- 2 bytes | Header Checksum | 24 25 | REG -- +-- | 10110111 01111101 (base value) | | -- +-- 4 bytes | Source IP Address | 26 27 28 29 | LUT -- +-- | X-X-X-X - FPGA | | -- +-- 4 bytes | Destin IP Address | 30 31 32 33 | LUT -- +-- | X-X-X-X - PC | | -- +-- -- Start of UDP Packet *** - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- | -- +-- 2 bytes | Source Port | 34 35 | LUT -- +-- | X-X | | -- +-- 2 bytes | Destination Port | 36 37 | LUT -- +-- | X-X | | -- +-- 2 bytes | Length | 38 39 | REG -- +-- | 00000000 - 00010000 (8 + # data bytes) | | -- +-- 2 bytes | Checksum | 40 41 | LUT -- +-- | 00000000 - 00000000 | | -- +-- X bytes | Data | 42 .. X | from input -- +-- | | | -- +----------------------------------------------------------------------------------------------------------------------------------------- +----------------------------------------------------------------------------------------------------------------------------------------- + +-- * More details about the Ethernet Type value you can find here: +-- http://en.wikipedia.org/wiki/Ethertype + +-- ** More details about the Internet Protocol, Version 4 (IPv4) you can find here: +-- http://en.wikipedia.org/wiki/IPv4 + +-- *** More details about the Internet Protocol, Version 4 (IPv4) you can find here: +-- http://en.wikipedia.org/wiki/User_Datagram_Protocol + +----------------------------------------------------------------------------------------------------------------------------------------- +----------------------------------------------------------------------------------------------------------------------------------------- + + + +-------------------------------------------------------------------------------------- +-- COMPONENT DECLARATION +-------------------------------------------------------------------------------------- + +component REG_16B_WREN is + Port ( rst : in STD_LOGIC; + clk : in STD_LOGIC; + wren : in STD_LOGIC; + input : in STD_LOGIC_VECTOR (15 downto 0); + output : out STD_LOGIC_VECTOR (15 downto 0)); +end component; + +component IPV4_LUT_INDEXER is + Port ( rst : in STD_LOGIC; + clk : in STD_LOGIC; + transmit_enable : in STD_LOGIC; + LUT_index : out STD_LOGIC_VECTOR (5 downto 0)); +end component; + +--component dist_mem_64x8 is +-- port ( +-- clk : in STD_LOGIC := 'X'; +-- a : in STD_LOGIC_VECTOR ( 5 downto 0 ); +-- qspo : out STD_LOGIC_VECTOR ( 7 downto 0 ) +-- ); +--end component; + +component dist_mem_64x8 is + port ( + clk : in STD_LOGIC := 'X'; + we : in STD_LOGIC := 'X'; + a : in STD_LOGIC_VECTOR ( 5 downto 0 ); + d : in STD_LOGIC_VECTOR ( 7 downto 0 ); + qspo : out STD_LOGIC_VECTOR ( 7 downto 0 ) + ); +end component; + +component OVERRIDE_LUT_CONTROL is + Port ( clk : in STD_LOGIC; + input_addr : in STD_LOGIC_VECTOR (5 downto 0); + sel_total_length_MSBs : out STD_LOGIC; + sel_total_length_LSBs : out STD_LOGIC; + sel_header_checksum_MSBs : out STD_LOGIC; + sel_header_checksum_LSBs : out STD_LOGIC; + sel_length_MSBs : out STD_LOGIC; + sel_length_LSBs : out STD_LOGIC + ); +end component; + +component TARGET_EOF is + Port ( rst : in STD_LOGIC; + clk : in STD_LOGIC; + start : in STD_LOGIC; + total_length_from_reg : in STD_LOGIC_VECTOR(15 downto 0); + eof_O : out STD_LOGIC); +end component; + +component ENABLE_USER_DATA_TRANSMISSION is + Port ( rst : in STD_LOGIC; + clk : in STD_LOGIC; + start_usr_data_trans : in STD_LOGIC; + stop_usr_data_trans : in STD_LOGIC; + usr_data_sel : out STD_LOGIC); +end component; + +component ALLOW_ZERO_UDP_CHECKSUM is + Port ( clk : in STD_LOGIC; + input : in STD_LOGIC; + output_to_readen : out STD_LOGIC; + output_to_datasel : out STD_LOGIC); +end component; + + +-------------------------------------------------------------------------------------- +-- SIGNAL DECLARATION +-------------------------------------------------------------------------------------- + +signal transmit_start_enable_tmp, + sel_total_length_MSBs, + sel_total_length_LSBs, + sel_header_checksum_MSBs, + sel_header_checksum_LSBs, + sel_length_MSBs, + sel_length_LSBs, + lut_out_sel, + source_ready_previous_value, + end_of_frame_O_tmp, + transmit_start_enable_reg, + usr_data_sel_sig, + start_usr_data_read, + start_usr_data_trans : STD_LOGIC; + +signal LUT_addr, + LUT_addr_dual, + sel_rd, + sel_wr: STD_LOGIC_VECTOR(5 downto 0); + +signal transmit_data_input_bus_tmp, + transmit_data_output_bus_tmp, + sel_total_length_MSBs_vec, + sel_total_length_LSBs_vec, + sel_header_checksum_MSBs_vec, + sel_header_checksum_LSBs_vec, + sel_length_MSBs_vec, + sel_length_LSBs_vec, + lut_out_sel_vec, + transmit_data_output_bus_no_usr_data, + usr_data_not_sel_vec, + usr_data_sel_vec : STD_LOGIC_VECTOR(7 downto 0); + +signal transmit_data_length_tmp, + data_length_regout, + tmp_total_length, + tmp_header_checksum, + tmp_header_checksum_baseval, + tmp_length : STD_LOGIC_VECTOR(15 downto 0); + + +begin + +transmit_start_enable_tmp<=transmit_start_enable; + +transmit_data_length_tmp<=transmit_data_length; + +transmit_data_input_bus_tmp<=transmit_data_input_bus; + +---------------------------------------------------------------------------------------------------- +-- start_of_frame_O signal +---------------------------------------------------------------------------------------------------- +-- Description: start_of_frame_O is active low +-- We connect it to the delayed for one clock cycle transmit_start_enable input signal +-- through a NOT gate since transmit_start_enable is active high. + +process(clk_125MHz) +begin +if clk_125MHz'event and clk_125MHz='1' then + transmit_start_enable_reg<=transmit_start_enable_tmp; -- Delay transmit_start_enable one cycle. +end if; +end process; + +start_of_frame_O<=not transmit_start_enable_reg; + +---------------------------------------------------------------------------------------------------- +-- end_of_frame_O signal +---------------------------------------------------------------------------------------------------- +-- Description: end_of_frame_O is active low +-- The TARGET_EOF module targets the last byte of the packet that is being transmitted +-- based on a counter that counts the number of transmitted bytes and a comparator that +-- detects the last byte which is the th byte. + +TARGET_EOF_port_map: TARGET_EOF port map +( + rst =>rst, + clk =>clk_125MHz, + start =>transmit_start_enable_reg, + total_length_from_reg =>tmp_total_length, + eof_O =>end_of_frame_O_tmp +); + +--* The counter in TARGET_EOF starts from -X, where X is the number of bytes transmitted before the +-- IPv4 packet. (MAC addresses + Ethernet Type) + +end_of_frame_O<=end_of_frame_O_tmp; + +---------------------------------------------------------------------------------------------------- +-- source_ready signal +---------------------------------------------------------------------------------------------------- +-- Description: source_ready is active low +-- This signal is idle(high). (based on rst and end_of_frame_O_tmp). +-- This signal is active(low). (based on transmit_start_enable and end_of_frame_O_tmp). + +process(clk_125MHz) +begin +if rst='1' then + source_ready<='1'; + source_ready_previous_value<='1'; +else + if clk_125MHz'event and clk_125MHz='1' then + if (transmit_start_enable_tmp='1' and source_ready_previous_value='1') then + source_ready<='0'; + source_ready_previous_value<='0'; + else + if (end_of_frame_O_tmp='0' and source_ready_previous_value='0') then + source_ready<='1'; + source_ready_previous_value<='1'; + end if; + end if; + end if; +end if; +end process; + +---------------------------------------------------------------------------------------------------- +-- transmit_data_output_bus +---------------------------------------------------------------------------------------------------- +---------------------------------------------------------------------------------------------------- +-- Component Name: REG_16B_WREN +-- Instance Name: NUMBER_OR_DATA_IN_BYTES_REGISTER +-- Description: Register that holds the number of bytes of input data +-- that will be transmitted in the packet. +---------------------------------------------------------------------------------------------------- +NUMBER_OR_DATA_IN_BYTES_REGISTER : REG_16B_WREN port map +( + rst =>rst, + clk =>clk_125MHz, + wren =>transmit_start_enable_tmp, -- The transmit_start_enable input signal can be used as wren. + input =>transmit_data_length_tmp, + output =>data_length_regout +); +---------------------------------------------------------------------------------------------------- + +tmp_total_length<="0000000000011100" + data_length_regout; + + +tmp_header_checksum_baseval<=flex_checksum_baseval; +--tmp_header_checksum_baseval<="1011011101111101"; -- CHANGE VALUE! : You have to change this value! +tmp_header_checksum<=tmp_header_checksum_baseval - data_length_regout; + +tmp_length<="0000000000001000" + data_length_regout; + +---------------------------------------------------------------------------------------------------- + +---------------------------------------------------------------------------------------------------- +-- Component Name: IPV4_LUT_INDEXER +-- Instance Name: IPV4_LUT_INDEXER_port_map +-- Description: When transmit_enable is high for one cycle IPV4_LUT_INDEXER generates the +-- addresses to the LUT that contains the header section of the IP packet. +---------------------------------------------------------------------------------------------------- +IPV4_LUT_INDEXER_port_map : IPV4_LUT_INDEXER port map +( + rst =>rst, + clk =>clk_125MHz, + transmit_enable =>transmit_start_enable_tmp, + LUT_index =>LUT_addr +); +---------------------------------------------------------------------------------------------------- + +---------------------------------------------------------------------------------------------------- +-- Component Name: dist_mem_64x8 +-- Instance Name: LUT_MEM +-- Description: LUT that contains the header section. +---------------------------------------------------------------------------------------------------- +LUT_addr_dual <= (LUT_addr and sel_rd) or (flex_wraddr and sel_wr); + +sel_rd <= (others=> not flex_wren); +sel_wr <= (others=> flex_wren); + +LUT_MEM : dist_mem_64x8 port map +( + --clk =>clk_125MHz, + --a =>LUT_addr_dual, + --qspo =>transmit_data_output_bus_tmp + + clk =>clk_125MHz, + we =>flex_wren, + a => LUT_addr_dual, + d => flex_wrdata, + qspo =>transmit_data_output_bus_tmp + + +); + + + + + + + +---------------------------------------------------------------------------------------------------- + +---------------------------------------------------------------------------------------------------- +-- Component Name: OVERRIDE_LUT_CONTROL +-- Instance Name: OVERRIDE_LUT_CONTROL_port_map +-- Description: Decides whether the output byte will come from the LUT or not. +---------------------------------------------------------------------------------------------------- +OVERRIDE_LUT_CONTROL_port_map : OVERRIDE_LUT_CONTROL port map +( + clk =>clk_125MHz, + input_addr =>LUT_addr, + sel_total_length_MSBs =>sel_total_length_MSBs, + sel_total_length_LSBs =>sel_total_length_LSBs, + sel_header_checksum_MSBs =>sel_header_checksum_MSBs, + sel_header_checksum_LSBs =>sel_header_checksum_LSBs, + sel_length_MSBs =>sel_length_MSBs, + sel_length_LSBs =>sel_length_LSBs +); +---------------------------------------------------------------------------------------------------- + +---------------------------------------------------------------------------------------------------- +-- MUX 7 to 1 +sel_total_length_MSBs_vec<=(others=>sel_total_length_MSBs); +sel_total_length_LSBs_vec<=(others=>sel_total_length_LSBs); +sel_header_checksum_MSBs_vec<=(others=>sel_header_checksum_MSBs); +sel_header_checksum_LSBs_vec<=(others=>sel_header_checksum_LSBs); +sel_length_MSBs_vec<=(others=>sel_length_MSBs); +sel_length_LSBs_vec<=(others=>sel_length_LSBs); +lut_out_sel_vec <= (others=>lut_out_sel); + +lut_out_sel<=(not sel_total_length_MSBs) and (not sel_total_length_LSBs) and + (not sel_header_checksum_MSBs) and (not sel_header_checksum_LSBs) and + (not sel_length_MSBs) and (not sel_length_LSBs); + +-- MUX output +transmit_data_output_bus_no_usr_data<= (transmit_data_output_bus_tmp and lut_out_sel_vec) or + (tmp_total_length(15 downto 8) and sel_total_length_MSBs_vec) or + (tmp_total_length(7 downto 0) and sel_total_length_LSBs_vec) or + (tmp_header_checksum(15 downto 8) and sel_header_checksum_MSBs_vec) or + (tmp_header_checksum(7 downto 0) and sel_header_checksum_LSBs_vec) or + (tmp_length(15 downto 8) and sel_length_MSBs_vec) or + (tmp_length(7 downto 0) and sel_length_LSBs_vec); +---------------------------------------------------------------------------------------------------- + +---------------------------------------------------------------------------------------------------- +-- Component Name: ALLOW_ZERO_UDP_CHECKSUM +-- Instance Name: ALLOW_ZERO_UDP_CHECKSUM_port_map +-- Description: Delays the user data transmition phase in order to transmit two bytes with zero +-- first. +---------------------------------------------------------------------------------------------------- +ALLOW_ZERO_UDP_CHECKSUM_port_map: ALLOW_ZERO_UDP_CHECKSUM port map +( + clk =>clk_125MHz, + input =>sel_length_LSBs, + output_to_readen =>start_usr_data_read, + output_to_datasel =>start_usr_data_trans +); +---------------------------------------------------------------------------------------------------- + +---------------------------------------------------------------------------------------------------- +-- Component Name: ENABLE_USER_DATA_TRANSMISSION +-- Instance Name: ENABLE_USER_DATA_READ_port_map +-- Description: Sets usr_data_trans_phase_on signal one cycle before the transmittion of the +-- first user byte. +---------------------------------------------------------------------------------------------------- +ENABLE_USER_DATA_READ_port_map: ENABLE_USER_DATA_TRANSMISSION port map +( rst =>rst, + clk =>clk_125MHz, + start_usr_data_trans =>start_usr_data_read, + stop_usr_data_trans =>end_of_frame_O_tmp, + usr_data_sel =>usr_data_trans_phase_on +); +---------------------------------------------------------------------------------------------------- + +---------------------------------------------------------------------------------------------------- +-- Component Name: ENABLE_USER_DATA_TRANSMISSION +-- Instance Name: ENABLE_USER_DATA_TRANSMISSION_port_map +-- Description: Sets usr_data_sel_sig signal to select user data for transmittion. +---------------------------------------------------------------------------------------------------- +ENABLE_USER_DATA_TRANSMISSION_port_map: ENABLE_USER_DATA_TRANSMISSION port map +( rst =>rst, + clk =>clk_125MHz, + start_usr_data_trans =>start_usr_data_trans, + stop_usr_data_trans =>end_of_frame_O_tmp, + usr_data_sel =>usr_data_sel_sig +); +---------------------------------------------------------------------------------------------------- + +---------------------------------------------------------------------------------------------------- +-- MUX 2 to 1 +usr_data_not_sel_vec<=(others=>not usr_data_sel_sig); +usr_data_sel_vec<=(others=>usr_data_sel_sig); + +-- MUX output +transmit_data_output_bus<=(transmit_data_output_bus_no_usr_data and usr_data_not_sel_vec) or + (transmit_data_input_bus and usr_data_sel_vec); +---------------------------------------------------------------------------------------------------- + +end Behavioral; Index: pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/wraddr_lut_mem.vhd =================================================================== --- pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/wraddr_lut_mem.vhd (nonexistent) +++ pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/wraddr_lut_mem.vhd (revision 2) @@ -0,0 +1,213 @@ +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version: K.39 +-- \ \ Application: netgen +-- / / Filename: wraddr_lut_mem.vhd +-- /___/ /\ Timestamp: Sat Feb 12 13:38:28 2011 +-- \ \ / \ +-- \___\/\___\ +-- +-- Command : -intstyle ise -w -sim -ofmt vhdl "C:\VERIFICATION PLATFORM\UDP_IP_FLEX\COREGEN\tmp\_cg\wraddr_lut_mem.ngc" "C:\VERIFICATION PLATFORM\UDP_IP_FLEX\COREGEN\tmp\_cg\wraddr_lut_mem.vhd" +-- Device : 5vsx95tff1136-1 +-- Input file : C:/VERIFICATION PLATFORM/UDP_IP_FLEX/COREGEN/tmp/_cg/wraddr_lut_mem.ngc +-- Output file : C:/VERIFICATION PLATFORM/UDP_IP_FLEX/COREGEN/tmp/_cg/wraddr_lut_mem.vhd +-- # of Entities : 1 +-- Design Name : wraddr_lut_mem +-- Xilinx : C:\Xilinx\10.1\ISE +-- +-- Purpose: +-- This VHDL netlist is a verification model and uses simulation +-- primitives which may not represent the true implementation of the +-- device, however the netlist is functionally correct and should not +-- be modified. This file cannot be synthesized and should only be used +-- with supported simulation tools. +-- +-- Reference: +-- Development System Reference Guide, Chapter 23 +-- Synthesis and Simulation Design Guide, Chapter 6 +-- +-------------------------------------------------------------------------------- + + +-- synthesis translate_off +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +use UNISIM.VPKG.ALL; + +entity wraddr_lut_mem is + port ( + clk : in STD_LOGIC := 'X'; + a : in STD_LOGIC_VECTOR ( 5 downto 0 ); + qspo : out STD_LOGIC_VECTOR ( 5 downto 0 ) + ); +end wraddr_lut_mem; + +architecture STRUCTURE of wraddr_lut_mem is + signal N0 : STD_LOGIC; + signal N1 : STD_LOGIC; + signal a_2 : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal qspo_3 : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal BU2_U0_gen_rom_rom_inst_spo_int : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal BU2_qdpo : STD_LOGIC_VECTOR ( 0 downto 0 ); +begin + a_2(5) <= a(5); + a_2(4) <= a(4); + a_2(3) <= a(3); + a_2(2) <= a(2); + a_2(1) <= a(1); + a_2(0) <= a(0); + qspo(5) <= qspo_3(5); + qspo(4) <= qspo_3(4); + qspo(3) <= qspo_3(3); + qspo(2) <= qspo_3(2); + qspo(1) <= qspo_3(1); + qspo(0) <= qspo_3(0); + VCC_0 : VCC + port map ( + P => N1 + ); + GND_1 : GND + port map ( + G => N0 + ); + BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000041 : LUT5 + generic map( + INIT => X"31266226" + ) + port map ( + I0 => a_2(4), + I1 => a_2(5), + I2 => a_2(1), + I3 => a_2(2), + I4 => a_2(3), + O => BU2_U0_gen_rom_rom_inst_spo_int(4) + ); + BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000051 : LUT5 + generic map( + INIT => X"16063662" + ) + port map ( + I0 => a_2(4), + I1 => a_2(5), + I2 => a_2(3), + I3 => a_2(2), + I4 => a_2(1), + O => BU2_U0_gen_rom_rom_inst_spo_int(5) + ); + BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom0000111 : LUT5 + generic map( + INIT => X"31276723" + ) + port map ( + I0 => a_2(4), + I1 => a_2(5), + I2 => a_2(1), + I3 => a_2(2), + I4 => a_2(3), + O => BU2_U0_gen_rom_rom_inst_spo_int(1) + ); + BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000021 : LUT5 + generic map( + INIT => X"13166627" + ) + port map ( + I0 => a_2(4), + I1 => a_2(5), + I2 => a_2(2), + I3 => a_2(1), + I4 => a_2(3), + O => BU2_U0_gen_rom_rom_inst_spo_int(2) + ); + BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000031 : LUT5 + generic map( + INIT => X"32166336" + ) + port map ( + I0 => a_2(4), + I1 => a_2(5), + I2 => a_2(2), + I3 => a_2(1), + I4 => a_2(3), + O => BU2_U0_gen_rom_rom_inst_spo_int(3) + ); + BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000011 : LUT6 + generic map( + INIT => X"1B161F061F043F2C" + ) + port map ( + I0 => a_2(3), + I1 => a_2(4), + I2 => a_2(5), + I3 => a_2(0), + I4 => a_2(1), + I5 => a_2(2), + O => BU2_U0_gen_rom_rom_inst_spo_int(0) + ); + BU2_U0_gen_rom_rom_inst_qspo_int_5 : FD + generic map( + INIT => '0' + ) + port map ( + C => clk, + D => BU2_U0_gen_rom_rom_inst_spo_int(5), + Q => qspo_3(5) + ); + BU2_U0_gen_rom_rom_inst_qspo_int_4 : FD + generic map( + INIT => '0' + ) + port map ( + C => clk, + D => BU2_U0_gen_rom_rom_inst_spo_int(4), + Q => qspo_3(4) + ); + BU2_U0_gen_rom_rom_inst_qspo_int_3 : FD + generic map( + INIT => '0' + ) + port map ( + C => clk, + D => BU2_U0_gen_rom_rom_inst_spo_int(3), + Q => qspo_3(3) + ); + BU2_U0_gen_rom_rom_inst_qspo_int_2 : FD + generic map( + INIT => '0' + ) + port map ( + C => clk, + D => BU2_U0_gen_rom_rom_inst_spo_int(2), + Q => qspo_3(2) + ); + BU2_U0_gen_rom_rom_inst_qspo_int_1 : FD + generic map( + INIT => '0' + ) + port map ( + C => clk, + D => BU2_U0_gen_rom_rom_inst_spo_int(1), + Q => qspo_3(1) + ); + BU2_U0_gen_rom_rom_inst_qspo_int_0 : FD + generic map( + INIT => '0' + ) + port map ( + C => clk, + D => BU2_U0_gen_rom_rom_inst_spo_int(0), + Q => qspo_3(0) + ); + BU2_XST_GND : GND + port map ( + G => BU2_qdpo(0) + ); + +end STRUCTURE; + +-- synthesis translate_on Index: pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/ALLOW_ZERO_UDP_CHECKSUM.vhd =================================================================== --- pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/ALLOW_ZERO_UDP_CHECKSUM.vhd (nonexistent) +++ pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/ALLOW_ZERO_UDP_CHECKSUM.vhd (revision 2) @@ -0,0 +1,60 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 14:46:33 12/04/2009 +-- Design Name: +-- Module Name: ALLOW_ZERO_UDP_CHECKSUM - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity ALLOW_ZERO_UDP_CHECKSUM is + Port ( clk : in STD_LOGIC; + input : in STD_LOGIC; + output_to_readen : out STD_LOGIC; + output_to_datasel : out STD_LOGIC); +end ALLOW_ZERO_UDP_CHECKSUM; + +architecture Behavioral of ALLOW_ZERO_UDP_CHECKSUM is + +signal input_reg : std_logic; + +begin + +process(clk) +begin + if clk'event and clk='1' then + input_reg<=input; + end if; +end process; + +output_to_readen<=input_reg; + +process(clk) +begin + if clk'event and clk='1' then + output_to_datasel<=input_reg; + end if; +end process; + +end Behavioral; + Index: pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/COUNTER_11B_EN_TRANS.vhd =================================================================== --- pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/COUNTER_11B_EN_TRANS.vhd (nonexistent) +++ pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/COUNTER_11B_EN_TRANS.vhd (revision 2) @@ -0,0 +1,58 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 16:16:57 11/30/2009 +-- Design Name: +-- Module Name: COUNTER_11B_EN_TRANS - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity COUNTER_11B_EN_TRANS is + Port ( rst : in STD_LOGIC; + clk : in STD_LOGIC; + count_en : in STD_LOGIC; + value_O : inout STD_LOGIC_VECTOR (10 downto 0)); +end COUNTER_11B_EN_TRANS; + +architecture Behavioral of COUNTER_11B_EN_TRANS is + +begin + +process(clk) +begin +if rst='1' then + value_O<="11111110110"; +else + if clk'event and clk='1' then + if count_en='1' then + value_O<=value_O+"00000000001"; + else + value_O<=value_O; + end if; + end if; +end if; +end process; + + +end Behavioral; + Index: pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/comp_6b_equal.vhd =================================================================== --- pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/comp_6b_equal.vhd (nonexistent) +++ pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/comp_6b_equal.vhd (revision 2) @@ -0,0 +1,141 @@ +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version: K.39 +-- \ \ Application: netgen +-- / / Filename: comp_6b_equal.vhd +-- /___/ /\ Timestamp: Mon Nov 30 14:23:03 2009 +-- \ \ / \ +-- \___\/\___\ +-- +-- Command : -intstyle ise -w -sim -ofmt vhdl C:\PHd_Projects\The_Felsenstein_CoProcessor\COREGEN_Design\tmp\_cg\comp_6b_equal.ngc C:\PHd_Projects\The_Felsenstein_CoProcessor\COREGEN_Design\tmp\_cg\comp_6b_equal.vhd +-- Device : 5vsx95tff1136-1 +-- Input file : C:/PHd_Projects/The_Felsenstein_CoProcessor/COREGEN_Design/tmp/_cg/comp_6b_equal.ngc +-- Output file : C:/PHd_Projects/The_Felsenstein_CoProcessor/COREGEN_Design/tmp/_cg/comp_6b_equal.vhd +-- # of Entities : 1 +-- Design Name : comp_6b_equal +-- Xilinx : C:\Xilinx\10.1\ISE +-- +-- Purpose: +-- This VHDL netlist is a verification model and uses simulation +-- primitives which may not represent the true implementation of the +-- device, however the netlist is functionally correct and should not +-- be modified. This file cannot be synthesized and should only be used +-- with supported simulation tools. +-- +-- Reference: +-- Development System Reference Guide, Chapter 23 +-- Synthesis and Simulation Design Guide, Chapter 6 +-- +-------------------------------------------------------------------------------- + + +-- synthesis translate_off +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +use UNISIM.VPKG.ALL; + +entity comp_6b_equal is + port ( + qa_eq_b : out STD_LOGIC; + clk : in STD_LOGIC := 'X'; + a : in STD_LOGIC_VECTOR ( 5 downto 0 ); + b : in STD_LOGIC_VECTOR ( 5 downto 0 ) + ); +end comp_6b_equal; + +architecture STRUCTURE of comp_6b_equal is + signal BU2_N01 : STD_LOGIC; + signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o85_16 : STD_LOGIC; + + signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_temp_result : STD_LOGIC; + signal BU2_a_ge_b : STD_LOGIC; + signal NLW_VCC_P_UNCONNECTED : STD_LOGIC; + signal NLW_GND_G_UNCONNECTED : STD_LOGIC; + signal a_2 : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal b_3 : STD_LOGIC_VECTOR ( 5 downto 0 ); +begin + a_2(5) <= a(5); + a_2(4) <= a(4); + a_2(3) <= a(3); + a_2(2) <= a(2); + a_2(1) <= a(1); + a_2(0) <= a(0); + b_3(5) <= b(5); + b_3(4) <= b(4); + b_3(3) <= b(3); + b_3(2) <= b(2); + b_3(1) <= b(1); + b_3(0) <= b(0); + VCC_0 : VCC + port map ( + P => NLW_VCC_P_UNCONNECTED + ); + GND_1 : GND + port map ( + G => NLW_GND_G_UNCONNECTED + ); + BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o107 : +LUT6 + generic map( + INIT => X"0000000080200802" + ) + port map ( + I0 => +BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o85_16 +, + I1 => b_3(5), + I2 => b_3(4), + I3 => a_2(5), + I4 => a_2(4), + I5 => BU2_N01, + O => BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_temp_result + ); + BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o107_SW0 : +LUT4 + generic map( + INIT => X"6FF6" + ) + port map ( + I0 => a_2(0), + I1 => b_3(0), + I2 => a_2(3), + I3 => b_3(3), + O => BU2_N01 + ); + BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o85 : +LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => a_2(1), + I1 => b_3(1), + I2 => a_2(2), + I3 => b_3(2), + O => +BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o85_16 + + ); + BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_gen_output_reg_output_reg_fd_output_1 : FD + generic map( + INIT => '0' + ) + port map ( + C => clk, + D => BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_temp_result, + Q => qa_eq_b + ); + BU2_XST_GND : GND + port map ( + G => BU2_a_ge_b + ); + +end STRUCTURE; + +-- synthesis translate_on Index: pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/wraddr_lut_mem.xco =================================================================== --- pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/wraddr_lut_mem.xco (nonexistent) +++ pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/wraddr_lut_mem.xco (revision 2) @@ -0,0 +1,63 @@ +############################################################## +# +# Xilinx Core Generator version K.39 +# Date: Sat Feb 12 12:38:28 2011 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = False +SET asysymbol = False +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = VHDL +SET device = xc5vsx95t +SET devicefamily = virtex5 +SET flowvendor = Other +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = ff1136 +SET removerpms = False +SET simulationfiles = Structural +SET speedgrade = -1 +SET verilogsim = False +SET vhdlsim = True +# END Project Options +# BEGIN Select +SELECT Distributed_Memory_Generator family Xilinx,_Inc. 3.4 +# END Select +# BEGIN Parameters +CSET ce_overrides=ce_overrides_sync_controls +CSET coefficient_file="C:/VERIFICATION PLATFORM/UDP_IP_FLEX/THE_FELSENSTEIN_COPROCESSOR/wraddr_lut.coe" +CSET common_output_ce=false +CSET common_output_clk=false +CSET component_name=wraddr_lut_mem +CSET data_width=6 +CSET default_data=0 +CSET default_data_radix=16 +CSET depth=64 +CSET dual_port_address=non_registered +CSET dual_port_output_clock_enable=false +CSET input_clock_enable=false +CSET input_options=non_registered +CSET memory_type=rom +CSET output_options=registered +CSET pipeline_stages=0 +CSET qualify_we_with_i_ce=false +CSET reset_qdpo=false +CSET reset_qspo=false +CSET single_port_output_clock_enable=false +CSET sync_reset_qdpo=false +CSET sync_reset_qspo=false +# END Parameters +GENERATE +# CRC: 5a000833 + Index: pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/comp_11b_equal.ngc =================================================================== --- pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/comp_11b_equal.ngc (nonexistent) +++ pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/comp_11b_equal.ngc (revision 2) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4e 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1e=:j1v;k50;0xZ34<500=>6*;c;11?xu1l3:1>vP91:?:>37<,=i1?95rs7a94?4|V?:014490:&7g?523ty=n7>52z\6b>;>2"3k39<7p}99;296~X2l27268j4$5a97==z{?21<7n636:4`8 1e=:;1v;850;0xZ0?<500>56*;c;00?xu1;3:1>vP:8:?:>0><,=i1>95rs9694?4|V>3014489:&7g?423ty3h7>52z\;5>;>21;0(9m5279~w=e=838pR5>4=88;4>"3k38<7p}7b;296~X0n2726:h4$5a96==z{1k1<7vP8b:?:>2d<,=i1>i5rs9494?4|V>k01448a:&7g?4b3ty397>52z\4<>;>2>20(9m52g9~w=4=838pR:94=8843>"3k39;7p}60;296~X>827264>4$5a974=z{0=1<7?2.?o7=<;|m==<72;qC8i5rn8;94?4|@=n0qc7n:181M2c3td2n7>52zJ7`>{i1j0;6?uG4e9~j5<5sA>o7p`6f;296~N3l2wem=4?:3yK0a=zfh;1<77}OvF;d:me=<72;qC8i5rn`;94?4|@=n0qcon:181M2c3tdjn7>52zJ7`>{iij0;6?uG4e9~jdb=838pD9j4}ocf>5<5sA>o7p`nf;296~N3l2we;l4?:0yK0a=zf091<7?tH5f8yk?3290:wE:k;|l:1?6=9rB?h6sa9783>4}Oj0 + + allow_match<='0'; + + next_st<=idle_state; + +when idle_state => + + allow_match<='0'; + + if sof='0' then + next_st <= header_state; + else + next_st <= idle_state; + end if; + +when header_state => + + if vld_i='1' then + allow_match<='1'; + next_st <= rst_state; + else + allow_match<='0'; + next_st <= header_state; + end if; + +end case; +end process; + +allow_match_v <=(others=>allow_match); +val_i_to_match <= val_i and allow_match_v; + +process(clk) +begin +if clk'event and clk='1' then + if val_i_to_match = cmd_to_match then + cmd_match <='1'; + else + cmd_match <='0'; + end if; +end if; +end process; + +end Behavioral; + Index: pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/TARGET_EOF.vhd =================================================================== --- pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/TARGET_EOF.vhd (nonexistent) +++ pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/TARGET_EOF.vhd (revision 2) @@ -0,0 +1,106 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 16:22:56 11/30/2009 +-- Design Name: +-- Module Name: TARGET_EOF - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity TARGET_EOF is + Port ( rst : in STD_LOGIC; + clk : in STD_LOGIC; + start : in STD_LOGIC; + total_length_from_reg : in STD_LOGIC_VECTOR(15 downto 0); + eof_O : out STD_LOGIC); +end TARGET_EOF; + +architecture Behavioral of TARGET_EOF is + +signal count_end : std_logic:='0'; +signal count_en_sig : std_logic:='0'; +signal rst_counter : std_logic:='0'; + +component COUNTER_11B_EN_TRANS is + Port ( rst : in STD_LOGIC; + clk : in STD_LOGIC; + count_en : in STD_LOGIC; + value_O : inout STD_LOGIC_VECTOR (10 downto 0)); +end component; + +signal value_O_tmp : std_logic_vector(10 downto 0); + +component comp_11b_equal is + port ( + qa_eq_b : out STD_LOGIC; + clk : in STD_LOGIC := 'X'; + a : in STD_LOGIC_VECTOR ( 10 downto 0 ); + b : in STD_LOGIC_VECTOR ( 10 downto 0 ) + ); +end component; + +signal last_byte,last_byte_reg_in,last_byte_reg_out : std_logic; + +begin + +process(clk) +begin +if (rst='1' or count_end='1') then + count_en_sig<='0'; + rst_counter<='1'; +else + rst_counter<='0'; + if clk'event and clk='1' then + if (start='1' and count_en_sig='0') then + count_en_sig<='1'; + end if; + end if; +end if; +end process; + + +COUNT_TRANFERED_BYTES : COUNTER_11B_EN_TRANS port map +( rst =>rst_counter, + clk =>clk, + count_en => count_en_sig, + value_O =>value_O_tmp +); + +COMP_TO_TARGET_LAST_BYTE : comp_11b_equal port map +( + qa_eq_b =>last_byte_reg_in, + clk =>clk, + a =>value_O_tmp, + b =>total_length_from_reg(10 downto 0) +); + +process(clk) +begin +if clk'event and clk='1' then + last_byte_reg_out<=last_byte_reg_in; +end if; +end process; +eof_O<=not last_byte_reg_out; +count_end<=last_byte_reg_out; +end Behavioral; + Index: pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/dist_mem_64x8.ngc =================================================================== --- pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/dist_mem_64x8.ngc (nonexistent) +++ pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/dist_mem_64x8.ngc (revision 2) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4e +$d;x5d=#Zl|bdaa:!3-522):'?%8#?/$09355=789:;<=>?0123456682:;<=>?0123457789;;7=>?0123456799:;<<>40123456789::8=>?1193456789:;<8>;01224>6789:;<=>?8123457739:;<=>?012;41678:1:"=h45wq{=0ran8;8: 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27=;11v4;50;0xZ=b<58314i5+7080=>{t0j0;6?uQ8b9>5<9;g;?!162:h0q~j;:181[ee34;26nl4$6397f=z{m81<7"0939n7p}k0;296~Xd027:57m7;%52>6`2j=0(:?5419~wfc=838pRn84=0;9g3=#?80?=6s|ce83>7}Yk<16=44l5:&45?253tyho7>52z\`0>;613i?7)9>:518yxh68>0;65<5sA=97p`>0c83>7}O?;1vb<>l:181M153td:5<5sA=97p`>1283>7}O?;1vb0;6?uG739~j47?2909wE9=;|l25<<72;qC;?5G479~j47f2909wE9=;I65?xh69k0;6?uG739K03=zf8;h6=4={I51?M213td:=i4?:3yK37=O=7p`>1g83>7}O?;1C8;5rn003>5<5sA=97E:9;|lf6safg83>4}O?;1vb<>?:182M153td:<<4?:0yK37=zf8:96=4>{I51?xh68:0;65<6sA=97psr}AB@4232ml::8ml8|BCF~6zHIZpqMN \ No newline at end of file Index: pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/REG_16B_WREN.vhd =================================================================== --- pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/REG_16B_WREN.vhd (nonexistent) +++ pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/REG_16B_WREN.vhd (revision 2) @@ -0,0 +1,56 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 21:15:16 11/27/2009 +-- Design Name: +-- Module Name: REG_16B_WREN - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: 16bit wide Register with write enable option. +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity REG_16B_WREN is + Port ( rst : in STD_LOGIC; + clk : in STD_LOGIC; + wren : in STD_LOGIC; + input : in STD_LOGIC_VECTOR (15 downto 0); + output : out STD_LOGIC_VECTOR (15 downto 0)); +end REG_16B_WREN; + +architecture Behavioral of REG_16B_WREN is + +begin + +process(clk) +begin +if rst='1' then + output<="0000000000000000"; +else +if clk'event and clk='1' then + if wren='1' then + output<=input; + end if; +end if; +end if; +end process; + +end Behavioral; + Index: pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/IPV4_LUT_INDEXER.vhd =================================================================== --- pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/IPV4_LUT_INDEXER.vhd (nonexistent) +++ pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/IPV4_LUT_INDEXER.vhd (revision 2) @@ -0,0 +1,110 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 22:11:55 11/27/2009 +-- Design Name: +-- Module Name: IPV4_LUT_INDEXER - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity IPV4_LUT_INDEXER is + Port ( rst : in STD_LOGIC; + clk : in STD_LOGIC; + transmit_enable : in STD_LOGIC; + LUT_index : out STD_LOGIC_VECTOR (5 downto 0)); +end IPV4_LUT_INDEXER; + +architecture Behavioral of IPV4_LUT_INDEXER is + +component dist_mem_64x8 is + port ( + clk : in STD_LOGIC := 'X'; + a : in STD_LOGIC_VECTOR ( 5 downto 0 ); + qspo : out STD_LOGIC_VECTOR ( 7 downto 0 ) + ); +end component; + +component COUNTER_6B_LUT_FIFO_MODE is + Port ( rst : in STD_LOGIC; + clk : in STD_LOGIC; + funct_sel : in STD_LOGIC; -- 0 for lut addressing, 1 for fifo addressing -- only LUT support is used + count_en : in STD_LOGIC; + value_O : inout STD_LOGIC_VECTOR (5 downto 0)); +end component; + +component comp_6b_equal is + port ( + qa_eq_b : out STD_LOGIC; + clk : in STD_LOGIC := 'X'; + a : in STD_LOGIC_VECTOR ( 5 downto 0 ); + b : in STD_LOGIC_VECTOR ( 5 downto 0 ) + ); +end component; + +signal count_en_sig , count_end , rst_counter: std_logic :='0'; +signal count_val: std_logic_Vector(5 downto 0):=(others=>'0'); +signal count_en_sig_comb : std_logic; +constant lut_upper_address :std_logic_vector(5 downto 0):="100110"; -- position 38 + +begin + +process(clk) +begin +if (rst='1' or count_end='1') then + count_en_sig<='0'; + rst_counter<='1'; +else + rst_counter<='0'; + if clk'event and clk='1' then + if (transmit_enable='1' and count_en_sig='0') then + count_en_sig<='1'; + end if; + end if; +end if; +end process; + +LUT_END_CHECK : comp_6b_equal port map ( +qa_eq_b =>count_end, + clk =>clk, + a =>count_val, + b =>lut_upper_address + +); + +count_en_sig_comb <=count_en_sig or transmit_enable; + + + +LUT_INDEXER_MODULE : COUNTER_6B_LUT_FIFO_MODE port map ( + rst => rst_counter, + clk => clk, + funct_sel =>'0', -- for now only one function is supported + count_en =>count_en_sig_comb, + value_O =>count_val +); + +LUT_index<=count_val; + + +end Behavioral; + Index: pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/comp_6b_equal.xco =================================================================== --- pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/comp_6b_equal.xco (nonexistent) +++ pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/comp_6b_equal.xco (revision 2) @@ -0,0 +1,59 @@ +############################################################## +# +# Xilinx Core Generator version K.39 +# Date: Mon Nov 30 13:23:03 2009 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = False +SET asysymbol = False +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = VHDL +SET device = xc5vsx95t +SET devicefamily = virtex5 +SET flowvendor = Other +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = ff1136 +SET removerpms = False +SET simulationfiles = Structural +SET speedgrade = -1 +SET verilogsim = False +SET vhdlsim = True +# END Project Options +# BEGIN Select +SELECT Comparator family Xilinx,_Inc. 9.0 +# END Select +# BEGIN Parameters +CSET aclr=false +CSET ainitval=0 +CSET aset=false +CSET ce=false +CSET cepriority=Sync_Overrides_CE +CSET component_name=comp_6b_equal +CSET constantbport=false +CSET constantbportvalue=0000000000000000 +CSET datatype=Unsigned +CSET nonregisteredoutput=false +CSET operation=eq +CSET pipelinestages=0 +CSET radix=2 +CSET registeredoutput=true +CSET sclr=false +CSET sset=false +CSET syncctrlpriority=Reset_Overrides_Set +CSET width=6 +# END Parameters +GENERATE +# CRC: 74b0a9bd + Index: pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/ENABLE_USER_DATA_TRANSMISSION.vhd =================================================================== --- pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/ENABLE_USER_DATA_TRANSMISSION.vhd (nonexistent) +++ pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/ENABLE_USER_DATA_TRANSMISSION.vhd (revision 2) @@ -0,0 +1,64 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 12:05:48 12/04/2009 +-- Design Name: +-- Module Name: ENABLE_USER_DATA_TRANSMISSION - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity ENABLE_USER_DATA_TRANSMISSION is + Port ( rst : in STD_LOGIC; + clk : in STD_LOGIC; + start_usr_data_trans : in STD_LOGIC; + stop_usr_data_trans : in STD_LOGIC; + usr_data_sel : out STD_LOGIC); +end ENABLE_USER_DATA_TRANSMISSION; + +architecture Behavioral of ENABLE_USER_DATA_TRANSMISSION is + +signal usr_data_sel_prev : std_logic :='0'; + +begin + +process(clk) +begin +if rst='1' then + usr_data_sel<='0'; + usr_data_sel_prev<='0'; +else + if clk'event and clk='1' then + if (start_usr_data_trans='1' and usr_data_sel_prev='0') then + usr_data_sel<='1'; + usr_data_sel_prev<='1'; + end if; + if (stop_usr_data_trans='0' and usr_data_sel_prev='1') then -- stop_usr_data_trans is active low + usr_data_sel<='0'; + usr_data_sel_prev<='0'; + end if; + end if; +end if; +end process; + +end Behavioral; + Index: pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/comp_11b_equal.vhd =================================================================== --- pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/comp_11b_equal.vhd (nonexistent) +++ pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/comp_11b_equal.vhd (revision 2) @@ -0,0 +1,196 @@ +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version: K.39 +-- \ \ Application: netgen +-- / / Filename: comp_11b_equal.vhd +-- /___/ /\ Timestamp: Mon Nov 30 16:37:25 2009 +-- \ \ / \ +-- \___\/\___\ +-- +-- Command : -intstyle ise -w -sim -ofmt vhdl C:\PHd_Projects\The_Felsenstein_CoProcessor\COREGEN_Design\tmp\_cg\comp_11b_equal.ngc C:\PHd_Projects\The_Felsenstein_CoProcessor\COREGEN_Design\tmp\_cg\comp_11b_equal.vhd +-- Device : 5vsx95tff1136-1 +-- Input file : C:/PHd_Projects/The_Felsenstein_CoProcessor/COREGEN_Design/tmp/_cg/comp_11b_equal.ngc +-- Output file : C:/PHd_Projects/The_Felsenstein_CoProcessor/COREGEN_Design/tmp/_cg/comp_11b_equal.vhd +-- # of Entities : 1 +-- Design Name : comp_11b_equal +-- Xilinx : C:\Xilinx\10.1\ISE +-- +-- Purpose: +-- This VHDL netlist is a verification model and uses simulation +-- primitives which may not represent the true implementation of the +-- device, however the netlist is functionally correct and should not +-- be modified. This file cannot be synthesized and should only be used +-- with supported simulation tools. +-- +-- Reference: +-- Development System Reference Guide, Chapter 23 +-- Synthesis and Simulation Design Guide, Chapter 6 +-- +-------------------------------------------------------------------------------- + + +-- synthesis translate_off +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +use UNISIM.VPKG.ALL; + +entity comp_11b_equal is + port ( + qa_eq_b : out STD_LOGIC; + clk : in STD_LOGIC := 'X'; + a : in STD_LOGIC_VECTOR ( 10 downto 0 ); + b : in STD_LOGIC_VECTOR ( 10 downto 0 ) + ); +end comp_11b_equal; + +architecture STRUCTURE of comp_11b_equal is + signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o189_29 : STD_LOGIC; + + signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o139_28 : STD_LOGIC; + + signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o62_27 : STD_LOGIC; + + signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o26_26 : STD_LOGIC; + + signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_temp_result : STD_LOGIC; + signal BU2_a_ge_b : STD_LOGIC; + signal NLW_VCC_P_UNCONNECTED : STD_LOGIC; + signal NLW_GND_G_UNCONNECTED : STD_LOGIC; + signal a_2 : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal b_3 : STD_LOGIC_VECTOR ( 10 downto 0 ); +begin + a_2(10) <= a(10); + a_2(9) <= a(9); + a_2(8) <= a(8); + a_2(7) <= a(7); + a_2(6) <= a(6); + a_2(5) <= a(5); + a_2(4) <= a(4); + a_2(3) <= a(3); + a_2(2) <= a(2); + a_2(1) <= a(1); + a_2(0) <= a(0); + b_3(10) <= b(10); + b_3(9) <= b(9); + b_3(8) <= b(8); + b_3(7) <= b(7); + b_3(6) <= b(6); + b_3(5) <= b(5); + b_3(4) <= b(4); + b_3(3) <= b(3); + b_3(2) <= b(2); + b_3(1) <= b(1); + b_3(0) <= b(0); + VCC_0 : VCC + port map ( + P => NLW_VCC_P_UNCONNECTED + ); + GND_1 : GND + port map ( + G => NLW_GND_G_UNCONNECTED + ); + BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o206 : +LUT6 + generic map( + INIT => X"9000000000000000" + ) + port map ( + I0 => a_2(2), + I1 => b_3(2), + I2 => +BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o26_26 +, + I3 => +BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o62_27 +, + I4 => +BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o139_28 +, + I5 => +BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o189_29 +, + O => BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_temp_result + ); + BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o189 : +LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => a_2(5), + I1 => b_3(5), + I2 => a_2(6), + I3 => b_3(6), + I4 => a_2(7), + I5 => b_3(7), + O => +BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o189_29 + + ); + BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o139 : +LUT6 + generic map( + INIT => X"9009000000009009" + ) + port map ( + I0 => a_2(8), + I1 => b_3(8), + I2 => a_2(9), + I3 => b_3(9), + I4 => a_2(10), + I5 => b_3(10), + O => +BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o139_28 + + ); + BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o62 : +LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => a_2(3), + I1 => b_3(3), + I2 => a_2(4), + I3 => b_3(4), + O => +BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o62_27 + + ); + BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o26 : +LUT4 + generic map( + INIT => X"9009" + ) + port map ( + I0 => a_2(0), + I1 => b_3(0), + I2 => a_2(1), + I3 => b_3(1), + O => +BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o26_26 + + ); + BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_gen_output_reg_output_reg_fd_output_1 : FD + generic map( + INIT => '0' + ) + port map ( + C => clk, + D => BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_temp_result, + Q => qa_eq_b + ); + BU2_XST_GND : GND + port map ( + G => BU2_a_ge_b + ); + +end STRUCTURE; + +-- synthesis translate_on Index: pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/UDP_IP_Core.vhd =================================================================== --- pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/UDP_IP_Core.vhd (nonexistent) +++ pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/UDP_IP_Core.vhd (revision 2) @@ -0,0 +1,188 @@ +----------------------------------------------------------------------------------------- +-- Copyright (C) 2010 Nikolaos Ch. Alachiotis -- +-- -- +-- Engineer: Nikolaos Ch. Alachiotis -- +-- -- +-- Contact: n.alachiotis@gmail.com -- +-- -- +-- Create Date: 04/03/2011 -- +-- Module Name: UDP_IP_Core -- +-- Target Devices: Virtex 5 FPGAs -- +-- Tool versions: ISE 10.1 -- +-- Description: This component can be used to transmit and receive UDP/IP -- +-- Ethernet Packets (IPv4). -- +-- Additional Comments: The core has been area-optimized and is suitable for direct -- +-- PC-FPGA communication at Gigabit speed. -- +-- -- +----------------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity UDP_IP_Core is + Port ( rst : in STD_LOGIC; -- active-high + clk_125MHz : in STD_LOGIC; + + -- Transmit signals + transmit_start_enable : in STD_LOGIC; + transmit_data_length : in STD_LOGIC_VECTOR (15 downto 0); + usr_data_trans_phase_on : out STD_LOGIC; + transmit_data_input_bus : in STD_LOGIC_VECTOR (7 downto 0); + start_of_frame_O : out STD_LOGIC; + end_of_frame_O : out STD_LOGIC; + source_ready : out STD_LOGIC; + transmit_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0); + + --Receive Signals + rx_sof : in STD_LOGIC; + rx_eof : in STD_LOGIC; + input_bus : in STD_LOGIC_VECTOR(7 downto 0); + valid_out_usr_data : out STD_LOGIC; + usr_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0); + + + locked : out STD_LOGIC + ); +end UDP_IP_Core; + +architecture Behavioral of UDP_IP_Core is + +component IPV4_PACKET_TRANSMITTER is + Port ( rst : in STD_LOGIC; + clk_125MHz : in STD_LOGIC; + transmit_start_enable : in STD_LOGIC; + transmit_data_length : in STD_LOGIC_VECTOR (15 downto 0); + usr_data_trans_phase_on : out STD_LOGIC; + transmit_data_input_bus : in STD_LOGIC_VECTOR (7 downto 0); + start_of_frame_O : out STD_LOGIC; + end_of_frame_O : out STD_LOGIC; + source_ready : out STD_LOGIC; + transmit_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0); + + flex_wren: in STD_LOGIC; + flex_wraddr: in STD_LOGIC_VECTOR(5 downto 0); + flex_wrdata: in STD_LOGIC_VECTOR(7 downto 0); + + flex_checksum_baseval: in std_logic_vector(15 downto 0) + ); +end component; + +component IPv4_PACKET_RECEIVER is + Port ( rst : in STD_LOGIC; + clk_125Mhz : in STD_LOGIC; + rx_sof : in STD_LOGIC; + rx_eof : in STD_LOGIC; + input_bus : in STD_LOGIC_VECTOR(7 downto 0); + valid_out_usr_data : out STD_LOGIC; + usr_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0)); +end component; + +component FLEX_CONTROL is + Port ( rst : in STD_LOGIC; + clk : in STD_LOGIC; + r_sof : in STD_LOGIC; + r_usrvld : in STD_LOGIC; + r_data : in STD_LOGIC_VECTOR (7 downto 0); + r_usrdata: in STD_LOGIC_VECTOR (7 downto 0); + r_eof : in STD_LOGIC; + l_wren : out STD_LOGIC; + l_addr : out STD_LOGIC_VECTOR (5 downto 0); + l_data : out STD_LOGIC_VECTOR (7 downto 0); + checksum_baseval : out STD_LOGIC_VECTOR(15 downto 0); + locked : out STD_LOGIC +); +end component; + +signal valid_out_usr_data_t : STD_LOGIC; +signal usr_data_output_bus_t : STD_LOGIC_VECTOR (7 downto 0); + +signal flex_wren: STD_LOGIC; +signal flex_wraddr: STD_LOGIC_VECTOR(5 downto 0); +signal flex_wrdata: STD_LOGIC_VECTOR(7 downto 0); +signal flex_checksum_baseval: std_logic_vector(15 downto 0); + +signal core_rst: std_logic; + +component MATCH_CMD is + Port ( rst : in STD_LOGIC; + clk : in STD_LOGIC; + sof : in STD_LOGIC; + vld_i : in STD_LOGIC; + val_i : in STD_LOGIC_VECTOR (7 downto 0); + cmd_to_match : in STD_LOGIC_VECTOR(7 downto 0); + cmd_match : out STD_LOGIC); +end component; + +begin + +MATCH_RST_CODE: MATCH_CMD Port Map +( rst => rst, + clk => clk_125MHz, + sof => rx_sof, + vld_i => valid_out_usr_data_t, + val_i => usr_data_output_bus_t, + cmd_to_match => "11111111", + cmd_match => core_rst + ); + +IPV4_PACKET_TRANSMITTER_port_map: IPV4_PACKET_TRANSMITTER + Port Map + ( rst => core_rst, + clk_125MHz => clk_125MHz, + transmit_start_enable => transmit_start_enable, + transmit_data_length => transmit_data_length, + usr_data_trans_phase_on => usr_data_trans_phase_on, + transmit_data_input_bus => transmit_data_input_bus, + start_of_frame_O => start_of_frame_O, + end_of_frame_O => end_of_frame_O, + source_ready => source_ready, + transmit_data_output_bus => transmit_data_output_bus, + flex_wren => flex_wren, + flex_wraddr => flex_wraddr, + flex_wrdata => flex_wrdata, + flex_checksum_baseval => flex_checksum_baseval + ); + + +IPv4_PACKET_RECEIVER_port_map: IPv4_PACKET_RECEIVER + Port Map + ( rst => core_rst, + clk_125Mhz => clk_125Mhz, + rx_sof => rx_sof, + rx_eof => rx_eof, + input_bus => input_bus, + valid_out_usr_data => valid_out_usr_data_t, + usr_data_output_bus => usr_data_output_bus_t + ); + + +valid_out_usr_data <= valid_out_usr_data_t; +usr_data_output_bus <= usr_data_output_bus_t; + +FLEX_CONTROL_port_map: FLEX_CONTROL + Port Map + ( rst => core_rst, + clk => clk_125Mhz, + r_sof => rx_sof, + r_usrvld => valid_out_usr_data_t, + r_data => input_bus, + r_usrdata => usr_data_output_bus_t, + r_eof => rx_eof, + l_wren => flex_wren, + l_addr => flex_wraddr, + l_data => flex_wrdata, + checksum_baseval => flex_checksum_baseval, + locked => locked + ); + + +end Behavioral; + Index: pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/dist_mem_64x8.vhd =================================================================== --- pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/dist_mem_64x8.vhd (nonexistent) +++ pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/dist_mem_64x8.vhd (revision 2) @@ -0,0 +1,299 @@ +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version: K.39 +-- \ \ Application: netgen +-- / / Filename: dist_mem_64x8.vhd +-- /___/ /\ Timestamp: Sat Feb 12 17:26:42 2011 +-- \ \ / \ +-- \___\/\___\ +-- +-- Command : -intstyle ise -w -sim -ofmt vhdl "C:\VERIFICATION PLATFORM\UDP_IP_FLEX\COREGEN\tmp\_cg\dist_mem_64x8.ngc" "C:\VERIFICATION PLATFORM\UDP_IP_FLEX\COREGEN\tmp\_cg\dist_mem_64x8.vhd" +-- Device : 5vsx95tff1136-1 +-- Input file : C:/VERIFICATION PLATFORM/UDP_IP_FLEX/COREGEN/tmp/_cg/dist_mem_64x8.ngc +-- Output file : C:/VERIFICATION PLATFORM/UDP_IP_FLEX/COREGEN/tmp/_cg/dist_mem_64x8.vhd +-- # of Entities : 1 +-- Design Name : dist_mem_64x8 +-- Xilinx : C:\Xilinx\10.1\ISE +-- +-- Purpose: +-- This VHDL netlist is a verification model and uses simulation +-- primitives which may not represent the true implementation of the +-- device, however the netlist is functionally correct and should not +-- be modified. This file cannot be synthesized and should only be used +-- with supported simulation tools. +-- +-- Reference: +-- Development System Reference Guide, Chapter 23 +-- Synthesis and Simulation Design Guide, Chapter 6 +-- +-------------------------------------------------------------------------------- + + +-- synthesis translate_off +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +use UNISIM.VPKG.ALL; + +entity dist_mem_64x8 is + port ( + clk : in STD_LOGIC := 'X'; + we : in STD_LOGIC := 'X'; + a : in STD_LOGIC_VECTOR ( 5 downto 0 ); + d : in STD_LOGIC_VECTOR ( 7 downto 0 ); + qspo : out STD_LOGIC_VECTOR ( 7 downto 0 ) + ); +end dist_mem_64x8; + +architecture STRUCTURE of dist_mem_64x8 is + signal N0 : STD_LOGIC; + signal N1 : STD_LOGIC; + signal a_2 : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal d_3 : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal qspo_4 : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal BU2_U0_gen_sp_ram_spram_inst_spo_int : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal BU2_qdpo : STD_LOGIC_VECTOR ( 0 downto 0 ); +begin + a_2(5) <= a(5); + a_2(4) <= a(4); + a_2(3) <= a(3); + a_2(2) <= a(2); + a_2(1) <= a(1); + a_2(0) <= a(0); + d_3(7) <= d(7); + d_3(6) <= d(6); + d_3(5) <= d(5); + d_3(4) <= d(4); + d_3(3) <= d(3); + d_3(2) <= d(2); + d_3(1) <= d(1); + d_3(0) <= d(0); + qspo(7) <= qspo_4(7); + qspo(6) <= qspo_4(6); + qspo(5) <= qspo_4(5); + qspo(4) <= qspo_4(4); + qspo(3) <= qspo_4(3); + qspo(2) <= qspo_4(2); + qspo(1) <= qspo_4(1); + qspo(0) <= qspo_4(0); + VCC_0 : VCC + port map ( + P => N1 + ); + GND_1 : GND + port map ( + G => N0 + ); + BU2_U0_gen_sp_ram_spram_inst_Mram_ram8 : RAM64X1S + generic map( + INIT => X"0000000000000000" + ) + port map ( + A0 => a_2(0), + A1 => a_2(1), + A2 => a_2(2), + A3 => a_2(3), + A4 => a_2(4), + A5 => a_2(5), + D => d_3(7), + WCLK => clk, + WE => we, + O => BU2_U0_gen_sp_ram_spram_inst_spo_int(7) + ); + BU2_U0_gen_sp_ram_spram_inst_Mram_ram7 : RAM64X1S + generic map( + INIT => X"0000000000504000" + ) + port map ( + A0 => a_2(0), + A1 => a_2(1), + A2 => a_2(2), + A3 => a_2(3), + A4 => a_2(4), + A5 => a_2(5), + D => d_3(6), + WCLK => clk, + WE => we, + O => BU2_U0_gen_sp_ram_spram_inst_spo_int(6) + ); + BU2_U0_gen_sp_ram_spram_inst_Mram_ram6 : RAM64X1S + generic map( + INIT => X"0000000000010000" + ) + port map ( + A0 => a_2(0), + A1 => a_2(1), + A2 => a_2(2), + A3 => a_2(3), + A4 => a_2(4), + A5 => a_2(5), + D => d_3(5), + WCLK => clk, + WE => we, + O => BU2_U0_gen_sp_ram_spram_inst_spo_int(5) + ); + BU2_U0_gen_sp_ram_spram_inst_Mram_ram5 : RAM64X1S + generic map( + INIT => X"0000000000800000" + ) + port map ( + A0 => a_2(0), + A1 => a_2(1), + A2 => a_2(2), + A3 => a_2(3), + A4 => a_2(4), + A5 => a_2(5), + D => d_3(4), + WCLK => clk, + WE => we, + O => BU2_U0_gen_sp_ram_spram_inst_spo_int(4) + ); + BU2_U0_gen_sp_ram_spram_inst_Mram_ram4 : RAM64X1S + generic map( + INIT => X"0000000000001000" + ) + port map ( + A0 => a_2(0), + A1 => a_2(1), + A2 => a_2(2), + A3 => a_2(3), + A4 => a_2(4), + A5 => a_2(5), + D => d_3(3), + WCLK => clk, + WE => we, + O => BU2_U0_gen_sp_ram_spram_inst_spo_int(3) + ); + BU2_U0_gen_sp_ram_spram_inst_Mram_ram3 : RAM64X1S + generic map( + INIT => X"0000000000014000" + ) + port map ( + A0 => a_2(0), + A1 => a_2(1), + A2 => a_2(2), + A3 => a_2(3), + A4 => a_2(4), + A5 => a_2(5), + D => d_3(2), + WCLK => clk, + WE => we, + O => BU2_U0_gen_sp_ram_spram_inst_spo_int(2) + ); + BU2_U0_gen_sp_ram_spram_inst_Mram_ram2 : RAM64X1S + generic map( + INIT => X"0000000000000000" + ) + port map ( + A0 => a_2(0), + A1 => a_2(1), + A2 => a_2(2), + A3 => a_2(3), + A4 => a_2(4), + A5 => a_2(5), + D => d_3(1), + WCLK => clk, + WE => we, + O => BU2_U0_gen_sp_ram_spram_inst_spo_int(1) + ); + BU2_U0_gen_sp_ram_spram_inst_Mram_ram1 : RAM64X1S + generic map( + INIT => X"0000000000804000" + ) + port map ( + A0 => a_2(0), + A1 => a_2(1), + A2 => a_2(2), + A3 => a_2(3), + A4 => a_2(4), + A5 => a_2(5), + D => d_3(0), + WCLK => clk, + WE => we, + O => BU2_U0_gen_sp_ram_spram_inst_spo_int(0) + ); + BU2_U0_gen_sp_ram_spram_inst_qspo_int_7 : FD + generic map( + INIT => '0' + ) + port map ( + C => clk, + D => BU2_U0_gen_sp_ram_spram_inst_spo_int(7), + Q => qspo_4(7) + ); + BU2_U0_gen_sp_ram_spram_inst_qspo_int_6 : FD + generic map( + INIT => '0' + ) + port map ( + C => clk, + D => BU2_U0_gen_sp_ram_spram_inst_spo_int(6), + Q => qspo_4(6) + ); + BU2_U0_gen_sp_ram_spram_inst_qspo_int_5 : FD + generic map( + INIT => '0' + ) + port map ( + C => clk, + D => BU2_U0_gen_sp_ram_spram_inst_spo_int(5), + Q => qspo_4(5) + ); + BU2_U0_gen_sp_ram_spram_inst_qspo_int_4 : FD + generic map( + INIT => '0' + ) + port map ( + C => clk, + D => BU2_U0_gen_sp_ram_spram_inst_spo_int(4), + Q => qspo_4(4) + ); + BU2_U0_gen_sp_ram_spram_inst_qspo_int_3 : FD + generic map( + INIT => '0' + ) + port map ( + C => clk, + D => BU2_U0_gen_sp_ram_spram_inst_spo_int(3), + Q => qspo_4(3) + ); + BU2_U0_gen_sp_ram_spram_inst_qspo_int_2 : FD + generic map( + INIT => '0' + ) + port map ( + C => clk, + D => BU2_U0_gen_sp_ram_spram_inst_spo_int(2), + Q => qspo_4(2) + ); + BU2_U0_gen_sp_ram_spram_inst_qspo_int_1 : FD + generic map( + INIT => '0' + ) + port map ( + C => clk, + D => BU2_U0_gen_sp_ram_spram_inst_spo_int(1), + Q => qspo_4(1) + ); + BU2_U0_gen_sp_ram_spram_inst_qspo_int_0 : FD + generic map( + INIT => '0' + ) + port map ( + C => clk, + D => BU2_U0_gen_sp_ram_spram_inst_spo_int(0), + Q => qspo_4(0) + ); + BU2_XST_GND : GND + port map ( + G => BU2_qdpo(0) + ); + +end STRUCTURE; + +-- synthesis translate_on Index: pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/wraddr_lut_mem.ngc =================================================================== --- pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/wraddr_lut_mem.ngc (nonexistent) +++ pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/wraddr_lut_mem.ngc (revision 2) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4e +$c;x5d=#Zl|bdaa:!3-522):'?%8#?/$0937>7)811:?<89635;?407>:<=><>41C355C619O:??K559?<8?;h45wq{=0ran8;8: ?j;78JJUSS2h6>6=0j;78JJUSS2m6>6=0>1:49MKVR\3n{~l2::1<25>0=AGZ^X7}r`>6>58692<1CXZ_UU8gtj:2294:>685OTVSQQ11395>JSSX\^1}~~`<483:47<>3E^X][[:rrl80<76:1IY?64BTQ\MK@H92I?;6M5/WGQMCODI]CDB-^CAUDLVH)RLYUB\RHCEY-@KWC@MG%a}!Pcf-tvdbczVf~xRcjm/ldk44O7:2C:>6G=2:K06>O3:2C>56GAIUQWEQC13EEJHHJ8;MMDMFGK<2F^X8:4LTV5g>Kfbfx]i}fooa8Ilhhz_oydaa2:L36>H6=2D9==::;O02403H5992>7C<>0878J7750<1E><;?5:L150723G8:9?;4N33670=I:8??96@=147e?KDXJ\Y[ECQ_RNRP3>HB\^EYG<5@2:MH5>V33YKYXl5_IO]AQVOCPk1[ECQMURLBI@7?01326g=R8&mnbR|`m/pliZoi{}%F~bcPsqm\mkrXzfg;<=>>100b?P6(oldT~bc!rno\mkus'DxdaR}o^kmpZthe9:;l5Z0.efjZthe'xdaRgasu-NvjkX{yeTeczPrno345639;k0Y=!heo]qkh(ugdUbb~z Msmn[vvhW`dSab0123147b3\:$kh`Prno-vjkXagy#|}o^kmpZ66m2_;#jka_smn*wijW`dxx"|pn]jjqY69l1^<"ijn^pli+theVcey!~sqm\mkrX:8o0Y=!heo]qkh(ugdUbb~z qrrl[lhsW:;n7X> gdl\vjk)zfgTec}{/pqskZoi|V>:i6[?/fgm[wij&{efSd`|t.sptjYnf}U>=h5Z0.efjZthe'xdaRgasu-ptjYnf}6;2e:W3+bciW{ef"ab_hlpp*uwgVcex1=11d9V4*abfVxda#|`m^kmwq)txfUbby2;>0g8Q5)`mgUyc` }ol]jjvr({yeTecz35?c8QVCUWHFBM^m4URGQ[SOTAKFN?6XLC89UM@QX\PZN=i5WIMKM\(^CJ):%=-][UC"3*4&F[JCB:6V\TMKA3>^T\VMEHo5W_BMQAZOINF<0TilPIed8\anXX{cfZh||inl24>^ceVGjfb|Yesqjkk773QnfS@gaosTfvvohf=1j$=';;`*2-1=f ;#?7l&<)59b,1/33h">%95n<1<7?d:66=1j0?0;;`>0:1=f4=4=7l2::1<7?d:26:1h`f:4d)2*0>b/9 >0h%<&4:f+7,2"86j'5(48`93=879?7ig|t^ofiZabfV|8S9"/Xhnjj}&DG[O+Kh`jr`vlv%77&8$;?Rg379gtj.7!?1o|b&>)79gtj.5!?1o|b&<)79gtj.3!?1o|b&:)99gtj:2294<7i~}a)2*3>bwzh":%:5kpsc+6,1'8;erqe-2.?2n{~l&:)89gtwg;=3:546kkig0mca23:<=vlye797>17:sgtjYdm11zh}aPcmi;?tbwgVxxx45~dqm\wwus?2{x|b&?)69rwui/9 =0}~~`(3+4?tuwg!9";6|pn*7-2=v{ye#9$94qrrl85803xy{c1?17:sptj:56>1z}a33?58uvvh4=427|}o=794;1%55|pn>6>5803zzym%>&7:qsvd.6!>1x|o'2(58wutf :#<7~~}a)6*3>uwzh">%45|psc?1?69:2}ni6y}aefq[issWdof>l5xr`fgvZjr|Vgna!jfsu]nahY`mgU}?R:#NNLF(KIIM8on7z|ndep\hprXelg'hd}{_lgn[bciW9T8!ul_icp[tbwgVigg0>#c^jbwZekc4;'oRfns^sgtjYdm4:'oRfns^f>4)eX`hyT}a20-a\v`gcWdcm1<"l_icp[tuwg4;'oRyfduj>2)eXzlmTmRjPiorvpv;7$jUcm~Qxe<2/gZvnxlfbbhQ|t`efw86+kVbjRkpn]qwq;7$jUyijQkpsc\mkvr|4:'oRzamke}Zqb59&hS~wac^gmegjb58&hSikti?50)eX`hyTh}|n=1.`[mgtWxy{cR}}su?3(fYoizUzh}aPssqw95*dWxinSgafndf>4)eXelgTxt~j=1.`[mgtW`Uhi0>#c^jbwZbwg4:'oRcjm^kmmqYaaeo6{okds]oqqYjmd$fek"l_egeepjsWmkm0>#c^jbwZuwzh7; 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Alachiotis -- +-- -- +-- Engineer: Nikolaos Ch. Alachiotis -- +-- -- +-- Contact: alachiot@cs.tum.edu -- +-- n.alachiotis@gmail.com -- +-- -- +-- Create Date: 14:32:06 02/07/2010 -- +-- Module Name: IPv4_PACKET_RECEIVER -- +-- Target Devices: Virtex 5 FPGAs -- +-- Tool versions: ISE 10.1 -- +-- Description: This component can be used to receive IPv4 Ethernet Packets. -- +-- Additional Comments: -- +-- -- +-- The receiver does not operate properly for data section of 1 or 2 bytes only. -- +-- -- +----------------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity IPv4_PACKET_RECEIVER is + Port ( rst : in STD_LOGIC; + clk_125Mhz : in STD_LOGIC; + rx_sof : in STD_LOGIC; + rx_eof : in STD_LOGIC; + input_bus : in STD_LOGIC_VECTOR(7 downto 0); + valid_out_usr_data : out STD_LOGIC; + usr_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0)); +end IPv4_PACKET_RECEIVER; + +architecture Behavioral of IPv4_PACKET_RECEIVER is + +component PACKET_RECEIVER_FSM is + Port ( + rst : in STD_LOGIC; + clk : in STD_LOGIC; + + -- Signals from EMAC + rx_sof: in STD_LOGIC; -- active low input + rx_eof: in STD_LOGIC; -- active low input + + -- Signals to Counter and Comparator + sel_comp_Bval: out STD_LOGIC; + comp_Bval: out STD_LOGIC_VECTOR(10 downto 0); + rst_count : out STD_LOGIC; + en_count : out STD_LOGIC; + + -- Signal from Comparator + comp_eq: in STD_LOGIC; + + -- Signals to Length Register + wren_MSbyte: out STD_LOGIC; + wren_LSbyte: out STD_LOGIC; + + -- Signal to user interface + valid_out_usr_data : out STD_LOGIC); +end component; + +component REG_8b_wren is + Port ( rst : in STD_LOGIC; + clk : in STD_LOGIC; + wren : in STD_LOGIC; + input_val : in STD_LOGIC_VECTOR (7 downto 0); + output_val : inout STD_LOGIC_VECTOR(7 downto 0)); +end component; + +component COUNTER_11B_EN_RECEIV is + Port ( rst : in STD_LOGIC; + clk : in STD_LOGIC; + count_en : in STD_LOGIC; + value_O : inout STD_LOGIC_VECTOR (10 downto 0)); +end component; + +component comp_11b_equal is + port ( + qa_eq_b : out STD_LOGIC; + clk : in STD_LOGIC := 'X'; + a : in STD_LOGIC_VECTOR ( 10 downto 0 ); + b : in STD_LOGIC_VECTOR ( 10 downto 0 ) + ); +end component; + +signal sel_comp_Bval, + rst_count, + en_count, + comp_eq, + wren_MSbyte, + wren_LSbyte: STD_LOGIC; + +signal MSbyte_reg_val_out, + LSbyte_reg_val_out : STD_LOGIC_VECTOR(7 downto 0); + +signal counter_val, + match_val, + comp_Bval, + comp_sel_val_vec, + comp_n_sel_val_vec, + length_val: STD_LOGIC_VECTOR(10 downto 0); + +constant length_offest : STD_LOGIC_VECTOR(7 downto 0):="00001010"; +-- This value is formed as 2 (1 clock the latency of comparator and 1 clock fro changing the FSM state) + 8 (number of bytes of UDP header section) + +begin + +usr_data_output_bus<=input_bus; + +PACKET_RECEIVER_FSM_port_map: PACKET_RECEIVER_FSM Port Map +( + rst => rst, + clk => clk_125MHz, + + rx_sof => rx_sof, + rx_eof => rx_eof, + + sel_comp_Bval => sel_comp_Bval, + comp_Bval => comp_Bval, + rst_count => rst_count, + en_count => en_count, + + comp_eq => comp_eq, + + wren_MSbyte => wren_MSbyte, + wren_LSbyte => wren_LSbyte, + + valid_out_usr_data => valid_out_usr_data +); + +MSbyte_REG: REG_8b_wren Port Map +( + rst => rst, + clk => clk_125MHz, + wren => wren_MSbyte, + input_val => input_bus, + output_val =>MSbyte_reg_val_out +); + +LSbyte_REG: REG_8b_wren Port Map +( + rst => rst, + clk => clk_125MHz, + wren => wren_LSbyte, + input_val => input_bus, + output_val =>LSbyte_reg_val_out +); + +COUNTER_11B_EN_port_map: COUNTER_11B_EN_RECEIV Port Map +( + rst => rst_count, + clk => clk_125MHz, + count_en => en_count, + value_O => counter_val +); + +Comp_11b_equal_port_map: Comp_11b_equal Port Map +( + qa_eq_b => comp_eq, + clk => clk_125MHz, + a => counter_val, + b => match_val + ); + +length_val(7 downto 0)<= LSbyte_reg_val_out-length_offest; +length_val(10 downto 8)<= MSbyte_reg_val_out (2 downto 0); + +comp_sel_val_vec<=(others=> sel_comp_Bval); +comp_n_sel_val_vec<= (others=> not sel_comp_Bval); + +match_val<= (comp_sel_val_vec and length_val) or (comp_n_sel_val_vec and comp_Bval); + + +end Behavioral; + Index: pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/FLEX_CONTROL.vhd =================================================================== --- pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/FLEX_CONTROL.vhd (nonexistent) +++ pc_fpga_com/trunk/UDP_IP_CORE_FLEX_Virtex5/FLEX_CONTROL.vhd (revision 2) @@ -0,0 +1,138 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 15:06:05 01/12/2011 +-- Design Name: +-- Module Name: FLEX_CONTROL - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity FLEX_CONTROL is + Port ( rst : in STD_LOGIC; + clk : in STD_LOGIC; + r_sof : in STD_LOGIC; + r_usrvld : in STD_LOGIC; + r_data : in STD_LOGIC_VECTOR (7 downto 0); + r_usrdata: in STD_LOGIC_VECTOR (7 downto 0); + r_eof : in STD_LOGIC; + l_wren : out STD_LOGIC; + l_addr : out STD_LOGIC_VECTOR (5 downto 0); + l_data : out STD_LOGIC_VECTOR (7 downto 0); + checksum_baseval : out STD_LOGIC_VECTOR(15 downto 0); + locked : out STD_LOGIC + ); +end FLEX_CONTROL; + +architecture Behavioral of FLEX_CONTROL is + +component MATCH_CMD_CODE is + Port ( clk : in STD_LOGIC; + vld : in STD_LOGIC; + data_in : in STD_LOGIC_VECTOR(7 downto 0); + eof : in STD_LOGIC; + cmd_code : in STD_LOGIC_VECTOR (7 downto 0); + sig_out : out STD_LOGIC); +end component; + +component MATCH_CMD is + Port ( rst : in STD_LOGIC; + clk : in STD_LOGIC; + sof : in STD_LOGIC; + vld_i : in STD_LOGIC; + val_i : in STD_LOGIC_VECTOR (7 downto 0); + cmd_to_match : in STD_LOGIC_VECTOR(7 downto 0); + cmd_match : out STD_LOGIC); +end component; + +signal config_en, ulock_en, wren_checksum_1, wren_checksum_2,local_rst: std_logic; + +component CONFIG_CONTROL is + Port ( rst : in STD_LOGIC; + clk : in STD_LOGIC; + config_en : in STD_LOGIC; + nxt_sof : in STD_LOGIC; + wren : out STD_LOGIC; + addr : out STD_LOGIC_VECTOR (5 downto 0); + ulock_en : in STD_LOGIC; + wren_checksum_1 : out STD_LOGIC; + wren_checksum_2 : out STD_LOGIC; + locked : out STD_LOGIC + ); +end component; + +signal checksum_baseval_t: std_logic_vector(15 downto 0); + +begin + +MATCH_RST_CODE: MATCH_CMD Port Map +( rst => rst, + clk => clk, + sof => r_sof, + vld_i => r_usrvld, + val_i => r_usrdata, + cmd_to_match => "00001111", + cmd_match => config_en + ); + +ulock_en <= '0'; + +CONFIG_CONTROL_FSM: CONFIG_CONTROL Port Map +( rst => rst, + clk => clk, + config_en => config_en, + nxt_sof => r_sof, + wren => l_wren, + addr => l_addr, + ulock_en => ulock_en, + wren_checksum_1 => wren_checksum_1, + wren_checksum_2 => wren_checksum_2, + locked => locked +); + +process(clk) +begin +if rst = '1' then + checksum_baseval_t <= (others=>'0'); +else + if clk'event and clk='1' then + if wren_checksum_1='1' then + checksum_baseval_t(15 downto 8) <= r_data; + end if; + if wren_checksum_2='1' then + checksum_baseval_t(7 downto 0) <= r_data; + end if; + end if; +end if; +end process; + +checksum_baseval <= checksum_baseval_t; + +process(clk) +begin +if clk'event and clk='1' then + l_data <= r_data; +end if; +end process; + +end Behavioral; +
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