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/robust_axi2ahb/trunk/run/run.bat
0,0 → 1,6
 
echo off
 
..\..\..\robust.exe ../src/base/axi2ahb.v -od out -I ../src/gen -list list.txt -listpath -header
 
echo Completed RobustVerilog axi2ahb run - results in run/out/
/robust_axi2ahb/trunk/run/run.sh
0,0 → 1,5
#!/bin/bash
 
../../../robust ../src/base/axi2ahb.v -od out -I ../src/gen -list list.txt -listpath -header ${@}
 
echo Completed RobustVerilog axi2ahb run - results in run/out/
/robust_axi2ahb/trunk/src/gen/prgen_fifo.v
0,0 → 1,196
/////////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
//// eyal@provartec.com ////
//// ////
//// Downloaded from: http://www.opencores.org ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Provartec LTD ////
//// www.provartec.com ////
//// info@provartec.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation.////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
/////////////////////////////////////////////////////////////////////
 
IFDEF STUB
OUTFILE prgen_fifo_stub.v
module prgen_fifo_stub(PORTS);
ELSE STUB
OUTFILE prgen_fifo.v
module prgen_fifo(PORTS);
ENDIF STUB
parameter WIDTH = 8;
parameter DEPTH_FULL = 8;
 
parameter SINGLE = DEPTH_FULL == 1;
parameter DEPTH = SINGLE ? 1 : DEPTH_FULL -1;
parameter DEPTH_BITS =
(DEPTH <= 2) ? 1 :
(DEPTH <= 4) ? 2 :
(DEPTH <= 8) ? 3 :
(DEPTH <= 16) ? 4 :
(DEPTH <= 32) ? 5 :
(DEPTH <= 64) ? 6 :
(DEPTH <= 128) ? 7 :
(DEPTH <= 256) ? 8 :
(DEPTH <= 512) ? 9 : 0; //0 is ilegal
 
parameter LAST_LINE = DEPTH-1;
 
input clk;
input reset;
 
input push;
input pop;
input [WIDTH-1:0] din;
output [WIDTH-1:0] dout;
IF STUB output [DEPTH_BITS:0] fullness;
output empty;
output full;
 
wire reg_push;
wire reg_pop;
wire fifo_push;
wire fifo_pop;
reg [DEPTH-1:0] full_mask_in;
reg [DEPTH-1:0] full_mask_out;
reg [DEPTH-1:0] full_mask;
reg [WIDTH-1:0] fifo [DEPTH-1:0];
wire fifo_empty;
wire next;
reg [WIDTH-1:0] dout;
reg dout_empty;
reg [DEPTH_BITS-1:0] ptr_in;
reg [DEPTH_BITS-1:0] ptr_out;
 
 
assign reg_push = push & fifo_empty & (dout_empty | pop);
assign reg_pop = pop & fifo_empty;
assign fifo_push = !SINGLE & push & (~reg_push);
assign fifo_pop = !SINGLE & pop & (~reg_pop);
always @(posedge clk or posedge reset)
if (reset)
begin
dout <= #FFD {WIDTH{1'b0}};
dout_empty <= #FFD 1'b1;
end
else if (reg_push)
begin
dout <= #FFD din;
dout_empty <= #FFD 1'b0;
end
else if (reg_pop)
begin
dout <= #FFD {WIDTH{1'b0}};
dout_empty <= #FFD 1'b1;
end
else if (fifo_pop)
begin
dout <= #FFD fifo[ptr_out];
dout_empty <= #FFD 1'b0;
end
always @(posedge clk or posedge reset)
if (reset)
ptr_in <= #FFD {DEPTH_BITS{1'b0}};
else if (fifo_push)
ptr_in <= #FFD ptr_in == LAST_LINE ? 0 : ptr_in + 1'b1;
 
always @(posedge clk or posedge reset)
if (reset)
ptr_out <= #FFD {DEPTH_BITS{1'b0}};
else if (fifo_pop)
ptr_out <= #FFD ptr_out == LAST_LINE ? 0 : ptr_out + 1'b1;
 
always @(posedge clk)
if (fifo_push)
fifo[ptr_in] <= #FFD din;
 
always @(/*AUTOSENSE*/fifo_push or ptr_in)
begin
full_mask_in = {DEPTH{1'b0}};
full_mask_in[ptr_in] = fifo_push;
end
always @(/*AUTOSENSE*/fifo_pop or ptr_out)
begin
full_mask_out = {DEPTH{1'b0}};
full_mask_out[ptr_out] = fifo_pop;
end
always @(posedge clk or posedge reset)
if (reset)
full_mask <= #FFD {DEPTH{1'b0}};
else if (fifo_push | fifo_pop)
full_mask <= #FFD (full_mask & (~full_mask_out)) | full_mask_in;
 
 
assign next = |full_mask;
assign fifo_empty = ~next;
assign empty = fifo_empty & dout_empty;
assign full = SINGLE ? !dout_empty : &full_mask;
 
 
IFDEF STUB
reg [DEPTH_BITS:0] fullness;
always @(posedge clk or posedge reset)
if (reset)
fullness <= #FFD {DEPTH_BITS+1{1'b0}};
else if (push | pop)
fullness <= #FFD fullness + push - pop;
wire overflow = full & fifo_push & (~fifo_pop);
wire underflow = empty & fifo_pop & (~fifo_push);
always @(posedge overflow)
begin
#1;
if (overflow)
begin
$display("-E-%m - overflow.\tTime: %0d ns", $time);
#1000;
$finish;
end
end
always @(posedge underflow)
begin
#1;
if (underflow)
begin
$display("-E-%m - underflow.\tTime: %0d ns", $time);
#1000;
$finish;
end
end
ENDIF STUB
endmodule
 
 
/robust_axi2ahb/trunk/src/base/def_axi2ahb_static.txt
0,0 → 1,57
 
VERIFY ((DATA_BITS==32) || (DATA_BITS==64))
GROUP AXI_A is {
ID ID_BITS input
ADDR ADDR_BITS input
LEN 4 input
SIZE 2 input
VALID 1 input
READY 1 output
}
 
GROUP AXI_W is {
ID ID_BITS input
DATA DATA_BITS input
STRB DATA_BITS/8 input
LAST 1 input
VALID 1 input
READY 1 output
}
 
GROUP AXI_B is {
ID ID_BITS output
RESP 2 output
VALID 1 output
READY 1 input
}
 
GROUP AXI_R is {
ID ID_BITS output
DATA DATA_BITS output
RESP 2 output
LAST 1 output
VALID 1 output
READY 1 input
}
 
GROUP AXI joins {
GROUP AXI_A prefix_AW
GROUP AXI_W prefix_W
GROUP AXI_B prefix_B
GROUP AXI_A prefix_AR
GROUP AXI_R prefix_R
}
 
GROUP AHB is {
HADDR ADDR_BITS input
HBURST 3 input
HSIZE 2 input
HTRANS 2 input
HWRITE 1 input
HWDATA DATA_BITS input
HRDATA DATA_BITS output
HREADY 1 output
HRESP 1 output
}
/robust_axi2ahb/trunk/src/base/axi2ahb.v
0,0 → 1,121
 
INCLUDE def_axi2ahb.txt
OUTFILE PREFIX_axi2ahb.v
 
CHECK CONST(#FFD)
CHECK CONST(PREFIX)
CHECK CONST(ADDR_BITS)
CHECK CONST(DATA_BITS)
CHECK CONST(ID_BITS)
CHECK CONST(CMD_DEPTH)
module PREFIX_axi2ahb (PORTS);
 
input clk;
input reset;
 
port GROUP_AXI;
 
revport GROUP_AHB;
 
//outputs of cmd
wire cmd_empty;
wire cmd_read;
wire [ID_BITS-1:0] cmd_id;
wire [ADDR_BITS-1:0] cmd_addr;
wire [3:0] cmd_len;
wire [1:0] cmd_size;
wire cmd_err;
//outputs of ctrl
wire ahb_finish;
wire data_last;
 
//outputs of wr fifo
wire wdata_phase;
wire wdata_ready;
//outputs of rd fifo
wire rdata_phase;
wire rdata_ready;
 
CREATE axi2ahb_cmd.v
PREFIX_axi2ahb_cmd PREFIX_axi2ahb_cmd(
.clk(clk),
.reset(reset),
.AWGROUP_AXI_A(AWGROUP_AXI_A),
.ARGROUP_AXI_A(ARGROUP_AXI_A),
.GROUP_AHB(GROUP_AHB),
.ahb_finish(ahb_finish),
.cmd_empty(cmd_empty),
.cmd_read(cmd_read),
.cmd_id(cmd_id),
.cmd_addr(cmd_addr),
.cmd_len(cmd_len),
.cmd_size(cmd_size),
.cmd_err(cmd_err)
);
 
 
CREATE axi2ahb_ctrl.v
PREFIX_axi2ahb_ctrl PREFIX_axi2ahb_ctrl(
.clk(clk),
.reset(reset),
.GROUP_AHB(GROUP_AHB),
.ahb_finish(ahb_finish),
.rdata_phase(rdata_phase),
.wdata_phase(wdata_phase),
.data_last(data_last),
.rdata_ready(rdata_ready),
.wdata_ready(wdata_ready),
.cmd_empty(cmd_empty),
.cmd_read(cmd_read),
.cmd_addr(cmd_addr),
.cmd_len(cmd_len),
.cmd_size(cmd_size)
);
 
CREATE axi2ahb_wr_fifo.v
PREFIX_axi2ahb_wr_fifo
PREFIX_axi2ahb_wr_fifo(
.clk(clk),
.reset(reset),
.WGROUP_AXI_W(WGROUP_AXI_W),
.BGROUP_AXI_B(BGROUP_AXI_B),
.HWDATA(HWDATA),
.HREADY(HREADY),
.HTRANS(HTRANS),
.HRESP(HRESP),
.cmd_err(cmd_err),
.wdata_phase(wdata_phase),
.wdata_ready(wdata_ready),
.data_last(data_last)
);
 
CREATE axi2ahb_rd_fifo.v
PREFIX_axi2ahb_rd_fifo
PREFIX_axi2ahb_rd_fifo(
.clk(clk),
.reset(reset),
.RGROUP_AXI_R(RGROUP_AXI_R),
.HRDATA(HRDATA),
.HREADY(HREADY),
.HTRANS(HTRANS),
.HRESP(HRESP),
.cmd_id(cmd_id),
.cmd_err(cmd_err),
.rdata_phase(rdata_phase),
.rdata_ready(rdata_ready),
.data_last(data_last)
);
 
endmodule
 
 
/robust_axi2ahb/trunk/src/base/axi2ahb_cmd.v
0,0 → 1,105
 
OUTFILE PREFIX_axi2ahb_cmd.v
INCLUDE def_axi2ahb.txt
 
module PREFIX_axi2ahb_cmd (PORTS);
 
input clk;
input reset;
 
port AWGROUP_AXI_A;
port ARGROUP_AXI_A;
input GROUP_AHB;
input ahb_finish;
output cmd_empty;
output cmd_read;
output [ID_BITS-1:0] cmd_id;
output [ADDR_BITS-1:0] cmd_addr;
output [3:0] cmd_len;
output [1:0] cmd_size;
output cmd_err;
wire AGROUP_AXI_A;
wire cmd_push;
wire cmd_pop;
wire cmd_empty;
wire cmd_full;
reg read;
wire err;
 
wire wreq, rreq;
wire wack, rack;
wire AERR;
assign wreq = AWVALID;
assign rreq = ARVALID;
assign wack = AWVALID & AWREADY;
assign rack = ARVALID & ARREADY;
always @(posedge clk or posedge reset)
if (reset)
read <= #FFD 1'b1;
else if (wreq & (rack | (~rreq)))
read <= #FFD 1'b0;
else if (rreq & (wack | (~wreq)))
read <= #FFD 1'b1;
 
//command mux
assign AGROUP_AXI_A = read ? ARGROUP_AXI_A : AWGROUP_AXI_A;
assign ARREADY = (~cmd_full) & read;
assign AWREADY = (~cmd_full) & (~read);
 
assign err =
((ALEN != 4'd0) &
(ALEN != 4'd3) &
(ALEN != 4'd7) &
(ALEN != 4'd15)) |
(((ASIZE == 2'b01) & (AADDR[0] != 1'b0)) |
((ASIZE == 2'b10) & (AADDR[1:0] != 2'b00)) |
((ASIZE == 2'b11) & (AADDR[2:0] != 3'b000)));
assign cmd_push = AVALID & AREADY;
assign cmd_pop = ahb_finish;
CREATE prgen_fifo.v DEFCMD(SWAP CONST(#FFD) #FFD)
prgen_fifo #(ID_BITS+ADDR_BITS+4+2+1+1, CMD_DEPTH)
cmd_fifo(
.clk(clk),
.reset(reset),
.push(cmd_push),
.pop(cmd_pop),
.din({
AID,
AADDR,
ALEN,
ASIZE,
read,
err
}
),
.dout({
cmd_id,
cmd_addr,
cmd_len,
cmd_size,
cmd_read,
cmd_err
}
),
.empty(cmd_empty),
.full(cmd_full)
);
 
endmodule
 
 
/robust_axi2ahb/trunk/src/base/axi2ahb_ctrl.v
0,0 → 1,144
 
INCLUDE def_axi2ahb.txt
OUTFILE PREFIX_axi2ahb_ctrl.v
 
module PREFIX_axi2ahb_ctrl (PORTS);
 
 
input clk;
input reset;
 
revport GROUP_AHB;
output ahb_finish;
output rdata_phase;
output wdata_phase;
output data_last;
 
input rdata_ready;
input wdata_ready;
input cmd_empty;
input cmd_read;
input [ADDR_BITS-1:0] cmd_addr;
input [3:0] cmd_len;
input [1:0] cmd_size;
parameter TRANS_IDLE = 2'b00;
parameter TRANS_BUSY = 2'b01;
parameter TRANS_NONSEQ = 2'b10;
parameter TRANS_SEQ = 2'b11;
parameter BURST_SINGLE = 3'b000;
parameter BURST_INCR4 = 3'b011;
parameter BURST_INCR8 = 3'b101;
parameter BURST_INCR16 = 3'b111;
 
wire data_ready;
wire ahb_idle;
wire ahb_ack;
wire ahb_ack_last;
wire ahb_start;
wire ahb_last;
wire data_last;
reg [4:0] cmd_counter;
reg rdata_phase;
reg wdata_phase;
wire data_phase;
reg [1:0] HTRANS;
reg [2:0] HBURST;
reg [1:0] HSIZE;
reg HWRITE;
reg [ADDR_BITS-1:0] HADDR;
 
assign ahb_finish = ahb_ack_last;
assign data_ready = cmd_read ? rdata_ready : wdata_ready;
assign data_phase = wdata_phase | rdata_phase;
assign ahb_idle = HTRANS == TRANS_IDLE;
assign ahb_ack = HTRANS[1] & HREADY;
assign ahb_ack_last = ahb_last & ahb_ack;
assign ahb_start = (~cmd_empty) & data_ready & ahb_idle & (HREADY | (~data_phase));
assign data_last = HREADY & (ahb_idle || (HTRANS == TRANS_NONSEQ));
always @(posedge clk or posedge reset)
if (reset)
cmd_counter <= #FFD 4'd0;
else if (ahb_ack_last)
cmd_counter <= #FFD 4'd0;
else if (ahb_ack)
cmd_counter <= #FFD cmd_counter + 1'b1;
 
assign ahb_last = cmd_counter == cmd_len;
always @(posedge clk or posedge reset)
if (reset)
rdata_phase <= #FFD 1'b0;
else if (ahb_ack & (~HWRITE))
rdata_phase <= #FFD 1'b1;
else if (data_last)
rdata_phase <= #FFD 1'b0;
always @(posedge clk or posedge reset)
if (reset)
wdata_phase <= #FFD 1'b0;
else if (ahb_ack & HWRITE)
wdata_phase <= #FFD 1'b1;
else if (data_last)
wdata_phase <= #FFD 1'b0;
always @(posedge clk or posedge reset)
if (reset)
HTRANS <= #FFD TRANS_IDLE;
else if (ahb_start)
HTRANS <= #FFD TRANS_NONSEQ;
else if (ahb_ack_last)
HTRANS <= #FFD TRANS_IDLE;
else if (ahb_ack)
HTRANS <= #FFD TRANS_SEQ;
 
always @(posedge clk or posedge reset)
if (reset)
HBURST <= #FFD BURST_SINGLE;
else if (ahb_start & (cmd_len == 4'd0))
HBURST <= #FFD BURST_SINGLE;
else if (ahb_start & (cmd_len == 4'd3))
HBURST <= #FFD BURST_INCR4;
else if (ahb_start & (cmd_len == 4'd7))
HBURST <= #FFD BURST_INCR8;
else if (ahb_start & (cmd_len == 4'd15))
HBURST <= #FFD BURST_INCR16;
always @(posedge clk or posedge reset)
if (reset)
HSIZE <= #FFD 2'b00;
else if (ahb_start)
HSIZE <= cmd_size;
always @(posedge clk or posedge reset)
if (reset)
HWRITE <= #FFD 2'b00;
else if (ahb_start)
HWRITE <= (~cmd_read);
always @(posedge clk or posedge reset)
if (reset)
HADDR <= #FFD {ADDR_BITS{1'b0}};
else if (ahb_start)
HADDR <= #FFD cmd_addr;
else if (ahb_ack_last)
HADDR <= #FFD {ADDR_BITS{1'b0}};
else if (ahb_ack)
HADDR <= #FFD HADDR + (
HSIZE == 2'b00 ? 4'd1 :
HSIZE == 2'b01 ? 4'd2 :
HSIZE == 2'b10 ? 4'd4 :
HSIZE == 2'b11 ? 4'd8 :
4'd0);
 
endmodule
 
/robust_axi2ahb/trunk/src/base/axi2ahb_rd_fifo.v
0,0 → 1,92
 
INCLUDE def_axi2ahb.txt
OUTFILE PREFIX_axi2ahb_rd_fifo.v
 
module PREFIX_axi2ahb_rd_fifo (PORTS);
 
parameter FIFO_LINES = EXPR(2 * 16); //double buffer of max burst
parameter RESP_SLVERR = 2'b10;
 
input clk;
input reset;
 
port RGROUP_AXI_R;
input [DATA_BITS-1:0] HRDATA;
input HREADY;
input [1:0] HTRANS;
input HRESP;
input [ID_BITS-1:0] cmd_id;
input cmd_err;
input rdata_phase;
output rdata_ready;
input data_last;
 
 
wire data_push;
wire data_pop;
wire data_empty;
wire data_full;
 
reg RVALID;
reg [LOG2(CMD_DEPTH):0] burst_cnt;
 
wire axi_last;
wire ahb_last;
wire [1:0] cmd_resp;
 
assign cmd_resp = cmd_err | HRESP ? RESP_SLVERR : 2'b00;
assign rdata_ready = burst_cnt < 'd2;
assign data_push = rdata_phase & HREADY;
assign data_pop = RVALID & RREADY;
assign axi_last = RVALID & RREADY & RLAST;
assign ahb_last = rdata_phase & data_last;
always @(posedge clk or posedge reset)
if (reset)
burst_cnt <= #FFD 'd0;
else if (axi_last | ahb_last)
burst_cnt <= #FFD burst_cnt - axi_last + ahb_last;
prgen_fifo #(DATA_BITS+ID_BITS+2+1, FIFO_LINES)
data_fifo(
.clk(clk),
.reset(reset),
.push(data_push),
.pop(data_pop),
.din({HRDATA,
cmd_id,
cmd_resp,
ahb_last
}
),
.dout({RDATA,
RID,
RRESP,
RLAST
}
),
.empty(data_empty),
.full(data_full)
);
 
 
always @(posedge clk or posedge reset)
if (reset)
RVALID <= #FFD 1'b0;
else if (axi_last)
RVALID <= #FFD 1'b0;
else if (burst_cnt > 'd0)
RVALID <= #FFD 1'b1;
else
RVALID <= #FFD 1'b0;
 
endmodule
 
/robust_axi2ahb/trunk/src/base/def_axi2ahb.txt
0,0 → 1,12
 
INCLUDE def_axi2ahb_static.txt
 
SWAP #FFD #1 ## flip-flop delay
 
SWAP PREFIX soc ## prefix for all modules and file names
 
SWAP CMD_DEPTH 4 ## number of AXI command FIFO
 
SWAP ADDR_BITS 24 ## AXI and AHB address bits
SWAP DATA_BITS 32 ## AXI and AHB data bits
SWAP ID_BITS 4 ## AXI ID bits
/robust_axi2ahb/trunk/src/base/axi2ahb_wr_fifo.v
0,0 → 1,108
 
INCLUDE def_axi2ahb.txt
OUTFILE PREFIX_axi2ahb_wr_fifo.v
 
module PREFIX_axi2ahb_wr_fifo (PORTS);
 
parameter FIFO_LINES = EXPR(2 * 16); //double buffer of max burst
parameter RESP_SLVERR = 2'b10;
 
input clk;
input reset;
 
port WGROUP_AXI_W;
port BGROUP_AXI_B;
output [DATA_BITS-1:0] HWDATA;
input HREADY;
input [1:0] HTRANS;
input HRESP;
 
input cmd_err;
input wdata_phase;
output wdata_ready;
input data_last;
 
 
wire data_push;
wire data_pop;
wire data_empty;
wire data_full;
 
wire resp_push;
wire resp_pop;
wire resp_empty;
wire resp_full;
reg [LOG2(CMD_DEPTH):0] burst_cnt;
wire burst_full;
wire axi_last;
wire ahb_last;
wire [1:0] cmd_resp;
 
assign cmd_resp = cmd_err | HRESP ? RESP_SLVERR : 2'b00;
 
assign wdata_ready = burst_cnt > 'd0;
assign WREADY = (~data_full) & (~burst_full);
assign data_push = WVALID & WREADY;
assign data_pop = wdata_phase & HREADY;
assign axi_last = WVALID & WREADY & WLAST;
assign ahb_last = wdata_phase & data_last;
 
assign burst_full = burst_cnt == {EXPR(LOG2(CMD_DEPTH)+1){1'b1}};
always @(posedge clk or posedge reset)
if (reset)
burst_cnt <= #FFD 'd0;
else if (axi_last | ahb_last)
burst_cnt <= #FFD burst_cnt + axi_last - ahb_last;
prgen_fifo #(DATA_BITS, FIFO_LINES)
data_fifo(
.clk(clk),
.reset(reset),
.push(data_push),
.pop(data_pop),
.din({WDATA
}
),
.dout({HWDATA
}
),
.empty(data_empty),
.full(data_full)
);
 
 
assign resp_push = ahb_last;
assign resp_pop = BVALID & BREADY;
 
assign BVALID = (~resp_empty);
prgen_fifo #(2+ID_BITS, CMD_DEPTH)
resp_fifo(
.clk(clk),
.reset(reset),
.push(resp_push),
.pop(resp_pop),
.din({cmd_resp,
WID
}
),
.dout({BRESP,
BID
}
),
.empty(resp_empty),
.full(resp_full)
);
 
 
endmodule
 
/robust_axi2ahb/trunk/README.txt
0,0 → 1,23
 
------------------------------ Remark ----------------------------------------
This code is a generic code written in RobustVerilog. In order to convert it to Verilog a RobustVerilog parser is required.
It is possible to download a free RobustVerilog parser from www.provartec.com/edatools.
 
We will be very happy to receive any kind of feedback regarding our tools and cores.
We will also be willing to support any company intending to integrate our cores into their project.
For any questions / remarks / suggestions / bugs please contact info@provartec.com.
------------------------------------------------------------------------------
 
RobustVerilog generic AXI to AHB bridge
 
In order to create the Verilog design use the run.sh script in the run directory (notice that the run scripts calls the robust binary (RobustVerilog parser)).
 
The RobustVerilog top source file is axi2ahb.v, it calls the top definition file named def_axi2ahb.txt.
 
The default definition file def_axi2ahb.txt generates a bridge with 8 APB slaves.
 
Changing the interconnect parameters should be made only in def_axi2ahb.txt in the src/base directory (changing slave num etc.).
 
 
 
 

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