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/sport/trunk/bench/testcase_1.v
0,0 → 1,96
//////////////////////////////////////////////////////////////////////
//// ////
//// weigand_tx_top.v ////
//// ////
//// ////
//// This file is part of the Time Triggered Protocol Controller ////
//// http://www.opencores.org/projects/weigand/ ////
//// ////
//// ////
//// Author(s): ////
//// Jeff Anderson ////
//// jeaander@opencores.org ////
//// ////
//// ////
//// All additional information is available in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2013 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//// The Weigand protocol is maintained by ////
//// This product has been tested to interoperate with certified ////
//// devices, but has not been certified itself. This product ////
//// should be certified through prior to claiming strict ////
//// adherence to the standard. ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// Revisions at end of file
//
 
`include "timescale.v"
`include "sport_defines.v"
`include "testbench_top.v"
 
module testcase_1;
testbench_top testbench();
initial
begin
testbench.wb_rst;
//#40 testbench.wb_write_async(32'h0);
//#40 testbench.wb_write_sync(32'h0);
//#40 testbench.wb_read_async;
//#40 testbench.wb_read_sync;
//write a small word adn send
#40 testbench.wb_write_async(32'hA5A5A50F);
#40 testbench.wb_writep2p_async(32'h7);
#40 testbench.wb_writepw_async(32'h3);
#40 testbench.wb_writesize_async(32'h87);
#40 testbench.wb_writesend_async(32'h7);
#40 testbench.wiegand_write(32'hA5, 6'h5, 6'h7, 6'h3);
//now write a 32 bit word
#1040 testbench.wb_write_async(32'hA5A5A50F);
#40 testbench.wb_writep2p_async(32'h7);
#40 testbench.wb_writepw_async(32'h3);
#40 testbench.wb_writesend_async(32'b00011111);
#40 testbench.wiegand_write(32'hA5A5A50F, 6'h20, 6'h7, 6'h3);
//now write a 35 bit word
#4040 testbench.wb_write_async(32'hA5A5A50F);
#40 testbench.wb_write_async(32'h33333333);
#40 testbench.wb_writep2p_async(32'h7);
#40 testbench.wb_writepw_async(32'h3);
#40 testbench.wb_writesend_async(32'b00100010);
#40 testbench.wiegand_write(40'hF0A5A5A50F, 6'h25, 6'h7, 6'h3);
#10000 $stop;
end
endmodule
/sport/trunk/bench/testbench_top.v.bak
0,0 → 1,310
//////////////////////////////////////////////////////////////////////
//// ////
//// weigand_tx_top.v ////
//// ////
//// ////
//// This file is part of the Time Triggered Protocol Controller ////
//// http://www.opencores.org/projects/weigand/ ////
//// ////
//// ////
//// Author(s): ////
//// Jeff Anderson ////
//// jeaander@opencores.org ////
//// ////
//// ////
//// All additional information is available in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2013 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//// The Weigand protocol is maintained by ////
//// This product has been tested to interoperate with certified ////
//// devices, but has not been certified itself. This product ////
//// should be certified through prior to claiming strict ////
//// adherence to the standard. ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// Revisions at end of file
//
 
`include "timescale.v"
`include "SPORT_defines.v"
 
module testbench_top;
reg [5:0] wb_addr_i;
reg [31:0] wb_dat_i;
wire [31:0] wb_dat_o;
wire [31:0] wb_dat_o_rx;
reg wb_cyc_i;
reg wb_stb_i;
reg [2:0] wb_cti_i;
reg [3:0] wb_sel_i;
reg wb_we_i;
reg wb_rst_i;
reg wb_clk_i;
reg one_i, zero_i;
//DUTs
sport_top sport_top(wb_clk_i,wb_rst_i,wb_dat_i,wb_dat_o,wb_cyc_i,wb_stb_i,wb_cti_i,wb_sel_i,wb_we_i,wb_addr_i,
wb_ack_o,wb_err_o,wb_rty_o, DTxPRI,DTxSEC,TSCLKx,TFSx,DRxPRI,DRxSEC,RSCLKx,TRSx,);
//tasks for simulation
initial begin
wb_addr_i = 6'h0;
wb_dat_i = 32'h0;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
wb_we_i = 1'b0;
wb_rst_i = 1'b0;
wb_clk_i = 1'b0;
one_i = 1'b1;
zero_i = 1'b1;
end
always
#5 wb_clk_i = !wb_clk_i;
/********************** tasks run by testcases for this testbench ******************/
//SPORT bus write tasks
task SPORT_write;
input [63:0] SPORT_data;
input [5:0] word_length;
input [5:0] p2p;
input [5:0] pw;
integer i;
integer j;
begin
j = 0;
repeat (word_length) begin
@ (posedge wb_clk_i) begin
if (SPORT_data[j] == 1'b0) begin
SPORT0(pw);
end
else begin
SPORT1(pw);
end
j=j+1;
i = 0;
while(i <= p2p) begin
@ (posedge wb_clk_i) begin i=i+1; end
end
end
end
end
endtask
task SPORT0;
input [5:0] pw;
integer i;
begin
for (i = 0; i <= pw; i=i+1) begin
@(posedge wb_clk_i) zero_i = 1'b0;
end
zero_i = 1'b1;
end
endtask
task SPORT1;
input [5:0] pw;
integer i;
begin
for (i = 0; i <= pw; i=i+1) begin
@(posedge wb_clk_i) one_i = 1'b0;
end
one_i = 1'b1;
end
endtask
//Wishbone readn adn write tasks
task wb_rst;
begin
wb_rst_i = 1'b1;
#20 wb_rst_i = 1'b0;
end
endtask
task wb_write_async;
input [31:0] wb_data;
begin
@ (posedge wb_clk_i) begin
wb_addr_i = `SPORT_ADDR;
wb_dat_i = wb_data;
wb_stb_i = 1'b1;
wb_cyc_i = 1'b1;
wb_we_i = 1'b1;
end
@ (posedge wb_clk_i) begin
wb_addr_i = 6'h0;
wb_dat_i = 32'h0;
wb_stb_i = 1'b0;
wb_cyc_i = 1'b0;
wb_we_i = 1'b0;
end
end
endtask
task wb_write_sync;
input [31:0] wb_data;
begin
@ (posedge wb_clk_i) begin
wb_addr_i = `SPORT_ADDR;
wb_dat_i = wb_data;
wb_stb_i = 1'b1;
wb_cyc_i = 1'b1;
wb_we_i = 1'b1;
end
@ (posedge wb_clk_i) begin
wb_addr_i = `SPORT_ADDR;
wb_dat_i = wb_data;
wb_stb_i = 1'b1;
wb_cyc_i = 1'b1;
wb_we_i = 1'b1;
end
@ (posedge wb_clk_i) begin
wb_addr_i = 6'h0;
wb_dat_i = 32'h0;
wb_stb_i = 1'b0;
wb_cyc_i = 1'b0;
wb_we_i = 1'b0;
end
end
endtask
task wb_writep2p_async;
input [31:0] p2p;
begin
@ (posedge wb_clk_i) begin
wb_addr_i = `WB_CNFG_P2P;
wb_dat_i = p2p;
wb_stb_i = 1'b1;
wb_cyc_i = 1'b1;
wb_we_i = 1'b1;
end
@ (posedge wb_clk_i) begin
wb_addr_i = 6'h0;
wb_dat_i = 32'h0;
wb_stb_i = 1'b0;
wb_cyc_i = 1'b0;
wb_we_i = 1'b0;
end
end
endtask
task wb_writepw_async;
input [31:0] pw;
begin
@ (posedge wb_clk_i) begin
wb_addr_i = `WB_CNFG_PW;
wb_dat_i = pw;
wb_stb_i = 1'b1;
wb_cyc_i = 1'b1;
wb_we_i = 1'b1;
end
@ (posedge wb_clk_i) begin
wb_addr_i = 6'h0;
wb_dat_i = 32'h0;
wb_stb_i = 1'b0;
wb_cyc_i = 1'b0;
wb_we_i = 1'b0;
end
end
endtask
task wb_writesize_async;
input [31:0] size;
begin
@ (posedge wb_clk_i) begin
wb_addr_i = `WB_CNFG_MSGSIZE;
wb_dat_i = (size & 32'h7F);
wb_stb_i = 1'b1;
wb_cyc_i = 1'b1;
wb_we_i = 1'b1;
end
@ (posedge wb_clk_i) begin
wb_addr_i = 6'h0;
wb_dat_i = 32'h0;
wb_stb_i = 1'b0;
wb_cyc_i = 1'b0;
wb_we_i = 1'b0;
end
end
endtask
task wb_writesend_async;
input [31:0] size;
begin
@ (posedge wb_clk_i) begin
wb_addr_i = `WB_CNFG_MSGSIZE;
wb_dat_i = (size | 32'h80);
wb_stb_i = 1'b1;
wb_cyc_i = 1'b1;
wb_we_i = 1'b1;
end
@ (posedge wb_clk_i) begin
wb_addr_i = 6'h0;
wb_dat_i = 32'h0;
wb_stb_i = 1'b0;
wb_cyc_i = 1'b0;
wb_we_i = 1'b0;
end
end
endtask
task wb_read_async;
begin
@ (posedge wb_clk_i) begin
wb_stb_i = 1'b1;
wb_cyc_i = 1'b1;
wb_we_i = 1'b0;
end
@ (posedge wb_clk_i) begin
wb_stb_i = 1'b0;
wb_cyc_i = 1'b0;
end
end
endtask
task wb_read_sync;
begin
@ (posedge wb_clk_i) begin
wb_stb_i = 1'b1;
wb_cyc_i = 1'b1;
wb_we_i = 1'b0;
end
@ (posedge wb_clk_i) begin
wb_stb_i = 1'b1;
wb_cyc_i = 1'b1;
end
@ (posedge wb_clk_i) begin
wb_stb_i = 1'b0;
wb_cyc_i = 1'b0;
end
end
endtask
endmodule
/sport/trunk/bench/testbench_top.v
0,0 → 1,270
//////////////////////////////////////////////////////////////////////
//// ////
//// weigand_tx_top.v ////
//// ////
//// ////
//// This file is part of the Time Triggered Protocol Controller ////
//// http://www.opencores.org/projects/weigand/ ////
//// ////
//// ////
//// Author(s): ////
//// Jeff Anderson ////
//// jeaander@opencores.org ////
//// ////
//// ////
//// All additional information is available in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2013 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//// The Weigand protocol is maintained by ////
//// This product has been tested to interoperate with certified ////
//// devices, but has not been certified itself. This product ////
//// should be certified through prior to claiming strict ////
//// adherence to the standard. ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// Revisions at end of file
//
 
`include "timescale.v"
`include "SPORT_defines.v"
 
module testbench_top;
reg [5:0] wb_addr_i;
reg [31:0] wb_dat_i;
wire [31:0] wb_dat_o;
wire [31:0] wb_dat_o_rx;
reg wb_cyc_i;
reg wb_stb_i;
reg [2:0] wb_cti_i;
reg [3:0] wb_sel_i;
reg wb_we_i;
reg wb_rst_i;
reg wb_clk_i;
reg one_i, zero_i;
//DUTs
sport_top sport_top(wb_clk_i,wb_rst_i,wb_dat_i,wb_dat_o,wb_cyc_i,wb_stb_i,wb_cti_i,wb_sel_i,wb_we_i,wb_addr_i,
wb_ack_o,wb_err_o,wb_rty_o, DTxPRI,DTxSEC,TSCLKx,TFSx,DRxPRI,DRxSEC,RSCLKx,TRSx,);
//tasks for simulation
initial begin
wb_addr_i = 6'h0;
wb_dat_i = 32'h0;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
wb_we_i = 1'b0;
wb_rst_i = 1'b0;
wb_clk_i = 1'b0;
one_i = 1'b1;
zero_i = 1'b1;
end
always
#5 wb_clk_i = !wb_clk_i;
/********************** tasks run by testcases for this testbench ******************/
//SPORT bus write tasks
task SPORT_write;
input [63:0] SPORT_data;
input [5:0] word_length;
input [5:0] p2p;
input [5:0] pw;
integer i;
integer j;
begin
j = 0;
repeat (word_length) begin
@ (posedge wb_clk_i) begin
if (SPORT_data[j] == 1'b0) begin
SPORT0(pw);
end
else begin
SPORT1(pw);
end
j=j+1;
i = 0;
while(i <= p2p) begin
@ (posedge wb_clk_i) begin i=i+1; end
end
end
end
end
endtask
task SPORT0;
input [5:0] pw;
integer i;
begin
for (i = 0; i <= pw; i=i+1) begin
@(posedge wb_clk_i) zero_i = 1'b0;
end
zero_i = 1'b1;
end
endtask
task SPORT1;
input [5:0] pw;
integer i;
begin
for (i = 0; i <= pw; i=i+1) begin
@(posedge wb_clk_i) one_i = 1'b0;
end
one_i = 1'b1;
end
endtask
//Wishbone readn adn write tasks
task wb_rst;
begin
wb_rst_i = 1'b1;
#20 wb_rst_i = 1'b0;
end
endtask
task wb_write_async;
input [31:0] wb_data;
begin
@ (posedge wb_clk_i) begin
wb_addr_i = `SPORT_ADDR;
wb_dat_i = wb_data;
wb_stb_i = 1'b1;
wb_cyc_i = 1'b1;
wb_we_i = 1'b1;
end
@ (posedge wb_clk_i) begin
wb_addr_i = 6'h0;
wb_dat_i = 32'h0;
wb_stb_i = 1'b0;
wb_cyc_i = 1'b0;
wb_we_i = 1'b0;
end
end
endtask
task wb_write_sync;
input [31:0] wb_data;
begin
@ (posedge wb_clk_i) begin
wb_addr_i = `SPORT_ADDR;
wb_dat_i = wb_data;
wb_stb_i = 1'b1;
wb_cyc_i = 1'b1;
wb_we_i = 1'b1;
end
@ (posedge wb_clk_i) begin
wb_addr_i = `SPORT_ADDR;
wb_dat_i = wb_data;
wb_stb_i = 1'b1;
wb_cyc_i = 1'b1;
wb_we_i = 1'b1;
end
@ (posedge wb_clk_i) begin
wb_addr_i = 6'h0;
wb_dat_i = 32'h0;
wb_stb_i = 1'b0;
wb_cyc_i = 1'b0;
wb_we_i = 1'b0;
end
end
endtask
task wb_writep2p_async;
input [31:0] p2p;
begin
@ (posedge wb_clk_i) begin
wb_addr_i = `WB_CNFG_RX;
wb_dat_i = p2p;
wb_stb_i = 1'b1;
wb_cyc_i = 1'b1;
wb_we_i = 1'b1;
end
@ (posedge wb_clk_i) begin
wb_addr_i = 6'h0;
wb_dat_i = 32'h0;
wb_stb_i = 1'b0;
wb_cyc_i = 1'b0;
wb_we_i = 1'b0;
end
end
endtask
task wb_writepw_async;
input [31:0] pw;
begin
@ (posedge wb_clk_i) begin
wb_addr_i = `WB_CNFG_TX;
wb_dat_i = pw;
wb_stb_i = 1'b1;
wb_cyc_i = 1'b1;
wb_we_i = 1'b1;
end
@ (posedge wb_clk_i) begin
wb_addr_i = 6'h0;
wb_dat_i = 32'h0;
wb_stb_i = 1'b0;
wb_cyc_i = 1'b0;
wb_we_i = 1'b0;
end
end
endtask
task wb_read_async;
begin
@ (posedge wb_clk_i) begin
wb_stb_i = 1'b1;
wb_cyc_i = 1'b1;
wb_we_i = 1'b0;
end
@ (posedge wb_clk_i) begin
wb_stb_i = 1'b0;
wb_cyc_i = 1'b0;
end
end
endtask
task wb_read_sync;
begin
@ (posedge wb_clk_i) begin
wb_stb_i = 1'b1;
wb_cyc_i = 1'b1;
wb_we_i = 1'b0;
end
@ (posedge wb_clk_i) begin
wb_stb_i = 1'b1;
wb_cyc_i = 1'b1;
end
@ (posedge wb_clk_i) begin
wb_stb_i = 1'b0;
wb_cyc_i = 1'b0;
end
end
endtask
endmodule
/sport/trunk/bench/timescale.v
0,0 → 1,63
//////////////////////////////////////////////////////////////////////
//// ////
//// timescale.v ////
//// ////
//// ////
//// This file is part of the CAN Protocol Controller ////
//// http://www.opencores.org/projects/can/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// igorm@opencores.org ////
//// ////
//// ////
//// All additional information is available in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002, 2003 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//// The CAN protocol is developed by Robert Bosch GmbH and ////
//// protected by patents. Anybody who wants to implement this ////
//// CAN IP core on silicon has to obtain a CAN protocol license ////
//// from Bosch. ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2002/12/27 00:12:48 mohor
// Header changed, testbench improved to send a frame (crc still missing).
//
// Revision 1.1.1.1 2002/12/20 16:39:21 mohor
// Initial
//
//
//
`timescale 1ns/1ps
/sport/trunk/bench/testcase_1.v.bak
0,0 → 1,96
//////////////////////////////////////////////////////////////////////
//// ////
//// weigand_tx_top.v ////
//// ////
//// ////
//// This file is part of the Time Triggered Protocol Controller ////
//// http://www.opencores.org/projects/weigand/ ////
//// ////
//// ////
//// Author(s): ////
//// Jeff Anderson ////
//// jeaander@opencores.org ////
//// ////
//// ////
//// All additional information is available in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2013 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//// The Weigand protocol is maintained by ////
//// This product has been tested to interoperate with certified ////
//// devices, but has not been certified itself. This product ////
//// should be certified through prior to claiming strict ////
//// adherence to the standard. ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// Revisions at end of file
//
 
`include "timescale.v"
`include "wiegand_defines.v"
`include "testbench_top.v"
 
module testcase_1;
testbench_top testbench();
initial
begin
testbench.wb_rst;
//#40 testbench.wb_write_async(32'h0);
//#40 testbench.wb_write_sync(32'h0);
//#40 testbench.wb_read_async;
//#40 testbench.wb_read_sync;
//write a small word adn send
#40 testbench.wb_write_async(32'hA5A5A50F);
#40 testbench.wb_writep2p_async(32'h7);
#40 testbench.wb_writepw_async(32'h3);
#40 testbench.wb_writesize_async(32'h87);
#40 testbench.wb_writesend_async(32'h7);
#40 testbench.wiegand_write(32'hA5, 6'h5, 6'h7, 6'h3);
//now write a 32 bit word
#1040 testbench.wb_write_async(32'hA5A5A50F);
#40 testbench.wb_writep2p_async(32'h7);
#40 testbench.wb_writepw_async(32'h3);
#40 testbench.wb_writesend_async(32'b00011111);
#40 testbench.wiegand_write(32'hA5A5A50F, 6'h20, 6'h7, 6'h3);
//now write a 35 bit word
#4040 testbench.wb_write_async(32'hA5A5A50F);
#40 testbench.wb_write_async(32'h33333333);
#40 testbench.wb_writep2p_async(32'h7);
#40 testbench.wb_writepw_async(32'h3);
#40 testbench.wb_writesend_async(32'b00100010);
#40 testbench.wiegand_write(40'hF0A5A5A50F, 6'h25, 6'h7, 6'h3);
#10000 $stop;
end
endmodule

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