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/tiny_encryption_algorithm/trunk/tea1tb.vhd
0,0 → 1,178
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:14:25 07/09/2015
-- Design Name:
-- Module Name: C:/Users/FeketeBV/projects/fpga/tea/tea1tb.vhd
-- Project Name: tea
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: tea1
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tea1tb IS
END tea1tb;
ARCHITECTURE behavior OF tea1tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT tea1
PORT(
clock, reset : IN std_logic;
start : IN std_logic;
ready : OUT std_logic;
key : IN std_logic_vector(127 downto 0);
text : IN std_logic_vector(63 downto 0);
cipher : OUT std_logic_vector(63 downto 0)
);
END COMPONENT;
 
--Inputs
signal reset : std_logic := '0';
signal clock : std_logic := '0';
signal start : std_logic := '0';
signal key : std_logic_vector(127 downto 0) := (others => '0');
signal text : std_logic_vector(63 downto 0) := (others => '0');
 
--Outputs
signal ready : std_logic;
signal cipher : std_logic_vector(63 downto 0);
 
-- Clock period definitions
constant clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: tea1 PORT MAP (
reset => reset,
clock => clock,
start => start,
ready => ready,
key => key,
text => text,
cipher => cipher
);
 
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset <= '1';
wait for 100 ns;
reset <= '0';
wait for clock_period*10;
key <= x"abcdef00111111111111111187654321";
text <= x"1234567812345678";
wait for clock_period;
start <= '1';
wait for clock_period;
start <= '0';
wait for clock_period*65;
wait;
 
-- insert stimulus here
 
wait;
end process;
 
END;
 
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/tiny_encryption_algorithm/trunk/tea64.vhd
0,0 → 1,46
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
 
entity tea64 is
port(
key : in std_logic_vector(127 downto 0);
text : in std_logic_vector(63 downto 0);
cipher : out std_logic_vector(63 downto 0)
);
end tea64;
 
architecture Behavioral of tea64 is
type teaA is array (64 downto 0) of std_logic_vector(31 downto 0);
signal v0,v1,sum,feistelOut,feistelKey0,feistelKey1 : teaA;
signal k0,k1,k2,k3 : std_logic_vector(31 downto 0);
begin
 
sum(0) <= x"9e3779b9";
k0 <= key(31 downto 0);
k1 <= key(63 downto 32);
k2 <= key(95 downto 64);
k3 <= key(127 downto 96);
v0(0) <= text(31 downto 0);
v1(0) <= text(63 downto 32);
 
general_pipe: for i in 1 to 64 generate
v1(i) <= v0(i-1) + feistelOut(i);
v0(i) <= v1(i-1);
end generate;
 
feistel_pipe_odd: for j in 0 to 31 generate
sum(2*j+1) <= sum(2*j);
feistelOut(2*j+1) <= (v1(2*j) + sum(2*j)) xor ((v1(2*j)(27 downto 0) & "0000") + k0) xor (("00000" & v1(2*j)(31 downto 5)) + k1);
end generate;
 
feistel_pipe_even: for k in 1 to 32 generate
sum(2*k) <= sum(2*k-1) + x"9e3779b9";
feistelOut(2*k) <= (v1(2*k-1) + sum(2*k-1)) xor ((v1(2*k-1)(27 downto 0) & "0000") + k2) xor (("00000" & v1(2*k-1)(31 downto 5)) + k3);
end generate;
 
cipher <= v1(64) & v0(64);
 
end Behavioral;
 
/tiny_encryption_algorithm/trunk/tea1.vhd
0,0 → 1,68
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
 
entity tea1 is
port(
clock, reset : in std_logic;
start : in std_logic;
ready : out std_logic;
key : in std_logic_vector(127 downto 0);
text : in std_logic_vector(63 downto 0);
cipher : out std_logic_vector(63 downto 0)
);
end tea1;
 
architecture Behavioral of tea1 is
signal cnt : std_logic_vector(6 downto 0);
signal k0,k1,k2,k3,v0,v1,sum,feistelOut,feistelKey0,feistelKey1 : std_logic_vector(31 downto 0);
begin
 
fcontrolling_fsm:process(reset, clock)
begin
if rising_edge(clock) then
if reset = '1' then
cnt <= (others => '1');
elsif cnt(6) = '1' then
if start = '1' then
cnt <= (others => '0');
end if;
else
cnt <= cnt + '1';
end if;
end if;
end process;
 
encryption:process(clock)
begin
if rising_edge(clock) then
if cnt(6) = '1' then
sum <= x"9e3779b9";
k0 <= key(31 downto 0);
k1 <= key(63 downto 32);
k2 <= key(95 downto 64);
k3 <= key(127 downto 96);
v0 <= text(31 downto 0);
v1 <= text(63 downto 32);
else
if cnt(0) = '1' then
sum <= sum + x"9e3779b9";
end if;
v1 <= v0 + feistelOut;
v0 <= v1;
end if;
end if;
end process;
 
--encryption asynchron parts
feistelKey0 <= k0 when cnt(0) = '0' else k2;
feistelKey1 <= k1 when cnt(0) = '0' else k3;
feistelOut <= (v1 + sum) xor ((v1(27 downto 0) & "0000") + feistelKey0) xor (("00000" & v1(31 downto 5)) + feistelKey1);
 
--output
cipher <= v1 & v0;
ready <= cnt(6);
 
end Behavioral;
 

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