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0,0 → 1,353
TWOFISH MANUAL |
|
(c) 2006 Spyros Ninos |
|
This document is under the GPL. See file COPYING for licence details. |
|
1. Introduction |
2. Crypto primitives usage |
3. Testbenches |
4. Misc + Tips |
|
NOTE (April 2006): for the time being the 256 bit key size functionality is not |
implemented. Testing and debugging is very time consuming. Bare with me :) |
|
1. INTRODUCTION |
=============== |
|
Twofish is a 128bit-block symmetric cipher, finalist candidate for the AES contest. |
It supports keys of 128, 192, 256 and all the sizes below 256 bits (with padding). This |
implementation accepts keys of 128, 192 and 256 bits. If you want a different size then |
you'll have to create the padder yourself. The implementation was written in a VHDL 87 |
and 93 mixed versions. Just to be sure, use the 93 version in compilation. The naming |
convention for the components is kept as simple but self-explanatory as I could. I had |
in mind that it would be possible to use two or three ciphers in the same design, so |
names are such that there would be no name-conflict (I hope...). For every key-depended |
component the respective key size was used in the name to indicate the component's |
target (i.e twofish_S128 is for 128 bit key). The cipher components are pure |
combinational circuits. This decision was based upon the assumption of portability. |
Since no memory is used, it can be implemented in any programmable device. Also, maximum |
flexibility was intended by dividing the cipher in key-parts. By doing this, you |
have the choice to implement the cipher as a rolled out, iterative, pipelined or any |
other architecture you may like to build. |
|
2. CRYPTO PRIMITIVES USAGE |
========================== |
|
The twofish.vhd file is divided in four parts. Firstly, there's the part where all |
the key-independent components are found. The next three parts concern the components |
that depend on the key - 128, 192 and 256 bits respectively. |
|
In the file you'll find the below main components: |
|
1) twofish_data_input |
2) twofish_data_output |
3) twofish_S128 |
4) twofish_keysched128 |
5) twofish_whit_keysched128 |
6) twofish_encryption_round128 |
7) twofish_decryption_round128 |
8) twofish_S192 |
9) twofish_keysched192 |
10) twofish_whit_keysched192 |
11) twofish_encryption_round192 |
12) twofish_decryption_round192 |
|
(NOTE: 256 bit components are not implemented yet). |
|
You'll also find all the other components that the above depend on, but they are not |
important in building the cipher - except perhaps if you want to study the structure |
of this implementation and/or modify it. A short description of them follows: |
|
1) The first component is the TWOFISH_DATA_INPUT, which is a simple tranformation of the |
input data from the way we provide it (which is big endian) to little endian convention, |
as required by the twofish specification. It must be used as an interface between the |
input data provided to the circuit and the rest of the cipher. An alternative would be |
to extract the code from it and integrate it to another component. Note that since the |
data block size of the cipher is always 128 bits, this component is supposed to be used |
with the components of all the key-sizes. The interface of the component is as follows: |
|
entity twofish_data_input is |
port ( |
in_tdi : in std_logic_vector(127 downto 0); |
out_tdi : out std_logic_vector(127 downto 0) |
); |
end twofish_data_input; |
|
It is quite simple; in_tdi is the data input as we provide it and out_tdi is the |
transformed input data. (tdi comes from the Twofish Data Input) |
|
2) The component TWOFISH_DATA_OUTPUT makes the reverse procedure of the twofish_data_input. |
It takes the little endian convention cipher result and transforms it to the big endian |
one, as the specification requires. This component too is supposed to be used with the |
components of all the key-sizes. The interface is as follows: |
|
entity twofish_data_output is |
port ( |
in_tdo : in std_logic_vector(127 downto 0); |
out_tdo : out std_logic_vector(127 downto 0) |
); |
end twofish_data_output; |
|
in_tdo accepts the ciphertext as we take it from the last round and out_tdo is the |
tranformed ciphertext. (tdo comes from the Twofish Data Output) |
|
3) The TWOFISH_S128 is a component that takes the key of 128 bits and produces the S0 |
and S1 for the f function. The interface is as follows: |
|
entity twofish_S128 is |
port ( |
in_key_ts128 : in std_logic_vector(127 downto 0); |
out_Sfirst_ts128, |
out_Ssecond_ts128 : out std_logic_vector(31 downto 0) |
); |
end twofish_S128; |
|
Here, in_key_ts128 is the key that we provide. Note that there is no component that |
transforms the key to the form that the twofish specification requires; rather the |
tranformation takes place within the twofish_S128 component. Here, there is the |
assumption/association that Sfirst refers to S0 and Ssecond refers to S1. There is |
no need to remember the association, since throughout the design, the same rule |
is followed, so the only thing you have to do it to connect the pins with the |
same name. This component can be used only when you implement a 128 bit key size |
design. (ts128 comes from Twofish_S128) |
|
|
4) The TWOFISH_KEYSCHED128 component is the key scheduler of the twofish cipher, |
for 128 bit keys. It's interface is as follows: |
|
entity twofish_keysched128 is |
port ( |
odd_in_tk128, |
even_in_tk128 : in std_logic_vector(7 downto 0); |
in_key_tk128 : in std_logic_vector(127 downto 0); |
out_key_up_tk128, |
out_key_down_tk128 : out std_logic_vector(31 downto 0) |
); |
end twofish_keysched128; |
|
odd_in_tk128 and even_in_tk128 are the numbers of the round 2i and 2i+1, as described |
in the specification. Clearly, 2i relates to the even_in_tk128 and 2i+1 relates to |
the odd_in_tk128. in_key_tk128 is where the key goes. The key must be supplied to the |
components without any endian-transformation; the tranformation takes place in the |
component, as in twofish_S128. out_key_up_tk128 and out_key_down_tk128 are the two |
keys produced from the scheduler. The association is that as we look the twofish |
diagram provided in the specification page 11 (figure 3), the upper key is what we |
get from out_key_up_tk128 and the down key is what we get from out_key_down_tk128. |
As before, you don't have to remember the association, names are used the same throughout |
the whole design. This component too, can be used only when you implement a 128 bit key |
size design. (tk128 comes from Twofish_Keysched128). |
|
IMPORTANT NOTICE: This component can be used in two ways: in combination with |
twofish_whit_keysched128 (see below) or as a standalone component. In the first |
case, whitening keys are produced by twofish_whit_keysched128; so even_in_tk128 and |
odd_in_tk128 must start from 8,9 respectively and above. Or if you use it standalone |
then you can start from 0 and above. |
|
5) The TWOFISH_WHIT_KEYSCHED128 produces the whitening keys K0..K7. The interface |
is as follows: |
|
entity twofish_whit_keysched128 is |
port ( |
in_key_twk128 : in std_logic_vector(127 downto 0); |
out_K0_twk128, |
out_K1_twk128, |
out_K2_twk128, |
out_K3_twk128, |
out_K4_twk128, |
out_K5_twk128, |
out_K6_twk128, |
out_K7_twk128 : out std_logic_vector(31 downto 0) |
); |
end twofish_whit_keysched128; |
|
in_key_twk128 is where the key is connected. As above, no big-little endian tranformation |
must take place. It is performed within the component. The eight outputs produce the |
keys. This component too can be used only when you implement a 128 bit key size design. |
(twk128 comes from Twofish_Whit_Keysched128). |
|
IMPORTANT NOTICE: If this component is to be used as a combination with twofish_keysched128 |
care should be taken when supplying numbers to the latter. Read the notice of the |
twofish_keysched128. |
|
6) The TWOFISH_ENCRYPTION_ROUND128 is the component that implements one round of encryption. |
The interface is as follows: |
|
entity twofish_encryption_round128 is |
port ( |
in1_ter128, |
in2_ter128, |
in3_ter128, |
in4_ter128, |
in_Sfirst_ter128, |
in_Ssecond_ter128, |
in_key_up_ter128, |
in_key_down_ter128 : in std_logic_vector(31 downto 0); |
out1_ter128, |
out2_ter128, |
out3_ter128, |
out4_ter128 : out std_logic_vector(31 downto 0) |
); |
end twofish_encryption_round128; |
|
in1_ter128, in1_ter128, in1_ter128, in1_ter128 are the four 32 bit inputs to the cipher |
round. in_Sfirst_ter128, in_Ssecond_ter128 are the two S needed for the g functions, |
in_key_up_ter128 and in_key_down_ter128 are the two round keys. Note that up and down |
names are given to keys according to the diagram given in Twofish spec. You don't need |
to worry about it, keys follow the same naming convention throughout the whole design. |
Finally, out1_ter128, out1_ter228, out3_ter128 and out4_ter128 are the 32 bit outputs |
of the encryption round. |
|
IMPORTANT NOTICE: the output swapping is taking place IN the component. YOU HAVE TO undo |
the last swap after the 16th round. |
|
7) The TWOFISH_DECRYPTION_ROUND128 is the component tha implements one round of decryption. |
The interface is as follows: |
|
entity twofish_decryption_round128 is |
port ( |
in1_tdr128, |
in2_tdr128, |
in3_tdr128, |
in4_tdr128, |
in_Sfirst_tdr128, |
in_Ssecond_tdr128, |
in_key_up_tdr128, |
in_key_down_tdr128 : in std_logic_vector(31 downto 0); |
out1_tdr128, |
out2_tdr128, |
out3_tdr128, |
out4_tdr128 : out std_logic_vector(31 downto 0) |
); |
end twofish_decryption_round128; |
|
As in twofish_encryption_round128 component, the ports are quite self-explanatory. |
|
IMPORTANT NOTICE: as in twofish_encryption_round128, inside the component the output |
swapping is taking place. YOU HAVE TO undo the last swap after the 16th round. |
|
|
Components |
|
8) twofish_S192 |
9) twofish_keysched192 |
10) twofish_whit_keysched192 |
11) twofish_encryption_round192 |
12) twofish_decryption_round192 |
|
work exactly as their 128 bit counterparts. The only difference is the third S that |
is provided by twofish_S192 and needed by some of the rest of them. I.e: |
|
entity twofish_S192 is |
port ( |
in_key_ts192 : in std_logic_vector(191 downto 0); |
out_Sfirst_ts192, |
out_Ssecond_ts192, |
out_Sthird_ts192 : out std_logic_vector(31 downto 0) |
); |
end twofish_S192; |
|
which provide a third S that is used in twofish encryption and decryption rounds. |
Every IMPORTANT NOTICE that exist for the 128 bit components, are valid for |
these components too. |
|
|
3. TESTBENCHES |
============== |
|
Testbenches for the cipher are provided for Tables, Variable key, Variable text, |
ECB/CBC Monte Carlo encryption and decryption tests. Every testbench comes with |
it's respective testvector file. The testvector file is transformed into a form |
that it's easier to be manipulated, than in the original form supplied by the |
cipher designer(s). |
|
Every testbench produces a file with the results, that can be cross-checked |
with the testvector file of input - just to be certain that results are as |
expected (usually with "diff"). |
|
Along with the transformed testvector files, the orignal testvector files - which |
are provided by the cipher designer(s) - are given. That way, you can check the |
originality of the transformed testvector files if you want to. |
|
Finally, some secondary circuits are provided for the testbenches to work. These |
are a 128 bit register, a mux and demux for 128 bit input(s)/output(s). |
|
4. MISC + TIPS |
============== |
|
You must pay attention in the whitening steps. None of the components actually |
implements the input or output whitening steps. You only have the component |
that produces the whitening keys. |
|
Each cipher implementation was designed so as to demand as few components as |
possible. That way, there would be no difficulty in using them and designing |
the algo in its total. The problem is that the Reed Solomon used to produce |
the S keys is in a rolled-out form, because I chose not to use any form of |
memory. So, if you want to implement more that one key size cipher in the |
same circuit/FPGA, the design size grows very much, and I doubt if it will |
fit in a signle FPGA. If you decide that you need more that one cipher |
instantiation, then you'll have to tweak the design of the Reed Solomon. |
One example follows: |
|
Current implementaion is that the reed solomon components are specifically |
designed for the key size of the cipher, i.e for 128 bits key: |
|
entity reed_solomon128 is |
port ( |
in_rs128 : in std_logic_vector(127 downto 0); |
out_Sfirst_rs128, |
out_Ssecond_rs128 : out std_logic_vector(31 downto 0) |
); |
end reed_solomon128; |
|
and for 192 bits key: |
|
entity reed_solomon192 is |
port ( |
in_rs192 : in std_logic_vector(191 downto 0); |
out_Sfirst_rs192, |
out_Ssecond_rs192, |
out_Sthird_rs192 : out std_logic_vector(31 downto 0) |
); |
end reed_solomon192; |
|
What is happening, is that each component takes the input key, and performs the |
multiplications in rolled-out form of every 64 bit input. In other terms, in_rs128 |
is split up in two 64 bit chunks, and each one is driven in it's respective |
multipliers. The result of the first multipliers is driven to out_Sfirst, the result |
of the second to out_Ssecond. Respectively for reed_solomon192 the result of the |
third multiplier is driven to out_Sthird. Every multiplication needs it's |
multipliers (note that it is not a single mul, but a group of them because its |
a matrix multiplication) so in the first component we need two groups of muls and |
in the second component three groups of them. |
|
If you had to implement cipher with 128 and 192 sizes you'd have to implement both |
reed solomon components which total in 5 groups of multipliers. One solution would |
be to create a reed solomon that would take a single 64 bit input and procude a |
single 32 bit output. For example: |
|
entity reed_solomon is |
port ( |
in_rs : in std_logic_vector(63 downto 0); |
out_S_rs : out std_logic_vector(31 downto 0) |
); |
end reed_solomon; |
|
|
Then you would divide the key into 64 bit chunks (128 bit in 2 chunks, 192 bit |
in 3 chunks) and provide them to the component sequentially. The results of |
the reed_solomon could be stored in a sort of RAM. That way you may slow down |
the process but you get to implement only one group of multipliers and you gain |
a lot in space. |
|
The same goes for the whitening keys components. In the whitening components |
the function h is impemented 16 times (2 h functions for each pair of keys, |
for the first 8 keys - K0..7). You could follow the above example and implement |
a component that accepts a 64 bit input (key chunk, every M is 32 bit, you need |
2 Ms for every h function) and produce a single 32 bit key. Thus, you can |
produce every key sequentially and store it in a RAM for example. |
|
If you want some implementation examples, you'll have to read the testbenches. |
The cipher is implemented in iterated mode, but you'll get a clear picture of how |
to connect the components. |
|
/trunk/test_vectors/twofish_ecb_vt_testvalues_192bits.txt
0,0 → 1,256
80000000000000000000000000000000 |
62EF193EDB7D399ACA50EC1CBE5398D8 |
40000000000000000000000000000000 |
E7A58D547688BA8B69DA949E38AA6FAD |
20000000000000000000000000000000 |
71579F70A8EDB2BA5C00C513E2D7DEEB |
10000000000000000000000000000000 |
C6171EF892F8224DC5FAE230AF629F52 |
08000000000000000000000000000000 |
C6A61053C48D7ECD7DDD12DB0F316AD7 |
04000000000000000000000000000000 |
EA5833714F1324DAB7F53CACC63F784F |
02000000000000000000000000000000 |
450BCB0C7351CB1CDAC5D02E80D13C64 |
01000000000000000000000000000000 |
C267D3634F84215FB7B4635AFA385E52 |
00800000000000000000000000000000 |
6DB5B1B156DA1C36B9AB5AB59B063C29 |
00400000000000000000000000000000 |
EDF2D9B19FF75561E8FA6F411C4A0431 |
00200000000000000000000000000000 |
A11AE84E6D2C56DED2B9497FEC7504A7 |
00100000000000000000000000000000 |
B3A1A1E271BF94DA3A5ECFF1D4293A56 |
00080000000000000000000000000000 |
5577374ADCF2F58EEEFFC432C42AEB76 |
00040000000000000000000000000000 |
CD9D355C3574343BC7FBE645CE7EA721 |
00020000000000000000000000000000 |
76EB4C046F052AE4ED41060BF60067FB |
00010000000000000000000000000000 |
1273A4BC420BCC9E29619567B1E61762 |
00008000000000000000000000000000 |
1F80E1CE3F12C96F2E647BACB6DA78D8 |
00004000000000000000000000000000 |
12D34A7875E716B37A7E250D37AFFDEA |
00002000000000000000000000000000 |
5A54D764EEFFC4B64143A58B071514B4 |
00001000000000000000000000000000 |
F4F1567BDC5B1F938D5A214419090FE0 |
00000800000000000000000000000000 |
6CB91B935A0FBF49636CDF64A12955B7 |
00000400000000000000000000000000 |
C082154A07AF64FF6ECA811B0E3302E6 |
00000200000000000000000000000000 |
49A746CC225C1B6009A93649CDD9EDCD |
00000100000000000000000000000000 |
1CAD0512E3CC51210B411EE452DF62E4 |
00000080000000000000000000000000 |
4FE9A0CF34BBCFFF906D8450197CC9D1 |
00000040000000000000000000000000 |
38DB8EF6C8993F17BB4D1614B9DE15D4 |
00000020000000000000000000000000 |
08DB3F476F551D19D9643A9E139E0553 |
00000010000000000000000000000000 |
F0F518F73795AB51BFB6E0AA99A0DAC7 |
00000008000000000000000000000000 |
91544D597F679E7DFE6D16D475809851 |
00000004000000000000000000000000 |
B1F92601B6D8C6B81176A46EE7341D28 |
00000002000000000000000000000000 |
796C3A8CBC6450E51FA6F8765ACD0F10 |
00000001000000000000000000000000 |
5F7BFE71BD2E81599DDA3411BC1CA579 |
00000000800000000000000000000000 |
2DF7D576EC6296101CAB16012092C12C |
00000000400000000000000000000000 |
20769DE071FBE22AE49E7B3F5D646418 |
00000000200000000000000000000000 |
B6F5C012E4BA15DC86536F328B137FC0 |
00000000100000000000000000000000 |
1C3031DD05EAA4C278B55EF0E7E4C1F9 |
00000000080000000000000000000000 |
3D72A53BD537D04AC59E0AF36D105ED9 |
00000000040000000000000000000000 |
A6FFE499A2050C38F4E89DBF12B27430 |
00000000020000000000000000000000 |
BFBB2A537B2C1339D6230F35A256F289 |
00000000010000000000000000000000 |
70E79718C97DDB187411436AC072B148 |
00000000008000000000000000000000 |
13BB56699085842B81DBE8FAA8B26269 |
00000000004000000000000000000000 |
3E4DB71B9C737C7F8AEF632A5ADEF61D |
00000000002000000000000000000000 |
D7A254B7341C7677C72F9DE729A3BB78 |
00000000001000000000000000000000 |
527D14E58B74224622DF7F3FD65932F5 |
00000000000800000000000000000000 |
708703993AD1DDE5C7F8714686F3AF32 |
00000000000400000000000000000000 |
C57D3ECB71A7DA4708DE6F338BC13E09 |
00000000000200000000000000000000 |
B31FF60BE0FDC17001CAF87FC7FC0B2D |
00000000000100000000000000000000 |
01877AC646A283472DA74182FDC1E2B5 |
00000000000080000000000000000000 |
3C678BADA3FB1B872C018DC035AE16E8 |
00000000000040000000000000000000 |
A2CB209DA6AA40E043E6FB9DD2476100 |
00000000000020000000000000000000 |
4F9402FF56D04C8FB37DBE1A3109D2DE |
00000000000010000000000000000000 |
342DAAD90F0F1699048D5CD16FDA2EC7 |
00000000000008000000000000000000 |
E68CC86CA4D952BC3890AEC0A7AAA4B5 |
00000000000004000000000000000000 |
02A88364BF94A677124F670A566E3F0D |
00000000000002000000000000000000 |
C961EF325E2A32A4359CC63BE1EE2C77 |
00000000000001000000000000000000 |
03BF43C9083E4D9919D12FE5C0315E67 |
00000000000000800000000000000000 |
B27063442470BE07DCC2256EC71A4F1A |
00000000000000400000000000000000 |
222CC5A29084A4BDB05D4C2FD95648DF |
00000000000000200000000000000000 |
E08686BFAA936E1890AEEC834E3B474A |
00000000000000100000000000000000 |
10DC4FFCAC5F5A1FB668277E8E75BEAB |
00000000000000080000000000000000 |
03A9199978F9D652A4C528FF86C39CE9 |
00000000000000040000000000000000 |
DDF718A1BEB37CC1B0905520DB7C1611 |
00000000000000020000000000000000 |
2072191C277EE40FD557FF5F67A2A546 |
00000000000000010000000000000000 |
96B3608C06112F619B156105EB082BBE |
00000000000000008000000000000000 |
B5D919DFD9828C4FF4427E72ABFC77B2 |
00000000000000004000000000000000 |
9570E7A96D4674C800AF8DCD01DEFF64 |
00000000000000002000000000000000 |
59723DB66EDB29A9C81175668903777F |
00000000000000001000000000000000 |
1779BDFAC6DB722BCAF4D3A8D9D2E725 |
00000000000000000800000000000000 |
5107B50A150998C6EA01C14697FC0E53 |
00000000000000000400000000000000 |
36A6CAA08BD5D2B332E9323F7C2E76CA |
00000000000000000200000000000000 |
D1CF37451667EDB8D2E9934D39A27A92 |
00000000000000000100000000000000 |
4E96227B0A018755FBE8AD5BF0E421B0 |
00000000000000000080000000000000 |
3221B3D3A24745B483BBF99509B330A0 |
00000000000000000040000000000000 |
98A4AB39B84D21D36A5DDC2660BD68C5 |
00000000000000000020000000000000 |
E5C351E1783465EDBA5CE0592BC77E8E |
00000000000000000010000000000000 |
35489488EE33D0344C1BDB6263D28286 |
00000000000000000008000000000000 |
97EA899F53C60536DAFEB18123FD6C5B |
00000000000000000004000000000000 |
8511B11C7D2D8FBF63702A7E3AACA08A |
00000000000000000002000000000000 |
FE0C90596E4F47FD8A9927D83F4DCA52 |
00000000000000000001000000000000 |
186FE000683CC19F621BC6C2DA300B71 |
00000000000000000000800000000000 |
8291F94EDF578E8A70CD0CF8F3FB3558 |
00000000000000000000400000000000 |
2891C81846949C917E757EBAE20D34EE |
00000000000000000000200000000000 |
762D85A32DAF0C9F3CFB3388E808FEC2 |
00000000000000000000100000000000 |
CC6807D209B728C559C32336FD8FB71D |
00000000000000000000080000000000 |
FCD07057EF4820154075A0DDCBFC0BBD |
00000000000000000000040000000000 |
FDBFE2C3FFC82792D338388A1FC6D22E |
00000000000000000000020000000000 |
04D5F7CD68FC2352BDDBC82CFE35DA80 |
00000000000000000000010000000000 |
B1784A7BF395FB525471EE3DC8972FED |
00000000000000000000008000000000 |
CB5D8A62D16220123EF0005876E35B19 |
00000000000000000000004000000000 |
311292EDE1F30E9F22F1EEF8FD19BD80 |
00000000000000000000002000000000 |
382BC583EC9B6E16E3DF2188CF0BF1E8 |
00000000000000000000001000000000 |
632C9AD674BD1B8A15827A789BD133A7 |
00000000000000000000000800000000 |
0EE175DF45B889CED6974E9C2B8F8A78 |
00000000000000000000000400000000 |
6131A1A18F00CFDA5B4AF4FBE5487445 |
00000000000000000000000200000000 |
0C8746747460A540E2304B55C12EA672 |
00000000000000000000000100000000 |
DD6D4D2AA3EB702C597E4E2DE59BF4C9 |
00000000000000000000000080000000 |
774EDF219459A4744AA1CCDE7D969A60 |
00000000000000000000000040000000 |
1D7B340C4CE68AC97369FFF0FF9980C8 |
00000000000000000000000020000000 |
D18104617258AB02AAE02ECCF552A891 |
00000000000000000000000010000000 |
8DC66F1D7648EB62F1DCBEB3CD237985 |
00000000000000000000000008000000 |
ABF090054ABE052ECE0B07BE6B6CC6DB |
00000000000000000000000004000000 |
89239AAFE9BA86E5EC794397E0180111 |
00000000000000000000000002000000 |
6E1CDC049333211B4D7533E21504D200 |
00000000000000000000000001000000 |
EFE662AF24D9997FAE45CAD4F92F3091 |
00000000000000000000000000800000 |
16F53F3A6CC3B4F86DDA1B8792244901 |
00000000000000000000000000400000 |
047CBACDC5EA84771A61FE1204813D46 |
00000000000000000000000000200000 |
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/trunk/test_vectors/twofish_ecb_encryption_monte_carlo_testvalues_128bits.txt
0,0 → 1,1200
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BA954C33EFC212A8479CC373702B1154 |
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6D188F15E724676032D06956949B5200 |
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05A765973AB726C003135514196336BB |
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E047E85F6A7AC7382C317713A4BFCE6D |
3AF048616AC276FA3F7923EEE4C258D6 |
E047E85F6A7AC7382C317713A4BFCE6D |
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6B806410178C7696CB3FDFC7393A361E |
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9F69838998270BDE231F3E426DA79424 |
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5555E4B19652465617DF93C830D2E58D |
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2214953AEBC3F2B7763D84EF1F07C38A |
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CD24189F850F4CC7E9A2E139917458B5 |
37DB5A05E75CC0A954B44F2C28AF1281 |
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02593DF1DFE45D23D3348096B698DD3B |
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3DC890AD855F3AB887017ABBAEFF4785 |
7B0CA9B33312318D0A4ED83CA7B6C27B |
6F624654280373A8D486763394060358 |
52AAD6F9AD5C491053870C883AF944DD |
6F624654280373A8D486763394060358 |
24B0F2A510C0969C5D5B088A72BB210E |
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24B0F2A510C0969C5D5B088A72BB210E |
363F869194D5200EF0289FDBDB2C8970 |
4025A2CD2949FF82FEF49BD9936EECA3 |
363F869194D5200EF0289FDBDB2C8970 |
7F8C01B642BEB931D09EA057755B564B |
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7F8C01B642BEB931D09EA057755B564B |
6CB2E88883229EF57956CC46A6519FAE |
531B4BF3E8D5D846573CF7C840642546 |
6CB2E88883229EF57956CC46A6519FAE |
C7F02F063AE45B8ABCF656E0B99E79B8 |
94EB64F5D23183CCEBCAA128F9FA5CFE |
C7F02F063AE45B8ABCF656E0B99E79B8 |
ECA140EFA7AC1550BFD21B5F9F25D9C6 |
784A241A759D969C5418BA7766DF8538 |
ECA140EFA7AC1550BFD21B5F9F25D9C6 |
6759610DA9468421223A8C63612F7F2F |
1F134517DCDB12BD7622361407F0FA17 |
6759610DA9468421223A8C63612F7F2F |
C908C35B04BF4C01EC0E7F7A9CE5950F |
D61B864CD8645EBC9A2C496E9B156F18 |
C908C35B04BF4C01EC0E7F7A9CE5950F |
C746473C7BD25ABA81192CA45B9D1297 |
115DC170A3B604061B3565CAC0887D8F |
C746473C7BD25ABA81192CA45B9D1297 |
964AAC0F8E8D2F0194986862869C198F |
87176D7F2D3B2B078FAD0DA846146400 |
964AAC0F8E8D2F0194986862869C198F |
D389B0ED5100D51636C518D65BC6732C |
549EDD927C3BFE11B968157E1DD2172C |
D389B0ED5100D51636C518D65BC6732C |
E1350ADF51AB4542B2769E1B7D7739E7 |
B5ABD74D2D90BB530B1E8B6560A52ECB |
E1350ADF51AB4542B2769E1B7D7739E7 |
8CC867F824948CA2BDC56D0D50363ECD |
3963B0B5090437F1B6DBE66830931006 |
8CC867F824948CA2BDC56D0D50363ECD |
B732DF6CC184B01F9974DB17289FB41D |
/trunk/test_vectors/twofish_ecb_encryption_monte_carlo_testvalues_192bits.txt
0,0 → 1,1200
000000000000000000000000000000000000000000000000 |
00000000000000000000000000000000 |
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/trunk/test_vectors/twofish_ecb_vk_testvalues_128bits.txt
0,0 → 1,256
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/trunk/test_vectors/twofish_ecb_tbl_testvalues_128bits.txt
0,0 → 1,147
00000000000000000000000000000000 |
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/trunk/test_vectors/twofish_ecb_tbl_testvalues_192bits.txt
0,0 → 1,147
000000000000000000000000000000000000000000000000 |
00000000000000000000000000000000 |
EFA71F788965BD4453F860178FC19101 |
000000000000000000000000000000000000000000000000 |
EFA71F788965BD4453F860178FC19101 |
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/trunk/test_vectors/twofish_ecb_decryption_monte_carlo_testvalues_192bits.txt
0,0 → 1,1200
000000000000000000000000000000000000000000000000 |
00000000000000000000000000000000 |
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/trunk/test_vectors/twofish_ecb_vt_testvalues_128bits.txt
0,0 → 1,256
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/trunk/COPYING
0,0 → 1,339
GNU GENERAL PUBLIC LICENSE |
Version 2, June 1991 |
|
Copyright (C) 1989, 1991 Free Software Foundation, Inc. |
675 Mass Ave, Cambridge, MA 02139, USA |
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END OF TERMS AND CONDITIONS |
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Appendix: How to Apply These Terms to Your New Programs |
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If you develop a new program, and you want it to be of the greatest |
possible use to the public, the best way to achieve this is to make it |
free software which everyone can redistribute and change under these terms. |
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To do so, attach the following notices to the program. It is safest |
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the "copyright" line and a pointer to where the full notice is found. |
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<one line to give the program's name and a brief idea of what it does.> |
Copyright (C) 19yy <name of author> |
|
This program is free software; you can redistribute it and/or modify |
it under the terms of the GNU General Public License as published by |
the Free Software Foundation; either version 2 of the License, or |
(at your option) any later version. |
|
This program is distributed in the hope that it will be useful, |
but WITHOUT ANY WARRANTY; without even the implied warranty of |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
GNU General Public License for more details. |
|
You should have received a copy of the GNU General Public License |
along with this program; if not, write to the Free Software |
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
|
Also add information on how to contact you by electronic and paper mail. |
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If the program is interactive, make it output a short notice like this |
when it starts in an interactive mode: |
|
Gnomovision version 69, Copyright (C) 19yy name of author |
Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. |
This is free software, and you are welcome to redistribute it |
under certain conditions; type `show c' for details. |
|
The hypothetical commands `show w' and `show c' should show the appropriate |
parts of the General Public License. Of course, the commands you use may |
be called something other than `show w' and `show c'; they could even be |
mouse-clicks or menu items--whatever suits your program. |
|
You should also get your employer (if you work as a programmer) or your |
school, if any, to sign a "copyright disclaimer" for the program, if |
necessary. Here is a sample; alter the names: |
|
Yoyodyne, Inc., hereby disclaims all copyright interest in the program |
`Gnomovision' (which makes passes at compilers) written by James Hacker. |
|
<signature of Ty Coon>, 1 April 1989 |
Ty Coon, President of Vice |
|
This General Public License does not permit incorporating your program into |
proprietary programs. If your program is a subroutine library, you may |
consider it more useful to permit linking proprietary applications with the |
library. If this is what you want to do, use the GNU Library General |
Public License instead of this License. |
/trunk/vhdl/twofish_cbc_encryption_monte_carlo_testbench_128bits.vhd
0,0 → 1,413
-- Twofish_cbc_encryption_monte_carlo_testbench_128bits.vhd |
-- Copyright (C) 2006 Spyros Ninos |
-- |
-- This program is free software; you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation; either version 2 of the License, or |
-- (at your option) any later version. |
-- |
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU General Public License |
-- along with this library; see the file COPYING. If not, write to: |
-- |
-- Free Software Foundation |
-- 59 Temple Place - Suite 330 |
-- Boston, MA 02111-1307, USA. |
-- |
-- description : this file is the testbench for the Encryption Monte Carlo KAT of the twofish cipher with 128 bit key |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
use ieee.std_logic_textio.all; |
use ieee.std_logic_arith.all; |
use std.textio.all; |
|
entity cbc_encryption_monte_carlo_testbench128 is |
end cbc_encryption_monte_carlo_testbench128; |
|
architecture cbc_encryption128_monte_carlo_testbench_arch of cbc_encryption_monte_carlo_testbench128 is |
|
component reg128 |
port ( |
in_reg128 : in std_logic_vector(127 downto 0); |
out_reg128 : out std_logic_vector(127 downto 0); |
enable_reg128, reset_reg128, clk_reg128 : in std_logic |
); |
end component; |
|
component twofish_keysched128 |
port ( |
odd_in_tk128, |
even_in_tk128 : in std_logic_vector(7 downto 0); |
in_key_tk128 : in std_logic_vector(127 downto 0); |
out_key_up_tk128, |
out_key_down_tk128 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component twofish_whit_keysched128 |
port ( |
in_key_twk128 : in std_logic_vector(127 downto 0); |
out_K0_twk128, |
out_K1_twk128, |
out_K2_twk128, |
out_K3_twk128, |
out_K4_twk128, |
out_K5_twk128, |
out_K6_twk128, |
out_K7_twk128 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component twofish_encryption_round128 |
port ( |
in1_ter128, |
in2_ter128, |
in3_ter128, |
in4_ter128, |
in_Sfirst_ter128, |
in_Ssecond_ter128, |
in_key_up_ter128, |
in_key_down_ter128 : in std_logic_vector(31 downto 0); |
out1_ter128, |
out2_ter128, |
out3_ter128, |
out4_ter128 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component twofish_data_input |
port ( |
in_tdi : in std_logic_vector(127 downto 0); |
out_tdi : out std_logic_vector(127 downto 0) |
); |
end component; |
|
component twofish_data_output |
port ( |
in_tdo : in std_logic_vector(127 downto 0); |
out_tdo : out std_logic_vector(127 downto 0) |
); |
end component; |
|
component demux128 |
port ( in_demux128 : in std_logic_vector(127 downto 0); |
out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0); |
selection_demux128 : in std_logic |
); |
end component; |
|
component mux128 |
port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0); |
selection_mux128 : in std_logic; |
out_mux128 : out std_logic_vector(127 downto 0) |
); |
end component; |
|
component twofish_S128 |
port ( |
in_key_ts128 : in std_logic_vector(127 downto 0); |
out_Sfirst_ts128, |
out_Ssecond_ts128 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
FILE input_file : text is in "twofish_cbc_encryption_monte_carlo_testvalues_128bits.txt"; |
FILE output_file : text is out "twofish_cbc_encryption_monte_carlo_128bits_results.txt"; |
|
-- we create the functions that transform a number to text |
-- transforming a signle digit to a character |
function digit_to_char(number : integer range 0 to 9) return character is |
begin |
case number is |
when 0 => return '0'; |
when 1 => return '1'; |
when 2 => return '2'; |
when 3 => return '3'; |
when 4 => return '4'; |
when 5 => return '5'; |
when 6 => return '6'; |
when 7 => return '7'; |
when 8 => return '8'; |
when 9 => return '9'; |
end case; |
end; |
|
-- transforming multi-digit number to text |
function to_text(int_number : integer range 0 to 9999) return string is |
variable our_text : string (1 to 4) := (others => ' '); |
variable thousands, |
hundreds, |
tens, |
ones : integer range 0 to 9; |
begin |
ones := int_number mod 10; |
tens := ((int_number mod 100) - ones) / 10; |
hundreds := ((int_number mod 1000) - (int_number mod 100)) / 100; |
thousands := (int_number - (int_number mod 1000)) / 1000; |
our_text(1) := digit_to_char(thousands); |
our_text(2) := digit_to_char(hundreds); |
our_text(3) := digit_to_char(tens); |
our_text(4) := digit_to_char(ones); |
return our_text; |
end; |
|
signal odd_number, |
even_number : std_logic_vector(7 downto 0); |
|
signal input_data, |
output_data, |
twofish_key, |
to_encr_reg128, |
from_tdi_to_xors, |
to_output_whit_xors, |
from_xors_to_tdo, |
to_mux, to_demux, |
from_input_whit_xors, |
to_round, |
to_input_mux : std_logic_vector(127 downto 0) ; |
|
signal key_up, |
key_down, |
Sfirst, |
Ssecond, |
from_xor0, |
from_xor1, |
from_xor2, |
from_xor3, |
K0,K1,K2,K3, |
K4,K5,K6,K7 : std_logic_vector(31 downto 0); |
|
signal clk : std_logic := '0'; |
signal mux_selection : std_logic := '0'; |
signal demux_selection: std_logic := '0'; |
signal enable_encr_reg : std_logic := '0'; |
signal reset : std_logic := '0'; |
signal enable_round_reg : std_logic := '0'; |
|
-- begin the testbench arch description |
begin |
|
|
-- getting data to encrypt |
data_input: twofish_data_input |
port map ( |
in_tdi => input_data, |
out_tdi => from_tdi_to_xors |
); |
|
-- producing whitening keys K0..7 |
the_whitening_step: twofish_whit_keysched128 |
port map ( |
in_key_twk128 => twofish_key, |
out_K0_twk128 => K0, |
out_K1_twk128 => K1, |
out_K2_twk128 => K2, |
out_K3_twk128 => K3, |
out_K4_twk128 => K4, |
out_K5_twk128 => K5, |
out_K6_twk128 => K6, |
out_K7_twk128 => K7 |
); |
|
-- performing the input whitening XORs |
from_xor0 <= K0 XOR from_tdi_to_xors(127 downto 96); |
from_xor1 <= K1 XOR from_tdi_to_xors(95 downto 64); |
from_xor2 <= K2 XOR from_tdi_to_xors(63 downto 32); |
from_xor3 <= K3 XOR from_tdi_to_xors(31 downto 0); |
|
from_input_whit_xors <= from_xor0 & from_xor1 & from_xor2 & from_xor3; |
|
round_reg: reg128 |
port map ( in_reg128 => from_input_whit_xors, |
out_reg128 => to_input_mux, |
enable_reg128 => enable_round_reg, |
reset_reg128 => reset, |
clk_reg128 => clk ); |
|
input_mux: mux128 |
port map ( in1_mux128 => to_input_mux, |
in2_mux128 => to_mux, |
out_mux128 => to_round, |
selection_mux128 => mux_selection |
); |
|
|
-- creating a round |
the_keysched_of_the_round: twofish_keysched128 |
port map ( |
odd_in_tk128 => odd_number, |
even_in_tk128 => even_number, |
in_key_tk128 => twofish_key, |
out_key_up_tk128 => key_up, |
out_key_down_tk128 => key_down |
); |
|
producing_the_Skeys: twofish_S128 |
port map ( |
in_key_ts128 => twofish_key, |
out_Sfirst_ts128 => Sfirst, |
out_Ssecond_ts128 => Ssecond |
); |
|
the_encryption_circuit: twofish_encryption_round128 |
port map ( |
in1_ter128 => to_round(127 downto 96), |
in2_ter128 => to_round(95 downto 64), |
in3_ter128 => to_round(63 downto 32), |
in4_ter128 => to_round(31 downto 0), |
in_Sfirst_ter128 => Sfirst, |
in_Ssecond_ter128 => Ssecond, |
in_key_up_ter128 => key_up, |
in_key_down_ter128 => key_down, |
out1_ter128 => to_encr_reg128(127 downto 96), |
out2_ter128 => to_encr_reg128(95 downto 64), |
out3_ter128 => to_encr_reg128(63 downto 32), |
out4_ter128 => to_encr_reg128(31 downto 0) |
); |
|
encr_reg: reg128 |
port map ( in_reg128 => to_encr_reg128, |
out_reg128 => to_demux, |
enable_reg128 => enable_encr_reg, |
reset_reg128 => reset, |
clk_reg128 => clk ); |
|
output_demux: demux128 |
port map ( in_demux128 => to_demux, |
out1_demux128 => to_output_whit_xors, |
out2_demux128 => to_mux, |
selection_demux128 => demux_selection ); |
|
-- don't forget the last swap !!! |
from_xors_to_tdo(127 downto 96) <= K4 XOR to_output_whit_xors(63 downto 32); |
from_xors_to_tdo(95 downto 64) <= K5 XOR to_output_whit_xors(31 downto 0); |
from_xors_to_tdo(63 downto 32) <= K6 XOR to_output_whit_xors(127 downto 96); |
from_xors_to_tdo(31 downto 0) <= K7 XOR to_output_whit_xors(95 downto 64); |
|
taking_the_output: twofish_data_output |
port map ( |
in_tdo => from_xors_to_tdo, |
out_tdo => output_data |
); |
|
-- we create the clock |
clk <= not clk after 50 ns; -- period 100 ns |
|
|
cbc_emc_proc: process |
|
variable key_f, -- key input from file |
pt_f, -- plaintext from file |
ct_f, |
iv_f : line; -- ciphertext from file |
variable key_v, -- key vector input |
pt_v , -- plaintext vector |
ct_v, |
iv_v : std_logic_vector(127 downto 0); -- ciphertext vector |
|
variable counter_10000 : integer range 0 to 9999 := 0; -- counter for the 10.000 repeats in the 400 next ones |
variable counter_400 : integer range 0 to 399 := 0; -- counter for the 400 repeats |
variable round : integer range 0 to 16 := 0; -- holds the rounds |
variable PT, CT, CV, CTj_1 : std_logic_vector(127 downto 0) := (others => '0'); |
|
begin |
|
while not endfile(input_file) loop |
|
readline(input_file, key_f); |
readline(input_file, iv_f); |
readline(input_file, pt_f); |
readline(input_file,ct_f); |
hread(key_f,key_v); |
hread(iv_f, iv_v); |
hread(pt_f,pt_v); |
hread(ct_f,ct_v); |
|
twofish_key <= key_v; |
PT := pt_v; |
CV := iv_v; |
|
for counter_10000 in 0 to 9999 loop |
|
input_data <= PT xor CV; |
|
wait for 25 ns; |
reset <= '1'; |
wait for 50 ns; |
reset <= '0'; |
|
mux_selection <= '0'; |
demux_selection <= '1'; |
enable_encr_reg <= '0'; |
enable_round_reg <= '0'; |
wait for 50 ns; |
enable_round_reg <= '1'; |
wait for 50 ns; |
enable_round_reg <= '0'; |
|
-- the first round |
even_number <= "00001000"; -- 8 |
odd_number <= "00001001"; -- 9 |
wait for 50 ns; |
enable_encr_reg <= '1'; |
wait for 50 ns; |
enable_encr_reg <= '0'; |
demux_selection <= '1'; |
mux_selection <= '1'; |
|
-- the rest 15 rounds |
for round in 1 to 15 loop |
even_number <= conv_std_logic_vector(((round*2)+8), 8); |
odd_number <= conv_std_logic_vector(((round*2)+9), 8); |
wait for 50 ns; |
enable_encr_reg <= '1'; |
wait for 50 ns; |
enable_encr_reg <= '0'; |
end loop; |
|
-- taking final results |
demux_selection <= '0'; |
wait for 25 ns; |
|
CTj_1 := CT; |
CT := output_data; |
|
if ( counter_10000 = 0 ) then |
PT := CV; |
else |
PT := CTj_1; |
end if; -- counter_10000 = 0 |
|
CV := CT; |
|
assert false report "I=" & to_text(counter_400) & " R=" & to_text(counter_10000) severity note; |
|
end loop; -- counter_10000 |
|
hwrite(key_f, key_v); |
hwrite(iv_f, iv_v); |
hwrite(pt_f, pt_v); |
hwrite(ct_f,output_data); |
writeline(output_file,key_f); |
writeline(output_file, iv_f); |
writeline(output_file,pt_f); |
writeline(output_file,ct_f); |
|
assert (ct_v = output_data) report "file entry and encryption result DO NOT match!!! :( " severity failure; |
assert (ct_v /= output_data) report "Encryption I=" & to_text(counter_400) &" OK" severity note; |
|
counter_400 := counter_400 + 1; |
|
end loop; |
assert false report "***** CBC Encryption Monte Carlo Test with 128 bits key size ended succesfully! :) *****" severity failure; |
end process cbc_emc_proc; |
|
end cbc_encryption128_monte_carlo_testbench_arch; |
|
/trunk/vhdl/twofish_cbc_encryption_monte_carlo_testbench_192bits.vhd
0,0 → 1,421
-- Twofish_cbc_encryption_monte_carlo_testbench_192bits.vhd |
-- Copyright (C) 2006 Spyros Ninos |
-- |
-- This program is free software; you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation; either version 2 of the License, or |
-- (at your option) any later version. |
-- |
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU General Public License |
-- along with this library; see the file COPYING. If not, write to: |
-- |
-- Free Software Foundation |
-- 59 Temple Place - Suite 330 |
-- Boston, MA 02111-1307, USA. |
-- |
-- description : this file is the testbench for the Encryption Monte Carlo KAT of the twofish cipher with 192 bit key |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
use ieee.std_logic_textio.all; |
use ieee.std_logic_arith.all; |
use std.textio.all; |
|
entity cbc_encryption_monte_carlo_testbench192 is |
end cbc_encryption_monte_carlo_testbench192; |
|
architecture cbc_encryption192_monte_carlo_testbench_arch of cbc_encryption_monte_carlo_testbench192 is |
|
component reg128 |
port ( |
in_reg128 : in std_logic_vector(127 downto 0); |
out_reg128 : out std_logic_vector(127 downto 0); |
enable_reg128, reset_reg128, clk_reg128 : in std_logic |
); |
end component; |
|
component twofish_keysched192 |
port ( |
odd_in_tk192, |
even_in_tk192 : in std_logic_vector(7 downto 0); |
in_key_tk192 : in std_logic_vector(191 downto 0); |
out_key_up_tk192, |
out_key_down_tk192 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component twofish_whit_keysched192 |
port ( |
in_key_twk192 : in std_logic_vector(191 downto 0); |
out_K0_twk192, |
out_K1_twk192, |
out_K2_twk192, |
out_K3_twk192, |
out_K4_twk192, |
out_K5_twk192, |
out_K6_twk192, |
out_K7_twk192 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component twofish_encryption_round192 |
port ( |
in1_ter192, |
in2_ter192, |
in3_ter192, |
in4_ter192, |
in_Sfirst_ter192, |
in_Ssecond_ter192, |
in_Sthird_ter192, |
in_key_up_ter192, |
in_key_down_ter192 : in std_logic_vector(31 downto 0); |
out1_ter192, |
out2_ter192, |
out3_ter192, |
out4_ter192 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component twofish_data_input |
port ( |
in_tdi : in std_logic_vector(127 downto 0); |
out_tdi : out std_logic_vector(127 downto 0) |
); |
end component; |
|
component twofish_data_output |
port ( |
in_tdo : in std_logic_vector(127 downto 0); |
out_tdo : out std_logic_vector(127 downto 0) |
); |
end component; |
|
component demux128 |
port ( in_demux128 : in std_logic_vector(127 downto 0); |
out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0); |
selection_demux128 : in std_logic |
); |
end component; |
|
component mux128 |
port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0); |
selection_mux128 : in std_logic; |
out_mux128 : out std_logic_vector(127 downto 0) |
); |
end component; |
|
component twofish_S192 |
port ( |
in_key_ts192 : in std_logic_vector(191 downto 0); |
out_Sfirst_ts192, |
out_Ssecond_ts192, |
out_Sthird_ts192 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
FILE input_file : text is in "twofish_cbc_encryption_monte_carlo_testvalues_192bits.txt"; |
FILE output_file : text is out "twofish_cbc_encryption_monte_carlo_192bits_results.txt"; |
|
-- we create the functions that transform a number to text |
-- transforming a signle digit to a character |
function digit_to_char(number : integer range 0 to 9) return character is |
begin |
case number is |
when 0 => return '0'; |
when 1 => return '1'; |
when 2 => return '2'; |
when 3 => return '3'; |
when 4 => return '4'; |
when 5 => return '5'; |
when 6 => return '6'; |
when 7 => return '7'; |
when 8 => return '8'; |
when 9 => return '9'; |
end case; |
end; |
|
-- transforming multi-digit number to text |
function to_text(int_number : integer range 0 to 9999) return string is |
variable our_text : string (1 to 4) := (others => ' '); |
variable thousands, |
hundreds, |
tens, |
ones : integer range 0 to 9; |
begin |
ones := int_number mod 10; |
tens := ((int_number mod 100) - ones) / 10; |
hundreds := ((int_number mod 1000) - (int_number mod 100)) / 100; |
thousands := (int_number - (int_number mod 1000)) / 1000; |
our_text(1) := digit_to_char(thousands); |
our_text(2) := digit_to_char(hundreds); |
our_text(3) := digit_to_char(tens); |
our_text(4) := digit_to_char(ones); |
return our_text; |
end; |
|
signal odd_number, |
even_number : std_logic_vector(7 downto 0); |
|
signal input_data, |
output_data, |
to_encr_reg128, |
from_tdi_to_xors, |
to_output_whit_xors, |
from_xors_to_tdo, |
to_mux, to_demux, |
from_input_whit_xors, |
to_round, |
to_input_mux : std_logic_vector(127 downto 0) ; |
|
signal twofish_key : std_logic_vector(191 downto 0); |
|
signal key_up, |
key_down, |
Sfirst, |
Ssecond, |
Sthird, |
from_xor0, |
from_xor1, |
from_xor2, |
from_xor3, |
K0,K1,K2,K3, |
K4,K5,K6,K7 : std_logic_vector(31 downto 0); |
|
signal clk : std_logic := '0'; |
signal mux_selection : std_logic := '0'; |
signal demux_selection: std_logic := '0'; |
signal enable_encr_reg : std_logic := '0'; |
signal reset : std_logic := '0'; |
signal enable_round_reg : std_logic := '0'; |
|
-- begin the testbench arch description |
begin |
|
|
-- getting data to encrypt |
data_input: twofish_data_input |
port map ( |
in_tdi => input_data, |
out_tdi => from_tdi_to_xors |
); |
|
-- producing whitening keys K0..7 |
the_whitening_step: twofish_whit_keysched192 |
port map ( |
in_key_twk192 => twofish_key, |
out_K0_twk192 => K0, |
out_K1_twk192 => K1, |
out_K2_twk192 => K2, |
out_K3_twk192 => K3, |
out_K4_twk192 => K4, |
out_K5_twk192 => K5, |
out_K6_twk192 => K6, |
out_K7_twk192 => K7 |
); |
|
-- performing the input whitening XORs |
from_xor0 <= K0 XOR from_tdi_to_xors(127 downto 96); |
from_xor1 <= K1 XOR from_tdi_to_xors(95 downto 64); |
from_xor2 <= K2 XOR from_tdi_to_xors(63 downto 32); |
from_xor3 <= K3 XOR from_tdi_to_xors(31 downto 0); |
|
from_input_whit_xors <= from_xor0 & from_xor1 & from_xor2 & from_xor3; |
|
round_reg: reg128 |
port map ( in_reg128 => from_input_whit_xors, |
out_reg128 => to_input_mux, |
enable_reg128 => enable_round_reg, |
reset_reg128 => reset, |
clk_reg128 => clk ); |
|
input_mux: mux128 |
port map ( in1_mux128 => to_input_mux, |
in2_mux128 => to_mux, |
out_mux128 => to_round, |
selection_mux128 => mux_selection |
); |
|
|
-- creating a round |
the_keysched_of_the_round: twofish_keysched192 |
port map ( |
odd_in_tk192 => odd_number, |
even_in_tk192 => even_number, |
in_key_tk192 => twofish_key, |
out_key_up_tk192 => key_up, |
out_key_down_tk192 => key_down |
); |
|
producing_the_Skeys: twofish_S192 |
port map ( |
in_key_ts192 => twofish_key, |
out_Sfirst_ts192 => Sfirst, |
out_Ssecond_ts192 => Ssecond, |
out_Sthird_ts192 => Sthird |
); |
|
the_encryption_circuit: twofish_encryption_round192 |
port map ( |
in1_ter192 => to_round(127 downto 96), |
in2_ter192 => to_round(95 downto 64), |
in3_ter192 => to_round(63 downto 32), |
in4_ter192 => to_round(31 downto 0), |
in_Sfirst_ter192 => Sfirst, |
in_Ssecond_ter192 => Ssecond, |
in_Sthird_ter192 => Sthird, |
in_key_up_ter192 => key_up, |
in_key_down_ter192 => key_down, |
out1_ter192 => to_encr_reg128(127 downto 96), |
out2_ter192 => to_encr_reg128(95 downto 64), |
out3_ter192 => to_encr_reg128(63 downto 32), |
out4_ter192 => to_encr_reg128(31 downto 0) |
); |
|
encr_reg: reg128 |
port map ( in_reg128 => to_encr_reg128, |
out_reg128 => to_demux, |
enable_reg128 => enable_encr_reg, |
reset_reg128 => reset, |
clk_reg128 => clk ); |
|
output_demux: demux128 |
port map ( in_demux128 => to_demux, |
out1_demux128 => to_output_whit_xors, |
out2_demux128 => to_mux, |
selection_demux128 => demux_selection ); |
|
-- don't forget the last swap !!! |
from_xors_to_tdo(127 downto 96) <= K4 XOR to_output_whit_xors(63 downto 32); |
from_xors_to_tdo(95 downto 64) <= K5 XOR to_output_whit_xors(31 downto 0); |
from_xors_to_tdo(63 downto 32) <= K6 XOR to_output_whit_xors(127 downto 96); |
from_xors_to_tdo(31 downto 0) <= K7 XOR to_output_whit_xors(95 downto 64); |
|
taking_the_output: twofish_data_output |
port map ( |
in_tdo => from_xors_to_tdo, |
out_tdo => output_data |
); |
|
-- we create the clock |
clk <= not clk after 50 ns; -- period 100 ns |
|
|
cbc_emc_proc: process |
|
variable key_f, -- key input from file |
pt_f, -- plaintext from file |
ct_f, |
iv_f : line; -- ciphertext from file |
variable key_v : std_logic_vector(191 downto 0); -- key vector input |
variable pt_v , -- plaintext vector |
ct_v, |
iv_v : std_logic_vector(127 downto 0); -- ciphertext vector |
|
variable counter_10000 : integer range 0 to 9999 := 0; -- counter for the 10.000 repeats in the 400 next ones |
variable counter_400 : integer range 0 to 399 := 0; -- counter for the 400 repeats |
variable round : integer range 0 to 16 := 0; -- holds the rounds |
variable PT, CT, CV, CTj_1 : std_logic_vector(127 downto 0) := (others => '0'); |
|
begin |
|
|
|
while not endfile(input_file) loop |
|
readline(input_file, key_f); |
readline(input_file, iv_f); |
readline(input_file, pt_f); |
readline(input_file,ct_f); |
hread(key_f,key_v); |
hread(iv_f, iv_v); |
hread(pt_f,pt_v); |
hread(ct_f,ct_v); |
|
twofish_key <= key_v; |
PT := pt_v; |
CV := iv_v; |
|
for counter_10000 in 0 to 9999 loop |
|
input_data <= PT xor CV; |
|
wait for 25 ns; |
reset <= '1'; |
wait for 50 ns; |
reset <= '0'; |
|
mux_selection <= '0'; |
demux_selection <= '1'; |
enable_encr_reg <= '0'; |
enable_round_reg <= '0'; |
wait for 50 ns; |
enable_round_reg <= '1'; |
wait for 50 ns; |
enable_round_reg <= '0'; |
|
-- the first round |
even_number <= "00001000"; -- 8 |
odd_number <= "00001001"; -- 9 |
wait for 50 ns; |
enable_encr_reg <= '1'; |
wait for 50 ns; |
enable_encr_reg <= '0'; |
demux_selection <= '1'; |
mux_selection <= '1'; |
|
-- the rest 15 rounds |
for round in 1 to 15 loop |
even_number <= conv_std_logic_vector(((round*2)+8), 8); |
odd_number <= conv_std_logic_vector(((round*2)+9), 8); |
wait for 50 ns; |
enable_encr_reg <= '1'; |
wait for 50 ns; |
enable_encr_reg <= '0'; |
end loop; |
|
-- taking final results |
demux_selection <= '0'; |
wait for 25 ns; |
|
CTj_1 := CT; |
CT := output_data; |
|
if ( counter_10000 = 0 ) then |
PT := CV; |
else |
PT := CTj_1; |
end if; -- counter_10000 = 0 |
|
CV := CT; |
|
assert false report "I=" & to_text(counter_400) & " R=" & to_text(counter_10000) severity note; |
|
end loop; -- counter_10000 |
|
hwrite(key_f, key_v); |
hwrite(iv_f, iv_v); |
hwrite(pt_f, pt_v); |
hwrite(ct_f,output_data); |
writeline(output_file,key_f); |
writeline(output_file, iv_f); |
writeline(output_file,pt_f); |
writeline(output_file,ct_f); |
|
assert (ct_v = output_data) report "file entry and encryption result DO NOT match!!! :( " severity failure; |
assert (ct_v /= output_data) report "Encryption I=" & to_text(counter_400) &" OK" severity note; |
|
counter_400 := counter_400 + 1; |
|
end loop; |
assert false report "***** CBC Encryption Monte Carlo Test with 192 bits key size ended succesfully! :) *****" severity failure; |
end process cbc_emc_proc; |
|
end cbc_encryption192_monte_carlo_testbench_arch; |
|
/trunk/vhdl/twofish_ecb_encryption_monte_carlo_testbench_128bits.vhd
0,0 → 1,396
-- Twofish_ecb_encryption_monte_carlo_testbench_128bits.vhd |
-- Copyright (C) 2006 Spyros Ninos |
-- |
-- This program is free software; you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation; either version 2 of the License, or |
-- (at your option) any later version. |
-- |
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU General Public License |
-- along with this library; see the file COPYING. If not, write to: |
-- |
-- Free Software Foundation |
-- 59 Temple Place - Suite 330 |
-- Boston, MA 02111-1307, USA. |
-- |
-- description : this file is the testbench for the Encryption Monte Carlo KAT of the twofish cipher with 128 bit key |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
use ieee.std_logic_textio.all; |
use ieee.std_logic_arith.all; |
use std.textio.all; |
|
entity ecb_encryption_monte_carlo_testbench128 is |
end ecb_encryption_monte_carlo_testbench128; |
|
architecture ecb_encryption128_monte_carlo_testbench_arch of ecb_encryption_monte_carlo_testbench128 is |
|
component reg128 |
port ( |
in_reg128 : in std_logic_vector(127 downto 0); |
out_reg128 : out std_logic_vector(127 downto 0); |
enable_reg128, reset_reg128, clk_reg128 : in std_logic |
); |
end component; |
|
component twofish_keysched128 |
port ( |
odd_in_tk128, |
even_in_tk128 : in std_logic_vector(7 downto 0); |
in_key_tk128 : in std_logic_vector(127 downto 0); |
out_key_up_tk128, |
out_key_down_tk128 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component twofish_whit_keysched128 |
port ( |
in_key_twk128 : in std_logic_vector(127 downto 0); |
out_K0_twk128, |
out_K1_twk128, |
out_K2_twk128, |
out_K3_twk128, |
out_K4_twk128, |
out_K5_twk128, |
out_K6_twk128, |
out_K7_twk128 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component twofish_encryption_round128 |
port ( |
in1_ter128, |
in2_ter128, |
in3_ter128, |
in4_ter128, |
in_Sfirst_ter128, |
in_Ssecond_ter128, |
in_key_up_ter128, |
in_key_down_ter128 : in std_logic_vector(31 downto 0); |
out1_ter128, |
out2_ter128, |
out3_ter128, |
out4_ter128 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component twofish_data_input |
port ( |
in_tdi : in std_logic_vector(127 downto 0); |
out_tdi : out std_logic_vector(127 downto 0) |
); |
end component; |
|
component twofish_data_output |
port ( |
in_tdo : in std_logic_vector(127 downto 0); |
out_tdo : out std_logic_vector(127 downto 0) |
); |
end component; |
|
component demux128 |
port ( in_demux128 : in std_logic_vector(127 downto 0); |
out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0); |
selection_demux128 : in std_logic |
); |
end component; |
|
component mux128 |
port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0); |
selection_mux128 : in std_logic; |
out_mux128 : out std_logic_vector(127 downto 0) |
); |
end component; |
|
component twofish_S128 |
port ( |
in_key_ts128 : in std_logic_vector(127 downto 0); |
out_Sfirst_ts128, |
out_Ssecond_ts128 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
FILE input_file : text is in "twofish_ecb_encryption_monte_carlo_testvalues_128bits.txt"; |
FILE output_file : text is out "twofish_ecb_encryption_monte_carlo_128bits_results.txt"; |
|
-- we create the functions that transform a number to text |
-- transforming a signle digit to a character |
function digit_to_char(number : integer range 0 to 9) return character is |
begin |
case number is |
when 0 => return '0'; |
when 1 => return '1'; |
when 2 => return '2'; |
when 3 => return '3'; |
when 4 => return '4'; |
when 5 => return '5'; |
when 6 => return '6'; |
when 7 => return '7'; |
when 8 => return '8'; |
when 9 => return '9'; |
end case; |
end; |
|
-- transforming multi-digit number to text |
function to_text(int_number : integer range 0 to 9999) return string is |
variable our_text : string (1 to 4) := (others => ' '); |
variable thousands, |
hundreds, |
tens, |
ones : integer range 0 to 9; |
begin |
ones := int_number mod 10; |
tens := ((int_number mod 100) - ones) / 10; |
hundreds := ((int_number mod 1000) - (int_number mod 100)) / 100; |
thousands := (int_number - (int_number mod 1000)) / 1000; |
our_text(1) := digit_to_char(thousands); |
our_text(2) := digit_to_char(hundreds); |
our_text(3) := digit_to_char(tens); |
our_text(4) := digit_to_char(ones); |
return our_text; |
end; |
|
signal odd_number, |
even_number : std_logic_vector(7 downto 0); |
|
signal input_data, |
output_data, |
twofish_key, |
to_encr_reg128, |
from_tdi_to_xors, |
to_output_whit_xors, |
from_xors_to_tdo, |
to_mux, to_demux, |
from_input_whit_xors, |
to_round, |
to_input_mux : std_logic_vector(127 downto 0) ; |
|
signal key_up, |
key_down, |
Sfirst, |
Ssecond, |
from_xor0, |
from_xor1, |
from_xor2, |
from_xor3, |
K0,K1,K2,K3, |
K4,K5,K6,K7 : std_logic_vector(31 downto 0); |
|
signal clk : std_logic := '0'; |
signal mux_selection : std_logic := '0'; |
signal demux_selection: std_logic := '0'; |
signal enable_encr_reg : std_logic := '0'; |
signal reset : std_logic := '0'; |
signal enable_round_reg : std_logic := '0'; |
|
-- begin the testbench arch description |
begin |
|
|
-- getting data to encrypt |
data_input: twofish_data_input |
port map ( |
in_tdi => input_data, |
out_tdi => from_tdi_to_xors |
); |
|
-- producing whitening keys K0..7 |
the_whitening_step: twofish_whit_keysched128 |
port map ( |
in_key_twk128 => twofish_key, |
out_K0_twk128 => K0, |
out_K1_twk128 => K1, |
out_K2_twk128 => K2, |
out_K3_twk128 => K3, |
out_K4_twk128 => K4, |
out_K5_twk128 => K5, |
out_K6_twk128 => K6, |
out_K7_twk128 => K7 |
); |
|
-- performing the input whitening XORs |
from_xor0 <= K0 XOR from_tdi_to_xors(127 downto 96); |
from_xor1 <= K1 XOR from_tdi_to_xors(95 downto 64); |
from_xor2 <= K2 XOR from_tdi_to_xors(63 downto 32); |
from_xor3 <= K3 XOR from_tdi_to_xors(31 downto 0); |
|
from_input_whit_xors <= from_xor0 & from_xor1 & from_xor2 & from_xor3; |
|
round_reg: reg128 |
port map ( in_reg128 => from_input_whit_xors, |
out_reg128 => to_input_mux, |
enable_reg128 => enable_round_reg, |
reset_reg128 => reset, |
clk_reg128 => clk ); |
|
input_mux: mux128 |
port map ( in1_mux128 => to_input_mux, |
in2_mux128 => to_mux, |
out_mux128 => to_round, |
selection_mux128 => mux_selection |
); |
|
|
-- creating a round |
the_keysched_of_the_round: twofish_keysched128 |
port map ( |
odd_in_tk128 => odd_number, |
even_in_tk128 => even_number, |
in_key_tk128 => twofish_key, |
out_key_up_tk128 => key_up, |
out_key_down_tk128 => key_down |
); |
|
producing_the_Skeys: twofish_S128 |
port map ( |
in_key_ts128 => twofish_key, |
out_Sfirst_ts128 => Sfirst, |
out_Ssecond_ts128 => Ssecond |
); |
|
the_encryption_circuit: twofish_encryption_round128 |
port map ( |
in1_ter128 => to_round(127 downto 96), |
in2_ter128 => to_round(95 downto 64), |
in3_ter128 => to_round(63 downto 32), |
in4_ter128 => to_round(31 downto 0), |
in_Sfirst_ter128 => Sfirst, |
in_Ssecond_ter128 => Ssecond, |
in_key_up_ter128 => key_up, |
in_key_down_ter128 => key_down, |
out1_ter128 => to_encr_reg128(127 downto 96), |
out2_ter128 => to_encr_reg128(95 downto 64), |
out3_ter128 => to_encr_reg128(63 downto 32), |
out4_ter128 => to_encr_reg128(31 downto 0) |
); |
|
encr_reg: reg128 |
port map ( in_reg128 => to_encr_reg128, |
out_reg128 => to_demux, |
enable_reg128 => enable_encr_reg, |
reset_reg128 => reset, |
clk_reg128 => clk ); |
|
output_demux: demux128 |
port map ( in_demux128 => to_demux, |
out1_demux128 => to_output_whit_xors, |
out2_demux128 => to_mux, |
selection_demux128 => demux_selection ); |
|
-- don't forget the last swap !!! |
from_xors_to_tdo(127 downto 96) <= K4 XOR to_output_whit_xors(63 downto 32); |
from_xors_to_tdo(95 downto 64) <= K5 XOR to_output_whit_xors(31 downto 0); |
from_xors_to_tdo(63 downto 32) <= K6 XOR to_output_whit_xors(127 downto 96); |
from_xors_to_tdo(31 downto 0) <= K7 XOR to_output_whit_xors(95 downto 64); |
|
taking_the_output: twofish_data_output |
port map ( |
in_tdo => from_xors_to_tdo, |
out_tdo => output_data |
); |
|
-- we create the clock |
clk <= not clk after 50 ns; -- period 100 ns |
|
|
ecb_emc_proc: process |
|
variable key_f, -- key input from file |
pt_f, -- plaintext from file |
ct_f : line; -- ciphertext from file |
variable key_v, -- key vector input |
pt_v , -- plaintext vector |
ct_v : std_logic_vector(127 downto 0); -- ciphertext vector |
|
variable counter_10000 : integer range 0 to 9999 := 0; -- counter for the 10.000 repeats in the 400 next ones |
variable counter_400 : integer range 0 to 399 := 0; -- counter for the 400 repeats |
variable round : integer range 0 to 16 := 0; -- holds the rounds |
variable intermediate_encryption_result : std_logic_vector(127 downto 0); -- holds the intermediate encryption result |
|
begin |
|
|
|
while not endfile(input_file) loop |
|
readline(input_file, key_f); |
readline(input_file, pt_f); |
readline(input_file,ct_f); |
hread(key_f,key_v); |
hread(pt_f,pt_v); |
hread(ct_f,ct_v); |
|
twofish_key <= key_v; |
intermediate_encryption_result := pt_v; |
|
for counter_10000 in 0 to 9999 loop |
input_data <= intermediate_encryption_result; |
|
wait for 25 ns; |
reset <= '1'; |
wait for 50 ns; |
reset <= '0'; |
|
mux_selection <= '0'; |
demux_selection <= '1'; |
enable_encr_reg <= '0'; |
enable_round_reg <= '0'; |
wait for 50 ns; |
enable_round_reg <= '1'; |
wait for 50 ns; |
enable_round_reg <= '0'; |
|
-- the first round |
even_number <= "00001000"; -- 8 |
odd_number <= "00001001"; -- 9 |
wait for 50 ns; |
enable_encr_reg <= '1'; |
wait for 50 ns; |
enable_encr_reg <= '0'; |
demux_selection <= '1'; |
mux_selection <= '1'; |
|
-- the rest 15 rounds |
for round in 1 to 15 loop |
even_number <= conv_std_logic_vector(((round*2)+8), 8); |
odd_number <= conv_std_logic_vector(((round*2)+9), 8); |
wait for 50 ns; |
enable_encr_reg <= '1'; |
wait for 50 ns; |
enable_encr_reg <= '0'; |
end loop; |
|
-- taking final results |
demux_selection <= '0'; |
wait for 25 ns; |
|
intermediate_encryption_result := output_data; |
|
assert false report "I=" & to_text(counter_400) & " R=" & to_text(counter_10000) severity note; |
|
end loop; -- counter_10000 |
|
hwrite(key_f, key_v); |
hwrite(pt_f, pt_v); |
hwrite(ct_f,output_data); |
writeline(output_file,key_f); |
writeline(output_file,pt_f); |
writeline(output_file,ct_f); |
|
assert (ct_v = output_data) report "file entry and encryption result DO NOT match!!! :( " severity failure; |
assert (ct_v /= output_data) report "Encryption I=" & to_text(counter_400) &" OK" severity note; |
counter_400 := counter_400 + 1; |
end loop; |
assert false report "***** ECB Encryption Monte Carlo Test with 128 bits key size ended succesfully! :) *****" severity failure; |
end process ecb_emc_proc; |
|
end ecb_encryption128_monte_carlo_testbench_arch; |
|
/trunk/vhdl/twofish_ecb_encryption_monte_carlo_testbench_192bits.vhd
0,0 → 1,402
-- Twofish_ecb_encryption_monte_carlo_testbench_192bits.vhd |
-- Copyright (C) 2006 Spyros Ninos |
-- |
-- This program is free software; you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation; either version 2 of the License, or |
-- (at your option) any later version. |
-- |
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU General Public License |
-- along with this library; see the file COPYING. If not, write to: |
-- |
-- Free Software Foundation |
-- 59 Temple Place - Suite 330 |
-- Boston, MA 02111-1307, USA. |
-- |
-- description : this file is the testbench for the Encryption Monte Carlo KAT of the twofish cipher with 192 bit key |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
use ieee.std_logic_textio.all; |
use ieee.std_logic_arith.all; |
use std.textio.all; |
|
entity ecb_encryption_monte_carlo_testbench192 is |
end ecb_encryption_monte_carlo_testbench192; |
|
architecture ecb_encryption192_monte_carlo_testbench_arch of ecb_encryption_monte_carlo_testbench192 is |
|
component reg128 |
port ( |
in_reg128 : in std_logic_vector(127 downto 0); |
out_reg128 : out std_logic_vector(127 downto 0); |
enable_reg128, reset_reg128, clk_reg128 : in std_logic |
); |
end component; |
|
component twofish_keysched192 |
port ( |
odd_in_tk192, |
even_in_tk192 : in std_logic_vector(7 downto 0); |
in_key_tk192 : in std_logic_vector(191 downto 0); |
out_key_up_tk192, |
out_key_down_tk192 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component twofish_whit_keysched192 |
port ( |
in_key_twk192 : in std_logic_vector(191 downto 0); |
out_K0_twk192, |
out_K1_twk192, |
out_K2_twk192, |
out_K3_twk192, |
out_K4_twk192, |
out_K5_twk192, |
out_K6_twk192, |
out_K7_twk192 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component twofish_encryption_round192 |
port ( |
in1_ter192, |
in2_ter192, |
in3_ter192, |
in4_ter192, |
in_Sfirst_ter192, |
in_Ssecond_ter192, |
in_Sthird_ter192, |
in_key_up_ter192, |
in_key_down_ter192 : in std_logic_vector(31 downto 0); |
out1_ter192, |
out2_ter192, |
out3_ter192, |
out4_ter192 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component twofish_data_input |
port ( |
in_tdi : in std_logic_vector(127 downto 0); |
out_tdi : out std_logic_vector(127 downto 0) |
); |
end component; |
|
component twofish_data_output |
port ( |
in_tdo : in std_logic_vector(127 downto 0); |
out_tdo : out std_logic_vector(127 downto 0) |
); |
end component; |
|
component demux128 |
port ( in_demux128 : in std_logic_vector(127 downto 0); |
out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0); |
selection_demux128 : in std_logic |
); |
end component; |
|
component mux128 |
port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0); |
selection_mux128 : in std_logic; |
out_mux128 : out std_logic_vector(127 downto 0) |
); |
end component; |
|
component twofish_S192 |
port ( |
in_key_ts192 : in std_logic_vector(191 downto 0); |
out_Sfirst_ts192, |
out_Ssecond_ts192, |
out_Sthird_ts192 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
FILE input_file : text is in "twofish_ecb_encryption_monte_carlo_testvalues_192bits.txt"; |
FILE output_file : text is out "twofish_ecb_encryption_monte_carlo_192bits_results.txt"; |
|
-- we create the functions that transform a number to text |
-- transforming a signle digit to a character |
function digit_to_char(number : integer range 0 to 9) return character is |
begin |
case number is |
when 0 => return '0'; |
when 1 => return '1'; |
when 2 => return '2'; |
when 3 => return '3'; |
when 4 => return '4'; |
when 5 => return '5'; |
when 6 => return '6'; |
when 7 => return '7'; |
when 8 => return '8'; |
when 9 => return '9'; |
end case; |
end; |
|
-- transforming multi-digit number to text |
function to_text(int_number : integer range 0 to 9999) return string is |
variable our_text : string (1 to 4) := (others => ' '); |
variable thousands, |
hundreds, |
tens, |
ones : integer range 0 to 9; |
begin |
ones := int_number mod 10; |
tens := ((int_number mod 100) - ones) / 10; |
hundreds := ((int_number mod 1000) - (int_number mod 100)) / 100; |
thousands := (int_number - (int_number mod 1000)) / 1000; |
our_text(1) := digit_to_char(thousands); |
our_text(2) := digit_to_char(hundreds); |
our_text(3) := digit_to_char(tens); |
our_text(4) := digit_to_char(ones); |
return our_text; |
end; |
|
signal odd_number, |
even_number : std_logic_vector(7 downto 0); |
|
signal input_data, |
output_data, |
to_encr_reg128, |
from_tdi_to_xors, |
to_output_whit_xors, |
from_xors_to_tdo, |
to_mux, to_demux, |
from_input_whit_xors, |
to_round, |
to_input_mux : std_logic_vector(127 downto 0) ; |
|
signal twofish_key : std_logic_vector(191 downto 0); |
|
signal key_up, |
key_down, |
Sfirst, |
Ssecond, |
Sthird, |
from_xor0, |
from_xor1, |
from_xor2, |
from_xor3, |
K0,K1,K2,K3, |
K4,K5,K6,K7 : std_logic_vector(31 downto 0); |
|
signal clk : std_logic := '0'; |
signal mux_selection : std_logic := '0'; |
signal demux_selection: std_logic := '0'; |
signal enable_encr_reg : std_logic := '0'; |
signal reset : std_logic := '0'; |
signal enable_round_reg : std_logic := '0'; |
|
-- begin the testbench arch description |
begin |
|
|
-- getting data to encrypt |
data_input: twofish_data_input |
port map ( |
in_tdi => input_data, |
out_tdi => from_tdi_to_xors |
); |
|
-- producing whitening keys K0..7 |
the_whitening_step: twofish_whit_keysched192 |
port map ( |
in_key_twk192 => twofish_key, |
out_K0_twk192 => K0, |
out_K1_twk192 => K1, |
out_K2_twk192 => K2, |
out_K3_twk192 => K3, |
out_K4_twk192 => K4, |
out_K5_twk192 => K5, |
out_K6_twk192 => K6, |
out_K7_twk192 => K7 |
); |
|
-- performing the input whitening XORs |
from_xor0 <= K0 XOR from_tdi_to_xors(127 downto 96); |
from_xor1 <= K1 XOR from_tdi_to_xors(95 downto 64); |
from_xor2 <= K2 XOR from_tdi_to_xors(63 downto 32); |
from_xor3 <= K3 XOR from_tdi_to_xors(31 downto 0); |
|
from_input_whit_xors <= from_xor0 & from_xor1 & from_xor2 & from_xor3; |
|
round_reg: reg128 |
port map ( in_reg128 => from_input_whit_xors, |
out_reg128 => to_input_mux, |
enable_reg128 => enable_round_reg, |
reset_reg128 => reset, |
clk_reg128 => clk ); |
|
input_mux: mux128 |
port map ( in1_mux128 => to_input_mux, |
in2_mux128 => to_mux, |
out_mux128 => to_round, |
selection_mux128 => mux_selection |
); |
|
|
-- creating a round |
the_keysched_of_the_round: twofish_keysched192 |
port map ( |
odd_in_tk192 => odd_number, |
even_in_tk192 => even_number, |
in_key_tk192 => twofish_key, |
out_key_up_tk192 => key_up, |
out_key_down_tk192 => key_down |
); |
|
producing_the_Skeys: twofish_S192 |
port map ( |
in_key_ts192 => twofish_key, |
out_Sfirst_ts192 => Sfirst, |
out_Ssecond_ts192 => Ssecond, |
out_Sthird_ts192 => Sthird |
); |
|
the_encryption_circuit: twofish_encryption_round192 |
port map ( |
in1_ter192 => to_round(127 downto 96), |
in2_ter192 => to_round(95 downto 64), |
in3_ter192 => to_round(63 downto 32), |
in4_ter192 => to_round(31 downto 0), |
in_Sfirst_ter192 => Sfirst, |
in_Ssecond_ter192 => Ssecond, |
in_Sthird_ter192 => Sthird, |
in_key_up_ter192 => key_up, |
in_key_down_ter192 => key_down, |
out1_ter192 => to_encr_reg128(127 downto 96), |
out2_ter192 => to_encr_reg128(95 downto 64), |
out3_ter192 => to_encr_reg128(63 downto 32), |
out4_ter192 => to_encr_reg128(31 downto 0) |
); |
|
encr_reg: reg128 |
port map ( in_reg128 => to_encr_reg128, |
out_reg128 => to_demux, |
enable_reg128 => enable_encr_reg, |
reset_reg128 => reset, |
clk_reg128 => clk ); |
|
output_demux: demux128 |
port map ( in_demux128 => to_demux, |
out1_demux128 => to_output_whit_xors, |
out2_demux128 => to_mux, |
selection_demux128 => demux_selection ); |
|
-- don't forget the last swap !!! |
from_xors_to_tdo(127 downto 96) <= K4 XOR to_output_whit_xors(63 downto 32); |
from_xors_to_tdo(95 downto 64) <= K5 XOR to_output_whit_xors(31 downto 0); |
from_xors_to_tdo(63 downto 32) <= K6 XOR to_output_whit_xors(127 downto 96); |
from_xors_to_tdo(31 downto 0) <= K7 XOR to_output_whit_xors(95 downto 64); |
|
taking_the_output: twofish_data_output |
port map ( |
in_tdo => from_xors_to_tdo, |
out_tdo => output_data |
); |
|
-- we create the clock |
clk <= not clk after 50 ns; -- period 100 ns |
|
|
ecb_emc_proc: process |
|
variable key_f, -- key input from file |
pt_f, -- plaintext from file |
ct_f : line; -- ciphertext from file |
variable key_v : std_logic_vector(191 downto 0); -- key vector input |
variable pt_v , -- plaintext vector |
ct_v : std_logic_vector(127 downto 0); -- ciphertext vector |
|
variable counter_10000 : integer range 0 to 9999 := 0; -- counter for the 10.000 repeats in the 400 next ones |
variable counter_400 : integer range 0 to 399 := 0; -- counter for the 400 repeats |
variable round : integer range 0 to 16 := 0; -- holds the rounds |
variable intermediate_encryption_result : std_logic_vector(127 downto 0); -- holds the intermediate encryption result |
|
begin |
|
|
|
while not endfile(input_file) loop |
|
readline(input_file, key_f); |
readline(input_file, pt_f); |
readline(input_file,ct_f); |
hread(key_f,key_v); |
hread(pt_f,pt_v); |
hread(ct_f,ct_v); |
|
twofish_key <= key_v; |
intermediate_encryption_result := pt_v; |
|
for counter_10000 in 0 to 9999 loop |
input_data <= intermediate_encryption_result; |
|
wait for 25 ns; |
reset <= '1'; |
wait for 50 ns; |
reset <= '0'; |
|
mux_selection <= '0'; |
demux_selection <= '1'; |
enable_encr_reg <= '0'; |
enable_round_reg <= '0'; |
wait for 50 ns; |
enable_round_reg <= '1'; |
wait for 50 ns; |
enable_round_reg <= '0'; |
|
-- the first round |
even_number <= "00001000"; -- 8 |
odd_number <= "00001001"; -- 9 |
wait for 50 ns; |
enable_encr_reg <= '1'; |
wait for 50 ns; |
enable_encr_reg <= '0'; |
demux_selection <= '1'; |
mux_selection <= '1'; |
|
-- the rest 15 rounds |
for round in 1 to 15 loop |
even_number <= conv_std_logic_vector(((round*2)+8), 8); |
odd_number <= conv_std_logic_vector(((round*2)+9), 8); |
wait for 50 ns; |
enable_encr_reg <= '1'; |
wait for 50 ns; |
enable_encr_reg <= '0'; |
end loop; |
|
-- taking final results |
demux_selection <= '0'; |
wait for 25 ns; |
|
intermediate_encryption_result := output_data; |
|
assert false report "I=" & to_text(counter_400) & " R=" & to_text(counter_10000) severity note; |
|
end loop; -- counter_10000 |
|
hwrite(key_f, key_v); |
hwrite(pt_f, pt_v); |
hwrite(ct_f,output_data); |
writeline(output_file,key_f); |
writeline(output_file,pt_f); |
writeline(output_file,ct_f); |
|
assert (ct_v = output_data) report "file entry and encryption result DO NOT match!!! :( " severity failure; |
assert (ct_v /= output_data) report "Encryption I=" & to_text(counter_400) &" OK" severity note; |
counter_400 := counter_400 + 1; |
end loop; |
assert false report "***** ECB Encryption Monte Carlo Test with 192 bits key size ended succesfully! :) *****" severity failure; |
end process ecb_emc_proc; |
|
end ecb_encryption192_monte_carlo_testbench_arch; |
|
/trunk/vhdl/twofish_ecb_vk_testbench_128bits.vhd
0,0 → 1,370
-- Twofish_ecb_vk_testbench_128bits.vhd |
-- Copyright (C) 2006 Spyros Ninos |
-- |
-- This program is free software; you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation; either version 2 of the License, or |
-- (at your option) any later version. |
-- |
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU General Public License |
-- along with this library; see the file COPYING. If not, write to: |
-- |
-- Free Software Foundation |
-- 59 Temple Place - Suite 330 |
-- Boston, MA 02111-1307, USA. |
-- |
-- description : this file is the testbench for the VARIABLE KEY KAT of the twofish cipher with 128 bit key |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
use ieee.std_logic_textio.all; |
use ieee.std_logic_arith.all; |
use std.textio.all; |
|
entity vk_testbench128 is |
end vk_testbench128; |
|
architecture vk_encryption128_testbench_arch of vk_testbench128 is |
|
component reg128 |
port ( |
in_reg128 : in std_logic_vector(127 downto 0); |
out_reg128 : out std_logic_vector(127 downto 0); |
enable_reg128, reset_reg128, clk_reg128 : in std_logic |
); |
end component; |
|
component twofish_keysched128 |
port ( |
odd_in_tk128, |
even_in_tk128 : in std_logic_vector(7 downto 0); |
in_key_tk128 : in std_logic_vector(127 downto 0); |
out_key_up_tk128, |
out_key_down_tk128 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component twofish_whit_keysched128 |
port ( |
in_key_twk128 : in std_logic_vector(127 downto 0); |
out_K0_twk128, |
out_K1_twk128, |
out_K2_twk128, |
out_K3_twk128, |
out_K4_twk128, |
out_K5_twk128, |
out_K6_twk128, |
out_K7_twk128 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component twofish_encryption_round128 |
port ( |
in1_ter128, |
in2_ter128, |
in3_ter128, |
in4_ter128, |
in_Sfirst_ter128, |
in_Ssecond_ter128, |
in_key_up_ter128, |
in_key_down_ter128 : in std_logic_vector(31 downto 0); |
out1_ter128, |
out2_ter128, |
out3_ter128, |
out4_ter128 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component twofish_data_input |
port ( |
in_tdi : in std_logic_vector(127 downto 0); |
out_tdi : out std_logic_vector(127 downto 0) |
); |
end component; |
|
component twofish_data_output |
port ( |
in_tdo : in std_logic_vector(127 downto 0); |
out_tdo : out std_logic_vector(127 downto 0) |
); |
end component; |
|
component demux128 |
port ( in_demux128 : in std_logic_vector(127 downto 0); |
out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0); |
selection_demux128 : in std_logic |
); |
end component; |
|
component mux128 |
port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0); |
selection_mux128 : in std_logic; |
out_mux128 : out std_logic_vector(127 downto 0) |
); |
end component; |
|
component twofish_S128 |
port ( |
in_key_ts128 : in std_logic_vector(127 downto 0); |
out_Sfirst_ts128, |
out_Ssecond_ts128 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
FILE input_file : text is in "twofish_ecb_vk_testvalues_128bits.txt"; |
FILE output_file : text is out "twofish_ecb_vk_128bits_results.txt"; |
|
-- we create the functions that transform a number to text |
-- transforming a signle digit to a character |
function digit_to_char(number : integer range 0 to 9) return character is |
begin |
case number is |
when 0 => return '0'; |
when 1 => return '1'; |
when 2 => return '2'; |
when 3 => return '3'; |
when 4 => return '4'; |
when 5 => return '5'; |
when 6 => return '6'; |
when 7 => return '7'; |
when 8 => return '8'; |
when 9 => return '9'; |
end case; |
end; |
|
-- transforming multi-digit number to text |
function to_text(int_number : integer range 1 to 129) return string is |
variable our_text : string (1 to 3) := (others => ' '); |
variable hundreds, |
tens, |
ones : integer range 0 to 9; |
begin |
ones := int_number mod 10; |
tens := ((int_number mod 100) - ones) / 10; |
hundreds := (int_number - (int_number mod 100)) / 100; |
our_text(1) := digit_to_char(hundreds); |
our_text(2) := digit_to_char(tens); |
our_text(3) := digit_to_char(ones); |
return our_text; |
end; |
|
signal odd_number, |
even_number : std_logic_vector(7 downto 0); |
|
signal input_data, |
output_data, |
twofish_key, |
to_encr_reg128, |
from_tdi_to_xors, |
to_output_whit_xors, |
from_xors_to_tdo, |
to_mux, to_demux, |
from_input_whit_xors, |
to_round, |
to_input_mux : std_logic_vector(127 downto 0) ; |
|
signal key_up, |
key_down, |
Sfirst, |
Ssecond, |
from_xor0, |
from_xor1, |
from_xor2, |
from_xor3, |
K0,K1,K2,K3, |
K4,K5,K6,K7 : std_logic_vector(31 downto 0); |
|
signal clk : std_logic := '0'; |
signal mux_selection : std_logic := '0'; |
signal demux_selection: std_logic := '0'; |
signal enable_encr_reg : std_logic := '0'; |
signal reset : std_logic := '0'; |
signal enable_round_reg : std_logic := '0'; |
|
-- begin the testbench arch description |
begin |
|
|
-- getting data to encrypt |
data_input: twofish_data_input |
port map ( |
in_tdi => input_data, |
out_tdi => from_tdi_to_xors |
); |
|
-- producing whitening keys K0..7 |
the_whitening_step: twofish_whit_keysched128 |
port map ( |
in_key_twk128 => twofish_key, |
out_K0_twk128 => K0, |
out_K1_twk128 => K1, |
out_K2_twk128 => K2, |
out_K3_twk128 => K3, |
out_K4_twk128 => K4, |
out_K5_twk128 => K5, |
out_K6_twk128 => K6, |
out_K7_twk128 => K7 |
); |
|
-- performing the input whitening XORs |
from_xor0 <= K0 XOR from_tdi_to_xors(127 downto 96); |
from_xor1 <= K1 XOR from_tdi_to_xors(95 downto 64); |
from_xor2 <= K2 XOR from_tdi_to_xors(63 downto 32); |
from_xor3 <= K3 XOR from_tdi_to_xors(31 downto 0); |
|
from_input_whit_xors <= from_xor0 & from_xor1 & from_xor2 & from_xor3; |
|
round_reg: reg128 |
port map ( in_reg128 => from_input_whit_xors, |
out_reg128 => to_input_mux, |
enable_reg128 => enable_round_reg, |
reset_reg128 => reset, |
clk_reg128 => clk ); |
|
input_mux: mux128 |
port map ( in1_mux128 => to_input_mux, |
in2_mux128 => to_mux, |
out_mux128 => to_round, |
selection_mux128 => mux_selection |
); |
|
|
-- creating a round |
the_keysched_of_the_round: twofish_keysched128 |
port map ( |
odd_in_tk128 => odd_number, |
even_in_tk128 => even_number, |
in_key_tk128 => twofish_key, |
out_key_up_tk128 => key_up, |
out_key_down_tk128 => key_down |
); |
|
producing_the_Skeys: twofish_S128 |
port map ( |
in_key_ts128 => twofish_key, |
out_Sfirst_ts128 => Sfirst, |
out_Ssecond_ts128 => Ssecond |
); |
|
the_encryption_circuit: twofish_encryption_round128 |
port map ( |
in1_ter128 => to_round(127 downto 96), |
in2_ter128 => to_round(95 downto 64), |
in3_ter128 => to_round(63 downto 32), |
in4_ter128 => to_round(31 downto 0), |
in_Sfirst_ter128 => Sfirst, |
in_Ssecond_ter128 => Ssecond, |
in_key_up_ter128 => key_up, |
in_key_down_ter128 => key_down, |
out1_ter128 => to_encr_reg128(127 downto 96), |
out2_ter128 => to_encr_reg128(95 downto 64), |
out3_ter128 => to_encr_reg128(63 downto 32), |
out4_ter128 => to_encr_reg128(31 downto 0) |
); |
|
encr_reg: reg128 |
port map ( in_reg128 => to_encr_reg128, |
out_reg128 => to_demux, |
enable_reg128 => enable_encr_reg, |
reset_reg128 => reset, |
clk_reg128 => clk ); |
|
output_demux: demux128 |
port map ( in_demux128 => to_demux, |
out1_demux128 => to_output_whit_xors, |
out2_demux128 => to_mux, |
selection_demux128 => demux_selection ); |
|
-- don't forget the last swap !!! |
from_xors_to_tdo(127 downto 96) <= K4 XOR to_output_whit_xors(63 downto 32); |
from_xors_to_tdo(95 downto 64) <= K5 XOR to_output_whit_xors(31 downto 0); |
from_xors_to_tdo(63 downto 32) <= K6 XOR to_output_whit_xors(127 downto 96); |
from_xors_to_tdo(31 downto 0) <= K7 XOR to_output_whit_xors(95 downto 64); |
|
taking_the_output: twofish_data_output |
port map ( |
in_tdo => from_xors_to_tdo, |
out_tdo => output_data |
); |
|
-- we create the clock |
clk <= not clk after 50 ns; -- period 100 ns |
|
|
vk_proc: process |
|
variable key_f, -- key input from file |
ct_f : line; -- ciphertext from file |
variable key_v, -- key vector input |
ct_v : std_logic_vector(127 downto 0); -- ciphertext vector |
|
variable counter : integer range 1 to 129 := 1; -- counts the encryptions |
variable round : integer range 1 to 16 := 1; -- holds the rounds of encryption |
|
begin |
|
-- plaintext stays fixed to zero |
input_data <= (others => '0'); |
|
while not endfile(input_file) loop |
readline(input_file, key_f); |
readline(input_file,ct_f); |
hread(key_f,key_v); |
hread(ct_f,ct_v); |
twofish_key <= key_v; |
wait for 25 ns; |
reset <= '1'; |
wait for 50 ns; |
reset <= '0'; |
mux_selection <= '0'; |
demux_selection <= '1'; |
enable_encr_reg <= '0'; |
enable_round_reg <= '0'; |
wait for 50 ns; |
enable_round_reg <= '1'; |
wait for 50 ns; |
enable_round_reg <= '0'; |
|
-- the first round |
even_number <= "00001000"; -- 8 |
odd_number <= "00001001"; -- 9 |
wait for 50 ns; |
enable_encr_reg <= '1'; |
wait for 50 ns; |
enable_encr_reg <= '0'; |
demux_selection <= '1'; |
mux_selection <= '1'; |
|
-- the rest 15 rounds |
for round in 1 to 15 loop |
even_number <= conv_std_logic_vector(((round*2)+8), 8); |
odd_number <= conv_std_logic_vector(((round*2)+9), 8); |
wait for 50 ns; |
enable_encr_reg <= '1'; |
wait for 50 ns; |
enable_encr_reg <= '0'; |
end loop; |
|
-- taking final results |
demux_selection <= '0'; |
wait for 25 ns; |
assert (ct_v = output_data) report "file entry and encryption result DO NOT match!!! :( " severity failure; |
assert (ct_v /= output_data) report "Encryption I=" & to_text(counter) &" OK" severity note; |
counter := counter+1; |
hwrite(ct_f,output_data); |
hwrite(key_f,key_v); |
writeline(output_file,key_f); |
writeline(output_file,ct_f); |
end loop; |
assert false report "***** Variable Key Known Answer Test with 128 bits key size ended succesfully! :) *****" severity failure; |
end process vk_proc; |
|
end vk_encryption128_testbench_arch; |
|
/trunk/vhdl/twofish_ecb_tbl_testbench_128bits.vhd
0,0 → 1,373
-- Twofish_ecb_tbl_testbench_128bits.vhd |
-- Copyright (C) 2006 Spyros Ninos |
-- |
-- This program is free software; you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation; either version 2 of the License, or |
-- (at your option) any later version. |
-- |
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU General Public License |
-- along with this library; see the file COPYING. If not, write to: |
-- |
-- Free Software Foundation |
-- 59 Temple Place - Suite 330 |
-- Boston, MA 02111-1307, USA. |
-- |
-- description : this file is the testbench for the TABLES KAT of the twofish cipher with 128 bit key |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
use ieee.std_logic_textio.all; |
use ieee.std_logic_arith.all; |
use std.textio.all; |
|
entity tbl_testbench128 is |
end tbl_testbench128; |
|
architecture tbl_encryption128_testbench_arch of tbl_testbench128 is |
|
component reg128 |
port ( |
in_reg128 : in std_logic_vector(127 downto 0); |
out_reg128 : out std_logic_vector(127 downto 0); |
enable_reg128, reset_reg128, clk_reg128 : in std_logic |
); |
end component; |
|
component twofish_keysched128 |
port ( |
odd_in_tk128, |
even_in_tk128 : in std_logic_vector(7 downto 0); |
in_key_tk128 : in std_logic_vector(127 downto 0); |
out_key_up_tk128, |
out_key_down_tk128 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component twofish_whit_keysched128 |
port ( |
in_key_twk128 : in std_logic_vector(127 downto 0); |
out_K0_twk128, |
out_K1_twk128, |
out_K2_twk128, |
out_K3_twk128, |
out_K4_twk128, |
out_K5_twk128, |
out_K6_twk128, |
out_K7_twk128 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component twofish_encryption_round128 |
port ( |
in1_ter128, |
in2_ter128, |
in3_ter128, |
in4_ter128, |
in_Sfirst_ter128, |
in_Ssecond_ter128, |
in_key_up_ter128, |
in_key_down_ter128 : in std_logic_vector(31 downto 0); |
out1_ter128, |
out2_ter128, |
out3_ter128, |
out4_ter128 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component twofish_data_input |
port ( |
in_tdi : in std_logic_vector(127 downto 0); |
out_tdi : out std_logic_vector(127 downto 0) |
); |
end component; |
|
component twofish_data_output |
port ( |
in_tdo : in std_logic_vector(127 downto 0); |
out_tdo : out std_logic_vector(127 downto 0) |
); |
end component; |
|
component demux128 |
port ( in_demux128 : in std_logic_vector(127 downto 0); |
out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0); |
selection_demux128 : in std_logic |
); |
end component; |
|
component mux128 |
port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0); |
selection_mux128 : in std_logic; |
out_mux128 : out std_logic_vector(127 downto 0) |
); |
end component; |
|
component twofish_S128 |
port ( |
in_key_ts128 : in std_logic_vector(127 downto 0); |
out_Sfirst_ts128, |
out_Ssecond_ts128 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
FILE input_file : text is in "twofish_ecb_tbl_testvalues_128bits.txt"; |
FILE output_file : text is out "twofish_ecb_tbl_128bits_results.txt"; |
|
-- we create the functions that transform a number to text |
-- transforming a signle digit to a character |
function digit_to_char(number : integer range 0 to 9) return character is |
begin |
case number is |
when 0 => return '0'; |
when 1 => return '1'; |
when 2 => return '2'; |
when 3 => return '3'; |
when 4 => return '4'; |
when 5 => return '5'; |
when 6 => return '6'; |
when 7 => return '7'; |
when 8 => return '8'; |
when 9 => return '9'; |
end case; |
end; |
|
-- transforming multi-digit number to text |
function to_text(int_number : integer range 1 to 50) return string is |
variable our_text : string (1 to 3) := (others => ' '); |
variable hundreds, |
tens, |
ones : integer range 0 to 9; |
begin |
ones := int_number mod 10; |
tens := ((int_number mod 100) - ones) / 10; |
hundreds := (int_number - (int_number mod 100)) / 100; |
our_text(1) := digit_to_char(hundreds); |
our_text(2) := digit_to_char(tens); |
our_text(3) := digit_to_char(ones); |
return our_text; |
end; |
|
signal odd_number, |
even_number : std_logic_vector(7 downto 0); |
|
signal input_data, |
output_data, |
twofish_key, |
to_encr_reg128, |
from_tdi_to_xors, |
to_output_whit_xors, |
from_xors_to_tdo, |
to_mux, to_demux, |
from_input_whit_xors, |
to_round, |
to_input_mux : std_logic_vector(127 downto 0) ; |
|
signal key_up, |
key_down, |
Sfirst, |
Ssecond, |
from_xor0, |
from_xor1, |
from_xor2, |
from_xor3, |
K0,K1,K2,K3, |
K4,K5,K6,K7 : std_logic_vector(31 downto 0); |
|
signal clk : std_logic := '0'; |
signal mux_selection : std_logic := '0'; |
signal demux_selection: std_logic := '0'; |
signal enable_encr_reg : std_logic := '0'; |
signal reset : std_logic := '0'; |
signal enable_round_reg : std_logic := '0'; |
|
-- begin the testbench arch description |
begin |
|
|
-- getting data to encrypt |
data_input: twofish_data_input |
port map ( |
in_tdi => input_data, |
out_tdi => from_tdi_to_xors |
); |
|
-- producing whitening keys K0..7 |
the_whitening_step: twofish_whit_keysched128 |
port map ( |
in_key_twk128 => twofish_key, |
out_K0_twk128 => K0, |
out_K1_twk128 => K1, |
out_K2_twk128 => K2, |
out_K3_twk128 => K3, |
out_K4_twk128 => K4, |
out_K5_twk128 => K5, |
out_K6_twk128 => K6, |
out_K7_twk128 => K7 |
); |
|
-- performing the input whitening XORs |
from_xor0 <= K0 XOR from_tdi_to_xors(127 downto 96); |
from_xor1 <= K1 XOR from_tdi_to_xors(95 downto 64); |
from_xor2 <= K2 XOR from_tdi_to_xors(63 downto 32); |
from_xor3 <= K3 XOR from_tdi_to_xors(31 downto 0); |
|
from_input_whit_xors <= from_xor0 & from_xor1 & from_xor2 & from_xor3; |
|
round_reg: reg128 |
port map ( in_reg128 => from_input_whit_xors, |
out_reg128 => to_input_mux, |
enable_reg128 => enable_round_reg, |
reset_reg128 => reset, |
clk_reg128 => clk ); |
|
input_mux: mux128 |
port map ( in1_mux128 => to_input_mux, |
in2_mux128 => to_mux, |
out_mux128 => to_round, |
selection_mux128 => mux_selection |
); |
|
|
-- creating a round |
the_keysched_of_the_round: twofish_keysched128 |
port map ( |
odd_in_tk128 => odd_number, |
even_in_tk128 => even_number, |
in_key_tk128 => twofish_key, |
out_key_up_tk128 => key_up, |
out_key_down_tk128 => key_down |
); |
|
producing_the_Skeys: twofish_S128 |
port map ( |
in_key_ts128 => twofish_key, |
out_Sfirst_ts128 => Sfirst, |
out_Ssecond_ts128 => Ssecond |
); |
|
the_encryption_circuit: twofish_encryption_round128 |
port map ( |
in1_ter128 => to_round(127 downto 96), |
in2_ter128 => to_round(95 downto 64), |
in3_ter128 => to_round(63 downto 32), |
in4_ter128 => to_round(31 downto 0), |
in_Sfirst_ter128 => Sfirst, |
in_Ssecond_ter128 => Ssecond, |
in_key_up_ter128 => key_up, |
in_key_down_ter128 => key_down, |
out1_ter128 => to_encr_reg128(127 downto 96), |
out2_ter128 => to_encr_reg128(95 downto 64), |
out3_ter128 => to_encr_reg128(63 downto 32), |
out4_ter128 => to_encr_reg128(31 downto 0) |
); |
|
encr_reg: reg128 |
port map ( in_reg128 => to_encr_reg128, |
out_reg128 => to_demux, |
enable_reg128 => enable_encr_reg, |
reset_reg128 => reset, |
clk_reg128 => clk ); |
|
output_demux: demux128 |
port map ( in_demux128 => to_demux, |
out1_demux128 => to_output_whit_xors, |
out2_demux128 => to_mux, |
selection_demux128 => demux_selection ); |
|
-- don't forget the last swap !!! |
from_xors_to_tdo(127 downto 96) <= K4 XOR to_output_whit_xors(63 downto 32); |
from_xors_to_tdo(95 downto 64) <= K5 XOR to_output_whit_xors(31 downto 0); |
from_xors_to_tdo(63 downto 32) <= K6 XOR to_output_whit_xors(127 downto 96); |
from_xors_to_tdo(31 downto 0) <= K7 XOR to_output_whit_xors(95 downto 64); |
|
taking_the_output: twofish_data_output |
port map ( |
in_tdo => from_xors_to_tdo, |
out_tdo => output_data |
); |
|
-- we create the clock |
clk <= not clk after 50 ns; -- period 100 ns |
|
|
tbl_proc: process |
|
variable key_f, -- key input from file |
pt_f, -- plaintext from file |
ct_f : line; -- ciphertext from file |
variable key_v, -- key vector input |
pt_v , -- plaintext vector |
ct_v : std_logic_vector(127 downto 0); -- ciphertext vector |
|
variable counter : integer range 1 to 50 := 1; |
variable round : integer range 0 to 16 := 0; |
|
begin |
while not endfile(input_file) loop |
readline(input_file, key_f); |
readline(input_file, pt_f); |
readline(input_file,ct_f); |
hread(key_f,key_v); |
hread(pt_f,pt_v); |
hread(ct_f,ct_v); |
twofish_key <= key_v; |
input_data <= pt_v; |
wait for 25 ns; |
reset <= '1'; |
wait for 50 ns; |
reset <= '0'; |
mux_selection <= '0'; |
demux_selection <= '1'; |
enable_encr_reg <= '0'; |
enable_round_reg <= '0'; |
wait for 50 ns; |
enable_round_reg <= '1'; |
wait for 50 ns; |
enable_round_reg <= '0'; |
|
-- the first round |
even_number <= "00001000"; -- 8 |
odd_number <= "00001001"; -- 9 |
wait for 50 ns; |
enable_encr_reg <= '1'; |
wait for 50 ns; |
enable_encr_reg <= '0'; |
demux_selection <= '1'; |
mux_selection <= '1'; |
|
-- the rest 15 rounds |
for round in 1 to 15 loop |
even_number <= conv_std_logic_vector(((round*2)+8), 8); |
odd_number <= conv_std_logic_vector(((round*2)+9), 8); |
wait for 50 ns; |
enable_encr_reg <= '1'; |
wait for 50 ns; |
enable_encr_reg <= '0'; |
end loop; |
|
-- taking final results |
demux_selection <= '0'; |
wait for 25 ns; |
assert (ct_v = output_data) report "file entry and encryption result DO NOT match!!! :( " severity failure; |
assert (ct_v /= output_data) report "Encryption I=" & to_text(counter) &" OK" severity note; |
counter := counter+1; |
hwrite(pt_f,input_data); |
hwrite(ct_f,output_data); |
hwrite(key_f,key_v); |
writeline(output_file,key_f); |
writeline(output_file,pt_f); |
writeline(output_file,ct_f); |
end loop; |
assert false report "***** Tables Known Answer Test with 128 bits key size ended succesfully! :) *****" severity failure; |
end process tbl_proc; |
|
end tbl_encryption128_testbench_arch; |
|
/trunk/vhdl/twofish_ecb_vk_testbench_192bits.vhd
0,0 → 1,376
-- Twofish_ecb_vk_testbench_192bits.vhd |
-- Copyright (C) 2006 Spyros Ninos |
-- |
-- This program is free software; you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation; either version 2 of the License, or |
-- (at your option) any later version. |
-- |
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU General Public License |
-- along with this library; see the file COPYING. If not, write to: |
-- |
-- Free Software Foundation |
-- 59 Temple Place - Suite 330 |
-- Boston, MA 02111-1307, USA. |
-- |
-- description : this file is the testbench for the VARIABLE KEY KAT of the twofish cipher with 192 bit key |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
use ieee.std_logic_textio.all; |
use ieee.std_logic_arith.all; |
use std.textio.all; |
|
entity vk_testbench192 is |
end vk_testbench192; |
|
architecture vk_encryption192_testbench_arch of vk_testbench192 is |
|
component reg128 |
port ( |
in_reg128 : in std_logic_vector(127 downto 0); |
out_reg128 : out std_logic_vector(127 downto 0); |
enable_reg128, reset_reg128, clk_reg128 : in std_logic |
); |
end component; |
|
component twofish_keysched192 |
port ( |
odd_in_tk192, |
even_in_tk192 : in std_logic_vector(7 downto 0); |
in_key_tk192 : in std_logic_vector(191 downto 0); |
out_key_up_tk192, |
out_key_down_tk192 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component twofish_whit_keysched192 |
port ( |
in_key_twk192 : in std_logic_vector(191 downto 0); |
out_K0_twk192, |
out_K1_twk192, |
out_K2_twk192, |
out_K3_twk192, |
out_K4_twk192, |
out_K5_twk192, |
out_K6_twk192, |
out_K7_twk192 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component twofish_encryption_round192 |
port ( |
in1_ter192, |
in2_ter192, |
in3_ter192, |
in4_ter192, |
in_Sfirst_ter192, |
in_Ssecond_ter192, |
in_Sthird_ter192, |
in_key_up_ter192, |
in_key_down_ter192 : in std_logic_vector(31 downto 0); |
out1_ter192, |
out2_ter192, |
out3_ter192, |
out4_ter192 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component twofish_data_input |
port ( |
in_tdi : in std_logic_vector(127 downto 0); |
out_tdi : out std_logic_vector(127 downto 0) |
); |
end component; |
|
component twofish_data_output |
port ( |
in_tdo : in std_logic_vector(127 downto 0); |
out_tdo : out std_logic_vector(127 downto 0) |
); |
end component; |
|
component demux128 |
port ( in_demux128 : in std_logic_vector(127 downto 0); |
out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0); |
selection_demux128 : in std_logic |
); |
end component; |
|
component mux128 |
port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0); |
selection_mux128 : in std_logic; |
out_mux128 : out std_logic_vector(127 downto 0) |
); |
end component; |
|
component twofish_S192 |
port ( |
in_key_ts192 : in std_logic_vector(191 downto 0); |
out_Sfirst_ts192, |
out_Ssecond_ts192, |
out_Sthird_ts192 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
FILE input_file : text is in "twofish_ecb_vk_testvalues_192bits.txt"; |
FILE output_file : text is out "twofish_ecb_vk_192bits_results.txt"; |
|
-- we create the functions that transform a number to text |
-- transforming a signle digit to a character |
function digit_to_char(number : integer range 0 to 9) return character is |
begin |
case number is |
when 0 => return '0'; |
when 1 => return '1'; |
when 2 => return '2'; |
when 3 => return '3'; |
when 4 => return '4'; |
when 5 => return '5'; |
when 6 => return '6'; |
when 7 => return '7'; |
when 8 => return '8'; |
when 9 => return '9'; |
end case; |
end; |
|
-- transforming multi-digit number to text |
function to_text(int_number : integer range 1 to 193) return string is |
variable our_text : string (1 to 3) := (others => ' '); |
variable hundreds, |
tens, |
ones : integer range 0 to 9; |
begin |
ones := int_number mod 10; |
tens := ((int_number mod 100) - ones) / 10; |
hundreds := (int_number - (int_number mod 100)) / 100; |
our_text(1) := digit_to_char(hundreds); |
our_text(2) := digit_to_char(tens); |
our_text(3) := digit_to_char(ones); |
return our_text; |
end; |
|
signal odd_number, |
even_number : std_logic_vector(7 downto 0); |
|
signal input_data, |
output_data, |
to_encr_reg128, |
from_tdi_to_xors, |
to_output_whit_xors, |
from_xors_to_tdo, |
to_mux, to_demux, |
from_input_whit_xors, |
to_round, |
to_input_mux : std_logic_vector(127 downto 0) ; |
|
signal twofish_key : std_logic_vector(191 downto 0); |
|
signal key_up, |
key_down, |
Sfirst, |
Ssecond, |
Sthird, |
from_xor0, |
from_xor1, |
from_xor2, |
from_xor3, |
K0,K1,K2,K3, |
K4,K5,K6,K7 : std_logic_vector(31 downto 0); |
|
signal clk : std_logic := '0'; |
signal mux_selection : std_logic := '0'; |
signal demux_selection: std_logic := '0'; |
signal enable_encr_reg : std_logic := '0'; |
signal reset : std_logic := '0'; |
signal enable_round_reg : std_logic := '0'; |
|
-- begin the testbench arch description |
begin |
|
|
-- getting data to encrypt |
data_input: twofish_data_input |
port map ( |
in_tdi => input_data, |
out_tdi => from_tdi_to_xors |
); |
|
-- producing whitening keys K0..7 |
the_whitening_step: twofish_whit_keysched192 |
port map ( |
in_key_twk192 => twofish_key, |
out_K0_twk192 => K0, |
out_K1_twk192 => K1, |
out_K2_twk192 => K2, |
out_K3_twk192 => K3, |
out_K4_twk192 => K4, |
out_K5_twk192 => K5, |
out_K6_twk192 => K6, |
out_K7_twk192 => K7 |
); |
|
-- performing the input whitening XORs |
from_xor0 <= K0 XOR from_tdi_to_xors(127 downto 96); |
from_xor1 <= K1 XOR from_tdi_to_xors(95 downto 64); |
from_xor2 <= K2 XOR from_tdi_to_xors(63 downto 32); |
from_xor3 <= K3 XOR from_tdi_to_xors(31 downto 0); |
|
from_input_whit_xors <= from_xor0 & from_xor1 & from_xor2 & from_xor3; |
|
round_reg: reg128 |
port map ( in_reg128 => from_input_whit_xors, |
out_reg128 => to_input_mux, |
enable_reg128 => enable_round_reg, |
reset_reg128 => reset, |
clk_reg128 => clk ); |
|
input_mux: mux128 |
port map ( in1_mux128 => to_input_mux, |
in2_mux128 => to_mux, |
out_mux128 => to_round, |
selection_mux128 => mux_selection |
); |
|
|
-- creating a round |
the_keysched_of_the_round: twofish_keysched192 |
port map ( |
odd_in_tk192 => odd_number, |
even_in_tk192 => even_number, |
in_key_tk192 => twofish_key, |
out_key_up_tk192 => key_up, |
out_key_down_tk192 => key_down |
); |
|
producing_the_Skeys: twofish_S192 |
port map ( |
in_key_ts192 => twofish_key, |
out_Sfirst_ts192 => Sfirst, |
out_Ssecond_ts192 => Ssecond, |
out_Sthird_ts192 => Sthird |
); |
|
the_encryption_circuit: twofish_encryption_round192 |
port map ( |
in1_ter192 => to_round(127 downto 96), |
in2_ter192 => to_round(95 downto 64), |
in3_ter192 => to_round(63 downto 32), |
in4_ter192 => to_round(31 downto 0), |
in_Sfirst_ter192 => Sfirst, |
in_Ssecond_ter192 => Ssecond, |
in_Sthird_ter192 => Sthird, |
in_key_up_ter192 => key_up, |
in_key_down_ter192 => key_down, |
out1_ter192 => to_encr_reg128(127 downto 96), |
out2_ter192 => to_encr_reg128(95 downto 64), |
out3_ter192 => to_encr_reg128(63 downto 32), |
out4_ter192 => to_encr_reg128(31 downto 0) |
); |
|
encr_reg: reg128 |
port map ( in_reg128 => to_encr_reg128, |
out_reg128 => to_demux, |
enable_reg128 => enable_encr_reg, |
reset_reg128 => reset, |
clk_reg128 => clk ); |
|
output_demux: demux128 |
port map ( in_demux128 => to_demux, |
out1_demux128 => to_output_whit_xors, |
out2_demux128 => to_mux, |
selection_demux128 => demux_selection ); |
|
-- don't forget the last swap !!! |
from_xors_to_tdo(127 downto 96) <= K4 XOR to_output_whit_xors(63 downto 32); |
from_xors_to_tdo(95 downto 64) <= K5 XOR to_output_whit_xors(31 downto 0); |
from_xors_to_tdo(63 downto 32) <= K6 XOR to_output_whit_xors(127 downto 96); |
from_xors_to_tdo(31 downto 0) <= K7 XOR to_output_whit_xors(95 downto 64); |
|
taking_the_output: twofish_data_output |
port map ( |
in_tdo => from_xors_to_tdo, |
out_tdo => output_data |
); |
|
-- we create the clock |
clk <= not clk after 50 ns; -- period 100 ns |
|
|
vk_proc: process |
|
variable key_f, -- key input from file |
ct_f : line; -- ciphertext from file |
variable key_v : std_logic_vector(191 downto 0); -- key vector input |
variable ct_v : std_logic_vector(127 downto 0); -- ciphertext vector |
|
variable counter : integer range 1 to 193 := 1; -- counts the encryptions |
variable round : integer range 1 to 16 := 1; -- holds the rounds of encryption |
|
begin |
|
-- plaintext stays fixed to zero |
input_data <= (others => '0'); |
|
while not endfile(input_file) loop |
readline(input_file, key_f); |
readline(input_file,ct_f); |
hread(key_f,key_v); |
hread(ct_f,ct_v); |
twofish_key <= key_v; |
wait for 25 ns; |
reset <= '1'; |
wait for 50 ns; |
reset <= '0'; |
mux_selection <= '0'; |
demux_selection <= '1'; |
enable_encr_reg <= '0'; |
enable_round_reg <= '0'; |
wait for 50 ns; |
enable_round_reg <= '1'; |
wait for 50 ns; |
enable_round_reg <= '0'; |
|
-- the first round |
even_number <= "00001000"; -- 8 |
odd_number <= "00001001"; -- 9 |
wait for 50 ns; |
enable_encr_reg <= '1'; |
wait for 50 ns; |
enable_encr_reg <= '0'; |
demux_selection <= '1'; |
mux_selection <= '1'; |
|
-- the rest 15 rounds |
for round in 1 to 15 loop |
even_number <= conv_std_logic_vector(((round*2)+8), 8); |
odd_number <= conv_std_logic_vector(((round*2)+9), 8); |
wait for 50 ns; |
enable_encr_reg <= '1'; |
wait for 50 ns; |
enable_encr_reg <= '0'; |
end loop; |
|
-- taking final results |
demux_selection <= '0'; |
wait for 25 ns; |
assert (ct_v = output_data) report "file entry and encryption result DO NOT match!!! :( " severity failure; |
assert (ct_v /= output_data) report "Encryption I=" & to_text(counter) &" OK" severity note; |
counter := counter+1; |
hwrite(ct_f,output_data); |
hwrite(key_f,key_v); |
writeline(output_file,key_f); |
writeline(output_file,ct_f); |
end loop; |
assert false report "***** Variable Key Known Answer Test with 192 bits key size ended succesfully! :) *****" severity failure; |
end process vk_proc; |
|
end vk_encryption192_testbench_arch; |
|
/trunk/vhdl/twofish_ecb_tbl_testbench_192bits.vhd
0,0 → 1,380
-- Twofish_ecb_tbl_testbench_192bits.vhd |
-- Copyright (C) 2006 Spyros Ninos |
-- |
-- This program is free software; you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation; either version 2 of the License, or |
-- (at your option) any later version. |
-- |
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU General Public License |
-- along with this library; see the file COPYING. If not, write to: |
-- |
-- Free Software Foundation |
-- 59 Temple Place - Suite 330 |
-- Boston, MA 02111-1307, USA. |
-- |
-- description : this file is the testbench for the TABLES KAT of the twofish cipher with 192 bit key |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
use ieee.std_logic_textio.all; |
use ieee.std_logic_arith.all; |
use std.textio.all; |
|
entity tbl_testbench192 is |
end tbl_testbench192; |
|
architecture tbl_encryption192_testbench_arch of tbl_testbench192 is |
|
component reg128 |
port ( |
in_reg128 : in std_logic_vector(127 downto 0); |
out_reg128 : out std_logic_vector(127 downto 0); |
enable_reg128, reset_reg128, clk_reg128 : in std_logic |
); |
end component; |
|
component twofish_keysched192 |
port ( |
odd_in_tk192, |
even_in_tk192 : in std_logic_vector(7 downto 0); |
in_key_tk192 : in std_logic_vector(191 downto 0); |
out_key_up_tk192, |
out_key_down_tk192 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component twofish_whit_keysched192 |
port ( |
in_key_twk192 : in std_logic_vector(191 downto 0); |
out_K0_twk192, |
out_K1_twk192, |
out_K2_twk192, |
out_K3_twk192, |
out_K4_twk192, |
out_K5_twk192, |
out_K6_twk192, |
out_K7_twk192 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component twofish_encryption_round192 |
port ( |
in1_ter192, |
in2_ter192, |
in3_ter192, |
in4_ter192, |
in_Sfirst_ter192, |
in_Ssecond_ter192, |
in_Sthird_ter192, |
in_key_up_ter192, |
in_key_down_ter192 : in std_logic_vector(31 downto 0); |
out1_ter192, |
out2_ter192, |
out3_ter192, |
out4_ter192 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component twofish_data_input |
port ( |
in_tdi : in std_logic_vector(127 downto 0); |
out_tdi : out std_logic_vector(127 downto 0) |
); |
end component; |
|
component twofish_data_output |
port ( |
in_tdo : in std_logic_vector(127 downto 0); |
out_tdo : out std_logic_vector(127 downto 0) |
); |
end component; |
|
component demux128 |
port ( in_demux128 : in std_logic_vector(127 downto 0); |
out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0); |
selection_demux128 : in std_logic |
); |
end component; |
|
component mux128 |
port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0); |
selection_mux128 : in std_logic; |
out_mux128 : out std_logic_vector(127 downto 0) |
); |
end component; |
|
component twofish_S192 |
port ( |
in_key_ts192 : in std_logic_vector(191 downto 0); |
out_Sfirst_ts192, |
out_Ssecond_ts192, |
out_Sthird_ts192 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
FILE input_file : text is in "twofish_ecb_tbl_testvalues_192bits.txt"; |
FILE output_file : text is out "twofish_ecb_tbl_192bits_results.txt"; |
|
-- we create the functions that transform a number to text |
-- transforming a signle digit to a character |
function digit_to_char(number : integer range 0 to 9) return character is |
begin |
case number is |
when 0 => return '0'; |
when 1 => return '1'; |
when 2 => return '2'; |
when 3 => return '3'; |
when 4 => return '4'; |
when 5 => return '5'; |
when 6 => return '6'; |
when 7 => return '7'; |
when 8 => return '8'; |
when 9 => return '9'; |
end case; |
end; |
|
-- transforming multi-digit number to text |
function to_text(int_number : integer range 1 to 50) return string is |
variable our_text : string (1 to 3) := (others => ' '); |
variable hundreds, |
tens, |
ones : integer range 0 to 9; |
begin |
ones := int_number mod 10; |
tens := ((int_number mod 100) - ones) / 10; |
hundreds := (int_number - (int_number mod 100)) / 100; |
our_text(1) := digit_to_char(hundreds); |
our_text(2) := digit_to_char(tens); |
our_text(3) := digit_to_char(ones); |
return our_text; |
end; |
|
signal odd_number, |
even_number : std_logic_vector(7 downto 0); |
|
signal input_data, |
output_data, |
to_encr_reg128, |
from_tdi_to_xors, |
to_output_whit_xors, |
from_xors_to_tdo, |
to_mux, to_demux, |
from_input_whit_xors, |
to_round, |
to_input_mux : std_logic_vector(127 downto 0) ; |
|
signal twofish_key : std_logic_vector(191 downto 0); |
|
signal key_up, |
key_down, |
Sfirst, |
Ssecond, |
Sthird, |
from_xor0, |
from_xor1, |
from_xor2, |
from_xor3, |
K0,K1,K2,K3, |
K4,K5,K6,K7 : std_logic_vector(31 downto 0); |
|
signal clk : std_logic := '0'; |
signal mux_selection : std_logic := '0'; |
signal demux_selection: std_logic := '0'; |
signal enable_encr_reg : std_logic := '0'; |
signal reset : std_logic := '0'; |
signal enable_round_reg : std_logic := '0'; |
|
-- begin the testbench arch description |
begin |
|
|
-- getting data to encrypt |
data_input: twofish_data_input |
port map ( |
in_tdi => input_data, |
out_tdi => from_tdi_to_xors |
); |
|
-- producing whitening keys K0..7 |
the_whitening_step: twofish_whit_keysched192 |
port map ( |
in_key_twk192 => twofish_key, |
out_K0_twk192 => K0, |
out_K1_twk192 => K1, |
out_K2_twk192 => K2, |
out_K3_twk192 => K3, |
out_K4_twk192 => K4, |
out_K5_twk192 => K5, |
out_K6_twk192 => K6, |
out_K7_twk192 => K7 |
); |
|
-- performing the input whitening XORs |
from_xor0 <= K0 XOR from_tdi_to_xors(127 downto 96); |
from_xor1 <= K1 XOR from_tdi_to_xors(95 downto 64); |
from_xor2 <= K2 XOR from_tdi_to_xors(63 downto 32); |
from_xor3 <= K3 XOR from_tdi_to_xors(31 downto 0); |
|
from_input_whit_xors <= from_xor0 & from_xor1 & from_xor2 & from_xor3; |
|
round_reg: reg128 |
port map ( in_reg128 => from_input_whit_xors, |
out_reg128 => to_input_mux, |
enable_reg128 => enable_round_reg, |
reset_reg128 => reset, |
clk_reg128 => clk ); |
|
input_mux: mux128 |
port map ( in1_mux128 => to_input_mux, |
in2_mux128 => to_mux, |
out_mux128 => to_round, |
selection_mux128 => mux_selection |
); |
|
|
-- creating a round |
the_keysched_of_the_round: twofish_keysched192 |
port map ( |
odd_in_tk192 => odd_number, |
even_in_tk192 => even_number, |
in_key_tk192 => twofish_key, |
out_key_up_tk192 => key_up, |
out_key_down_tk192 => key_down |
); |
|
producing_the_Skeys: twofish_S192 |
port map ( |
in_key_ts192 => twofish_key, |
out_Sfirst_ts192 => Sfirst, |
out_Ssecond_ts192 => Ssecond, |
out_Sthird_ts192 => Sthird |
); |
|
the_encryption_circuit: twofish_encryption_round192 |
port map ( |
in1_ter192 => to_round(127 downto 96), |
in2_ter192 => to_round(95 downto 64), |
in3_ter192 => to_round(63 downto 32), |
in4_ter192 => to_round(31 downto 0), |
in_Sfirst_ter192 => Sfirst, |
in_Ssecond_ter192 => Ssecond, |
in_Sthird_ter192 => Sthird, |
in_key_up_ter192 => key_up, |
in_key_down_ter192 => key_down, |
out1_ter192 => to_encr_reg128(127 downto 96), |
out2_ter192 => to_encr_reg128(95 downto 64), |
out3_ter192 => to_encr_reg128(63 downto 32), |
out4_ter192 => to_encr_reg128(31 downto 0) |
); |
|
encr_reg: reg128 |
port map ( in_reg128 => to_encr_reg128, |
out_reg128 => to_demux, |
enable_reg128 => enable_encr_reg, |
reset_reg128 => reset, |
clk_reg128 => clk ); |
|
output_demux: demux128 |
port map ( in_demux128 => to_demux, |
out1_demux128 => to_output_whit_xors, |
out2_demux128 => to_mux, |
selection_demux128 => demux_selection ); |
|
-- don't forget the last swap !!! |
from_xors_to_tdo(127 downto 96) <= K4 XOR to_output_whit_xors(63 downto 32); |
from_xors_to_tdo(95 downto 64) <= K5 XOR to_output_whit_xors(31 downto 0); |
from_xors_to_tdo(63 downto 32) <= K6 XOR to_output_whit_xors(127 downto 96); |
from_xors_to_tdo(31 downto 0) <= K7 XOR to_output_whit_xors(95 downto 64); |
|
taking_the_output: twofish_data_output |
port map ( |
in_tdo => from_xors_to_tdo, |
out_tdo => output_data |
); |
|
-- we create the clock |
clk <= not clk after 50 ns; -- period 100 ns |
|
|
tbl_proc: process |
|
variable key_f, -- key input from file |
pt_f, -- plaintext from file |
ct_f : line; -- ciphertext from file |
variable pt_v , -- plaintext vector |
ct_v : std_logic_vector(127 downto 0); -- ciphertext vector |
variable key_v : std_logic_vector(191 downto 0); -- key vector input |
|
|
variable counter : integer range 1 to 50 := 1; |
variable round : integer range 0 to 16 := 0; |
|
begin |
while not endfile(input_file) loop |
readline(input_file, key_f); |
readline(input_file, pt_f); |
readline(input_file,ct_f); |
hread(key_f,key_v); |
hread(pt_f,pt_v); |
hread(ct_f,ct_v); |
twofish_key <= key_v; |
input_data <= pt_v; |
wait for 25 ns; |
reset <= '1'; |
wait for 50 ns; |
reset <= '0'; |
mux_selection <= '0'; |
demux_selection <= '1'; |
enable_encr_reg <= '0'; |
enable_round_reg <= '0'; |
wait for 50 ns; |
enable_round_reg <= '1'; |
wait for 50 ns; |
enable_round_reg <= '0'; |
|
-- the first round |
even_number <= "00001000"; -- 8 |
odd_number <= "00001001"; -- 9 |
wait for 50 ns; |
enable_encr_reg <= '1'; |
wait for 50 ns; |
enable_encr_reg <= '0'; |
demux_selection <= '1'; |
mux_selection <= '1'; |
|
-- the rest 15 rounds |
for round in 1 to 15 loop |
even_number <= conv_std_logic_vector(((round*2)+8), 8); |
odd_number <= conv_std_logic_vector(((round*2)+9), 8); |
wait for 50 ns; |
enable_encr_reg <= '1'; |
wait for 50 ns; |
enable_encr_reg <= '0'; |
end loop; |
|
-- taking final results |
demux_selection <= '0'; |
wait for 25 ns; |
assert (ct_v = output_data) report "file entry and encryption result DO NOT match!!! :( " severity failure; |
assert (ct_v /= output_data) report "Encryption I=" & to_text(counter) &" OK" severity note; |
counter := counter+1; |
hwrite(pt_f,input_data); |
hwrite(ct_f,output_data); |
hwrite(key_f,key_v); |
writeline(output_file,key_f); |
writeline(output_file,pt_f); |
writeline(output_file,ct_f); |
end loop; |
assert false report "***** Tables Known Answer Test with 192 bits key size ended succesfully! :) *****" severity failure; |
end process tbl_proc; |
|
end tbl_encryption192_testbench_arch; |
|
/trunk/vhdl/twofish_ecb_vt_testbench_128bits.vhd
0,0 → 1,370
-- Twofish_ecb_vt_testbench_128bits.vhd |
-- Copyright (C) 2006 Spyros Ninos |
-- |
-- This program is free software; you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation; either version 2 of the License, or |
-- (at your option) any later version. |
-- |
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU General Public License |
-- along with this library; see the file COPYING. If not, write to: |
-- |
-- Free Software Foundation |
-- 59 Temple Place - Suite 330 |
-- Boston, MA 02111-1307, USA. |
-- |
-- description : this file is the testbench for the VARIABLE TEXT KAT of the twofish cipher with 128 bit key |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
use ieee.std_logic_textio.all; |
use ieee.std_logic_arith.all; |
use std.textio.all; |
|
entity vt_testbench128 is |
end vt_testbench128; |
|
architecture vt_encryption128_testbench_arch of vt_testbench128 is |
|
component reg128 |
port ( |
in_reg128 : in std_logic_vector(127 downto 0); |
out_reg128 : out std_logic_vector(127 downto 0); |
enable_reg128, reset_reg128, clk_reg128 : in std_logic |
); |
end component; |
|
component twofish_keysched128 |
port ( |
odd_in_tk128, |
even_in_tk128 : in std_logic_vector(7 downto 0); |
in_key_tk128 : in std_logic_vector(127 downto 0); |
out_key_up_tk128, |
out_key_down_tk128 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component twofish_whit_keysched128 |
port ( |
in_key_twk128 : in std_logic_vector(127 downto 0); |
out_K0_twk128, |
out_K1_twk128, |
out_K2_twk128, |
out_K3_twk128, |
out_K4_twk128, |
out_K5_twk128, |
out_K6_twk128, |
out_K7_twk128 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component twofish_encryption_round128 |
port ( |
in1_ter128, |
in2_ter128, |
in3_ter128, |
in4_ter128, |
in_Sfirst_ter128, |
in_Ssecond_ter128, |
in_key_up_ter128, |
in_key_down_ter128 : in std_logic_vector(31 downto 0); |
out1_ter128, |
out2_ter128, |
out3_ter128, |
out4_ter128 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component twofish_data_input |
port ( |
in_tdi : in std_logic_vector(127 downto 0); |
out_tdi : out std_logic_vector(127 downto 0) |
); |
end component; |
|
component twofish_data_output |
port ( |
in_tdo : in std_logic_vector(127 downto 0); |
out_tdo : out std_logic_vector(127 downto 0) |
); |
end component; |
|
component demux128 |
port ( in_demux128 : in std_logic_vector(127 downto 0); |
out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0); |
selection_demux128 : in std_logic |
); |
end component; |
|
component mux128 |
port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0); |
selection_mux128 : in std_logic; |
out_mux128 : out std_logic_vector(127 downto 0) |
); |
end component; |
|
component twofish_S128 |
port ( |
in_key_ts128 : in std_logic_vector(127 downto 0); |
out_Sfirst_ts128, |
out_Ssecond_ts128 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
FILE input_file : text is in "twofish_ecb_vt_testvalues_128bits.txt"; |
FILE output_file : text is out "twofish_ecb_vt_128bits_results.txt"; |
|
-- we create the functions that transform a number to text |
-- transforming a signle digit to a character |
function digit_to_char(number : integer range 0 to 9) return character is |
begin |
case number is |
when 0 => return '0'; |
when 1 => return '1'; |
when 2 => return '2'; |
when 3 => return '3'; |
when 4 => return '4'; |
when 5 => return '5'; |
when 6 => return '6'; |
when 7 => return '7'; |
when 8 => return '8'; |
when 9 => return '9'; |
end case; |
end; |
|
-- transforming multi-digit number to text |
function to_text(int_number : integer range 1 to 129) return string is |
variable our_text : string (1 to 3) := (others => ' '); |
variable hundreds, |
tens, |
ones : integer range 0 to 9; |
begin |
ones := int_number mod 10; |
tens := ((int_number mod 100) - ones) / 10; |
hundreds := (int_number - (int_number mod 100)) / 100; |
our_text(1) := digit_to_char(hundreds); |
our_text(2) := digit_to_char(tens); |
our_text(3) := digit_to_char(ones); |
return our_text; |
end; |
|
signal odd_number, |
even_number : std_logic_vector(7 downto 0); |
|
signal input_data, |
output_data, |
twofish_key, |
to_encr_reg128, |
from_tdi_to_xors, |
to_output_whit_xors, |
from_xors_to_tdo, |
to_mux, to_demux, |
from_input_whit_xors, |
to_round, |
to_input_mux : std_logic_vector(127 downto 0) ; |
|
signal key_up, |
key_down, |
Sfirst, |
Ssecond, |
from_xor0, |
from_xor1, |
from_xor2, |
from_xor3, |
K0,K1,K2,K3, |
K4,K5,K6,K7 : std_logic_vector(31 downto 0); |
|
signal clk : std_logic := '0'; |
signal mux_selection : std_logic := '0'; |
signal demux_selection: std_logic := '0'; |
signal enable_encr_reg : std_logic := '0'; |
signal reset : std_logic := '0'; |
signal enable_round_reg : std_logic := '0'; |
|
-- begin the testbench arch description |
begin |
|
|
-- getting data to encrypt |
data_input: twofish_data_input |
port map ( |
in_tdi => input_data, |
out_tdi => from_tdi_to_xors |
); |
|
-- producing whitening keys K0..7 |
the_whitening_step: twofish_whit_keysched128 |
port map ( |
in_key_twk128 => twofish_key, |
out_K0_twk128 => K0, |
out_K1_twk128 => K1, |
out_K2_twk128 => K2, |
out_K3_twk128 => K3, |
out_K4_twk128 => K4, |
out_K5_twk128 => K5, |
out_K6_twk128 => K6, |
out_K7_twk128 => K7 |
); |
|
-- performing the input whitening XORs |
from_xor0 <= K0 XOR from_tdi_to_xors(127 downto 96); |
from_xor1 <= K1 XOR from_tdi_to_xors(95 downto 64); |
from_xor2 <= K2 XOR from_tdi_to_xors(63 downto 32); |
from_xor3 <= K3 XOR from_tdi_to_xors(31 downto 0); |
|
from_input_whit_xors <= from_xor0 & from_xor1 & from_xor2 & from_xor3; |
|
round_reg: reg128 |
port map ( in_reg128 => from_input_whit_xors, |
out_reg128 => to_input_mux, |
enable_reg128 => enable_round_reg, |
reset_reg128 => reset, |
clk_reg128 => clk ); |
|
input_mux: mux128 |
port map ( in1_mux128 => to_input_mux, |
in2_mux128 => to_mux, |
out_mux128 => to_round, |
selection_mux128 => mux_selection |
); |
|
|
-- creating a round |
the_keysched_of_the_round: twofish_keysched128 |
port map ( |
odd_in_tk128 => odd_number, |
even_in_tk128 => even_number, |
in_key_tk128 => twofish_key, |
out_key_up_tk128 => key_up, |
out_key_down_tk128 => key_down |
); |
|
producing_the_Skeys: twofish_S128 |
port map ( |
in_key_ts128 => twofish_key, |
out_Sfirst_ts128 => Sfirst, |
out_Ssecond_ts128 => Ssecond |
); |
|
the_encryption_circuit: twofish_encryption_round128 |
port map ( |
in1_ter128 => to_round(127 downto 96), |
in2_ter128 => to_round(95 downto 64), |
in3_ter128 => to_round(63 downto 32), |
in4_ter128 => to_round(31 downto 0), |
in_Sfirst_ter128 => Sfirst, |
in_Ssecond_ter128 => Ssecond, |
in_key_up_ter128 => key_up, |
in_key_down_ter128 => key_down, |
out1_ter128 => to_encr_reg128(127 downto 96), |
out2_ter128 => to_encr_reg128(95 downto 64), |
out3_ter128 => to_encr_reg128(63 downto 32), |
out4_ter128 => to_encr_reg128(31 downto 0) |
); |
|
encr_reg: reg128 |
port map ( in_reg128 => to_encr_reg128, |
out_reg128 => to_demux, |
enable_reg128 => enable_encr_reg, |
reset_reg128 => reset, |
clk_reg128 => clk ); |
|
output_demux: demux128 |
port map ( in_demux128 => to_demux, |
out1_demux128 => to_output_whit_xors, |
out2_demux128 => to_mux, |
selection_demux128 => demux_selection ); |
|
-- don't forget the last swap !!! |
from_xors_to_tdo(127 downto 96) <= K4 XOR to_output_whit_xors(63 downto 32); |
from_xors_to_tdo(95 downto 64) <= K5 XOR to_output_whit_xors(31 downto 0); |
from_xors_to_tdo(63 downto 32) <= K6 XOR to_output_whit_xors(127 downto 96); |
from_xors_to_tdo(31 downto 0) <= K7 XOR to_output_whit_xors(95 downto 64); |
|
taking_the_output: twofish_data_output |
port map ( |
in_tdo => from_xors_to_tdo, |
out_tdo => output_data |
); |
|
-- we create the clock |
clk <= not clk after 50 ns; -- period 100 ns |
|
|
vt_proc: process |
|
variable pt_f, -- plaintext input from file |
ct_f : line; -- ciphertext from file |
variable pt_v, -- plaintext vector input |
ct_v : std_logic_vector(127 downto 0); -- ciphertext vector |
|
variable counter : integer range 1 to 129 := 1; -- counts the encryptions |
variable round : integer range 1 to 16 := 1; -- holds the rounds of encryption |
|
begin |
|
-- key stays fixed to zero |
twofish_key <= (others => '0'); |
|
while not endfile(input_file) loop |
readline(input_file, pt_f); |
readline(input_file,ct_f); |
hread(pt_f,pt_v); |
hread(ct_f,ct_v); |
input_data <= pt_v; |
wait for 25 ns; |
reset <= '1'; |
wait for 50 ns; |
reset <= '0'; |
mux_selection <= '0'; |
demux_selection <= '1'; |
enable_encr_reg <= '0'; |
enable_round_reg <= '0'; |
wait for 50 ns; |
enable_round_reg <= '1'; |
wait for 50 ns; |
enable_round_reg <= '0'; |
|
-- the first round |
even_number <= "00001000"; -- 8 |
odd_number <= "00001001"; -- 9 |
wait for 50 ns; |
enable_encr_reg <= '1'; |
wait for 50 ns; |
enable_encr_reg <= '0'; |
demux_selection <= '1'; |
mux_selection <= '1'; |
|
-- the rest 15 rounds |
for round in 1 to 15 loop |
even_number <= conv_std_logic_vector(((round*2)+8), 8); |
odd_number <= conv_std_logic_vector(((round*2)+9), 8); |
wait for 50 ns; |
enable_encr_reg <= '1'; |
wait for 50 ns; |
enable_encr_reg <= '0'; |
end loop; |
|
-- taking final results |
demux_selection <= '0'; |
wait for 25 ns; |
assert (ct_v = output_data) report "file entry and encryption result DO NOT match!!! :( " severity failure; |
assert (ct_v /= output_data) report "Encryption I=" & to_text(counter) &" OK" severity note; |
counter := counter+1; |
hwrite(ct_f,output_data); |
hwrite(pt_f,pt_v); |
writeline(output_file,pt_f); |
writeline(output_file,ct_f); |
end loop; |
assert false report "***** Variable Text Known Answer Test with 128 bits key size ended succesfully! :) *****" severity failure; |
end process vt_proc; |
|
end vt_encryption128_testbench_arch; |
|
/trunk/vhdl/twofish_ecb_vt_testbench_192bits.vhd
0,0 → 1,376
-- Twofish_ecb_vt_testbench_192bits.vhd |
-- Copyright (C) 2006 Spyros Ninos |
-- |
-- This program is free software; you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation; either version 2 of the License, or |
-- (at your option) any later version. |
-- |
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU General Public License |
-- along with this library; see the file COPYING. If not, write to: |
-- |
-- Free Software Foundation |
-- 59 Temple Place - Suite 330 |
-- Boston, MA 02111-1307, USA. |
-- |
-- description : this file is the testbench for the VARIABLE TEXT KAT of the twofish cipher with 192 bit key |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
use ieee.std_logic_textio.all; |
use ieee.std_logic_arith.all; |
use std.textio.all; |
|
entity vt_testbench192 is |
end vt_testbench192; |
|
architecture vt_encryption192_testbench_arch of vt_testbench192 is |
|
component reg128 |
port ( |
in_reg128 : in std_logic_vector(127 downto 0); |
out_reg128 : out std_logic_vector(127 downto 0); |
enable_reg128, reset_reg128, clk_reg128 : in std_logic |
); |
end component; |
|
component twofish_keysched192 |
port ( |
odd_in_tk192, |
even_in_tk192 : in std_logic_vector(7 downto 0); |
in_key_tk192 : in std_logic_vector(191 downto 0); |
out_key_up_tk192, |
out_key_down_tk192 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component twofish_whit_keysched192 |
port ( |
in_key_twk192 : in std_logic_vector(191 downto 0); |
out_K0_twk192, |
out_K1_twk192, |
out_K2_twk192, |
out_K3_twk192, |
out_K4_twk192, |
out_K5_twk192, |
out_K6_twk192, |
out_K7_twk192 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component twofish_encryption_round192 |
port ( |
in1_ter192, |
in2_ter192, |
in3_ter192, |
in4_ter192, |
in_Sfirst_ter192, |
in_Ssecond_ter192, |
in_Sthird_ter192, |
in_key_up_ter192, |
in_key_down_ter192 : in std_logic_vector(31 downto 0); |
out1_ter192, |
out2_ter192, |
out3_ter192, |
out4_ter192 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component twofish_data_input |
port ( |
in_tdi : in std_logic_vector(127 downto 0); |
out_tdi : out std_logic_vector(127 downto 0) |
); |
end component; |
|
component twofish_data_output |
port ( |
in_tdo : in std_logic_vector(127 downto 0); |
out_tdo : out std_logic_vector(127 downto 0) |
); |
end component; |
|
component demux128 |
port ( in_demux128 : in std_logic_vector(127 downto 0); |
out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0); |
selection_demux128 : in std_logic |
); |
end component; |
|
component mux128 |
port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0); |
selection_mux128 : in std_logic; |
out_mux128 : out std_logic_vector(127 downto 0) |
); |
end component; |
|
component twofish_S192 |
port ( |
in_key_ts192 : in std_logic_vector(191 downto 0); |
out_Sfirst_ts192, |
out_Ssecond_ts192, |
out_Sthird_ts192 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
FILE input_file : text is in "twofish_ecb_vt_testvalues_192bits.txt"; |
FILE output_file : text is out "twofish_ecb_vt_192bits_results.txt"; |
|
-- we create the functions that transform a number to text |
-- transforming a signle digit to a character |
function digit_to_char(number : integer range 0 to 9) return character is |
begin |
case number is |
when 0 => return '0'; |
when 1 => return '1'; |
when 2 => return '2'; |
when 3 => return '3'; |
when 4 => return '4'; |
when 5 => return '5'; |
when 6 => return '6'; |
when 7 => return '7'; |
when 8 => return '8'; |
when 9 => return '9'; |
end case; |
end; |
|
-- transforming multi-digit number to text |
function to_text(int_number : integer range 1 to 129) return string is |
variable our_text : string (1 to 3) := (others => ' '); |
variable hundreds, |
tens, |
ones : integer range 0 to 9; |
begin |
ones := int_number mod 10; |
tens := ((int_number mod 100) - ones) / 10; |
hundreds := (int_number - (int_number mod 100)) / 100; |
our_text(1) := digit_to_char(hundreds); |
our_text(2) := digit_to_char(tens); |
our_text(3) := digit_to_char(ones); |
return our_text; |
end; |
|
signal odd_number, |
even_number : std_logic_vector(7 downto 0); |
|
signal input_data, |
output_data, |
to_encr_reg128, |
from_tdi_to_xors, |
to_output_whit_xors, |
from_xors_to_tdo, |
to_mux, to_demux, |
from_input_whit_xors, |
to_round, |
to_input_mux : std_logic_vector(127 downto 0) ; |
|
signal twofish_key : std_logic_vector(191 downto 0); |
|
signal key_up, |
key_down, |
Sfirst, |
Ssecond, |
Sthird, |
from_xor0, |
from_xor1, |
from_xor2, |
from_xor3, |
K0,K1,K2,K3, |
K4,K5,K6,K7 : std_logic_vector(31 downto 0); |
|
signal clk : std_logic := '0'; |
signal mux_selection : std_logic := '0'; |
signal demux_selection: std_logic := '0'; |
signal enable_encr_reg : std_logic := '0'; |
signal reset : std_logic := '0'; |
signal enable_round_reg : std_logic := '0'; |
|
-- begin the testbench arch description |
begin |
|
|
-- getting data to encrypt |
data_input: twofish_data_input |
port map ( |
in_tdi => input_data, |
out_tdi => from_tdi_to_xors |
); |
|
-- producing whitening keys K0..7 |
the_whitening_step: twofish_whit_keysched192 |
port map ( |
in_key_twk192 => twofish_key, |
out_K0_twk192 => K0, |
out_K1_twk192 => K1, |
out_K2_twk192 => K2, |
out_K3_twk192 => K3, |
out_K4_twk192 => K4, |
out_K5_twk192 => K5, |
out_K6_twk192 => K6, |
out_K7_twk192 => K7 |
); |
|
-- performing the input whitening XORs |
from_xor0 <= K0 XOR from_tdi_to_xors(127 downto 96); |
from_xor1 <= K1 XOR from_tdi_to_xors(95 downto 64); |
from_xor2 <= K2 XOR from_tdi_to_xors(63 downto 32); |
from_xor3 <= K3 XOR from_tdi_to_xors(31 downto 0); |
|
from_input_whit_xors <= from_xor0 & from_xor1 & from_xor2 & from_xor3; |
|
round_reg: reg128 |
port map ( in_reg128 => from_input_whit_xors, |
out_reg128 => to_input_mux, |
enable_reg128 => enable_round_reg, |
reset_reg128 => reset, |
clk_reg128 => clk ); |
|
input_mux: mux128 |
port map ( in1_mux128 => to_input_mux, |
in2_mux128 => to_mux, |
out_mux128 => to_round, |
selection_mux128 => mux_selection |
); |
|
|
-- creating a round |
the_keysched_of_the_round: twofish_keysched192 |
port map ( |
odd_in_tk192 => odd_number, |
even_in_tk192 => even_number, |
in_key_tk192 => twofish_key, |
out_key_up_tk192 => key_up, |
out_key_down_tk192 => key_down |
); |
|
producing_the_Skeys: twofish_S192 |
port map ( |
in_key_ts192 => twofish_key, |
out_Sfirst_ts192 => Sfirst, |
out_Ssecond_ts192 => Ssecond, |
out_Sthird_ts192 => Sthird |
); |
|
the_encryption_circuit: twofish_encryption_round192 |
port map ( |
in1_ter192 => to_round(127 downto 96), |
in2_ter192 => to_round(95 downto 64), |
in3_ter192 => to_round(63 downto 32), |
in4_ter192 => to_round(31 downto 0), |
in_Sfirst_ter192 => Sfirst, |
in_Ssecond_ter192 => Ssecond, |
in_Sthird_ter192 => Sthird, |
in_key_up_ter192 => key_up, |
in_key_down_ter192 => key_down, |
out1_ter192 => to_encr_reg128(127 downto 96), |
out2_ter192 => to_encr_reg128(95 downto 64), |
out3_ter192 => to_encr_reg128(63 downto 32), |
out4_ter192 => to_encr_reg128(31 downto 0) |
); |
|
encr_reg: reg128 |
port map ( in_reg128 => to_encr_reg128, |
out_reg128 => to_demux, |
enable_reg128 => enable_encr_reg, |
reset_reg128 => reset, |
clk_reg128 => clk ); |
|
output_demux: demux128 |
port map ( in_demux128 => to_demux, |
out1_demux128 => to_output_whit_xors, |
out2_demux128 => to_mux, |
selection_demux128 => demux_selection ); |
|
-- don't forget the last swap !!! |
from_xors_to_tdo(127 downto 96) <= K4 XOR to_output_whit_xors(63 downto 32); |
from_xors_to_tdo(95 downto 64) <= K5 XOR to_output_whit_xors(31 downto 0); |
from_xors_to_tdo(63 downto 32) <= K6 XOR to_output_whit_xors(127 downto 96); |
from_xors_to_tdo(31 downto 0) <= K7 XOR to_output_whit_xors(95 downto 64); |
|
taking_the_output: twofish_data_output |
port map ( |
in_tdo => from_xors_to_tdo, |
out_tdo => output_data |
); |
|
-- we create the clock |
clk <= not clk after 50 ns; -- period 100 ns |
|
|
vt_proc: process |
|
variable pt_f, -- plaintext input from file |
ct_f : line; -- ciphertext from file |
variable pt_v, -- plaintext vector input |
ct_v : std_logic_vector(127 downto 0); -- ciphertext vector |
|
variable counter : integer range 1 to 129 := 1; -- counts the encryptions |
variable round : integer range 1 to 16 := 1; -- holds the rounds of encryption |
|
begin |
|
-- key stays fixed to zero |
twofish_key <= (others => '0'); |
|
while not endfile(input_file) loop |
readline(input_file, pt_f); |
readline(input_file,ct_f); |
hread(pt_f,pt_v); |
hread(ct_f,ct_v); |
input_data <= pt_v; |
wait for 25 ns; |
reset <= '1'; |
wait for 50 ns; |
reset <= '0'; |
mux_selection <= '0'; |
demux_selection <= '1'; |
enable_encr_reg <= '0'; |
enable_round_reg <= '0'; |
wait for 50 ns; |
enable_round_reg <= '1'; |
wait for 50 ns; |
enable_round_reg <= '0'; |
|
-- the first round |
even_number <= "00001000"; -- 8 |
odd_number <= "00001001"; -- 9 |
wait for 50 ns; |
enable_encr_reg <= '1'; |
wait for 50 ns; |
enable_encr_reg <= '0'; |
demux_selection <= '1'; |
mux_selection <= '1'; |
|
-- the rest 15 rounds |
for round in 1 to 15 loop |
even_number <= conv_std_logic_vector(((round*2)+8), 8); |
odd_number <= conv_std_logic_vector(((round*2)+9), 8); |
wait for 50 ns; |
enable_encr_reg <= '1'; |
wait for 50 ns; |
enable_encr_reg <= '0'; |
end loop; |
|
-- taking final results |
demux_selection <= '0'; |
wait for 25 ns; |
assert (ct_v = output_data) report "file entry and encryption result DO NOT match!!! :( " severity failure; |
assert (ct_v /= output_data) report "Encryption I=" & to_text(counter) &" OK" severity note; |
counter := counter+1; |
hwrite(ct_f,output_data); |
hwrite(pt_f,pt_v); |
writeline(output_file,pt_f); |
writeline(output_file,ct_f); |
end loop; |
assert false report "***** Variable Text Known Answer Test with 192 bits key size ended succesfully! :) *****" severity failure; |
end process vt_proc; |
|
end vt_encryption192_testbench_arch; |
|
/trunk/vhdl/twofish.vhd
0,0 → 1,5527
-- Twofish.vhd |
-- Copyright (C) 2006 Spyros Ninos |
-- |
-- This program is free software; you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation; either version 2 of the License, or |
-- (at your option) any later version. |
-- |
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU General Public License |
-- along with this library; see the file COPYING. If not, write to: |
-- |
-- Free Software Foundation |
-- 59 Temple Place - Suite 330 |
-- Boston, MA 02111-1307, USA. |
|
-- description : this file includes all the components necessary to perform symmetric encryption |
-- with the twofish 128 bit block cipher. Within there are four main parts of the file. |
-- the first part is the twofish crypto primitives which are independent of the key |
-- input length, the second part is the 128 bit key input components, the third part |
-- is the 192 bit key components and finaly the 256 bit key input components |
-- |
|
|
-- ====================================================== -- |
-- ====================================================== -- |
-- -- |
-- first part: key input independent component primitives -- |
-- -- |
-- ====================================================== -- |
-- ====================================================== -- |
|
-- |
-- q0 |
-- |
|
library ieee; |
Use ieee.std_logic_1164.all; |
|
entity q0 is |
port ( |
in_q0 : in std_logic_vector(7 downto 0); |
out_q0 : out std_logic_vector(7 downto 0) |
); |
end q0; |
|
architecture q0_arch of q0 is |
|
-- declaring internal signals |
signal a0,b0, |
a1,b1, |
a2,b2, |
a3,b3, |
a4,b4 : std_logic_vector(3 downto 0); |
signal b0_ror4, |
a0_times_8, |
b2_ror4, |
a2_times_8 : std_logic_vector(3 downto 0); |
|
-- beginning of the architecture description |
begin |
|
-- little endian |
b0 <= in_q0(3 downto 0); |
a0 <= in_q0(7 downto 4); |
|
a1 <= a0 XOR b0; |
|
-- signal b0 is ror4'ed by 1 bit |
b0_ror4(2 downto 0) <= b0(3 downto 1); |
b0_ror4(3) <= b0(0); |
|
-- 8*a0 = 2^3*a0= a0 << 3 |
a0_times_8(2 downto 0) <= (others => '0'); |
a0_times_8(3) <= a0(0); |
|
b1 <= a0 XOR b0_ror4 XOR a0_times_8; |
|
-- |
-- t0 table |
-- |
with a1 select |
a2 <= "1000" when "0000", -- 8 |
"0001" when "0001", -- 1 |
"0111" when "0010", -- 7 |
"1101" when "0011", -- D |
"0110" when "0100", -- 6 |
"1111" when "0101", -- F |
"0011" when "0110", -- 3 |
"0010" when "0111", -- 2 |
"0000" when "1000", -- 0 |
"1011" when "1001", -- B |
"0101" when "1010", -- 5 |
"1001" when "1011", -- 9 |
"1110" when "1100", -- E |
"1100" when "1101", -- C |
"1010" when "1110", -- A |
"0100" when others; -- 4 |
|
-- |
-- t1 table |
-- |
with b1 select |
b2 <= "1110" when "0000", -- E |
"1100" when "0001", -- C |
"1011" when "0010", -- B |
"1000" when "0011", -- 8 |
"0001" when "0100", -- 1 |
"0010" when "0101", -- 2 |
"0011" when "0110", -- 3 |
"0101" when "0111", -- 5 |
"1111" when "1000", -- F |
"0100" when "1001", -- 4 |
"1010" when "1010", -- A |
"0110" when "1011", -- 6 |
"0111" when "1100", -- 7 |
"0000" when "1101", -- 0 |
"1001" when "1110", -- 9 |
"1101" when others; -- D |
|
a3 <= a2 XOR b2; |
|
-- signal b2 is ror4'ed by 1 bit |
b2_ror4(2 downto 0) <= b2(3 downto 1); |
b2_ror4(3) <= b2(0); |
|
-- 8*a2 = 2^3*a2=a2<<3 |
a2_times_8(2 downto 0) <= (others => '0'); |
a2_times_8(3) <= a2(0); |
|
b3 <= a2 XOR b2_ror4 XOR a2_times_8; |
|
|
-- |
-- t0 table |
-- |
with a3 select |
a4 <= "1011" when "0000", -- B |
"1010" when "0001", -- A |
"0101" when "0010", -- 5 |
"1110" when "0011", -- E |
"0110" when "0100", -- 6 |
"1101" when "0101", -- D |
"1001" when "0110", -- 9 |
"0000" when "0111", -- 0 |
"1100" when "1000", -- C |
"1000" when "1001", -- 8 |
"1111" when "1010", -- F |
"0011" when "1011", -- 3 |
"0010" when "1100", -- 2 |
"0100" when "1101", -- 4 |
"0111" when "1110", -- 7 |
"0001" when others; -- 1 |
|
-- |
-- t1 table |
-- |
with b3 select |
b4 <= "1101" when "0000", -- D |
"0111" when "0001", -- 7 |
"1111" when "0010", -- F |
"0100" when "0011", -- 4 |
"0001" when "0100", -- 1 |
"0010" when "0101", -- 2 |
"0110" when "0110", -- 6 |
"1110" when "0111", -- E |
"1001" when "1000", -- 9 |
"1011" when "1001", -- B |
"0011" when "1010", -- 3 |
"0000" when "1011", -- 0 |
"1000" when "1100", -- 8 |
"0101" when "1101", -- 5 |
"1100" when "1110", -- C |
"1010" when others; -- A |
|
-- the output of q0 |
out_q0 <= b4 & a4; |
|
end q0_arch; |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
-- |
-- q1 |
-- |
|
library ieee; |
Use ieee.std_logic_1164.all; |
|
entity q1 is |
port ( |
in_q1 : in std_logic_vector(7 downto 0); |
out_q1 : out std_logic_vector(7 downto 0) |
); |
end q1; |
|
-- architecture description |
architecture q1_arch of q1 is |
|
-- declaring the internal signals |
signal a0,b0, |
a1,b1, |
a2,b2, |
a3,b3, |
a4,b4 : std_logic_vector(3 downto 0); |
signal b0_ror4, |
a0_times_8, |
b2_ror4, |
a2_times_8 : std_logic_vector(3 downto 0); |
|
-- begin the architecture description |
begin |
|
-- little endian |
b0 <= in_q1(3 downto 0); |
a0 <= in_q1(7 downto 4); |
|
a1 <= a0 XOR b0; |
|
-- signal b0 is ror4'ed by 1 bit |
b0_ror4(2 downto 0) <= b0(3 downto 1); |
b0_ror4(3) <= b0(0); |
|
-- 8*a0 = 2^3*a0=a0<<3 |
a0_times_8(2 downto 0) <= (others => '0'); |
a0_times_8(3) <= a0(0); |
|
b1 <= a0 XOR b0_ror4 XOR a0_times_8; |
|
-- |
-- t0 table |
-- |
with a1 select |
a2 <= "0010" when "0000", -- 2 |
"1000" when "0001", -- 8 |
"1011" when "0010", -- b |
"1101" when "0011", -- d |
"1111" when "0100", -- f |
"0111" when "0101", -- 7 |
"0110" when "0110", -- 6 |
"1110" when "0111", -- e |
"0011" when "1000", -- 3 |
"0001" when "1001", -- 1 |
"1001" when "1010", -- 9 |
"0100" when "1011", -- 4 |
"0000" when "1100", -- 0 |
"1010" when "1101", -- a |
"1100" when "1110", -- c |
"0101" when others; -- 5 |
|
-- |
-- t1 table |
-- |
with b1 select |
b2 <= "0001" when "0000", -- 1 |
"1110" when "0001", -- e |
"0010" when "0010", -- 2 |
"1011" when "0011", -- b |
"0100" when "0100", -- 4 |
"1100" when "0101", -- c |
"0011" when "0110", -- 3 |
"0111" when "0111", -- 7 |
"0110" when "1000", -- 6 |
"1101" when "1001", -- d |
"1010" when "1010", -- a |
"0101" when "1011", -- 5 |
"1111" when "1100", -- f |
"1001" when "1101", -- 9 |
"0000" when "1110", -- 0 |
"1000" when others; -- 8 |
|
a3 <= a2 XOR b2; |
|
-- signal b2 is ror4'ed by 1 bit |
b2_ror4(2 downto 0) <= b2(3 downto 1); |
b2_ror4(3) <= b2(0); |
|
-- 8*a2 = 2^3*a2=a2<<3 |
a2_times_8(2 downto 0) <= (others => '0'); |
a2_times_8(3) <= a2(0); |
|
b3 <= a2 XOR b2_ror4 XOR a2_times_8; |
|
-- |
-- t0 table |
-- |
with a3 select |
a4 <= "0100" when "0000", -- 4 |
"1100" when "0001", -- c |
"0111" when "0010", -- 7 |
"0101" when "0011", -- 5 |
"0001" when "0100", -- 1 |
"0110" when "0101", -- 6 |
"1001" when "0110", -- 9 |
"1010" when "0111", -- a |
"0000" when "1000", -- 0 |
"1110" when "1001", -- e |
"1101" when "1010", -- d |
"1000" when "1011", -- 8 |
"0010" when "1100", -- 2 |
"1011" when "1101", -- b |
"0011" when "1110", -- 3 |
"1111" when others; -- f |
|
-- |
-- t1 table |
-- |
with b3 select |
b4 <= "1011" when "0000", -- b |
"1001" when "0001", -- 9 |
"0101" when "0010", -- 5 |
"0001" when "0011", -- 1 |
"1100" when "0100", -- c |
"0011" when "0101", -- 3 |
"1101" when "0110", -- d |
"1110" when "0111", -- e |
"0110" when "1000", -- 6 |
"0100" when "1001", -- 4 |
"0111" when "1010", -- 7 |
"1111" when "1011", -- f |
"0010" when "1100", -- 2 |
"0000" when "1101", -- 0 |
"1000" when "1110", -- 8 |
"1010" when others; -- a |
|
-- output of q1 |
out_q1 <= b4 & a4; |
|
end q1_arch; |
|
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
-- |
-- ef multiplier |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity mul_ef is |
port ( |
in_ef : in std_logic_vector(7 downto 0); |
out_ef : out std_logic_vector(7 downto 0) |
); |
end mul_ef; |
|
|
architecture mul_ef_arch of mul_ef is |
|
begin |
out_ef(0) <= in_ef(2) XOR in_ef(1) XOR in_ef(0); |
out_ef(1) <= in_ef(3) XOR in_ef(2) XOR in_ef(1) XOR in_ef(0); |
out_ef(2) <= in_ef(4) XOR in_ef(3) XOR in_ef(2) XOR in_ef(1) XOR in_ef(0); |
out_ef(3) <= in_ef(5) XOR in_ef(4) XOR in_ef(3) XOR in_ef(0); |
out_ef(4) <= in_ef(6) XOR in_ef(5) XOR in_ef(4) XOR in_ef(1); |
out_ef(5) <= in_ef(7) XOR in_ef(6) XOR in_ef(5) XOR in_ef(1) XOR in_ef(0); |
out_ef(6) <= in_ef(7) XOR in_ef(6) XOR in_ef(0); |
out_ef(7) <= in_ef(7) XOR in_ef(1) XOR in_ef(0); |
end mul_ef_arch; |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
|
-- |
-- 5b multiplier |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity mul_5b is |
port ( |
in_5b : in std_logic_vector(7 downto 0); |
out_5b : out std_logic_vector(7 downto 0) |
); |
end mul_5b; |
|
architecture mul_5b_arch of mul_5b is |
begin |
out_5b(0) <= in_5b(2) XOR in_5b(0); |
out_5b(1) <= in_5b(3) XOR in_5b(1) XOR in_5b(0); |
out_5b(2) <= in_5b(4) XOR in_5b(2) XOR in_5b(1); |
out_5b(3) <= in_5b(5) XOR in_5b(3) XOR in_5b(0); |
out_5b(4) <= in_5b(6) XOR in_5b(4) XOR in_5b(1) XOR in_5b(0); |
out_5b(5) <= in_5b(7) XOR in_5b(5) XOR in_5b(1); |
out_5b(6) <= in_5b(6) XOR in_5b(0); |
out_5b(7) <= in_5b(7) XOR in_5b(1); |
end mul_5b_arch; |
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
-- |
-- mds |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity mds is |
port ( |
y0, |
y1, |
y2, |
y3 : in std_logic_vector(7 downto 0); |
z0, |
z1, |
z2, |
z3 : out std_logic_vector(7 downto 0) |
); |
end mds; |
|
|
-- architecture description of mds component |
architecture mds_arch of mds is |
|
-- we declare the multiplier by ef |
component mul_ef |
port ( |
in_ef : in std_logic_vector(7 downto 0); |
out_ef : out std_logic_vector(7 downto 0) |
); |
end component; |
|
-- we declare the multiplier by 5b |
component mul_5b |
port ( |
in_5b : in std_logic_vector(7 downto 0); |
out_5b : out std_logic_vector(7 downto 0) |
); |
end component; |
|
-- we declare the multiplier's outputs |
signal y0_ef, y0_5b, |
y1_ef, y1_5b, |
y2_ef, y2_5b, |
y3_ef, y3_5b : std_logic_vector(7 downto 0); |
|
begin |
|
-- we perform the signal multiplication |
y0_times_ef: mul_ef |
port map ( |
in_ef => y0, |
out_ef => y0_ef |
); |
|
y0_times_5b: mul_5b |
port map ( |
in_5b => y0, |
out_5b => y0_5b |
); |
|
y1_times_ef: mul_ef |
port map ( |
in_ef => y1, |
out_ef => y1_ef |
); |
|
y1_times_5b: mul_5b |
port map ( |
in_5b => y1, |
out_5b => y1_5b |
); |
|
y2_times_ef: mul_ef |
port map ( |
in_ef => y2, |
out_ef => y2_ef |
); |
|
y2_times_5b: mul_5b |
port map ( |
in_5b => y2, |
out_5b => y2_5b |
); |
|
y3_times_ef: mul_ef |
port map ( |
in_ef => y3, |
out_ef => y3_ef |
); |
|
y3_times_5b: mul_5b |
port map ( |
in_5b => y3, |
out_5b => y3_5b |
); |
|
-- we perform the addition of the partial results in order to receive |
-- the table output |
|
-- z0 = y0*01 + y1*ef + y2*5b + y3*5b , opoy + bazoyme XOR |
z0 <= y0 XOR y1_ef XOR y2_5b XOR y3_5b; |
|
-- z1 = y0*5b + y1*ef + y2*ef + y3*01 |
z1 <= y0_5b XOR y1_ef XOR y2_ef XOR y3; |
|
-- z2 = y0*ef + y1*5b + y2*01 +y3*ef |
z2 <= y0_ef XOR y1_5b XOR y2 XOR y3_ef; |
|
-- z3 = y0*ef + y1*01 + y2*ef + y3*5b |
z3 <= y0_ef XOR y1 XOR y2_ef XOR y3_5b; |
|
end mds_arch; |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
-- |
-- 1 bit adder |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity adder is |
port ( |
in1_adder, |
in2_adder, |
in_carry_adder : in std_logic; |
out_adder, |
out_carry_adder : out std_logic |
); |
end adder; |
|
architecture adder_arch of adder is |
begin |
|
out_adder <= in_carry_adder XOR in1_adder XOR in2_adder; |
out_carry_adder <= (in_carry_adder AND (in1_adder XOR in2_adder)) OR (in1_adder AND in2_adder); |
|
end adder_arch; |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
-- |
-- pht |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity pht is |
port ( |
up_in_pht, |
down_in_pht : in std_logic_vector(31 downto 0); |
up_out_pht, |
down_out_pht : out std_logic_vector(31 downto 0) |
); |
end pht; |
|
|
-- architecture description |
architecture pht_arch of pht is |
|
-- we declare internal signals |
signal intermediate_carry1, |
intermediate_carry2, |
to_upper_out : std_logic_vector(31 downto 0); |
signal zero : std_logic; |
|
component adder |
port ( |
in1_adder, |
in2_adder, |
in_carry_adder : in std_logic; |
out_adder, |
out_carry_adder : out std_logic |
); |
end component; |
|
begin |
|
-- initializing zero signal |
zero <= '0'; |
|
-- instantiating the upper adder of 32 bits |
up_adder: for i in 0 to 31 generate |
adder_one: if (i=0) generate |
the_adder: adder |
port map ( |
in1_adder => up_in_pht(0), |
in2_adder => down_in_pht(0), |
in_carry_adder => zero, |
out_adder => to_upper_out(0), |
out_carry_adder => intermediate_carry1(0) |
); |
end generate adder_one; |
rest_adders: if (i>0) generate |
next_adder: adder |
port map ( |
in1_adder => up_in_pht(i), |
in2_adder => down_in_pht(i), |
in_carry_adder => intermediate_carry1(i-1), |
out_adder => to_upper_out(i), |
out_carry_adder => intermediate_carry1(i) |
); |
end generate rest_adders; |
end generate up_adder; |
|
intermediate_carry1(31) <= '0'; |
|
-- receiving the upper pht output |
up_out_pht <= to_upper_out; |
|
-- instantiating the lower adder of 32 bits |
down_adder: for i in 0 to 31 generate |
adder_one_1: if (i=0) generate |
the_adder_1: adder |
port map ( |
in1_adder => down_in_pht(0), |
in2_adder => to_upper_out(0), |
in_carry_adder => zero, |
out_adder => down_out_pht(0), |
out_carry_adder => intermediate_carry2(0) |
); |
end generate adder_one_1; |
rest_adders_1: if (i>0) generate |
next_adder_1: adder |
port map ( |
in1_adder => down_in_pht(i), |
in2_adder => to_upper_out(i), |
in_carry_adder => intermediate_carry2(i-1), |
out_adder => down_out_pht(i), |
out_carry_adder => intermediate_carry2(i) |
); |
end generate rest_adders_1; |
end generate down_adder; |
|
intermediate_carry2(31) <= '0'; |
|
end pht_arch; |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
-- |
-- multiplier by 01 |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity mul01 is |
port ( |
in_mul01 : in std_logic_vector(7 downto 0); |
out_mul01 : out std_logic_vector(7 downto 0) |
); |
end mul01; |
|
architecture mul01_arch of mul01 is |
begin |
out_mul01 <= in_mul01; |
end mul01_arch; |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
-- |
-- multiplier by a4 |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity mula4 is |
port ( |
in_mula4 : in std_logic_vector(7 downto 0); |
out_mula4 : out std_logic_vector(7 downto 0) |
); |
end mula4; |
|
architecture mula4_arch of mula4 is |
begin |
out_mula4(0) <= in_mula4(7) xor in_mula4(1); |
out_mula4(1) <= in_mula4(2); |
out_mula4(2) <= in_mula4(7) xor in_mula4(3) xor in_mula4(1) xor in_mula4(0); |
out_mula4(3) <= in_mula4(7) xor in_mula4(4) xor in_mula4(2); |
out_mula4(4) <= in_mula4(5) xor in_mula4(3); |
out_mula4(5) <= in_mula4(6) xor in_mula4(4) xor in_mula4(0); |
out_mula4(6) <= in_mula4(5); |
out_mula4(7) <= in_mula4(6) xor in_mula4(0); |
end mula4_arch; |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
-- |
-- multiplier by 55 |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity mul55 is |
port ( |
in_mul55 : in std_logic_vector(7 downto 0); |
out_mul55 : out std_logic_vector(7 downto 0) |
); |
end mul55; |
|
architecture mul55_arch of mul55 is |
begin |
out_mul55(0) <= in_mul55(7) xor in_mul55(6) xor in_mul55(2) xor in_mul55(0); |
out_mul55(1) <= in_mul55(7) xor in_mul55(3) xor in_mul55(1); |
out_mul55(2) <= in_mul55(7) xor in_mul55(6) xor in_mul55(4) xor in_mul55(0); |
out_mul55(3) <= in_mul55(6) xor in_mul55(5) xor in_mul55(2) xor in_mul55(1); |
out_mul55(4) <= in_mul55(7) xor in_mul55(6) xor in_mul55(3) xor in_mul55(2) xor in_mul55(0); |
out_mul55(5) <= in_mul55(7) xor in_mul55(4) xor in_mul55(3) xor in_mul55(1); |
out_mul55(6) <= in_mul55(7) xor in_mul55(6) xor in_mul55(5) xor in_mul55(4) xor in_mul55(0); |
out_mul55(7) <= in_mul55(7) xor in_mul55(6) xor in_mul55(5) xor in_mul55(1); |
end mul55_arch; |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
-- |
-- multiplier by 87 |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity mul87 is |
port ( |
in_mul87 : in std_logic_vector(7 downto 0); |
out_mul87 : out std_logic_vector(7 downto 0) |
); |
end mul87; |
|
architecture mul87_arch of mul87 is |
begin |
out_mul87(0) <= in_mul87(7) xor in_mul87(5) xor in_mul87(3) xor in_mul87(1) xor in_mul87(0); |
out_mul87(1) <= in_mul87(6) xor in_mul87(4) xor in_mul87(2) xor in_mul87(1) xor in_mul87(0); |
out_mul87(2) <= in_mul87(2) xor in_mul87(0); |
out_mul87(3) <= in_mul87(7) xor in_mul87(5); |
out_mul87(4) <= in_mul87(6); |
out_mul87(5) <= in_mul87(7); |
out_mul87(6) <= in_mul87(7) xor in_mul87(5) xor in_mul87(3) xor in_mul87(1); |
out_mul87(7) <= in_mul87(6) xor in_mul87(4) xor in_mul87(2) xor in_mul87(0); |
end mul87_arch; |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
-- |
-- multiplier by 5a |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity mul5a is |
port ( |
in_mul5a : in std_logic_vector(7 downto 0); |
out_mul5a : out std_logic_vector(7 downto 0) |
); |
end mul5a; |
|
architecture mul5a_arch of mul5a is |
begin |
out_mul5a(0) <= in_mul5a(7) xor in_mul5a(5) xor in_mul5a(2); |
out_mul5a(1) <= in_mul5a(6) xor in_mul5a(3) xor in_mul5a(0); |
out_mul5a(2) <= in_mul5a(5) xor in_mul5a(4) xor in_mul5a(2) xor in_mul5a(1); |
out_mul5a(3) <= in_mul5a(7) xor in_mul5a(6) xor in_mul5a(3) xor in_mul5a(0); |
out_mul5a(4) <= in_mul5a(7) xor in_mul5a(4) xor in_mul5a(1) xor in_mul5a(0); |
out_mul5a(5) <= in_mul5a(5) xor in_mul5a(2) xor in_mul5a(1); |
out_mul5a(6) <= in_mul5a(7) xor in_mul5a(6) xor in_mul5a(5) xor in_mul5a(3) xor in_mul5a(0); |
out_mul5a(7) <= in_mul5a(7) xor in_mul5a(6) xor in_mul5a(4) xor in_mul5a(1); |
end mul5a_arch; |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
-- |
-- multiplier by 58 |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity mul58 is |
port ( |
in_mul58 : in std_logic_vector(7 downto 0); |
out_mul58 : out std_logic_vector(7 downto 0) |
); |
end mul58; |
|
architecture mul58_arch of mul58 is |
begin |
out_mul58(0) <= in_mul58(5) xor in_mul58(2); |
out_mul58(1) <= in_mul58(6) xor in_mul58(3); |
out_mul58(2) <= in_mul58(7) xor in_mul58(5) xor in_mul58(4) xor in_mul58(2); |
out_mul58(3) <= in_mul58(6) xor in_mul58(3) xor in_mul58(2) xor in_mul58(0); |
out_mul58(4) <= in_mul58(7) xor in_mul58(4) xor in_mul58(3) xor in_mul58(1) xor in_mul58(0); |
out_mul58(5) <= in_mul58(5) xor in_mul58(4) xor in_mul58(2) xor in_mul58(1); |
out_mul58(6) <= in_mul58(6) xor in_mul58(3) xor in_mul58(0); |
out_mul58(7) <= in_mul58(7) xor in_mul58(4) xor in_mul58(1); |
end mul58_arch; |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
-- |
-- multiplier by db |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity muldb is |
port ( |
in_muldb : in std_logic_vector(7 downto 0); |
out_muldb : out std_logic_vector(7 downto 0) |
); |
end muldb; |
|
architecture muldb_arch of muldb is |
begin |
out_muldb(0) <= in_muldb(7) xor in_muldb(6) xor in_muldb(3) xor in_muldb(2) xor in_muldb(1) xor in_muldb(0); |
out_muldb(1) <= in_muldb(7) xor in_muldb(4) xor in_muldb(3) xor in_muldb(2) xor in_muldb(1) xor in_muldb(0); |
out_muldb(2) <= in_muldb(7) xor in_muldb(6) xor in_muldb(5) xor in_muldb(4); |
out_muldb(3) <= in_muldb(5) xor in_muldb(3) xor in_muldb(2) xor in_muldb(1) xor in_muldb(0); |
out_muldb(4) <= in_muldb(6) xor in_muldb(4) xor in_muldb(3) xor in_muldb(2) xor in_muldb(1) xor in_muldb(0); |
out_muldb(5) <= in_muldb(7) xor in_muldb(5) xor in_muldb(4) xor in_muldb(3) xor in_muldb(2) xor in_muldb(1); |
out_muldb(6) <= in_muldb(7) xor in_muldb(5) xor in_muldb(4) xor in_muldb(1) xor in_muldb(0); |
out_muldb(7) <= in_muldb(6) xor in_muldb(5) xor in_muldb(2) xor in_muldb(1) xor in_muldb(0); |
end muldb_arch; |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
-- |
-- multiplier by 9e |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity mul9e is |
port ( |
in_mul9e : in std_logic_vector(7 downto 0); |
out_mul9e : out std_logic_vector(7 downto 0) |
); |
end mul9e; |
|
architecture mul9e_arch of mul9e is |
begin |
out_mul9e(0) <= in_mul9e(6) xor in_mul9e(4) xor in_mul9e(3) xor in_mul9e(1); |
out_mul9e(1) <= in_mul9e(7) xor in_mul9e(5) xor in_mul9e(4) xor in_mul9e(2) xor in_mul9e(0); |
out_mul9e(2) <= in_mul9e(5) xor in_mul9e(4) xor in_mul9e(0); |
out_mul9e(3) <= in_mul9e(5) xor in_mul9e(4) xor in_mul9e(3) xor in_mul9e(0); |
out_mul9e(4) <= in_mul9e(6) xor in_mul9e(5) xor in_mul9e(4) xor in_mul9e(1) xor in_mul9e(0); |
out_mul9e(5) <= in_mul9e(7) xor in_mul9e(6) xor in_mul9e(5) xor in_mul9e(2) xor in_mul9e(1); |
out_mul9e(6) <= in_mul9e(7) xor in_mul9e(4) xor in_mul9e(2) xor in_mul9e(1); |
out_mul9e(7) <= in_mul9e(5) xor in_mul9e(3) xor in_mul9e(2) xor in_mul9e(0); |
end mul9e_arch; |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
-- |
-- multiplier by 56 |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity mul56 is |
port ( |
in_mul56 : in std_logic_vector(7 downto 0); |
out_mul56 : out std_logic_vector(7 downto 0) |
); |
end mul56; |
|
architecture mul56_arch of mul56 is |
begin |
out_mul56(0) <= in_mul56(6) xor in_mul56(2); |
out_mul56(1) <= in_mul56(7) xor in_mul56(3) xor in_mul56(0); |
out_mul56(2) <= in_mul56(6) xor in_mul56(4) xor in_mul56(2) xor in_mul56(1) xor in_mul56(0); |
out_mul56(3) <= in_mul56(7) xor in_mul56(6) xor in_mul56(5) xor in_mul56(3) xor in_mul56(1); |
out_mul56(4) <= in_mul56(7) xor in_mul56(6) xor in_mul56(4) xor in_mul56(2) xor in_mul56(0); |
out_mul56(5) <= in_mul56(7) xor in_mul56(5) xor in_mul56(3) xor in_mul56(1); |
out_mul56(6) <= in_mul56(4) xor in_mul56(0); |
out_mul56(7) <= in_mul56(5) xor in_mul56(1); |
end mul56_arch; |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
-- |
-- multiplier by 82 |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity mul82 is |
port ( |
in_mul82 : in std_logic_vector(7 downto 0); |
out_mul82 : out std_logic_vector(7 downto 0) |
); |
end mul82; |
|
architecture mul82_arch of mul82 is |
begin |
out_mul82(0) <= in_mul82(7) xor in_mul82(6) xor in_mul82(5) xor in_mul82(3) xor in_mul82(1); |
out_mul82(1) <= in_mul82(7) xor in_mul82(6) xor in_mul82(4) xor in_mul82(2) xor in_mul82(0); |
out_mul82(2) <= in_mul82(6); |
out_mul82(3) <= in_mul82(6) xor in_mul82(5) xor in_mul82(3) xor in_mul82(1); |
out_mul82(4) <= in_mul82(7) xor in_mul82(6) xor in_mul82(4) xor in_mul82(2); |
out_mul82(5) <= in_mul82(7) xor in_mul82(5) xor in_mul82(3); |
out_mul82(6) <= in_mul82(7) xor in_mul82(5) xor in_mul82(4) xor in_mul82(3) xor in_mul82(1); |
out_mul82(7) <= in_mul82(6) xor in_mul82(5) xor in_mul82(4) xor in_mul82(2) xor in_mul82(0); |
end mul82_arch; |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
-- |
-- multiplier by f3 |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity mulf3 is |
port ( |
in_mulf3 : in std_logic_vector(7 downto 0); |
out_mulf3 : out std_logic_vector(7 downto 0) |
); |
end mulf3; |
|
architecture mulf3_arch of mulf3 is |
begin |
out_mulf3(0) <= in_mulf3(7) xor in_mulf3(6) xor in_mulf3(2) xor in_mulf3(1) xor in_mulf3(0); |
out_mulf3(1) <= in_mulf3(7) xor in_mulf3(3) xor in_mulf3(2) xor in_mulf3(1) xor in_mulf3(0); |
out_mulf3(2) <= in_mulf3(7) xor in_mulf3(6) xor in_mulf3(4) xor in_mulf3(3); |
out_mulf3(3) <= in_mulf3(6) xor in_mulf3(5) xor in_mulf3(4) xor in_mulf3(2) xor in_mulf3(1); |
out_mulf3(4) <= in_mulf3(7) xor in_mulf3(6) xor in_mulf3(5) xor in_mulf3(3) xor in_mulf3(2) xor in_mulf3(0); |
out_mulf3(5) <= in_mulf3(7) xor in_mulf3(6) xor in_mulf3(4) xor in_mulf3(3) xor in_mulf3(1) xor in_mulf3(0); |
out_mulf3(6) <= in_mulf3(6) xor in_mulf3(5) xor in_mulf3(4) xor in_mulf3(0); |
out_mulf3(7) <= in_mulf3(7) xor in_mulf3(6) xor in_mulf3(5) xor in_mulf3(1) xor in_mulf3(0); |
end mulf3_arch; |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
-- |
-- multiplier by 1e |
-- |
|
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity mul1e is |
port ( |
in_mul1e : in std_logic_vector(7 downto 0); |
out_mul1e : out std_logic_vector(7 downto 0) |
); |
end mul1e; |
|
architecture mul1e_arch of mul1e is |
begin |
out_mul1e(0) <= in_mul1e(5) xor in_mul1e(4); |
out_mul1e(1) <= in_mul1e(6) xor in_mul1e(5) xor in_mul1e(0); |
out_mul1e(2) <= in_mul1e(7) xor in_mul1e(6) xor in_mul1e(5) xor in_mul1e(4) xor in_mul1e(1) xor in_mul1e(0); |
out_mul1e(3) <= in_mul1e(7) xor in_mul1e(6) xor in_mul1e(4) xor in_mul1e(2) xor in_mul1e(1) xor in_mul1e(0); |
out_mul1e(4) <= in_mul1e(7) xor in_mul1e(5) xor in_mul1e(3) xor in_mul1e(2) xor in_mul1e(1) xor in_mul1e(0); |
out_mul1e(5) <= in_mul1e(6) xor in_mul1e(4) xor in_mul1e(3) xor in_mul1e(2) xor in_mul1e(1); |
out_mul1e(6) <= in_mul1e(7) xor in_mul1e(3) xor in_mul1e(2); |
out_mul1e(7) <= in_mul1e(4) xor in_mul1e(3); |
end mul1e_arch; |
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
-- |
-- multiplier by c6 |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity mulc6 is |
port ( |
in_mulc6 : in std_logic_vector(7 downto 0); |
out_mulc6 : out std_logic_vector(7 downto 0) |
); |
end mulc6; |
|
architecture mulc6_arch of mulc6 is |
begin |
out_mulc6(0) <= in_mulc6(6) xor in_mulc6(5) xor in_mulc6(4) xor in_mulc6(3) xor in_mulc6(2) xor in_mulc6(1); |
out_mulc6(1) <= in_mulc6(7) xor in_mulc6(6) xor in_mulc6(5) xor in_mulc6(4) xor in_mulc6(3) xor in_mulc6(2) xor in_mulc6(0); |
out_mulc6(2) <= in_mulc6(7) xor in_mulc6(2) xor in_mulc6(0); |
out_mulc6(3) <= in_mulc6(6) xor in_mulc6(5) xor in_mulc6(4) xor in_mulc6(2); |
out_mulc6(4) <= in_mulc6(7) xor in_mulc6(6) xor in_mulc6(5) xor in_mulc6(3); |
out_mulc6(5) <= in_mulc6(7) xor in_mulc6(6) xor in_mulc6(4); |
out_mulc6(6) <= in_mulc6(7) xor in_mulc6(6) xor in_mulc6(4) xor in_mulc6(3) xor in_mulc6(2) xor in_mulc6(1) xor in_mulc6(0); |
out_mulc6(7) <= in_mulc6(7) xor in_mulc6(5) xor in_mulc6(4) xor in_mulc6(3) xor in_mulc6(2) xor in_mulc6(1) xor in_mulc6(0); |
end mulc6_arch; |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
-- |
-- multiplier by 68 |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity mul68 is |
port ( |
in_mul68 : in std_logic_vector(7 downto 0); |
out_mul68 : out std_logic_vector(7 downto 0) |
); |
end mul68; |
|
|
architecture mul68_arch of mul68 is |
begin |
out_mul68(0) <= in_mul68(7) xor in_mul68(6) xor in_mul68(4) xor in_mul68(3) xor in_mul68(2); |
out_mul68(1) <= in_mul68(7) xor in_mul68(5) xor in_mul68(4) xor in_mul68(3); |
out_mul68(2) <= in_mul68(7) xor in_mul68(5) xor in_mul68(3) xor in_mul68(2); |
out_mul68(3) <= in_mul68(7) xor in_mul68(2) xor in_mul68(0); |
out_mul68(4) <= in_mul68(3) xor in_mul68(1); |
out_mul68(5) <= in_mul68(4) xor in_mul68(2) xor in_mul68(0); |
out_mul68(6) <= in_mul68(7) xor in_mul68(6) xor in_mul68(5) xor in_mul68(4) xor in_mul68(2) xor in_mul68(1) xor in_mul68(0); |
out_mul68(7) <= in_mul68(7) xor in_mul68(6) xor in_mul68(5) xor in_mul68(3) xor in_mul68(2) xor in_mul68(1); |
end mul68_arch; |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
-- |
-- multiplier by e5 |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity mule5 is |
port ( |
in_mule5 : in std_logic_vector(7 downto 0); |
out_mule5 : out std_logic_vector(7 downto 0) |
); |
end mule5; |
|
|
architecture mule5_arch of mule5 is |
begin |
out_mule5(0) <= in_mule5(6) xor in_mule5(4) xor in_mule5(2) xor in_mule5(1) xor in_mule5(0); |
out_mule5(1) <= in_mule5(7) xor in_mule5(5) xor in_mule5(3) xor in_mule5(2) xor in_mule5(1); |
out_mule5(2) <= in_mule5(3) xor in_mule5(1) xor in_mule5(0); |
out_mule5(3) <= in_mule5(6); |
out_mule5(4) <= in_mule5(7); |
out_mule5(5) <= in_mule5(0); |
out_mule5(6) <= in_mule5(6) xor in_mule5(4) xor in_mule5(2) xor in_mule5(0); |
out_mule5(7) <= in_mule5(7) xor in_mule5(5) xor in_mule5(3) xor in_mule5(1) xor in_mule5(0); |
end mule5_arch; |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
-- |
-- multiplier by 02 |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity mul02 is |
port ( |
in_mul02 : in std_logic_vector(7 downto 0); |
out_mul02 : out std_logic_vector(7 downto 0) |
); |
end mul02; |
|
|
architecture mul02_arch of mul02 is |
begin |
out_mul02(0) <= in_mul02(7); |
out_mul02(1) <= in_mul02(0); |
out_mul02(2) <= in_mul02(7) xor in_mul02(1); |
out_mul02(3) <= in_mul02(7) xor in_mul02(2); |
out_mul02(4) <= in_mul02(3); |
out_mul02(5) <= in_mul02(4); |
out_mul02(6) <= in_mul02(7) xor in_mul02(5); |
out_mul02(7) <= in_mul02(6); |
end mul02_arch; |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
-- |
-- multiplier by a1 |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity mula1 is |
port ( |
in_mula1 : in std_logic_vector(7 downto 0); |
out_mula1 : out std_logic_vector(7 downto 0) |
); |
end mula1; |
|
architecture mula1_arch of mula1 is |
begin |
out_mula1(0) <= in_mula1(7) xor in_mula1(6) xor in_mula1(1) xor in_mula1(0); |
out_mula1(1) <= in_mula1(7) xor in_mula1(2) xor in_mula1(1); |
out_mula1(2) <= in_mula1(7) xor in_mula1(6) xor in_mula1(3) xor in_mula1(2) xor in_mula1(1); |
out_mula1(3) <= in_mula1(6) xor in_mula1(4) xor in_mula1(3) xor in_mula1(2) xor in_mula1(1); |
out_mula1(4) <= in_mula1(7) xor in_mula1(5) xor in_mula1(4) xor in_mula1(3) xor in_mula1(2); |
out_mula1(5) <= in_mula1(6) xor in_mula1(5) xor in_mula1(4) xor in_mula1(3) xor in_mula1(0); |
out_mula1(6) <= in_mula1(5) xor in_mula1(4); |
out_mula1(7) <= in_mula1(6) xor in_mula1(5) xor in_mula1(0); |
end mula1_arch; |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
-- |
-- multiplier by fc |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity mulfc is |
port ( |
in_mulfc : in std_logic_vector(7 downto 0); |
out_mulfc : out std_logic_vector(7 downto 0) |
); |
end mulfc; |
|
|
architecture mulfc_arch of mulfc is |
begin |
out_mulfc(0) <= in_mulfc(7) xor in_mulfc(5) xor in_mulfc(2) xor in_mulfc(1); |
out_mulfc(1) <= in_mulfc(6) xor in_mulfc(3) xor in_mulfc(2); |
out_mulfc(2) <= in_mulfc(5) xor in_mulfc(4) xor in_mulfc(3) xor in_mulfc(2) xor in_mulfc(1) xor in_mulfc(0); |
out_mulfc(3) <= in_mulfc(7) xor in_mulfc(6) xor in_mulfc(4) xor in_mulfc(3) xor in_mulfc(0); |
out_mulfc(4) <= in_mulfc(7) xor in_mulfc(5) xor in_mulfc(4) xor in_mulfc(1) xor in_mulfc(0); |
out_mulfc(5) <= in_mulfc(6) xor in_mulfc(5) xor in_mulfc(2) xor in_mulfc(1) xor in_mulfc(0); |
out_mulfc(6) <= in_mulfc(6) xor in_mulfc(5) xor in_mulfc(3) xor in_mulfc(0); |
out_mulfc(7) <= in_mulfc(7) xor in_mulfc(6) xor in_mulfc(4) xor in_mulfc(1) xor in_mulfc(0); |
end mulfc_arch; |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
-- |
-- multiplier by c1 |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity mulc1 is |
port ( |
in_mulc1 : in std_logic_vector(7 downto 0); |
out_mulc1 : out std_logic_vector(7 downto 0) |
); |
end mulc1; |
|
|
architecture mulc1_arch of mulc1 is |
begin |
out_mulc1(0) <= in_mulc1(7) xor in_mulc1(5) xor in_mulc1(4) xor in_mulc1(3) xor in_mulc1(2) xor in_mulc1(1) xor in_mulc1(0); |
out_mulc1(1) <= in_mulc1(6) xor in_mulc1(5) xor in_mulc1(4) xor in_mulc1(3) xor in_mulc1(2) xor in_mulc1(1); |
out_mulc1(2) <= in_mulc1(6) xor in_mulc1(1); |
out_mulc1(3) <= in_mulc1(5) xor in_mulc1(4) xor in_mulc1(3) xor in_mulc1(1); |
out_mulc1(4) <= in_mulc1(6) xor in_mulc1(5) xor in_mulc1(4) xor in_mulc1(2); |
out_mulc1(5) <= in_mulc1(7) xor in_mulc1(6) xor in_mulc1(5) xor in_mulc1(3); |
out_mulc1(6) <= in_mulc1(6) xor in_mulc1(5) xor in_mulc1(3) xor in_mulc1(2) xor in_mulc1(1) xor in_mulc1(0); |
out_mulc1(7) <= in_mulc1(7) xor in_mulc1(6) xor in_mulc1(4) xor in_mulc1(3) xor in_mulc1(2) xor in_mulc1(1) xor in_mulc1(0); |
end mulc1_arch; |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
-- |
-- multiplier by 47 |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity mul47 is |
port ( |
in_mul47 : in std_logic_vector(7 downto 0); |
out_mul47 : out std_logic_vector(7 downto 0) |
); |
end mul47; |
|
architecture mul47_arch of mul47 is |
begin |
out_mul47(0) <= in_mul47(4) xor in_mul47(2) xor in_mul47(0); |
out_mul47(1) <= in_mul47(5) xor in_mul47(3) xor in_mul47(1) xor in_mul47(0); |
out_mul47(2) <= in_mul47(6) xor in_mul47(1) xor in_mul47(0); |
out_mul47(3) <= in_mul47(7) xor in_mul47(4) xor in_mul47(1); |
out_mul47(4) <= in_mul47(5) xor in_mul47(2); |
out_mul47(5) <= in_mul47(6) xor in_mul47(3); |
out_mul47(6) <= in_mul47(7) xor in_mul47(2) xor in_mul47(0); |
out_mul47(7) <= in_mul47(3) xor in_mul47(1); |
end mul47_arch; |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
-- |
-- multiplier by ae |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity mulae is |
port ( |
in_mulae : in std_logic_vector(7 downto 0); |
out_mulae : out std_logic_vector(7 downto 0) |
); |
end mulae; |
|
architecture mulae_arch of mulae is |
begin |
out_mulae(0) <= in_mulae(7) xor in_mulae(5) xor in_mulae(1); |
out_mulae(1) <= in_mulae(6) xor in_mulae(2) xor in_mulae(0); |
out_mulae(2) <= in_mulae(5) xor in_mulae(3) xor in_mulae(0); |
out_mulae(3) <= in_mulae(7) xor in_mulae(6) xor in_mulae(5) xor in_mulae(4) xor in_mulae(0); |
out_mulae(4) <= in_mulae(7) xor in_mulae(6) xor in_mulae(5) xor in_mulae(1); |
out_mulae(5) <= in_mulae(7) xor in_mulae(6) xor in_mulae(2) xor in_mulae(0); |
out_mulae(6) <= in_mulae(5) xor in_mulae(3); |
out_mulae(7) <= in_mulae(6) xor in_mulae(4) xor in_mulae(0); |
end mulae_arch; |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
-- |
-- multiplier by 3d |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity mul3d is |
port ( |
in_mul3d : in std_logic_vector(7 downto 0); |
out_mul3d : out std_logic_vector(7 downto 0) |
); |
end mul3d; |
|
architecture mul3d_arch of mul3d is |
begin |
out_mul3d(0) <= in_mul3d(4) xor in_mul3d(3) xor in_mul3d(0); |
out_mul3d(1) <= in_mul3d(5) xor in_mul3d(4) xor in_mul3d(1); |
out_mul3d(2) <= in_mul3d(6) xor in_mul3d(5) xor in_mul3d(4) xor in_mul3d(3) xor in_mul3d(2) xor in_mul3d(0); |
out_mul3d(3) <= in_mul3d(7) xor in_mul3d(6) xor in_mul3d(5) xor in_mul3d(1) xor in_mul3d(0); |
out_mul3d(4) <= in_mul3d(7) xor in_mul3d(6) xor in_mul3d(2) xor in_mul3d(1) xor in_mul3d(0); |
out_mul3d(5) <= in_mul3d(7) xor in_mul3d(3) xor in_mul3d(2) xor in_mul3d(1) xor in_mul3d(0); |
out_mul3d(6) <= in_mul3d(2) xor in_mul3d(1); |
out_mul3d(7) <= in_mul3d(3) xor in_mul3d(2); |
end mul3d_arch; |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
-- |
-- multiplier by 19 |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity mul19 is |
port ( |
in_mul19 : in std_logic_vector(7 downto 0); |
out_mul19 : out std_logic_vector(7 downto 0) |
); |
end mul19; |
|
architecture mul19_arch of mul19 is |
begin |
out_mul19(0) <= in_mul19(7) xor in_mul19(6) xor in_mul19(5) xor in_mul19(4) xor in_mul19(0); |
out_mul19(1) <= in_mul19(7) xor in_mul19(6) xor in_mul19(5) xor in_mul19(1); |
out_mul19(2) <= in_mul19(5) xor in_mul19(4) xor in_mul19(2); |
out_mul19(3) <= in_mul19(7) xor in_mul19(4) xor in_mul19(3) xor in_mul19(0); |
out_mul19(4) <= in_mul19(5) xor in_mul19(4) xor in_mul19(1) xor in_mul19(0); |
out_mul19(5) <= in_mul19(6) xor in_mul19(5) xor in_mul19(2) xor in_mul19(1); |
out_mul19(6) <= in_mul19(5) xor in_mul19(4) xor in_mul19(3) xor in_mul19(2); |
out_mul19(7) <= in_mul19(6) xor in_mul19(5) xor in_mul19(4) xor in_mul19(3); |
end mul19_arch; |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
-- |
-- multiplier by 03 |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity mul03 is |
port ( |
in_mul03 : in std_logic_vector(7 downto 0); |
out_mul03 : out std_logic_vector(7 downto 0) |
); |
end mul03; |
|
architecture mul03_arch of mul03 is |
begin |
out_mul03(0) <= in_mul03(7) xor in_mul03(0); |
out_mul03(1) <= in_mul03(1) xor in_mul03(0); |
out_mul03(2) <= in_mul03(7) xor in_mul03(2) xor in_mul03(1); |
out_mul03(3) <= in_mul03(7) xor in_mul03(3) xor in_mul03(2); |
out_mul03(4) <= in_mul03(4) xor in_mul03(3); |
out_mul03(5) <= in_mul03(5) xor in_mul03(4); |
out_mul03(6) <= in_mul03(7) xor in_mul03(6) xor in_mul03(5); |
out_mul03(7) <= in_mul03(7) xor in_mul03(6); |
end mul03_arch; |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
-- |
-- twofish data input is the component |
-- that transforms the data input to the |
-- first round to the wanted form as is |
-- described in the twofish prototype |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity twofish_data_input is |
port ( |
in_tdi : in std_logic_vector(127 downto 0); |
out_tdi : out std_logic_vector(127 downto 0) |
); |
end twofish_data_input; |
|
architecture twofish_data_input_arch of twofish_data_input is |
|
-- we declare internal signals |
signal byte0, byte1, byte2, byte3, |
byte4, byte5, byte6, |
byte7, byte8, byte9, |
byte10, byte11, byte12, |
byte13, byte14, byte15 : std_logic_vector(7 downto 0); |
signal P0, P1, P2, P3 : std_logic_vector(31 downto 0); |
|
begin |
|
-- we assign the input signal to the respective |
-- bytes as is described in the prototype |
byte15 <= in_tdi(7 downto 0); |
byte14 <= in_tdi(15 downto 8); |
byte13 <= in_tdi(23 downto 16); |
byte12 <= in_tdi(31 downto 24); |
byte11 <= in_tdi(39 downto 32); |
byte10 <= in_tdi(47 downto 40); |
byte9 <= in_tdi(55 downto 48); |
byte8 <= in_tdi(63 downto 56); |
byte7 <= in_tdi(71 downto 64); |
byte6 <= in_tdi(79 downto 72); |
byte5 <= in_tdi(87 downto 80); |
byte4 <= in_tdi(95 downto 88); |
byte3 <= in_tdi(103 downto 96); |
byte2 <= in_tdi(111 downto 104); |
byte1 <= in_tdi(119 downto 112); |
byte0 <= in_tdi(127 downto 120); |
|
-- we rearrange the bytes and send them to exit |
P0 <= byte3 & byte2 & byte1 & byte0; |
P1 <= byte7 & byte6 & byte5 & byte4; |
P2 <= byte11 & byte10 & byte9 & byte8; |
P3 <= byte15 & byte14 & byte13 & byte12; |
|
out_tdi <= P0 & P1 & P2 & P3; |
|
end twofish_data_input_arch; |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
|
-- |
-- twofish data output is the component |
-- that transforms the data output from the |
-- 16th round to the wanted form as is |
-- described in the twofish prototype |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity twofish_data_output is |
port ( |
in_tdo : in std_logic_vector(127 downto 0); |
out_tdo : out std_logic_vector(127 downto 0) |
); |
end twofish_data_output; |
|
architecture twofish_data_output_arch of twofish_data_output is |
|
-- we declare internal signals |
signal byte0, byte1, byte2, byte3, |
byte4, byte5, byte6, |
byte7, byte8, byte9, |
byte10, byte11, byte12, |
byte13, byte14, byte15 : std_logic_vector(7 downto 0); |
signal C0, C1, C2, C3 : std_logic_vector(31 downto 0); |
|
begin |
|
-- we assign the input signal to the respective |
-- bytes as is described in the prototype |
byte15 <= in_tdo(7 downto 0); |
byte14 <= in_tdo(15 downto 8); |
byte13 <= in_tdo(23 downto 16); |
byte12 <= in_tdo(31 downto 24); |
byte11 <= in_tdo(39 downto 32); |
byte10 <= in_tdo(47 downto 40); |
byte9 <= in_tdo(55 downto 48); |
byte8 <= in_tdo(63 downto 56); |
byte7 <= in_tdo(71 downto 64); |
byte6 <= in_tdo(79 downto 72); |
byte5 <= in_tdo(87 downto 80); |
byte4 <= in_tdo(95 downto 88); |
byte3 <= in_tdo(103 downto 96); |
byte2 <= in_tdo(111 downto 104); |
byte1 <= in_tdo(119 downto 112); |
byte0 <= in_tdo(127 downto 120); |
|
-- we rearrange the bytes and send them to exit |
C0 <= byte3 & byte2 & byte1 & byte0; |
C1 <= byte7 & byte6 & byte5 & byte4; |
C2 <= byte11 & byte10 & byte9 & byte8; |
C3 <= byte15 & byte14 & byte13 & byte12; |
|
out_tdo <= C0 & C1 & C2 & C3; |
|
end twofish_data_output_arch; |
|
-- =======-======================================= -- |
-- =============================================== -- |
-- -- |
-- second part: 128 key input dependent components -- |
-- -- |
-- =============================================== -- |
-- =============================================== -- |
|
|
-- |
-- reed solomon for 128bits key |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity reed_solomon128 is |
port ( |
in_rs128 : in std_logic_vector(127 downto 0); |
out_Sfirst_rs128, |
out_Ssecond_rs128 : out std_logic_vector(31 downto 0) |
); |
end reed_solomon128; |
|
architecture rs_128_arch of reed_solomon128 is |
|
-- declaring all components necessary for reed solomon |
-- 01 |
component mul01 |
port ( |
in_mul01 : in std_logic_vector(7 downto 0); |
out_mul01 : out std_logic_vector(7 downto 0) |
); |
end component; |
|
-- a4 |
component mula4 |
port ( |
in_mula4 : in std_logic_vector(7 downto 0); |
out_mula4 : out std_logic_vector(7 downto 0) |
); |
end component; |
|
-- 55 |
component mul55 |
port ( |
in_mul55 : in std_logic_vector(7 downto 0); |
out_mul55 : out std_logic_vector(7 downto 0) |
); |
end component; |
|
-- 87 |
component mul87 |
port ( |
in_mul87 : in std_logic_vector(7 downto 0); |
out_mul87 : out std_logic_vector(7 downto 0) |
); |
end component; |
|
-- 5a |
component mul5a |
port ( |
in_mul5a : in std_logic_vector(7 downto 0); |
out_mul5a : out std_logic_vector(7 downto 0) |
); |
end component; |
|
-- 58 |
component mul58 |
port ( |
in_mul58 : in std_logic_vector(7 downto 0); |
out_mul58 : out std_logic_vector(7 downto 0) |
); |
end component; |
|
|
-- db |
component muldb |
port ( |
in_muldb : in std_logic_vector(7 downto 0); |
out_muldb : out std_logic_vector(7 downto 0) |
); |
end component; |
|
|
-- 9e |
component mul9e |
port ( |
in_mul9e : in std_logic_vector(7 downto 0); |
out_mul9e : out std_logic_vector(7 downto 0) |
); |
end component; |
|
|
-- 56 |
component mul56 |
port ( |
in_mul56 : in std_logic_vector(7 downto 0); |
out_mul56 : out std_logic_vector(7 downto 0) |
); |
end component; |
|
|
-- 82 |
component mul82 |
port ( |
in_mul82 : in std_logic_vector(7 downto 0); |
out_mul82 : out std_logic_vector(7 downto 0) |
); |
end component; |
|
|
-- f3 |
component mulf3 |
port ( |
in_mulf3 : in std_logic_vector(7 downto 0); |
out_mulf3 : out std_logic_vector(7 downto 0) |
); |
end component; |
|
|
-- 1e |
component mul1e |
port ( |
in_mul1e : in std_logic_vector(7 downto 0); |
out_mul1e : out std_logic_vector(7 downto 0) |
); |
end component; |
|
|
-- c6 |
component mulc6 |
port ( |
in_mulc6 : in std_logic_vector(7 downto 0); |
out_mulc6 : out std_logic_vector(7 downto 0) |
); |
end component; |
|
|
-- 68 |
component mul68 |
port ( |
in_mul68 : in std_logic_vector(7 downto 0); |
out_mul68 : out std_logic_vector(7 downto 0) |
); |
end component; |
|
|
-- e5 |
component mule5 |
port ( |
in_mule5 : in std_logic_vector(7 downto 0); |
out_mule5 : out std_logic_vector(7 downto 0) |
); |
end component; |
|
|
-- 02 |
component mul02 |
port ( |
in_mul02 : in std_logic_vector(7 downto 0); |
out_mul02 : out std_logic_vector(7 downto 0) |
); |
end component; |
|
|
-- a1 |
component mula1 |
port ( |
in_mula1 : in std_logic_vector(7 downto 0); |
out_mula1 : out std_logic_vector(7 downto 0) |
); |
end component; |
|
|
-- fc |
component mulfc |
port ( |
in_mulfc : in std_logic_vector(7 downto 0); |
out_mulfc : out std_logic_vector(7 downto 0) |
); |
end component; |
|
|
-- c1 |
component mulc1 |
port ( |
in_mulc1 : in std_logic_vector(7 downto 0); |
out_mulc1 : out std_logic_vector(7 downto 0) |
); |
end component; |
|
|
-- 47 |
component mul47 |
port ( |
in_mul47 : in std_logic_vector(7 downto 0); |
out_mul47 : out std_logic_vector(7 downto 0) |
); |
end component; |
|
|
|
-- ae |
component mulae |
port ( |
in_mulae : in std_logic_vector(7 downto 0); |
out_mulae : out std_logic_vector(7 downto 0) |
); |
end component; |
|
|
|
-- 3d |
component mul3d |
port ( |
in_mul3d : in std_logic_vector(7 downto 0); |
out_mul3d : out std_logic_vector(7 downto 0) |
); |
end component; |
|
|
|
-- 19 |
component mul19 |
port ( |
in_mul19 : in std_logic_vector(7 downto 0); |
out_mul19 : out std_logic_vector(7 downto 0) |
); |
end component; |
|
|
-- 03 |
component mul03 |
port ( |
in_mul03 : in std_logic_vector(7 downto 0); |
out_mul03 : out std_logic_vector(7 downto 0) |
); |
end component; |
|
|
-- declaring internal signals |
signal m0,m1,m2,m3,m4,m5,m6,m7,m8,m9,m10,m11,m12,m13,m14,m15 : std_logic_vector(7 downto 0); |
signal s00,s01,s02,s03,s10,s11,s12,s13 : std_logic_vector(7 downto 0); |
signal m0_01,m1_a4,m2_55,m3_87,m4_5a,m5_58,m6_db,m7_9e, |
m0_a4,m1_56,m2_82,m3_f3,m4_1e,m5_c6,m6_68,m7_e5, |
m0_02,m1_a1,m2_fc,m3_c1,m4_47,m5_ae,m6_3d,m7_19, |
m0_a4_1,m1_55,m2_87,m3_5a,m4_58,m5_db,m6_9e,m7_03 : std_logic_vector(7 downto 0); |
signal m8_01,m9_a4,m10_55,m11_87,m12_5a,m13_58,m14_db,m15_9e, |
m8_a4,m9_56,m10_82,m11_f3,m12_1e,m13_c6,m14_68,m15_e5, |
m8_02,m9_a1,m10_fc,m11_c1,m12_47,m13_ae,m14_3d,m15_19, |
m8_a4_1,m9_55,m10_87,m11_5a,m12_58,m13_db,m14_9e,m15_03 : std_logic_vector(7 downto 0); |
|
-- begin architecture description |
begin |
|
-- first, we separate the input to the respective m |
-- for s1,j j=0..3 |
m0 <= in_rs128(7 downto 0); |
m1 <= in_rs128(15 downto 8); |
m2 <= in_rs128(23 downto 16); |
m3 <= in_rs128(31 downto 24); |
m4 <= in_rs128(39 downto 32); |
m5 <= in_rs128(47 downto 40); |
m6 <= in_rs128(55 downto 48); |
m7 <= in_rs128(63 downto 56); |
|
-- for s0,j j=0..3 |
m8 <= in_rs128(71 downto 64); |
m9 <= in_rs128(79 downto 72); |
m10 <= in_rs128(87 downto 80); |
m11 <= in_rs128(95 downto 88); |
m12 <= in_rs128(103 downto 96); |
m13 <= in_rs128(111 downto 104); |
m14 <= in_rs128(119 downto 112); |
m15 <= in_rs128(127 downto 120); |
|
|
-- after separating signals, we drive them to multipliers |
-- the first line of m0..7 forms s00 |
m0_with_01: mul01 |
port map ( |
in_mul01 => m0, |
out_mul01 => m0_01 |
); |
|
m1_with_a4: mula4 |
port map ( |
in_mula4 => m1, |
out_mula4 => m1_a4 |
); |
|
m2_with_55: mul55 |
port map ( |
in_mul55 => m2, |
out_mul55 => m2_55 |
); |
|
m3_with_87: mul87 |
port map ( |
in_mul87 => m3, |
out_mul87 => m3_87 |
); |
|
m4_with_5a: mul5a |
port map ( |
in_mul5a => m4, |
out_mul5a => m4_5a |
); |
|
m5_with_58: mul58 |
port map ( |
in_mul58 => m5, |
out_mul58 => m5_58 |
); |
|
m6_with_db: muldb |
port map ( |
in_muldb => m6, |
out_muldb => m6_db |
); |
|
m7_with_9e: mul9e |
port map ( |
in_mul9e => m7, |
out_mul9e => m7_9e |
); |
|
-- the second row creates s01 |
m0_with_a4: mula4 |
port map ( |
in_mula4 => m0, |
out_mula4 => m0_a4 |
); |
|
m1_with_56: mul56 |
port map ( |
in_mul56 => m1, |
out_mul56 => m1_56 |
); |
|
m2_with_82: mul82 |
port map ( |
in_mul82 => m2, |
out_mul82 => m2_82 |
); |
|
m3_with_f3: mulf3 |
port map ( |
in_mulf3 => m3, |
out_mulf3 => m3_f3 |
); |
|
m4_with_1e: mul1e |
port map ( |
in_mul1e => m4, |
out_mul1e => m4_1e |
); |
|
m5_with_c6: mulc6 |
port map ( |
in_mulc6 => m5, |
out_mulc6 => m5_c6 |
); |
|
m6_with_68: mul68 |
port map ( |
in_mul68 => m6, |
out_mul68 => m6_68 |
); |
|
m7_with_e5: mule5 |
port map ( |
in_mule5 => m7, |
out_mule5 => m7_e5 |
); |
|
-- the third row creates s02 |
m0_with_02: mul02 |
port map ( |
in_mul02 => m0, |
out_mul02 => m0_02 |
); |
|
m1_with_a1: mula1 |
port map ( |
in_mula1 => m1, |
out_mula1 => m1_a1 |
); |
|
m2_with_fc: mulfc |
port map ( |
in_mulfc => m2, |
out_mulfc => m2_fc |
); |
|
m3_with_c1: mulc1 |
port map ( |
in_mulc1 => m3, |
out_mulc1 => m3_c1 |
); |
|
m4_with_47: mul47 |
port map ( |
in_mul47 => m4, |
out_mul47 => m4_47 |
); |
|
m5_with_ae: mulae |
port map ( |
in_mulae => m5, |
out_mulae => m5_ae |
); |
|
m6_with_3d: mul3d |
port map ( |
in_mul3d => m6, |
out_mul3d => m6_3d |
); |
|
m7_with_19: mul19 |
port map ( |
in_mul19 => m7, |
out_mul19 => m7_19 |
); |
|
-- the fourth row creates s03 |
m0_with_a4_1: mula4 |
port map ( |
in_mula4 => m0, |
out_mula4 => m0_a4_1 |
); |
|
m1_with_55: mul55 |
port map ( |
in_mul55 => m1, |
out_mul55 => m1_55 |
); |
|
m2_with_87: mul87 |
port map ( |
in_mul87 => m2, |
out_mul87 => m2_87 |
); |
|
m3_with_5a: mul5a |
port map ( |
in_mul5a => m3, |
out_mul5a => m3_5a |
); |
|
m4_with_58: mul58 |
port map ( |
in_mul58 => m4, |
out_mul58 => m4_58 |
); |
|
m5_with_db: muldb |
port map ( |
in_muldb => m5, |
out_muldb => m5_db |
); |
|
m6_with_9e: mul9e |
port map ( |
in_mul9e => m6, |
out_mul9e => m6_9e |
); |
|
m7_with_03: mul03 |
port map ( |
in_mul03 => m7, |
out_mul03 => m7_03 |
); |
|
|
-- we create the s1,j j=0..3 |
-- the first row of m0..7 creates the s10 |
m8_with_01: mul01 |
port map ( |
in_mul01 => m8, |
out_mul01 => m8_01 |
); |
|
m9_with_a4: mula4 |
port map ( |
in_mula4 => m9, |
out_mula4 => m9_a4 |
); |
|
m10_with_55: mul55 |
port map ( |
in_mul55 => m10, |
out_mul55 => m10_55 |
); |
|
m11_with_87: mul87 |
port map ( |
in_mul87 => m11, |
out_mul87 => m11_87 |
); |
|
m12_with_5a: mul5a |
port map ( |
in_mul5a => m12, |
out_mul5a => m12_5a |
); |
|
m13_with_58: mul58 |
port map ( |
in_mul58 => m13, |
out_mul58 => m13_58 |
); |
|
m14_with_db: muldb |
port map ( |
in_muldb => m14, |
out_muldb => m14_db |
); |
|
m15_with_9e: mul9e |
port map ( |
in_mul9e => m15, |
out_mul9e => m15_9e |
); |
|
-- the second row creates s11 |
m8_with_a4: mula4 |
port map ( |
in_mula4 => m8, |
out_mula4 => m8_a4 |
); |
|
m9_with_56: mul56 |
port map ( |
in_mul56 => m9, |
out_mul56 => m9_56 |
); |
|
m10_with_82: mul82 |
port map ( |
in_mul82 => m10, |
out_mul82 => m10_82 |
); |
|
m11_with_f3: mulf3 |
port map ( |
in_mulf3 => m11, |
out_mulf3 => m11_f3 |
); |
|
m12_with_1e: mul1e |
port map ( |
in_mul1e => m12, |
out_mul1e => m12_1e |
); |
|
m13_with_c6: mulc6 |
port map ( |
in_mulc6 => m13, |
out_mulc6 => m13_c6 |
); |
|
m14_with_68: mul68 |
port map ( |
in_mul68 => m14, |
out_mul68 => m14_68 |
); |
|
m15_with_e5: mule5 |
port map ( |
in_mule5 => m15, |
out_mule5 => m15_e5 |
); |
|
-- the third row creates s12 |
m8_with_02: mul02 |
port map ( |
in_mul02 => m8, |
out_mul02 => m8_02 |
); |
|
m9_with_a1: mula1 |
port map ( |
in_mula1 => m9, |
out_mula1 => m9_a1 |
); |
|
m10_with_fc: mulfc |
port map ( |
in_mulfc => m10, |
out_mulfc => m10_fc |
); |
|
m11_with_c1: mulc1 |
port map ( |
in_mulc1 => m11, |
out_mulc1 => m11_c1 |
); |
|
m12_with_47: mul47 |
port map ( |
in_mul47 => m12, |
out_mul47 => m12_47 |
); |
|
m13_with_ae: mulae |
port map ( |
in_mulae => m13, |
out_mulae => m13_ae |
); |
|
m14_with_3d: mul3d |
port map ( |
in_mul3d => m14, |
out_mul3d => m14_3d |
); |
|
m15_with_19: mul19 |
port map ( |
in_mul19 => m15, |
out_mul19 => m15_19 |
); |
|
-- the fourth row creates s13 |
m8_with_a4_1: mula4 |
port map ( |
in_mula4 => m8, |
out_mula4 => m8_a4_1 |
); |
|
m9_with_55: mul55 |
port map ( |
in_mul55 => m9, |
out_mul55 => m9_55 |
); |
|
m10_with_87: mul87 |
port map ( |
in_mul87 => m10, |
out_mul87 => m10_87 |
); |
|
m11_with_5a: mul5a |
port map ( |
in_mul5a => m11, |
out_mul5a => m11_5a |
); |
|
m12_with_58: mul58 |
port map ( |
in_mul58 => m12, |
out_mul58 => m12_58 |
); |
|
m13_with_db: muldb |
port map ( |
in_muldb => m13, |
out_muldb => m13_db |
); |
|
m14_with_9e: mul9e |
port map ( |
in_mul9e => m14, |
out_mul9e => m14_9e |
); |
|
m15_with_03: mul03 |
port map ( |
in_mul03 => m15, |
out_mul03 => m15_03 |
); |
|
|
-- after getting the results from multipliers |
-- we combine them in order to get the additions |
s00 <= m0_01 XOR m1_a4 XOR m2_55 XOR m3_87 XOR m4_5a XOR m5_58 XOR m6_db XOR m7_9e; |
s01 <= m0_a4 XOR m1_56 XOR m2_82 XOR m3_f3 XOR m4_1e XOR m5_c6 XOR m6_68 XOR m7_e5; |
s02 <= m0_02 XOR m1_a1 XOR m2_fc XOR m3_c1 XOR m4_47 XOR m5_ae XOR m6_3d XOR m7_19; |
s03 <= m0_a4_1 XOR m1_55 XOR m2_87 XOR m3_5a XOR m4_58 XOR m5_db XOR m6_9e XOR m7_03; |
|
-- after creating s0,j j=0...3 we form the S0 |
-- little endian |
out_Sfirst_rs128 <= s03 & s02 & s01 & s00; |
|
s10 <= m8_01 XOR m9_a4 XOR m10_55 XOR m11_87 XOR m12_5a XOR m13_58 XOR m14_db XOR m15_9e; |
s11 <= m8_a4 XOR m9_56 XOR m10_82 XOR m11_f3 XOR m12_1e XOR m13_c6 XOR m14_68 XOR m15_e5; |
s12 <= m8_02 XOR m9_a1 XOR m10_fc XOR m11_c1 XOR m12_47 XOR m13_ae XOR m14_3d XOR m15_19; |
s13 <= m8_a4_1 XOR m9_55 XOR m10_87 XOR m11_5a XOR m12_58 XOR m13_db XOR m14_9e XOR m15_03; |
|
-- after creating s1,j j=0...3 we form the S1 |
-- little endian |
out_Ssecond_rs128 <= s13 & s12 & s11 & s10; |
|
end rs_128_arch; |
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
-- |
-- h function for 128 bits key |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity h_128 is |
port ( |
in_h128 : in std_logic_vector(7 downto 0); |
Mfirst_h128, |
Msecond_h128 : in std_logic_vector(31 downto 0); |
out_h128 : out std_logic_vector(31 downto 0) |
); |
end h_128; |
|
architecture h128_arch of h_128 is |
|
-- we declare internal signals |
signal from_first_row, |
to_second_row, |
from_second_row, |
to_third_row, |
to_mds : std_logic_vector(31 downto 0); |
|
-- we declare all components needed |
component q0 |
port ( |
in_q0 : in std_logic_vector(7 downto 0); |
out_q0 : out std_logic_vector(7 downto 0) |
); |
end component; |
|
component q1 |
port ( |
in_q1 : in std_logic_vector(7 downto 0); |
out_q1 : out std_logic_vector(7 downto 0) |
); |
end component; |
|
component mds |
port ( |
y0, |
y1, |
y2, |
y3 : in std_logic_vector(7 downto 0); |
z0, |
z1, |
z2, |
z3 : out std_logic_vector(7 downto 0) |
); |
end component; |
|
-- begin architecture description |
begin |
|
-- first row of q |
first_q0_1: q0 |
port map ( |
in_q0 => in_h128, |
out_q0 => from_first_row(7 downto 0) |
); |
first_q1_1: q1 |
port map ( |
in_q1 => in_h128, |
out_q1 => from_first_row(15 downto 8) |
); |
first_q0_2: q0 |
port map ( |
in_q0 => in_h128, |
out_q0 => from_first_row(23 downto 16) |
); |
first_q1_2: q1 |
port map ( |
in_q1 => in_h128, |
out_q1 => from_first_row(31 downto 24) |
); |
|
-- we perform the XOR of the results of the first row |
-- with first M of h (Mfist_h128) |
to_second_row <= from_first_row XOR Mfirst_h128; |
|
-- second row of q |
second_q0_1: q0 |
port map ( |
in_q0 => to_second_row(7 downto 0), |
out_q0 => from_second_row(7 downto 0) |
); |
second_q0_2: q0 |
port map ( |
in_q0 => to_second_row(15 downto 8), |
out_q0 => from_second_row(15 downto 8) |
); |
second_q1_1: q1 |
port map ( |
in_q1 => to_second_row(23 downto 16), |
out_q1 => from_second_row(23 downto 16) |
); |
second_q1_2: q1 |
port map ( |
in_q1 => to_second_row(31 downto 24), |
out_q1 => from_second_row(31 downto 24) |
); |
|
-- we perform the second XOR |
to_third_row <= from_second_row XOR Msecond_h128; |
|
-- the third row of q |
third_q1_1: q1 |
port map ( |
in_q1 => to_third_row(7 downto 0), |
out_q1 => to_mds(7 downto 0) |
); |
third_q0_1: q0 |
port map ( |
in_q0 => to_third_row(15 downto 8), |
out_q0 => to_mds(15 downto 8) |
); |
third_q1_2: q1 |
port map ( |
in_q1 => to_third_row(23 downto 16), |
out_q1 => to_mds(23 downto 16) |
); |
third_q0_2: q0 |
port map ( |
in_q0 => to_third_row(31 downto 24), |
out_q0 => to_mds(31 downto 24) |
); |
|
-- mds table |
mds_table: mds |
port map ( |
y0 => to_mds(7 downto 0), |
y1 => to_mds(15 downto 8), |
y2 => to_mds(23 downto 16), |
y3 => to_mds(31 downto 24), |
z0 => out_h128(7 downto 0), |
z1 => out_h128(15 downto 8), |
z2 => out_h128(23 downto 16), |
z3 => out_h128(31 downto 24) |
); |
|
end h128_arch; |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
|
-- |
-- g function for 128 bits key |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity g_128 is |
port ( |
in_g128, |
in_S0_g128, |
in_S1_g128 : in std_logic_vector(31 downto 0); |
out_g128 : out std_logic_vector(31 downto 0) |
); |
end g_128; |
|
architecture g128_arch of g_128 is |
|
-- we declare the internal signals |
signal from_first_row, |
to_second_row, |
from_second_row, |
to_third_row, |
to_mds : std_logic_vector(31 downto 0); |
|
component q0 |
port ( |
in_q0 : in std_logic_vector(7 downto 0); |
out_q0 : out std_logic_vector(7 downto 0) |
); |
end component; |
|
component q1 |
port ( |
in_q1 : in std_logic_vector(7 downto 0); |
out_q1 : out std_logic_vector(7 downto 0) |
); |
end component; |
|
component mds |
port ( |
y0, |
y1, |
y2, |
y3 : in std_logic_vector(7 downto 0); |
z0, |
z1, |
z2, |
z3 : out std_logic_vector(7 downto 0) |
); |
end component; |
|
-- begin architecture description |
begin |
|
-- first row of q |
first_q0_1: q0 |
port map ( |
in_q0 => in_g128(7 downto 0), |
out_q0 => from_first_row(7 downto 0) |
); |
first_q1_1: q1 |
port map ( |
in_q1 => in_g128(15 downto 8), |
out_q1 => from_first_row(15 downto 8) |
); |
first_q0_2: q0 |
port map ( |
in_q0 => in_g128(23 downto 16), |
out_q0 => from_first_row(23 downto 16) |
); |
first_q1_2: q1 |
port map ( |
in_q1 => in_g128(31 downto 24), |
out_q1 => from_first_row(31 downto 24) |
); |
|
-- we XOR the result of the first row |
-- with the S0 |
to_second_row <= from_first_row XOR in_S0_g128; |
|
-- second row of q |
second_q0_1: q0 |
port map ( |
in_q0 => to_second_row(7 downto 0), |
out_q0 => from_second_row(7 downto 0) |
); |
second_q0_2: q0 |
port map ( |
in_q0 => to_second_row(15 downto 8), |
out_q0 => from_second_row(15 downto 8) |
); |
second_q1_1: q1 |
port map ( |
in_q1 => to_second_row(23 downto 16), |
out_q1 => from_second_row(23 downto 16) |
); |
second_q1_2: q1 |
port map ( |
in_q1 => to_second_row(31 downto 24), |
out_q1 => from_second_row(31 downto 24) |
); |
|
-- we perform the XOR |
to_third_row <= from_second_row XOR in_S1_g128; |
|
-- third row of q |
third_q1_1: q1 |
port map ( |
in_q1 => to_third_row(7 downto 0), |
out_q1 => to_mds(7 downto 0) |
); |
third_q0_1: q0 |
port map ( |
in_q0 => to_third_row(15 downto 8), |
out_q0 => to_mds(15 downto 8) |
); |
third_q1_2: q1 |
port map ( |
in_q1 => to_third_row(23 downto 16), |
out_q1 => to_mds(23 downto 16) |
); |
third_q0_2: q0 |
port map ( |
in_q0 => to_third_row(31 downto 24), |
out_q0 => to_mds(31 downto 24) |
); |
|
-- mds table |
mds_table: mds |
port map ( |
y0 => to_mds(7 downto 0), |
y1 => to_mds(15 downto 8), |
y2 => to_mds(23 downto 16), |
y3 => to_mds(31 downto 24), |
z0 => out_g128(7 downto 0), |
z1 => out_g128(15 downto 8), |
z2 => out_g128(23 downto 16), |
z3 => out_g128(31 downto 24) |
); |
|
end g128_arch; |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
|
-- |
-- f function with 128 bits key |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity f_128 is |
port ( |
up_in_f128, |
low_in_f128, |
S0_in_f128, |
S1_in_f128, |
up_key_f128, |
low_key_f128 : in std_logic_vector(31 downto 0); |
up_out_f128, |
low_out_f128 : out std_logic_vector(31 downto 0) |
); |
end f_128; |
|
architecture f128_arch of f_128 is |
|
-- we declare the internal signals |
signal from_shift_8, |
to_up_pht, |
to_low_pht, |
to_up_key, |
to_low_key, |
intermediate_carry1, |
intermediate_carry2 : std_logic_vector(31 downto 0); |
signal zero : std_logic; |
|
|
component g_128 |
port ( |
in_g128, |
in_S0_g128, |
in_S1_g128 : in std_logic_vector(31 downto 0); |
out_g128 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component pht |
port ( |
up_in_pht, |
down_in_pht : in std_logic_vector(31 downto 0); |
up_out_pht, |
down_out_pht : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component adder |
port ( |
in1_adder, |
in2_adder, |
in_carry_adder : in std_logic; |
out_adder, |
out_carry_adder : out std_logic |
); |
end component; |
|
-- begin architecture description |
begin |
|
-- we initialize zero |
zero <= '0'; |
|
-- upper g_128 |
upper_g128: g_128 |
port map ( |
in_g128 => up_in_f128, |
in_S0_g128 => S0_in_f128, |
in_S1_g128 => S1_in_f128, |
out_g128 => to_up_pht |
); |
|
-- left rotation by 8 |
from_shift_8(31 downto 8) <= low_in_f128(23 downto 0); |
from_shift_8(7 downto 0) <= low_in_f128(31 downto 24); |
|
-- lower g128 |
lower_g128: g_128 |
port map ( |
in_g128 => from_shift_8, |
in_S0_g128 => S0_in_f128, |
in_S1_g128 => S1_in_f128, |
out_g128 => to_low_pht |
); |
|
-- pht |
pht_transform: pht |
port map ( |
up_in_pht => to_up_pht, |
down_in_pht => to_low_pht, |
up_out_pht => to_up_key, |
down_out_pht => to_low_key |
); |
|
-- upper adder of 32 bits |
up_adder: for i in 0 to 31 generate |
first: if (i=0) generate |
the_adder: adder |
port map ( |
in1_adder => to_up_key(0), |
in2_adder => up_key_f128(0), |
in_carry_adder => zero, |
out_adder => up_out_f128(0), |
out_carry_adder => intermediate_carry1(0) |
); |
end generate first; |
the_rest: if (i>0) generate |
the_adders: adder |
port map ( |
in1_adder => to_up_key(i), |
in2_adder => up_key_f128(i), |
in_carry_adder => intermediate_carry1(i-1), |
out_adder => up_out_f128(i), |
out_carry_adder => intermediate_carry1(i) |
); |
end generate the_rest; |
end generate up_adder; |
|
-- lower adder of 32 bits |
low_adder: for i in 0 to 31 generate |
first1: if (i=0) generate |
the_adder1:adder |
port map ( |
in1_adder => to_low_key(0), |
in2_adder => low_key_f128(0), |
in_carry_adder => zero, |
out_adder => low_out_f128(0), |
out_carry_adder => intermediate_carry2(0) |
); |
end generate first1; |
the_rest1: if (i>0) generate |
the_adders1: adder |
port map ( |
in1_adder => to_low_key(i), |
in2_adder => low_key_f128(i), |
in_carry_adder => intermediate_carry2(i-1), |
out_adder => low_out_f128(i), |
out_carry_adder => intermediate_carry2(i) |
); |
end generate the_rest1; |
end generate low_adder; |
|
end f128_arch; |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
-- |
-- twofish key scheduler for 128 bits key input |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity twofish_keysched128 is |
port ( |
odd_in_tk128, |
even_in_tk128 : in std_logic_vector(7 downto 0); |
in_key_tk128 : in std_logic_vector(127 downto 0); |
out_key_up_tk128, |
out_key_down_tk128 : out std_logic_vector(31 downto 0) |
); |
end twofish_keysched128; |
|
architecture twofish_keysched128_arch of twofish_keysched128 is |
|
-- we declare internal signals |
signal to_up_pht, |
to_shift_8, |
from_shift_8, |
to_shift_9, |
M0, M1, M2, M3 : std_logic_vector(31 downto 0); |
|
signal byte0, byte1, byte2, byte3, |
byte4, byte5, byte6, byte7, |
byte8, byte9, byte10, byte11, |
byte12, byte13, byte14, byte15 : std_logic_vector(7 downto 0); |
|
-- we declare the components to be used |
component pht |
port ( |
up_in_pht, |
down_in_pht : in std_logic_vector(31 downto 0); |
up_out_pht, |
down_out_pht : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component h_128 |
port ( |
in_h128 : in std_logic_vector(7 downto 0); |
Mfirst_h128, |
Msecond_h128 : in std_logic_vector(31 downto 0); |
out_h128 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
-- begin architecture description |
begin |
|
-- we assign the input signal to the respective |
-- bytes as is described in the prototype |
byte15 <= in_key_tk128(7 downto 0); |
byte14 <= in_key_tk128(15 downto 8); |
byte13 <= in_key_tk128(23 downto 16); |
byte12 <= in_key_tk128(31 downto 24); |
byte11 <= in_key_tk128(39 downto 32); |
byte10 <= in_key_tk128(47 downto 40); |
byte9 <= in_key_tk128(55 downto 48); |
byte8 <= in_key_tk128(63 downto 56); |
byte7 <= in_key_tk128(71 downto 64); |
byte6 <= in_key_tk128(79 downto 72); |
byte5 <= in_key_tk128(87 downto 80); |
byte4 <= in_key_tk128(95 downto 88); |
byte3 <= in_key_tk128(103 downto 96); |
byte2 <= in_key_tk128(111 downto 104); |
byte1 <= in_key_tk128(119 downto 112); |
byte0 <= in_key_tk128(127 downto 120); |
|
-- we form the M{0..3} |
M0 <= byte3 & byte2 & byte1 & byte0; |
M1 <= byte7 & byte6 & byte5 & byte4; |
M2 <= byte11 & byte10 & byte9 & byte8; |
M3 <= byte15 & byte14 & byte13 & byte12; |
|
-- upper h |
upper_h: h_128 |
port map ( |
in_h128 => even_in_tk128, |
Mfirst_h128 => M2, |
Msecond_h128 => M0, |
out_h128 => to_up_pht |
); |
|
-- lower h |
lower_h: h_128 |
port map ( |
in_h128 => odd_in_tk128, |
Mfirst_h128 => M3, |
Msecond_h128 => M1, |
out_h128 => to_shift_8 |
); |
|
-- left rotate by 8 |
from_shift_8(31 downto 8) <= to_shift_8(23 downto 0); |
from_shift_8(7 downto 0) <= to_shift_8(31 downto 24); |
|
-- pht transformation |
pht_transform: pht |
port map ( |
up_in_pht => to_up_pht, |
down_in_pht => from_shift_8, |
up_out_pht => out_key_up_tk128, |
down_out_pht => to_shift_9 |
); |
|
-- left rotate by 9 |
out_key_down_tk128(31 downto 9) <= to_shift_9(22 downto 0); |
out_key_down_tk128(8 downto 0) <= to_shift_9(31 downto 23); |
|
end twofish_keysched128_arch; |
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
-- |
-- twofish S key component for 128 bits key |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity twofish_S128 is |
port ( |
in_key_ts128 : in std_logic_vector(127 downto 0); |
out_Sfirst_ts128, |
out_Ssecond_ts128 : out std_logic_vector(31 downto 0) |
); |
end twofish_S128; |
|
architecture twofish_S128_arch of twofish_S128 is |
|
-- we declare the components to be used |
component reed_solomon128 |
port ( |
in_rs128 : in std_logic_vector(127 downto 0); |
out_Sfirst_rs128, |
out_Ssecond_rs128 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
signal twofish_key : std_logic_vector(127 downto 0); |
signal byte15, byte14, byte13, byte12, byte11, byte10, |
byte9, byte8, byte7, byte6, byte5, byte4, |
byte3, byte2, byte1, byte0 : std_logic_vector(7 downto 0); |
|
-- begin architecture description |
begin |
|
-- splitting the input |
byte15 <= in_key_ts128(7 downto 0); |
byte14 <= in_key_ts128(15 downto 8); |
byte13 <= in_key_ts128(23 downto 16); |
byte12 <= in_key_ts128(31 downto 24); |
byte11 <= in_key_ts128(39 downto 32); |
byte10 <= in_key_ts128(47 downto 40); |
byte9 <= in_key_ts128(55 downto 48); |
byte8 <= in_key_ts128(63 downto 56); |
byte7 <= in_key_ts128(71 downto 64); |
byte6 <= in_key_ts128(79 downto 72); |
byte5 <= in_key_ts128(87 downto 80); |
byte4 <= in_key_ts128(95 downto 88); |
byte3 <= in_key_ts128(103 downto 96); |
byte2 <= in_key_ts128(111 downto 104); |
byte1 <= in_key_ts128(119 downto 112); |
byte0 <= in_key_ts128(127 downto 120); |
|
-- forming the key |
twofish_key <= byte15 & byte14 & byte13 & byte12 & byte11 & byte10 & byte9 & byte8 & byte7 & |
byte6 & byte5 & byte4 & byte3 & byte2 & byte1 & byte0; |
|
|
-- the keys S0,1 |
produce_S0_S1: reed_solomon128 |
port map ( |
in_rs128 => twofish_key, |
out_Sfirst_rs128 => out_Sfirst_ts128, |
out_Ssecond_rs128 => out_Ssecond_ts128 |
); |
|
|
end twofish_S128_arch; |
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
-- |
-- twofish whitening key scheduler for 128 bits key input |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity twofish_whit_keysched128 is |
port ( |
in_key_twk128 : in std_logic_vector(127 downto 0); |
out_K0_twk128, |
out_K1_twk128, |
out_K2_twk128, |
out_K3_twk128, |
out_K4_twk128, |
out_K5_twk128, |
out_K6_twk128, |
out_K7_twk128 : out std_logic_vector(31 downto 0) |
); |
end twofish_whit_keysched128; |
|
architecture twofish_whit_keysched128_arch of twofish_whit_keysched128 is |
|
-- we declare internal signals |
signal to_up_pht_1, |
to_shift_8_1, |
from_shift_8_1, |
to_shift_9_1, |
to_up_pht_2, |
to_shift_8_2, |
from_shift_8_2, |
to_shift_9_2, |
to_up_pht_3, |
to_shift_8_3, |
from_shift_8_3, |
to_shift_9_3, |
to_up_pht_4, |
to_shift_8_4, |
from_shift_8_4, |
to_shift_9_4, |
M0, M1, M2, M3 : std_logic_vector(31 downto 0); |
|
signal byte0, byte1, byte2, byte3, |
byte4, byte5, byte6, byte7, |
byte8, byte9, byte10, byte11, |
byte12, byte13, byte14, byte15 : std_logic_vector(7 downto 0); |
|
signal zero, one, two, three, four, five, six, seven : std_logic_vector(7 downto 0); |
|
-- we declare the components to be used |
component pht |
port ( |
up_in_pht, |
down_in_pht : in std_logic_vector(31 downto 0); |
up_out_pht, |
down_out_pht : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component h_128 |
port ( |
in_h128 : in std_logic_vector(7 downto 0); |
Mfirst_h128, |
Msecond_h128 : in std_logic_vector(31 downto 0); |
out_h128 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
-- begin architecture description |
begin |
|
-- we produce the first eight numbers |
zero <= "00000000"; |
one <= "00000001"; |
two <= "00000010"; |
three <= "00000011"; |
four <= "00000100"; |
five <= "00000101"; |
six <= "00000110"; |
seven <= "00000111"; |
|
-- we assign the input signal to the respective |
-- bytes as is described in the prototype |
byte15 <= in_key_twk128(7 downto 0); |
byte14 <= in_key_twk128(15 downto 8); |
byte13 <= in_key_twk128(23 downto 16); |
byte12 <= in_key_twk128(31 downto 24); |
byte11 <= in_key_twk128(39 downto 32); |
byte10 <= in_key_twk128(47 downto 40); |
byte9 <= in_key_twk128(55 downto 48); |
byte8 <= in_key_twk128(63 downto 56); |
byte7 <= in_key_twk128(71 downto 64); |
byte6 <= in_key_twk128(79 downto 72); |
byte5 <= in_key_twk128(87 downto 80); |
byte4 <= in_key_twk128(95 downto 88); |
byte3 <= in_key_twk128(103 downto 96); |
byte2 <= in_key_twk128(111 downto 104); |
byte1 <= in_key_twk128(119 downto 112); |
byte0 <= in_key_twk128(127 downto 120); |
|
-- we form the M{0..3} |
M0 <= byte3 & byte2 & byte1 & byte0; |
M1 <= byte7 & byte6 & byte5 & byte4; |
M2 <= byte11 & byte10 & byte9 & byte8; |
M3 <= byte15 & byte14 & byte13 & byte12; |
|
-- we produce the keys for the whitening steps |
-- keys K0,1 |
-- upper h |
upper_h1: h_128 |
port map ( |
in_h128 => zero, |
Mfirst_h128 => M2, |
Msecond_h128 => M0, |
out_h128 => to_up_pht_1 |
); |
|
-- lower h |
lower_h1: h_128 |
port map ( |
in_h128 => one, |
Mfirst_h128 => M3, |
Msecond_h128 => M1, |
out_h128 => to_shift_8_1 |
); |
|
-- left rotate by 8 |
from_shift_8_1(31 downto 8) <= to_shift_8_1(23 downto 0); |
from_shift_8_1(7 downto 0) <= to_shift_8_1(31 downto 24); |
|
-- pht transformation |
pht_transform1: pht |
port map ( |
up_in_pht => to_up_pht_1, |
down_in_pht => from_shift_8_1, |
up_out_pht => out_K0_twk128, |
down_out_pht => to_shift_9_1 |
); |
|
-- left rotate by 9 |
out_K1_twk128(31 downto 9) <= to_shift_9_1(22 downto 0); |
out_K1_twk128(8 downto 0) <= to_shift_9_1(31 downto 23); |
|
-- keys K2,3 |
-- upper h |
upper_h2: h_128 |
port map ( |
in_h128 => two, |
Mfirst_h128 => M2, |
Msecond_h128 => M0, |
out_h128 => to_up_pht_2 |
); |
|
-- lower h |
lower_h2: h_128 |
port map ( |
in_h128 => three, |
Mfirst_h128 => M3, |
Msecond_h128 => M1, |
out_h128 => to_shift_8_2 |
); |
|
-- left rotate by 8 |
from_shift_8_2(31 downto 8) <= to_shift_8_2(23 downto 0); |
from_shift_8_2(7 downto 0) <= to_shift_8_2(31 downto 24); |
|
-- pht transformation |
pht_transform2: pht |
port map ( |
up_in_pht => to_up_pht_2, |
down_in_pht => from_shift_8_2, |
up_out_pht => out_K2_twk128, |
down_out_pht => to_shift_9_2 |
); |
|
-- left rotate by 9 |
out_K3_twk128(31 downto 9) <= to_shift_9_2(22 downto 0); |
out_K3_twk128(8 downto 0) <= to_shift_9_2(31 downto 23); |
|
-- keys K4,5 |
-- upper h |
upper_h3: h_128 |
port map ( |
in_h128 => four, |
Mfirst_h128 => M2, |
Msecond_h128 => M0, |
out_h128 => to_up_pht_3 |
); |
|
-- lower h |
lower_h3: h_128 |
port map ( |
in_h128 => five, |
Mfirst_h128 => M3, |
Msecond_h128 => M1, |
out_h128 => to_shift_8_3 |
); |
|
-- left rotate by 8 |
from_shift_8_3(31 downto 8) <= to_shift_8_3(23 downto 0); |
from_shift_8_3(7 downto 0) <= to_shift_8_3(31 downto 24); |
|
-- pht transformation |
pht_transform3: pht |
port map ( |
up_in_pht => to_up_pht_3, |
down_in_pht => from_shift_8_3, |
up_out_pht => out_K4_twk128, |
down_out_pht => to_shift_9_3 |
); |
|
-- left rotate by 9 |
out_K5_twk128(31 downto 9) <= to_shift_9_3(22 downto 0); |
out_K5_twk128(8 downto 0) <= to_shift_9_3(31 downto 23); |
|
-- keys K6,7 |
-- upper h |
upper_h4: h_128 |
port map ( |
in_h128 => six, |
Mfirst_h128 => M2, |
Msecond_h128 => M0, |
out_h128 => to_up_pht_4 |
); |
|
-- lower h |
lower_h4: h_128 |
port map ( |
in_h128 => seven, |
Mfirst_h128 => M3, |
Msecond_h128 => M1, |
out_h128 => to_shift_8_4 |
); |
|
-- left rotate by 8 |
from_shift_8_4(31 downto 8) <= to_shift_8_4(23 downto 0); |
from_shift_8_4(7 downto 0) <= to_shift_8_4(31 downto 24); |
|
-- pht transformation |
pht_transform4: pht |
port map ( |
up_in_pht => to_up_pht_4, |
down_in_pht => from_shift_8_4, |
up_out_pht => out_K6_twk128, |
down_out_pht => to_shift_9_4 |
); |
|
-- left rotate by 9 |
out_K7_twk128(31 downto 9) <= to_shift_9_4(22 downto 0); |
out_K7_twk128(8 downto 0) <= to_shift_9_4(31 downto 23); |
|
end twofish_whit_keysched128_arch; |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
-- |
-- twofish encryption round with 128 bit key input |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity twofish_encryption_round128 is |
port ( |
in1_ter128, |
in2_ter128, |
in3_ter128, |
in4_ter128, |
in_Sfirst_ter128, |
in_Ssecond_ter128, |
in_key_up_ter128, |
in_key_down_ter128 : in std_logic_vector(31 downto 0); |
out1_ter128, |
out2_ter128, |
out3_ter128, |
out4_ter128 : out std_logic_vector(31 downto 0) |
); |
end twofish_encryption_round128; |
|
architecture twofish_encryption_round128_arch of twofish_encryption_round128 is |
|
-- we declare internal signals |
signal to_left_shift, |
from_right_shift, |
to_xor_with3, |
to_xor_with4 : std_logic_vector(31 downto 0); |
|
component f_128 |
port ( |
up_in_f128, |
low_in_f128, |
S0_in_f128, |
S1_in_f128, |
up_key_f128, |
low_key_f128 : in std_logic_vector(31 downto 0); |
up_out_f128, |
low_out_f128 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
-- begin architecture description |
begin |
|
-- we declare f_128 |
function_f: f_128 |
port map ( |
up_in_f128 => in1_ter128, |
low_in_f128 => in2_ter128, |
S0_in_f128 => in_Sfirst_ter128, |
S1_in_f128 => in_Ssecond_ter128, |
up_key_f128 => in_key_up_ter128, |
low_key_f128 => in_key_down_ter128, |
up_out_f128 => to_xor_with3, |
low_out_f128 => to_xor_with4 |
); |
|
-- we perform the exchange |
-- in1_ter128 -> out3_ter128 |
-- in2_ter128 -> out4_ter128 |
-- in3_ter128 -> out1_ter128 |
-- in4_ter128 -> out2_ter128 |
|
-- we perform the left xor between the upper f function and |
-- the third input (input 3) |
to_left_shift <= to_xor_with3 XOR in3_ter128; |
|
-- we perform the left side rotation to the right by 1 and |
-- we perform the exchange too |
out1_ter128(30 downto 0) <= to_left_shift(31 downto 1); |
out1_ter128(31) <= to_left_shift(0); |
|
-- we perform the right side rotation to the left by 1 |
from_right_shift(0) <= in4_ter128(31); |
from_right_shift(31 downto 1) <= in4_ter128(30 downto 0); |
|
-- we perform the right xor between the lower f function and |
-- the fourth input (input 4) |
out2_ter128 <= from_right_shift XOR to_xor_with4; |
|
-- we perform the last exchanges |
out3_ter128 <= in1_ter128; |
out4_ter128 <= in2_ter128; |
|
end twofish_encryption_round128_arch; |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
-- |
-- twofish decryption round with 128 bit key input |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity twofish_decryption_round128 is |
port ( |
in1_tdr128, |
in2_tdr128, |
in3_tdr128, |
in4_tdr128, |
in_Sfirst_tdr128, |
in_Ssecond_tdr128, |
in_key_up_tdr128, |
in_key_down_tdr128 : in std_logic_vector(31 downto 0); |
out1_tdr128, |
out2_tdr128, |
out3_tdr128, |
out4_tdr128 : out std_logic_vector(31 downto 0) |
); |
end twofish_decryption_round128; |
|
architecture twofish_decryption_round128_arch of twofish_decryption_round128 is |
|
signal to_xor_with3, |
to_xor_with4, |
to_xor_with_up_f, |
from_xor_with_down_f : std_logic_vector(31 downto 0); |
|
component f_128 |
port ( |
up_in_f128, |
low_in_f128, |
S0_in_f128, |
S1_in_f128, |
up_key_f128, |
low_key_f128 : in std_logic_vector(31 downto 0); |
up_out_f128, |
low_out_f128 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
begin |
|
-- we instantiate f function |
function_f: f_128 |
port map ( |
up_in_f128 => in1_tdr128, |
low_in_f128 => in2_tdr128, |
S0_in_f128 => in_Sfirst_tdr128, |
S1_in_f128 => in_Ssecond_tdr128, |
up_key_f128 => in_key_up_tdr128, |
low_key_f128 => in_key_down_tdr128, |
up_out_f128 => to_xor_with3, |
low_out_f128 => to_xor_with4 |
); |
|
-- output 1: input3 with upper f |
-- we first rotate the input3 by 1 bit leftwise |
to_xor_with_up_f(0) <= in3_tdr128(31); |
to_xor_with_up_f(31 downto 1) <= in3_tdr128(30 downto 0); |
|
-- we perform the XOR with the upper output of f and the result |
-- is ouput 1 |
out1_tdr128 <= to_xor_with_up_f XOR to_xor_with3; |
|
-- output 2: input4 with lower f |
-- we perform the XOR with the lower output of f |
from_xor_with_down_f <= in4_tdr128 XOR to_xor_with4; |
|
-- we perform the rotation by 1 bit rightwise and the result |
-- is output2 |
out2_tdr128(31) <= from_xor_with_down_f(0); |
out2_tdr128(30 downto 0) <= from_xor_with_down_f(31 downto 1); |
|
-- we assign outputs 3 and 4 |
out3_tdr128 <= in1_tdr128; |
out4_tdr128 <= in2_tdr128; |
|
end twofish_decryption_round128_arch; |
|
-- ============================================== -- |
-- ============================================== -- |
-- -- |
-- third part: 192 key input dependent components -- |
-- -- |
-- ============================================== -- |
-- ============================================== -- |
|
-- |
-- reed solomon for 192bits key |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity reed_solomon192 is |
port ( |
in_rs192 : in std_logic_vector(191 downto 0); |
out_Sfirst_rs192, |
out_Ssecond_rs192, |
out_Sthird_rs192 : out std_logic_vector(31 downto 0) |
); |
end reed_solomon192; |
|
architecture rs_192_arch of reed_solomon192 is |
|
-- declaring all components necessary for reed solomon |
-- 01 |
component mul01 |
port ( |
in_mul01 : in std_logic_vector(7 downto 0); |
out_mul01 : out std_logic_vector(7 downto 0) |
); |
end component; |
|
-- a4 |
component mula4 |
port ( |
in_mula4 : in std_logic_vector(7 downto 0); |
out_mula4 : out std_logic_vector(7 downto 0) |
); |
end component; |
|
-- 55 |
component mul55 |
port ( |
in_mul55 : in std_logic_vector(7 downto 0); |
out_mul55 : out std_logic_vector(7 downto 0) |
); |
end component; |
|
-- 87 |
component mul87 |
port ( |
in_mul87 : in std_logic_vector(7 downto 0); |
out_mul87 : out std_logic_vector(7 downto 0) |
); |
end component; |
|
-- 5a |
component mul5a |
port ( |
in_mul5a : in std_logic_vector(7 downto 0); |
out_mul5a : out std_logic_vector(7 downto 0) |
); |
end component; |
|
-- 58 |
component mul58 |
port ( |
in_mul58 : in std_logic_vector(7 downto 0); |
out_mul58 : out std_logic_vector(7 downto 0) |
); |
end component; |
|
|
-- db |
component muldb |
port ( |
in_muldb : in std_logic_vector(7 downto 0); |
out_muldb : out std_logic_vector(7 downto 0) |
); |
end component; |
|
|
-- 9e |
component mul9e |
port ( |
in_mul9e : in std_logic_vector(7 downto 0); |
out_mul9e : out std_logic_vector(7 downto 0) |
); |
end component; |
|
|
-- 56 |
component mul56 |
port ( |
in_mul56 : in std_logic_vector(7 downto 0); |
out_mul56 : out std_logic_vector(7 downto 0) |
); |
end component; |
|
|
-- 82 |
component mul82 |
port ( |
in_mul82 : in std_logic_vector(7 downto 0); |
out_mul82 : out std_logic_vector(7 downto 0) |
); |
end component; |
|
|
-- f3 |
component mulf3 |
port ( |
in_mulf3 : in std_logic_vector(7 downto 0); |
out_mulf3 : out std_logic_vector(7 downto 0) |
); |
end component; |
|
|
-- 1e |
component mul1e |
port ( |
in_mul1e : in std_logic_vector(7 downto 0); |
out_mul1e : out std_logic_vector(7 downto 0) |
); |
end component; |
|
|
-- c6 |
component mulc6 |
port ( |
in_mulc6 : in std_logic_vector(7 downto 0); |
out_mulc6 : out std_logic_vector(7 downto 0) |
); |
end component; |
|
|
-- 68 |
component mul68 |
port ( |
in_mul68 : in std_logic_vector(7 downto 0); |
out_mul68 : out std_logic_vector(7 downto 0) |
); |
end component; |
|
|
-- e5 |
component mule5 |
port ( |
in_mule5 : in std_logic_vector(7 downto 0); |
out_mule5 : out std_logic_vector(7 downto 0) |
); |
end component; |
|
|
-- 02 |
component mul02 |
port ( |
in_mul02 : in std_logic_vector(7 downto 0); |
out_mul02 : out std_logic_vector(7 downto 0) |
); |
end component; |
|
|
-- a1 |
component mula1 |
port ( |
in_mula1 : in std_logic_vector(7 downto 0); |
out_mula1 : out std_logic_vector(7 downto 0) |
); |
end component; |
|
|
-- fc |
component mulfc |
port ( |
in_mulfc : in std_logic_vector(7 downto 0); |
out_mulfc : out std_logic_vector(7 downto 0) |
); |
end component; |
|
|
-- c1 |
component mulc1 |
port ( |
in_mulc1 : in std_logic_vector(7 downto 0); |
out_mulc1 : out std_logic_vector(7 downto 0) |
); |
end component; |
|
|
-- 47 |
component mul47 |
port ( |
in_mul47 : in std_logic_vector(7 downto 0); |
out_mul47 : out std_logic_vector(7 downto 0) |
); |
end component; |
|
|
|
-- ae |
component mulae |
port ( |
in_mulae : in std_logic_vector(7 downto 0); |
out_mulae : out std_logic_vector(7 downto 0) |
); |
end component; |
|
|
|
-- 3d |
component mul3d |
port ( |
in_mul3d : in std_logic_vector(7 downto 0); |
out_mul3d : out std_logic_vector(7 downto 0) |
); |
end component; |
|
|
|
-- 19 |
component mul19 |
port ( |
in_mul19 : in std_logic_vector(7 downto 0); |
out_mul19 : out std_logic_vector(7 downto 0) |
); |
end component; |
|
|
-- 03 |
component mul03 |
port ( |
in_mul03 : in std_logic_vector(7 downto 0); |
out_mul03 : out std_logic_vector(7 downto 0) |
); |
end component; |
|
|
-- declaring internal signals |
signal m0,m1,m2,m3,m4,m5,m6,m7,m8,m9,m10,m11,m12,m13,m14,m15, |
m16, m17, m18, m19, m20, m21, m22, m23 : std_logic_vector(7 downto 0); |
signal s00,s01,s02,s03,s10,s11,s12,s13, s20, s21, s22, s23 : std_logic_vector(7 downto 0); |
signal m0_01,m1_a4,m2_55,m3_87,m4_5a,m5_58,m6_db,m7_9e, |
m0_a4,m1_56,m2_82,m3_f3,m4_1e,m5_c6,m6_68,m7_e5, |
m0_02,m1_a1,m2_fc,m3_c1,m4_47,m5_ae,m6_3d,m7_19, |
m0_a4_1,m1_55,m2_87,m3_5a,m4_58,m5_db,m6_9e,m7_03 : std_logic_vector(7 downto 0); |
signal m8_01,m9_a4,m10_55,m11_87,m12_5a,m13_58,m14_db,m15_9e, |
m8_a4,m9_56,m10_82,m11_f3,m12_1e,m13_c6,m14_68,m15_e5, |
m8_02,m9_a1,m10_fc,m11_c1,m12_47,m13_ae,m14_3d,m15_19, |
m8_a4_1,m9_55,m10_87,m11_5a,m12_58,m13_db,m14_9e,m15_03 : std_logic_vector(7 downto 0); |
signal m16_01,m17_a4,m18_55,m19_87,m20_5a,m21_58,m22_db,m23_9e, |
m16_a4,m17_56,m18_82,m19_f3,m20_1e,m21_c6,m22_68,m23_e5, |
m16_02,m17_a1,m18_fc,m19_c1,m20_47,m21_ae,m22_3d,m23_19, |
m16_a4_1,m17_55,m18_87,m19_5a,m20_58,m21_db,m22_9e,m23_03 : std_logic_vector(7 downto 0); |
|
|
-- begin architecture description |
begin |
|
-- first, we separate the input to the respective m |
-- for s0j j=0..3 |
m0 <= in_rs192(7 downto 0); |
m1 <= in_rs192(15 downto 8); |
m2 <= in_rs192(23 downto 16); |
m3 <= in_rs192(31 downto 24); |
m4 <= in_rs192(39 downto 32); |
m5 <= in_rs192(47 downto 40); |
m6 <= in_rs192(55 downto 48); |
m7 <= in_rs192(63 downto 56); |
|
-- for s1j j=0..3 |
m8 <= in_rs192(71 downto 64); |
m9 <= in_rs192(79 downto 72); |
m10 <= in_rs192(87 downto 80); |
m11 <= in_rs192(95 downto 88); |
m12 <= in_rs192(103 downto 96); |
m13 <= in_rs192(111 downto 104); |
m14 <= in_rs192(119 downto 112); |
m15 <= in_rs192(127 downto 120); |
|
-- for s2j j=0..3 |
m16 <= in_rs192(135 downto 128); |
m17 <= in_rs192(143 downto 136); |
m18 <= in_rs192(151 downto 144); |
m19 <= in_rs192(159 downto 152); |
m20 <= in_rs192(167 downto 160); |
m21 <= in_rs192(175 downto 168); |
m22 <= in_rs192(183 downto 176); |
m23 <= in_rs192(191 downto 184); |
|
|
-- after separating signals, we drive them to multipliers |
-- the first line of m0..7 forms s00 |
m0_with_01: mul01 |
port map ( |
in_mul01 => m0, |
out_mul01 => m0_01 |
); |
|
m1_with_a4: mula4 |
port map ( |
in_mula4 => m1, |
out_mula4 => m1_a4 |
); |
|
m2_with_55: mul55 |
port map ( |
in_mul55 => m2, |
out_mul55 => m2_55 |
); |
|
m3_with_87: mul87 |
port map ( |
in_mul87 => m3, |
out_mul87 => m3_87 |
); |
|
m4_with_5a: mul5a |
port map ( |
in_mul5a => m4, |
out_mul5a => m4_5a |
); |
|
m5_with_58: mul58 |
port map ( |
in_mul58 => m5, |
out_mul58 => m5_58 |
); |
|
m6_with_db: muldb |
port map ( |
in_muldb => m6, |
out_muldb => m6_db |
); |
|
m7_with_9e: mul9e |
port map ( |
in_mul9e => m7, |
out_mul9e => m7_9e |
); |
|
-- the second row creates s01 |
m0_with_a4: mula4 |
port map ( |
in_mula4 => m0, |
out_mula4 => m0_a4 |
); |
|
m1_with_56: mul56 |
port map ( |
in_mul56 => m1, |
out_mul56 => m1_56 |
); |
|
m2_with_82: mul82 |
port map ( |
in_mul82 => m2, |
out_mul82 => m2_82 |
); |
|
m3_with_f3: mulf3 |
port map ( |
in_mulf3 => m3, |
out_mulf3 => m3_f3 |
); |
|
m4_with_1e: mul1e |
port map ( |
in_mul1e => m4, |
out_mul1e => m4_1e |
); |
|
m5_with_c6: mulc6 |
port map ( |
in_mulc6 => m5, |
out_mulc6 => m5_c6 |
); |
|
m6_with_68: mul68 |
port map ( |
in_mul68 => m6, |
out_mul68 => m6_68 |
); |
|
m7_with_e5: mule5 |
port map ( |
in_mule5 => m7, |
out_mule5 => m7_e5 |
); |
|
-- the third row creates s02 |
m0_with_02: mul02 |
port map ( |
in_mul02 => m0, |
out_mul02 => m0_02 |
); |
|
m1_with_a1: mula1 |
port map ( |
in_mula1 => m1, |
out_mula1 => m1_a1 |
); |
|
m2_with_fc: mulfc |
port map ( |
in_mulfc => m2, |
out_mulfc => m2_fc |
); |
|
m3_with_c1: mulc1 |
port map ( |
in_mulc1 => m3, |
out_mulc1 => m3_c1 |
); |
|
m4_with_47: mul47 |
port map ( |
in_mul47 => m4, |
out_mul47 => m4_47 |
); |
|
m5_with_ae: mulae |
port map ( |
in_mulae => m5, |
out_mulae => m5_ae |
); |
|
m6_with_3d: mul3d |
port map ( |
in_mul3d => m6, |
out_mul3d => m6_3d |
); |
|
m7_with_19: mul19 |
port map ( |
in_mul19 => m7, |
out_mul19 => m7_19 |
); |
|
-- the fourth row creates s03 |
m0_with_a4_1: mula4 |
port map ( |
in_mula4 => m0, |
out_mula4 => m0_a4_1 |
); |
|
m1_with_55: mul55 |
port map ( |
in_mul55 => m1, |
out_mul55 => m1_55 |
); |
|
m2_with_87: mul87 |
port map ( |
in_mul87 => m2, |
out_mul87 => m2_87 |
); |
|
m3_with_5a: mul5a |
port map ( |
in_mul5a => m3, |
out_mul5a => m3_5a |
); |
|
m4_with_58: mul58 |
port map ( |
in_mul58 => m4, |
out_mul58 => m4_58 |
); |
|
m5_with_db: muldb |
port map ( |
in_muldb => m5, |
out_muldb => m5_db |
); |
|
m6_with_9e: mul9e |
port map ( |
in_mul9e => m6, |
out_mul9e => m6_9e |
); |
|
m7_with_03: mul03 |
port map ( |
in_mul03 => m7, |
out_mul03 => m7_03 |
); |
|
|
-- we create the s1,j j=0..3 |
-- the first row of m8..15 creates the s10 |
m8_with_01: mul01 |
port map ( |
in_mul01 => m8, |
out_mul01 => m8_01 |
); |
|
m9_with_a4: mula4 |
port map ( |
in_mula4 => m9, |
out_mula4 => m9_a4 |
); |
|
m10_with_55: mul55 |
port map ( |
in_mul55 => m10, |
out_mul55 => m10_55 |
); |
|
m11_with_87: mul87 |
port map ( |
in_mul87 => m11, |
out_mul87 => m11_87 |
); |
|
m12_with_5a: mul5a |
port map ( |
in_mul5a => m12, |
out_mul5a => m12_5a |
); |
|
m13_with_58: mul58 |
port map ( |
in_mul58 => m13, |
out_mul58 => m13_58 |
); |
|
m14_with_db: muldb |
port map ( |
in_muldb => m14, |
out_muldb => m14_db |
); |
|
m15_with_9e: mul9e |
port map ( |
in_mul9e => m15, |
out_mul9e => m15_9e |
); |
|
-- the second row creates s11 |
m8_with_a4: mula4 |
port map ( |
in_mula4 => m8, |
out_mula4 => m8_a4 |
); |
|
m9_with_56: mul56 |
port map ( |
in_mul56 => m9, |
out_mul56 => m9_56 |
); |
|
m10_with_82: mul82 |
port map ( |
in_mul82 => m10, |
out_mul82 => m10_82 |
); |
|
m11_with_f3: mulf3 |
port map ( |
in_mulf3 => m11, |
out_mulf3 => m11_f3 |
); |
|
m12_with_1e: mul1e |
port map ( |
in_mul1e => m12, |
out_mul1e => m12_1e |
); |
|
m13_with_c6: mulc6 |
port map ( |
in_mulc6 => m13, |
out_mulc6 => m13_c6 |
); |
|
m14_with_68: mul68 |
port map ( |
in_mul68 => m14, |
out_mul68 => m14_68 |
); |
|
m15_with_e5: mule5 |
port map ( |
in_mule5 => m15, |
out_mule5 => m15_e5 |
); |
|
-- the third row creates s12 |
m8_with_02: mul02 |
port map ( |
in_mul02 => m8, |
out_mul02 => m8_02 |
); |
|
m9_with_a1: mula1 |
port map ( |
in_mula1 => m9, |
out_mula1 => m9_a1 |
); |
|
m10_with_fc: mulfc |
port map ( |
in_mulfc => m10, |
out_mulfc => m10_fc |
); |
|
m11_with_c1: mulc1 |
port map ( |
in_mulc1 => m11, |
out_mulc1 => m11_c1 |
); |
|
m12_with_47: mul47 |
port map ( |
in_mul47 => m12, |
out_mul47 => m12_47 |
); |
|
m13_with_ae: mulae |
port map ( |
in_mulae => m13, |
out_mulae => m13_ae |
); |
|
m14_with_3d: mul3d |
port map ( |
in_mul3d => m14, |
out_mul3d => m14_3d |
); |
|
m15_with_19: mul19 |
port map ( |
in_mul19 => m15, |
out_mul19 => m15_19 |
); |
|
-- the fourth row creates s13 |
m8_with_a4_1: mula4 |
port map ( |
in_mula4 => m8, |
out_mula4 => m8_a4_1 |
); |
|
m9_with_55: mul55 |
port map ( |
in_mul55 => m9, |
out_mul55 => m9_55 |
); |
|
m10_with_87: mul87 |
port map ( |
in_mul87 => m10, |
out_mul87 => m10_87 |
); |
|
m11_with_5a: mul5a |
port map ( |
in_mul5a => m11, |
out_mul5a => m11_5a |
); |
|
m12_with_58: mul58 |
port map ( |
in_mul58 => m12, |
out_mul58 => m12_58 |
); |
|
m13_with_db: muldb |
port map ( |
in_muldb => m13, |
out_muldb => m13_db |
); |
|
m14_with_9e: mul9e |
port map ( |
in_mul9e => m14, |
out_mul9e => m14_9e |
); |
|
m15_with_03: mul03 |
port map ( |
in_mul03 => m15, |
out_mul03 => m15_03 |
); |
|
-- we create the s2,j j=0..3 |
-- the first row of m16..23 creates the s20 |
m16_with_01: mul01 |
port map ( |
in_mul01 => m16, |
out_mul01 => m16_01 |
); |
|
m17_with_a4: mula4 |
port map ( |
in_mula4 => m17, |
out_mula4 => m17_a4 |
); |
|
m18_with_55: mul55 |
port map ( |
in_mul55 => m18, |
out_mul55 => m18_55 |
); |
|
m19_with_87: mul87 |
port map ( |
in_mul87 => m19, |
out_mul87 => m19_87 |
); |
|
m20_with_5a: mul5a |
port map ( |
in_mul5a => m20, |
out_mul5a => m20_5a |
); |
|
m21_with_58: mul58 |
port map ( |
in_mul58 => m21, |
out_mul58 => m21_58 |
); |
|
m22_with_db: muldb |
port map ( |
in_muldb => m22, |
out_muldb => m22_db |
); |
|
m23_with_9e: mul9e |
port map ( |
in_mul9e => m23, |
out_mul9e => m23_9e |
); |
|
-- the second row creates s21 |
m16_with_a4: mula4 |
port map ( |
in_mula4 => m16, |
out_mula4 => m16_a4 |
); |
|
m17_with_56: mul56 |
port map ( |
in_mul56 => m17, |
out_mul56 => m17_56 |
); |
|
m18_with_82: mul82 |
port map ( |
in_mul82 => m18, |
out_mul82 => m18_82 |
); |
|
m19_with_f3: mulf3 |
port map ( |
in_mulf3 => m19, |
out_mulf3 => m19_f3 |
); |
|
m20_with_1e: mul1e |
port map ( |
in_mul1e => m20, |
out_mul1e => m20_1e |
); |
|
m21_with_c6: mulc6 |
port map ( |
in_mulc6 => m21, |
out_mulc6 => m21_c6 |
); |
|
m22_with_68: mul68 |
port map ( |
in_mul68 => m22, |
out_mul68 => m22_68 |
); |
|
m23_with_e5: mule5 |
port map ( |
in_mule5 => m23, |
out_mule5 => m23_e5 |
); |
|
-- the third row creates s22 |
m16_with_02: mul02 |
port map ( |
in_mul02 => m16, |
out_mul02 => m16_02 |
); |
|
m17_with_a1: mula1 |
port map ( |
in_mula1 => m17, |
out_mula1 => m17_a1 |
); |
|
m18_with_fc: mulfc |
port map ( |
in_mulfc => m18, |
out_mulfc => m18_fc |
); |
|
m19_with_c1: mulc1 |
port map ( |
in_mulc1 => m19, |
out_mulc1 => m19_c1 |
); |
|
m20_with_47: mul47 |
port map ( |
in_mul47 => m20, |
out_mul47 => m20_47 |
); |
|
m21_with_ae: mulae |
port map ( |
in_mulae => m21, |
out_mulae => m21_ae |
); |
|
m22_with_3d: mul3d |
port map ( |
in_mul3d => m22, |
out_mul3d => m22_3d |
); |
|
m23_with_19: mul19 |
port map ( |
in_mul19 => m23, |
out_mul19 => m23_19 |
); |
|
-- the fourth row creates s23 |
m16_with_a4_1: mula4 |
port map ( |
in_mula4 => m16, |
out_mula4 => m16_a4_1 |
); |
|
m17_with_55: mul55 |
port map ( |
in_mul55 => m17, |
out_mul55 => m17_55 |
); |
|
m18_with_87: mul87 |
port map ( |
in_mul87 => m18, |
out_mul87 => m18_87 |
); |
|
m19_with_5a: mul5a |
port map ( |
in_mul5a => m19, |
out_mul5a => m19_5a |
); |
|
m20_with_58: mul58 |
port map ( |
in_mul58 => m20, |
out_mul58 => m20_58 |
); |
|
m21_with_db: muldb |
port map ( |
in_muldb => m21, |
out_muldb => m21_db |
); |
|
m22_with_9e: mul9e |
port map ( |
in_mul9e => m22, |
out_mul9e => m22_9e |
); |
|
m23_with_03: mul03 |
port map ( |
in_mul03 => m23, |
out_mul03 => m23_03 |
); |
|
-- after getting the results from multipliers |
-- we combine them in order to get the additions |
s00 <= m0_01 XOR m1_a4 XOR m2_55 XOR m3_87 XOR m4_5a XOR m5_58 XOR m6_db XOR m7_9e; |
s01 <= m0_a4 XOR m1_56 XOR m2_82 XOR m3_f3 XOR m4_1e XOR m5_c6 XOR m6_68 XOR m7_e5; |
s02 <= m0_02 XOR m1_a1 XOR m2_fc XOR m3_c1 XOR m4_47 XOR m5_ae XOR m6_3d XOR m7_19; |
s03 <= m0_a4_1 XOR m1_55 XOR m2_87 XOR m3_5a XOR m4_58 XOR m5_db XOR m6_9e XOR m7_03; |
|
-- after creating s0,j j=0...3 we form the S0 |
-- little endian |
out_Sfirst_rs192 <= s03 & s02 & s01 & s00; |
|
s10 <= m8_01 XOR m9_a4 XOR m10_55 XOR m11_87 XOR m12_5a XOR m13_58 XOR m14_db XOR m15_9e; |
s11 <= m8_a4 XOR m9_56 XOR m10_82 XOR m11_f3 XOR m12_1e XOR m13_c6 XOR m14_68 XOR m15_e5; |
s12 <= m8_02 XOR m9_a1 XOR m10_fc XOR m11_c1 XOR m12_47 XOR m13_ae XOR m14_3d XOR m15_19; |
s13 <= m8_a4_1 XOR m9_55 XOR m10_87 XOR m11_5a XOR m12_58 XOR m13_db XOR m14_9e XOR m15_03; |
|
-- after creating s1,j j=0...3 we form the S1 |
-- little endian |
out_Ssecond_rs192 <= s13 & s12 & s11 & s10; |
|
s20 <= m16_01 XOR m17_a4 XOR m18_55 XOR m19_87 XOR m20_5a XOR m21_58 XOR m22_db XOR m23_9e; |
s21 <= m16_a4 XOR m17_56 XOR m18_82 XOR m19_f3 XOR m20_1e XOR m21_c6 XOR m22_68 XOR m23_e5; |
s22 <= m16_02 XOR m17_a1 XOR m18_fc XOR m19_c1 XOR m20_47 XOR m21_ae XOR m22_3d XOR m23_19; |
s23 <= m16_a4_1 XOR m17_55 XOR m18_87 XOR m19_5a XOR m20_58 XOR m21_db XOR m22_9e XOR m23_03; |
|
-- after creating s2j j=0...3 we form the S2 |
-- little endian |
out_Sthird_rs192 <= s23 & s22 & s21 & s20; |
|
|
end rs_192_arch; |
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
-- |
-- h function for 192 bits key |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity h_192 is |
port ( |
in_h192 : in std_logic_vector(7 downto 0); |
Mfirst_h192, |
Msecond_h192, |
Mthird_h192 : in std_logic_vector(31 downto 0); |
out_h192 : out std_logic_vector(31 downto 0) |
); |
end h_192; |
|
architecture h192_arch of h_192 is |
|
-- we declare internal signals |
signal from_first_row, |
to_second_row, |
from_second_row, |
to_third_row, |
from_third_row, |
to_fourth_row, |
to_mds : std_logic_vector(31 downto 0); |
|
-- we declare all components needed |
component q0 |
port ( |
in_q0 : in std_logic_vector(7 downto 0); |
out_q0 : out std_logic_vector(7 downto 0) |
); |
end component; |
|
component q1 |
port ( |
in_q1 : in std_logic_vector(7 downto 0); |
out_q1 : out std_logic_vector(7 downto 0) |
); |
end component; |
|
component mds |
port ( |
y0, |
y1, |
y2, |
y3 : in std_logic_vector(7 downto 0); |
z0, |
z1, |
z2, |
z3 : out std_logic_vector(7 downto 0) |
); |
end component; |
|
-- begin architecture description |
begin |
|
-- first row of q |
first_q1_1: q1 |
port map ( |
in_q1 => in_h192, |
out_q1 => from_first_row(7 downto 0) |
); |
|
first_q1_2: q1 |
port map ( |
in_q1 => in_h192, |
out_q1 => from_first_row(15 downto 8) |
); |
|
first_q0_1: q0 |
port map ( |
in_q0 => in_h192, |
out_q0 => from_first_row(23 downto 16) |
); |
|
first_q0_2: q0 |
port map ( |
in_q0 => in_h192, |
out_q0 => from_first_row(31 downto 24) |
); |
|
-- we perform the XOR of the results of the first row |
-- with first M of h (Mfirst_h128) |
to_second_row <= from_first_row XOR Mfirst_h192; |
|
-- second row of q |
second_q0_1: q0 |
port map ( |
in_q0 => to_second_row(7 downto 0), |
out_q0 => from_second_row(7 downto 0) |
); |
second_q1_1: q1 |
port map ( |
in_q1 => to_second_row(15 downto 8), |
out_q1 => from_second_row(15 downto 8) |
); |
second_q0_2: q0 |
port map ( |
in_q0 => to_second_row(23 downto 16), |
out_q0 => from_second_row(23 downto 16) |
); |
second_q1_2: q1 |
port map ( |
in_q1 => to_second_row(31 downto 24), |
out_q1 => from_second_row(31 downto 24) |
); |
|
-- we perform the XOR of the results of the second row |
-- with second M of h (Msecond_h128) |
to_third_row <= from_second_row XOR Msecond_h192; |
|
-- third row of q |
third_q0_1: q0 |
port map ( |
in_q0 => to_third_row(7 downto 0), |
out_q0 => from_third_row(7 downto 0) |
); |
third_q0_2: q0 |
port map ( |
in_q0 => to_third_row(15 downto 8), |
out_q0 => from_third_row(15 downto 8) |
); |
third_q1_1: q1 |
port map ( |
in_q1 => to_third_row(23 downto 16), |
out_q1 => from_third_row(23 downto 16) |
); |
third_q1_2: q1 |
port map ( |
in_q1 => to_third_row(31 downto 24), |
out_q1 => from_third_row(31 downto 24) |
); |
|
-- we perform the third XOR |
to_fourth_row <= from_third_row XOR Mthird_h192; |
|
-- the fourth row of q |
fourth_q1_1: q1 |
port map ( |
in_q1 => to_fourth_row(7 downto 0), |
out_q1 => to_mds(7 downto 0) |
); |
fourth_q0_1: q0 |
port map ( |
in_q0 => to_fourth_row(15 downto 8), |
out_q0 => to_mds(15 downto 8) |
); |
fourth_q1_2: q1 |
port map ( |
in_q1 => to_fourth_row(23 downto 16), |
out_q1 => to_mds(23 downto 16) |
); |
fourth_q0_2: q0 |
port map ( |
in_q0 => to_fourth_row(31 downto 24), |
out_q0 => to_mds(31 downto 24) |
); |
|
-- mds table |
mds_table: mds |
port map ( |
y0 => to_mds(7 downto 0), |
y1 => to_mds(15 downto 8), |
y2 => to_mds(23 downto 16), |
y3 => to_mds(31 downto 24), |
z0 => out_h192(7 downto 0), |
z1 => out_h192(15 downto 8), |
z2 => out_h192(23 downto 16), |
z3 => out_h192(31 downto 24) |
); |
|
end h192_arch; |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
|
-- |
-- g function for 192 bits key |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity g_192 is |
port ( |
in_g192, |
in_S0_g192, |
in_S1_g192, |
in_S2_g192 : in std_logic_vector(31 downto 0); |
out_g192 : out std_logic_vector(31 downto 0) |
); |
end g_192; |
|
architecture g192_arch of g_192 is |
|
-- we declare the internal signals |
signal from_first_row, |
to_second_row, |
from_second_row, |
to_third_row, |
from_third_row, |
to_fourth_row, |
to_mds : std_logic_vector(31 downto 0); |
|
component q0 |
port ( |
in_q0 : in std_logic_vector(7 downto 0); |
out_q0 : out std_logic_vector(7 downto 0) |
); |
end component; |
|
component q1 |
port ( |
in_q1 : in std_logic_vector(7 downto 0); |
out_q1 : out std_logic_vector(7 downto 0) |
); |
end component; |
|
component mds |
port ( |
y0, |
y1, |
y2, |
y3 : in std_logic_vector(7 downto 0); |
z0, |
z1, |
z2, |
z3 : out std_logic_vector(7 downto 0) |
); |
end component; |
|
-- begin architecture description |
begin |
|
-- first row of q |
first_q1_1: q1 |
port map ( |
in_q1 => in_g192(7 downto 0), |
out_q1 => from_first_row(7 downto 0) |
); |
first_q1_2: q1 |
port map ( |
in_q1 => in_g192(15 downto 8), |
out_q1 => from_first_row(15 downto 8) |
); |
first_q0_1: q0 |
port map ( |
in_q0 => in_g192(23 downto 16), |
out_q0 => from_first_row(23 downto 16) |
); |
first_q0_2: q0 |
port map ( |
in_q0 => in_g192(31 downto 24), |
out_q0 => from_first_row(31 downto 24) |
); |
|
-- we XOR the result of the first row |
-- with the S0 |
to_second_row <= from_first_row XOR in_S0_g192; |
|
-- second row of q |
second_q0_1: q0 |
port map ( |
in_q0 => to_second_row(7 downto 0), |
out_q0 => from_second_row(7 downto 0) |
); |
second_q1_1: q1 |
port map ( |
in_q1 => to_second_row(15 downto 8), |
out_q1 => from_second_row(15 downto 8) |
); |
second_q0_2: q0 |
port map ( |
in_q0 => to_second_row(23 downto 16), |
out_q0 => from_second_row(23 downto 16) |
); |
second_q1_2: q1 |
port map ( |
in_q1 => to_second_row(31 downto 24), |
out_q1 => from_second_row(31 downto 24) |
); |
|
-- we perform the XOR |
to_third_row <= from_second_row XOR in_S1_g192; |
|
-- third row of q |
third_q0_1: q0 |
port map ( |
in_q0 => to_third_row(7 downto 0), |
out_q0 => from_third_row(7 downto 0) |
); |
third_q0_2: q0 |
port map ( |
in_q0 => to_third_row(15 downto 8), |
out_q0 => from_third_row(15 downto 8) |
); |
third_q1_1: q1 |
port map ( |
in_q1 => to_third_row(23 downto 16), |
out_q1 => from_third_row(23 downto 16) |
); |
third_q1_2: q1 |
port map ( |
in_q1 => to_third_row(31 downto 24), |
out_q1 => from_third_row(31 downto 24) |
); |
|
-- we perform the XOR |
to_fourth_row <= from_third_row XOR in_S2_g192; |
|
-- fourth row of q |
fourth_q1_1: q1 |
port map ( |
in_q1=> to_fourth_row(7 downto 0), |
out_q1 => to_mds(7 downto 0) |
); |
fourth_q0_1: q0 |
port map ( |
in_q0 => to_fourth_row(15 downto 8), |
out_q0 => to_mds(15 downto 8) |
); |
fourth_q1_2: q1 |
port map ( |
in_q1 => to_fourth_row(23 downto 16), |
out_q1 => to_mds(23 downto 16) |
); |
fourth_q0_2: q0 |
port map ( |
in_q0 => to_fourth_row(31 downto 24), |
out_q0 => to_mds(31 downto 24) |
); |
|
-- mds table |
mds_table: mds |
port map ( |
y0 => to_mds(7 downto 0), |
y1 => to_mds(15 downto 8), |
y2 => to_mds(23 downto 16), |
y3 => to_mds(31 downto 24), |
z0 => out_g192(7 downto 0), |
z1 => out_g192(15 downto 8), |
z2 => out_g192(23 downto 16), |
z3 => out_g192(31 downto 24) |
); |
|
end g192_arch; |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
|
-- |
-- f function with 192 bits key |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity f_192 is |
port ( |
up_in_f192, |
low_in_f192, |
S0_in_f192, |
S1_in_f192, |
S2_in_f192, |
up_key_f192, |
low_key_f192 : in std_logic_vector(31 downto 0); |
up_out_f192, |
low_out_f192 : out std_logic_vector(31 downto 0) |
); |
end f_192; |
|
architecture f192_arch of f_192 is |
|
-- we declare the internal signals |
signal from_shift_8, |
to_up_pht, |
to_low_pht, |
to_up_key, |
to_low_key, |
intermediate_carry1, |
intermediate_carry2 : std_logic_vector(31 downto 0); |
signal zero : std_logic; |
|
|
component g_192 |
port ( |
in_g192, |
in_S0_g192, |
in_S1_g192, |
in_S2_g192 : in std_logic_vector(31 downto 0); |
out_g192 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component pht |
port ( |
up_in_pht, |
down_in_pht : in std_logic_vector(31 downto 0); |
up_out_pht, |
down_out_pht : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component adder |
port ( |
in1_adder, |
in2_adder, |
in_carry_adder : in std_logic; |
out_adder, |
out_carry_adder : out std_logic |
); |
end component; |
|
-- begin architecture description |
begin |
|
-- we initialize zero |
zero <= '0'; |
|
-- upper g_192 |
upper_g192: g_192 |
port map ( |
in_g192 => up_in_f192, |
in_S0_g192 => S0_in_f192, |
in_S1_g192 => S1_in_f192, |
in_S2_g192 => S2_in_f192, |
out_g192 => to_up_pht |
); |
|
-- left rotation by 8 |
from_shift_8(31 downto 8) <= low_in_f192(23 downto 0); |
from_shift_8(7 downto 0) <= low_in_f192(31 downto 24); |
|
-- lower g192 |
lower_g192: g_192 |
port map ( |
in_g192 => from_shift_8, |
in_S0_g192 => S0_in_f192, |
in_S1_g192 => S1_in_f192, |
in_S2_g192 => S2_in_f192, |
out_g192 => to_low_pht |
); |
|
-- pht |
pht_transform: pht |
port map ( |
up_in_pht => to_up_pht, |
down_in_pht => to_low_pht, |
up_out_pht => to_up_key, |
down_out_pht => to_low_key |
); |
|
-- upper adder of 32 bits |
up_adder: for i in 0 to 31 generate |
first: if (i=0) generate |
the_adder: adder |
port map ( |
in1_adder => to_up_key(0), |
in2_adder => up_key_f192(0), |
in_carry_adder => zero, |
out_adder => up_out_f192(0), |
out_carry_adder => intermediate_carry1(0) |
); |
end generate first; |
the_rest: if (i>0) generate |
the_adders: adder |
port map ( |
in1_adder => to_up_key(i), |
in2_adder => up_key_f192(i), |
in_carry_adder => intermediate_carry1(i-1), |
out_adder => up_out_f192(i), |
out_carry_adder => intermediate_carry1(i) |
); |
end generate the_rest; |
end generate up_adder; |
|
-- lower adder of 32 bits |
low_adder: for i in 0 to 31 generate |
first1: if (i=0) generate |
the_adder1:adder |
port map ( |
in1_adder => to_low_key(0), |
in2_adder => low_key_f192(0), |
in_carry_adder => zero, |
out_adder => low_out_f192(0), |
out_carry_adder => intermediate_carry2(0) |
); |
end generate first1; |
the_rest1: if (i>0) generate |
the_adders1: adder |
port map ( |
in1_adder => to_low_key(i), |
in2_adder => low_key_f192(i), |
in_carry_adder => intermediate_carry2(i-1), |
out_adder => low_out_f192(i), |
out_carry_adder => intermediate_carry2(i) |
); |
end generate the_rest1; |
end generate low_adder; |
|
end f192_arch; |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
-- |
-- twofish key scheduler for 192 bits key input |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity twofish_keysched192 is |
port ( |
odd_in_tk192, |
even_in_tk192 : in std_logic_vector(7 downto 0); |
in_key_tk192 : in std_logic_vector(191 downto 0); |
out_key_up_tk192, |
out_key_down_tk192 : out std_logic_vector(31 downto 0) |
); |
end twofish_keysched192; |
|
architecture twofish_keysched192_arch of twofish_keysched192 is |
|
-- we declare internal signals |
signal to_up_pht, |
to_shift_8, |
from_shift_8, |
to_shift_9, |
M0, M1, M2, M3, M4, M5 : std_logic_vector(31 downto 0); |
|
signal byte0, byte1, byte2, byte3, |
byte4, byte5, byte6, byte7, |
byte8, byte9, byte10, byte11, |
byte12, byte13, byte14, byte15, |
byte16, byte17, byte18, byte19, |
byte20, byte21, byte22, byte23 : std_logic_vector(7 downto 0); |
|
-- we declare the components to be used |
component pht |
port ( |
up_in_pht, |
down_in_pht : in std_logic_vector(31 downto 0); |
up_out_pht, |
down_out_pht : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component h_192 |
port ( |
in_h192 : in std_logic_vector(7 downto 0); |
Mfirst_h192, |
Msecond_h192, |
Mthird_h192 : in std_logic_vector(31 downto 0); |
out_h192 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
-- begin architecture description |
begin |
|
-- we assign the input signal to the respective |
-- bytes as is described in the prototype |
byte23 <= in_key_tk192(7 downto 0); |
byte22 <= in_key_tk192(15 downto 8); |
byte21 <= in_key_tk192(23 downto 16); |
byte20 <= in_key_tk192(31 downto 24); |
byte19 <= in_key_tk192(39 downto 32); |
byte18 <= in_key_tk192(47 downto 40); |
byte17 <= in_key_tk192(55 downto 48); |
byte16 <= in_key_tk192(63 downto 56); |
byte15 <= in_key_tk192(71 downto 64); |
byte14 <= in_key_tk192(79 downto 72); |
byte13 <= in_key_tk192(87 downto 80); |
byte12 <= in_key_tk192(95 downto 88); |
byte11 <= in_key_tk192(103 downto 96); |
byte10 <= in_key_tk192(111 downto 104); |
byte9 <= in_key_tk192(119 downto 112); |
byte8 <= in_key_tk192(127 downto 120); |
byte7 <= in_key_tk192(135 downto 128); |
byte6 <= in_key_tk192(143 downto 136); |
byte5 <= in_key_tk192(151 downto 144); |
byte4 <= in_key_tk192(159 downto 152); |
byte3 <= in_key_tk192(167 downto 160); |
byte2 <= in_key_tk192(175 downto 168); |
byte1 <= in_key_tk192(183 downto 176); |
byte0 <= in_key_tk192(191 downto 184); |
|
-- we form the M{0..5} |
M0 <= byte3 & byte2 & byte1 & byte0; |
M1 <= byte7 & byte6 & byte5 & byte4; |
M2 <= byte11 & byte10 & byte9 & byte8; |
M3 <= byte15 & byte14 & byte13 & byte12; |
M4 <= byte19 & byte18 & byte17 & byte16; |
M5 <= byte23 & byte22 & byte21 & byte20; |
|
-- upper h |
upper_h: h_192 |
port map ( |
in_h192 => even_in_tk192, |
Mfirst_h192 => M4, |
Msecond_h192 => M2, |
Mthird_h192 => M0, |
out_h192 => to_up_pht |
); |
|
-- lower h |
lower_h: h_192 |
port map ( |
in_h192 => odd_in_tk192, |
Mfirst_h192 => M5, |
Msecond_h192 => M3, |
Mthird_h192 => M1, |
out_h192 => to_shift_8 |
); |
|
-- left rotate by 8 |
from_shift_8(31 downto 8) <= to_shift_8(23 downto 0); |
from_shift_8(7 downto 0) <= to_shift_8(31 downto 24); |
|
-- pht transformation |
pht_transform: pht |
port map ( |
up_in_pht => to_up_pht, |
down_in_pht => from_shift_8, |
up_out_pht => out_key_up_tk192, |
down_out_pht => to_shift_9 |
); |
|
-- left rotate by 9 |
out_key_down_tk192(31 downto 9) <= to_shift_9(22 downto 0); |
out_key_down_tk192(8 downto 0) <= to_shift_9(31 downto 23); |
|
end twofish_keysched192_arch; |
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
-- |
-- twofish S key component for 192 bits key |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity twofish_S192 is |
port ( |
in_key_ts192 : in std_logic_vector(191 downto 0); |
out_Sfirst_ts192, |
out_Ssecond_ts192, |
out_Sthird_ts192 : out std_logic_vector(31 downto 0) |
); |
end twofish_S192; |
|
architecture twofish_S192_arch of twofish_S192 is |
|
-- we declare the components to be used |
component reed_solomon192 |
port ( |
in_rs192 : in std_logic_vector(191 downto 0); |
out_Sfirst_rs192, |
out_Ssecond_rs192, |
out_Sthird_rs192 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
signal twofish_key : std_logic_vector(191 downto 0); |
signal byte15, byte14, byte13, byte12, byte11, byte10, |
byte9, byte8, byte7, byte6, byte5, byte4, |
byte3, byte2, byte1, byte0, |
byte16, byte17, byte18, byte19, |
byte20, byte21, byte22, byte23 : std_logic_vector(7 downto 0); |
|
-- begin architecture description |
begin |
|
-- splitting the input |
byte23 <= in_key_ts192(7 downto 0); |
byte22 <= in_key_ts192(15 downto 8); |
byte21 <= in_key_ts192(23 downto 16); |
byte20 <= in_key_ts192(31 downto 24); |
byte19 <= in_key_ts192(39 downto 32); |
byte18 <= in_key_ts192(47 downto 40); |
byte17 <= in_key_ts192(55 downto 48); |
byte16 <= in_key_ts192(63 downto 56); |
byte15 <= in_key_ts192(71 downto 64); |
byte14 <= in_key_ts192(79 downto 72); |
byte13 <= in_key_ts192(87 downto 80); |
byte12 <= in_key_ts192(95 downto 88); |
byte11 <= in_key_ts192(103 downto 96); |
byte10 <= in_key_ts192(111 downto 104); |
byte9 <= in_key_ts192(119 downto 112); |
byte8 <= in_key_ts192(127 downto 120); |
byte7 <= in_key_ts192(135 downto 128); |
byte6 <= in_key_ts192(143 downto 136); |
byte5 <= in_key_ts192(151 downto 144); |
byte4 <= in_key_ts192(159 downto 152); |
byte3 <= in_key_ts192(167 downto 160); |
byte2 <= in_key_ts192(175 downto 168); |
byte1 <= in_key_ts192(183 downto 176); |
byte0 <= in_key_ts192(191 downto 184); |
|
-- forming the key |
twofish_key <= byte23 & byte22 & byte21 & byte20 & byte19 & byte18 & byte17 & byte16 & |
byte15 & byte14 & byte13 & byte12 & byte11 & byte10 & byte9 & byte8 & byte7 & |
byte6 & byte5 & byte4 & byte3 & byte2 & byte1 & byte0; |
|
|
-- the keys S0,1,2 |
produce_S0_S1_S2: reed_solomon192 |
port map ( |
in_rs192 => twofish_key, |
out_Sfirst_rs192 => out_Sfirst_ts192, |
out_Ssecond_rs192 => out_Ssecond_ts192, |
out_Sthird_rs192 => out_Sthird_ts192 |
); |
|
|
end twofish_S192_arch; |
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
-- |
-- twofish whitening key scheduler for 192 bits key input |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity twofish_whit_keysched192 is |
port ( |
in_key_twk192 : in std_logic_vector(191 downto 0); |
out_K0_twk192, |
out_K1_twk192, |
out_K2_twk192, |
out_K3_twk192, |
out_K4_twk192, |
out_K5_twk192, |
out_K6_twk192, |
out_K7_twk192 : out std_logic_vector(31 downto 0) |
); |
end twofish_whit_keysched192; |
|
architecture twofish_whit_keysched192_arch of twofish_whit_keysched192 is |
|
-- we declare internal signals |
signal to_up_pht_1, |
to_shift_8_1, |
from_shift_8_1, |
to_shift_9_1, |
to_up_pht_2, |
to_shift_8_2, |
from_shift_8_2, |
to_shift_9_2, |
to_up_pht_3, |
to_shift_8_3, |
from_shift_8_3, |
to_shift_9_3, |
to_up_pht_4, |
to_shift_8_4, |
from_shift_8_4, |
to_shift_9_4, |
M0, M1, M2, M3, M4, M5 : std_logic_vector(31 downto 0); |
|
signal byte0, byte1, byte2, byte3, |
byte4, byte5, byte6, byte7, |
byte8, byte9, byte10, byte11, |
byte12, byte13, byte14, byte15, |
byte16, byte17, byte18, byte19, |
byte20, byte21, byte22, byte23 : std_logic_vector(7 downto 0); |
|
signal zero, one, two, three, four, five, six, seven : std_logic_vector(7 downto 0); |
|
-- we declare the components to be used |
component pht |
port ( |
up_in_pht, |
down_in_pht : in std_logic_vector(31 downto 0); |
up_out_pht, |
down_out_pht : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component h_192 |
port ( |
in_h192 : in std_logic_vector(7 downto 0); |
Mfirst_h192, |
Msecond_h192, |
Mthird_h192 : in std_logic_vector(31 downto 0); |
out_h192 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
-- begin architecture description |
begin |
|
-- we produce the first eight numbers |
zero <= "00000000"; |
one <= "00000001"; |
two <= "00000010"; |
three <= "00000011"; |
four <= "00000100"; |
five <= "00000101"; |
six <= "00000110"; |
seven <= "00000111"; |
|
-- we assign the input signal to the respective |
-- bytes as is described in the prototype |
byte23 <= in_key_twk192(7 downto 0); |
byte22 <= in_key_twk192(15 downto 8); |
byte21 <= in_key_twk192(23 downto 16); |
byte20 <= in_key_twk192(31 downto 24); |
byte19 <= in_key_twk192(39 downto 32); |
byte18 <= in_key_twk192(47 downto 40); |
byte17 <= in_key_twk192(55 downto 48); |
byte16 <= in_key_twk192(63 downto 56); |
byte15 <= in_key_twk192(71 downto 64); |
byte14 <= in_key_twk192(79 downto 72); |
byte13 <= in_key_twk192(87 downto 80); |
byte12 <= in_key_twk192(95 downto 88); |
byte11 <= in_key_twk192(103 downto 96); |
byte10 <= in_key_twk192(111 downto 104); |
byte9 <= in_key_twk192(119 downto 112); |
byte8 <= in_key_twk192(127 downto 120); |
byte7 <= in_key_twk192(135 downto 128); |
byte6 <= in_key_twk192(143 downto 136); |
byte5 <= in_key_twk192(151 downto 144); |
byte4 <= in_key_twk192(159 downto 152); |
byte3 <= in_key_twk192(167 downto 160); |
byte2 <= in_key_twk192(175 downto 168); |
byte1 <= in_key_twk192(183 downto 176); |
byte0 <= in_key_twk192(191 downto 184); |
|
-- we form the M{0..5} |
M0 <= byte3 & byte2 & byte1 & byte0; |
M1 <= byte7 & byte6 & byte5 & byte4; |
M2 <= byte11 & byte10 & byte9 & byte8; |
M3 <= byte15 & byte14 & byte13 & byte12; |
M4 <= byte19 & byte18 & byte17 & byte16; |
M5 <= byte23 & byte22 & byte21 & byte20; |
|
-- we produce the keys for the whitening steps |
-- keys K0,1 |
-- upper h |
upper_h1: h_192 |
port map ( |
in_h192 => zero, |
Mfirst_h192 => M4, |
Msecond_h192 => M2, |
Mthird_h192 => M0, |
out_h192 => to_up_pht_1 |
); |
|
-- lower h |
lower_h1: h_192 |
port map ( |
in_h192 => one, |
Mfirst_h192 => M5, |
Msecond_h192 => M3, |
Mthird_h192 => M1, |
out_h192 => to_shift_8_1 |
); |
|
-- left rotate by 8 |
from_shift_8_1(31 downto 8) <= to_shift_8_1(23 downto 0); |
from_shift_8_1(7 downto 0) <= to_shift_8_1(31 downto 24); |
|
-- pht transformation |
pht_transform1: pht |
port map ( |
up_in_pht => to_up_pht_1, |
down_in_pht => from_shift_8_1, |
up_out_pht => out_K0_twk192, |
down_out_pht => to_shift_9_1 |
); |
|
-- left rotate by 9 |
out_K1_twk192(31 downto 9) <= to_shift_9_1(22 downto 0); |
out_K1_twk192(8 downto 0) <= to_shift_9_1(31 downto 23); |
|
-- keys K2,3 |
-- upper h |
upper_h2: h_192 |
port map ( |
in_h192 => two, |
Mfirst_h192 => M4, |
Msecond_h192 => M2, |
Mthird_h192 => M0, |
out_h192 => to_up_pht_2 |
); |
|
-- lower h |
lower_h2: h_192 |
port map ( |
in_h192 => three, |
Mfirst_h192 => M5, |
Msecond_h192 => M3, |
Mthird_h192 => M1, |
out_h192 => to_shift_8_2 |
); |
|
-- left rotate by 8 |
from_shift_8_2(31 downto 8) <= to_shift_8_2(23 downto 0); |
from_shift_8_2(7 downto 0) <= to_shift_8_2(31 downto 24); |
|
-- pht transformation |
pht_transform2: pht |
port map ( |
up_in_pht => to_up_pht_2, |
down_in_pht => from_shift_8_2, |
up_out_pht => out_K2_twk192, |
down_out_pht => to_shift_9_2 |
); |
|
-- left rotate by 9 |
out_K3_twk192(31 downto 9) <= to_shift_9_2(22 downto 0); |
out_K3_twk192(8 downto 0) <= to_shift_9_2(31 downto 23); |
|
-- keys K4,5 |
-- upper h |
upper_h3: h_192 |
port map ( |
in_h192 => four, |
Mfirst_h192 => M4, |
Msecond_h192 => M2, |
Mthird_h192 => M0, |
out_h192 => to_up_pht_3 |
); |
|
-- lower h |
lower_h3: h_192 |
port map ( |
in_h192 => five, |
Mfirst_h192 => M5, |
Msecond_h192 => M3, |
Mthird_h192 => M1, |
out_h192 => to_shift_8_3 |
); |
|
-- left rotate by 8 |
from_shift_8_3(31 downto 8) <= to_shift_8_3(23 downto 0); |
from_shift_8_3(7 downto 0) <= to_shift_8_3(31 downto 24); |
|
-- pht transformation |
pht_transform3: pht |
port map ( |
up_in_pht => to_up_pht_3, |
down_in_pht => from_shift_8_3, |
up_out_pht => out_K4_twk192, |
down_out_pht => to_shift_9_3 |
); |
|
-- left rotate by 9 |
out_K5_twk192(31 downto 9) <= to_shift_9_3(22 downto 0); |
out_K5_twk192(8 downto 0) <= to_shift_9_3(31 downto 23); |
|
-- keys K6,7 |
-- upper h |
upper_h4: h_192 |
port map ( |
in_h192 => six, |
Mfirst_h192 => M4, |
Msecond_h192 => M2, |
Mthird_h192 => M0, |
out_h192 => to_up_pht_4 |
); |
|
-- lower h |
lower_h4: h_192 |
port map ( |
in_h192 => seven, |
Mfirst_h192 => M5, |
Msecond_h192 => M3, |
Mthird_h192 => M1, |
out_h192 => to_shift_8_4 |
); |
|
-- left rotate by 8 |
from_shift_8_4(31 downto 8) <= to_shift_8_4(23 downto 0); |
from_shift_8_4(7 downto 0) <= to_shift_8_4(31 downto 24); |
|
-- pht transformation |
pht_transform4: pht |
port map ( |
up_in_pht => to_up_pht_4, |
down_in_pht => from_shift_8_4, |
up_out_pht => out_K6_twk192, |
down_out_pht => to_shift_9_4 |
); |
|
-- left rotate by 9 |
out_K7_twk192(31 downto 9) <= to_shift_9_4(22 downto 0); |
out_K7_twk192(8 downto 0) <= to_shift_9_4(31 downto 23); |
|
end twofish_whit_keysched192_arch; |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
-- |
-- twofish encryption round with 128 bit key input |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity twofish_encryption_round192 is |
port ( |
in1_ter192, |
in2_ter192, |
in3_ter192, |
in4_ter192, |
in_Sfirst_ter192, |
in_Ssecond_ter192, |
in_Sthird_ter192, |
in_key_up_ter192, |
in_key_down_ter192 : in std_logic_vector(31 downto 0); |
out1_ter192, |
out2_ter192, |
out3_ter192, |
out4_ter192 : out std_logic_vector(31 downto 0) |
); |
end twofish_encryption_round192; |
|
architecture twofish_encryption_round192_arch of twofish_encryption_round192 is |
|
-- we declare internal signals |
signal to_left_shift, |
from_right_shift, |
to_xor_with3, |
to_xor_with4 : std_logic_vector(31 downto 0); |
|
component f_192 |
port ( |
up_in_f192, |
low_in_f192, |
S0_in_f192, |
S1_in_f192, |
S2_in_f192, |
up_key_f192, |
low_key_f192 : in std_logic_vector(31 downto 0); |
up_out_f192, |
low_out_f192 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
-- begin architecture description |
begin |
|
-- we declare f_192 |
function_f: f_192 |
port map ( |
up_in_f192 => in1_ter192, |
low_in_f192 => in2_ter192, |
S0_in_f192 => in_Sfirst_ter192, |
S1_in_f192 => in_Ssecond_ter192, |
S2_in_f192 => in_Sthird_ter192, |
up_key_f192 => in_key_up_ter192, |
low_key_f192 => in_key_down_ter192, |
up_out_f192 => to_xor_with3, |
low_out_f192 => to_xor_with4 |
); |
|
-- we perform the exchange |
-- in1_ter128 -> out3_ter128 |
-- in2_ter128 -> out4_ter128 |
-- in3_ter128 -> out1_ter128 |
-- in4_ter128 -> out2_ter128 |
|
-- we perform the left xor between the upper f function and |
-- the third input (input 3) |
to_left_shift <= to_xor_with3 XOR in3_ter192; |
|
-- we perform the left side rotation to the right by 1 and |
-- we perform the exchange too |
out1_ter192(30 downto 0) <= to_left_shift(31 downto 1); |
out1_ter192(31) <= to_left_shift(0); |
|
-- we perform the right side rotation to the left by 1 |
from_right_shift(0) <= in4_ter192(31); |
from_right_shift(31 downto 1) <= in4_ter192(30 downto 0); |
|
-- we perform the right xor between the lower f function and |
-- the fourth input (input 4) |
out2_ter192 <= from_right_shift XOR to_xor_with4; |
|
-- we perform the last exchanges |
out3_ter192 <= in1_ter192; |
out4_ter192 <= in2_ter192; |
|
end twofish_encryption_round192_arch; |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
-- |
-- twofish decryption round with 128 bit key input |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity twofish_decryption_round192 is |
port ( |
in1_tdr192, |
in2_tdr192, |
in3_tdr192, |
in4_tdr192, |
in_Sfirst_tdr192, |
in_Ssecond_tdr192, |
in_Sthird_tdr192, |
in_key_up_tdr192, |
in_key_down_tdr192 : in std_logic_vector(31 downto 0); |
out1_tdr192, |
out2_tdr192, |
out3_tdr192, |
out4_tdr192 : out std_logic_vector(31 downto 0) |
); |
end twofish_decryption_round192; |
|
architecture twofish_decryption_round192_arch of twofish_decryption_round192 is |
|
signal to_xor_with3, |
to_xor_with4, |
to_xor_with_up_f, |
from_xor_with_down_f : std_logic_vector(31 downto 0); |
|
component f_192 |
port ( |
up_in_f192, |
low_in_f192, |
S0_in_f192, |
S1_in_f192, |
S2_in_f192, |
up_key_f192, |
low_key_f192 : in std_logic_vector(31 downto 0); |
up_out_f192, |
low_out_f192 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
begin |
|
-- we instantiate f function |
function_f: f_192 |
port map ( |
up_in_f192 => in1_tdr192, |
low_in_f192 => in2_tdr192, |
S0_in_f192 => in_Sfirst_tdr192, |
S1_in_f192 => in_Ssecond_tdr192, |
S2_in_f192 => in_Sthird_tdr192, |
up_key_f192 => in_key_up_tdr192, |
low_key_f192 => in_key_down_tdr192, |
up_out_f192 => to_xor_with3, |
low_out_f192 => to_xor_with4 |
); |
|
-- output 1: input3 with upper f |
-- we first rotate the input3 by 1 bit leftwise |
to_xor_with_up_f(0) <= in3_tdr192(31); |
to_xor_with_up_f(31 downto 1) <= in3_tdr192(30 downto 0); |
|
-- we perform the XOR with the upper output of f and the result |
-- is ouput 1 |
out1_tdr192 <= to_xor_with_up_f XOR to_xor_with3; |
|
-- output 2: input4 with lower f |
-- we perform the XOR with the lower output of f |
from_xor_with_down_f <= in4_tdr192 XOR to_xor_with4; |
|
-- we perform the rotation by 1 bit rightwise and the result |
-- is output2 |
out2_tdr192(31) <= from_xor_with_down_f(0); |
out2_tdr192(30 downto 0) <= from_xor_with_down_f(31 downto 1); |
|
-- we assign outputs 3 and 4 |
out3_tdr192 <= in1_tdr192; |
out4_tdr192 <= in2_tdr192; |
|
end twofish_decryption_round192_arch; |
|
|
-- =============================================== -- |
-- =============================================== -- |
-- -- |
-- fourth part: 256 key input dependent components -- |
-- -- |
-- =============================================== -- |
-- =============================================== -- |
/trunk/vhdl/twofish_testbenches_secondary_circuits.vhd
0,0 → 1,115
-- Twofish_testbenches_secondary_circuits.vhd |
-- Copyright (C) 2006 Spyros Ninos |
-- |
-- This program is free software; you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation; either version 2 of the License, or |
-- (at your option) any later version. |
-- |
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU General Public License |
-- along with this library; see the file COPYING. If not, write to: |
-- |
-- Free Software Foundation |
-- 59 Temple Place - Suite 330 |
-- Boston, MA 02111-1307, USA. |
-- |
-- description : this file contains all the secondary circuits that are needed for running the testbenches |
-- |
|
|
-- |
-- reg128 |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity reg128 is |
port ( in_reg128 : in std_logic_vector(127 downto 0); |
out_reg128 : out std_logic_vector(127 downto 0); |
enable_reg128, reset_reg128,clk_reg128 : in std_logic |
); |
end reg128; |
|
architecture reg128_arch of reg128 is |
begin |
clk_proc: process(clk_reg128, reset_reg128,enable_reg128) |
variable internal_state : std_logic_vector(127 downto 0); |
begin |
if reset_reg128 = '1' then |
internal_state := ( others => '0' ); |
elsif (clk_reg128'event and clk_reg128 = '1') then |
if enable_reg128='1' then |
internal_state := in_reg128; |
else |
internal_state := internal_state; |
end if; |
end if; |
out_reg128 <= internal_state; |
end process clk_proc; |
end reg128_arch; |
|
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
-- |
-- mux128 |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity mux128 is |
port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0); |
selection_mux128 : in std_logic; |
out_mux128 : out std_logic_vector(127 downto 0) |
); |
end mux128; |
|
architecture mux128_arch of mux128 is |
begin |
with selection_mux128 select |
out_mux128 <= in1_mux128 when '0', |
in2_mux128 when others; |
end mux128_arch; |
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
-- -- |
-- new component -- |
-- -- |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- |
|
-- |
-- demux128 |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
entity demux128 is |
port ( in_demux128 : in std_logic_vector(127 downto 0); |
out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0); |
selection_demux128 : in std_logic |
); |
end demux128; |
|
architecture demux128_arch of demux128 is |
begin |
demux_proc: process(in_demux128, selection_demux128) |
begin |
if selection_demux128 = '0' then |
out1_demux128 <= in_demux128; |
else |
out2_demux128 <= in_demux128; |
end if; |
end process demux_proc; |
end demux128_arch; |
/trunk/vhdl/twofish_cbc_decryption_monte_carlo_testbench_128bits.vhd
0,0 → 1,406
-- Twofish_cbc_decryption_monte_carlo_testbench_128bits.vhd |
-- Copyright (C) 2006 Spyros Ninos |
-- |
-- This program is free software; you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation; either version 2 of the License, or |
-- (at your option) any later version. |
-- |
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU General Public License |
-- along with this library; see the file COPYING. If not, write to: |
-- |
-- Free Software Foundation |
-- 59 Temple Place - Suite 330 |
-- Boston, MA 02111-1307, USA. |
-- |
-- description : this file is the testbench for the Decryption Monte Carlo KAT of the twofish cipher with 128 bit key |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
use ieee.std_logic_textio.all; |
use ieee.std_logic_arith.all; |
use std.textio.all; |
|
entity cbc_decryption_monte_carlo_testbench128 is |
end cbc_decryption_monte_carlo_testbench128; |
|
architecture cbc_decryption128_monte_carlo_testbench_arch of cbc_decryption_monte_carlo_testbench128 is |
|
component reg128 |
port ( |
in_reg128 : in std_logic_vector(127 downto 0); |
out_reg128 : out std_logic_vector(127 downto 0); |
enable_reg128, reset_reg128, clk_reg128 : in std_logic |
); |
end component; |
|
component twofish_keysched128 |
port ( |
odd_in_tk128, |
even_in_tk128 : in std_logic_vector(7 downto 0); |
in_key_tk128 : in std_logic_vector(127 downto 0); |
out_key_up_tk128, |
out_key_down_tk128 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component twofish_whit_keysched128 |
port ( |
in_key_twk128 : in std_logic_vector(127 downto 0); |
out_K0_twk128, |
out_K1_twk128, |
out_K2_twk128, |
out_K3_twk128, |
out_K4_twk128, |
out_K5_twk128, |
out_K6_twk128, |
out_K7_twk128 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component twofish_decryption_round128 |
port ( |
in1_tdr128, |
in2_tdr128, |
in3_tdr128, |
in4_tdr128, |
in_Sfirst_tdr128, |
in_Ssecond_tdr128, |
in_key_up_tdr128, |
in_key_down_tdr128 : in std_logic_vector(31 downto 0); |
out1_tdr128, |
out2_tdr128, |
out3_tdr128, |
out4_tdr128 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component twofish_data_input |
port ( |
in_tdi : in std_logic_vector(127 downto 0); |
out_tdi : out std_logic_vector(127 downto 0) |
); |
end component; |
|
component twofish_data_output |
port ( |
in_tdo : in std_logic_vector(127 downto 0); |
out_tdo : out std_logic_vector(127 downto 0) |
); |
end component; |
|
component demux128 |
port ( in_demux128 : in std_logic_vector(127 downto 0); |
out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0); |
selection_demux128 : in std_logic |
); |
end component; |
|
component mux128 |
port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0); |
selection_mux128 : in std_logic; |
out_mux128 : out std_logic_vector(127 downto 0) |
); |
end component; |
|
component twofish_S128 |
port ( |
in_key_ts128 : in std_logic_vector(127 downto 0); |
out_Sfirst_ts128, |
out_Ssecond_ts128 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
FILE input_file : text is in "twofish_cbc_decryption_monte_carlo_testvalues_128bits.txt"; |
FILE output_file : text is out "twofish_cbc_decryption_monte_carlo_128bits_results.txt"; |
|
-- we create the functions that transform a number to text |
-- transforming a signle digit to a character |
function digit_to_char(number : integer range 0 to 9) return character is |
begin |
case number is |
when 0 => return '0'; |
when 1 => return '1'; |
when 2 => return '2'; |
when 3 => return '3'; |
when 4 => return '4'; |
when 5 => return '5'; |
when 6 => return '6'; |
when 7 => return '7'; |
when 8 => return '8'; |
when 9 => return '9'; |
end case; |
end; |
|
-- transforming multi-digit number to text |
function to_text(int_number : integer range 0 to 9999) return string is |
variable our_text : string (1 to 4) := (others => ' '); |
variable thousands, |
hundreds, |
tens, |
ones : integer range 0 to 9; |
begin |
ones := int_number mod 10; |
tens := ((int_number mod 100) - ones) / 10; |
hundreds := ((int_number mod 1000) - (int_number mod 100)) / 100; |
thousands := (int_number - (int_number mod 1000)) / 1000; |
our_text(1) := digit_to_char(thousands); |
our_text(2) := digit_to_char(hundreds); |
our_text(3) := digit_to_char(tens); |
our_text(4) := digit_to_char(ones); |
return our_text; |
end; |
|
signal odd_number, |
even_number : std_logic_vector(7 downto 0); |
|
signal input_data, |
output_data, |
twofish_key, |
to_encr_reg128, |
from_tdi_to_xors, |
to_output_whit_xors, |
from_xors_to_tdo, |
to_mux, to_demux, |
from_input_whit_xors, |
to_round, |
to_input_mux : std_logic_vector(127 downto 0) ; |
|
signal key_up, |
key_down, |
Sfirst, |
Ssecond, |
from_xor0, |
from_xor1, |
from_xor2, |
from_xor3, |
K0,K1,K2,K3, |
K4,K5,K6,K7 : std_logic_vector(31 downto 0); |
|
signal clk : std_logic := '0'; |
signal mux_selection : std_logic := '0'; |
signal demux_selection: std_logic := '0'; |
signal enable_encr_reg : std_logic := '0'; |
signal reset : std_logic := '0'; |
signal enable_round_reg : std_logic := '0'; |
|
-- begin the testbench arch description |
begin |
|
|
-- getting data to encrypt |
data_input: twofish_data_input |
port map ( |
in_tdi => input_data, |
out_tdi => from_tdi_to_xors |
); |
|
-- producing whitening keys K0..7 |
the_whitening_step: twofish_whit_keysched128 |
port map ( |
in_key_twk128 => twofish_key, |
out_K0_twk128 => K0, |
out_K1_twk128 => K1, |
out_K2_twk128 => K2, |
out_K3_twk128 => K3, |
out_K4_twk128 => K4, |
out_K5_twk128 => K5, |
out_K6_twk128 => K6, |
out_K7_twk128 => K7 |
); |
|
-- performing the input whitening XORs |
from_xor0 <= K4 XOR from_tdi_to_xors(127 downto 96); |
from_xor1 <= K5 XOR from_tdi_to_xors(95 downto 64); |
from_xor2 <= K6 XOR from_tdi_to_xors(63 downto 32); |
from_xor3 <= K7 XOR from_tdi_to_xors(31 downto 0); |
|
from_input_whit_xors <= from_xor0 & from_xor1 & from_xor2 & from_xor3; |
|
round_reg: reg128 |
port map ( in_reg128 => from_input_whit_xors, |
out_reg128 => to_input_mux, |
enable_reg128 => enable_round_reg, |
reset_reg128 => reset, |
clk_reg128 => clk ); |
|
input_mux: mux128 |
port map ( in1_mux128 => to_input_mux, |
in2_mux128 => to_mux, |
out_mux128 => to_round, |
selection_mux128 => mux_selection |
); |
|
|
-- creating a round |
the_keysched_of_the_round: twofish_keysched128 |
port map ( |
odd_in_tk128 => odd_number, |
even_in_tk128 => even_number, |
in_key_tk128 => twofish_key, |
out_key_up_tk128 => key_up, |
out_key_down_tk128 => key_down |
); |
|
producing_the_Skeys: twofish_S128 |
port map ( |
in_key_ts128 => twofish_key, |
out_Sfirst_ts128 => Sfirst, |
out_Ssecond_ts128 => Ssecond |
); |
|
the_decryption_circuit: twofish_decryption_round128 |
port map ( |
in1_tdr128 => to_round(127 downto 96), |
in2_tdr128 => to_round(95 downto 64), |
in3_tdr128 => to_round(63 downto 32), |
in4_tdr128 => to_round(31 downto 0), |
in_Sfirst_tdr128 => Sfirst, |
in_Ssecond_tdr128 => Ssecond, |
in_key_up_tdr128 => key_up, |
in_key_down_tdr128 => key_down, |
out1_tdr128 => to_encr_reg128(127 downto 96), |
out2_tdr128 => to_encr_reg128(95 downto 64), |
out3_tdr128 => to_encr_reg128(63 downto 32), |
out4_tdr128 => to_encr_reg128(31 downto 0) |
); |
|
encr_reg: reg128 |
port map ( in_reg128 => to_encr_reg128, |
out_reg128 => to_demux, |
enable_reg128 => enable_encr_reg, |
reset_reg128 => reset, |
clk_reg128 => clk ); |
|
output_demux: demux128 |
port map ( in_demux128 => to_demux, |
out1_demux128 => to_output_whit_xors, |
out2_demux128 => to_mux, |
selection_demux128 => demux_selection ); |
|
-- don't forget the last swap !!! |
from_xors_to_tdo(127 downto 96) <= K0 XOR to_output_whit_xors(63 downto 32); |
from_xors_to_tdo(95 downto 64) <= K1 XOR to_output_whit_xors(31 downto 0); |
from_xors_to_tdo(63 downto 32) <= K2 XOR to_output_whit_xors(127 downto 96); |
from_xors_to_tdo(31 downto 0) <= K3 XOR to_output_whit_xors(95 downto 64); |
|
taking_the_output: twofish_data_output |
port map ( |
in_tdo => from_xors_to_tdo, |
out_tdo => output_data |
); |
|
-- we create the clock |
clk <= not clk after 50 ns; -- period 100 ns |
|
|
cbc_dmc_proc: process |
|
variable key_f, -- key input from file |
pt_f, -- plaintext from file |
ct_f, |
iv_f : line; -- ciphertext from file |
variable key_v, -- key vector input |
pt_v , -- plaintext vector |
ct_v, |
iv_v : std_logic_vector(127 downto 0); -- ciphertext vector |
|
variable counter_10000 : integer range 0 to 9999 := 0; -- counter for the 10.000 repeats in the 400 next ones |
variable counter_400 : integer range 0 to 399 := 0; -- counter for the 400 repeats |
variable round : integer range 0 to 16 := 0; -- holds the rounds |
variable PT, CT, CV, CTj_1 : std_logic_vector(127 downto 0) := (others => '0'); |
|
begin |
|
while not endfile(input_file) loop |
|
readline(input_file, key_f); |
readline(input_file, iv_f); |
readline(input_file,ct_f); |
readline(input_file, pt_f); |
hread(key_f,key_v); |
hread(iv_f, iv_v); |
hread(ct_f,ct_v); |
hread(pt_f,pt_v); |
|
twofish_key <= key_v; |
CV := iv_v; |
CT := ct_v; |
|
for counter_10000 in 0 to 9999 loop |
|
input_data <= CT; |
|
wait for 25 ns; |
reset <= '1'; |
wait for 50 ns; |
reset <= '0'; |
|
mux_selection <= '0'; |
demux_selection <= '1'; |
enable_encr_reg <= '0'; |
enable_round_reg <= '0'; |
wait for 50 ns; |
enable_round_reg <= '1'; |
wait for 50 ns; |
enable_round_reg <= '0'; |
|
-- the first round |
even_number <= "00100110"; -- 38 |
odd_number <= "00100111"; -- 39 |
wait for 50 ns; |
enable_encr_reg <= '1'; |
wait for 50 ns; |
enable_encr_reg <= '0'; |
demux_selection <= '1'; |
mux_selection <= '1'; |
|
-- the rest 15 rounds |
for round in 1 to 15 loop |
even_number <= conv_std_logic_vector((((15-round)*2)+8), 8); |
odd_number <= conv_std_logic_vector((((15-round)*2)+9), 8); |
wait for 50 ns; |
enable_encr_reg <= '1'; |
wait for 50 ns; |
enable_encr_reg <= '0'; |
end loop; |
|
-- taking final results |
demux_selection <= '0'; |
wait for 25 ns; |
|
PT := output_data XOR CV; |
CV := CT; |
CT := PT; |
|
assert false report "I=" & to_text(counter_400) & " R=" & to_text(counter_10000) severity note; |
|
end loop; -- counter_10000 |
|
hwrite(key_f, key_v); |
hwrite(iv_f, iv_v); |
hwrite(ct_f, ct_v); |
hwrite(pt_f, PT); |
writeline(output_file,key_f); |
writeline(output_file, iv_f); |
writeline(output_file,ct_f); |
writeline(output_file,pt_f); |
|
assert (pt_v = PT) report "file entry and decryption result DO NOT match!!! :( " severity failure; |
assert (pt_v /= PT) report "Decryption I=" & to_text(counter_400) &" OK" severity note; |
|
counter_400 := counter_400 + 1; |
|
end loop; |
assert false report "***** CBC Decryption Monte Carlo Test with 128 bits key size ended succesfully! :) *****" severity failure; |
end process cbc_dmc_proc; |
|
end cbc_decryption128_monte_carlo_testbench_arch; |
|
/trunk/vhdl/twofish_cbc_decryption_monte_carlo_testbench_192bits.vhd
0,0 → 1,409
-- Twofish_cbc_decryption_monte_carlo_testbench_192bits.vhd |
-- Copyright (C) 2006 Spyros Ninos |
-- |
-- This program is free software; you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation; either version 2 of the License, or |
-- (at your option) any later version. |
-- |
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU General Public License |
-- along with this library; see the file COPYING. If not, write to: |
-- |
-- |
-- description : this file is the testbench for the Decryption Monte Carlo KAT of the twofish cipher with 192 bit key |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
use ieee.std_logic_textio.all; |
use ieee.std_logic_arith.all; |
use std.textio.all; |
|
entity cbc_decryption_monte_carlo_testbench192 is |
end cbc_decryption_monte_carlo_testbench192; |
|
architecture cbc_decryption192_monte_carlo_testbench_arch of cbc_decryption_monte_carlo_testbench192 is |
|
component reg128 |
port ( |
in_reg128 : in std_logic_vector(127 downto 0); |
out_reg128 : out std_logic_vector(127 downto 0); |
enable_reg128, reset_reg128, clk_reg128 : in std_logic |
); |
end component; |
|
component twofish_keysched192 |
port ( |
odd_in_tk192, |
even_in_tk192 : in std_logic_vector(7 downto 0); |
in_key_tk192 : in std_logic_vector(191 downto 0); |
out_key_up_tk192, |
out_key_down_tk192 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component twofish_whit_keysched192 |
port ( |
in_key_twk192 : in std_logic_vector(191 downto 0); |
out_K0_twk192, |
out_K1_twk192, |
out_K2_twk192, |
out_K3_twk192, |
out_K4_twk192, |
out_K5_twk192, |
out_K6_twk192, |
out_K7_twk192 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component twofish_decryption_round192 |
port ( |
in1_tdr192, |
in2_tdr192, |
in3_tdr192, |
in4_tdr192, |
in_Sfirst_tdr192, |
in_Ssecond_tdr192, |
in_Sthird_tdr192, |
in_key_up_tdr192, |
in_key_down_tdr192 : in std_logic_vector(31 downto 0); |
out1_tdr192, |
out2_tdr192, |
out3_tdr192, |
out4_tdr192 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component twofish_data_input |
port ( |
in_tdi : in std_logic_vector(127 downto 0); |
out_tdi : out std_logic_vector(127 downto 0) |
); |
end component; |
|
component twofish_data_output |
port ( |
in_tdo : in std_logic_vector(127 downto 0); |
out_tdo : out std_logic_vector(127 downto 0) |
); |
end component; |
|
component demux128 |
port ( in_demux128 : in std_logic_vector(127 downto 0); |
out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0); |
selection_demux128 : in std_logic |
); |
end component; |
|
component mux128 |
port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0); |
selection_mux128 : in std_logic; |
out_mux128 : out std_logic_vector(127 downto 0) |
); |
end component; |
|
component twofish_S192 |
port ( |
in_key_ts192 : in std_logic_vector(191 downto 0); |
out_Sfirst_ts192, |
out_Ssecond_ts192, |
out_Sthird_ts192 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
FILE input_file : text is in "twofish_cbc_decryption_monte_carlo_testvalues_192bits.txt"; |
FILE output_file : text is out "twofish_cbc_decryption_monte_carlo_192bits_results.txt"; |
|
-- we create the functions that transform a number to text |
-- transforming a signle digit to a character |
function digit_to_char(number : integer range 0 to 9) return character is |
begin |
case number is |
when 0 => return '0'; |
when 1 => return '1'; |
when 2 => return '2'; |
when 3 => return '3'; |
when 4 => return '4'; |
when 5 => return '5'; |
when 6 => return '6'; |
when 7 => return '7'; |
when 8 => return '8'; |
when 9 => return '9'; |
end case; |
end; |
|
-- transforming multi-digit number to text |
function to_text(int_number : integer range 0 to 9999) return string is |
variable our_text : string (1 to 4) := (others => ' '); |
variable thousands, |
hundreds, |
tens, |
ones : integer range 0 to 9; |
begin |
ones := int_number mod 10; |
tens := ((int_number mod 100) - ones) / 10; |
hundreds := ((int_number mod 1000) - (int_number mod 100)) / 100; |
thousands := (int_number - (int_number mod 1000)) / 1000; |
our_text(1) := digit_to_char(thousands); |
our_text(2) := digit_to_char(hundreds); |
our_text(3) := digit_to_char(tens); |
our_text(4) := digit_to_char(ones); |
return our_text; |
end; |
|
signal odd_number, |
even_number : std_logic_vector(7 downto 0); |
|
signal input_data, |
output_data, |
to_encr_reg128, |
from_tdi_to_xors, |
to_output_whit_xors, |
from_xors_to_tdo, |
to_mux, to_demux, |
from_input_whit_xors, |
to_round, |
to_input_mux : std_logic_vector(127 downto 0) ; |
|
signal twofish_key : std_logic_vector(191 downto 0); |
|
signal key_up, |
key_down, |
Sfirst, |
Ssecond, |
Sthird, |
from_xor0, |
from_xor1, |
from_xor2, |
from_xor3, |
K0,K1,K2,K3, |
K4,K5,K6,K7 : std_logic_vector(31 downto 0); |
|
signal clk : std_logic := '0'; |
signal mux_selection : std_logic := '0'; |
signal demux_selection: std_logic := '0'; |
signal enable_encr_reg : std_logic := '0'; |
signal reset : std_logic := '0'; |
signal enable_round_reg : std_logic := '0'; |
|
-- begin the testbench arch description |
begin |
|
|
-- getting data to encrypt |
data_input: twofish_data_input |
port map ( |
in_tdi => input_data, |
out_tdi => from_tdi_to_xors |
); |
|
-- producing whitening keys K0..7 |
the_whitening_step: twofish_whit_keysched192 |
port map ( |
in_key_twk192 => twofish_key, |
out_K0_twk192 => K0, |
out_K1_twk192 => K1, |
out_K2_twk192 => K2, |
out_K3_twk192 => K3, |
out_K4_twk192 => K4, |
out_K5_twk192 => K5, |
out_K6_twk192 => K6, |
out_K7_twk192 => K7 |
); |
|
-- performing the input whitening XORs |
from_xor0 <= K4 XOR from_tdi_to_xors(127 downto 96); |
from_xor1 <= K5 XOR from_tdi_to_xors(95 downto 64); |
from_xor2 <= K6 XOR from_tdi_to_xors(63 downto 32); |
from_xor3 <= K7 XOR from_tdi_to_xors(31 downto 0); |
|
from_input_whit_xors <= from_xor0 & from_xor1 & from_xor2 & from_xor3; |
|
round_reg: reg128 |
port map ( in_reg128 => from_input_whit_xors, |
out_reg128 => to_input_mux, |
enable_reg128 => enable_round_reg, |
reset_reg128 => reset, |
clk_reg128 => clk ); |
|
input_mux: mux128 |
port map ( in1_mux128 => to_input_mux, |
in2_mux128 => to_mux, |
out_mux128 => to_round, |
selection_mux128 => mux_selection |
); |
|
|
-- creating a round |
the_keysched_of_the_round: twofish_keysched192 |
port map ( |
odd_in_tk192 => odd_number, |
even_in_tk192 => even_number, |
in_key_tk192 => twofish_key, |
out_key_up_tk192 => key_up, |
out_key_down_tk192 => key_down |
); |
|
producing_the_Skeys: twofish_S192 |
port map ( |
in_key_ts192 => twofish_key, |
out_Sfirst_ts192 => Sfirst, |
out_Ssecond_ts192 => Ssecond, |
out_Sthird_ts192 => Sthird |
); |
|
the_decryption_circuit: twofish_decryption_round192 |
port map ( |
in1_tdr192 => to_round(127 downto 96), |
in2_tdr192 => to_round(95 downto 64), |
in3_tdr192 => to_round(63 downto 32), |
in4_tdr192 => to_round(31 downto 0), |
in_Sfirst_tdr192 => Sfirst, |
in_Ssecond_tdr192 => Ssecond, |
in_Sthird_tdr192 => Sthird, |
in_key_up_tdr192 => key_up, |
in_key_down_tdr192 => key_down, |
out1_tdr192 => to_encr_reg128(127 downto 96), |
out2_tdr192 => to_encr_reg128(95 downto 64), |
out3_tdr192 => to_encr_reg128(63 downto 32), |
out4_tdr192 => to_encr_reg128(31 downto 0) |
); |
|
encr_reg: reg128 |
port map ( in_reg128 => to_encr_reg128, |
out_reg128 => to_demux, |
enable_reg128 => enable_encr_reg, |
reset_reg128 => reset, |
clk_reg128 => clk ); |
|
output_demux: demux128 |
port map ( in_demux128 => to_demux, |
out1_demux128 => to_output_whit_xors, |
out2_demux128 => to_mux, |
selection_demux128 => demux_selection ); |
|
-- don't forget the last swap !!! |
from_xors_to_tdo(127 downto 96) <= K0 XOR to_output_whit_xors(63 downto 32); |
from_xors_to_tdo(95 downto 64) <= K1 XOR to_output_whit_xors(31 downto 0); |
from_xors_to_tdo(63 downto 32) <= K2 XOR to_output_whit_xors(127 downto 96); |
from_xors_to_tdo(31 downto 0) <= K3 XOR to_output_whit_xors(95 downto 64); |
|
taking_the_output: twofish_data_output |
port map ( |
in_tdo => from_xors_to_tdo, |
out_tdo => output_data |
); |
|
-- we create the clock |
clk <= not clk after 50 ns; -- period 100 ns |
|
|
cbc_dmc_proc: process |
|
variable key_f, -- key input from file |
pt_f, -- plaintext from file |
ct_f, |
iv_f : line; -- ciphertext from file |
variable key_v : std_logic_vector(191 downto 0); -- key vector input |
variable pt_v , -- plaintext vector |
ct_v, |
iv_v : std_logic_vector(127 downto 0); -- ciphertext vector |
|
variable counter_10000 : integer range 0 to 9999 := 0; -- counter for the 10.000 repeats in the 400 next ones |
variable counter_400 : integer range 0 to 399 := 0; -- counter for the 400 repeats |
variable round : integer range 0 to 16 := 0; -- holds the rounds |
variable PT, CT, CV, CTj_1 : std_logic_vector(127 downto 0) := (others => '0'); |
|
begin |
|
while not endfile(input_file) loop |
|
readline(input_file, key_f); |
readline(input_file, iv_f); |
readline(input_file,ct_f); |
readline(input_file, pt_f); |
hread(key_f,key_v); |
hread(iv_f, iv_v); |
hread(ct_f,ct_v); |
hread(pt_f,pt_v); |
|
twofish_key <= key_v; |
CV := iv_v; |
CT := ct_v; |
|
for counter_10000 in 0 to 9999 loop |
|
input_data <= CT; |
|
wait for 25 ns; |
reset <= '1'; |
wait for 50 ns; |
reset <= '0'; |
|
mux_selection <= '0'; |
demux_selection <= '1'; |
enable_encr_reg <= '0'; |
enable_round_reg <= '0'; |
wait for 50 ns; |
enable_round_reg <= '1'; |
wait for 50 ns; |
enable_round_reg <= '0'; |
|
-- the first round |
even_number <= "00100110"; -- 38 |
odd_number <= "00100111"; -- 39 |
wait for 50 ns; |
enable_encr_reg <= '1'; |
wait for 50 ns; |
enable_encr_reg <= '0'; |
demux_selection <= '1'; |
mux_selection <= '1'; |
|
-- the rest 15 rounds |
for round in 1 to 15 loop |
even_number <= conv_std_logic_vector((((15-round)*2)+8), 8); |
odd_number <= conv_std_logic_vector((((15-round)*2)+9), 8); |
wait for 50 ns; |
enable_encr_reg <= '1'; |
wait for 50 ns; |
enable_encr_reg <= '0'; |
end loop; |
|
-- taking final results |
demux_selection <= '0'; |
wait for 25 ns; |
|
PT := output_data XOR CV; |
CV := CT; |
CT := PT; |
|
assert false report "I=" & to_text(counter_400) & " R=" & to_text(counter_10000) severity note; |
|
end loop; -- counter_10000 |
|
hwrite(key_f, key_v); |
hwrite(iv_f, iv_v); |
hwrite(ct_f, ct_v); |
hwrite(pt_f, PT); |
writeline(output_file,key_f); |
writeline(output_file, iv_f); |
writeline(output_file,ct_f); |
writeline(output_file,pt_f); |
|
assert (pt_v = PT) report "file entry and decryption result DO NOT match!!! :( " severity failure; |
assert (pt_v /= PT) report "Decryption I=" & to_text(counter_400) &" OK" severity note; |
|
counter_400 := counter_400 + 1; |
|
end loop; |
assert false report "***** CBC Decryption Monte Carlo Test with 192 bits key size ended succesfully! :) *****" severity failure; |
end process cbc_dmc_proc; |
|
end cbc_decryption192_monte_carlo_testbench_arch; |
|
/trunk/vhdl/twofish_ecb_decryption_monte_carlo_testbench_128bits.vhd
0,0 → 1,394
-- Twofish_ecb_decryption_monte_carlo_testbench_128bits.vhd |
-- Copyright (C) 2006 Spyros Ninos |
-- |
-- This program is free software; you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation; either version 2 of the License, or |
-- (at your option) any later version. |
-- |
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU General Public License |
-- along with this library; see the file COPYING. If not, write to: |
-- |
-- Free Software Foundation |
-- 59 Temple Place - Suite 330 |
-- Boston, MA 02111-1307, USA. |
-- |
-- description : this file is the testbench for the Decryption Monte Carlo KAT of the twofish cipher with 128 bit key |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
use ieee.std_logic_textio.all; |
use ieee.std_logic_arith.all; |
use std.textio.all; |
|
entity ecb_decryption_monte_carlo_testbench128 is |
end ecb_decryption_monte_carlo_testbench128; |
|
architecture ecb_decryption128_monte_carlo_testbench_arch of ecb_decryption_monte_carlo_testbench128 is |
|
component reg128 |
port ( |
in_reg128 : in std_logic_vector(127 downto 0); |
out_reg128 : out std_logic_vector(127 downto 0); |
enable_reg128, reset_reg128, clk_reg128 : in std_logic |
); |
end component; |
|
component twofish_keysched128 |
port ( |
odd_in_tk128, |
even_in_tk128 : in std_logic_vector(7 downto 0); |
in_key_tk128 : in std_logic_vector(127 downto 0); |
out_key_up_tk128, |
out_key_down_tk128 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component twofish_whit_keysched128 |
port ( |
in_key_twk128 : in std_logic_vector(127 downto 0); |
out_K0_twk128, |
out_K1_twk128, |
out_K2_twk128, |
out_K3_twk128, |
out_K4_twk128, |
out_K5_twk128, |
out_K6_twk128, |
out_K7_twk128 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component twofish_decryption_round128 |
port ( |
in1_tdr128, |
in2_tdr128, |
in3_tdr128, |
in4_tdr128, |
in_Sfirst_tdr128, |
in_Ssecond_tdr128, |
in_key_up_tdr128, |
in_key_down_tdr128 : in std_logic_vector(31 downto 0); |
out1_tdr128, |
out2_tdr128, |
out3_tdr128, |
out4_tdr128 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component twofish_data_input |
port ( |
in_tdi : in std_logic_vector(127 downto 0); |
out_tdi : out std_logic_vector(127 downto 0) |
); |
end component; |
|
component twofish_data_output |
port ( |
in_tdo : in std_logic_vector(127 downto 0); |
out_tdo : out std_logic_vector(127 downto 0) |
); |
end component; |
|
component demux128 |
port ( in_demux128 : in std_logic_vector(127 downto 0); |
out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0); |
selection_demux128 : in std_logic |
); |
end component; |
|
component mux128 |
port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0); |
selection_mux128 : in std_logic; |
out_mux128 : out std_logic_vector(127 downto 0) |
); |
end component; |
|
component twofish_S128 |
port ( |
in_key_ts128 : in std_logic_vector(127 downto 0); |
out_Sfirst_ts128, |
out_Ssecond_ts128 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
FILE input_file : text is in "twofish_ecb_decryption_monte_carlo_testvalues_128bits.txt"; |
FILE output_file : text is out "twofish_ecb_decryption_monte_carlo_128bits_results.txt"; |
|
-- we create the functions that transform a number to text |
-- transforming a signle digit to a character |
function digit_to_char(number : integer range 0 to 9) return character is |
begin |
case number is |
when 0 => return '0'; |
when 1 => return '1'; |
when 2 => return '2'; |
when 3 => return '3'; |
when 4 => return '4'; |
when 5 => return '5'; |
when 6 => return '6'; |
when 7 => return '7'; |
when 8 => return '8'; |
when 9 => return '9'; |
end case; |
end; |
|
-- transforming multi-digit number to text |
function to_text(int_number : integer range 0 to 9999) return string is |
variable our_text : string (1 to 4) := (others => ' '); |
variable thousands, |
hundreds, |
tens, |
ones : integer range 0 to 9; |
begin |
ones := int_number mod 10; |
tens := ((int_number mod 100) - ones) / 10; |
hundreds := ((int_number mod 1000) - (int_number mod 100)) / 100; |
thousands := (int_number - (int_number mod 1000)) / 1000; |
our_text(1) := digit_to_char(thousands); |
our_text(2) := digit_to_char(hundreds); |
our_text(3) := digit_to_char(tens); |
our_text(4) := digit_to_char(ones); |
return our_text; |
end; |
|
signal odd_number, |
even_number : std_logic_vector(7 downto 0); |
|
signal input_data, |
output_data, |
twofish_key, |
to_encr_reg128, |
from_tdi_to_xors, |
to_output_whit_xors, |
from_xors_to_tdo, |
to_mux, to_demux, |
from_input_whit_xors, |
to_round, |
to_input_mux : std_logic_vector(127 downto 0) ; |
|
signal key_up, |
key_down, |
Sfirst, |
Ssecond, |
from_xor0, |
from_xor1, |
from_xor2, |
from_xor3, |
K0,K1,K2,K3, |
K4,K5,K6,K7 : std_logic_vector(31 downto 0); |
|
signal clk : std_logic := '0'; |
signal mux_selection : std_logic := '0'; |
signal demux_selection: std_logic := '0'; |
signal enable_encr_reg : std_logic := '0'; |
signal reset : std_logic := '0'; |
signal enable_round_reg : std_logic := '0'; |
|
-- begin the testbench arch description |
begin |
|
|
-- getting data to encrypt |
data_input: twofish_data_input |
port map ( |
in_tdi => input_data, |
out_tdi => from_tdi_to_xors |
); |
|
-- producing whitening keys K0..7 |
the_whitening_step: twofish_whit_keysched128 |
port map ( |
in_key_twk128 => twofish_key, |
out_K0_twk128 => K0, |
out_K1_twk128 => K1, |
out_K2_twk128 => K2, |
out_K3_twk128 => K3, |
out_K4_twk128 => K4, |
out_K5_twk128 => K5, |
out_K6_twk128 => K6, |
out_K7_twk128 => K7 |
); |
|
-- performing the input whitening XORs |
from_xor0 <= K4 XOR from_tdi_to_xors(127 downto 96); |
from_xor1 <= K5 XOR from_tdi_to_xors(95 downto 64); |
from_xor2 <= K6 XOR from_tdi_to_xors(63 downto 32); |
from_xor3 <= K7 XOR from_tdi_to_xors(31 downto 0); |
|
from_input_whit_xors <= from_xor0 & from_xor1 & from_xor2 & from_xor3; |
|
round_reg: reg128 |
port map ( in_reg128 => from_input_whit_xors, |
out_reg128 => to_input_mux, |
enable_reg128 => enable_round_reg, |
reset_reg128 => reset, |
clk_reg128 => clk ); |
|
input_mux: mux128 |
port map ( in1_mux128 => to_input_mux, |
in2_mux128 => to_mux, |
out_mux128 => to_round, |
selection_mux128 => mux_selection |
); |
|
|
-- creating a round |
the_keysched_of_the_round: twofish_keysched128 |
port map ( |
odd_in_tk128 => odd_number, |
even_in_tk128 => even_number, |
in_key_tk128 => twofish_key, |
out_key_up_tk128 => key_up, |
out_key_down_tk128 => key_down |
); |
|
producing_the_Skeys: twofish_S128 |
port map ( |
in_key_ts128 => twofish_key, |
out_Sfirst_ts128 => Sfirst, |
out_Ssecond_ts128 => Ssecond |
); |
|
the_decryption_circuit: twofish_decryption_round128 |
port map ( |
in1_tdr128 => to_round(127 downto 96), |
in2_tdr128 => to_round(95 downto 64), |
in3_tdr128 => to_round(63 downto 32), |
in4_tdr128 => to_round(31 downto 0), |
in_Sfirst_tdr128 => Sfirst, |
in_Ssecond_tdr128 => Ssecond, |
in_key_up_tdr128 => key_up, |
in_key_down_tdr128 => key_down, |
out1_tdr128 => to_encr_reg128(127 downto 96), |
out2_tdr128 => to_encr_reg128(95 downto 64), |
out3_tdr128 => to_encr_reg128(63 downto 32), |
out4_tdr128 => to_encr_reg128(31 downto 0) |
); |
|
encr_reg: reg128 |
port map ( in_reg128 => to_encr_reg128, |
out_reg128 => to_demux, |
enable_reg128 => enable_encr_reg, |
reset_reg128 => reset, |
clk_reg128 => clk ); |
|
output_demux: demux128 |
port map ( in_demux128 => to_demux, |
out1_demux128 => to_output_whit_xors, |
out2_demux128 => to_mux, |
selection_demux128 => demux_selection ); |
|
-- don't forget the last swap !!! |
from_xors_to_tdo(127 downto 96) <= K0 XOR to_output_whit_xors(63 downto 32); |
from_xors_to_tdo(95 downto 64) <= K1 XOR to_output_whit_xors(31 downto 0); |
from_xors_to_tdo(63 downto 32) <= K2 XOR to_output_whit_xors(127 downto 96); |
from_xors_to_tdo(31 downto 0) <= K3 XOR to_output_whit_xors(95 downto 64); |
|
taking_the_output: twofish_data_output |
port map ( |
in_tdo => from_xors_to_tdo, |
out_tdo => output_data |
); |
|
-- we create the clock |
clk <= not clk after 50 ns; -- period 100 ns |
|
|
ecb_dmc_proc: process |
|
variable key_f, -- key input from file |
pt_f, -- plaintext from file |
ct_f : line; -- ciphertext from file |
variable key_v, -- key vector input |
pt_v , -- plaintext vector |
ct_v : std_logic_vector(127 downto 0); -- ciphertext vector |
|
variable counter_10000 : integer range 0 to 9999 := 0; -- counter for the 10.000 repeats in the 400 next ones |
variable counter_400 : integer range 0 to 399 := 0; -- counter for the 400 repeats |
variable round : integer range 0 to 16 := 0; -- holds the rounds |
variable intermediate_decryption_result : std_logic_vector(127 downto 0); -- holds the intermediate decryption result |
|
begin |
|
while not endfile(input_file) loop |
|
readline(input_file, key_f); |
readline(input_file, pt_f); |
readline(input_file,ct_f); |
hread(key_f,key_v); |
hread(pt_f,pt_v); |
hread(ct_f,ct_v); |
|
twofish_key <= key_v; |
intermediate_decryption_result := pt_v; |
|
for counter_10000 in 0 to 9999 loop |
input_data <= intermediate_decryption_result; |
|
wait for 25 ns; |
reset <= '1'; |
wait for 50 ns; |
reset <= '0'; |
|
mux_selection <= '0'; |
demux_selection <= '1'; |
enable_encr_reg <= '0'; |
enable_round_reg <= '0'; |
wait for 50 ns; |
enable_round_reg <= '1'; |
wait for 50 ns; |
enable_round_reg <= '0'; |
|
-- the first round |
even_number <= "00100110"; -- 38 |
odd_number <= "00100111"; -- 39 |
wait for 50 ns; |
enable_encr_reg <= '1'; |
wait for 50 ns; |
enable_encr_reg <= '0'; |
demux_selection <= '1'; |
mux_selection <= '1'; |
|
-- the rest 15 rounds |
for round in 1 to 15 loop |
even_number <= conv_std_logic_vector((((15-round)*2)+8), 8); |
odd_number <= conv_std_logic_vector((((15-round)*2)+9), 8); |
wait for 50 ns; |
enable_encr_reg <= '1'; |
wait for 50 ns; |
enable_encr_reg <= '0'; |
end loop; |
|
-- taking final results |
demux_selection <= '0'; |
wait for 25 ns; |
|
intermediate_decryption_result := output_data; |
|
assert false report "I=" & to_text(counter_400) & " R=" & to_text(counter_10000) severity note; |
|
end loop; -- counter_10000 |
|
hwrite(key_f, key_v); |
hwrite(pt_f, pt_v); |
hwrite(ct_f,output_data); |
writeline(output_file,key_f); |
writeline(output_file,pt_f); |
writeline(output_file,ct_f); |
|
assert (ct_v = output_data) report "file entry and decryption result DO NOT match!!! :( " severity failure; |
assert (ct_v /= output_data) report "Decryption I=" & to_text(counter_400) &" OK" severity note; |
counter_400 := counter_400 + 1; |
end loop; |
assert false report "***** ECB Decryption Monte Carlo Test with 128 bits key size ended succesfully! :) *****" severity failure; |
end process ecb_dmc_proc; |
|
end ecb_decryption128_monte_carlo_testbench_arch; |
|
/trunk/vhdl/twofish_ecb_decryption_monte_carlo_testbench_192bits.vhd
0,0 → 1,400
-- Twofish_ecb_decryption_monte_carlo_testbench_192bits.vhd |
-- Copyright (C) 2006 Spyros Ninos |
-- |
-- This program is free software; you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
-- the Free Software Foundation; either version 2 of the License, or |
-- (at your option) any later version. |
-- |
-- This program is distributed in the hope that it will be useful, |
-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
-- GNU General Public License for more details. |
-- |
-- You should have received a copy of the GNU General Public License |
-- along with this library; see the file COPYING. If not, write to: |
-- |
-- Free Software Foundation |
-- 59 Temple Place - Suite 330 |
-- Boston, MA 02111-1307, USA. |
-- |
-- description : this file is the testbench for the Decryption Monte Carlo KAT of the twofish cipher with 192 bit key |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
use ieee.std_logic_textio.all; |
use ieee.std_logic_arith.all; |
use std.textio.all; |
|
entity ecb_decryption_monte_carlo_testbench192 is |
end ecb_decryption_monte_carlo_testbench192; |
|
architecture ecb_decryption192_monte_carlo_testbench_arch of ecb_decryption_monte_carlo_testbench192 is |
|
component reg128 |
port ( |
in_reg128 : in std_logic_vector(127 downto 0); |
out_reg128 : out std_logic_vector(127 downto 0); |
enable_reg128, reset_reg128, clk_reg128 : in std_logic |
); |
end component; |
|
component twofish_keysched192 |
port ( |
odd_in_tk192, |
even_in_tk192 : in std_logic_vector(7 downto 0); |
in_key_tk192 : in std_logic_vector(191 downto 0); |
out_key_up_tk192, |
out_key_down_tk192 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component twofish_whit_keysched192 |
port ( |
in_key_twk192 : in std_logic_vector(191 downto 0); |
out_K0_twk192, |
out_K1_twk192, |
out_K2_twk192, |
out_K3_twk192, |
out_K4_twk192, |
out_K5_twk192, |
out_K6_twk192, |
out_K7_twk192 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component twofish_decryption_round192 |
port ( |
in1_tdr192, |
in2_tdr192, |
in3_tdr192, |
in4_tdr192, |
in_Sfirst_tdr192, |
in_Ssecond_tdr192, |
in_Sthird_tdr192, |
in_key_up_tdr192, |
in_key_down_tdr192 : in std_logic_vector(31 downto 0); |
out1_tdr192, |
out2_tdr192, |
out3_tdr192, |
out4_tdr192 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
component twofish_data_input |
port ( |
in_tdi : in std_logic_vector(127 downto 0); |
out_tdi : out std_logic_vector(127 downto 0) |
); |
end component; |
|
component twofish_data_output |
port ( |
in_tdo : in std_logic_vector(127 downto 0); |
out_tdo : out std_logic_vector(127 downto 0) |
); |
end component; |
|
component demux128 |
port ( in_demux128 : in std_logic_vector(127 downto 0); |
out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0); |
selection_demux128 : in std_logic |
); |
end component; |
|
component mux128 |
port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0); |
selection_mux128 : in std_logic; |
out_mux128 : out std_logic_vector(127 downto 0) |
); |
end component; |
|
component twofish_S192 |
port ( |
in_key_ts192 : in std_logic_vector(191 downto 0); |
out_Sfirst_ts192, |
out_Ssecond_ts192, |
out_Sthird_ts192 : out std_logic_vector(31 downto 0) |
); |
end component; |
|
FILE input_file : text is in "twofish_ecb_decryption_monte_carlo_testvalues_192bits.txt"; |
FILE output_file : text is out "twofish_ecb_decryption_monte_carlo_192bits_results.txt"; |
|
-- we create the functions that transform a number to text |
-- transforming a signle digit to a character |
function digit_to_char(number : integer range 0 to 9) return character is |
begin |
case number is |
when 0 => return '0'; |
when 1 => return '1'; |
when 2 => return '2'; |
when 3 => return '3'; |
when 4 => return '4'; |
when 5 => return '5'; |
when 6 => return '6'; |
when 7 => return '7'; |
when 8 => return '8'; |
when 9 => return '9'; |
end case; |
end; |
|
-- transforming multi-digit number to text |
function to_text(int_number : integer range 0 to 9999) return string is |
variable our_text : string (1 to 4) := (others => ' '); |
variable thousands, |
hundreds, |
tens, |
ones : integer range 0 to 9; |
begin |
ones := int_number mod 10; |
tens := ((int_number mod 100) - ones) / 10; |
hundreds := ((int_number mod 1000) - (int_number mod 100)) / 100; |
thousands := (int_number - (int_number mod 1000)) / 1000; |
our_text(1) := digit_to_char(thousands); |
our_text(2) := digit_to_char(hundreds); |
our_text(3) := digit_to_char(tens); |
our_text(4) := digit_to_char(ones); |
return our_text; |
end; |
|
signal odd_number, |
even_number : std_logic_vector(7 downto 0); |
|
signal input_data, |
output_data, |
to_encr_reg128, |
from_tdi_to_xors, |
to_output_whit_xors, |
from_xors_to_tdo, |
to_mux, to_demux, |
from_input_whit_xors, |
to_round, |
to_input_mux : std_logic_vector(127 downto 0) ; |
|
signal twofish_key : std_logic_vector(191 downto 0); |
|
signal key_up, |
key_down, |
Sfirst, |
Ssecond, |
Sthird, |
from_xor0, |
from_xor1, |
from_xor2, |
from_xor3, |
K0,K1,K2,K3, |
K4,K5,K6,K7 : std_logic_vector(31 downto 0); |
|
signal clk : std_logic := '0'; |
signal mux_selection : std_logic := '0'; |
signal demux_selection: std_logic := '0'; |
signal enable_encr_reg : std_logic := '0'; |
signal reset : std_logic := '0'; |
signal enable_round_reg : std_logic := '0'; |
|
-- begin the testbench arch description |
begin |
|
|
-- getting data to encrypt |
data_input: twofish_data_input |
port map ( |
in_tdi => input_data, |
out_tdi => from_tdi_to_xors |
); |
|
-- producing whitening keys K0..7 |
the_whitening_step: twofish_whit_keysched192 |
port map ( |
in_key_twk192 => twofish_key, |
out_K0_twk192 => K0, |
out_K1_twk192 => K1, |
out_K2_twk192 => K2, |
out_K3_twk192 => K3, |
out_K4_twk192 => K4, |
out_K5_twk192 => K5, |
out_K6_twk192 => K6, |
out_K7_twk192 => K7 |
); |
|
-- performing the input whitening XORs |
from_xor0 <= K4 XOR from_tdi_to_xors(127 downto 96); |
from_xor1 <= K5 XOR from_tdi_to_xors(95 downto 64); |
from_xor2 <= K6 XOR from_tdi_to_xors(63 downto 32); |
from_xor3 <= K7 XOR from_tdi_to_xors(31 downto 0); |
|
from_input_whit_xors <= from_xor0 & from_xor1 & from_xor2 & from_xor3; |
|
round_reg: reg128 |
port map ( in_reg128 => from_input_whit_xors, |
out_reg128 => to_input_mux, |
enable_reg128 => enable_round_reg, |
reset_reg128 => reset, |
clk_reg128 => clk ); |
|
input_mux: mux128 |
port map ( in1_mux128 => to_input_mux, |
in2_mux128 => to_mux, |
out_mux128 => to_round, |
selection_mux128 => mux_selection |
); |
|
|
-- creating a round |
the_keysched_of_the_round: twofish_keysched192 |
port map ( |
odd_in_tk192 => odd_number, |
even_in_tk192 => even_number, |
in_key_tk192 => twofish_key, |
out_key_up_tk192 => key_up, |
out_key_down_tk192 => key_down |
); |
|
producing_the_Skeys: twofish_S192 |
port map ( |
in_key_ts192 => twofish_key, |
out_Sfirst_ts192 => Sfirst, |
out_Ssecond_ts192 => Ssecond, |
out_Sthird_ts192 => Sthird |
); |
|
the_decryption_circuit: twofish_decryption_round192 |
port map ( |
in1_tdr192 => to_round(127 downto 96), |
in2_tdr192 => to_round(95 downto 64), |
in3_tdr192 => to_round(63 downto 32), |
in4_tdr192 => to_round(31 downto 0), |
in_Sfirst_tdr192 => Sfirst, |
in_Ssecond_tdr192 => Ssecond, |
in_Sthird_tdr192 => Sthird, |
in_key_up_tdr192 => key_up, |
in_key_down_tdr192 => key_down, |
out1_tdr192 => to_encr_reg128(127 downto 96), |
out2_tdr192 => to_encr_reg128(95 downto 64), |
out3_tdr192 => to_encr_reg128(63 downto 32), |
out4_tdr192 => to_encr_reg128(31 downto 0) |
); |
|
encr_reg: reg128 |
port map ( in_reg128 => to_encr_reg128, |
out_reg128 => to_demux, |
enable_reg128 => enable_encr_reg, |
reset_reg128 => reset, |
clk_reg128 => clk ); |
|
output_demux: demux128 |
port map ( in_demux128 => to_demux, |
out1_demux128 => to_output_whit_xors, |
out2_demux128 => to_mux, |
selection_demux128 => demux_selection ); |
|
-- don't forget the last swap !!! |
from_xors_to_tdo(127 downto 96) <= K0 XOR to_output_whit_xors(63 downto 32); |
from_xors_to_tdo(95 downto 64) <= K1 XOR to_output_whit_xors(31 downto 0); |
from_xors_to_tdo(63 downto 32) <= K2 XOR to_output_whit_xors(127 downto 96); |
from_xors_to_tdo(31 downto 0) <= K3 XOR to_output_whit_xors(95 downto 64); |
|
taking_the_output: twofish_data_output |
port map ( |
in_tdo => from_xors_to_tdo, |
out_tdo => output_data |
); |
|
-- we create the clock |
clk <= not clk after 50 ns; -- period 100 ns |
|
|
ecb_dmc_proc: process |
|
variable key_f, -- key input from file |
pt_f, -- plaintext from file |
ct_f : line; -- ciphertext from file |
variable key_v : std_logic_vector(191 downto 0); -- key vector input |
variable pt_v , -- plaintext vector |
ct_v : std_logic_vector(127 downto 0); -- ciphertext vector |
|
variable counter_10000 : integer range 0 to 9999 := 0; -- counter for the 10.000 repeats in the 400 next ones |
variable counter_400 : integer range 0 to 399 := 0; -- counter for the 400 repeats |
variable round : integer range 0 to 16 := 0; -- holds the rounds |
variable intermediate_decryption_result : std_logic_vector(127 downto 0); -- holds the intermediate decryption result |
|
begin |
|
while not endfile(input_file) loop |
|
readline(input_file, key_f); |
readline(input_file, pt_f); |
readline(input_file,ct_f); |
hread(key_f,key_v); |
hread(pt_f,pt_v); |
hread(ct_f,ct_v); |
|
twofish_key <= key_v; |
intermediate_decryption_result := pt_v; |
|
for counter_10000 in 0 to 9999 loop |
input_data <= intermediate_decryption_result; |
|
wait for 25 ns; |
reset <= '1'; |
wait for 50 ns; |
reset <= '0'; |
|
mux_selection <= '0'; |
demux_selection <= '1'; |
enable_encr_reg <= '0'; |
enable_round_reg <= '0'; |
wait for 50 ns; |
enable_round_reg <= '1'; |
wait for 50 ns; |
enable_round_reg <= '0'; |
|
-- the first round |
even_number <= "00100110"; -- 38 |
odd_number <= "00100111"; -- 39 |
wait for 50 ns; |
enable_encr_reg <= '1'; |
wait for 50 ns; |
enable_encr_reg <= '0'; |
demux_selection <= '1'; |
mux_selection <= '1'; |
|
-- the rest 15 rounds |
for round in 1 to 15 loop |
even_number <= conv_std_logic_vector((((15-round)*2)+8), 8); |
odd_number <= conv_std_logic_vector((((15-round)*2)+9), 8); |
wait for 50 ns; |
enable_encr_reg <= '1'; |
wait for 50 ns; |
enable_encr_reg <= '0'; |
end loop; |
|
-- taking final results |
demux_selection <= '0'; |
wait for 25 ns; |
|
intermediate_decryption_result := output_data; |
|
assert false report "I=" & to_text(counter_400) & " R=" & to_text(counter_10000) severity note; |
|
end loop; -- counter_10000 |
|
hwrite(key_f, key_v); |
hwrite(pt_f, pt_v); |
hwrite(ct_f,output_data); |
writeline(output_file,key_f); |
writeline(output_file,pt_f); |
writeline(output_file,ct_f); |
|
assert (ct_v = output_data) report "file entry and decryption result DO NOT match!!! :( " severity failure; |
assert (ct_v /= output_data) report "Decryption I=" & to_text(counter_400) &" OK" severity note; |
counter_400 := counter_400 + 1; |
end loop; |
assert false report "***** ECB Decryption Monte Carlo Test with 192 bits key size ended succesfully! :) *****" severity failure; |
end process ecb_dmc_proc; |
|
end ecb_decryption192_monte_carlo_testbench_arch; |
|
/trunk/Readme.en
0,0 → 1,9
This is under the GPL. See file COPYING. |
|
This design implements the Twofish cipher for 128 and 192 bit keys. |
|
Read the manual for further details. |
|
Happy VHDLing! |
|
- spyros |