OpenCores
URL https://opencores.org/ocsvn/wb_size_bridge/wb_size_bridge/trunk

Subversion Repositories wb_size_bridge

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/wb_size_bridge/trunk/tb/test/debug/debug.cr.mti
0,0 → 1,36
C:/qaz/work/qaz/proj/de1_board/wb_size_bridge/tb/test/debug/tb_dut.v {1 {vlog -work work C:/qaz/work/qaz/proj/de1_board/wb_size_bridge/tb/test/debug/tb_dut.v
Model Technology ModelSim ALTERA vlog 6.1g Compiler 2006.08 Aug 12 2006
-- Compiling module tb_dut
 
Top level modules:
tb_dut
 
} {} {}} C:/qaz/work/qaz/proj/de1_board/wb_size_bridge/tb/models/wb_master_model.v {1 {vlog -work work C:/qaz/work/qaz/proj/de1_board/wb_size_bridge/tb/models/wb_master_model.v
Model Technology ModelSim ALTERA vlog 6.1g Compiler 2006.08 Aug 12 2006
-- Compiling module wb_master_model
 
Top level modules:
wb_master_model
 
} {} {}} C:/qaz/work/qaz/proj/de1_board/wb_size_bridge/tb/test/debug/tb_top.v {1 {vlog -work work C:/qaz/work/qaz/proj/de1_board/wb_size_bridge/tb/test/debug/tb_top.v
Model Technology ModelSim ALTERA vlog 6.1g Compiler 2006.08 Aug 12 2006
-- Compiling module tb_top
 
Top level modules:
tb_top
 
} {} {}} C:/qaz/work/qaz/proj/de1_board/wb_size_bridge/src/wb_size_bridge.v {1 {vlog -work work C:/qaz/work/qaz/proj/de1_board/wb_size_bridge/src/wb_size_bridge.v
Model Technology ModelSim ALTERA vlog 6.1g Compiler 2006.08 Aug 12 2006
-- Compiling module wb_size_bridge
 
Top level modules:
wb_size_bridge
 
} {} {}} C:/qaz/work/qaz/proj/de1_board/wb_size_bridge/tb/models/wb_slave_model.v {1 {vlog -work work C:/qaz/work/qaz/proj/de1_board/wb_size_bridge/tb/models/wb_slave_model.v
Model Technology ModelSim ALTERA vlog 6.1g Compiler 2006.08 Aug 12 2006
-- Compiling module wb_slave_model
 
Top level modules:
wb_slave_model
 
} {} {}}
/wb_size_bridge/trunk/tb/test/debug/wb_slave_16_bit.txt
0,0 → 1,16
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/wb_size_bridge/trunk/tb/test/debug/tb_dut.v
0,0 → 1,152
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
`timescale 1ns/10ps
 
 
module tb_dut(
input tb_clk,
input tb_rst
);
 
 
wire wb_hi_clk = tb_clk;
wire wb_hi_rst = tb_rst;
 
wire [31:0] wb_hi_dat_i, wb_hi_dat_o;
wire [31:0] wb_hi_adr_o;
wire wb_hi_cyc_o, wb_hi_stb_o;
wire wb_hi_we_o;
wire [ 3:0] wb_hi_sel_o;
wire wb_hi_ack_i, wb_hi_err_i, wb_hi_rty_i;
 
wire wb_lo_clk_o;
wire wb_lo_rst_o;
 
wire [15:0] wb_lo_dat_i, wb_lo_dat_o;
wire [31:0] wb_lo_adr_o;
wire wb_lo_cyc_o, wb_lo_stb_o;
wire wb_lo_we_o;
wire [1:0] wb_lo_sel_o;
wire wb_lo_ack_i, wb_lo_err_i, wb_lo_rty_i;
wire lo_byte_if_i;
 
 
// --------------------------------------------------------------------
// wb_hi_master_model
wb_master_model wbm(
.clk(wb_hi_clk),
.rst(wb_hi_rst),
.adr(wb_hi_adr_o),
.din(wb_hi_dat_i),
.dout(wb_hi_dat_o),
.cyc(wb_hi_cyc_o),
.stb(wb_hi_stb_o),
.we(wb_hi_we_o),
.sel(wb_hi_sel_o),
.ack(wb_hi_ack_i),
.err(wb_hi_err_i),
.rty(wb_hi_rty_i)
);
 
 
// --------------------------------------------------------------------
// wb_hi_size_bridge
wb_size_bridge i_wb_size_bridge(
.wb_hi_clk_i(wb_hi_clk),
.wb_hi_rst_i(wb_hi_rst),
.wb_hi_dat_o(wb_hi_dat_i),
.wb_hi_dat_i(wb_hi_dat_o),
.wb_hi_adr_i(wb_hi_adr_o),
.wb_hi_cyc_i(wb_hi_cyc_o),
.wb_hi_we_i(wb_hi_we_o),
.wb_hi_stb_i(wb_hi_stb_o),
.wb_hi_sel_i(wb_hi_sel_o),
.wb_hi_ack_o(wb_hi_ack_i),
.wb_hi_err_o(wb_hi_err_i),
.wb_hi_rty_o(wb_hi_rty_i),
.wb_lo_clk_o(wb_lo_clk_o),
.wb_lo_rst_o(wb_lo_rst_o),
.wb_lo_dat_o(wb_lo_dat_o),
.wb_lo_dat_i(wb_lo_dat_i),
.wb_lo_adr_o(wb_lo_adr_o),
.wb_lo_cyc_o(wb_lo_cyc_o),
.wb_lo_we_o(wb_lo_we_o),
.wb_lo_stb_o(wb_lo_stb_o),
.wb_lo_sel_o(wb_lo_sel_o),
.wb_lo_ack_i(wb_lo_ack_i),
.wb_lo_err_i(wb_lo_err_i),
.wb_lo_rty_i(wb_lo_rty_i),
.lo_byte_if_i(lo_byte_if_i)
);
// --------------------------------------------------------------------
// wb_slave_model
wire slave_08_bit_hit = (wb_lo_adr_o[31:24] == 8'h60) & wb_lo_cyc_o;
wire [15:0] slave_08_bit_dat_o;
wire [15:0] slave_16_bit_dat_o;
assign wb_lo_dat_i[15:0] = slave_08_bit_hit ? slave_08_bit_dat_o : slave_16_bit_dat_o;
wire slave_08_bit_ack_o;
wire slave_08_bit_err_o;
wire slave_08_bit_rty_o;
wire slave_16_bit_ack_o;
wire slave_16_bit_err_o;
wire slave_16_bit_rty_o;
assign wb_lo_ack_i = slave_08_bit_hit ? slave_08_bit_ack_o : slave_16_bit_ack_o;
assign wb_lo_err_i = slave_08_bit_hit ? slave_08_bit_err_o : slave_16_bit_err_o;
assign wb_lo_rty_i = slave_08_bit_hit ? slave_08_bit_rty_o : slave_16_bit_rty_o;
wire slave_08_bit_cyc_i = wb_lo_cyc_o & slave_08_bit_hit;
wire slave_08_bit_stb_i = wb_lo_stb_o & slave_08_bit_hit;
wire slave_16_bit_cyc_i = wb_lo_cyc_o & ~slave_08_bit_hit;
wire slave_16_bit_stb_i = wb_lo_stb_o & ~slave_08_bit_hit;
assign lo_byte_if_i = slave_08_bit_hit;
wb_slave_model #(.DWIDTH(8), .AWIDTH(5), .ACK_DELAY(2), .SLAVE_RAM_INIT( "wb_slave_08_bit.txt") )
wb_slave_08_bit(
.clk_i(wb_lo_clk_o),
.rst_i(wb_lo_rst_o),
.dat_o(slave_08_bit_dat_o[7:0]),
.dat_i(wb_lo_dat_o[7:0]),
.adr_i(wb_lo_adr_o[4:0]),
.cyc_i(slave_08_bit_cyc_i),
.stb_i(slave_08_bit_stb_i),
.we_i(wb_lo_we_o),
.sel_i(wb_lo_sel_o[0]),
.ack_o(slave_08_bit_ack_o),
.err_o(slave_08_bit_err_o),
.rty_o(slave_08_bit_rty_o)
);
wb_slave_model #(.DWIDTH(16), .AWIDTH(5), .ACK_DELAY(2), .SLAVE_RAM_INIT( "wb_slave_16_bit.txt") )
wb_slave_16_bit(
.clk_i(wb_lo_clk_o),
.rst_i(wb_lo_rst_o),
.dat_o(slave_16_bit_dat_o),
.dat_i(wb_lo_dat_o[15:0]),
.adr_i(wb_lo_adr_o[4:0]),
.cyc_i(slave_16_bit_cyc_i),
.stb_i(slave_16_bit_stb_i),
.we_i(wb_lo_we_o),
.sel_i(wb_lo_sel_o),
.ack_o(slave_16_bit_ack_o),
.err_o(slave_16_bit_err_o),
.rty_o(slave_16_bit_rty_o)
);
 
endmodule
 
 
/wb_size_bridge/trunk/tb/test/debug/wb_slave_08_bit.txt
0,0 → 1,16
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/wb_size_bridge/trunk/tb/test/debug/debug.mpf
0,0 → 1,304
[Library]
 
; Altera specific primitive library mappings
 
vital2000 = $MODEL_TECH/../vital2000
ieee = $MODEL_TECH/../ieee
verilog = $MODEL_TECH/../verilog
std = $MODEL_TECH/../std
std_developerskit = $MODEL_TECH/../std_developerskit
synopsys = $MODEL_TECH/../synopsys
modelsim_lib = $MODEL_TECH/../modelsim_lib
apex20k = $MODEL_TECH/../altera/vhdl/apex20k
apex20ke = $MODEL_TECH/../altera/vhdl/apex20ke
apexii = $MODEL_TECH/../altera/vhdl/apexii
altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf
altera = $MODEL_TECH/../altera/vhdl/altera
lpm = $MODEL_TECH/../altera/vhdl/220model
220model = $MODEL_TECH/../altera/vhdl/220model
alt_vtl = $MODEL_TECH/../altera/vhdl/alt_vtl
flex6000 = $MODEL_TECH/../altera/vhdl/flex6000
flex10ke = $MODEL_TECH/../altera/vhdl/flex10ke
max = $MODEL_TECH/../altera/vhdl/max
maxii = $MODEL_TECH/../altera/vhdl/maxii
stratix = $MODEL_TECH/../altera/vhdl/stratix
stratixii = $MODEL_TECH/../altera/vhdl/stratixii
stratixiigx = $MODEL_TECH/../altera/vhdl/stratixiigx
cyclone = $MODEL_TECH/../altera/vhdl/cyclone
cycloneii = $MODEL_TECH/../altera/vhdl/cycloneii
cycloneiii = $MODEL_TECH/../altera/vhdl/cycloneiii
sgate = $MODEL_TECH/../altera/vhdl/sgate
stratixiigx_hssi = $MODEL_TECH/../altera/vhdl/stratixiigx_hssi
arriagx_hssi = $MODEL_TECH/../altera/vhdl/arriagx_hssi
arriagx = $MODEL_TECH/../altera/vhdl/arriagx
stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv
stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi
stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip
apex20k_ver = $MODEL_TECH/../altera/verilog/apex20k
apex20ke_ver = $MODEL_TECH/../altera/verilog/apex20ke
apexii_ver = $MODEL_TECH/../altera/verilog/apexii
altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf
altera_ver = $MODEL_TECH/../altera/verilog/altera
lpm_ver = $MODEL_TECH/../altera/verilog/220model
220model_ver = $MODEL_TECH/../altera/verilog/220model
alt_ver = $MODEL_TECH/../altera/verilog/alt_vtl
flex6000_ver = $MODEL_TECH/../altera/verilog/flex6000
flex10ke_ver = $MODEL_TECH/../altera/verilog/flex10ke
max_ver = $MODEL_TECH/../altera/verilog/max
maxii_ver = $MODEL_TECH/../altera/verilog/maxii
stratix_ver = $MODEL_TECH/../altera/verilog/stratix
stratixii_ver = $MODEL_TECH/../altera/verilog/stratixii
stratixiigx_ver = $MODEL_TECH/../altera/verilog/stratixiigx
arriagx_ver = $MODEL_TECH/../altera/verilog/arriagx
cyclone_ver = $MODEL_TECH/../altera/verilog/cyclone
cycloneii_ver = $MODEL_TECH/../altera/verilog/cycloneii
cycloneiii_ver = $MODEL_TECH/../altera/verilog/cycloneiii
sgate_ver = $MODEL_TECH/../altera/verilog/sgate
stratixiigx_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiigx_hssi
arriagx_hssi_ver = $MODEL_TECH/../altera/verilog/arriagx_hssi
stratixiii_ver = $MODEL_TECH/../altera/verilog/stratixiii
stratixiii = $MODEL_TECH/../altera/vhdl/stratixiii
stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv
stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi
stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip
 
work = work
[vcom]
; Turn on VHDL-1993 as the default. Normally is off.
; VHDL93 = 1
 
; Show source line containing error. Default is off.
; Show_source = 1
 
; Turn off unbound-component warnings. Default is on.
; Show_Warning1 = 0
 
; Turn off process-without-a-wait-statement warnings. Default is on.
; Show_Warning2 = 0
 
; Turn off null-range warnings. Default is on.
; Show_Warning3 = 0
 
; Turn off no-space-in-time-literal warnings. Default is on.
; Show_Warning4 = 0
 
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
; Show_Warning5 = 0
 
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
; Optimize_1164 = 0
 
; Turn on resolving of ambiguous function overloading in favor of the
; "explicit" function declaration (not the one automatically created by
; the compiler for each type declaration). Default is off.
; .ini file has Explict enable so that std_logic_signed/unsigned
; will match synthesis tools behavior.
Explicit = 1
 
; Turn off VITAL compliance checking. Default is checking on.
; NoVitalCheck = 1
 
; Ignore VITAL compliance checking errors. Default is to not ignore.
; IgnoreVitalErrors = 1
 
; Turn off VITAL compliance checking warnings. Default is to show warnings.
; Show_VitalChecksWarnings = false
 
; Turn off acceleration of the VITAL packages. Default is to accelerate.
; NoVital = 1
 
; Turn off inclusion of debugging info within design units. Default is to include.
; NoDebug = 1
 
; Turn off "loading..." messages. Default is messages on.
; Quiet = 1
 
; Turn on some limited synthesis rule compliance checking. Checks only:
; -- signals used (read) by a process must be in the sensitivity list
; CheckSynthesis = 1
 
; Require the user to specify a configuration for all bindings,
; and do not generate a compile time default binding for the
; component. This will result in an elaboration error of
; 'component not bound' if the user fails to do so. Avoids the rare
; issue of a false dependency upon the unused default binding.
 
; RequireConfigForAllDefaultBinding = 1
 
[vlog]
 
; Turn off inclusion of debugging info within design units. Default is to include.
; NoDebug = 1
 
; Turn off "loading..." messages. Default is messages on.
; Quiet = 1
 
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
; Default is off.
; Hazard = 1
 
; Turn on converting regular Verilog identifiers to uppercase. Allows case
; insensitivity for module names. Default is no conversion.
; UpCase = 1
 
; Turns on incremental compilation of modules
; Incremental = 1
 
[vsim]
; Simulator resolution
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
resolution = 10ps
 
; User time unit for run commands
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
; unit specified for Resolution. For example, if Resolution is 100ps,
; then UserTimeUnit defaults to ps.
UserTimeUnit = default
 
; Default run length
RunLength = 100 ps
 
; Maximum iterations that can be run without advancing simulation time
IterationLimit = 5000
 
; Directive to license manager:
; vhdl Immediately reserve a VHDL license
; vlog Immediately reserve a Verilog license
; plus Immediately reserve a VHDL and Verilog license
; nomgc Do not look for Mentor Graphics Licenses
; nomti Do not look for Model Technology Licenses
; noqueue Do not wait in the license queue when a license isn't available
; License = plus
 
; Stop the simulator after an assertion message
; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
BreakOnAssertion = 3
 
; Assertion Message Format
; %S - Severity Level
; %R - Report Message
; %T - Time of assertion
; %D - Delta
; %I - Instance or Region pathname (if available)
; %% - print '%' character
; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
 
; Assertion File - alternate file for storing assertion messages
; AssertFile = assert.log
 
; Default radix for all windows and commands...
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
DefaultRadix = symbolic
 
; VSIM Startup command
; Startup = do startup.do
 
; File for saving command transcript
TranscriptFile = transcript
 
; File for saving command history
;CommandHistory = cmdhist.log
 
; Specify whether paths in simulator commands should be described
; in VHDL or Verilog format. For VHDL, PathSeparator = /
; for Verilog, PathSeparator = .
PathSeparator = /
 
; Specify the dataset separator for fully rooted contexts.
; The default is ':'. For example, sim:/top
; Must not be the same character as PathSeparator.
DatasetSeparator = :
 
; Disable assertion messages
; IgnoreNote = 1
; IgnoreWarning = 1
; IgnoreError = 1
; IgnoreFailure = 1
 
; Default force kind. May be freeze, drive, or deposit
; or in other terms, fixed, wired or charged.
; DefaultForceKind = freeze
 
; If zero, open files when elaborated
; else open files on first read or write
; DelayFileOpen = 0
 
; Control VHDL files opened for write
; 0 = Buffered, 1 = Unbuffered
UnbufferedOutput = 0
 
; Control number of VHDL files open concurrently
; This number should always be less then the
; current ulimit setting for max file descriptors
; 0 = unlimited
ConcurrentFileLimit = 40
 
; This controls the number of hierarchical regions displayed as
; part of a signal name shown in the waveform window. The default
; value or a value of zero tells VSIM to display the full name.
; WaveSignalNameWidth = 0
 
; Turn off warnings from the std_logic_arith, std_logic_unsigned
; and std_logic_signed packages.
; StdArithNoWarnings = 1
 
; Turn off warnings from the IEEE numeric_std and numeric_bit
; packages.
; NumericStdNoWarnings = 1
 
; Control the format of a generate statement label. Don't quote it.
; GenerateFormat = %s__%d
 
; Specify whether checkpoint files should be compressed.
; The default is to be compressed.
; CheckpointCompressMode = 0
 
; List of dynamically loaded objects for Verilog PLI applications
; Veriuser = veriuser.sl
[Project]
Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 5
Project_File_0 = C:/qaz/work/qaz/proj/de1_board/wb_size_bridge/tb/models/wb_master_model.v
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1216923358 cover_branch 0 vlog_noload 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 2 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_1 = C:/qaz/work/qaz/proj/de1_board/wb_size_bridge/tb/test/debug/tb_dut.v
Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1217279699 cover_branch 0 vlog_noload 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_2 = C:/qaz/work/qaz/proj/de1_board/wb_size_bridge/src/wb_size_bridge.v
Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1217287216 cover_branch 0 vlog_noload 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_3 = C:/qaz/work/qaz/proj/de1_board/wb_size_bridge/tb/test/debug/tb_top.v
Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1217284836 cover_branch 0 vlog_noload 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_4 = C:/qaz/work/qaz/proj/de1_board/wb_size_bridge/tb/models/wb_slave_model.v
Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1217285469 cover_branch 0 vlog_noload 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 3 dont_compile 0 cover_expr 0 cover_stmt 0
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
Save_Compile_Report = 1
Project_Opt_Count = 0
ForceSoftPaths = 0
ReOpenSourceFiles = 1
VERILOG_DoubleClick = Edit
VERILOG_CustomDoubleClick =
VHDL_DoubleClick = Edit
VHDL_CustomDoubleClick =
PSL_DoubleClick = Edit
PSL_CustomDoubleClick =
TEXT_DoubleClick = Edit
TEXT_CustomDoubleClick =
SYSTEMC_DoubleClick = Edit
SYSTEMC_CustomDoubleClick =
TCL_DoubleClick = Edit
TCL_CustomDoubleClick =
MACRO_DoubleClick = Edit
MACRO_CustomDoubleClick =
VCD_DoubleClick = Edit
VCD_CustomDoubleClick =
SDF_DoubleClick = Edit
SDF_CustomDoubleClick =
XML_DoubleClick = Edit
XML_CustomDoubleClick =
LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick =
EditorState =
Project_Major_Version = 6
Project_Minor_Version = 1
/wb_size_bridge/trunk/tb/test/debug/tb_top.v
0,0 → 1,132
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
`timescale 1ns/10ps
 
 
module tb_top();
 
parameter CLK_PERIOD = 10;
 
reg tb_clk, tb_rst;
 
initial
begin
tb_clk <= 1'b1;
tb_rst <= 1'b1;
#(CLK_PERIOD); #(CLK_PERIOD/3);
tb_rst = 1'b0;
end
 
always
#(CLK_PERIOD/2) tb_clk = ~tb_clk;
// --------------------------------------------------------------------
// tb_dut
tb_dut dut( tb_clk, tb_rst );
 
// --------------------------------------------------------------------
// insert test below
 
initial
begin
wait( ~tb_rst );
repeat(2) @(posedge tb_clk);
// 8 bit if
$display("\n^^^- testing 8 bit interface\n");
dut.wbm.wb_cmp(0, 0, 32'h6000_0000, 32'h3322_1100);
dut.wbm.wb_cmp(0, 0, 32'h6000_0004, 32'h7766_5544);
dut.wbm.wb_cmp(0, 0, 32'h6000_0008, 32'hbbaa_9988);
dut.wbm.wb_cmp(0, 0, 32'h6000_000c, 32'hffee_ddcc);
dut.wbm.wb_write(0, 0, 32'h6000_0010, 32'habba_beef);
dut.wbm.wb_write(0, 0, 32'h6000_0014, 32'h1a2b_3c4d);
dut.wbm.wb_write(0, 0, 32'h6000_0018, 32'hcafe_1a7e);
dut.wbm.wb_write(0, 0, 32'h6000_001c, 32'h5a5a_0f0f);
dut.wbm.wb_cmp(0, 0, 32'h6000_0010, 32'habba_beef);
dut.wbm.wb_cmp(0, 0, 32'h6000_0014, 32'h1a2b_3c4d);
dut.wbm.wb_cmp(0, 0, 32'h6000_0018, 32'hcafe_1a7e);
dut.wbm.wb_cmp(0, 0, 32'h6000_001c, 32'h5a5a_0f0f);
dut.wbm.wb_write_sel(0, 0, 4'b0001, 32'h6000_0010, 32'hxxxx_xx00);
dut.wbm.wb_write_sel(0, 0, 4'b0010, 32'h6000_0014, 32'hxxxx_11xx);
dut.wbm.wb_write_sel(0, 0, 4'b0100, 32'h6000_0018, 32'hxx22_xxxx);
dut.wbm.wb_write_sel(0, 0, 4'b1000, 32'h6000_001c, 32'h33xx_xxxx);
dut.wbm.wb_cmp_sel(0, 0, 4'b0001, 32'h6000_0010, 32'hxxxx_xx00);
dut.wbm.wb_cmp_sel(0, 0, 4'b0010, 32'h6000_0014, 32'hxxxx_11xx);
dut.wbm.wb_cmp_sel(0, 0, 4'b0100, 32'h6000_0018, 32'hxx22_xxxx);
dut.wbm.wb_cmp_sel(0, 0, 4'b1000, 32'h6000_001c, 32'h33xx_xxxx);
dut.wbm.wb_write_sel(0, 0, 4'b0011, 32'h6000_0000, 32'hxxxx_0ab1);
dut.wbm.wb_write_sel(0, 0, 4'b1100, 32'h6000_0004, 32'h2cd3_xxxx);
dut.wbm.wb_write_sel(0, 0, 4'b0011, 32'h6000_0008, 32'hxxxx_4ef5);
dut.wbm.wb_write_sel(0, 0, 4'b1100, 32'h6000_000c, 32'h0f0f_xxxx);
dut.wbm.wb_cmp_sel(0, 0, 4'b0011, 32'h6000_0000, 32'hxxxx_0ab1);
dut.wbm.wb_cmp_sel(0, 0, 4'b1100, 32'h6000_0004, 32'h2cd3_xxxx);
dut.wbm.wb_cmp_sel(0, 0, 4'b0011, 32'h6000_0008, 32'hxxxx_4ef5);
dut.wbm.wb_cmp_sel(0, 0, 4'b1100, 32'h6000_000c, 32'h0f0f_xxxx);
// 16 bit if
$display("\n^^^- testing 16 bit interface\n");
dut.wbm.wb_cmp(0, 0, 32'ha000_0000, 32'h3322_1100);
dut.wbm.wb_cmp(0, 0, 32'ha000_0004, 32'h7766_5544);
dut.wbm.wb_cmp(0, 0, 32'ha000_0008, 32'hbbaa_9988);
dut.wbm.wb_cmp(0, 0, 32'ha000_000c, 32'hffee_ddcc);
dut.wbm.wb_write(0, 0, 32'ha000_0010, 32'habba_beef);
dut.wbm.wb_write(0, 0, 32'ha000_0014, 32'h1a2b_3c4d);
dut.wbm.wb_write(0, 0, 32'ha000_0018, 32'hcafe_1a7e);
dut.wbm.wb_write(0, 0, 32'ha000_001c, 32'h5a5a_0f0f);
dut.wbm.wb_cmp(0, 0, 32'ha000_0010, 32'habba_beef);
dut.wbm.wb_cmp(0, 0, 32'ha000_0014, 32'h1a2b_3c4d);
dut.wbm.wb_cmp(0, 0, 32'ha000_0018, 32'hcafe_1a7e);
dut.wbm.wb_cmp(0, 0, 32'ha000_001c, 32'h5a5a_0f0f);
dut.wbm.wb_write_sel(0, 0, 4'b0011, 32'ha000_0000, 32'hxxxx_0ab1);
dut.wbm.wb_write_sel(0, 0, 4'b1100, 32'ha000_0004, 32'h2cd3_xxxx);
dut.wbm.wb_write_sel(0, 0, 4'b0011, 32'ha000_0008, 32'hxxxx_4ef5);
dut.wbm.wb_write_sel(0, 0, 4'b1100, 32'ha000_000c, 32'h0f0f_xxxx);
dut.wbm.wb_cmp_sel(0, 0, 4'b0011, 32'ha000_0000, 32'hxxxx_0ab1);
dut.wbm.wb_cmp_sel(0, 0, 4'b1100, 32'ha000_0004, 32'h2cd3_xxxx);
dut.wbm.wb_cmp_sel(0, 0, 4'b0011, 32'ha000_0008, 32'hxxxx_4ef5);
dut.wbm.wb_cmp_sel(0, 0, 4'b1100, 32'ha000_000c, 32'h0f0f_xxxx);
dut.wbm.wb_write_sel(0, 0, 4'b0001, 32'h0000_0010, 32'hxxxx_xx00);
dut.wbm.wb_write_sel(0, 0, 4'b0010, 32'h0000_0014, 32'hxxxx_11xx);
dut.wbm.wb_write_sel(0, 0, 4'b0100, 32'h0000_0018, 32'hxx22_xxxx);
dut.wbm.wb_write_sel(0, 0, 4'b1000, 32'h0000_001c, 32'h33xx_xxxx);
dut.wbm.wb_cmp_sel(0, 0, 4'b0001, 32'h0000_0010, 32'hxxxx_xx00);
dut.wbm.wb_cmp_sel(0, 0, 4'b0010, 32'h0000_0014, 32'hxxxx_11xx);
dut.wbm.wb_cmp_sel(0, 0, 4'b0100, 32'h0000_0018, 32'hxx22_xxxx);
dut.wbm.wb_cmp_sel(0, 0, 4'b1000, 32'h0000_001c, 32'h33xx_xxxx);
// do illegal byte boundary access
$display("\n^^^- testing illegal byte boundary access\n");
dut.wbm.wb_write_sel(0, 0, 4'b0110, 32'ha000_0020, 32'hxxba_adxx);
repeat(2) @(posedge tb_clk);
$display("\n^^^---------------------------------\n");
$display("^^^- Testbench done. %t.\n", $time);
$stop();
end
endmodule
 
/wb_size_bridge/trunk/tb/models/wb_slave_model.v
0,0 → 1,123
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
`timescale 1ns/10ps
 
 
module wb_slave_model( clk_i, rst_i, dat_o, dat_i, adr_i,
cyc_i, stb_i, we_i, sel_i,
ack_o, err_o, rty_o );
 
parameter DWIDTH = 8;
parameter AWIDTH = 8;
parameter ACK_DELAY = 2;
parameter SLAVE_RAM_INIT = "wb_slave_model.txt";
input clk_i;
input rst_i;
output [DWIDTH-1:0] dat_o;
input [DWIDTH-1:0] dat_i;
input [AWIDTH-1:0] adr_i;
input cyc_i;
input stb_i;
input we_i;
input [( (DWIDTH/8) - 1 ):0] sel_i;
output ack_o;
output err_o;
output rty_o;
// --------------------------------------------------------------------
// slave ram
reg [7:0] ram[2**AWIDTH-1:0];
initial
$readmemh( SLAVE_RAM_INIT, ram );
 
// --------------------------------------------------------------------
//
generate
case( DWIDTH )
8: begin
initial
$display( "###- wb_slave_model(): WISHBONE 8 BIT SLAVE MODEL INSTANTIATED " );
always @ (posedge clk_i)
if (we_i & cyc_i & stb_i & sel_i[0])
ram[adr_i] <= dat_i[7:0];
assign dat_o = ram[adr_i];
end
16: begin
initial
$display( "###- wb_slave_model(): WISHBONE 16 BIT SLAVE MODEL INSTANTIATED " );
always @ (posedge clk_i)
if (we_i & cyc_i & stb_i & sel_i[0])
ram[{adr_i[AWIDTH-1:1], 1'b0}] <= dat_i[7:0];
always @ (posedge clk_i)
if (we_i & cyc_i & stb_i & sel_i[1])
ram[{adr_i[AWIDTH-1:1], 1'b1}] <= dat_i[15:8];
assign dat_o = { ram[{adr_i[AWIDTH-1:1], 1'b1}], ram[{adr_i[AWIDTH-1:1], 1'b0}] };
end
32: begin
initial
begin
$display( "###- wb_slave_model(): WISHBONE 32 BIT SLAVE MODEL INSTANTIATED " );
$display( "###- wb_slave_model(): Not yet supported " );
$stop();
end
end
default: begin
localparam SLAVE_SIZE = -1;
initial
begin
$display( "!!!- wb_slave_model(): invalad DWIDTH parameter" );
$stop();
end
end
endcase
endgenerate
 
// --------------------------------------------------------------------
// ack delay
reg ack_delayed;
initial
ack_delayed = 1'b0;
always @(posedge clk_i or cyc_i or stb_i)
begin
if(cyc_i & stb_i)
begin
ack_delayed = 1'b0;
repeat(ACK_DELAY) @(posedge clk_i);
if(cyc_i & stb_i)
ack_delayed = 1'b1;
else
ack_delayed = 1'b0;
end
else
ack_delayed = 1'b0;
end
// --------------------------------------------------------------------
// assign outputs
assign ack_o = ack_delayed;
assign err_o = 1'b0;
assign rty_o = 1'b0;
 
endmodule
/wb_size_bridge/trunk/tb/models/wb_master_model.v
0,0 → 1,510
///////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE rev.B2 Wishbone Master model ////
//// ////
//// ////
//// Author: Richard Herveille ////
//// richard@asics.ws ////
//// www.asics.ws ////
//// ////
//// Downloaded from: http://www.opencores.org/projects/mem_ctrl ////
//// ////
///////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// richard@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
///////////////////////////////////////////////////////////////////////
 
// CVS Log
//
// $Id: wb_master_model.v,v 1.1 2009/02/19 23:51:32 kenagy Exp $
//
// $Date: 2009/02/19 23:51:32 $
// $Revision: 1.1 $
// $Author: kenagy $
// $Locker: $
// $State: Exp $
//
// Change History:
//
 
`timescale 1ns/10ps
 
 
module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty);
 
//
// parameters
//
parameter dwidth = 32;
parameter awidth = 32;
parameter log_level = 3;
 
//
// inputs & outputs
//
input clk, rst;
output [awidth -1:0] adr;
input [dwidth -1:0] din;
output [dwidth -1:0] dout;
output cyc, stb;
output we;
output [dwidth/8 -1:0] sel;
input ack, err, rty;
 
//
// variables
//
reg [awidth -1:0] adr;
reg [dwidth -1:0] dout;
reg cyc, stb;
reg we;
reg [dwidth/8 -1:0] sel;
 
reg [dwidth -1:0] q;
 
integer err_cur_cnt, err_tot_cnt, err_wb_cnt, err_watchdog;
 
 
//
// module body
//
 
// check ack, err and rty assertion
always@(ack or err or rty)
begin
case ({ack, err, rty})
// ok-states
// 3'b000: // none asserted
// 3'b001: // only rty asserted
// 3'b010: // only err asserted
// 3'b100: // only ack asserted
 
// fault-states
3'b011: // oops, err and rty
begin
err_wb_cnt = err_wb_cnt +1;
$display("Wishbone error: ERR_I and RTY_I are both asserted at time %t.", $time);
end
3'b101: // oops, ack and rty
begin
err_wb_cnt = err_wb_cnt +1;
$display("Wishbone error: ACK_I and RTY_I are both asserted at time %t.", $time);
end
3'b110: // oops, ack and err
begin
err_wb_cnt = err_wb_cnt +1;
$display("Wishbone error: ACK_I and ERR_I are both asserted at time %t.", $time);
end
3'b111: // oops, ack, err and rty
begin
err_wb_cnt = err_wb_cnt +1;
$display("Wishbone error: ACK_I, ERR_I and RTY_I are all asserted at time %t.", $time);
end
endcase
if (err_wb_cnt > err_watchdog)
begin
$display("\n!!!-Testbench stopped. More than %d wishbone errors detected.\n", err_watchdog);
$stop;
end
end
 
// initial settings
initial
begin
//adr = 32'hxxxx_xxxx;
//adr = 0;
adr = {awidth{1'bx}};
dout = {dwidth{1'bx}};
cyc = 1'b0;
stb = 1'bx;
we = 1'hx;
sel = {dwidth/8{1'bx}};
 
err_tot_cnt = 0;
err_cur_cnt = 0;
err_wb_cnt = 0;
err_watchdog = 3;
 
#1;
$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");
end
 
 
////////////////////////////
//
// Wishbone write cycle
//
 
task wb_write;
input delay;
integer delay;
input stb_delay;
integer stb_delay;
 
input [awidth -1:0] a;
input [dwidth -1:0] d;
 
begin
if( log_level > 2 )
$display( "###- wb_write: 0x%h @ 0x%h at time %t. ", d, a, $time );
 
// wait initial delay
repeat(delay) @(posedge clk);
 
#1;
// assert cyc_signal
cyc = 1'b1;
stb = 1'b0;
 
// wait for stb_assertion
repeat(stb_delay) @(posedge clk);
 
// assert wishbone signals
adr = a;
dout = d;
stb = 1'b1;
we = 1'b1;
sel = {dwidth/8{1'b1}};
@(posedge clk);
 
// wait for acknowledge from slave
// err is treated as normal ack
// rty is ignored (thus retrying cycle)
while(~ (ack || err)) @(posedge clk);
 
// negate wishbone signals
#1;
cyc = 1'b0;
stb = 1'bx;
adr = {awidth{1'bx}};
dout = {dwidth{1'bx}};
we = 1'hx;
sel = {dwidth/8{1'bx}};
 
end
endtask
 
task wb_write_sel;
input delay;
integer delay;
input stb_delay;
integer stb_delay;
 
input [dwidth/8 -1:0] s;
input [awidth -1:0] a;
input [dwidth -1:0] d;
 
begin
 
if( log_level > 2 )
$display( "###- wb_write_sel: 0x%h @ 0x%h (sel = %b) at time %t. ", d, a, s, $time );
 
// wait initial delay
repeat(delay) @(posedge clk);
 
#1;
// assert cyc_signal
cyc = 1'b1;
stb = 1'b0;
 
// wait for stb_assertion
repeat(stb_delay) @(posedge clk);
 
// assert wishbone signals
adr = a;
dout = d;
stb = 1'b1;
we = 1'b1;
sel = s;
@(posedge clk);
 
// wait for acknowledge from slave
// err is treated as normal ack
// rty is ignored (thus retrying cycle)
while(~ (ack || err)) @(posedge clk);
 
// negate wishbone signals
#1;
cyc = 1'b0;
stb = 1'bx;
adr = {awidth{1'bx}};
dout = {dwidth{1'bx}};
we = 1'hx;
sel = {dwidth/8{1'bx}};
 
end
endtask
 
////////////////////////////
//
// Wishbone read cycle
//
 
task wb_read;
input delay;
integer delay;
input stb_delay;
integer stb_delay;
 
input [awidth -1:0] a;
output [dwidth -1:0] d;
 
begin
 
// wait initial delay
repeat(delay) @(posedge clk);
 
#1;
// assert cyc_signal
cyc = 1'b1;
stb = 1'b0;
 
// wait for stb_assertion
repeat(stb_delay) @(posedge clk);
 
// assert wishbone signals
adr = a;
dout = {dwidth{1'bx}};
stb = 1'b1;
we = 1'b0;
sel = {dwidth/8{1'b1}};
@(posedge clk);
 
// wait for acknowledge from slave
// err is treated as normal ack
// rty is ignored (thus retrying cycle)
while(~ (ack || err)) @(posedge clk);
 
// negate wishbone signals
#1;
cyc = 1'b0;
stb = 1'bx;
adr = {awidth{1'bx}};
dout = {dwidth{1'bx}};
we = 1'hx;
sel = {dwidth/8{1'bx}};
d = din;
 
if( log_level > 2 )
$display( "###- wb_read: 0x%h @ 0x%h at time %t. ", d, a, $time );
end
endtask
 
task wb_read_sel;
input delay;
integer delay;
input stb_delay;
integer stb_delay;
 
input [dwidth/8 -1:0] s;
input [awidth -1:0] a;
output [dwidth -1:0] d;
 
begin
 
// wait initial delay
repeat(delay) @(posedge clk);
 
#1;
// assert cyc_signal
cyc = 1'b1;
stb = 1'b0;
 
// wait for stb_assertion
repeat(stb_delay) @(posedge clk);
 
// assert wishbone signals
adr = a;
dout = {dwidth{1'bx}};
stb = 1'b1;
we = 1'b0;
sel = s;
@(posedge clk);
 
// wait for acknowledge from slave
// err is treated as normal ack
// rty is ignored (thus retrying cycle)
while(~ (ack || err)) @(posedge clk);
 
// negate wishbone signals
#1;
cyc = 1'b0;
stb = 1'bx;
adr = {awidth{1'bx}};
dout = {dwidth{1'bx}};
we = 1'hx;
sel = {dwidth/8{1'bx}};
d = din;
 
if( log_level > 2 )
$display( "###- wb_read_sel: 0x%h @ 0x%h (sel = %b) at time %t. ", d, a, s, $time );
end
endtask
 
////////////////////////////
//
// Wishbone compare cycle
// read data from location and compare with expected data
//
 
task wb_cmp;
input delay;
integer delay;
input stb_delay;
integer stb_delay;
 
input [awidth -1:0] a;
input [dwidth -1:0] d_exp;
 
begin
wb_read (delay, stb_delay, a, q);
 
if (d_exp !== q)
begin
err_tot_cnt = err_tot_cnt +1;
err_cur_cnt = err_cur_cnt +1;
$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q, d_exp, a);
end
 
if (err_tot_cnt > err_watchdog)
begin
$display("\n!!!-Testbench stopped. More than %d errors detected.\n", err_watchdog);
$stop;
end
end
endtask
 
 
task wb_cmp_sel;
input delay;
integer delay;
input stb_delay;
integer stb_delay;
input [dwidth/8 -1:0] s;
input [awidth -1:0] a;
input [dwidth -1:0] d_exp;
 
begin
wb_read_sel (delay, stb_delay, s, a, q);
 
if( (d_exp[7:0] !== q[7:0]) & s == 4'b0001 )
begin
err_tot_cnt = err_tot_cnt +1;
err_cur_cnt = err_cur_cnt +1;
$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[7:0], d_exp[7:0], a);
end
 
if( (d_exp[15:8] !== q[15:8]) & s == 4'b0010 )
begin
err_tot_cnt = err_tot_cnt +1;
err_cur_cnt = err_cur_cnt +1;
$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[15:8], d_exp[15:8], a);
end
 
if( (d_exp[23:16] !== q[23:16]) & s == 4'b0100 )
begin
err_tot_cnt = err_tot_cnt +1;
err_cur_cnt = err_cur_cnt +1;
$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[23:16], d_exp[23:16], a);
end
 
if( (d_exp[31:24] !== q[31:24]) & s == 4'b1000 )
begin
err_tot_cnt = err_tot_cnt +1;
err_cur_cnt = err_cur_cnt +1;
$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[31:24], d_exp[31:24], a);
end
 
if( (d_exp[15:0] !== q[15:0]) & s == 4'b0011 )
begin
err_tot_cnt = err_tot_cnt +1;
err_cur_cnt = err_cur_cnt +1;
$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[15:0], d_exp[15:0], a);
end
 
if( (d_exp[31:16] !== q[31:16]) & s == 4'b1100 )
begin
err_tot_cnt = err_tot_cnt +1;
err_cur_cnt = err_cur_cnt +1;
$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q[31:16], d_exp[31:16], a);
end
 
if( (d_exp !== q) & s == 4'b1111 )
begin
err_tot_cnt = err_tot_cnt +1;
err_cur_cnt = err_cur_cnt +1;
$display( "!!!- Data compare error(%d) at time %t. Received %h, expected %h at address %h", err_tot_cnt, $time, q, d_exp, a);
end
case( s )
4'b0001: ;
4'b0010: ;
4'b0100: ;
4'b1000: ;
4'b0011: ;
4'b1100: ;
4'b1111: ;
default: $display( "!!!- Data compare error(%d) at time %t. Invalad byte select.", err_tot_cnt, $time );
endcase
 
if (err_tot_cnt > err_watchdog)
begin
$display("\n!!!-Testbench stopped. More than %d errors detected.\n", err_watchdog);
$stop;
end
end
endtask
 
 
////////////////////////////
//
// Error counter handlers
//
task set_cur_err_cnt;
input value;
begin
err_cur_cnt = value;
end
endtask
 
task show_cur_err_cnt;
$display("\nCurrent errors detected: %d\n", err_cur_cnt);
endtask
 
task show_tot_err_cnt;
$display("\nTotal errors detected: %d\n", err_tot_cnt);
endtask
always @(posedge clk)
if( err & (cyc == 1'b1) & (stb == 1'b1) )
$display( "!!!- WB Bus Error at time %t. ", $time );
 
endmodule
 
/wb_size_bridge/trunk/src/wb_size_bridge.v
0,0 → 1,310
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
`timescale 1ns/10ps
 
 
module wb_size_bridge(
input wb_hi_clk_i,
input wb_hi_rst_i,
output [31:0] wb_hi_dat_o,
input [31:0] wb_hi_dat_i,
input [31:0] wb_hi_adr_i,
input wb_hi_cyc_i,
input wb_hi_stb_i,
input wb_hi_we_i,
input [3:0] wb_hi_sel_i,
output wb_hi_ack_o,
output wb_hi_err_o,
output wb_hi_rty_o,
 
output wb_lo_clk_o,
output wb_lo_rst_o,
input [15:0] wb_lo_dat_i,
output [15:0] wb_lo_dat_o,
output [31:0] wb_lo_adr_o,
output wb_lo_cyc_o,
output wb_lo_stb_o,
output wb_lo_we_o,
output [1:0] wb_lo_sel_o,
input wb_lo_ack_i,
input wb_lo_err_i,
input wb_lo_rty_i,
input lo_byte_if_i
);
 
// --------------------------------------------------------------------
// state machine encoder
reg [2:0] state_enc;
wire state_enc_3_more_chunks = state_enc[2];
wire state_enc_1_more_chunks = state_enc[1];
wire state_enc_error = state_enc[0];
always @(*)
case( { lo_byte_if_i, wb_hi_sel_i } )
5'b1_0001: state_enc = { 1'b0, 1'b0, 1'b0 };
5'b1_0010: state_enc = { 1'b0, 1'b0, 1'b0 };
5'b1_0100: state_enc = { 1'b0, 1'b0, 1'b0 };
5'b1_1000: state_enc = { 1'b0, 1'b0, 1'b0 };
5'b1_0011: state_enc = { 1'b0, 1'b1, 1'b0 };
5'b1_1100: state_enc = { 1'b0, 1'b1, 1'b0 };
5'b1_1111: state_enc = { 1'b1, 1'b0, 1'b0 };
5'b0_0001: state_enc = { 1'b0, 1'b0, 1'b0 };
5'b0_0010: state_enc = { 1'b0, 1'b0, 1'b0 };
5'b0_0100: state_enc = { 1'b0, 1'b0, 1'b0 };
5'b0_1000: state_enc = { 1'b0, 1'b0, 1'b0 };
5'b0_0011: state_enc = { 1'b0, 1'b0, 1'b0 };
5'b0_1100: state_enc = { 1'b0, 1'b0, 1'b0 };
5'b0_1111: state_enc = { 1'b0, 1'b1, 1'b0 };
default: state_enc = { 1'b0, 1'b0, 1'b1 };
endcase
// --------------------------------------------------------------------
// state machine
 
localparam STATE_DONT_CARE = 4'b????;
localparam STATE_PASS_THROUGH = 4'b0001;
localparam STATE_1_MORE_CHUNK = 4'b0010;
localparam STATE_2_MORE_CHUNK = 4'b0100;
localparam STATE_3_MORE_CHUNK = 4'b1000;
 
reg [3:0] state;
reg [3:0] next_state;
 
always @(posedge wb_hi_clk_i or posedge wb_hi_rst_i)
if(wb_hi_rst_i)
state <= STATE_PASS_THROUGH;
else
state <= next_state;
 
always @(*)
case( state )
STATE_PASS_THROUGH: if( state_enc_1_more_chunks & wb_lo_ack_i & wb_hi_stb_i & wb_hi_cyc_i )
next_state = STATE_1_MORE_CHUNK;
else if( state_enc_3_more_chunks & wb_lo_ack_i & wb_hi_stb_i & wb_hi_cyc_i )
next_state = STATE_3_MORE_CHUNK;
else
next_state = STATE_PASS_THROUGH;
 
STATE_3_MORE_CHUNK: if( wb_lo_ack_i )
next_state = STATE_2_MORE_CHUNK;
else
next_state = STATE_3_MORE_CHUNK;
STATE_2_MORE_CHUNK: if( wb_lo_ack_i )
next_state = STATE_1_MORE_CHUNK;
else
next_state = STATE_2_MORE_CHUNK;
 
STATE_1_MORE_CHUNK: if( wb_lo_ack_i )
next_state = STATE_PASS_THROUGH;
else
next_state = STATE_1_MORE_CHUNK;
default: next_state = STATE_PASS_THROUGH;
endcase
 
// --------------------------------------------------------------------
// byte enable & select
reg [3:0] byte_enable;
localparam BYTE_N_ENABLED = 4'b0000;
localparam BYTE_0_ENABLED = 4'b0001;
localparam BYTE_1_ENABLED = 4'b0010;
localparam BYTE_2_ENABLED = 4'b0100;
localparam BYTE_3_ENABLED = 4'b1000;
reg [1:0] byte_select;
localparam BYTE_0_SELECTED = 2'b00;
localparam BYTE_1_SELECTED = 2'b01;
localparam BYTE_2_SELECTED = 2'b10;
localparam BYTE_3_SELECTED = 2'b11;
localparam BYTE_X_SELECTED = 2'b??;
 
always @(*)
casez( { lo_byte_if_i, wb_hi_sel_i, state } )
{ 1'b1, 4'b0001, STATE_PASS_THROUGH }: byte_enable = BYTE_0_ENABLED;
{ 1'b1, 4'b0010, STATE_PASS_THROUGH }: byte_enable = BYTE_1_ENABLED;
{ 1'b1, 4'b0100, STATE_PASS_THROUGH }: byte_enable = BYTE_2_ENABLED;
{ 1'b1, 4'b1000, STATE_PASS_THROUGH }: byte_enable = BYTE_3_ENABLED;
{ 1'b1, 4'b0011, STATE_PASS_THROUGH }: byte_enable = BYTE_0_ENABLED;
{ 1'b1, 4'b0011, STATE_1_MORE_CHUNK }: byte_enable = BYTE_1_ENABLED;
{ 1'b1, 4'b1100, STATE_PASS_THROUGH }: byte_enable = BYTE_2_ENABLED;
{ 1'b1, 4'b1100, STATE_1_MORE_CHUNK }: byte_enable = BYTE_3_ENABLED;
{ 1'b1, 4'b1111, STATE_PASS_THROUGH }: byte_enable = BYTE_0_ENABLED;
{ 1'b1, 4'b1111, STATE_3_MORE_CHUNK }: byte_enable = BYTE_1_ENABLED;
{ 1'b1, 4'b1111, STATE_2_MORE_CHUNK }: byte_enable = BYTE_2_ENABLED;
{ 1'b1, 4'b1111, STATE_1_MORE_CHUNK }: byte_enable = BYTE_3_ENABLED;
{ 1'b0, 4'b????, STATE_DONT_CARE }: byte_enable = BYTE_N_ENABLED;
default: byte_enable = BYTE_N_ENABLED;
endcase
 
always @(*)
case( byte_enable )
BYTE_0_ENABLED: byte_select = BYTE_0_SELECTED;
BYTE_1_ENABLED: byte_select = BYTE_1_SELECTED;
BYTE_2_ENABLED: byte_select = BYTE_2_SELECTED;
BYTE_3_ENABLED: byte_select = BYTE_3_SELECTED;
default: byte_select = 2'bxx;
endcase
 
// --------------------------------------------------------------------
// word enable & select
reg [1:0] word_enable;
localparam WORD_N_ENABLED = 2'b00;
localparam WORD_0_ENABLED = 2'b01;
localparam WORD_1_ENABLED = 2'b10;
reg word_select;
localparam WORD_0_SELECTED = 1'b0;
localparam WORD_1_SELECTED = 1'b1;
localparam WORD_X_SELECTED = 1'b?;
 
always @(*)
casez( { lo_byte_if_i, wb_hi_sel_i, state } )
{ 1'b0, 4'b0011, STATE_PASS_THROUGH }: word_enable = WORD_0_ENABLED;
{ 1'b0, 4'b1100, STATE_PASS_THROUGH }: word_enable = WORD_1_ENABLED;
{ 1'b0, 4'b0001, STATE_PASS_THROUGH }: word_enable = WORD_0_ENABLED;
{ 1'b0, 4'b0010, STATE_PASS_THROUGH }: word_enable = WORD_0_ENABLED;
{ 1'b0, 4'b0100, STATE_PASS_THROUGH }: word_enable = WORD_1_ENABLED;
{ 1'b0, 4'b1000, STATE_PASS_THROUGH }: word_enable = WORD_1_ENABLED;
{ 1'b0, 4'b1111, STATE_PASS_THROUGH }: word_enable = WORD_0_ENABLED;
{ 1'b0, 4'b1111, STATE_1_MORE_CHUNK }: word_enable = WORD_1_ENABLED;
{ 1'b1, 4'b????, STATE_DONT_CARE }: word_enable = WORD_N_ENABLED;
default: word_enable = WORD_N_ENABLED;
endcase
 
always @(*)
case( word_enable )
WORD_0_ENABLED: word_select = WORD_0_SELECTED;
WORD_1_ENABLED: word_select = WORD_1_SELECTED;
default: word_select = 1'bx;
endcase
 
// --------------------------------------------------------------------
// write mux
reg [1:0] byte_write_mux_enc;
always @(*)
casez( {lo_byte_if_i, byte_select, word_select} )
{ 1'b1, BYTE_0_SELECTED, WORD_X_SELECTED }: byte_write_mux_enc = 2'b00;
{ 1'b1, BYTE_1_SELECTED, WORD_X_SELECTED }: byte_write_mux_enc = 2'b01;
{ 1'b1, BYTE_2_SELECTED, WORD_X_SELECTED }: byte_write_mux_enc = 2'b10;
{ 1'b1, BYTE_3_SELECTED, WORD_X_SELECTED }: byte_write_mux_enc = 2'b11;
{ 1'b0, BYTE_X_SELECTED, WORD_0_SELECTED }: byte_write_mux_enc = 2'b00;
{ 1'b0, BYTE_X_SELECTED, WORD_1_SELECTED }: byte_write_mux_enc = 2'b10;
default: byte_write_mux_enc = 2'b00;
endcase
reg [7:0] byte_write_mux;
 
always @(*)
case( byte_write_mux_enc )
2'b00: byte_write_mux = wb_hi_dat_i[7:0];
2'b01: byte_write_mux = wb_hi_dat_i[15:8];
2'b10: byte_write_mux = wb_hi_dat_i[23:16];
2'b11: byte_write_mux = wb_hi_dat_i[31:24];
default: byte_write_mux = wb_hi_dat_i[7:0];
endcase
reg [7:0] word_write_mux;
 
always @(*)
case( word_select )
WORD_0_SELECTED: word_write_mux = wb_hi_dat_i[15:8];
WORD_1_SELECTED: word_write_mux = wb_hi_dat_i[31:24];
default: word_write_mux = wb_hi_dat_i[15:8];
endcase
// --------------------------------------------------------------------
// read buffer & bypass mux
// low side input mux
wire [7:0] read_word_lo_mux = wb_lo_dat_i[7:0];
wire [7:0] read_word_hi_mux = ( word_enable[0] | word_enable[1] )? wb_lo_dat_i[15:8] : wb_lo_dat_i[7:0];
reg [31:0] read_buffer;
wire read_buffer_0_enable = (byte_enable[0] | word_enable[0]) & ~wb_hi_we_i;
wire read_buffer_1_enable = (byte_enable[1] | word_enable[0]) & ~wb_hi_we_i;
wire read_buffer_2_enable = (byte_enable[2] | word_enable[1]) & ~wb_hi_we_i;
wire read_buffer_3_enable = (byte_enable[3] | word_enable[1]) & ~wb_hi_we_i;
always @(posedge wb_hi_clk_i)
if( read_buffer_0_enable )
read_buffer[7:0] <= read_word_lo_mux;
always @(posedge wb_hi_clk_i)
if( read_buffer_1_enable )
read_buffer[15:8] <= read_word_hi_mux;
always @(posedge wb_hi_clk_i)
if( read_buffer_2_enable )
read_buffer[23:16] <= read_word_lo_mux;
always @(posedge wb_hi_clk_i)
if( read_buffer_3_enable )
read_buffer[31:24] <= read_word_hi_mux;
wire [31:0] read_buffer_mux;
// bypass read mux
assign read_buffer_mux[7:0] = read_buffer_0_enable ? read_word_lo_mux : read_buffer[7:0];
assign read_buffer_mux[15:8] = read_buffer_1_enable ? read_word_hi_mux : read_buffer[15:8];
assign read_buffer_mux[23:16] = read_buffer_2_enable ? read_word_lo_mux : read_buffer[23:16];
assign read_buffer_mux[31:24] = read_buffer_3_enable ? read_word_hi_mux : read_buffer[31:24];
// --------------------------------------------------------------------
// misc logic
wire [1:0] lo_addr_bits;
assign lo_addr_bits = ( |byte_enable ) ? byte_select : { word_select, 1'b0 };
wire all_done = ( ~(|state_enc) & (state == STATE_PASS_THROUGH) ) |
( |state_enc & (state == STATE_1_MORE_CHUNK) );
reg [1:0] wb_lo_sel_r;
always @(*)
casez( { lo_byte_if_i, wb_hi_sel_i, state } )
{ 1'b0, 4'b0001, STATE_PASS_THROUGH }: wb_lo_sel_r = 2'b01;
{ 1'b0, 4'b0010, STATE_PASS_THROUGH }: wb_lo_sel_r = 2'b10;
{ 1'b0, 4'b0100, STATE_PASS_THROUGH }: wb_lo_sel_r = 2'b01;
{ 1'b0, 4'b1000, STATE_PASS_THROUGH }: wb_lo_sel_r = 2'b10;
default: wb_lo_sel_r = 2'b11;
endcase
 
// --------------------------------------------------------------------
// output port assignments
assign wb_hi_dat_o = read_buffer_mux;
assign wb_hi_err_o = (wb_lo_err_i | state_enc_error) & wb_hi_stb_i & wb_hi_cyc_i;
assign wb_hi_rty_o = wb_lo_rty_i;
assign wb_hi_ack_o = all_done & wb_hi_stb_i & wb_hi_cyc_i & wb_lo_ack_i;
assign wb_lo_adr_o = { wb_hi_adr_i[31:2], lo_addr_bits };
assign wb_lo_clk_o = wb_hi_clk_i;
assign wb_lo_rst_o = wb_hi_rst_i;
assign wb_lo_cyc_o = wb_hi_cyc_i;
assign wb_lo_stb_o = wb_hi_stb_i;
assign wb_lo_we_o = wb_hi_we_i & wb_hi_stb_i & wb_hi_cyc_i;
assign wb_lo_dat_o = {word_write_mux, byte_write_mux};
assign wb_lo_sel_o = wb_lo_sel_r;
 
endmodule
 
 
/wb_size_bridge/trunk/src/asram_if.v
0,0 → 1,83
//
//
//
 
module asram_if(
inout [15:0] sram_dq, // SRAM Data bus 16 Bits
output [17:0] sram_addr, // SRAM Address bus 18 Bits
output sram_ub_n, // SRAM High-byte Data Mask
output sram_lb_n, // SRAM Low-byte Data Mask
output sram_we_n, // SRAM Write Enable
output sram_ce_n, // SRAM Chip Enable
output sram_oe_n, // SRAM Output Enable
input wb_clk_i, // WISHBONE interface
input wb_rst_i,
input [18:0] wb_adr_i,
input [31:0] wb_dat_i,
input wb_we_i,
input wb_stb_i,
input wb_cyc_i,
input [3:0] wb_sel_i,
output [31:0] wb_dat_o,
output wb_ack_o
);
 
//---------------------------------------------------
// wb_size_bridge
wire [15:0] wb_lo_dat_o;
wire [31:0] wb_lo_adr_o;
wire wb_lo_cyc_o;
wire wb_lo_stb_o;
wire wb_lo_we_o;
wire [1:0] wb_lo_sel_o;
wire wb_lo_ack_i = 1'b1;
wire wb_lo_err_i = 1'b0;
wire wb_lo_rty_i = 1'b0;
wb_size_bridge i_wb_size_bridge(
.wb_hi_clk_i(wb_clk_i),
.wb_hi_rst_i(wb_rst_i),
.wb_hi_dat_o(wb_dat_o),
.wb_hi_dat_i(wb_dat_i),
.wb_hi_adr_i( {13'h0000, wb_adr_i} ),
.wb_hi_cyc_i(wb_cyc_i),
.wb_hi_stb_i(wb_stb_i),
.wb_hi_we_i(wb_we_i),
.wb_hi_sel_i(wb_sel_i),
.wb_hi_ack_o(wb_ack_o),
.wb_hi_err_o(),
.wb_hi_rty_o(),
.wb_lo_clk_o(),
.wb_lo_rst_o(),
.wb_lo_dat_i(sram_dq),
.wb_lo_dat_o(wb_lo_dat_o),
.wb_lo_adr_o(wb_lo_adr_o),
.wb_lo_cyc_o(wb_lo_cyc_o),
.wb_lo_stb_o(wb_lo_stb_o),
.wb_lo_we_o(wb_lo_we_o),
.wb_lo_sel_o(wb_lo_sel_o),
.wb_lo_ack_i(wb_lo_ack_i),
.wb_lo_err_i(wb_lo_err_i),
.wb_lo_rty_i(wb_lo_rty_i),
.lo_byte_if_i(1'b0)
);
//---------------------------------------------------
// outputs
assign sram_dq = wb_lo_we_o ? wb_lo_dat_o : 16'hzz;
assign sram_addr = wb_lo_adr_o[18:1];
assign sram_ub_n = ~wb_lo_sel_o[1];
assign sram_lb_n = ~wb_lo_sel_o[0];
assign sram_we_n = ~wb_lo_we_o;
// assign sram_ce_n = ~(wb_lo_stb_o & wb_lo_cyc_o);
assign sram_ce_n = 1'b0;
assign sram_oe_n = wb_lo_we_o;
endmodule
 
 
/wb_size_bridge/trunk/src/async_mem_if.v
0,0 → 1,253
//
//
//
 
 
module async_mem_if( async_dq, async_addr, async_ub_n, async_lb_n,
async_we_n, async_ce_n, async_oe_n,
wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i,
wb_we_i, wb_stb_i, wb_cyc_i, wb_sel_i,
wb_dat_o, wb_ack_o,
ce_setup, op_hold, ce_hold,
big_endian_if_i, lo_byte_if_i
);
 
parameter AW = 32;
parameter DW = 8;
 
inout [(DW-1):0] async_dq;
output [(AW-1):0] async_addr;
output async_ub_n;
output async_lb_n;
output async_we_n;
output async_ce_n;
output async_oe_n;
input wb_clk_i;
input wb_rst_i;
input [31:0] wb_adr_i;
input [31:0] wb_dat_i;
input wb_we_i;
input wb_stb_i;
input wb_cyc_i;
input [3:0] wb_sel_i;
output [31:0] wb_dat_o;
output wb_ack_o;
input [3:0] ce_setup;
input [3:0] op_hold; // do not set to zero.
input [3:0] ce_hold;
input big_endian_if_i;
input lo_byte_if_i;
 
 
//---------------------------------------------------
// big endian bridge
 
wire [31:0] beb_wb_dat_i;
assign beb_wb_dat_i[7:0] = big_endian_if_i ? wb_dat_i[31:24] : wb_dat_i[7:0];
assign beb_wb_dat_i[15:8] = big_endian_if_i ? wb_dat_i[23:16] : wb_dat_i[15:8];
assign beb_wb_dat_i[23:16] = big_endian_if_i ? wb_dat_i[15:8] : wb_dat_i[23:16];
assign beb_wb_dat_i[31:24] = big_endian_if_i ? wb_dat_i[7:0] : wb_dat_i[31:24];
 
wire [31:0] beb_wb_dat_o;
assign wb_dat_o[7:0] = big_endian_if_i ? beb_wb_dat_o[31:24] : beb_wb_dat_o[7:0];
assign wb_dat_o[15:8] = big_endian_if_i ? beb_wb_dat_o[23:16] : beb_wb_dat_o[15:8];
assign wb_dat_o[23:16] = big_endian_if_i ? beb_wb_dat_o[15:8] : beb_wb_dat_o[23:16];
assign wb_dat_o[31:24] = big_endian_if_i ? beb_wb_dat_o[7:0] : beb_wb_dat_o[31:24];
 
wire [3:0] beb_wb_sel_i;
assign beb_wb_sel_i[0] = big_endian_if_i ? wb_sel_i[3] : wb_sel_i[0];
assign beb_wb_sel_i[1] = big_endian_if_i ? wb_sel_i[2] : wb_sel_i[1];
assign beb_wb_sel_i[2] = big_endian_if_i ? wb_sel_i[1] : wb_sel_i[2];
assign beb_wb_sel_i[3] = big_endian_if_i ? wb_sel_i[0] : wb_sel_i[3];
 
 
//---------------------------------------------------
// wb_size_bridge
wire [15:0] wb_lo_dat_o;
wire [15:0] wb_lo_dat_i;
wire [31:0] wb_lo_adr_o;
wire wb_lo_cyc_o;
wire wb_lo_stb_o;
wire wb_lo_we_o;
wire [1:0] wb_lo_sel_o;
wire wb_lo_ack_i;
wire wb_lo_err_i = 1'b0;
wire wb_lo_rty_i = 1'b0;
 
 
wb_size_bridge i_wb_size_bridge(
.wb_hi_clk_i(wb_clk_i),
.wb_hi_rst_i(wb_rst_i),
.wb_hi_dat_o(beb_wb_dat_o),
.wb_hi_dat_i(beb_wb_dat_i),
.wb_hi_adr_i( wb_adr_i ),
.wb_hi_cyc_i(wb_cyc_i),
.wb_hi_stb_i(wb_stb_i),
.wb_hi_we_i(wb_we_i),
.wb_hi_sel_i(beb_wb_sel_i),
.wb_hi_ack_o(wb_ack_o),
.wb_hi_err_o(),
.wb_hi_rty_o(),
 
.wb_lo_clk_o(),
.wb_lo_rst_o(),
.wb_lo_dat_i(wb_lo_dat_i),
.wb_lo_dat_o(wb_lo_dat_o),
.wb_lo_adr_o(wb_lo_adr_o),
.wb_lo_cyc_o(wb_lo_cyc_o),
.wb_lo_stb_o(wb_lo_stb_o),
.wb_lo_we_o(wb_lo_we_o),
.wb_lo_sel_o(wb_lo_sel_o),
.wb_lo_ack_i(wb_lo_ack_i),
.wb_lo_err_i(wb_lo_err_i),
.wb_lo_rty_i(wb_lo_rty_i),
 
.lo_byte_if_i(lo_byte_if_i)
);
 
 
// --------------------------------------------------------------------
// state machine inputs
 
wire zero_ce_setup = (ce_setup == 4'h0);
wire zero_ce_hold = (ce_hold == 4'h0);
wire wait_for_counter;
 
 
// --------------------------------------------------------------------
// state machine
 
localparam STATE_DONT_CARE = 4'b????;
localparam STATE_IDLE = 4'b0001;
localparam STATE_CE_SETUP = 4'b0010;
localparam STATE_OP_HOLD = 4'b0100;
localparam STATE_CE_HOLD = 4'b1000;
 
reg [3:0] state;
reg [3:0] next_state;
 
always @(posedge wb_clk_i or posedge wb_rst_i)
if(wb_rst_i)
state <= STATE_IDLE;
else
state <= next_state;
 
always @(*)
case( state )
STATE_IDLE: if( wb_stb_i & wb_cyc_i )
if( zero_ce_setup )
next_state = STATE_OP_HOLD;
else
next_state = STATE_CE_SETUP;
else
next_state = STATE_IDLE;
 
STATE_CE_SETUP: if( wait_for_counter )
next_state = STATE_CE_SETUP;
else
next_state = STATE_OP_HOLD;
 
STATE_OP_HOLD: if( wait_for_counter )
next_state = STATE_OP_HOLD;
else
if( zero_ce_hold )
next_state = STATE_IDLE;
else
next_state = STATE_CE_HOLD;
 
STATE_CE_HOLD: if( wait_for_counter )
next_state = STATE_CE_HOLD;
else
next_state = STATE_IDLE;
 
default: next_state = STATE_IDLE;
endcase
 
 
// --------------------------------------------------------------------
// state machine outputs
 
wire assert_ce = (state != STATE_IDLE);
// wire assert_op = (state == STATE_OP_HOLD) | (state == STATE_CE_HOLD);
wire assert_op = (state == STATE_OP_HOLD);
 
assign wb_lo_ack_i = ( (state == STATE_OP_HOLD) & ~wait_for_counter & zero_ce_hold) |
( (state == STATE_CE_HOLD) & ~wait_for_counter );
 
 
//---------------------------------------------------
// async_dq_buffer
reg [(DW-1):0] async_dq_buffer;
wire async_dq_buffer_en = (state == STATE_OP_HOLD);
 
always @(posedge wb_clk_i)
if(async_dq_buffer_en)
async_dq_buffer <= async_dq;
else
async_dq_buffer <= async_dq_buffer;
 
//---------------------------------------------------
// bypass_mux
 
wire bypass_mux_en = (state == STATE_OP_HOLD) & zero_ce_hold;
wire [(DW-1):0] bypass_mux;
 
assign bypass_mux = bypass_mux_en ? async_dq : async_dq_buffer;
 
 
// --------------------------------------------------------------------
// wait counter mux
reg [3:0] counter_mux;
 
always @(*)
case( next_state )
STATE_CE_SETUP: counter_mux = ce_setup;
STATE_OP_HOLD: counter_mux = op_hold;
STATE_CE_HOLD: counter_mux = ce_hold;
default: counter_mux = 4'bxxxx;
endcase
 
 
// --------------------------------------------------------------------
// wait counter
reg [3:0] counter;
wire counter_load = ~(state == next_state);
 
always @(posedge wb_clk_i)
if( counter_load )
counter <= counter_mux - 1'b1;
else
counter <= counter - 1'b1;
 
assign wait_for_counter = (counter != 4'h0);
 
 
//---------------------------------------------------
// outputs
 
generate
if( DW == 16 )
begin
assign async_dq = wb_lo_we_o ? wb_lo_dat_o : 16'hzz;
assign async_addr = wb_lo_adr_o[AW:1];
assign wb_lo_dat_i = bypass_mux;
end
else
begin
assign async_dq = wb_lo_we_o ? wb_lo_dat_o : 8'hz;
assign async_addr = wb_lo_adr_o[(AW-1):0];
assign wb_lo_dat_i = {8'h00, bypass_mux};
end
endgenerate
 
assign async_ub_n = ~wb_lo_sel_o[1];
assign async_lb_n = ~wb_lo_sel_o[0];
assign async_we_n = ~( wb_lo_we_o & assert_op );
assign async_ce_n = ~( wb_stb_i & wb_cyc_i & assert_ce );
assign async_oe_n = ~( ~wb_lo_we_o & assert_op );
 
 
endmodule
 
 

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