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URL https://opencores.org/ocsvn/deflatecore/deflatecore/trunk

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    from Rev 10 to Rev 11
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Rev 10 → Rev 11

/trunk/search.vhd
10,7 → 10,7
-- Revision 0.01 - File Created
-- Additional Comments:
-- Slightly modified approach to use a hash search
-- Instead of searching a chain of hashes a table of the hashes generated by the
-- Instead of searching a chain of hash keys in a table of the hashes generated by the
-- minimum length chains is maintained
--------------------------------------------------------------------------------
library IEEE;
64,13 → 64,10
Port
(
Table_Start : in std_logic_vector ( log2(Length_of_Table) downto 0); -- Starting Address of the data table
Table_End : in std_logic_vector ( log2(Length_of_Table) downto 0); -- Ending address of the table
Hash_key : in std_logic_vector ( (Hash_Width -1) downto 0); -- Accept a 32 bit hash input
Hash_inout : inout std_logic_vector ( (Data_Width -1) downto 0); -- Hash key read/write to be stored
Datain : in std_logic_vector ( (Data_Width -1) downto 0); -- Data input from byte stream
Clock, -- Clock input
Output_E : in bit; -- Enable/~Tristate output
Table_Match : out std_logic_vector ( log2(Length_of_Table) downto 0); -- Address at which the match was found
Match , -- when 1 hash key generated matches hash from table
Write_Hash : out bit -- no match read the next byte from memory
);
77,6 → 74,7
end stream_hash;
--The search is a one to one search of the table
--The hash keys are stored FIFO unsorted in the table.
--Very inefficent as it searches the entire table from start to finishto see if the hash value is present
--it is the easiest method and needs to be changed to a sorted store-search.
architecture one_to_one of stream_hash is
component HashChain
87,26 → 85,32
Port(
Hash_o : out std_logic_vector (Hash_Width - 1 downto 0); -- Hash value of previous data
Data_in : in std_logic_vector (Data_Width -1 downto 0); -- Data input from byte stream
Hash_Generated: out bit;
Clock, -- Clock
Reset, -- Reset
Output_E : in bit -- Output Enable
);
end component;
--hg1 is used for the last generated hash key
--hg2 and hg3 are used for storing the previous hash keys
--hg4 is used while matcching longer lenths and also uses the second hash key generator
signal hg1,hg2,hg3,hg4 : std_logic_vector ( (Hash_Width -1) downto 0); -- Accept a 32 bit hash input
signal hashink : std_logic_vector (Data_Width-1 downto 0);
signal clk,rst,ope, match1, read, ist : bit;
signal clk,rst,ope, match1, read, ist, hashr, hashr2 : bit;
signal mode:integer;
 
begin
glink:HashChain port map (Hash_o => hg1,
Data_in => Datain,
Hash_Generated =>hashr,
Clock=>clk, -- Clock
Reset=>rst, -- Reset
Output_E =>ope -- Output Enable
);
--Second hash generator to concurrently search hash values longer than 4
glink1:HashChain port map (Hash_o => hg2,
glink1:HashChain port map (Hash_o => hg4,
Data_in => hg1,
Hash_Generated => hashr2,
Clock=>clk, -- Clock
Reset=>rst, -- Reset
Output_E =>ope -- Output Enable
126,17 → 130,11
--3. If its a match then output the location of the hash value
3 when match1 ='1' else
4;
 
 
--State machine using the above states
Process (mode, Clock)
begin
case mode is
when 0 =>
match1 <='0';
read <='1';
when 1 =>
 
when others =>
 
end case;
end process;
end one_to_one;

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