URL
https://opencores.org/ocsvn/fir_wishbone/fir_wishbone/trunk
Subversion Repositories fir_wishbone
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- This comparison shows the changes necessary to convert path
/
- from Rev 10 to Rev 11
- ↔ Reverse comparison
Rev 10 → Rev 11
/fir_wishbone/trunk/tester/tb_fir.vhdl
31,7 → 31,7
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
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entity tb_fir is generic(order:positive:=30; width:positive:=16); |
entity tb_fir is generic(order:positive:=30); --; width:positive:=16); |
port( |
-- clk:in std_ulogic:='0'; |
-- nRst:in std_ulogic:='0'; |
42,7 → 42,7
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architecture rtl of tb_fir is |
signal reset:std_ulogic:='0'; |
signal u:signed(16-1 downto 0); |
signal u:signed(y'range); |
signal trig:std_logic; |
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/* synthesis translate_off */ |
91,7 → 91,7
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filter: entity work.fir(rtl) |
generic map(order=>order, width=>width) |
generic map(order=>order) --, width=>width) |
port map( |
reset=>reset, |
clk=>clk, |
127,9 → 127,9
trig<='1' when count<300 else '0'; -- Stop SignalTap Triggering after 300 counts, Total data=280 |
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/* SignalTap debugger. */ |
dbgSignals(width-1 downto 0)<=std_ulogic_vector(u); -- u:16bits |
dbgSignals(width*2-1 downto width)<=std_ulogic_vector(y); -- y:32bits |
dbgSignals(8+width*2 downto width*2)<=std_ulogic_vector(count); --9bits (300<512) |
dbgSignals(u'range)<=std_ulogic_vector(u); -- u:16bits |
dbgSignals(u'length*2-1 downto u'length)<=std_ulogic_vector(y); -- y:32bits |
dbgSignals(8+u'length*2 downto u'length*2)<=std_ulogic_vector(count); --9bits (300<512) |
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/* debugger: entity work.stp(syn) port map( |
acq_clk=>clk, |