URL
https://opencores.org/ocsvn/mpdma/mpdma/trunk
Subversion Repositories mpdma
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 10 to Rev 11
- ↔ Reverse comparison
Rev 10 → Rev 11
/trunk/system.mss
10,7 → 10,13
PARAMETER STDOUT = RS232_Uart_1 |
END |
|
BEGIN OS |
PARAMETER OS_NAME = standalone |
PARAMETER OS_VER = 1.00.a |
PARAMETER PROC_INSTANCE = microblaze_2 |
END |
|
|
BEGIN PROCESSOR |
PARAMETER DRIVER_NAME = cpu |
PARAMETER DRIVER_VER = 1.00.a |
20,7 → 26,15
PARAMETER XMDSTUB_PERIPHERAL = debug_module |
END |
|
BEGIN PROCESSOR |
PARAMETER DRIVER_NAME = cpu |
PARAMETER DRIVER_VER = 1.00.a |
PARAMETER HW_INSTANCE = microblaze_2 |
PARAMETER COMPILER = mb-gcc |
PARAMETER ARCHIVER = mb-ar |
END |
|
|
BEGIN DRIVER |
PARAMETER DRIVER_NAME = opbarb |
PARAMETER DRIVER_VER = 1.02.a |
36,13 → 50,13
BEGIN DRIVER |
PARAMETER DRIVER_NAME = bram |
PARAMETER DRIVER_VER = 1.00.a |
PARAMETER HW_INSTANCE = dlmb_cntlr |
PARAMETER HW_INSTANCE = dlmb_cntlr0 |
END |
|
BEGIN DRIVER |
PARAMETER DRIVER_NAME = bram |
PARAMETER DRIVER_VER = 1.00.a |
PARAMETER HW_INSTANCE = ilmb_cntlr |
PARAMETER HW_INSTANCE = ilmb_cntlr0 |
END |
|
BEGIN DRIVER |
93,7 → 107,31
PARAMETER HW_INSTANCE = dcm_1 |
END |
|
BEGIN DRIVER |
PARAMETER DRIVER_NAME = bram |
PARAMETER DRIVER_VER = 1.00.a |
PARAMETER HW_INSTANCE = dlmb_cntlr2 |
END |
|
BEGIN DRIVER |
PARAMETER DRIVER_NAME = bram |
PARAMETER DRIVER_VER = 1.00.a |
PARAMETER HW_INSTANCE = ilmb_cntlr2 |
END |
|
BEGIN DRIVER |
PARAMETER DRIVER_NAME = generic |
PARAMETER DRIVER_VER = 1.00.a |
PARAMETER HW_INSTANCE = fifo02 |
END |
|
BEGIN DRIVER |
PARAMETER DRIVER_NAME = generic |
PARAMETER DRIVER_VER = 1.00.a |
PARAMETER HW_INSTANCE = fifo20 |
END |
|
|
BEGIN LIBRARY |
PARAMETER LIBRARY_NAME = xilfatfs |
PARAMETER LIBRARY_VER = 1.00.a |
/trunk/mb-dct/fifo_link.h
0,0 → 1,91
////////////////////////////////////////////////////////////////////////////// |
// |
// *************************************************************************** |
// ** ** |
// ** Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. ** |
// ** ** |
// ** You may copy and modify these files for your own internal use solely ** |
// ** with Xilinx programmable logic devices and Xilinx EDK system or ** |
// ** create IP modules solely for Xilinx programmable logic devices and ** |
// ** Xilinx EDK system. No rights are granted to distribute any files ** |
// ** unless they are distributed in Xilinx programmable logic devices. ** |
// ** ** |
// *************************************************************************** |
// |
////////////////////////////////////////////////////////////////////////////// |
// Filename: D:\thesis\FIFO1\drivers\fifo_link_v1_00_a\src\\fifo_link.h |
// Version: 1.00.a |
// Description: fifo_link (FIFO link) Driver Header File |
// Date: Fri Oct 06 17:25:29 2006 (by Create and Import Peripheral Wizard) |
////////////////////////////////////////////////////////////////////////////// |
|
#ifndef FIFO_LINK_H |
#define FIFO_LINK_H |
|
#ifdef __MICROBLAZE__ |
#include "mb_interface.h" |
#define write_into_fsl(val, id) microblaze_bwrite_datafsl(val, id) |
#define read_from_fsl(val, id) microblaze_bread_datafsl(val, id) |
#else |
#include "xpseudo_asm_gcc.h" |
#define write_into_fsl(val, id) putfsl(val, id) |
#define read_from_fsl(val, id) getfsl(val, id) |
#endif |
|
/* |
* A macro for accessing FSL peripheral. |
* |
* This example driver writes all the data in the input arguments |
* into the input FSL bus through blocking wrties. FSL peripheral will |
* automatically read from the FSL bus. Once all the inputs |
* have been written, the output from the FSL peripheral is read |
* into output arguments through blocking reads. |
* |
* Arguments: |
* output_slot_id |
* Compile time constant indicating FSL slot from |
* which output data is read. Defined in |
* xparameters.h . |
* input_slot_id |
* Compile time constant indicating FSL slot into |
* which input data is written. Defined in |
* xparameters.h . |
* input_0 An array of unsigned integers. Array size is 1 |
* output_0 An array of unsigned integers. Array size is 1 |
* |
* Caveats: |
* The output_slot_id and input_slot_id arguments must be |
* constants available at compile time. Do not pass |
* variables for these arguments. |
* |
* Since this is a macro, using it too many times will |
* increase the size of your application. In such cases, |
* or when this macro is too simplistic for your |
* application you may want to create your own instance |
* specific driver function (not a macro) using the |
* macros defined in this file and the slot |
* identifiers defined in xparameters.h . Please see the |
* example code (fifo_link_app.c) for details. |
*/ |
|
#define fifo_link(\ |
input_slot_id,\ |
output_slot_id,\ |
input_0, \ |
output_0 \ |
)\ |
{\ |
int i;\ |
\ |
for (i=0; i<1; i++)\ |
{\ |
write_into_fsl(input_0[i], input_slot_id);\ |
}\ |
\ |
for (i=0; i<1; i++)\ |
{\ |
read_from_fsl(output_0[i], output_slot_id);\ |
}\ |
} |
|
#endif |
/trunk/system.mhs
1,23 → 1,17
# |
# ############################################################################## |
# |
# Created by Base System Builder Wizard for Xilinx EDK 7.1.2 Build EDK_H.12.5.1 |
# |
# Thu Oct 19 14:57:41 2006 |
# |
# Target Board: Xilinx XUP Virtex-II Pro Development System Rev C |
# Family: virtex2p |
# Device: xc2vp30 |
# Package: ff896 |
# Speed Grade: -7 |
# |
# Processor: Microblaze |
# System clock frequency: 100.000000 MHz |
# Debug interface: On-Chip HW Debug Module |
# On Chip Memory : 64 KB |
# Total Off Chip Memory : 256 MB |
# - DDR_SDRAM_32Mx64 Single Rank = 256 MB |
# |
# - DDR_SDRAM_32Mx64 Single Rank = 256 MB |
# ############################################################################## |
|
|
27,22 → 21,22
PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX, DIR = INPUT |
PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX, DIR = OUTPUT |
PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR = INPUT |
PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA, DIR = OUTPUT, VEC = [6:0] |
PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD, DIR = INOUT, VEC = [15:0] |
PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA, VEC = [6:0], DIR = OUTPUT |
PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD, VEC = [15:0], DIR = INOUT |
PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR = OUTPUT |
PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR = OUTPUT |
PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR = OUTPUT |
PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR = INPUT |
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk, DIR = OUTPUT, VEC = [0:2] |
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn, DIR = OUTPUT, VEC = [0:2] |
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr, DIR = OUTPUT, VEC = [0:12] |
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr, DIR = OUTPUT, VEC = [0:1] |
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk, VEC = [0:2], DIR = OUTPUT |
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn, VEC = [0:2], DIR = OUTPUT |
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr, VEC = [0:12], DIR = OUTPUT |
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr, VEC = [0:1], DIR = OUTPUT |
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn, DIR = OUTPUT |
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn, DIR = OUTPUT |
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn, DIR = OUTPUT |
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM, DIR = OUTPUT, VEC = [0:7] |
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS, DIR = INOUT, VEC = [0:7] |
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ, DIR = INOUT, VEC = [0:63] |
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM, VEC = [0:7], DIR = OUTPUT |
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS, VEC = [0:7], DIR = INOUT |
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ, VEC = [0:63], DIR = INOUT |
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE, DIR = OUTPUT |
PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn, DIR = OUTPUT |
PORT fpga_0_DDR_CLK_FB = ddr_feedback_s, DIR = INPUT |
58,10 → 52,13
PARAMETER C_NUMBER_OF_PC_BRK = 2 |
PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1 |
PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1 |
BUS_INTERFACE DLMB = dlmb |
BUS_INTERFACE ILMB = ilmb |
PARAMETER C_FSL_LINKS = 1 |
BUS_INTERFACE DLMB = dlmb0 |
BUS_INTERFACE ILMB = ilmb0 |
BUS_INTERFACE DOPB = mb_opb |
BUS_INTERFACE IOPB = mb_opb |
BUS_INTERFACE MFSL0 = fsl0m |
BUS_INTERFACE SFSL0 = fsl0s |
PORT CLK = sys_clk_s |
PORT DBG_CAPTURE = DBG_CAPTURE_s |
PORT DBG_CLK = DBG_CLK_s |
71,6 → 68,23
PORT DBG_UPDATE = DBG_UPDATE_s |
END |
|
BEGIN microblaze |
PARAMETER INSTANCE = microblaze_2 |
PARAMETER HW_VER = 4.00.a |
PARAMETER C_DEBUG_ENABLED = 1 |
PARAMETER C_NUMBER_OF_PC_BRK = 2 |
PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1 |
PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1 |
PARAMETER C_FSL_LINKS = 1 |
BUS_INTERFACE DLMB = dlmb2 |
BUS_INTERFACE ILMB = ilmb2 |
BUS_INTERFACE DOPB = mb_opb |
BUS_INTERFACE IOPB = mb_opb |
BUS_INTERFACE SFSL0 = fsl2s |
BUS_INTERFACE MFSL0 = fsl2m |
PORT CLK = sys_clk_s |
END |
|
BEGIN opb_v20 |
PARAMETER INSTANCE = mb_opb |
PARAMETER HW_VER = 1.10.c |
98,7 → 112,7
END |
|
BEGIN lmb_v10 |
PARAMETER INSTANCE = ilmb |
PARAMETER INSTANCE = ilmb0 |
PARAMETER HW_VER = 1.00.a |
PARAMETER C_EXT_RESET_HIGH = 0 |
PORT SYS_Rst = sys_rst_s |
106,7 → 120,7
END |
|
BEGIN lmb_v10 |
PARAMETER INSTANCE = dlmb |
PARAMETER INSTANCE = dlmb0 |
PARAMETER HW_VER = 1.00.a |
PARAMETER C_EXT_RESET_HIGH = 0 |
PORT SYS_Rst = sys_rst_s |
113,31 → 127,108
PORT LMB_Clk = sys_clk_s |
END |
|
BEGIN lmb_v10 |
PARAMETER INSTANCE = ilmb2 |
PARAMETER HW_VER = 1.00.a |
PARAMETER C_EXT_RESET_HIGH = 0 |
PORT SYS_Rst = sys_rst_s |
PORT LMB_Clk = sys_clk_s |
END |
|
BEGIN lmb_v10 |
PARAMETER INSTANCE = dlmb2 |
PARAMETER HW_VER = 1.00.a |
PARAMETER C_EXT_RESET_HIGH = 0 |
PORT SYS_Rst = sys_rst_s |
PORT LMB_Clk = sys_clk_s |
END |
|
BEGIN fsl_v20 |
PARAMETER INSTANCE = fsl0m |
PARAMETER HW_VER = 2.00.a |
PARAMETER C_EXT_RESET_HIGH = 0 |
PARAMETER C_FSL_DEPTH = 128 |
PORT FSL_Clk = sys_clk_s |
PORT SYS_Rst = sys_rst_s |
END |
|
BEGIN fsl_v20 |
PARAMETER INSTANCE = fsl0s |
PARAMETER HW_VER = 2.00.a |
PARAMETER C_EXT_RESET_HIGH = 0 |
PARAMETER C_FSL_DEPTH = 128 |
PORT FSL_Clk = sys_clk_s |
PORT SYS_Rst = sys_rst_s |
END |
|
BEGIN fsl_v20 |
PARAMETER INSTANCE = fsl2m |
PARAMETER HW_VER = 2.00.a |
PARAMETER C_EXT_RESET_HIGH = 0 |
PARAMETER C_FSL_DEPTH = 128 |
PORT FSL_Clk = sys_clk_s |
PORT SYS_Rst = sys_rst_s |
END |
|
BEGIN fsl_v20 |
PARAMETER INSTANCE = fsl2s |
PARAMETER HW_VER = 2.00.a |
PARAMETER C_EXT_RESET_HIGH = 0 |
PARAMETER C_FSL_DEPTH = 128 |
PORT FSL_Clk = sys_clk_s |
PORT SYS_Rst = sys_rst_s |
END |
|
BEGIN lmb_bram_if_cntlr |
PARAMETER INSTANCE = dlmb_cntlr |
PARAMETER INSTANCE = dlmb_cntlr0 |
PARAMETER HW_VER = 1.00.b |
PARAMETER C_BASEADDR = 0x00000000 |
PARAMETER C_HIGHADDR = 0x0000ffff |
BUS_INTERFACE SLMB = dlmb |
BUS_INTERFACE BRAM_PORT = dlmb_port |
BUS_INTERFACE SLMB = dlmb0 |
BUS_INTERFACE BRAM_PORT = dlmb_port0 |
END |
|
BEGIN lmb_bram_if_cntlr |
PARAMETER INSTANCE = ilmb_cntlr |
PARAMETER INSTANCE = ilmb_cntlr0 |
PARAMETER HW_VER = 1.00.b |
PARAMETER C_BASEADDR = 0x00000000 |
PARAMETER C_HIGHADDR = 0x0000ffff |
BUS_INTERFACE SLMB = ilmb |
BUS_INTERFACE BRAM_PORT = ilmb_port |
BUS_INTERFACE SLMB = ilmb0 |
BUS_INTERFACE BRAM_PORT = ilmb_port0 |
END |
|
BEGIN bram_block |
PARAMETER INSTANCE = lmb_bram |
PARAMETER INSTANCE = lmb_bram0 |
PARAMETER HW_VER = 1.00.a |
BUS_INTERFACE PORTA = ilmb_port |
BUS_INTERFACE PORTB = dlmb_port |
BUS_INTERFACE PORTA = ilmb_port0 |
BUS_INTERFACE PORTB = dlmb_port0 |
END |
|
BEGIN lmb_bram_if_cntlr |
PARAMETER INSTANCE = dlmb_cntlr2 |
PARAMETER HW_VER = 1.00.b |
PARAMETER C_BASEADDR = 0x00000000 |
PARAMETER C_HIGHADDR = 0x00001fff |
BUS_INTERFACE SLMB = dlmb2 |
BUS_INTERFACE BRAM_PORT = dlmb_port2 |
END |
|
BEGIN lmb_bram_if_cntlr |
PARAMETER INSTANCE = ilmb_cntlr2 |
PARAMETER HW_VER = 1.00.b |
PARAMETER C_BASEADDR = 0x00000000 |
PARAMETER C_HIGHADDR = 0x00001fff |
BUS_INTERFACE SLMB = ilmb2 |
BUS_INTERFACE BRAM_PORT = ilmb_port2 |
END |
|
BEGIN bram_block |
PARAMETER INSTANCE = lmb_bram2 |
PARAMETER HW_VER = 1.00.a |
BUS_INTERFACE PORTA = ilmb_port2 |
BUS_INTERFACE PORTB = dlmb_port2 |
END |
|
BEGIN opb_uartlite |
PARAMETER INSTANCE = RS232_Uart_1 |
PARAMETER HW_VER = 1.00.b |
276,3 → 367,17
PORT LOCKED = dcm_1_lock |
END |
|
BEGIN fifo_link |
PARAMETER INSTANCE = fifo02 |
PARAMETER HW_VER = 1.00.a |
BUS_INTERFACE SFSL = fsl0m |
BUS_INTERFACE MFSL = fsl2s |
END |
|
BEGIN fifo_link |
PARAMETER INSTANCE = fifo20 |
PARAMETER HW_VER = 1.00.a |
BUS_INTERFACE SFSL = fsl2m |
BUS_INTERFACE MFSL = fsl0s |
END |
|