OpenCores
URL https://opencores.org/ocsvn/tg68kc/tg68kc/trunk

Subversion Repositories tg68kc

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Rev 10 → Rev 11

/tg68kc/trunk/TG68K_ALU.vhd
37,6 → 37,7
port(clk : in std_logic;
Reset : in std_logic;
clkena_lw : in std_logic:='1';
CPU : in std_logic_vector(1 downto 0):="00"; -- 00->68000 01->68010 11->68020(only some parts - yet)
execOPC : in bit;
decodeOPC : in bit;
exe_condition : in std_logic;
92,6 → 93,7
signal flag_z : std_logic_vector(2 downto 0);
signal set_Flags : std_logic_vector(3 downto 0); --NZVC
signal CCRin : std_logic_vector(7 downto 0);
signal last_Flags1 : std_logic_vector(3 downto 0); --NZVC
--BCD
signal bcd_pur : std_logic_vector(9 downto 0);
136,7 → 138,7
signal div_over : std_logic_vector(32 downto 0);
signal nozero : std_logic;
signal div_qsign : std_logic;
signal divisor : std_logic_vector(63 downto 0);
signal divident : std_logic_vector(63 downto 0);
signal divs : std_logic;
signal signedOP : std_logic;
signal OP1_sign : std_logic;
253,7 → 255,8
OP1in(7 downto 0) <= (others=>exe_condition);
ELSIF exec(opcEOR)='1' THEN
OP1in <= OP2out XOR OP1out;
ELSIF exec(opcMOVE)='1' OR exec(exg)='1' THEN
-- ELSIF exec(alu_move)='1' OR exec(exg)='1' THEN
ELSIF exec(alu_move)='1' THEN
-- OP1in <= OP2out(31 downto 8)&(OP2out(7)OR exec_tas)&OP2out(6 downto 0);
OP1in <= OP2out;
ELSIF exec(opcROT)='1' THEN
358,7 → 361,7
------------------------------------------------------------------------------
--ALU
------------------------------------------------------------------------------
PROCESS (OP1out, OP2out, exec, add_result, bcd_pur, bcd_a, bcd_kor, halve_carry, c_in)
PROCESS (OP1out, OP2out, CPU, exec, add_result, bcd_pur, bcd_a, bcd_kor, halve_carry, c_in)
BEGIN
--BCD_ARITH-------------------------------------------------------------------
--04.04.2017 by Tobiflex - BCD handling with all undefined behavior!
386,9 → 389,9
-- bcd_pur <= ('0'&OP1out(7 downto 0)&'0') - ('0'&OP2out(7 downto 0)&Flags(4));
bcd_a <= bcd_pur(9 downto 1) - bcd_kor;
END IF;
-- IF cpu(1)='1' THEN
Vflag_a <= '0'; --TG 01.11.2019 only for cputest -- but other behaiver in real 68000 Hardware ??? I must check this later
-- END IF;
IF cpu(1)='1' THEN
Vflag_a <= '0'; --68020
END IF;
bcd_a_carry <= bcd_pur(9) OR bcd_a(8);
END PROCESS;
972,6 → 975,7
Flags(3 downto 0) <= "0100";
END IF;
ELSIF exec(no_Flags)='0' THEN
last_Flags1 <= Flags(3 downto 0);
IF exec(opcADD)='1' THEN
Flags(4) <= set_flags(0);
ELSIF exec(opcROT)='1' AND rot_bits/="11" AND exec(rot_nop)='0' THEN
980,7 → 984,8
Flags(4) <= BS_X;
END IF;
IF (exec(opcADD) OR exec(opcCMP))='1' THEN
-- IF (exec(opcADD) OR exec(opcCMP))='1' OR exec(alu_setFlags)='1' THEN
IF (exec(opcCMP) OR exec(alu_setFlags))='1' THEN
Flags(3 downto 0) <= set_flags;
ELSIF exec(opcDIVU)='1' AND DIV_Mode/=3 THEN
IF V_Flag='1' THEN
1020,6 → 1025,16
Flags(1) <= BS_V;
ELSIF exec(opcBITS)='1' THEN
Flags(2) <= NOT one_bit_in;
ELSIF exec(opcCHK2)='1' THEN
Flags(0) <= '0';
Flags(2) <= Flags(2) OR set_flags(2);
----lower bound first
IF last_Flags1(0)='0' THEN --unsigned OP
Flags(0) <= Flags(0) OR (NOT set_flags(0) AND NOT set_flags(2));
ELSE --signed OP
Flags(0) <= (Flags(3) AND NOT Flags(1)) OR (NOT Flags(3) AND Flags(1)) OR --LT
(set_flags(3) AND set_flags(1) AND NOT set_flags(2)) OR (NOT set_flags(3) AND NOT set_flags(1) AND NOT set_flags(2)); --GT
END IF;
ELSIF exec(opcCHK)='1' THEN
IF exe_datatype="01" THEN --Word
Flags(3) <= OP1out(15);
1032,7 → 1047,7
Flags(2) <='0';
END IF;
Flags(1) <= '0';
Flags(0) <= NOT set_flags(0);
Flags(0) <= '0';
END IF;
END IF;
END IF;
1174,14 → 1189,14
signedOP, nozero, div_qsign, OP2outext)
BEGIN
divs <= (opcode(15) AND opcode(8)) OR (NOT opcode(15) AND sndOPC(11));
divisor(15 downto 0) <= (OTHERS=> '0');
divisor(63 downto 32) <= (OTHERS=> divs AND reg_QA(31));
divident(15 downto 0) <= (OTHERS=> '0');
divident(63 downto 32) <= (OTHERS=> divs AND reg_QA(31));
IF exe_opcode(15)='1' OR DIV_Mode=0 THEN
divisor(47 downto 16) <= reg_QA;
divident(47 downto 16) <= reg_QA;
ELSE
divisor(31 downto 0) <= reg_QA;
divident(31 downto 0) <= reg_QA;
IF exe_opcode(14)='1' AND sndOPC(10)='1' THEN
divisor(63 downto 32) <= reg_QB;
divident(63 downto 32) <= reg_QB;
END IF;
END IF;
IF signedOP='1' OR opcode(15)='0' THEN
1223,12 → 1238,12
signedOP <= divs;
IF micro_state=div1 THEN
nozero <= '0';
IF divs='1' AND divisor(63)='1' THEN -- Neg divisor
IF divs='1' AND divident(63)='1' THEN -- Neg divident
OP1_sign <= '1';
div_reg <= 0-divisor;
div_reg <= 0-divident;
ELSE
OP1_sign <= '0';
div_reg <= divisor;
div_reg <= divident;
END IF;
ELSE
div_reg <= div_quot;
/tg68kc/trunk/TG68K_Pack.vhd
29,7 → 29,8
ld_229_1, ld_229_2, ld_229_3, ld_229_4, st_229_1, st_229_2, st_229_3, st_229_4,
st_AnXn1, st_AnXn2, bra1, bsr1, bsr2, nopnop, dbcc1, movem1, movem2, movem3,
andi, pack1, pack2, pack3, op_AxAy, cmpm, link1, link2, unlink1, unlink2, int1, int2, int3, int4, rte1, rte2, rte3,
rte4, rte5, rtd1, rtd2, trap00, trap0, trap1, trap2, trap3,
rte4, rte5, rtd1, rtd2, trap00, trap0, trap1, trap2, trap3, cas1, cas2, cas21, cas22, cas23, cas24,
cas25, cas26, cas27, cas28, chk20, chk21, chk22, chk23, chk24,
trap4, trap5, trap6, movec1, movep1, movep2, movep3, movep4, movep5, rota1, bf1,
mul1, mul2, mul_end1, mul_end2, div1, div2, div3, div4, div_end1, div_end2);
116,8 → 117,14
constant store_ea_packdata : integer := 80; --
constant exec_BS : integer := 81; --
constant hold_OP2 : integer := 82; --
constant restore_ADDR : integer := 83; --
constant alu_exec : integer := 84; --
constant alu_move : integer := 85; --
constant alu_setFlags : integer := 86; --
constant opcCHK2 : integer := 87; --
constant opcEXTB : integer := 88; --
 
constant lastOpcBit : integer := 82;
constant lastOpcBit : integer := 88;
 
component TG68K_ALU
generic(
129,6 → 136,7
port(
clk : in std_logic;
Reset : in std_logic;
CPU : in std_logic_vector(1 downto 0):="00"; -- 00->68000 01->68010 11->68020(only some parts - yet)
clkena_lw : in std_logic:='1';
execOPC : in bit;
decodeOPC : in bit;
/tg68kc/trunk/TG68KdotC_Kernel.vhd
21,7 → 21,12
------------------------------------------------------------------------------
------------------------------------------------------------------------------
 
-- 10.11.2019 TG inset TRAPcc
-- 25.11.2019 TG bugfix ILLEGAL.B handling
-- 24.11.2019 TG next try CMP2 and CHK2.l
-- 24.11.2019 retrofun(RF) commit ILLEGAL.B handling
-- 18.11.2019 TG insert CMP2 and CHK2.l
-- 17.11.2019 TG insert CAS and CAS2
-- 10.11.2019 TG insert TRAPcc
-- 08.11.2019 TG bugfix movem in 68020 mode
-- 06.11.2019 TG bugfix CHK
-- 06.11.2019 TG bugfix flags and stackframe DIVU
56,7 → 61,7
 
-- optimize Register file
 
-- to do 68010:
-- to do 68010:
-- (MOVEC)
-- BKPT
-- MOVES
65,12 → 70,15
-- (CALLM)
-- (RETM)
 
-- CAS, CAS2
-- bugfix DIVS.W
-- bugfix CHK2, CMP2
-- rework barrel shifter
-- CHK2
-- CMP2
-- cpXXX Coprozessor stuff
 
-- done 020:
-- CAS, CAS2
-- TRAPcc
-- PACK
-- UNPK
200,8 → 208,6
signal TG68_PC_word : bit;
signal getbrief : bit;
signal brief : std_logic_vector(15 downto 0);
signal dest_areg : std_logic;
signal source_areg : std_logic;
signal data_is_source : bit;
signal store_in_tmp : bit;
signal write_back : bit;
213,6 → 219,7
signal setopcode : bit;
signal decodeOPC : bit;
signal execOPC : bit;
signal execOPC_ALU : bit;
signal setexecOPC : bit;
signal endOPC : bit;
signal setendOPC : bit;
225,10 → 232,19
 
signal exe_condition : std_logic;
signal ea_only : bit;
signal source_areg : std_logic;
signal source_lowbits : bit;
signal source_LDRLbits : bit;
signal source_LDRMbits : bit;
signal source_2ndHbits : bit;
signal source_2ndMbits : bit;
signal source_2ndLbits : bit;
signal dest_areg : std_logic;
signal dest_LDRareg : std_logic;
signal dest_LDRHbits : bit;
signal dest_LDRLbits : bit;
signal dest_2ndHbits : bit;
signal dest_2ndLbits : bit;
signal dest_hbits : bit;
signal rot_bits : std_logic_vector(1 downto 0);
signal set_rot_bits : std_logic_vector(1 downto 0);
256,7 → 272,6
signal trap_1111 : bit;
signal trap_trap : bit;
signal trap_trapv : bit;
signal trap_trapcc : bit;
signal trap_interrupt : bit;
signal trapmake : bit;
signal trapd : bit;
349,8 → 364,9
port map(
clk => clk, --: in std_logic;
Reset => Reset, --: in std_logic;
CPU => CPU, --: in std_logic_vector(1 downto 0):="00"; -- 00->68000 01->68010 11->68020(only some parts - yet)
clkena_lw => clkena_lw, --: in std_logic:='1';
execOPC => execOPC, --: in bit;
execOPC => execOPC_ALU, --: in bit;
decodeOPC => decodeOPC, --: in bit;
exe_condition => exe_condition, --: in std_logic;
exec_tas => exec_tas, --: in std_logic;
389,7 → 405,7
);
 
long_start_alu <= to_bit(NOT memmaskmux(3));
 
execOPC_ALU <= execOPC OR exec(alu_exec);
process (memmaskmux)
begin
non_aligned <= '0';
581,7 → 597,7
-----------------------------------------------------------------------------
-- set dest regaddr
-----------------------------------------------------------------------------
PROCESS (opcode, rf_source_addrd, brief, setstackaddr, dest_hbits, dest_areg, data_is_source, sndOPC, exec, set, dest_2ndHbits)
PROCESS (opcode, rf_source_addrd, brief, setstackaddr, dest_hbits, dest_areg, dest_LDRareg, data_is_source, sndOPC, exec, set, dest_2ndHbits, dest_2ndLbits, dest_LDRHbits, dest_LDRLbits, last_data_read)
BEGIN
IF exec(movem_action) ='1' THEN
rf_dest_addr <= rf_source_addrd;
594,8 → 610,12
-- rf_dest_addr <= sndOPC(9 downto 6);
-- END IF;
ELSIF dest_2ndHbits='1' THEN
rf_dest_addr <= '0'&sndOPC(14 downto 12);
ELSIF set(write_reminder)='1' THEN
rf_dest_addr <= dest_LDRareg&sndOPC(14 downto 12);
ELSIF dest_LDRHbits='1' THEN
rf_dest_addr <= last_data_read(15 downto 12);
ELSIF dest_LDRLbits='1' THEN
rf_dest_addr <= '0'&last_data_read(2 downto 0);
ELSIF dest_2ndLbits='1' THEN
rf_dest_addr <= '0'&sndOPC(2 downto 0);
ELSIF setstackaddr='1' THEN
rf_dest_addr <= "1111";
613,7 → 633,7
-----------------------------------------------------------------------------
-- set source regaddr
-----------------------------------------------------------------------------
PROCESS (opcode, movem_presub, movem_regaddr, source_lowbits, source_areg, sndOPC, exec, set, source_2ndLbits, source_2ndHbits)
PROCESS (opcode, movem_presub, movem_regaddr, source_lowbits, source_areg, sndOPC, exec, set, source_2ndLbits, source_2ndHbits, source_LDRLbits, source_LDRMbits, last_data_read, source_2ndMbits)
BEGIN
IF exec(movem_action)='1' OR set(movem_action) ='1' THEN
IF movem_presub='1' THEN
625,6 → 645,12
rf_source_addr <= '0'&sndOPC(2 downto 0);
ELSIF source_2ndHbits='1' THEN
rf_source_addr <= '0'&sndOPC(14 downto 12);
ELSIF source_2ndMbits='1' THEN
rf_source_addr <= '0'&sndOPC(8 downto 6);
ELSIF source_LDRLbits='1' THEN
rf_source_addr <= '0'&last_data_read(2 downto 0);
ELSIF source_LDRMbits='1' THEN
rf_source_addr <= '0'&last_data_read(8 downto 6);
ELSIF source_lowbits='1' THEN
rf_source_addr <= source_areg&opcode(2 downto 0);
ELSIF exec(linksp)='1' THEN
659,10 → 685,6
OP2out(31 downto 16) <= (OTHERS => OP2out(15));
IF exec(OP2out_one)='1' THEN
OP2out(15 downto 0) <= "1111111111111111";
ELSIF exec(opcEXT)='1' THEN
IF exe_opcode(6)='0' OR exe_opcode(8)='1' THEN --ext.w
OP2out(15 downto 8) <= (OTHERS => OP2out(7));
END IF;
ELSIF use_direct_data='1' OR (exec(exg)='1' AND execOPC='1') OR exec(get_bfoffset)='1' THEN
OP2out <= data_write_tmp;
ELSIF (exec(ea_data_OP1)='0' AND store_in_tmp='1') OR exec(ea_data_OP2)='1' THEN
678,9 → 700,12
OP2out(3) <='0';
END IF;
OP2out(15 downto 4) <= (OTHERS => '0');
ELSIF exe_datatype="10" THEN
ELSIF exe_datatype="10" AND exec(opcEXT)='0' THEN
OP2out(31 downto 16) <= reg_QB(31 downto 16);
END IF;
IF exec(opcEXTB)='1' THEN
OP2out(31 downto 8) <= (OTHERS => OP2out(7));
END IF;
END PROCESS;
 
692,7 → 717,6
IF rising_edge(clk) THEN
IF Reset = '1' THEN
store_in_tmp <='0';
exec_write_back <= '0';
direct_data <= '0';
use_direct_data <= '0';
Z_error <= '0';
699,14 → 723,6
ELSIF clkena_lw='1' THEN
useStackframe2<='0';
direct_data <= '0';
IF state="11" THEN
exec_write_back <= '0';
ELSIF setstate="10" AND write_back='1' THEN
-- ELSIF setstate = "10" AND write_back = '1' AND next_micro_state = idle THEN --this shut be a fix for pinball
-- --but it destory pack -(ax),-(ay) and unpack
exec_write_back <= '1';
END IF;
 
IF exec(hold_OP2)='1' THEN
use_direct_data <= '1';
END IF;
713,7 → 729,7
IF set_direct_data='1' THEN
direct_data <= '1';
use_direct_data <= '1';
ELSIF endOPC='1' THEN
ELSIF endOPC='1' OR set(ea_data_OP2)='1' THEN
use_direct_data <= '0';
END IF;
exec_DIRECT <= set_exec(opcMOVE);
900,7 → 916,7
use_base <= '0';
IF memmaskmux(3)='0' OR exec(mem_addsub)='1' THEN
memaddr_delta <= addsub_q;
ELSIF state="01" AND exec_write_back='1' THEN
ELSIF set(restore_ADDR)='1' THEN
memaddr_delta <= tmp_TG68_PC;
ELSIF exec(direct_delta)='1' THEN
memaddr_delta <= data_read;
945,7 → 961,7
-- PC Calc + fetch opcode
-----------------------------------------------------------------------------
PROCESS (clk, IPL, setstate, state, exec_write_back, set_direct_data, next_micro_state, stop, make_trace, make_berr, IPL_nr, FlagsSR, set_rot_cnt, opcode, writePCbig, set_exec, exec,
PC_dataa, PC_datab, setnextpass, last_data_read, TG68_PC_brw, TG68_PC_word, Z_error, trap_trap, trap_trapv, trap_trapcc, interrupt, tmp_TG68_PC, TG68_PC)
PC_dataa, PC_datab, setnextpass, last_data_read, TG68_PC_brw, TG68_PC_word, Z_error, trap_trap, trap_trapv, interrupt, tmp_TG68_PC, TG68_PC)
BEGIN
PC_dataa <= TG68_PC;
1013,6 → 1029,7
endOPC <= '0';
TG68_PC_word <= '0';
execOPC <= '0';
-- execOPC_ALU <= '0';
stop <= '0';
rot_cnt <="000001";
-- byte <= '0';
1024,6 → 1041,7
Suppress_Base <= '0';
make_berr <= '0';
memmask <= "111111";
exec_write_back <= '0';
ELSE
-- IPL_nr <= NOT IPL;
IF clkena_in='1' THEN
1044,7 → 1062,12
interrupt <= setinterrupt;
decodeOPC <= setopcode;
endOPC <= setendOPC;
execOPC <= setexecOPC;
execOPC <= setexecOPC;
-- IF setexecOPC='1' OR set(alu_exec)='1' THEN
-- execOPC_ALU <= '1';
-- ELSE
-- execOPC_ALU <= '0';
-- END IF;
exe_datatype <= set_datatype;
exe_opcode <= opcode;
1099,7 → 1122,13
FC(0) <= setstate(1) AND (NOT PCbase OR setstate(0));
IF interrupt='1' THEN
FC(1 downto 0) <= "11";
END IF;
END IF;
IF state="11" THEN
exec_write_back <= '0';
ELSIF setstate="10" AND write_back='1' THEN
exec_write_back <= '1';
END IF;
IF (state="10" AND write_back='1' AND setstate/="10") OR set_rot_cnt/="000001" OR (stop='1' AND interrupt='0') OR set_exec(opcCHK)='1' THEN
state <= "01";
memmask <= "111111";
1177,15 → 1206,6
END IF;
END IF;
 
-- why do not I need this ??? What are the immediate data for ???
-- IF trap_trapcc='1' THEN
-- IF opcode(2 downto 0)="100" THEN
-- exe_pc <= (others => '0');
-- ELSE
-- exe_pc <= last_data_read;
-- END IF;
-- END IF;
IF decodeOPC='1' OR interrupt='1' THEN
trap_SR <= FlagsSR;
END IF;
1204,10 → 1224,14
END IF;
IF clkena_lw='1' THEN
exec <= set;
exec(alu_move) <= set(opcMOVE) OR set(alu_move);
exec(alu_setFlags) <= set(opcADD) OR set(alu_setFlags);
exec_tas <= '0';
exec(subidx) <= set(presub) or set(subidx);
IF setexecOPC='1' THEN
exec <= set_exec OR set;
exec <= set_exec OR set;
exec(alu_move) <= set_exec(opcMOVE) OR set(opcMOVE) OR set(alu_move);
exec(alu_setFlags) <= set_exec(opcADD) OR set(opcADD) OR set(alu_setFlags);
exec_tas <= set_exec_tas;
END IF;
exec(get_2ndOPC) <= set(get_2ndOPC) OR setopcode;
1342,6 → 1366,7
FC(2) <= '1';
END IF;
IF cpu(1)='0' THEN
FlagsSR(4) <= '0';
FlagsSR(6) <= '0';
END IF;
FlagsSR(3) <= '0';
1355,7 → 1380,7
PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state, decodeOPC, state, setexecOPC, Flags, FlagsSR, direct_data, build_logical,
build_bcd, set_Z_error, trapd, movem_run, last_data_read, set, set_V_Flag, z_error, trap_trace, trap_interrupt,
SVmode, preSVmode, stop, long_done, ea_only, setstate, execOPC, exec_write_back, exe_datatype,
datatype, interrupt, c_out, trapmake, rot_cnt, brief, addr, trap_trapv, trap_trapcc, last_data_in, use_VBR_Stackframe,
datatype, interrupt, c_out, trapmake, rot_cnt, brief, addr, trap_trapv, last_data_in, use_VBR_Stackframe,
long_start, set_datatype, sndOPC, set_exec, exec, ea_build_now, reg_QA, reg_QB, make_berr, trap_berr)
BEGIN
TG68_PC_brw <= '0';
1367,7 → 1392,8
setdisp <= '0';
setdispbyte <= '0';
getbrief <= '0';
dest_areg <= '0';
dest_LDRareg <= '0';
dest_areg <= '0';
source_areg <= '0';
data_is_source <= '0';
write_back <= '0';
1378,10 → 1404,16
set_rot_bits <= opcode(4 downto 3);
set_rot_cnt <= "000001";
dest_hbits <= '0';
source_lowbits <= '0';
source_lowbits <= '0';
source_LDRLbits <= '0';
source_LDRMbits <= '0';
source_2ndHbits <= '0';
source_2ndMbits <= '0';
source_2ndLbits <= '0';
dest_LDRHbits <= '0';
dest_LDRLbits <= '0';
dest_2ndHbits <= '0';
dest_2ndLbits <= '0';
ea_only <= '0';
set_direct_data <= '0';
set_exec_tas <= '0';
1392,7 → 1424,6
trap_1111 <='0';
trap_trap <='0';
trap_trapv <= '0';
trap_trapcc <= '0';
trapmake <='0';
set_vectoraddr <='0';
writeSR <= '0';
1428,6 → 1459,10
WHEN "01" => datatype <= "01"; --Word
WHEN OTHERS => datatype <= "10"; --Long
END CASE;
 
IF execOPC='1' AND exec_write_back='1' THEN
set(restore_ADDR) <= '1';
END IF;
IF interrupt='1' AND trap_berr='1' THEN
next_micro_state <= trap0;
1437,7 → 1472,8
setstate <= "01";
END IF;
IF trapmake='1' AND trapd='0' THEN
IF use_VBR_Stackframe='1' AND (trap_trapv='1' OR set_Z_error='1' OR exec(opcCHK)='1') THEN
-- IF use_VBR_Stackframe='1' AND (trap_trapv='1' OR set_Z_error='1' OR exec(opcCHK)='1') THEN
IF use_VBR_Stackframe='1' AND (trap_trapv='1' OR set_Z_error='1' OR exec(trap_chk)='1') THEN
next_micro_state <= trap00;
else
next_micro_state <= trap0;
1556,11 → 1592,11
END CASE;
END IF;
------------------------------------------------------------------------------
--prepere opcode
------------------------------------------------------------------------------
--prepare opcode
------------------------------------------------------------------------------
CASE opcode(15 downto 12) IS
-- 0000 ----------------------------------------------------------------------------
WHEN "0000" =>
-- 0000 ----------------------------------------------------------------------------
WHEN "0000" =>
IF opcode(8)='1' AND opcode(5 downto 3)="001" THEN --movep
datatype <= "00"; --Byte
set(use_SP) <= '1'; --addr+2
1571,192 → 1607,324
set(movepl) <= '1';
END IF;
IF decodeOPC='1' THEN
IF opcode(6)='1' THEN
set(movepl) <= '1';
END IF;
IF opcode(7)='0' THEN
IF opcode(6)='1' THEN
set(movepl) <= '1';
END IF;
IF opcode(7)='0' THEN
set_direct_data <= '1'; -- to register
END IF;
next_micro_state <= movep1;
END IF;
IF setexecOPC='1' THEN
IF setexecOPC='1' THEN
dest_hbits <='1';
END IF;
ELSE
IF opcode(8)='1' OR opcode(11 downto 9)="100" THEN --Bits
set_exec(opcBITS) <= '1';
set_exec(ea_data_OP1) <= '1';
IF opcode(7 downto 6)/="00" THEN
IF opcode(5 downto 3)/="001" AND --ea An illegal mode
(opcode(8 downto 3)/="000111" OR opcode(2)='0') AND --BTST bit number static illegal modes
(opcode(8 downto 2)/="1001111" OR opcode(1 downto 0)="00") AND --BTST bit number dynamic illegal modes
(opcode(7 downto 6)="00" OR opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00") THEN --BCHG, BCLR, BSET illegal modes
set_exec(opcBITS) <= '1';
set_exec(ea_data_OP1) <= '1';
IF opcode(7 downto 6)/="00" THEN
IF opcode(5 downto 4)="00" THEN
set_exec(Regwrena) <= '1';
END IF;
write_back <= '1';
END IF;
IF opcode(5 downto 4)="00" THEN
set_exec(Regwrena) <= '1';
datatype <= "10"; --Long
ELSE
datatype <= "00"; --Byte
END IF;
write_back <= '1';
IF opcode(8)='0' THEN
IF decodeOPC='1' THEN
next_micro_state <= nop;
set(get_2ndOPC) <= '1';
set(ea_build) <= '1';
END IF;
ELSE
ea_build_now <= '1';
END IF;
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
IF opcode(5 downto 4)="00" THEN
datatype <= "10"; --Long
ELSE
datatype <= "00"; --Byte
ELSIF opcode(8 downto 6)="011" THEN --CAS/CAS2/CMP2/CHK2
IF cpu(1)='1' THEN
IF opcode(11)='1' THEN --CAS/CAS2
IF (opcode(10 downto 9)/="00" AND --CAS illegal size
opcode(5 downto 4)/="00" AND (opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00")) OR --ea illegal modes
(opcode(10)='1' AND opcode(5 downto 0)="111100") THEN --CAS2
CASE opcode(10 downto 9) IS
WHEN "01" => datatype <= "00"; --Byte
WHEN "10" => datatype <= "01"; --Word
WHEN OTHERS => datatype <= "10"; --Long
END CASE;
IF opcode(10)='1' AND opcode(5 downto 0)="111100" THEN --CAS2
IF decodeOPC='1' THEN
set(get_2ndOPC) <= '1';
next_micro_state <= cas21;
END IF;
ELSE --CAS
IF decodeOPC='1' THEN
next_micro_state <= nop;
set(get_2ndOPC) <= '1';
set(ea_build) <= '1';
END IF;
IF micro_state=idle AND nextpass='1' THEN
source_2ndLbits <= '1';
set(ea_data_OP1) <= '1';
set(addsub) <= '1';
set(alu_exec) <= '1';
set(alu_setFlags) <= '1';
setstate <= "01";
next_micro_state <= cas1;
END IF;
END IF;
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
ELSE --CMP2/CHK2
IF opcode(10 downto 9)/="11" AND --illegal size
opcode(5 downto 4)/="00" AND opcode(5 downto 3)/="011" AND opcode(5 downto 3)/="100" AND opcode(5 downto 2)/="1111" THEN --ea illegal modes
set(trap_chk) <= '1';
datatype <= opcode(10 downto 9);
IF decodeOPC='1' THEN
next_micro_state <= nop;
set(get_2ndOPC) <= '1';
set(ea_build) <= '1';
END IF;
IF set(get_ea_now)='1' THEN
set(mem_addsub) <= '1';
set(OP1addr) <= '1';
END IF;
IF micro_state=idle AND nextpass='1' THEN
setstate <= "10";
set(hold_OP2) <='1';
next_micro_state <= chk20;
END IF;
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
END IF;
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
IF opcode(8)='0' THEN
IF decodeOPC='1' THEN
next_micro_state <= nop;
set(get_2ndOPC) <= '1';
set(ea_build) <= '1';
END IF;
ELSE
ea_build_now <= '1';
END IF;
ELSIF opcode(11 downto 9)="111" THEN --MOVES not in 68000
trap_illegal <= '1';
-- trap_addr_error <= '1';
trapmake <= '1';
ELSE --andi, ...xxxi
IF opcode(11 downto 9)="000" THEN --ORI
set_exec(opcOR) <= '1';
END IF;
IF opcode(11 downto 9)="001" THEN --ANDI
set_exec(opcAND) <= '1';
END IF;
IF opcode(11 downto 9)="010" OR opcode(11 downto 9)="011" THEN --SUBI, ADDI
set_exec(opcADD) <= '1';
END IF;
IF opcode(11 downto 9)="101" THEN --EORI
set_exec(opcEOR) <= '1';
END IF;
IF opcode(11 downto 9)="110" THEN --CMPI
set_exec(opcCMP) <= '1';
END IF;
IF opcode(7)='0' AND opcode(5 downto 0)="111100" AND (set_exec(opcAND) OR set_exec(opcOR) OR set_exec(opcEOR))='1' THEN --SR
IF decodeOPC='1' AND SVmode='0' AND opcode(6)='1' THEN --SR
IF cpu(0)='1' AND opcode(7 downto 6)/="11" AND opcode(5 downto 4)/="00" AND (opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00") THEN
IF SVmode='1' THEN
--TODO: implement MOVES
trap_illegal <= '1';
trapmake <= '1';
ELSE
trap_priv <= '1';
trapmake <= '1';
ELSE
set(no_Flags) <= '1';
IF decodeOPC='1' THEN
IF opcode(6)='1' THEN
set(to_SR) <= '1';
END IF;
set(to_CCR) <= '1';
set(andiSR) <= set_exec(opcAND);
set(eoriSR) <= set_exec(opcEOR);
set(oriSR) <= set_exec(opcOR);
setstate <= "01";
next_micro_state <= nopnop;
END IF;
END IF;
ELSE
IF decodeOPC='1' THEN
next_micro_state <= andi;
set(get_2ndOPC) <='1';
set(ea_build) <= '1';
set_direct_data <= '1';
IF datatype="10" THEN
set(longaktion) <= '1';
trap_illegal <= '1';
trapmake <= '1';
END IF;
ELSE --andi, ...xxxi
IF opcode(7 downto 6)/="11" AND opcode(5 downto 3)/="001" THEN --ea An illegal mode
IF opcode(11 downto 9)="000" THEN --ORI
IF opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00" OR opcode(2 downto 0)="100" THEN
set_exec(opcOR) <= '1';
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
END IF;
IF opcode(5 downto 4)/="00" THEN
set_exec(ea_data_OP1) <= '1';
END IF;
IF opcode(11 downto 9)/="110" THEN --CMPI
IF opcode(5 downto 4)="00" THEN
set_exec(Regwrena) <= '1';
END IF;
write_back <= '1';
IF opcode(11 downto 9)="001" THEN --ANDI
IF opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00" OR opcode(2 downto 0)="100" THEN
set_exec(opcAND) <= '1';
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
END IF;
IF opcode(10 downto 9)="10" THEN --CMPI, SUBI
set(addsub) <= '1';
IF opcode(11 downto 9)="010" OR opcode(11 downto 9)="011" THEN --SUBI, ADDI
IF opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00" THEN
set_exec(opcADD) <= '1';
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
END IF;
END IF;
END IF;
END IF;
IF opcode(11 downto 9)="101" THEN --EORI
IF opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00" OR opcode(2 downto 0)="100" THEN
set_exec(opcEOR) <= '1';
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
END IF;
IF opcode(11 downto 9)="110" THEN --CMPI
IF opcode(5 downto 3)/="111" OR opcode(2)='0' THEN
set_exec(opcCMP) <= '1';
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
END IF;
IF (set_exec(opcor) OR set_exec(opcand) OR set_exec(opcADD) OR set_exec(opcEor) OR set_exec(opcCMP))='1' THEN
IF opcode(7)='0' AND opcode(5 downto 0)="111100" AND (set_exec(opcAND) OR set_exec(opcOR) OR set_exec(opcEOR))='1' THEN --SR
IF decodeOPC='1' AND SVmode='0' AND opcode(6)='1' THEN --SR
trap_priv <= '1';
trapmake <= '1';
ELSE
set(no_Flags) <= '1';
IF decodeOPC='1' THEN
IF opcode(6)='1' THEN
set(to_SR) <= '1';
END IF;
set(to_CCR) <= '1';
set(andiSR) <= set_exec(opcAND);
set(eoriSR) <= set_exec(opcEOR);
set(oriSR) <= set_exec(opcOR);
setstate <= "01";
next_micro_state <= nopnop;
END IF;
END IF;
ELSIF opcode(7)='0' OR opcode(5 downto 0)/="111100" OR (set_exec(opcand) OR set_exec(opcor) OR set_exec(opcEor))='0' THEN
IF decodeOPC='1' THEN
next_micro_state <= andi;
set(get_2ndOPC) <='1';
set(ea_build) <= '1';
set_direct_data <= '1';
IF datatype="10" THEN
set(longaktion) <= '1';
END IF;
END IF;
IF opcode(5 downto 4)/="00" THEN
set_exec(ea_data_OP1) <= '1';
END IF;
IF opcode(11 downto 9)/="110" THEN --CMPI
IF opcode(5 downto 4)="00" THEN
set_exec(Regwrena) <= '1';
END IF;
write_back <= '1';
END IF;
IF opcode(10 downto 9)="10" THEN --CMPI, SUBI
set(addsub) <= '1';
END IF;
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
END IF;
END IF;
-- 0001, 0010, 0011 -----------------------------------------------------------------
-- 0001, 0010, 0011 -----------------------------------------------------------------
WHEN "0001"|"0010"|"0011" => --move.b, move.l, move.w
set_exec(opcMOVE) <= '1';
ea_build_now <= '1';
IF opcode(8 downto 6)="001" THEN
set(no_Flags) <= '1';
END IF;
IF opcode(5 downto 4)="00" THEN --Dn, An
IF opcode(8 downto 7)="00" THEN
set_exec(Regwrena) <= '1';
END IF;
END IF;
CASE opcode(13 downto 12) IS
WHEN "01" => datatype <= "00"; --Byte
WHEN "10" => datatype <= "10"; --Long
WHEN OTHERS => datatype <= "01"; --Word
END CASE;
source_lowbits <= '1'; -- Dn=> An=>
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
IF nextpass='1' OR opcode(5 downto 4)="00" THEN
dest_hbits <= '1';
IF opcode(8 downto 6)/="000" THEN
dest_areg <= '1';
IF ((opcode(11 downto 10)="00" OR opcode(8 downto 6)/="111") AND --illegal dest ea
(opcode(5 downto 2)/="1111" OR opcode(1 downto 0)="00") AND --illegal src ea
(opcode(13)='1' OR (opcode(8 downto 6)/="001" AND opcode(5 downto 3)/="001"))) THEN --byte src address reg direct, byte movea
set_exec(opcMOVE) <= '1';
ea_build_now <= '1';
IF opcode(8 downto 6)="001" THEN
set(no_Flags) <= '1';
END IF;
END IF;
-- IF setstate="10" THEN
-- set(update_ld) <= '0';
-- END IF;
IF opcode(5 downto 4)="00" THEN --Dn, An
IF opcode(8 downto 7)="00" THEN
set_exec(Regwrena) <= '1';
END IF;
END IF;
CASE opcode(13 downto 12) IS
WHEN "01" => datatype <= "00"; --Byte
WHEN "10" => datatype <= "10"; --Long
WHEN OTHERS => datatype <= "01"; --Word
END CASE;
source_lowbits <= '1'; -- Dn=> An=>
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
 
IF nextpass='1' OR opcode(5 downto 4)="00" THEN
dest_hbits <= '1';
IF opcode(8 downto 6)/="000" THEN
dest_areg <= '1';
END IF;
END IF;
-- IF setstate="10" THEN
-- set(update_ld) <= '0';
-- END IF;
--
IF micro_state=idle AND (nextpass='1' OR (opcode(5 downto 4)="00" AND decodeOPC='1')) THEN
CASE opcode(8 downto 6) IS --destination
WHEN "000"|"001" => --Dn,An
set_exec(Regwrena) <= '1';
WHEN "010"|"011"|"100" => --destination -(an)+
IF opcode(6)='1' THEN --(An)+
set(postadd) <= '1';
IF opcode(11 downto 9)="111" THEN
set(use_SP) <= '1';
IF micro_state=idle AND (nextpass='1' OR (opcode(5 downto 4)="00" AND decodeOPC='1')) THEN
CASE opcode(8 downto 6) IS --destination
WHEN "000"|"001" => --Dn,An
set_exec(Regwrena) <= '1';
WHEN "010"|"011"|"100" => --destination -(an)+
IF opcode(6)='1' THEN --(An)+
set(postadd) <= '1';
IF opcode(11 downto 9)="111" THEN
set(use_SP) <= '1';
END IF;
END IF;
END IF;
IF opcode(8)='1' THEN -- -(An)
set(presub) <= '1';
IF opcode(11 downto 9)="111" THEN
set(use_SP) <= '1';
IF opcode(8)='1' THEN -- -(An)
set(presub) <= '1';
IF opcode(11 downto 9)="111" THEN
set(use_SP) <= '1';
END IF;
END IF;
END IF;
setstate <= "11";
next_micro_state <= nop;
IF nextpass='0' THEN
set(write_reg) <= '1';
END IF;
WHEN "101" => --(d16,An)
next_micro_state <= st_dAn1;
-- getbrief <= '1';
WHEN "110" => --(d8,An,Xn)
next_micro_state <= st_AnXn1;
getbrief <= '1';
WHEN "111" =>
CASE opcode(11 downto 9) IS
WHEN "000" => --(xxxx).w
next_micro_state <= st_nn;
WHEN "001" => --(xxxx).l
set(longaktion) <= '1';
next_micro_state <= st_nn;
WHEN OTHERS => NULL;
END CASE;
WHEN OTHERS => NULL;
END CASE;
END IF;
setstate <= "11";
next_micro_state <= nop;
IF nextpass='0' THEN
set(write_reg) <= '1';
END IF;
WHEN "101" => --(d16,An)
next_micro_state <= st_dAn1;
-- getbrief <= '1';
WHEN "110" => --(d8,An,Xn)
next_micro_state <= st_AnXn1;
getbrief <= '1';
WHEN "111" =>
CASE opcode(11 downto 9) IS
WHEN "000" => --(xxxx).w
next_micro_state <= st_nn;
WHEN "001" => --(xxxx).l
set(longaktion) <= '1';
next_micro_state <= st_nn;
WHEN OTHERS => NULL;
END CASE;
WHEN OTHERS => NULL;
END CASE;
END IF;
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
---- 0100 ----------------------------------------------------------------------------
WHEN "0100" => --rts_group
IF opcode(8)='1' THEN --lea
IF opcode(6)='1' THEN --lea
IF opcode(7)='1' THEN
source_lowbits <= '1';
-- IF opcode(5 downto 3)="000" AND opcode(10)='0' THEN --ext
IF opcode(5 downto 4)="00" THEN --extb.l
IF opcode(8)='1' THEN --lea, extb.l, chk
IF opcode(6)='1' THEN --lea, extb.l
IF opcode(11 downto 9)="100" AND opcode(5 downto 3)="000" THEN --extb.l
IF opcode(7)='1' AND cpu(1)='1' THEN
source_lowbits <= '1';
set_exec(opcEXT) <= '1';
set_exec(opcEXTB) <= '1';
set_exec(opcMOVE) <= '1';
set_exec(Regwrena) <= '1';
-- IF opcode(6)='0' THEN
-- datatype <= "01"; --WORD
-- END IF;
ELSE
set_exec(Regwrena) <= '1';
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
ELSE
IF opcode(7)='1' AND
(opcode(5)='1' OR opcode(4 downto 3)="10") AND
opcode(5 downto 3)/="100" AND opcode(5 downto 2)/="1111" THEN --ea illegal opcodes
source_lowbits <= '1';
source_areg <= '1';
ea_only <= '1';
set_exec(Regwrena) <= '1';
1776,152 → 1944,195
dest_areg <= '1';
dest_hbits <= '1';
END IF;
END IF;
ELSE
trap_illegal <= '1';
trapmake <= '1';
ELSE
trap_illegal <='1';
trapmake <='1';
END IF;
END IF;
ELSE --chk
IF opcode(7)='1' THEN
datatype <= "01"; --Word
set(trap_chk) <= '1';
IF (c_out(1)='0' OR OP1out(15)='1' OR OP2out(15)='1') AND exec(opcCHK)='1' THEN
IF opcode(5 downto 3)/="001" AND --ea An illegal mode
(opcode(5 downto 2)/="1111" OR opcode(1 downto 0)="00") THEN --ea illegal modes
IF opcode(7)='1' THEN
datatype <= "01"; --Word
set(trap_chk) <= '1';
IF (c_out(1)='0' OR OP1out(15)='1' OR OP2out(15)='1') AND exec(opcCHK)='1' THEN
trapmake <= '1';
END IF;
ELSIF cpu(1)='1' THEN --chk long for 68020
datatype <= "10"; --Long
set(trap_chk) <= '1';
IF (c_out(2)='0' OR OP1out(31)='1' OR OP2out(31)='1') AND exec(opcCHK)='1' THEN
trapmake <= '1';
END IF;
ELSE
trap_illegal <= '1'; -- chk long for 68020
trapmake <= '1';
END IF;
ELSIF cpu(1)='1' THEN --chk long for 68020
datatype <= "10"; --Long
set(trap_chk) <= '1';
IF (c_out(2)='0' OR OP1out(31)='1' OR OP2out(31)='1') AND exec(opcCHK)='1' THEN
trapmake <= '1';
IF opcode(7)='1' OR cpu(1)='1' THEN
IF (nextpass='1' OR opcode(5 downto 4)="00") AND exec(opcCHK)='0' AND micro_state=idle THEN
set_exec(opcCHK) <= '1';
END IF;
ea_build_now <= '1';
set(addsub) <= '1';
IF setexecOPC='1' THEN
dest_hbits <= '1';
source_lowbits <='1';
END IF;
END IF;
ELSE
trap_illegal <= '1'; -- chk long for 68020
trap_illegal <= '1';
trapmake <= '1';
END IF;
IF opcode(7)='1' OR cpu(1)='1' THEN
IF (nextpass='1' OR opcode(5 downto 4)="00") AND exec(opcCHK)='0' AND micro_state=idle THEN
set_exec(opcCHK) <= '1';
END IF;
ea_build_now <= '1';
set(addsub) <= '1';
IF setexecOPC='1' THEN
dest_hbits <= '1';
source_lowbits <='1';
END IF;
END IF;
END IF;
ELSE
CASE opcode(11 downto 9) IS
WHEN "000"=>
IF opcode(7 downto 6)="11" THEN --move from SR
IF SR_Read=0 OR (cpu(0)='0' AND SR_Read=2) OR SVmode='1' THEN
IF (opcode(5 downto 3)/="001" AND --ea An illegal mode
(opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00")) THEN --ea illegal modes
IF opcode(7 downto 6)="11" THEN --move from SR
IF SR_Read=0 OR (cpu(0)='0' AND SR_Read=2) OR SVmode='1' THEN
ea_build_now <= '1';
set_exec(opcMOVESR) <= '1';
datatype <= "01";
write_back <='1'; -- im 68000 wird auch erst gelesen
IF cpu(0)='1' AND state="10" THEN
skipFetch <= '1';
END IF;
IF opcode(5 downto 4)="00" THEN
set_exec(Regwrena) <= '1';
END IF;
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
ELSE --negx
ea_build_now <= '1';
set_exec(opcMOVESR) <= '1';
datatype <= "01";
write_back <='1'; -- im 68000 wird auch erst gelesen
IF cpu(0)='1' AND state="10" THEN
skipFetch <= '1';
END IF;
set_exec(use_XZFlag) <= '1';
write_back <='1';
set_exec(opcADD) <= '1';
set(addsub) <= '1';
source_lowbits <= '1';
IF opcode(5 downto 4)="00" THEN
set_exec(Regwrena) <= '1';
END IF;
ELSE
trap_priv <= '1';
trapmake <= '1';
IF setexecOPC='1' THEN
set(OP1out_zero) <= '1';
END IF;
END IF;
ELSE --negx
ea_build_now <= '1';
set_exec(use_XZFlag) <= '1';
write_back <='1';
set_exec(opcADD) <= '1';
set(addsub) <= '1';
source_lowbits <= '1';
IF opcode(5 downto 4)="00" THEN
set_exec(Regwrena) <= '1';
END IF;
IF setexecOPC='1' THEN
set(OP1out_zero) <= '1';
END IF;
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
WHEN "001"=>
IF opcode(7 downto 6)="11" THEN --move from CCR 68010
IF SR_Read=1 OR (cpu(0)='1' AND SR_Read=2) THEN
IF (opcode(5 downto 3)/="001" AND --ea An illegal mode
(opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00")) THEN --ea illegal modes
IF opcode(7 downto 6)="11" THEN --move from CCR 68010
IF SR_Read=1 OR (cpu(0)='1' AND SR_Read=2) THEN
ea_build_now <= '1';
set_exec(opcMOVESR) <= '1';
datatype <= "01";
write_back <='1'; -- im 68000 wird auch erst gelesen
-- IF state="10" THEN
-- skipFetch <= '1';
-- END IF;
IF opcode(5 downto 4)="00" THEN
set_exec(Regwrena) <= '1';
END IF;
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
ELSE --clr
ea_build_now <= '1';
set_exec(opcMOVESR) <= '1';
datatype <= "01";
write_back <='1'; -- im 68000 wird auch erst gelesen
-- IF state="10" THEN
-- skipFetch <= '1';
-- END IF;
write_back <='1';
set_exec(opcAND) <= '1';
IF cpu(0)='1' AND state="10" THEN
skipFetch <= '1';
END IF;
IF setexecOPC='1' THEN
set(OP1out_zero) <= '1';
END IF;
IF opcode(5 downto 4)="00" THEN
set_exec(Regwrena) <= '1';
END IF;
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
ELSE --clr
ea_build_now <= '1';
write_back <='1';
set_exec(opcAND) <= '1';
IF cpu(0)='1' AND state="10" THEN
skipFetch <= '1';
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
IF setexecOPC='1' THEN
set(OP1out_zero) <= '1';
END IF;
IF opcode(5 downto 4)="00" THEN
set_exec(Regwrena) <= '1';
END IF;
END IF;
WHEN "010"=>
ea_build_now <= '1';
IF opcode(7 downto 6)="11" THEN --move to CCR
datatype <= "01";
source_lowbits <= '1';
IF (decodeOPC='1' AND opcode(5 downto 4)="00") OR state="10" OR direct_data='1' THEN
set(to_CCR) <= '1';
IF opcode(5 downto 3)/="001" AND --ea An illegal mode
(opcode(5 downto 2)/="1111" OR opcode(1 downto 0)="00") THEN --ea illegal modes
ea_build_now <= '1';
datatype <= "01";
source_lowbits <= '1';
IF (decodeOPC='1' AND opcode(5 downto 4)="00") OR state="10" OR direct_data='1' THEN
set(to_CCR) <= '1';
END IF;
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
ELSE --neg
write_back <='1';
set_exec(opcADD) <= '1';
set(addsub) <= '1';
source_lowbits <= '1';
IF opcode(5 downto 4)="00" THEN
set_exec(Regwrena) <= '1';
IF (opcode(5 downto 3)/="001" AND --ea An illegal mode
(opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00")) THEN --ea illegal modes
ea_build_now <= '1';
write_back <='1';
set_exec(opcADD) <= '1';
set(addsub) <= '1';
source_lowbits <= '1';
IF opcode(5 downto 4)="00" THEN
set_exec(Regwrena) <= '1';
END IF;
IF setexecOPC='1' THEN
set(OP1out_zero) <= '1';
END IF;
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
IF setexecOPC='1' THEN
set(OP1out_zero) <= '1';
END IF;
END IF;
WHEN "011"=> --not, move toSR
IF opcode(7 downto 6)="11" THEN --move to SR
IF SVmode='1' THEN
IF opcode(5 downto 3)/="001" AND --ea An illegal mode
(opcode(5 downto 2)/="1111" OR opcode(1 downto 0)="00") THEN --ea illegal modes
IF SVmode='1' THEN
ea_build_now <= '1';
datatype <= "01";
source_lowbits <= '1';
IF (decodeOPC='1' AND opcode(5 downto 4)="00") OR state="10" OR direct_data='1' THEN
set(to_SR) <= '1';
set(to_CCR) <= '1';
END IF;
IF exec(to_SR)='1' OR (decodeOPC='1' AND opcode(5 downto 4)="00") OR state="10" OR direct_data='1' THEN
setstate <="01";
END IF;
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
ELSE --not
IF opcode(5 downto 3)/="001" AND --ea An illegal mode
(opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00") THEN --ea illegal modes
ea_build_now <= '1';
datatype <= "01";
source_lowbits <= '1';
IF (decodeOPC='1' AND opcode(5 downto 4)="00") OR state="10" OR direct_data='1' THEN
set(to_SR) <= '1';
set(to_CCR) <= '1';
write_back <='1';
set_exec(opcEOR) <= '1';
set_exec(ea_data_OP1) <= '1';
IF opcode(5 downto 3)="000" THEN
set_exec(Regwrena) <= '1';
END IF;
IF exec(to_SR)='1' OR (decodeOPC='1' AND opcode(5 downto 4)="00") OR state="10" OR direct_data='1' THEN
setstate <="01";
IF setexecOPC='1' THEN
set(OP2out_one) <= '1';
END IF;
ELSE
trap_priv <= '1';
trap_illegal <= '1';
trapmake <= '1';
END IF;
ELSE --not
ea_build_now <= '1';
write_back <='1';
set_exec(opcEOR) <= '1';
set_exec(ea_data_OP1) <= '1';
IF opcode(5 downto 3)="000" THEN
set_exec(Regwrena) <= '1';
END IF;
IF setexecOPC='1' THEN
set(OP2out_one) <= '1';
END IF;
END IF;
WHEN "100"|"110"=>
IF opcode(7)='1' THEN --movem, ext
1932,82 → 2143,94
set_exec(Regwrena) <= '1';
IF opcode(6)='0' THEN
datatype <= "01"; --WORD
set_exec(opcEXTB) <= '1';
END IF;
ELSE --movem
-- IF opcode(11 downto 7)="10001" OR opcode(11 downto 7)="11001" THEN --MOVEM
ea_only <= '1';
set(no_Flags) <= '1';
IF opcode(6)='0' THEN
datatype <= "01"; --Word transfer
END IF;
IF (opcode(5 downto 3)="100" OR opcode(5 downto 3)="011") AND state="01" THEN -- -(An), (An)+
set_exec(save_memaddr) <= '1';
set_exec(Regwrena) <= '1';
END IF;
IF opcode(5 downto 3)="100" THEN -- -(An)
movem_presub <= '1';
set(subidx) <= '1';
END IF;
IF state="10" THEN
set(Regwrena) <= '1';
set(opcMOVE) <= '1';
END IF;
IF decodeOPC='1' THEN
set(get_2ndOPC) <='1';
IF opcode(5 downto 3)="010" OR opcode(5 downto 3)="011" OR opcode(5 downto 3)="100" THEN
next_micro_state <= movem1;
ELSE
next_micro_state <= nop;
set(ea_build) <= '1';
END IF;
END IF;
IF set(get_ea_now)='1' THEN
IF movem_run='1' THEN
set(movem_action) <= '1';
IF opcode(10)='0' THEN
setstate <="11";
set(write_reg) <= '1';
IF (opcode(10)='1' OR ((opcode(5)='1' OR opcode(4 downto 3)="10") AND
(opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00"))) AND
(opcode(10)='0' OR (opcode(5 downto 4)/="00" AND
opcode(5 downto 3)/="100" AND
opcode(5 downto 2)/="1111")) THEN --ea illegal modes
ea_only <= '1';
set(no_Flags) <= '1';
IF opcode(6)='0' THEN
datatype <= "01"; --Word transfer
END IF;
IF (opcode(5 downto 3)="100" OR opcode(5 downto 3)="011") AND state="01" THEN -- -(An), (An)+
set_exec(save_memaddr) <= '1';
set_exec(Regwrena) <= '1';
END IF;
IF opcode(5 downto 3)="100" THEN -- -(An)
movem_presub <= '1';
set(subidx) <= '1';
END IF;
IF state="10" THEN
set(Regwrena) <= '1';
set(opcMOVE) <= '1';
END IF;
IF decodeOPC='1' THEN
set(get_2ndOPC) <='1';
IF opcode(5 downto 3)="010" OR opcode(5 downto 3)="011" OR opcode(5 downto 3)="100" THEN
next_micro_state <= movem1;
ELSE
setstate <="10";
next_micro_state <= nop;
set(ea_build) <= '1';
END IF;
next_micro_state <= movem2;
set(mem_addsub) <= '1';
ELSE
setstate <="01";
END IF;
IF set(get_ea_now)='1' THEN
IF movem_run='1' THEN
set(movem_action) <= '1';
IF opcode(10)='0' THEN
setstate <="11";
set(write_reg) <= '1';
ELSE
setstate <="10";
END IF;
next_micro_state <= movem2;
set(mem_addsub) <= '1';
ELSE
setstate <="01";
END IF;
END IF;
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
END IF;
ELSE
IF opcode(10)='1' THEN --MUL.L, DIV.L 68020
IF opcode(10)='1' THEN --MUL.L, DIV.L 68020
--FPGA Multiplier for long
IF MUL_Hardware=1 AND (opcode(6)='0' AND (MUL_Mode=1 OR (cpu(1)='1' AND MUL_Mode=2))) THEN
IF decodeOPC='1' THEN
next_micro_state <= nop;
set(get_2ndOPC) <= '1';
set(ea_build) <= '1';
END IF;
IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND exec(ea_build)='1') THEN
dest_2ndHbits <= '1';
datatype <= "10";
set(opcMULU) <= '1';
set(write_lowlong) <= '1';
IF sndOPC(10)='1' THEN
setstate <="01";
next_micro_state <= mul_end2;
END IF;
set(Regwrena) <= '1';
END IF;
source_lowbits <='1';
datatype <= "10";
 
--no FPGA Multplier
ELSIF (opcode(6)='1' AND (DIV_Mode=1 OR (cpu(1)='1' AND DIV_Mode=2))) OR
(opcode(6)='0' AND (MUL_Mode=1 OR (cpu(1)='1' AND MUL_Mode=2))) THEN
IF opcode(8 downto 7)="00" AND opcode(5 downto 3)/="001" AND --ea An illegal mode
MUL_Hardware=1 AND (opcode(6)='0' AND (MUL_Mode=1 OR (cpu(1)='1' AND MUL_Mode=2))) THEN
IF decodeOPC='1' THEN
next_micro_state <= nop;
set(get_2ndOPC) <= '1';
set(ea_build) <= '1';
END IF;
END IF;
IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND exec(ea_build)='1') THEN
dest_2ndHbits <= '1';
datatype <= "10";
set(opcMULU) <= '1';
set(write_lowlong) <= '1';
IF sndOPC(10)='1' THEN
setstate <="01";
next_micro_state <= mul_end2;
END IF;
set(Regwrena) <= '1';
END IF;
source_lowbits <='1';
datatype <= "10";
 
--no FPGA Multiplier
ELSIF opcode(8 downto 7)="00" AND opcode(5 downto 3)/="001" AND (opcode(5 downto 2)/="1111" OR opcode(1 downto 0)="00") AND --ea An illegal mode
((opcode(6)='1' AND (DIV_Mode=1 OR (cpu(1)='1' AND DIV_Mode=2))) OR
(opcode(6)='0' AND (MUL_Mode=1 OR (cpu(1)='1' AND MUL_Mode=2)))) THEN
IF decodeOPC='1' THEN
next_micro_state <= nop;
set(get_2ndOPC) <= '1';
set(ea_build) <= '1';
END IF;
IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND exec(ea_build)='1')THEN
setstate <="01";
dest_2ndHbits <= '1';
2016,7 → 2239,7
next_micro_state <= div1;
ELSE
next_micro_state <= mul1;
set(ld_rot_cnt) <= '1';
set(ld_rot_cnt) <= '1';
END IF;
END IF;
IF z_error='0' AND set_V_Flag='0' AND set(opcDIVU)='1' THEN
2039,22 → 2262,29
set_exec(opcSWAP) <= '1';
set_exec(Regwrena) <= '1';
ELSIF opcode(5 downto 3)="001" THEN --bkpt
trap_illegal <= '1';
trapmake <= '1';
trap_illegal <= '1';
trapmake <= '1';
ELSE --pea
ea_only <= '1';
ea_build_now <= '1';
IF nextpass='1' AND micro_state=idle THEN
set(presub) <= '1';
setstackaddr <='1';
setstate <="11";
next_micro_state <= nop;
IF (opcode(5)='1' OR opcode(4 downto 3)="10") AND
opcode(5 downto 3)/="100" AND
opcode(5 downto 2)/="1111" THEN --ea illegal modes
ea_only <= '1';
ea_build_now <= '1';
IF nextpass='1' AND micro_state=idle THEN
set(presub) <= '1';
setstackaddr <='1';
setstate <="11";
next_micro_state <= nop;
END IF;
IF set(get_ea_now)='1' THEN
setstate <="01";
END IF;
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
IF set(get_ea_now)='1' THEN
setstate <="01";
END IF;
END IF;
ELSE
END IF;
ELSE
IF opcode(5 downto 3)="001" THEN --link.l
datatype <= "10";
set_exec(opcADD) <= '1'; --for displacement
2071,20 → 2301,26
source_areg <= '1';
set(store_ea_data) <= '1';
END IF;
ELSE --nbcd
ea_build_now <= '1';
set_exec(use_XZFlag) <= '1';
write_back <='1';
set_exec(opcADD) <= '1';
set_exec(opcSBCD) <= '1';
set(addsub) <= '1';
source_lowbits <= '1';
IF opcode(5 downto 4)="00" THEN
set_exec(Regwrena) <= '1';
ELSE --nbcd
IF opcode(5 downto 3)/="001" AND --ea An illegal mode
(opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00") THEN --ea illegal modes
ea_build_now <= '1';
set_exec(use_XZFlag) <= '1';
write_back <='1';
set_exec(opcADD) <= '1';
set_exec(opcSBCD) <= '1';
set(addsub) <= '1';
source_lowbits <= '1';
IF opcode(5 downto 4)="00" THEN
set_exec(Regwrena) <= '1';
END IF;
IF setexecOPC='1' THEN
set(OP1out_zero) <= '1';
END IF;
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
IF setexecOPC='1' THEN
set(OP1out_zero) <= '1';
END IF;
END IF;
END IF;
END IF;
2092,25 → 2328,34
--0x4AXX
WHEN "101"=> --tst, tas 4aFC - illegal
-- IF opcode(7 downto 2)="111111" THEN --illegal
IF opcode(7 downto 3)="11111" AND opcode(2 downto 1)/="00" THEN --0x4AFC illegal --0x4AFB BKP Sinclair QL
IF opcode(7 downto 3)="11111" AND opcode(2 downto 1)/="00" THEN --0x4AFC illegal --0x4AFB BKP Sinclair QL
trap_illegal <= '1';
trapmake <= '1';
ELSE
ea_build_now <= '1';
IF setexecOPC='1' THEN
source_lowbits <= '1';
IF opcode(3)='1' THEN --MC68020...
source_areg <= '1';
IF (opcode(7 downto 6)/="11" OR --tas
(opcode(5 downto 3)/="001" AND --ea An illegal mode
(opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00"))) AND --ea illegal modes
((opcode(7 downto 6)/="00" OR (opcode(5 downto 3)/="001")) AND
(opcode(5 downto 2)/="1111" OR opcode(1 downto 0)="00")) THEN
ea_build_now <= '1';
IF setexecOPC='1' THEN
source_lowbits <= '1';
IF opcode(3)='1' THEN --MC68020...
source_areg <= '1';
END IF;
END IF;
END IF;
set_exec(opcMOVE) <= '1';
IF opcode(7 downto 6)="11" THEN --tas
set_exec_tas <= '1';
write_back <= '1';
datatype <= "00"; --Byte
IF opcode(5 downto 4)="00" THEN
set_exec(Regwrena) <= '1';
set_exec(opcMOVE) <= '1';
IF opcode(7 downto 6)="11" THEN --tas
set_exec_tas <= '1';
write_back <= '1';
datatype <= "00"; --Byte
IF opcode(5 downto 4)="00" THEN
set_exec(Regwrena) <= '1';
END IF;
END IF;
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
END IF;
---- WHEN "110"=>
2133,32 → 2378,38
IF opcode(7)='1' THEN --jsr, jmp
datatype <= "10";
ea_only <= '1';
ea_build_now <= '1';
IF exec(ea_to_pc)='1' THEN
next_micro_state <= nop;
END IF;
IF nextpass='1' AND micro_state=idle AND opcode(6)='0' THEN
set(presub) <= '1';
setstackaddr <='1';
setstate <="11";
next_micro_state <= nopnop;
END IF;
-- achtung buggefahr
IF micro_state=ld_AnXn1 AND brief(8)='0'THEN --JMP/JSR n(Ax,Dn)
skipFetch <= '1';
END IF;
IF state="00" THEN
writePC <= '1';
END IF;
set(hold_dwr) <= '1';
IF set(get_ea_now)='1' THEN --jsr
IF exec(longaktion)='0' OR long_done='1' THEN
IF (opcode(5)='1' OR opcode(4 downto 3)="10") AND
opcode(5 downto 3)/="100" AND opcode(5 downto 2)/="1111" THEN --ea illegal modes
datatype <= "10";
ea_only <= '1';
ea_build_now <= '1';
IF exec(ea_to_pc)='1' THEN
next_micro_state <= nop;
END IF;
IF nextpass='1' AND micro_state=idle AND opcode(6)='0' THEN
set(presub) <= '1';
setstackaddr <='1';
setstate <="11";
next_micro_state <= nopnop;
END IF;
IF micro_state=ld_AnXn1 AND brief(8)='0'THEN --JMP/JSR n(Ax,Dn)
skipFetch <= '1';
END IF;
setstate <="01";
set(ea_to_pc) <= '1';
IF state="00" THEN
writePC <= '1';
END IF;
set(hold_dwr) <= '1';
IF set(get_ea_now)='1' THEN --jsr
IF exec(longaktion)='0' OR long_done='1' THEN
skipFetch <= '1';
END IF;
setstate <="01";
set(ea_to_pc) <= '1';
END IF;
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
ELSE --
CASE opcode(6 downto 0) IS
2166,6 → 2417,7
"1001000"|"1001001"|"1001010"|"1001011"|"1001100"|"1001101"|"1001110"|"1001111" => --trap
trap_trap <='1';
trapmake <= '1';
WHEN "1010000"|"1010001"|"1010010"|"1010011"|"1010100"|"1010101"|"1010110"|"1010111"=> --link word
datatype <= "10";
set_exec(opcADD) <= '1'; --for displacement
2207,6 → 2459,7
trap_priv <= '1';
trapmake <= '1';
END IF;
WHEN "1101000"|"1101001"|"1101010"|"1101011"|"1101100"|"1101101"|"1101110"|"1101111" => --move USP,An
IF SVmode='1' THEN
-- set(no_Flags) <= '1';
2263,21 → 2516,21
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
END IF;
WHEN "1110100" => --rtd
datatype <= "10";
IF decodeOPC='1' THEN
setstate <= "10";
set(postadd) <= '1';
setstackaddr <= '1';
set(direct_delta) <= '1';
set(directPC) <= '1';
set_direct_data <= '1';
next_micro_state <= rtd1;
END IF;
WHEN "1110100" => --rtd
datatype <= "10";
IF decodeOPC='1' THEN
setstate <= "10";
set(postadd) <= '1';
setstackaddr <= '1';
set(direct_delta) <= '1';
set(directPC) <= '1';
set_direct_data <= '1';
next_micro_state <= rtd1;
END IF;
WHEN "1110101" => --rts
datatype <= "10";
IF decodeOPC='1' THEN
2333,8 → 2586,8
END CASE;
END IF;
--
---- 0101 ----------------------------------------------------------------------------
WHEN "0101" => --subq, addq
---- 0101 ----------------------------------------------------------------------------
WHEN "0101" => --subq, addq
IF opcode(7 downto 6)="11" THEN --dbcc
IF opcode(5 downto 3)="001" THEN --dbcc
IF decodeOPC='1' THEN
2341,30 → 2594,29
next_micro_state <= dbcc1;
set(OP2out_one) <= '1';
data_is_source <= '1';
END IF;
ELSIF opcode(5 downto 3)="111" AND (opcode(2 downto 1)="01" OR opcode(2 downto 0)="100") THEN --trapcc
IF cpu(1)='1' THEN -- only 68020+
IF opcode(2 downto 1)="01" THEN
IF decodeOPC='1' THEN
IF opcode(0)='1' THEN --long
set(longaktion) <= '1';
END IF;
next_micro_state <= nop;
END IF;
ELSE
IF decodeOPC='1' THEN
setstate <= "01";
END IF;
END IF;
trap_trapcc<='1';
IF exe_condition='1' AND decodeOPC='0' THEN
trap_trapv <= '1';
trapmake <= '1';
END IF;
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
END IF;
ELSIF opcode(5 downto 3)="111" AND (opcode(2 downto 1)="01" OR opcode(2 downto 0)="100") THEN --trapcc
IF cpu(1)='1' THEN -- only 68020+
IF opcode(2 downto 1)="01" THEN
IF decodeOPC='1' THEN
IF opcode(0)='1' THEN --long
set(longaktion) <= '1';
END IF;
next_micro_state <= nop;
END IF;
ELSE
IF decodeOPC='1' THEN
setstate <= "01";
END IF;
END IF;
IF exe_condition='1' AND decodeOPC='0' THEN
trap_trapv <= '1';
trapmake <= '1';
END IF;
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
ELSE --Scc
datatype <= "00"; --Byte
ea_build_now <= '1';
2373,26 → 2625,32
IF cpu(0)='1' AND state="10" THEN
skipFetch <= '1';
END IF;
IF opcode(5 downto 4)="00" THEN
IF opcode(5 downto 4)="00" THEN
set_exec(Regwrena) <= '1';
END IF;
END IF;
ELSE --addq, subq
ea_build_now <= '1';
IF opcode(5 downto 3)="001" THEN
set(no_Flags) <= '1';
IF opcode(7 downto 3)/="00001" AND
(opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00") THEN --ea illegal modes
ea_build_now <= '1';
IF opcode(5 downto 3)="001" THEN
set(no_Flags) <= '1';
END IF;
IF opcode(8)='1' THEN
set(addsub) <= '1';
END IF;
write_back <= '1';
set_exec(opcADDQ) <= '1';
set_exec(opcADD) <= '1';
set_exec(ea_data_OP1) <= '1';
IF opcode(5 downto 4)="00" THEN
set_exec(Regwrena) <= '1';
END IF;
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
IF opcode(8)='1' THEN
set(addsub) <= '1';
END IF;
write_back <= '1';
set_exec(opcADDQ) <= '1';
set_exec(opcADD) <= '1';
set_exec(ea_data_OP1) <= '1';
IF opcode(5 downto 4)="00" THEN
set_exec(Regwrena) <= '1';
END IF;
END IF;
END IF;
--
---- 0110 ----------------------------------------------------------------------------
WHEN "0110" => --bra,bsr,bcc
2427,20 → 2685,26
-- 0111 ----------------------------------------------------------------------------
WHEN "0111" => --moveq
IF opcode(8)='0' THEN
datatype <= "10"; --Long
set_exec(Regwrena) <= '1';
set_exec(opcMOVEQ) <= '1';
set_exec(opcMOVE) <= '1';
dest_hbits <= '1';
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
---- 1000 ----------------------------------------------------------------------------
WHEN "1000" => --or
IF opcode(7 downto 6)="11" THEN --divu, divs
IF DIV_Mode/=3 THEN
IF DIV_Mode/=3 AND
opcode(5 downto 3)/="001" AND (opcode(5 downto 2)/="1111" OR opcode(1 downto 0)="00") THEN --ea illegal modes
IF opcode(5 downto 4)="00" THEN --Dn, An
regdirectsource <= '1';
END IF;
IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
setstate <="01";
next_micro_state <= div1;
END IF;
2449,7 → 2713,7
set_exec(Regwrena) <= '1';
END IF;
source_lowbits <='1';
IF nextpass='1' OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
IF nextpass='1' OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
dest_hbits <= '1';
END IF;
datatype <= "01";
2457,83 → 2721,95
trap_illegal <= '1';
trapmake <= '1';
END IF;
ELSIF opcode(8)='1' AND opcode(5 downto 4)="00" THEN --sbcd, pack , unpack
IF opcode(7 downto 6)="00" THEN --sbcd
build_bcd <= '1';
set_exec(opcADD) <= '1';
set_exec(opcSBCD) <= '1';
set(addsub) <= '1';
ELSIF opcode(7 downto 6)="01" OR opcode(7 downto 6)="10" THEN --pack , unpack
set_exec(ea_data_OP1) <= '1';
set(no_Flags) <= '1';
source_lowbits <='1';
IF opcode(7 downto 6) = "01" THEN --pack
set_exec(opcPACK) <= '1';
datatype <= "01"; --Word
ELSE --unpk
set_exec(opcUNPACK) <= '1';
datatype <= "00"; --Byte
END IF;
IF opcode(3)='0' THEN
IF opcode(7 downto 6) = "01" THEN --pack
set_datatype <= "00"; --Byte
ELSE --unpk
set_datatype <= "01"; --Word
END IF;
set_exec(Regwrena) <= '1';
dest_hbits <= '1';
IF decodeOPC='1' THEN
next_micro_state <= nop;
-- set_direct_data <= '1';
set(store_ea_packdata) <= '1';
set(store_ea_data) <= '1';
END IF;
ELSE -- pack -(Ax),-(Ay)
write_back <= '1';
IF decodeOPC='1' THEN
next_micro_state <= pack1;
set_direct_data <= '1';
END IF;
END IF;
ELSE
set(addsub) <= '1';
ELSIF opcode(7 downto 6)="01" OR opcode(7 downto 6)="10" THEN --pack , unpack
set_exec(ea_data_OP1) <= '1';
set(no_Flags) <= '1';
source_lowbits <='1';
IF opcode(7 downto 6) = "01" THEN --pack
set_exec(opcPACK) <= '1';
datatype <= "01"; --Word
ELSE --unpk
set_exec(opcUNPACK) <= '1';
datatype <= "00"; --Byte
END IF;
IF opcode(3)='0' THEN
IF opcode(7 downto 6) = "01" THEN --pack
set_datatype <= "00"; --Byte
ELSE --unpk
set_datatype <= "01"; --Word
END IF;
set_exec(Regwrena) <= '1';
dest_hbits <= '1';
IF decodeOPC='1' THEN
next_micro_state <= nop;
-- set_direct_data <= '1';
set(store_ea_packdata) <= '1';
set(store_ea_data) <= '1';
END IF;
ELSE -- pack -(Ax),-(Ay)
write_back <= '1';
IF decodeOPC='1' THEN
next_micro_state <= pack1;
set_direct_data <= '1';
END IF;
END IF;
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
ELSE --or
set_exec(opcOR) <= '1';
build_logical <= '1';
IF opcode(7 downto 6)/="11" AND --illegal opmode
((opcode(8)='0' AND opcode(5 downto 3)/="001" AND (opcode(5 downto 2)/="1111" OR opcode(1 downto 0)="00")) OR --illegal src ea
(opcode(8)='1' AND opcode(5 downto 4)/="00" AND (opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00"))) THEN --illegal dst ea
set_exec(opcOR) <= '1';
build_logical <= '1';
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
END IF;
---- 1001, 1101 -----------------------------------------------------------------------
WHEN "1001"|"1101" => --sub, add
set_exec(opcADD) <= '1';
ea_build_now <= '1';
IF opcode(14)='0' THEN
set(addsub) <= '1';
END IF;
IF opcode(7 downto 6)="11" THEN -- --adda, suba
IF opcode(8)='0' THEN --adda.w, suba.w
datatype <= "01"; --Word
WHEN "1001"|"1101" => --sub, add
IF opcode(8 downto 3)/="000001" AND --byte src address reg direct
(((opcode(8)='0' OR opcode(7 downto 6)="11") AND (opcode(5 downto 2)/="1111" OR opcode(1 downto 0)="00")) OR --illegal src ea
(opcode(8)='1' AND (opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00"))) THEN --illegal dst ea
set_exec(opcADD) <= '1';
ea_build_now <= '1';
IF opcode(14)='0' THEN
set(addsub) <= '1';
END IF;
set_exec(Regwrena) <= '1';
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
IF opcode(7 downto 6)="11" THEN -- --adda, suba
IF opcode(8)='0' THEN --adda.w, suba.w
datatype <= "01"; --Word
END IF;
set_exec(Regwrena) <= '1';
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
set(no_Flags) <= '1';
IF setexecOPC='1' THEN
dest_areg <='1';
dest_hbits <= '1';
END IF;
ELSE
IF opcode(8)='1' AND opcode(5 downto 4)="00" THEN --addx, subx
build_bcd <= '1';
ELSE --sub, add
build_logical <= '1';
END IF;
END IF;
set(no_Flags) <= '1';
IF setexecOPC='1' THEN
dest_areg <='1';
dest_hbits <= '1';
END IF;
ELSE
IF opcode(8)='1' AND opcode(5 downto 4)="00" THEN --addx, subx
build_bcd <= '1';
ELSE --sub, add
build_logical <= '1';
END IF;
END IF;
 
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
--
---- 1010 ----------------------------------------------------------------------------
WHEN "1010" => --Trap 1010
2541,30 → 2817,36
trapmake <= '1';
---- 1011 ----------------------------------------------------------------------------
WHEN "1011" => --eor, cmp
ea_build_now <= '1';
IF opcode(7 downto 6)="11" THEN --CMPA
IF opcode(8)='0' THEN --cmpa.w
datatype <= "01"; --Word
set_exec(opcCPMAW) <= '1';
IF opcode(5 downto 2)/="1111" OR opcode(1 downto 0)="00" THEN --illegal src ea
ea_build_now <= '1';
IF opcode(8)='0' THEN --cmpa.w
datatype <= "01"; --Word
set_exec(opcCPMAW) <= '1';
END IF;
set_exec(opcCMP) <= '1';
IF setexecOPC='1' THEN
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
dest_areg <='1';
dest_hbits <= '1';
END IF;
set(addsub) <= '1';
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
set_exec(opcCMP) <= '1';
IF setexecOPC='1' THEN
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
dest_areg <='1';
dest_hbits <= '1';
END IF;
set(addsub) <= '1';
ELSE
ELSE --cmpm, eor, cmp
IF opcode(8)='1' THEN
IF opcode(5 downto 3)="001" THEN --cmpm
ea_build_now <= '1';
set_exec(opcCMP) <= '1';
IF decodeOPC='1' THEN
IF opcode(2 downto 0)="111" THEN
set(use_SP) <= '1';
END IF;
IF opcode(2 downto 0)="111" THEN
set(use_SP) <= '1';
END IF;
setstate <= "10";
set(update_ld) <= '1';
set(postadd) <= '1';
2573,49 → 2855,61
set_exec(ea_data_OP1) <= '1';
set(addsub) <= '1';
ELSE --EOR
IF opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00" THEN --illegal dst ea
ea_build_now <= '1';
build_logical <= '1';
set_exec(opcEOR) <= '1';
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
END IF;
ELSE --CMP
IF opcode(8 downto 3)/="000001" AND --byte src address reg direct
(opcode(5 downto 2)/="1111" OR opcode(1 downto 0)="00") THEN --illegal src ea
ea_build_now <= '1';
build_logical <= '1';
set_exec(opcEOR) <= '1';
set_exec(opcCMP) <= '1';
set(addsub) <= '1';
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
ELSE --CMP
build_logical <= '1';
set_exec(opcCMP) <= '1';
set(addsub) <= '1';
END IF;
END IF;
END IF;
--
---- 1100 ----------------------------------------------------------------------------
WHEN "1100" => --and, exg
IF opcode(7 downto 6)="11" THEN --mulu, muls
IF MUL_Mode/=3 THEN
IF MUL_Mode/=3 AND
opcode(5 downto 3)/="001" AND (opcode(5 downto 2)/="1111" OR opcode(1 downto 0)="00") THEN --ea illegal modes
IF opcode(5 downto 4)="00" THEN --Dn, An
regdirectsource <= '1';
END IF;
END IF;
IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
IF MUL_Hardware=0 THEN
setstate <="01";
set(ld_rot_cnt) <= '1';
set(ld_rot_cnt) <= '1';
next_micro_state <= mul1;
ELSE
ELSE
set_exec(write_lowlong) <= '1';
set_exec(opcMULU) <= '1';
END IF;
set_exec(opcMULU) <= '1';
END IF;
END IF;
ea_build_now <= '1';
set_exec(Regwrena) <= '1';
set_exec(Regwrena) <= '1';
source_lowbits <='1';
IF (nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
dest_hbits <= '1';
END IF;
datatype <= "01";
IF setexecOPC='1' THEN
datatype <= "10";
END IF;
 
datatype <= "01";
IF setexecOPC='1' THEN
datatype <= "10";
END IF;
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
ELSIF opcode(8)='1' AND opcode(5 downto 4)="00" THEN --exg, abcd
IF opcode(7 downto 6)="00" THEN --abcd
build_bcd <= '1';
2622,40 → 2916,62
set_exec(opcADD) <= '1';
set_exec(opcABCD) <= '1';
ELSE --exg
datatype <= "10";
set(Regwrena) <= '1';
set(exg) <= '1';
IF opcode(6)='1' AND opcode(3)='1' THEN
dest_areg <= '1';
source_areg <= '1';
END IF;
IF decodeOPC='1' THEN
setstate <= "01";
IF opcode(7 downto 4)="0100" OR opcode(7 downto 3)="10001" THEN
datatype <= "10";
set(Regwrena) <= '1';
set(exg) <= '1';
set(alu_move) <= '1';
IF opcode(6)='1' AND opcode(3)='1' THEN
dest_areg <= '1';
source_areg <= '1';
END IF;
IF decodeOPC='1' THEN
setstate <= "01";
ELSE
dest_hbits <= '1';
END IF;
ELSE
dest_hbits <= '1';
trap_illegal <= '1';
trapmake <= '1';
END IF;
END IF;
ELSE --and
set_exec(opcAND) <= '1';
build_logical <= '1';
END IF;
IF opcode(7 downto 6)/="11" AND --illegal opmode
((opcode(8)='0' AND opcode(5 downto 3)/="001" AND (opcode(5 downto 2)/="1111" OR opcode(1 downto 0)="00")) OR --illegal src ea
(opcode(8)='1' AND opcode(5 downto 4)/="00" AND (opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00"))) THEN --illegal dst ea
set_exec(opcAND) <= '1';
build_logical <= '1';
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
END IF;
--
---- 1110 ----------------------------------------------------------------------------
WHEN "1110" => --rotation / bitfield
IF opcode(7 downto 6)="11" THEN
IF opcode(11)='0' THEN
IF BarrelShifter=0 THEN
set_exec(opcROT) <= '1';
ELSE
set_exec(exec_BS) <='1';
END IF;
ea_build_now <= '1';
datatype <= "01";
set_rot_bits <= opcode(10 downto 9);
set_exec(ea_data_OP1) <= '1';
write_back <= '1';
IF (opcode(5 downto 4)/="00" AND (opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00")) THEN --ea illegal modes
IF BarrelShifter=0 THEN
set_exec(opcROT) <= '1';
ELSE
set_exec(exec_BS) <='1';
END IF;
ea_build_now <= '1';
datatype <= "01";
set_rot_bits <= opcode(10 downto 9);
set_exec(ea_data_OP1) <= '1';
write_back <= '1';
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
ELSE --bitfield
IF BitField=0 OR (cpu(1)='0' AND BitField=2) THEN
IF BitField=0 OR (cpu(1)='0' AND BitField=2) OR
((opcode(10 downto 9)="11" OR opcode(10 downto 8)="010" OR opcode(10 downto 8)="100") AND
(opcode(5 downto 3)="001" OR opcode(5 downto 3)="011" OR opcode(5 downto 3)="100" OR (opcode(5 downto 3)="111" AND opcode(2 downto 1)/="00"))) OR
((opcode(10 downto 9)="00" OR opcode(10 downto 8)="011" OR opcode(10 downto 8)="101") AND
(opcode(5 downto 3)="001" OR opcode(5 downto 3)="011" OR opcode(5 downto 3)="100" OR opcode(5 downto 2)="1111")) THEN
trap_illegal <= '1';
trapmake <= '1';
ELSE
2663,26 → 2979,25
next_micro_state <= nop;
set(get_2ndOPC) <= '1';
set(ea_build) <= '1';
END IF;
END IF;
set_exec(opcBF) <= '1';
-- 000-bftst, 001-bfextu, 010-bfchg, 011-bfexts, 100-bfclr, 101-bfff0, 110-bfset, 111-bfins
IF opcode(10)='1' OR opcode(8)='0' THEN
IF opcode(10)='1' OR opcode(8)='0' THEN
set_exec(opcBFwb) <= '1'; --'1' for tst,chg,clr,ffo,set,ins --'0' for extu,exts
END IF;
END IF;
IF opcode(10 downto 8)="111" THEN --BFINS
set_exec(ea_data_OP1) <= '1';
END IF;
 
END IF;
IF opcode(10 downto 8)="010" OR opcode(10 downto 8)="100" OR opcode(10 downto 8)="110" OR opcode(10 downto 8)="111" THEN
write_back <= '1';
END IF;
END IF;
ea_only <= '1';
IF opcode(10 downto 8)="001" OR opcode(10 downto 8)="011" OR opcode(10 downto 8)="101" THEN
set_exec(Regwrena) <= '1';
END IF;
IF opcode(4 downto 3)="00" THEN
END IF;
IF opcode(4 downto 3)="00" THEN
IF opcode(10 downto 8)/="000" THEN
set_exec(Regwrena) <= '1';
set_exec(Regwrena) <= '1';
END IF;
IF exec(ea_build)='1' THEN
dest_2ndHbits <= '1';
2693,7 → 3008,7
END IF;
IF set(get_ea_now)='1' THEN
setstate <= "01";
END IF;
END IF;
IF exec(get_ea_now)='1' THEN
dest_2ndHbits <= '1';
source_2ndLbits <= '1';
2702,23 → 3017,21
set(mem_addsub) <='1';
next_micro_state <= bf1;
END IF;
IF setexecOPC='1' THEN
IF setexecOPC='1' THEN
IF opcode(10 downto 8)="111" THEN --BFINS
source_2ndHbits <= '1';
ELSE
ELSE
source_lowbits <= '1';
END IF;
IF opcode(10 downto 8)="001" OR opcode(10 downto 8)="011" OR opcode(10 downto 8)="101" THEN --BFEXT, BFFFO
dest_2ndHbits <= '1';
END IF;
END IF;
IF opcode(10 downto 8)="001" OR opcode(10 downto 8)="011" OR opcode(10 downto 8)="101" THEN --BFEXT, BFFFO
dest_2ndHbits <= '1';
END IF;
END IF;
END IF;
END IF;
ELSE
ELSE
data_is_source <= '1';
IF BarrelShifter=0 OR (cpu(1)='0' AND BarrelShifter=2) THEN
 
IF BarrelShifter=0 OR (cpu(1)='0' AND BarrelShifter=2) THEN
set_exec(opcROT) <= '1';
set_rot_bits <= opcode(4 downto 3);
set_exec(Regwrena) <= '1';
2735,20 → 3048,94
set_rot_cnt(3) <='0';
END IF;
END IF;
END IF;
ELSE
set_exec(exec_BS) <='1';
set_rot_bits <= opcode(4 downto 3);
set_exec(Regwrena) <= '1';
END IF;
ELSE
set_exec(exec_BS) <='1';
set_rot_bits <= opcode(4 downto 3);
set_exec(Regwrena) <= '1';
END IF;
END IF;
END IF;
--
---- 1111 ----------------------------------------------------------------------------
WHEN "1111" =>
IF cpu(1)='1' AND opcode(8 downto 6)="100" THEN --cpSAVE
IF opcode(5 downto 4)/="00" AND opcode(5 downto 3)/="011" AND
(opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00") THEN --ea illegal modes
IF opcode(11 downto 9)/="000" THEN
IF SVmode='1' THEN
IF opcode(5)='0' AND opcode(5 downto 4)/="01" THEN
--never reached according to cputest?!
--cpSAVE not implemented
trap_illegal <= '1';
trapmake <= '1';
ELSE
trap_1111 <= '1';
trapmake <= '1';
END IF;
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
ELSE
IF SVmode='1' THEN
trap_1111 <= '1';
trapmake <= '1';
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
END IF;
ELSE
trap_1111 <= '1';
trapmake <= '1';
END IF;
ELSIF cpu(1)='1' AND opcode(8 downto 6)="101" THEN --cpRESTORE
IF opcode(5 downto 4)/="00" AND opcode(5 downto 3)/="100" AND
(opcode(5 downto 3)/="111" OR (opcode(2 downto 1)/="11" AND
opcode(2 downto 0)/="101")) THEN --ea illegal modes
IF opcode(5 downto 1)/="11110" THEN
IF opcode(11 downto 9)="001" OR opcode(11 downto 9)="010" THEN
IF SVmode='1' THEN
IF opcode(5 downto 3)="101" THEN
--cpRESTORE not implemented
trap_illegal <= '1';
trapmake <= '1';
ELSE
trap_1111 <= '1';
trapmake <= '1';
END IF;
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
ELSE
IF SVmode='1' THEN
trap_1111 <= '1';
trapmake <= '1';
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
END IF;
ELSE
trap_1111 <= '1';
trapmake <= '1';
END IF;
ELSE
trap_1111 <= '1';
trapmake <= '1';
END IF;
ELSE
trap_1111 <= '1';
trapmake <= '1';
END IF;
--
---- ----------------------------------------------------------------------------
WHEN OTHERS =>
trap_1111 <= '1';
WHEN OTHERS =>
trap_illegal <= '1';
trapmake <= '1';
 
END CASE;
END CASE;
 
-- use for AND, OR, EOR, CMP
IF build_logical='1' THEN
3042,8 → 3429,132
next_micro_state <= nop;
TG68_PC_brw <= '1';
END IF;
END IF;
END IF;
 
WHEN chk20 => --if C is set -> signed compare
set(ea_data_OP1) <= '1';
set(addsub) <= '1';
set(alu_exec) <= '1';
set(alu_setFlags) <= '1';
setstate <="01";
next_micro_state <= chk21;
WHEN chk21 => -- check lower bound
dest_2ndHbits <= '1';
IF sndOPC(15)='1' THEN
set_datatype <="10"; --long
dest_LDRareg <= '1';
IF opcode(10 downto 9)="00" THEN
set(opcEXTB) <= '1';
END IF;
END IF;
set(addsub) <= '1';
set(alu_exec) <= '1';
set(alu_setFlags) <= '1';
setstate <="01";
next_micro_state <= chk22;
WHEN chk22 => --check upper bound
dest_2ndHbits <= '1';
set(ea_data_OP2) <= '1';
IF sndOPC(15)='1' THEN
set_datatype <="10"; --long
dest_LDRareg <= '1';
END IF;
set(addsub) <= '1';
set(alu_exec) <= '1';
set(opcCHK2) <= '1';
set(opcEXTB) <= exec(opcEXTB);
IF sndOPC(11)='1' THEN
setstate <="01";
next_micro_state <= chk23;
END IF;
WHEN chk23 =>
setstate <="01";
next_micro_state <= chk24;
WHEN chk24 =>
IF Flags(0)='1'THEN
trapmake <= '1';
END IF;
WHEN cas1 =>
setstate <="01";
next_micro_state <= cas2;
WHEN cas2 =>
source_2ndMbits <= '1';
IF Flags(2)='1'THEN
setstate<="11";
set(write_reg) <= '1';
set(restore_ADDR) <= '1';
next_micro_state <= nop;
ELSE
set(Regwrena) <= '1';
set(ea_data_OP2) <='1';
dest_2ndLbits <= '1';
set(alu_move) <= '1';
END IF;
WHEN cas21 =>
dest_2ndHbits <= '1';
dest_LDRareg <= sndOPC(15);
set(get_ea_now) <='1';
next_micro_state <= cas22;
WHEN cas22 =>
setstate <= "01";
source_2ndLbits <= '1';
set(ea_data_OP1) <= '1';
set(addsub) <= '1';
set(alu_exec) <= '1';
set(alu_setFlags) <= '1';
next_micro_state <= cas23;
WHEN cas23 =>
dest_LDRHbits <= '1';
set(get_ea_now) <='1';
next_micro_state <= cas24;
WHEN cas24 =>
IF Flags(2)='1'THEN
set(alu_setFlags) <= '1';
END IF;
setstate <="01";
set(hold_dwr) <= '1';
source_LDRLbits <= '1';
set(ea_data_OP1) <= '1';
set(addsub) <= '1';
set(alu_exec) <= '1';
next_micro_state <= cas25;
WHEN cas25 =>
setstate <= "01";
set(hold_dwr) <= '1';
next_micro_state <= cas26;
WHEN cas26 =>
IF Flags(2)='1'THEN -- write Update 1 to Destination 1
source_2ndMbits <= '1';
set(write_reg) <= '1';
dest_2ndHbits <= '1';
dest_LDRareg <= sndOPC(15);
setstate <= "11";
set(get_ea_now) <='1';
next_micro_state <= cas27;
ELSE -- write Destination 2 to Compare 2 first
set(hold_dwr) <= '1';
set(hold_OP2) <='1';
dest_LDRLbits <= '1';
set(alu_move) <= '1';
set(Regwrena) <= '1';
set(ea_data_OP2) <='1';
next_micro_state <= cas28;
END IF;
WHEN cas27 => -- write Update 2 to Destination 2
source_LDRMbits <= '1';
set(write_reg) <= '1';
dest_LDRHbits <= '1';
setstate <= "11";
set(get_ea_now) <='1';
next_micro_state <= nopnop;
WHEN cas28 => -- write Destination 1 to Compare 1 second
dest_2ndLbits <= '1';
set(alu_move) <= '1';
set(Regwrena) <= '1';
WHEN movem1 => --movem
IF last_data_read(15 downto 0)/=X"0000" THEN
setstate <="01";
3375,7 → 3886,8
set(Regwrena) <= '1';
END IF;
datatype <= "10";
WHEN mul_end2 => -- divu
WHEN mul_end2 => -- divu
dest_2ndLbits <= '1';
set(write_reminder) <= '1';
set(Regwrena) <= '1';
set(opcMULU) <= '1';
3408,6 → 3920,7
END IF;
WHEN div_end1 => -- divu
IF opcode(15)='0' AND (DIV_Mode=1 OR DIV_Mode=2) THEN
dest_2ndLbits <= '1';
set(write_reminder) <= '1';
next_micro_state <= div_end2;
setstate <="01";

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