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URL https://opencores.org/ocsvn/wbscope/wbscope/trunk

Subversion Repositories wbscope

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    from Rev 10 to Rev 11
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Rev 10 → Rev 11

/wbscope/trunk/rtl/wbscopc.v
36,7 → 36,7
// scope is still to be defined.
//
// Like I said, this version is placed here for discussion purposes,
// not because it runs nor because I have recognized that it has any
// not because it runs well nor because I have recognized that it has any
// particular value (yet).
//
// Well, I take that back. When dealing with an interface such as the
48,8 → 48,18
// you'll wish to add the trigger as another data line, so you can find
// when it took place in your own data?
//
// Okay, I take that back twice: I'm finding this compressed scope very
// valuable for evaluating the timing associated with a GPS PPS and
// associated NMEA stream. I need to collect over a seconds worth of
// data, and I don't have enough memory to handle one memory value per
// clock, yet I still want to know exactly when the GPS PPS goes high,
// when it goes low, when I'm adjusting my clock, and when the clock's
// PPS output goes high. Did I synchronize them well? Oh, and when does
// the NMEA time string show up when compared with the PPS? All of those
// are valuable, but could never be done if the scope wasn't compressed.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Tecnology, LLC
// Gisselquist Technology, LLC
//
///////////////////////////////////////////////////////////////////////////
//
81,10 → 91,10
i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
o_wb_ack, o_wb_stall, o_wb_data,
o_interrupt);
parameter LGMEM = 5'd10, BUSW = 32, SYNCHRONOUS=1;
parameter LGMEM = 5'd10, NELM=32, BUSW = 32, SYNCHRONOUS=1;
// The input signals that we wish to record
input i_clk, i_ce, i_trigger;
input [(BUSW-2):0] i_data;
input [(NELM-1):0] i_data;
// The WISHBONE bus for reading and configuring this scope
input i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we;
input i_wb_addr; // One address line only
117,7 → 127,8
// data changes, but increment it on all other clocks. Should the
// address difference get to our maximum value, we let it saturate
// rather than overflow.
reg [(BUSW-2):0] ck_addr, lst_dat;
reg [(BUSW-2):0] ck_addr;
reg [(NELM-1):0] lst_dat;
initial ck_addr = 0;
always @(posedge i_clk)
if ((lcl_reset)||((i_ce)&&(i_data != lst_dat)))
145,10 → 156,10
imm_adr <= 1'b1;
lst_val <= 31'h0;
lst_adr <= 1'b1;
lst_dat <= 31'b0;
lst_dat <= 0;
end else if ((i_ce)&&(i_data != lst_dat))
begin
imm_val <= i_data;
imm_val <= { {(BUSW-1-NELM){1'b0}}, i_data };
imm_adr <= 1'b0;
lst_val <= imm_val;
lst_adr <= imm_adr;
172,14 → 183,30
always @(posedge i_clk)
r_data <= ((~lst_adr)||(~imm_adr))
? { lst_adr, lst_val }
: { 1'b0, i_data };
: { {(32 - NELM){1'b0}}, i_data };
 
 
//
// The trigger needs some extra attention, in order to keep triggers
// that happen between events from being ignored.
//
wire w_trigger;
assign w_trigger = (r_trigger)||(i_trigger);
 
reg r_trigger;
initial r_trigger = 1'b0;
always @(posedge i_clk)
if (lcl_reset)
r_trigger <= 1'b0;
else
r_trigger <= w_trigger;
 
//
// Call the regular wishbone scope to do all of our real work, now
// that we've compressed the input.
//
wbscope #(.SYNCHRONOUS(1), .LGMEM(LGMEM),
.BUSW(BUSW)) cheatersscope(i_clk, r_ce, i_trigger, r_data,
.BUSW(BUSW)) cheatersscope(i_clk, r_ce, w_trigger, r_data,
i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
o_wb_ack, o_wb_stall, o_wb_data, o_interrupt);
endmodule
/wbscope/trunk/rtl/wbscope.v
56,7 → 56,7
// dw_ A wire/net, controlled by the data clock
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Tecnology, LLC
// Gisselquist Technology, LLC
//
///////////////////////////////////////////////////////////////////////////
//
/wbscope/trunk/sw/cfgscope.cpp
21,7 → 21,7
// a simulator difficult.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Tecnology, LLC
// Gisselquist Technology, LLC
//
///////////////////////////////////////////////////////////////////////////
//

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