URL
https://opencores.org/ocsvn/xge_mac/xge_mac/trunk
Subversion Repositories xge_mac
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- This comparison shows the changes necessary to convert path
/
- from Rev 10 to Rev 11
- ↔ Reverse comparison
Rev 10 → Rev 11
/xge_mac/trunk/rtl/verilog/generic_fifo_ctrl.v
102,6 → 102,7
// Combinatorial |
|
wire [AWIDTH:0] wr_gray; |
reg [AWIDTH:0] wr_gray_reg; |
reg [AWIDTH:0] wr_gray_meta; |
reg [AWIDTH:0] wr_gray_sync; |
reg [AWIDTH:0] wck_rd_ptr; |
108,6 → 109,7
wire [AWIDTH:0] wck_level; |
|
wire [AWIDTH:0] rd_gray; |
reg [AWIDTH:0] rd_gray_reg; |
reg [AWIDTH:0] rd_gray_meta; |
reg [AWIDTH:0] rd_gray_sync; |
reg [AWIDTH:0] rck_wr_ptr; |
202,11 → 204,13
always @(posedge rclk or negedge rrst_n) |
begin |
if (!rrst_n) begin |
rd_gray_reg <= {(AWIDTH+1){1'b0}}; |
wr_gray_meta <= {(AWIDTH+1){1'b0}}; |
wr_gray_sync <= {(AWIDTH+1){1'b0}}; |
end |
else begin |
wr_gray_meta <= wr_gray; |
rd_gray_reg <= rd_gray; |
wr_gray_meta <= wr_gray_reg; |
wr_gray_sync <= wr_gray_meta; |
end |
end |
214,11 → 218,13
always @(posedge wclk or negedge wrst_n) |
begin |
if (!wrst_n) begin |
wr_gray_reg <= {(AWIDTH+1){1'b0}}; |
rd_gray_meta <= {(AWIDTH+1){1'b0}}; |
rd_gray_sync <= {(AWIDTH+1){1'b0}}; |
end |
else begin |
rd_gray_meta <= rd_gray; |
wr_gray_reg <= wr_gray; |
rd_gray_meta <= rd_gray_reg; |
rd_gray_sync <= rd_gray_meta; |
end |
end |
251,7 → 257,7
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// With early read, data will be present at output |
// before ren is asserted. Usufull if we want to add |
// an output register and not add latency. |
// an output register and not add latency. |
assign mem_raddr = next_rd_ptr; |
assign mem_ren = 1'b1; |
|
265,6 → 271,3
endgenerate |
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endmodule |
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/xge_mac/trunk/tbench/verilog/packets_tx.txt
70,4 → 70,4
02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 |
12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 |
22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 |
32 33 34 35 |
32 33 34 35 |