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URL https://opencores.org/ocsvn/ac97/ac97/trunk

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Rev 9 → Rev 10

/trunk/bench/verilog/test_bench_top.v
37,10 → 37,10
 
// CVS Log
//
// $Id: test_bench_top.v,v 1.1 2002-02-13 08:22:32 rudi Exp $
// $Id: test_bench_top.v,v 1.2 2002-03-05 04:44:04 rudi Exp $
//
// $Date: 2002-02-13 08:22:32 $
// $Revision: 1.1 $
// $Date: 2002-03-05 04:44:04 $
// $Revision: 1.2 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,8 → 47,12
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/02/13 08:22:32 rudi
//
// Added test bench for public release
//
//
//
//
 
`include "ac97_defines.v"
113,8 → 117,19
integer ic1_ptr;
integer ic2_ptr;
 
integer oc0_th;
integer oc1_th;
integer oc2_th;
integer oc3_th;
integer oc4_th;
integer oc5_th;
integer ic0_th;
integer ic1_th;
integer ic2_th;
 
reg [31:0] ints_r;
reg int_chk_en;
reg int_ctrl_en;
integer int_cnt;
 
integer n;
201,6 → 216,7
`endif
//wd_cnt = 0;
int_chk_en = 1;
int_ctrl_en = 0;
int_cnt = 0;
error_cnt = 0;
clk = 1;
238,7 → 254,7
 
// HERE IS WHERE THE TEST CASES GO ...
 
if(0) // Full Regression Run
if(1) // Full Regression Run
begin
$display(" ......................................................");
$display(" : :");
255,6 → 271,8
 
vsr1;
 
vsr_int;
 
end
else
if(1) // Debug Tests
264,16 → 282,18
$display(" : Test Debug Testing ... :");
$display(" :....................................................:");
 
basic1;
//basic1;
 
do_rst;
//do_rst;
 
basic2;
//basic2;
 
do_rst;
//do_rst;
 
vsr1;
//vsr1;
 
vsr_int;
 
repeat(100) @(posedge clk);
$finish;
end
598,6 → 618,7
//
 
always @(posedge clk)
begin
if(int & int_chk_en)
begin
while(wb_busy) @(posedge clk);
607,7 → 628,126
wb_busy = 0;
int_cnt = int_cnt + 1;
end
if(int & int_ctrl_en)
begin
 
while(wb_busy) @(posedge clk);
wb_busy = 1;
m0.wb_rd1(`INTS,4'hf, ints_r);
//$display("INFO: Got Interrupt (%0d). INTS: %h (%t)", int_cnt, ints_r, $time);
 
out_chan_int_handl(ints_r[04:02],0);
out_chan_int_handl(ints_r[07:05],1);
out_chan_int_handl(ints_r[10:08],2);
out_chan_int_handl(ints_r[13:11],3);
out_chan_int_handl(ints_r[16:14],4);
out_chan_int_handl(ints_r[19:17],5);
 
in_chan_int_handl(ints_r[22:20],0);
in_chan_int_handl(ints_r[25:23],1);
in_chan_int_handl(ints_r[28:26],2);
 
m0.wb_rd1(`INTS,4'hf, ints_r);
wb_busy = 0;
int_cnt = int_cnt + 1;
end
end
 
 
task out_chan_int_handl;
input [2:0] int_r;
input ch;
 
reg [2:0] int_r;
integer ch;
integer p;
 
begin
 
if(int_r[0]) // Output Channel at Thrash hold
begin
case(ch)
0: begin
for(p=0;p<oc0_th;p=p+1)
m0.wb_wr1(`OC0,4'hf, oc0_mem[oc0_ptr+p] );
oc0_ptr = oc0_ptr + oc0_th;
end
1: begin
for(p=0;p<oc1_th;p=p+1)
m0.wb_wr1(`OC1,4'hf, oc1_mem[oc1_ptr+p] );
oc1_ptr = oc1_ptr + oc1_th;
end
2: begin
for(p=0;p<oc2_th;p=p+1)
m0.wb_wr1(`OC2,4'hf, oc2_mem[oc2_ptr+p] );
oc2_ptr = oc2_ptr + oc2_th;
end
3: begin
for(p=0;p<oc3_th;p=p+1)
m0.wb_wr1(`OC3,4'hf, oc3_mem[oc3_ptr+p] );
oc3_ptr = oc3_ptr + oc3_th;
end
4: begin
for(p=0;p<oc4_th;p=p+1)
m0.wb_wr1(`OC4,4'hf, oc4_mem[oc4_ptr+p] );
oc4_ptr = oc4_ptr + oc4_th;
end
5: begin
for(p=0;p<oc5_th;p=p+1)
m0.wb_wr1(`OC5,4'hf, oc5_mem[oc5_ptr+p] );
oc5_ptr = oc5_ptr + oc5_th;
end
endcase
end
if(int_r[1]) // Output Channel FIFO Underrun
$display("ERROR: Output Channel %0d FIFO Underrun", ch);
 
if(int_r[2]) // Output Channel FIFO Overun
$display("ERROR: Output Channel %0d FIFO Ovverun", ch);
end
endtask
 
 
 
task in_chan_int_handl;
input [2:0] int_r;
input ch;
 
reg [2:0] int_r;
integer ch;
integer p;
 
begin
if(int_r[0]) // Input Channel at Thrash hold
begin
case(ch)
0: begin
for(p=0;p<ic0_th;p=p+1)
m0.wb_rd1(`IC0,4'hf, ic0_mem[ic0_ptr+p] );
ic0_ptr = ic0_ptr + ic0_th;
end
1: begin
for(p=0;p<ic1_th;p=p+1)
m0.wb_rd1(`IC1,4'hf, ic1_mem[ic1_ptr+p] );
ic1_ptr = ic1_ptr + ic1_th;
end
2: begin
for(p=0;p<ic2_th;p=p+1)
m0.wb_rd1(`IC2,4'hf, ic2_mem[ic2_ptr+p] );
ic2_ptr = ic2_ptr + ic2_th;
end
endcase
end
if(int_r[1]) // Input Channel FIFO Underrun
$display("ERROR: Input Channel %0d FIFO Underrun", ch);
 
if(int_r[2]) // Input Channel FIFO Overun
$display("ERROR: Input Channel %0d FIFO Ovverun", ch);
end
endtask
 
 
 
/////////////////////////////////////////////////////////////////////
//
// Simple DMA Engine
767,6 → 907,7
//
 
always #2.5 clk = ~clk;
//always #15 clk = ~clk;
 
always #40.69 bit_clk <= ~bit_clk;
 
/trunk/bench/verilog/tests.v
37,10 → 37,10
 
// CVS Log
//
// $Id: tests.v,v 1.1 2002-02-13 08:22:32 rudi Exp $
// $Id: tests.v,v 1.2 2002-03-05 04:44:04 rudi Exp $
//
// $Date: 2002-02-13 08:22:32 $
// $Revision: 1.1 $
// $Date: 2002-03-05 04:44:04 $
// $Revision: 1.2 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,8 → 47,12
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/02/13 08:22:32 rudi
//
// Added test bench for public release
//
//
//
//
 
 
127,7 → 131,8
for(n=0;n<75;n=n+1)
begin
@(negedge sync);
repeat(230) @(posedge bit_clk);
//repeat(230) @(posedge bit_clk);
repeat(130) @(posedge bit_clk);
 
repeat(n) @(posedge bit_clk);
 
410,7 → 415,8
for(n=0;n<75;n=n+1)
begin
@(negedge sync);
repeat(230) @(posedge bit_clk);
//repeat(230) @(posedge bit_clk);
repeat(130) @(posedge bit_clk);
 
repeat(n) @(posedge bit_clk);
 
649,11 → 655,14
$display("*****************************************************\n");
 
wb_busy = 1;
m0.wb_wr1(`INTM,4'hf, 32'h0492_4924);
 
m0.wb_wr1(`OCC0,4'hf, 32'h7373_7373);
m0.wb_wr1(`OCC1,4'hf, 32'h0000_7373);
m0.wb_wr1(`ICC,4'hf, 32'h0073_7373);
 
wb_busy = 0;
 
oc0_dma_en = 1;
oc1_dma_en = 1;
oc2_dma_en = 1;
873,3 → 882,371
endtask
 
 
 
task vsr_int;
 
reg [31:0] data;
reg [31:0] data1;
reg [31:0] data2;
integer size, frames, m, th, smpl;
 
begin
$display("\n\n");
$display("*****************************************************");
$display("*** VSR AC97 I/O Test (INT ctrl) ... ***");
$display("*****************************************************\n");
 
for(smpl=0;smpl<4;smpl=smpl+1)
begin
$display("Sampling selection: %0d",smpl);
for(th=0;th<4;th=th+1)
begin
do_rst;
 
while(wb_busy) @(posedge clk);
 
wb_busy = 1;
 
m0.wb_wr1(`INTM,4'hf, 32'hffff_fffc);
 
case(th)
0:
begin
$display("Interrupt thrash hold: 100%");
// Thrash holds
oc0_th = 4; // 100% (4/4) Full Empty
oc1_th = 4;
oc2_th = 4;
oc3_th = 4;
oc4_th = 4;
oc5_th = 4;
ic0_th = 4;
ic1_th = 4;
ic2_th = 4;
 
m0.wb_wr1(`OCC0,4'hf, 32'h3333_3333);
m0.wb_wr1(`OCC1,4'hf, 32'h0000_3333);
m0.wb_wr1(`ICC,4'hf, 32'h0033_3333);
end
 
1:
begin
$display("Interrupt thrash hold: 75%");
// Thrash holds
oc0_th = 3; // 75% (3/4) Full Empty
oc1_th = 3;
oc2_th = 3;
oc3_th = 3;
oc4_th = 3;
oc5_th = 3;
ic0_th = 3;
ic1_th = 3;
ic2_th = 3;
 
m0.wb_wr1(`OCC0,4'hf, 32'h2323_2323);
m0.wb_wr1(`OCC1,4'hf, 32'h0000_2323);
m0.wb_wr1(`ICC,4'hf, 32'h0023_2323);
end
 
2:
begin
$display("Interrupt thrash hold: 50%");
// Thrash holds
oc0_th = 2; // 50% (1/2) Full/Empty
oc1_th = 2;
oc2_th = 2;
oc3_th = 2;
oc4_th = 2;
oc5_th = 2;
ic0_th = 2;
ic1_th = 2;
ic2_th = 2;
 
m0.wb_wr1(`OCC0,4'hf, 32'h1313_1313);
m0.wb_wr1(`OCC1,4'hf, 32'h0000_1313);
m0.wb_wr1(`ICC,4'hf, 32'h0013_1313);
end
 
3:
begin
$display("Interrupt thrash hold: 25%");
// Thrash holds
oc0_th = 1; // 25% (1/4) Full/Empty
oc1_th = 1;
oc2_th = 1;
oc3_th = 1;
oc4_th = 1;
oc5_th = 1;
ic0_th = 1;
ic1_th = 1;
ic2_th = 1;
 
m0.wb_wr1(`OCC0,4'hf, 32'h0303_0303);
m0.wb_wr1(`OCC1,4'hf, 32'h0000_0303);
m0.wb_wr1(`ICC,4'hf, 32'h0003_0303);
end
 
endcase
 
wb_busy = 0;
 
oc0_dma_en = 0;
oc1_dma_en = 0;
oc2_dma_en = 0;
oc3_dma_en = 0;
oc4_dma_en = 0;
oc5_dma_en = 0;
ic0_dma_en = 0;
ic1_dma_en = 0;
ic2_dma_en = 0;
int_chk_en = 0;
int_ctrl_en = 1;
 
for(n=0;n<256;n=n+1)
begin
oc0_mem[n] = $random;
oc1_mem[n] = $random;
oc2_mem[n] = $random;
oc3_mem[n] = $random;
oc4_mem[n] = $random;
oc5_mem[n] = $random;
ic0_mem[n] = $random;
ic1_mem[n] = $random;
ic2_mem[n] = $random;
end
 
u1.init(0);
frames = 132;
frames = 132 + 132 + 132;
 
 
case(smpl)
0: // All FULL Speed (48 Khz per channel)
u1.tx1( frames, // Number of frames to process
0, // How many frames before codec is ready
10'b1101_1110_00, // Output slots valid bits
10'b1101_0000_00, // Input slots valid bits
20'b00_00_00_00_00_00_00_00_00_00, // Output Slots intervals
20'b00_00_00_00_00_00_00_00_00_00 // Input Slots intervals
);
1: // All 1/4 Speed (12 Khz per channel)
u1.tx1( frames, // Number of frames to process
0, // How many frames before codec is ready
10'b1101_1110_00, // Output slots valid bits
10'b1101_0000_00, // Input slots valid bits
20'b11_11_00_11_11_11_11_00_00_00, // Output Slots intervals
20'b11_11_00_11_00_00_00_00_00_00 // Input Slots intervals
);
2: // Mix 1
u1.tx1( frames, // Number of frames to process
0, // How many frames before codec is ready
10'b1101_1110_00, // Output slots valid bits
10'b1101_0000_00, // Input slots valid bits
20'b00_01_00_10_11_01_10_00_00_00, // Output Slots intervals
20'b11_10_00_01_00_00_00_00_00_00 // Input Slots intervals
);
3: // Mix 2
u1.tx1( frames, // Number of frames to process
0, // How many frames before codec is ready
10'b1101_1110_00, // Output slots valid bits
10'b1101_0000_00, // Input slots valid bits
20'b00_00_00_01_01_10_10_00_00_00, // Output Slots intervals
20'b00_00_00_10_00_00_00_00_00_00 // Input Slots intervals
);
endcase
 
 
size = (frames - 4)/2;
size = (frames - 4)/3;
size = size - 36;
 
repeat(100) @(posedge clk);
 
for(n=0;n<size;n=n+1)
begin
data1 = u1.rs3_mem[n];
data = oc0_mem[n[8:1]];
 
if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};
else data2 = {12'h0, data[31:16], 4'h0};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: Out. CH0 Sample %0d Mismatch Sent: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
end
 
 
for(n=0;n<size;n=n+1)
begin
data1 = u1.rs4_mem[n];
data = oc1_mem[n[8:1]];
 
if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};
else data2 = {12'h0, data[31:16], 4'h0};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: Out. CH1 Sample %0d Mismatch Sent: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
end
 
for(n=0;n<size;n=n+1)
begin
data1 = u1.rs6_mem[n];
data = oc2_mem[n[8:1]];
 
if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};
else data2 = {12'h0, data[31:16], 4'h0};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: Out. CH2 Sample %0d Mismatch Sent: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
end
 
for(n=0;n<size;n=n+1)
begin
data1 = u1.rs7_mem[n];
data = oc3_mem[n[8:1]];
 
if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};
else data2 = {12'h0, data[31:16], 4'h0};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: Out. CH3 Sample %0d Mismatch Sent: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
end
 
for(n=0;n<size;n=n+1)
begin
data1 = u1.rs8_mem[n];
data = oc4_mem[n[8:1]];
 
if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};
else data2 = {12'h0, data[31:16], 4'h0};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: Out. CH4 Sample %0d Mismatch Sent: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
end
 
for(n=0;n<size;n=n+1)
begin
data1 = u1.rs9_mem[n];
data = oc5_mem[n[8:1]];
 
if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};
else data2 = {12'h0, data[31:16], 4'h0};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: Out. CH5 Sample %0d Mismatch Sent: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
end
 
for(n=0;n<size;n=n+1)
begin
data1 = u1.is3_mem[n];
data = ic0_mem[n[8:1]];
 
if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};
else data2 = {12'h0, data[31:16], 4'h0};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: In. CH0 Sample %0d Mismatch Sent: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
end
 
for(n=0;n<size;n=n+1)
begin
data1 = u1.is4_mem[n];
data = ic1_mem[n[8:1]];
 
if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};
else data2 = {12'h0, data[31:16], 4'h0};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: In. CH1 Sample %0d Mismatch Sent: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
end
 
for(n=0;n<size;n=n+1)
begin
data1 = u1.is6_mem[n];
data = ic2_mem[n[8:1]];
 
if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};
else data2 = {12'h0, data[31:16], 4'h0};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: In. CH2 Sample %0d Mismatch Sent: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
end
 
repeat(10) @(posedge clk);
end
end
 
$display("Processed %0d samples per channel for each test",size);
 
show_errors;
$display("*****************************************************");
$display("*** Test DONE ... ***");
$display("*****************************************************\n\n");
 
end
endtask
 
 
 
/trunk/rtl/verilog/ac97_int.v
38,10 → 38,10
 
// CVS Log
//
// $Id: ac97_int.v,v 1.1 2001-08-03 06:54:50 rudi Exp $
// $Id: ac97_int.v,v 1.2 2002-03-05 04:44:05 rudi Exp $
//
// $Date: 2001-08-03 06:54:50 $
// $Revision: 1.1 $
// $Date: 2002-03-05 04:44:05 $
// $Revision: 1.2 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
48,6 → 48,11
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/08/03 06:54:50 rudi
//
//
// - Changed to new directory structure
//
// Revision 1.1.1.1 2001/05/19 02:29:18 rudi
// Initial Checkin
//
86,26 → 91,26
//
 
always @(posedge clk or negedge rst)
if(!rst) int_set[0] <= #1 0;
if(!rst) int_set[0] <= #1 1'b0;
else
case(cfg[5:4]) // synopsys parallel_case full_case
// 1/4 full/empty
0: int_set[0] <= #1 cfg[0] & (full_empty | (status == 2'd0));
2'h2: int_set[0] <= #1 cfg[0] & (full_empty | (status == 2'h0));
// 1/2 full/empty
1: int_set[0] <= #1 cfg[0] & (full_empty | (status[1] == 1'd0));
2'h1: int_set[0] <= #1 cfg[0] & (full_empty | (status[1] == 1'h0));
// 3/4 full/empty
2: int_set[0] <= #1 cfg[0] & (full_empty | (status < 2'd3));
3: int_set[0] <= #1 cfg[0] & full_empty;
2'h0: int_set[0] <= #1 cfg[0] & (full_empty | (status < 2'h3));
2'h3: int_set[0] <= #1 cfg[0] & full_empty;
endcase
 
always @(posedge clk or negedge rst)
if(!rst) int_set[1] <= #1 0;
if(!rst) int_set[1] <= #1 1'b0;
else
if(empty & re) int_set[1] <= #1 1;
if(empty & re) int_set[1] <= #1 1'b1;
 
always @(posedge clk or negedge rst)
if(!rst) int_set[2] <= #1 0;
if(!rst) int_set[2] <= #1 1'b0;
else
if(full & we) int_set[2] <= #1 1;
if(full & we) int_set[2] <= #1 1'b1;
 
endmodule
/trunk/rtl/verilog/ac97_top.v
37,10 → 37,10
 
// CVS Log
//
// $Id: ac97_top.v,v 1.2 2001-08-10 08:09:42 rudi Exp $
// $Id: ac97_top.v,v 1.3 2002-03-05 04:44:05 rudi Exp $
//
// $Date: 2001-08-10 08:09:42 $
// $Revision: 1.2 $
// $Date: 2002-03-05 04:44:05 $
// $Revision: 1.3 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 47,13
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.2 2001/08/10 08:09:42 rudi
//
// - Removed RTY_O output.
// - Added Clock and Reset Inputs to documentation.
// - Changed IO names to be more clear.
// - Uniquifyed define names to be core specific.
//
// Revision 1.1 2001/08/03 06:54:50 rudi
//
//
314,10 → 321,10
.empty( o6_empty )
);
`else
assign out_slt6 = 0;
assign o6_status = 0;
assign o6_full = 0;
assign o6_empty = 0;
assign out_slt6 = 20'h0;
assign o6_status = 2'h0;
assign o6_full = 1'b0;
assign o6_empty = 1'b0;
`endif
 
`ifdef AC97_SURROUND
349,14 → 356,14
.empty( o8_empty )
);
`else
assign out_slt7 = 0;
assign o7_status = 0;
assign o7_full = 0;
assign o7_empty = 0;
assign out_slt8 = 0;
assign o8_status = 0;
assign o8_full = 0;
assign o8_empty = 0;
assign out_slt7 = 20'h0;
assign o7_status = 2'h0;
assign o7_full = 1'b0;
assign o7_empty = 1'b0;
assign out_slt8 = 20'h0;
assign o8_status = 2'h0;
assign o8_full = 1'b0;
assign o8_empty = 1'b0;
`endif
 
`ifdef AC97_LFE
374,10 → 381,10
.empty( o9_empty )
);
`else
assign out_slt9 = 0;
assign o9_status = 0;
assign o9_full = 0;
assign o9_empty = 0;
assign out_slt9 = 20'h0;
assign o9_status = 2'h0;
assign o9_full = 1'b0;
assign o9_empty = 1'b0;
`endif
 
`ifdef AC97_SIN
409,14 → 416,14
.empty( i4_empty )
);
`else
assign i3_dout = 0;
assign i3_status = 0;
assign i3_full = 0;
assign i3_empty = 0;
assign i4_dout = 0;
assign i4_status = 0;
assign i4_full = 0;
assign i4_empty = 0;
assign i3_dout = 20'h0;
assign i3_status = 2'h0;
assign i3_full = 1'b0;
assign i3_empty = 1'b0;
assign i4_dout = 20'h0;
assign i4_status = 2'h0;
assign i4_full = 1'b0;
assign i4_empty = 1'b0;
`endif
 
`ifdef AC97_MICIN
434,10 → 441,10
.empty( i6_empty )
);
`else
assign i6_dout = 0;
assign i6_status = 0;
assign i6_full = 0;
assign i6_empty = 0;
assign i6_dout = 20'h0;
assign i6_status = 2'h0;
assign i6_full = 1'b0;
assign i6_empty = 1'b0;
`endif
 
ac97_wb_if u12(
633,7 → 640,7
.we( o6_we )
);
`else
assign oc2_int_set = 0;
assign oc2_int_set = 1'b0;
`endif
 
`ifdef AC97_SURROUND
663,8 → 670,8
.we( o8_we )
);
`else
assign oc3_int_set = 0;
assign oc4_int_set = 0;
assign oc3_int_set = 1'b0;
assign oc4_int_set = 1'b0;
`endif
 
`ifdef AC97_LFE
681,7 → 688,7
.we( o9_we )
);
`else
assign oc5_int_set = 0;
assign oc5_int_set = 1'b0;
`endif
 
`ifdef AC97_SIN
711,8 → 718,8
.we( i4_we )
);
`else
assign ic0_int_set = 0;
assign ic1_int_set = 0;
assign ic0_int_set = 1'b0;
assign ic1_int_set = 1'b0;
`endif
 
`ifdef AC97_MICIN
729,7 → 736,7
.we( i6_we )
);
`else
assign ic2_int_set = 0;
assign ic2_int_set = 1'b0;
`endif
 
ac97_rst u26(
/trunk/rtl/verilog/ac97_cra.v
38,10 → 38,10
 
// CVS Log
//
// $Id: ac97_cra.v,v 1.1 2001-08-03 06:54:49 rudi Exp $
// $Id: ac97_cra.v,v 1.2 2002-03-05 04:44:05 rudi Exp $
//
// $Date: 2001-08-03 06:54:49 $
// $Revision: 1.1 $
// $Date: 2002-03-05 04:44:05 $
// $Revision: 1.2 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
48,6 → 48,11
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/08/03 06:54:49 rudi
//
//
// - Changed to new directory structure
//
// Revision 1.1.1.1 2001/05/19 02:29:18 rudi
// Initial Checkin
//
130,41 → 135,41
crac_we_r <= #1 crac_we;
 
always @(posedge clk or negedge rst)
if(!rst) crac_wr <= #1 0;
if(!rst) crac_wr <= #1 1'b0;
else
if(crac_we_r & !crac_out[31]) crac_wr <= #1 1;
if(crac_we_r & !crac_out[31]) crac_wr <= #1 1'b1;
else
if(valid_ne) crac_wr <= #1 0;
if(valid_ne) crac_wr <= #1 1'b0;
 
assign crac_wr_done = crac_wr & valid_ne;
 
always @(posedge clk or negedge rst)
if(!rst) crac_rd <= #1 0;
if(!rst) crac_rd <= #1 1'b0;
else
if(crac_we_r & crac_out[31]) crac_rd <= #1 1;
if(crac_we_r & crac_out[31]) crac_rd <= #1 1'b1;
else
if(rdd1 & valid_pe) crac_rd <= #1 0;
if(rdd1 & valid_pe) crac_rd <= #1 1'b0;
 
always @(posedge clk or negedge rst)
if(!rst) rdd1 <= #1 0;
if(!rst) rdd1 <= #1 1'b0;
else
if(crac_rd & valid_ne) rdd1 <= #1 1;
if(crac_rd & valid_ne) rdd1 <= #1 1'b1;
else
if(!crac_rd) rdd1 <= #1 0;
if(!crac_rd) rdd1 <= #1 1'b0;
 
always @(posedge clk or negedge rst)
if(!rst) rdd2 <= #1 0;
if(!rst) rdd2 <= #1 1'b0;
else
if( (crac_rd & valid_ne) | (!rdd3 & rdd2) ) rdd2 <= #1 1;
if( (crac_rd & valid_ne) | (!rdd3 & rdd2) ) rdd2 <= #1 1'b1;
else
if(crac_rd_done) rdd2 <= #1 0;
if(crac_rd_done) rdd2 <= #1 1'b0;
 
always @(posedge clk or negedge rst)
if(!rst) rdd3 <= #1 0;
if(!rst) rdd3 <= #1 1'b0;
else
if(rdd2 & valid_pe) rdd3 <= #1 1;
if(rdd2 & valid_pe) rdd3 <= #1 1'b1;
else
if(crac_rd_done) rdd3 <= #1 0;
if(crac_rd_done) rdd3 <= #1 1'b0;
 
always @(posedge clk)
crac_rd_done <= #1 rdd3 & valid_pe;
/trunk/rtl/verilog/ac97_fifo_ctrl.v
38,10 → 38,10
 
// CVS Log
//
// $Id: ac97_fifo_ctrl.v,v 1.1 2001-08-03 06:54:49 rudi Exp $
// $Id: ac97_fifo_ctrl.v,v 1.2 2002-03-05 04:44:05 rudi Exp $
//
// $Date: 2001-08-03 06:54:49 $
// $Revision: 1.1 $
// $Date: 2002-03-05 04:44:05 $
// $Revision: 1.2 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
48,6 → 48,11
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/08/03 06:54:49 rudi
//
//
// - Changed to new directory structure
//
// Revision 1.1.1.1 2001/05/19 02:29:18 rudi
// Initial Checkin
//
89,10 → 94,10
 
always @(posedge clk)
if(valid & ch_en & !full_empty_r & crdy & (!srs | (srs & req) ) )
en_out_l <= #1 1;
en_out_l <= #1 1'b1;
else
if(!valid & !(ch_en & !full_empty_r & crdy & (!srs | (srs & req) )) )
en_out_l <= #1 0;
en_out_l <= #1 1'b0;
 
always @(posedge clk)
en_out_l2 <= #1 en_out_l & valid;
/trunk/rtl/verilog/ac97_rf.v
38,10 → 38,10
 
// CVS Log
//
// $Id: ac97_rf.v,v 1.2 2001-08-10 08:09:42 rudi Exp $
// $Id: ac97_rf.v,v 1.3 2002-03-05 04:44:05 rudi Exp $
//
// $Date: 2001-08-10 08:09:42 $
// $Revision: 1.2 $
// $Date: 2002-03-05 04:44:05 $
// $Revision: 1.3 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
48,6 → 48,13
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.2 2001/08/10 08:09:42 rudi
//
// - Removed RTY_O output.
// - Added Clock and Reset Inputs to documentation.
// - Changed IO names to be more clear.
// - Uniquifyed define names to be core specific.
//
// Revision 1.1 2001/08/03 06:54:50 rudi
//
//
166,37 → 173,37
endcase
 
always @(posedge clk or negedge rst)
if(!rst) csr_r <= #1 0;
if(!rst) csr_r <= #1 1'b0;
else
if(rf_we & (adr[2:0]==0)) csr_r <= #1 rf_din;
if(rf_we & (adr[2:0]==3'h0)) csr_r <= #1 rf_din;
 
always @(posedge clk)
if(rf_we & (adr[2:0]==0)) ac97_rst_force <= #1 rf_din[0];
else ac97_rst_force <= #1 0;
if(rf_we & (adr[2:0]==3'h0)) ac97_rst_force <= #1 rf_din[0];
else ac97_rst_force <= #1 1'b0;
 
always @(posedge clk)
if(rf_we & (adr[2:0]==0)) resume_req <= #1 rf_din[1];
else resume_req <= #1 0;
if(rf_we & (adr[2:0]==3'h0)) resume_req <= #1 rf_din[1];
else resume_req <= #1 1'b0;
 
always @(posedge clk or negedge rst)
if(!rst) occ0_r <= #1 0;
if(!rst) occ0_r <= #1 1'b0;
else
if(rf_we & (adr[2:0]==1)) occ0_r <= #1 rf_din;
if(rf_we & (adr[2:0]==3'h1)) occ0_r <= #1 rf_din;
 
always @(posedge clk or negedge rst)
if(!rst) occ1_r <= #1 0;
if(!rst) occ1_r <= #1 1'b0;
else
if(rf_we & (adr[2:0]==2)) occ1_r <= #1 rf_din[23:0];
if(rf_we & (adr[2:0]==3'h2)) occ1_r <= #1 rf_din[23:0];
 
always @(posedge clk or negedge rst)
if(!rst) icc_r <= #1 0;
if(!rst) icc_r <= #1 1'b0;
else
if(rf_we & (adr[2:0]==3)) icc_r <= #1 rf_din[23:0];
if(rf_we & (adr[2:0]==3'h3)) icc_r <= #1 rf_din[23:0];
 
assign crac_we = rf_we & (adr[2:0]==4);
assign crac_we = rf_we & (adr[2:0]==3'h4);
 
always @(posedge clk or negedge rst)
if(!rst) crac_r <= #1 0;
if(!rst) crac_r <= #1 1'b0;
else
if(crac_we) crac_r <= #1 {rf_din[31], rf_din[22:16]};
 
204,59 → 211,59
if(crac_we) crac_dout_r <= #1 rf_din[15:0];
 
always @(posedge clk or negedge rst)
if(!rst) intm_r <= #1 0;
if(!rst) intm_r <= #1 1'b0;
else
if(rf_we & (adr[2:0]==5)) intm_r <= #1 rf_din[28:0];
if(rf_we & (adr[2:0]==3'h5)) intm_r <= #1 rf_din[28:0];
 
// Interrupt Source Register
always @(posedge clk or negedge rst)
if(!rst) ints_r <= #1 0;
if(!rst) ints_r <= #1 1'b0;
else
if(rf_re & (adr[2:0]==6)) ints_r <= #1 0;
if(rf_re & (adr[2:0]==3'h6)) ints_r <= #1 1'b0;
else
begin
if(crac_rd_done) ints_r[0] <= #1 1;
if(crac_wr_done) ints_r[1] <= #1 1;
if(oc0_int_set[0]) ints_r[2] <= #1 1;
if(oc0_int_set[1]) ints_r[3] <= #1 1;
if(oc0_int_set[2]) ints_r[4] <= #1 1;
if(oc1_int_set[0]) ints_r[5] <= #1 1;
if(oc1_int_set[1]) ints_r[6] <= #1 1;
if(oc1_int_set[2]) ints_r[7] <= #1 1;
if(crac_rd_done) ints_r[0] <= #1 1'b1;
if(crac_wr_done) ints_r[1] <= #1 1'b1;
if(oc0_int_set[0]) ints_r[2] <= #1 1'b1;
if(oc0_int_set[1]) ints_r[3] <= #1 1'b1;
if(oc0_int_set[2]) ints_r[4] <= #1 1'b1;
if(oc1_int_set[0]) ints_r[5] <= #1 1'b1;
if(oc1_int_set[1]) ints_r[6] <= #1 1'b1;
if(oc1_int_set[2]) ints_r[7] <= #1 1'b1;
`ifdef AC97_CENTER
if(oc2_int_set[0]) ints_r[8] <= #1 1;
if(oc2_int_set[1]) ints_r[9] <= #1 1;
if(oc2_int_set[2]) ints_r[10] <= #1 1;
if(oc2_int_set[0]) ints_r[8] <= #1 1'b1;
if(oc2_int_set[1]) ints_r[9] <= #1 1'b1;
if(oc2_int_set[2]) ints_r[10] <= #1 1'b1;
`endif
 
`ifdef AC97_SURROUND
if(oc3_int_set[0]) ints_r[11] <= #1 1;
if(oc3_int_set[1]) ints_r[12] <= #1 1;
if(oc3_int_set[2]) ints_r[13] <= #1 1;
if(oc4_int_set[0]) ints_r[14] <= #1 1;
if(oc4_int_set[1]) ints_r[15] <= #1 1;
if(oc4_int_set[2]) ints_r[16] <= #1 1;
if(oc3_int_set[0]) ints_r[11] <= #1 1'b1;
if(oc3_int_set[1]) ints_r[12] <= #1 1'b1;
if(oc3_int_set[2]) ints_r[13] <= #1 1'b1;
if(oc4_int_set[0]) ints_r[14] <= #1 1'b1;
if(oc4_int_set[1]) ints_r[15] <= #1 1'b1;
if(oc4_int_set[2]) ints_r[16] <= #1 1'b1;
`endif
 
`ifdef AC97_LFE
if(oc5_int_set[0]) ints_r[17] <= #1 1;
if(oc5_int_set[1]) ints_r[18] <= #1 1;
if(oc5_int_set[2]) ints_r[19] <= #1 1;
if(oc5_int_set[0]) ints_r[17] <= #1 1'b1;
if(oc5_int_set[1]) ints_r[18] <= #1 1'b1;
if(oc5_int_set[2]) ints_r[19] <= #1 1'b1;
`endif
 
`ifdef AC97_SIN
if(ic0_int_set[0]) ints_r[20] <= #1 1;
if(ic0_int_set[1]) ints_r[21] <= #1 1;
if(ic0_int_set[2]) ints_r[22] <= #1 1;
if(ic1_int_set[0]) ints_r[23] <= #1 1;
if(ic1_int_set[1]) ints_r[24] <= #1 1;
if(ic1_int_set[2]) ints_r[25] <= #1 1;
if(ic0_int_set[0]) ints_r[20] <= #1 1'b1;
if(ic0_int_set[1]) ints_r[21] <= #1 1'b1;
if(ic0_int_set[2]) ints_r[22] <= #1 1'b1;
if(ic1_int_set[0]) ints_r[23] <= #1 1'b1;
if(ic1_int_set[1]) ints_r[24] <= #1 1'b1;
if(ic1_int_set[2]) ints_r[25] <= #1 1'b1;
`endif
 
`ifdef AC97_MICIN
if(ic2_int_set[0]) ints_r[26] <= #1 1;
if(ic2_int_set[1]) ints_r[27] <= #1 1;
if(ic2_int_set[2]) ints_r[28] <= #1 1;
if(ic2_int_set[0]) ints_r[26] <= #1 1'b1;
if(ic2_int_set[1]) ints_r[27] <= #1 1'b1;
if(ic2_int_set[2]) ints_r[28] <= #1 1'b1;
`endif
end
 
/trunk/rtl/verilog/ac97_dma_req.v
38,10 → 38,10
 
// CVS Log
//
// $Id: ac97_dma_req.v,v 1.1 2001-08-03 06:54:49 rudi Exp $
// $Id: ac97_dma_req.v,v 1.2 2002-03-05 04:44:05 rudi Exp $
//
// $Date: 2001-08-03 06:54:49 $
// $Revision: 1.1 $
// $Date: 2002-03-05 04:44:05 $
// $Revision: 1.2 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
48,6 → 48,11
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/08/03 06:54:49 rudi
//
//
// - Changed to new directory structure
//
// Revision 1.1.1.1 2001/05/19 02:29:16 rudi
// Initial Checkin
//
82,12 → 87,12
case(cfg[5:4]) // synopsys parallel_case full_case
// REQ = Ch_EN & DMA_EN & Status
// 1/4 full/empty
0: dma_req_d = cfg[0] & cfg[6] & (full_empty | (status == 2'd0));
2'h2: dma_req_d = cfg[0] & cfg[6] & (full_empty | (status == 2'h0));
// 1/2 full/empty
1: dma_req_d = cfg[0] & cfg[6] & (full_empty | (status[1] == 1'd0));
2'h1: dma_req_d = cfg[0] & cfg[6] & (full_empty | (status[1] == 1'h0));
// 3/4 full/empty
2: dma_req_d = cfg[0] & cfg[6] & (full_empty | (status < 2'd3));
3: dma_req_d = cfg[0] & cfg[6] & full_empty;
2'h0: dma_req_d = cfg[0] & cfg[6] & (full_empty | (status < 2'h3));
2'h3: dma_req_d = cfg[0] & cfg[6] & full_empty;
endcase
 
always @(posedge clk)
94,11 → 99,11
dma_req_r1 <= #1 dma_req_d & !dma_ack;
 
always @(posedge clk or negedge rst)
if(!rst) dma_req <= #1 0;
if(!rst) dma_req <= #1 1'b0;
else
if(dma_req_r1 & dma_req_d & !dma_ack) dma_req <= #1 1;
if(dma_req_r1 & dma_req_d & !dma_ack) dma_req <= #1 1'b1;
else
if(dma_ack) dma_req <= #1 0;
if(dma_ack) dma_req <= #1 1'b0;
 
endmodule
 
/trunk/rtl/verilog/ac97_in_fifo.v
38,10 → 38,10
 
// CVS Log
//
// $Id: ac97_in_fifo.v,v 1.1 2001-08-03 06:54:50 rudi Exp $
// $Id: ac97_in_fifo.v,v 1.2 2002-03-05 04:44:05 rudi Exp $
//
// $Date: 2001-08-03 06:54:50 $
// $Revision: 1.1 $
// $Date: 2002-03-05 04:44:05 $
// $Revision: 1.2 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
48,6 → 48,11
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/08/03 06:54:50 rudi
//
//
// - Changed to new directory structure
//
// Revision 1.1.1.1 2001/05/19 02:29:14 rudi
// Initial Checkin
//
98,19 → 103,19
assign m16b = (mode == 2'h0); // 16 Bit Mode
 
always @(posedge clk)
if(!en) wp <= #1 0;
if(!en) wp <= #1 4'h0;
else
if(we) wp <= #1 wp_p1;
 
assign wp_p1 = m16b ? (wp + 1) : (wp + 2);
assign wp_p1 = m16b ? (wp + 4'h1) : (wp + 4'h2);
 
always @(posedge clk)
if(!en) rp <= #1 0;
if(!en) rp <= #1 3'h0;
else
if(re) rp <= #1 rp + 1;
if(re) rp <= #1 rp + 3'h1;
 
always @(posedge clk)
status <= #1 ((rp - wp[2:1]) - 1);
status <= #1 ((rp - wp[2:1]) - 2'h1);
 
always @(posedge clk)
empty <= #1 (wp[3:1] == rp[2:0]) & (m16b ? !wp[0] : 1'b0);
/trunk/rtl/verilog/ac97_out_fifo.v
38,10 → 38,10
 
// CVS Log
//
// $Id: ac97_out_fifo.v,v 1.1 2001-08-03 06:54:50 rudi Exp $
// $Id: ac97_out_fifo.v,v 1.2 2002-03-05 04:44:05 rudi Exp $
//
// $Date: 2001-08-03 06:54:50 $
// $Revision: 1.1 $
// $Date: 2002-03-05 04:44:05 $
// $Revision: 1.2 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
48,6 → 48,11
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/08/03 06:54:50 rudi
//
//
// - Changed to new directory structure
//
// Revision 1.1.1.1 2001/05/19 02:29:16 rudi
// Initial Checkin
//
98,23 → 103,23
assign m16b = (mode == 2'h0); // 16 Bit Mode
 
always @(posedge clk)
if(!en) wp <= #1 0;
if(!en) wp <= #1 3'h0;
else
if(we) wp <= #1 wp_p1;
 
assign wp_p1 = wp + 1;
assign wp_p1 = wp + 3'h1;
 
always @(posedge clk)
if(!en) rp <= #1 0;
if(!en) rp <= #1 4'h0;
else
if(re & m16b) rp <= #1 rp + 1;
if(re & m16b) rp <= #1 rp + 4'h1;
else
if(re & !m16b) rp <= #1 rp + 2;
if(re & !m16b) rp <= #1 rp + 4'h2;
 
always @(posedge clk)
status <= #1 (wp[1:0] - rp[2:1]) - 1;
status <= #1 (wp[1:0] - rp[2:1]) - 2'h1;
 
wire [3:0] rp_p1 = rp[3:0] + 1;
wire [3:0] rp_p1 = rp[3:0] + 4'h1;
 
always @(posedge clk)
empty <= #1 (rp_p1[3:1] == wp[2:0]) & (m16b ? rp_p1[0] : 1'b1);
137,8 → 142,8
2: dout <= #1 dout_tmp[19:0]; // 20 Bit Output
endcase
 
 
always @(posedge clk)
if(we) mem[wp[1:0]] <= #1 din;
 
endmodule
 
/trunk/rtl/verilog/ac97_defines.v
37,10 → 37,10
 
// CVS Log
//
// $Id: ac97_defines.v,v 1.2 2001-08-10 08:09:42 rudi Exp $
// $Id: ac97_defines.v,v 1.3 2002-03-05 04:44:05 rudi Exp $
//
// $Date: 2001-08-10 08:09:42 $
// $Revision: 1.2 $
// $Date: 2002-03-05 04:44:05 $
// $Revision: 1.3 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
47,6 → 47,13
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.2 2001/08/10 08:09:42 rudi
//
// - Removed RTY_O output.
// - Added Clock and Reset Inputs to documentation.
// - Changed IO names to be more clear.
// - Uniquifyed define names to be core specific.
//
// Revision 1.1 2001/08/03 06:54:49 rudi
//
//
68,7 → 75,7
// are always supported.
 
// Surround Left + Right
`define AC97_SURROUND 1
`define AC97_SURROUND 1
 
// Center Channel
`define AC97_CENTER 1
96,7 → 103,7
// The value here should one less than the actually calculated
// value.
// For a 200 MHz wishbone clock, this value is 49 (50-1).
`define AC97_250_PS 6'd49
`define AC97_250_PS 6'h31
 
/////////////////////////////////////////////////////////////////////
//
105,7 → 112,7
// The reset timer is driven by the AC97_250_PS prescaler.
// This value should probably be never changed. Adjust the
// AC97_250_PS instead.
`define AC97_RST_DEL 3'd4
`define AC97_RST_DEL 3'h4
 
/////////////////////////////////////////////////////////////////////
//
116,7 → 123,7
// the current state of the prescaler, and must somehow insure we
// meet the minimum 1uS length. This value should probably be never
// changed. Modify the AC97_250_PS instead.
`define AC97_RES_SIG 3'd5
`define AC97_RES_SIG 3'h5
 
/////////////////////////////////////////////////////////////////////
//
125,5 → 132,5
// This value defines how many WISHBONE cycles must pass without
// any change on the bit clock input before we signal "suspended".
// For a 200 MHz WISHBONE clock this would be about (163/5) 33 cycles.
`define AC97_SUSP_DET 6'd33
`define AC97_SUSP_DET 6'h21
 
/trunk/rtl/verilog/ac97_dma_if.v
38,10 → 38,10
 
// CVS Log
//
// $Id: ac97_dma_if.v,v 1.2 2001-08-10 08:09:42 rudi Exp $
// $Id: ac97_dma_if.v,v 1.3 2002-03-05 04:44:05 rudi Exp $
//
// $Date: 2001-08-10 08:09:42 $
// $Revision: 1.2 $
// $Date: 2002-03-05 04:44:05 $
// $Revision: 1.3 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
48,6 → 48,13
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.2 2001/08/10 08:09:42 rudi
//
// - Removed RTY_O output.
// - Added Clock and Reset Inputs to documentation.
// - Changed IO names to be more clear.
// - Uniquifyed define names to be core specific.
//
// Revision 1.1 2001/08/03 06:54:49 rudi
//
//
123,7 → 130,7
.dma_ack( dma_ack[2] )
);
`else
assign dma_req[2] = 0;
assign dma_req[2] = 1'b0;
`endif
 
`ifdef AC97_SURROUND
145,8 → 152,8
.dma_ack( dma_ack[4] )
);
`else
assign dma_req[3] = 0;
assign dma_req[4] = 0;
assign dma_req[3] = 1'b0;
assign dma_req[4] = 1'b0;
`endif
 
`ifdef AC97_LFE
159,7 → 166,7
.dma_ack( dma_ack[5] )
);
`else
assign dma_req[5] = 0;
assign dma_req[5] = 1'b0;
`endif
 
`ifdef AC97_SIN
181,8 → 188,8
.dma_ack( dma_ack[7] )
);
`else
assign dma_req[6] = 0;
assign dma_req[7] = 0;
assign dma_req[6] = 1'b0;
assign dma_req[7] = 1'b0;
`endif
 
`ifdef AC97_MICIN
195,7 → 202,7
.dma_ack( dma_ack[8] )
);
`else
assign dma_req[8] = 0;
assign dma_req[8] = 1'b0;
`endif
 
endmodule
/trunk/rtl/verilog/ac97_prc.v
38,10 → 38,10
 
// CVS Log
//
// $Id: ac97_prc.v,v 1.2 2001-08-10 08:09:42 rudi Exp $
// $Id: ac97_prc.v,v 1.3 2002-03-05 04:44:05 rudi Exp $
//
// $Date: 2001-08-10 08:09:42 $
// $Revision: 1.2 $
// $Date: 2002-03-05 04:44:05 $
// $Revision: 1.3 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
48,6 → 48,13
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.2 2001/08/10 08:09:42 rudi
//
// - Removed RTY_O output.
// - Added Clock and Reset Inputs to documentation.
// - Changed IO names to be more clear.
// - Uniquifyed define names to be core specific.
//
// Revision 1.1 2001/08/03 06:54:50 rudi
//
//
153,7 → 160,7
 
assign out_slt0[12] = o3_re_l;
assign out_slt0[11] = o4_re_l;
assign out_slt0[10] = 0;
assign out_slt0[10] = 1'b0;
assign out_slt0[09] = o6_re_l;
assign out_slt0[08] = o7_re_l;
assign out_slt0[07] = o8_re_l;
211,8 → 218,8
.en_out_l( o6_re_l )
);
`else
assign o6_re = 0;
assign o6_re_l = 0;
assign o6_re = 1'b0;
assign o6_re_l = 1'b0;
`endif
 
`ifdef AC97_SURROUND
242,10 → 249,10
.en_out_l( o8_re_l )
);
`else
assign o7_re = 0;
assign o7_re_l = 0;
assign o8_re = 0;
assign o8_re_l = 0;
assign o7_re = 1'b0;
assign o7_re_l = 1'b0;
assign o8_re = 1'b0;
assign o8_re_l = 1'b0;
`endif
 
`ifdef AC97_LFE
262,8 → 269,8
.en_out_l( o9_re_l )
);
`else
assign o9_re = 0;
assign o9_re_l = 0;
assign o9_re = 1'b0;
assign o9_re_l = 1'b0;
`endif
 
`ifdef AC97_SIN
293,8 → 300,8
.en_out_l( )
);
`else
assign i3_we = 0;
assign i4_we = 0;
assign i3_we = 1'b0;
assign i4_we = 1'b0;
`endif
 
`ifdef AC97_MICIN
311,7 → 318,7
.en_out_l( )
);
`else
assign i6_we = 0;
assign i6_we = 1'b0;
`endif
 
endmodule
/trunk/rtl/verilog/ac97_soc.v
38,10 → 38,10
 
// CVS Log
//
// $Id: ac97_soc.v,v 1.1 2001-08-03 06:54:50 rudi Exp $
// $Id: ac97_soc.v,v 1.2 2002-03-05 04:44:05 rudi Exp $
//
// $Date: 2001-08-03 06:54:50 $
// $Revision: 1.1 $
// $Date: 2002-03-05 04:44:05 $
// $Revision: 1.2 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
48,6 → 48,11
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/08/03 06:54:50 rudi
//
//
// - Changed to new directory structure
//
// Revision 1.1.1.1 2001/05/19 02:29:15 rudi
// Initial Checkin
//
103,43 → 108,43
if(!rst) cnt <= #1 8'hff;
else
if(suspended) cnt <= #1 8'hff;
else cnt <= #1 cnt + 1;
else cnt <= #1 cnt + 8'h1;
 
always @(posedge clk)
ld <= #1 (cnt == 8'h00);
 
always @(posedge clk)
sync_beat <= #1 (cnt == 8'h00) | ((cnt > 0) & (cnt < 16));
sync_beat <= #1 (cnt == 8'h00) | ((cnt > 8'h00) & (cnt < 8'h10));
 
always @(posedge clk)
valid <= #1 (cnt > 57);
valid <= #1 (cnt > 8'h39);
 
always @(posedge clk)
out_le[0] <= #1 (cnt == 8'd17); // Slot 0 Latch Enable
out_le[0] <= #1 (cnt == 8'h11); // Slot 0 Latch Enable
 
always @(posedge clk)
out_le[1] <= #1 (cnt == 8'd37); // Slot 1 Latch Enable
out_le[1] <= #1 (cnt == 8'h25); // Slot 1 Latch Enable
 
always @(posedge clk)
out_le[2] <= #1 (cnt == 8'd57); // Slot 2 Latch Enable
out_le[2] <= #1 (cnt == 8'h39); // Slot 2 Latch Enable
 
always @(posedge clk)
out_le[3] <= #1 (cnt == 8'd77); // Slot 3 Latch Enable
out_le[3] <= #1 (cnt == 8'h4d); // Slot 3 Latch Enable
 
always @(posedge clk)
out_le[4] <= #1 (cnt == 8'd97); // Slot 4 Latch Enable
out_le[4] <= #1 (cnt == 8'h61); // Slot 4 Latch Enable
 
always @(posedge clk)
out_le[5] <= #1 (cnt == 8'd137); // Slot 6 Latch Enable
out_le[5] <= #1 (cnt == 8'h89); // Slot 6 Latch Enable
 
always @(posedge clk)
in_valid[0] <= #1 (cnt > 8'd77); // Input Slot 3 Valid
in_valid[0] <= #1 (cnt > 8'h4d); // Input Slot 3 Valid
 
always @(posedge clk)
in_valid[1] <= #1 (cnt > 8'd97); // Input Slot 3 Valid
in_valid[1] <= #1 (cnt > 8'h61); // Input Slot 3 Valid
 
always @(posedge clk)
in_valid[2] <= #1 (cnt > 8'd137); // Input Slot 3 Valid
in_valid[2] <= #1 (cnt > 8'h89); // Input Slot 3 Valid
 
////////////////////////////////////////////////////////////////////
//
158,11 → 163,11
assign to = (to_cnt == `AC97_SUSP_DET);
 
always @(posedge wclk or negedge rst)
if(!rst) to_cnt <= #1 0;
if(!rst) to_cnt <= #1 6'h0;
else
if(bit_clk_e) to_cnt <= #1 0;
if(bit_clk_e) to_cnt <= #1 6'h0;
else
if(!to) to_cnt <= #1 to_cnt + 1;
if(!to) to_cnt <= #1 to_cnt + 6'h1;
 
////////////////////////////////////////////////////////////////////
//
170,17 → 175,17
//
 
always @(posedge wclk or negedge rst)
if(!rst) sync_resume <= #1 0;
if(!rst) sync_resume <= #1 1'b0;
else
if(resume_done) sync_resume <= #1 0;
if(resume_done) sync_resume <= #1 1'b0;
else
if(suspended & resume) sync_resume <= #1 1;
if(suspended & resume) sync_resume <= #1 1'b1;
 
assign resume_done = (res_cnt == `AC97_RES_SIG);
 
always @(posedge wclk)
if(!sync_resume) res_cnt <= #1 0;
if(!sync_resume) res_cnt <= #1 4'h0;
else
if(ps_ce) res_cnt <= #1 res_cnt + 1;
if(ps_ce) res_cnt <= #1 res_cnt + 4'h1;
 
endmodule
/trunk/rtl/verilog/ac97_wb_if.v
38,10 → 38,10
 
// CVS Log
//
// $Id: ac97_wb_if.v,v 1.2 2001-08-10 08:09:42 rudi Exp $
// $Id: ac97_wb_if.v,v 1.3 2002-03-05 04:44:05 rudi Exp $
//
// $Date: 2001-08-10 08:09:42 $
// $Revision: 1.2 $
// $Date: 2002-03-05 04:44:05 $
// $Revision: 1.3 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
48,6 → 48,13
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.2 2001/08/10 08:09:42 rudi
//
// - Removed RTY_O output.
// - Added Clock and Reset Inputs to documentation.
// - Changed IO names to be more clear.
// - Uniquifyed define names to be core specific.
//
// Revision 1.1 2001/08/03 06:54:50 rudi
//
//
120,7 → 127,7
 
assign adr = wb_addr_i[5:2];
 
assign wb_err_o = 0;
assign wb_err_o = 1'b0;
 
always @(posedge clk)
dout <= #1 wb_data_i;
127,9 → 134,9
 
always @(posedge clk)
case(wb_addr_i[6:2]) // synopsys parallel_case full_case
14: wb_data_o <= #1 i3_din;
15: wb_data_o <= #1 i4_din;
16: wb_data_o <= #1 i6_din;
5'he: wb_data_o <= #1 i3_din;
5'hf: wb_data_o <= #1 i4_din;
5'h10: wb_data_o <= #1 i6_din;
default: wb_data_o <= #1 rf_din;
endcase
 
141,7 → 148,7
 
assign re = re1 & !re2 & wb_cyc_i & wb_stb_i & !wb_we_i;
 
assign rf_re = re & (wb_addr_i[6:2] < 8);
assign rf_re = re & (wb_addr_i[6:2] < 5'h8);
 
always @(posedge clk)
we1 <= #1 !we & wb_cyc_i & wb_stb_i & wb_we_i & `AC97_REG_SEL;
155,33 → 162,33
wb_ack_o <= #1 (re | we) & wb_cyc_i & wb_stb_i & ~wb_ack_o;
 
always @(posedge clk)
rf_we <= #1 we & (wb_addr_i[6:2] < 8);
rf_we <= #1 we & (wb_addr_i[6:2] < 5'h8);
 
always @(posedge clk)
o3_we <= #1 we & (wb_addr_i[6:2] == 8);
o3_we <= #1 we & (wb_addr_i[6:2] == 5'h8);
 
always @(posedge clk)
o4_we <= #1 we & (wb_addr_i[6:2] == 9);
o4_we <= #1 we & (wb_addr_i[6:2] == 5'h9);
 
always @(posedge clk)
o6_we <= #1 we & (wb_addr_i[6:2] == 10);
o6_we <= #1 we & (wb_addr_i[6:2] == 5'ha);
 
always @(posedge clk)
o7_we <= #1 we & (wb_addr_i[6:2] == 11);
o7_we <= #1 we & (wb_addr_i[6:2] == 5'hb);
 
always @(posedge clk)
o8_we <= #1 we & (wb_addr_i[6:2] == 12);
o8_we <= #1 we & (wb_addr_i[6:2] == 5'hc);
 
always @(posedge clk)
o9_we <= #1 we & (wb_addr_i[6:2] == 13);
o9_we <= #1 we & (wb_addr_i[6:2] == 5'hd);
 
always @(posedge clk)
i3_re <= #1 re & (wb_addr_i[6:2] == 14);
i3_re <= #1 re & (wb_addr_i[6:2] == 5'he);
 
always @(posedge clk)
i4_re <= #1 re & (wb_addr_i[6:2] == 15);
i4_re <= #1 re & (wb_addr_i[6:2] == 5'hf);
 
always @(posedge clk)
i6_re <= #1 re & (wb_addr_i[6:2] == 16);
i6_re <= #1 re & (wb_addr_i[6:2] == 5'h10);
 
endmodule
/trunk/sim/rtl_sim/run/Makefile
44,9 → 44,11
#
##########################################################################
 
INCDIR="-INCDIR ./$(DUT_SRC_DIR)/ -INCDIR ./$(TB_SRC_DIR)/"
LOGF=-LOGFILE .nclog
NCCOMMON=-CDSLIB ncwork/cds.lib -HDLVAR ncwork/hdl.var -NOCOPYRIGHT
INCDIR=+incdir+./$(DUT_SRC_DIR)/ +incdir+./$(TB_SRC_DIR)/
LOGF=-l .nclog
#NCCOMMON=-CDSLIB ncwork/cds.lib -HDLVAR ncwork/hdl.var -NOCOPYRIGHT
UMC_LIB=/tools/dc_libraries/virtual_silicon/umc_lib.v
GATE_NETLIST = ../../../syn/out/mc_top_ps.v
 
##########################################################################
#
53,32 → 55,21
# Make Targets
#
##########################################################################
simw:
@$(MAKE) -s sim ACCESS="-ACCESS +r " WAVES="-DEFINE WAVES"
 
ss:
signalscan -do waves/waves.do -waves waves/waves.trn &
 
simw:
@$(MAKE) -s sim ACCESS="+access+r " WAVES="+define+WAVES"
 
simxl:
verilog +incdir+$(DUT_SRC_DIR) +incdir+$(TB_SRC_DIR) \
$(_TARGETS_) $(_TB_)
 
sim:
@echo ""
@echo "----- Running NCVLOG ... ----------"
@$(MAKE) $(MS) vlog \
TARGETS="$(_TARGETS_)" \
TB="$(_TB_)" \
INCDIR=$(INCDIR) \
WAVES="$(WAVES)"
@echo ""
@echo "----- Running NCELAB ... ----------"
@$(MAKE) $(MS) elab \
ACCESS="$(ACCESS)" TOP=$(_TOP_)
@echo ""
@echo "----- Running NCSIM ... ----------"
@$(MAKE) $(MS) ncsim TOP=$(_TOP_)
@echo ""
ncverilog -q +define+RUDIS_TB $(_TARGETS_) $(_TB_) \
$(INCDIR) $(WAVES) $(ACCESS) $(LOGF) +ncstatus \
+ncuid+`hostname`
 
hal:
@echo ""
91,43 → 82,8
clean:
rm -rf ./waves/*.dsn ./waves/*.trn \
ncwork/.inc* ncwork/inc* \
./verilog.* .nclog hal.log
./verilog.* .nclog hal.log \
INCA_libs/
 
##########################################################################
#
# NCVLOG
#
##########################################################################
 
vhdl:
ncvhdl $(NCCOMMON) $(LOGF) -APPEND_LOG \
-WORK count -V93 hdl/counter.vhd
ncvhdl $(NCCOMMON) $(LOGF) -APPEND_LOG \
-WORK work -V93 $(TARGETS)
 
vlog:
ncvlog $(NCCOMMON) $(LOGF) \
-WORK work $(WAVES) $(TB) $(TARGETS) $(INCDIR)
 
##########################################################################
#
# NCELAB
#
##########################################################################
 
elab:
ncelab $(NCCOMMON) $(LOGF) -APPEND_LOG \
-WORK work $(ACCESS) -NOTIMINGCHECKS \
work.$(TOP)
 
##########################################################################
#
# NCSIM
#
##########################################################################
 
ncsim:
ncsim $(NCCOMMON) $(LOGF) -APPEND_LOG \
-EXIT -ERRORMAX 10 work.$(TOP)
 
 
/trunk/sim/rtl_sim/bin/Makefile
44,9 → 44,11
#
##########################################################################
 
INCDIR="-INCDIR ./$(DUT_SRC_DIR)/ -INCDIR ./$(TB_SRC_DIR)/"
LOGF=-LOGFILE .nclog
NCCOMMON=-CDSLIB ncwork/cds.lib -HDLVAR ncwork/hdl.var -NOCOPYRIGHT
INCDIR=+incdir+./$(DUT_SRC_DIR)/ +incdir+./$(TB_SRC_DIR)/
LOGF=-l .nclog
#NCCOMMON=-CDSLIB ncwork/cds.lib -HDLVAR ncwork/hdl.var -NOCOPYRIGHT
UMC_LIB=/tools/dc_libraries/virtual_silicon/umc_lib.v
GATE_NETLIST = ../../../syn/out/mc_top_ps.v
 
##########################################################################
#
53,32 → 55,21
# Make Targets
#
##########################################################################
simw:
@$(MAKE) -s sim ACCESS="-ACCESS +r " WAVES="-DEFINE WAVES"
 
ss:
signalscan -do waves/waves.do -waves waves/waves.trn &
 
simw:
@$(MAKE) -s sim ACCESS="+access+r " WAVES="+define+WAVES"
 
simxl:
verilog +incdir+$(DUT_SRC_DIR) +incdir+$(TB_SRC_DIR) \
$(_TARGETS_) $(_TB_)
 
sim:
@echo ""
@echo "----- Running NCVLOG ... ----------"
@$(MAKE) $(MS) vlog \
TARGETS="$(_TARGETS_)" \
TB="$(_TB_)" \
INCDIR=$(INCDIR) \
WAVES="$(WAVES)"
@echo ""
@echo "----- Running NCELAB ... ----------"
@$(MAKE) $(MS) elab \
ACCESS="$(ACCESS)" TOP=$(_TOP_)
@echo ""
@echo "----- Running NCSIM ... ----------"
@$(MAKE) $(MS) ncsim TOP=$(_TOP_)
@echo ""
ncverilog -q +define+RUDIS_TB $(_TARGETS_) $(_TB_) \
$(INCDIR) $(WAVES) $(ACCESS) $(LOGF) +ncstatus \
+ncuid+`hostname`
 
hal:
@echo ""
91,43 → 82,8
clean:
rm -rf ./waves/*.dsn ./waves/*.trn \
ncwork/.inc* ncwork/inc* \
./verilog.* .nclog hal.log
./verilog.* .nclog hal.log \
INCA_libs/
 
##########################################################################
#
# NCVLOG
#
##########################################################################
 
vhdl:
ncvhdl $(NCCOMMON) $(LOGF) -APPEND_LOG \
-WORK count -V93 hdl/counter.vhd
ncvhdl $(NCCOMMON) $(LOGF) -APPEND_LOG \
-WORK work -V93 $(TARGETS)
 
vlog:
ncvlog $(NCCOMMON) $(LOGF) \
-WORK work $(WAVES) $(TB) $(TARGETS) $(INCDIR)
 
##########################################################################
#
# NCELAB
#
##########################################################################
 
elab:
ncelab $(NCCOMMON) $(LOGF) -APPEND_LOG \
-WORK work $(ACCESS) -NOTIMINGCHECKS \
work.$(TOP)
 
##########################################################################
#
# NCSIM
#
##########################################################################
 
ncsim:
ncsim $(NCCOMMON) $(LOGF) -APPEND_LOG \
-EXIT -ERRORMAX 10 work.$(TOP)
 
 

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