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/aes_pipe/trunk/syn/Xilinx/log/aes.twr
0,0 → 1,760
--------------------------------------------------------------------------------
Release 11.1 Trace (lin)
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
 
/opt/Xilinx/11.1/ISE/bin/lin/unwrapped/trce -v 10 -fastpaths -xml
../log/aes.twx ../out/aes.map.ncd -o ../log/aes.twr ../out/aes.pcf
 
Design file: aes.map.ncd
Physical constraint file: aes.pcf
Device,package,speed: xc5vlx50t,ff1136,-1 (PRODUCTION 1.64 2009-03-03, STEPPING level 0)
Report level: verbose report, limited to 10 items per constraint
 
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
 
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
 
================================================================================
Timing constraint: TS_clk = PERIOD TIMEGRP "clk_i" 3 ns HIGH 50%;
 
59472 paths analyzed, 27896 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
Minimum period is 2.974ns.
--------------------------------------------------------------------------------
Slack (setup path): 0.026ns (requirement - (data path - clock path skew + uncertainty))
Source: proc[0].mix/outrkey<2>_1_5 (FF)
Destination: proc[1].add/dataout<2>_1_5 (FF)
Requirement: 3.000ns
Data Path Delay: 2.793ns (Levels of Logic = 1)
Clock Path Skew: -0.146ns (1.244 - 1.390)
Source Clock: clk_i_BUFGP rising at 0.000ns
Destination Clock: clk_i_BUFGP rising at 3.000ns
Clock Uncertainty: 0.035ns
 
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
 
Maximum Data Path: proc[0].mix/outrkey<2>_1_5 to proc[1].add/dataout<2>_1_5
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X20Y103.BQ Tcko 0.471 proc[0].mix/outrkey<2>_1_7
proc[0].mix/outrkey<2>_1_5
SLICE_X47Y110.B6 net (fanout=4) 2.295 proc[0].mix/outrkey<2>_1_5
SLICE_X47Y110.CLK Tas 0.027 proc[1].add/dataout<2>_1_7
proc[1].add/Mxor_added<2><1>_Result<5>1
proc[1].add/dataout<2>_1_5
------------------------------------------------- ---------------------------
Total 2.793ns (0.498ns logic, 2.295ns route)
(17.8% logic, 82.2% route)
 
--------------------------------------------------------------------------------
Slack (setup path): 0.026ns (requirement - (data path - clock path skew + uncertainty))
Source: add_f_1/dataout<1>_1_1 (FF)
Destination: sbox_f_1/g0[1].g1[1].sub/byteout_5 (FF)
Requirement: 3.000ns
Data Path Delay: 2.850ns (Levels of Logic = 2)
Clock Path Skew: -0.089ns (1.226 - 1.315)
Source Clock: clk_i_BUFGP rising at 0.000ns
Destination Clock: clk_i_BUFGP rising at 3.000ns
Clock Uncertainty: 0.035ns
 
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
 
Maximum Data Path: add_f_1/dataout<1>_1_1 to sbox_f_1/g0[1].g1[1].sub/byteout_5
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X52Y59.BQ Tcko 0.471 add_f_1/dataout<1>_1_3
add_f_1/dataout<1>_1_1
SLICE_X59Y62.C1 net (fanout=32) 1.538 add_f_1/dataout<1>_1_1
SLICE_X59Y62.C Tilo 0.094 sbox_f_1/g0[2].g1[0].sub_Mrom_byteout_rom000022
sbox_f_1/g0[1].g1[1].sub_Mrom_byteout_rom0000101
SLICE_X56Y61.B5 net (fanout=1) 0.546 sbox_f_1/g0[1].g1[1].sub_Mrom_byteout_rom0000101
SLICE_X56Y61.CLK Tas 0.201 sbox_f_1/g0[1].g1[1].sub/byteout<5>
sbox_f_1/g0[1].g1[1].sub_Mrom_byteout_rom000010_f7
sbox_f_1/g0[1].g1[1].sub_Mrom_byteout_rom000010_f7_rt
sbox_f_1/g0[1].g1[1].sub_Mrom_byteout_rom000010_f8
sbox_f_1/g0[1].g1[1].sub/byteout_5
------------------------------------------------- ---------------------------
Total 2.850ns (0.766ns logic, 2.084ns route)
(26.9% logic, 73.1% route)
 
--------------------------------------------------------------------------------
Slack (setup path): 0.027ns (requirement - (data path - clock path skew + uncertainty))
Source: proc[3].add/dataout<3>_1_4 (FF)
Destination: proc[3].sbox/g0[3].g1[1].sub/byteout_4 (FF)
Requirement: 3.000ns
Data Path Delay: 2.814ns (Levels of Logic = 2)
Clock Path Skew: -0.124ns (1.168 - 1.292)
Source Clock: clk_i_BUFGP rising at 0.000ns
Destination Clock: clk_i_BUFGP rising at 3.000ns
Clock Uncertainty: 0.035ns
 
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
 
Maximum Data Path: proc[3].add/dataout<3>_1_4 to proc[3].sbox/g0[3].g1[1].sub/byteout_4
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X24Y89.AQ Tcko 0.471 proc[3].add/dataout<3>_1_7
proc[3].add/dataout<3>_1_4
SLICE_X29Y84.B1 net (fanout=32) 1.591 proc[3].add/dataout<3>_1_4
SLICE_X29Y84.B Tilo 0.094 proc[3].sbox/g0[3].g1[1].sub_Mrom_byteout_rom000083
proc[3].sbox/g0[3].g1[1].sub_Mrom_byteout_rom000083
SLICE_X28Y84.D6 net (fanout=1) 0.433 proc[3].sbox/g0[3].g1[1].sub_Mrom_byteout_rom000083
SLICE_X28Y84.CLK Tas 0.225 proc[3].sbox/g0[3].g1[1].sub/byteout<4>
proc[3].sbox/g0[3].g1[1].sub_Mrom_byteout_rom00008_f7_0
proc[3].sbox/g0[3].g1[1].sub_Mrom_byteout_rom00008_f71_rt
proc[3].sbox/g0[3].g1[1].sub_Mrom_byteout_rom00008_f8
proc[3].sbox/g0[3].g1[1].sub/byteout_4
------------------------------------------------- ---------------------------
Total 2.814ns (0.790ns logic, 2.024ns route)
(28.1% logic, 71.9% route)
 
--------------------------------------------------------------------------------
Slack (setup path): 0.029ns (requirement - (data path - clock path skew + uncertainty))
Source: proc[4].add/dataout<0>_3_5 (FF)
Destination: proc[4].sbox/g0[0].g1[3].sub/byteout_1 (FF)
Requirement: 3.000ns
Data Path Delay: 2.833ns (Levels of Logic = 2)
Clock Path Skew: -0.103ns (1.169 - 1.272)
Source Clock: clk_i_BUFGP rising at 0.000ns
Destination Clock: clk_i_BUFGP rising at 3.000ns
Clock Uncertainty: 0.035ns
 
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
 
Maximum Data Path: proc[4].add/dataout<0>_3_5 to proc[4].sbox/g0[0].g1[3].sub/byteout_1
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X24Y60.BQ Tcko 0.471 proc[4].add/dataout<0>_3_7
proc[4].add/dataout<0>_3_5
SLICE_X19Y52.A4 net (fanout=32) 1.447 proc[4].add/dataout<0>_3_5
SLICE_X19Y52.A Tilo 0.094 proc[4].sbox/g0[0].g1[3].sub_Mrom_byteout_rom0000141
proc[4].sbox/g0[0].g1[3].sub_Mrom_byteout_rom000024
SLICE_X15Y51.D6 net (fanout=1) 0.569 proc[4].sbox/g0[0].g1[3].sub_Mrom_byteout_rom000024
SLICE_X15Y51.CLK Tas 0.252 proc[4].sbox/g0[0].g1[3].sub/byteout<1>
proc[4].sbox/g0[0].g1[3].sub_Mrom_byteout_rom00002_f7_0
proc[4].sbox/g0[0].g1[3].sub_Mrom_byteout_rom00002_f71_rt
proc[4].sbox/g0[0].g1[3].sub_Mrom_byteout_rom00002_f8
proc[4].sbox/g0[0].g1[3].sub/byteout_1
------------------------------------------------- ---------------------------
Total 2.833ns (0.817ns logic, 2.016ns route)
(28.8% logic, 71.2% route)
 
--------------------------------------------------------------------------------
Slack (setup path): 0.031ns (requirement - (data path - clock path skew + uncertainty))
Source: proc[7].add/dataout<0>_1_4 (FF)
Destination: proc[7].sbox/g0[0].g1[1].sub/byteout_3 (FF)
Requirement: 3.000ns
Data Path Delay: 2.875ns (Levels of Logic = 2)
Clock Path Skew: -0.059ns (1.245 - 1.304)
Source Clock: clk_i_BUFGP rising at 0.000ns
Destination Clock: clk_i_BUFGP rising at 3.000ns
Clock Uncertainty: 0.035ns
 
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
 
Maximum Data Path: proc[7].add/dataout<0>_1_4 to proc[7].sbox/g0[0].g1[1].sub/byteout_3
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X29Y13.AQ Tcko 0.450 proc[7].add/dataout<0>_1_7
proc[7].add/dataout<0>_1_4
SLICE_X27Y8.A1 net (fanout=32) 1.693 proc[7].add/dataout<0>_1_4
SLICE_X27Y8.A Tilo 0.094 proc[7].sbox/g0[0].g1[1].sub_Mrom_byteout_rom000063
proc[7].sbox/g0[0].g1[1].sub_Mrom_byteout_rom000063
SLICE_X27Y10.D5 net (fanout=1) 0.386 proc[7].sbox/g0[0].g1[1].sub_Mrom_byteout_rom000063
SLICE_X27Y10.CLK Tas 0.252 proc[7].sbox/g0[0].g1[1].sub/byteout<3>
proc[7].sbox/g0[0].g1[1].sub_Mrom_byteout_rom00006_f7_0
proc[7].sbox/g0[0].g1[1].sub_Mrom_byteout_rom00006_f71_rt
proc[7].sbox/g0[0].g1[1].sub_Mrom_byteout_rom00006_f8
proc[7].sbox/g0[0].g1[1].sub/byteout_3
------------------------------------------------- ---------------------------
Total 2.875ns (0.796ns logic, 2.079ns route)
(27.7% logic, 72.3% route)
 
--------------------------------------------------------------------------------
Slack (setup path): 0.036ns (requirement - (data path - clock path skew + uncertainty))
Source: proc[8].add/dataout<1>_3_4 (FF)
Destination: proc[8].sbox/g0[1].g1[3].sub/byteout_3 (FF)
Requirement: 3.000ns
Data Path Delay: 2.786ns (Levels of Logic = 2)
Clock Path Skew: -0.143ns (1.130 - 1.273)
Source Clock: clk_i_BUFGP rising at 0.000ns
Destination Clock: clk_i_BUFGP rising at 3.000ns
Clock Uncertainty: 0.035ns
 
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
 
Maximum Data Path: proc[8].add/dataout<1>_3_4 to proc[8].sbox/g0[1].g1[3].sub/byteout_3
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X36Y35.AQ Tcko 0.471 proc[8].add/dataout<1>_3_7
proc[8].add/dataout<1>_3_4
SLICE_X35Y42.C3 net (fanout=32) 1.552 proc[8].add/dataout<1>_3_4
SLICE_X35Y42.C Tilo 0.094 sbox_f_1/g0[3].g1[2].sub_Mrom_byteout_rom000083
proc[8].sbox/g0[1].g1[3].sub_Mrom_byteout_rom000063
SLICE_X32Y42.D6 net (fanout=1) 0.444 proc[8].sbox/g0[1].g1[3].sub_Mrom_byteout_rom000063
SLICE_X32Y42.CLK Tas 0.225 proc[8].sbox/g0[1].g1[3].sub/byteout<3>
proc[8].sbox/g0[1].g1[3].sub_Mrom_byteout_rom00006_f7_0
proc[8].sbox/g0[1].g1[3].sub_Mrom_byteout_rom00006_f71_rt
proc[8].sbox/g0[1].g1[3].sub_Mrom_byteout_rom00006_f8
proc[8].sbox/g0[1].g1[3].sub/byteout_3
------------------------------------------------- ---------------------------
Total 2.786ns (0.790ns logic, 1.996ns route)
(28.4% logic, 71.6% route)
 
--------------------------------------------------------------------------------
Slack (setup path): 0.036ns (requirement - (data path - clock path skew + uncertainty))
Source: proc[8].mix/g0[1].mix/out2_2 (FF)
Destination: add_f_1/dataout<2>_1_2 (FF)
Requirement: 3.000ns
Data Path Delay: 2.762ns (Levels of Logic = 1)
Clock Path Skew: -0.167ns (1.208 - 1.375)
Source Clock: clk_i_BUFGP rising at 0.000ns
Destination Clock: clk_i_BUFGP rising at 3.000ns
Clock Uncertainty: 0.035ns
 
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
 
Maximum Data Path: proc[8].mix/g0[1].mix/out2_2 to add_f_1/dataout<2>_1_2
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X55Y36.CQ Tcko 0.450 proc[8].mix/g0[1].mix/out2<5>
proc[8].mix/g0[1].mix/out2_2
SLICE_X57Y73.C5 net (fanout=1) 2.283 proc[8].mix/g0[1].mix/out2<2>
SLICE_X57Y73.CLK Tas 0.029 add_f_1/dataout<2>_1_3
add_f_1/Mxor_added<2><1>_Result<2>1
add_f_1/dataout<2>_1_2
------------------------------------------------- ---------------------------
Total 2.762ns (0.479ns logic, 2.283ns route)
(17.3% logic, 82.7% route)
 
--------------------------------------------------------------------------------
Slack (setup path): 0.040ns (requirement - (data path - clock path skew + uncertainty))
Source: proc[5].sbox/g0[1].g1[1].sub/byteout_2 (FF)
Destination: proc[5].mix/g0[0].mix/out1_3 (FF)
Requirement: 3.000ns
Data Path Delay: 2.871ns (Levels of Logic = 1)
Clock Path Skew: -0.054ns (1.331 - 1.385)
Source Clock: clk_i_BUFGP rising at 0.000ns
Destination Clock: clk_i_BUFGP rising at 3.000ns
Clock Uncertainty: 0.035ns
 
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
 
Maximum Data Path: proc[5].sbox/g0[1].g1[1].sub/byteout_2 to proc[5].mix/g0[0].mix/out1_3
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X0Y32.BQ Tcko 0.471 proc[5].sbox/g0[1].g1[1].sub/byteout<2>
proc[5].sbox/g0[1].g1[1].sub/byteout_2
SLICE_X10Y18.A6 net (fanout=7) 2.253 proc[5].sbox/g0[1].g1[1].sub/byteout<2>
SLICE_X10Y18.CLK Tas 0.147 proc[5].mix/g0[0].mix/out1<3>
proc[5].mix/g0[0].mix/out1_xor0000<3>1
proc[5].mix/g0[0].mix/out1_xor0000<3>_f7
proc[5].mix/g0[0].mix/out1_3
------------------------------------------------- ---------------------------
Total 2.871ns (0.618ns logic, 2.253ns route)
(21.5% logic, 78.5% route)
 
--------------------------------------------------------------------------------
Slack (setup path): 0.041ns (requirement - (data path - clock path skew + uncertainty))
Source: proc[6].add/dataout<2>_0_5 (FF)
Destination: proc[6].sbox/g0[2].g1[0].sub/byteout_4 (FF)
Requirement: 3.000ns
Data Path Delay: 2.742ns (Levels of Logic = 2)
Clock Path Skew: -0.182ns (1.254 - 1.436)
Source Clock: clk_i_BUFGP rising at 0.000ns
Destination Clock: clk_i_BUFGP rising at 3.000ns
Clock Uncertainty: 0.035ns
 
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
 
Maximum Data Path: proc[6].add/dataout<2>_0_5 to proc[6].sbox/g0[2].g1[0].sub/byteout_4
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X14Y16.BQ Tcko 0.450 proc[6].add/dataout<2>_0_7
proc[6].add/dataout<2>_0_5
SLICE_X20Y20.C2 net (fanout=32) 1.524 proc[6].add/dataout<2>_0_5
SLICE_X20Y20.C Tilo 0.094 proc[6].sbox/g0[2].g1[0].sub/byteout<4>
proc[6].sbox/g0[2].g1[0].sub_Mrom_byteout_rom000082
SLICE_X20Y20.D6 net (fanout=1) 0.449 proc[6].sbox/g0[2].g1[0].sub_Mrom_byteout_rom000082
SLICE_X20Y20.CLK Tas 0.225 proc[6].sbox/g0[2].g1[0].sub/byteout<4>
proc[6].sbox/g0[2].g1[0].sub_Mrom_byteout_rom00008_f7_0
proc[6].sbox/g0[2].g1[0].sub_Mrom_byteout_rom00008_f71_rt
proc[6].sbox/g0[2].g1[0].sub_Mrom_byteout_rom00008_f8
proc[6].sbox/g0[2].g1[0].sub/byteout_4
------------------------------------------------- ---------------------------
Total 2.742ns (0.769ns logic, 1.973ns route)
(28.0% logic, 72.0% route)
 
--------------------------------------------------------------------------------
Slack (setup path): 0.041ns (requirement - (data path - clock path skew + uncertainty))
Source: proc[5].sbox/g0[1].g1[1].sub/byteout_2 (FF)
Destination: proc[5].mix/g0[0].mix/out1_3 (FF)
Requirement: 3.000ns
Data Path Delay: 2.870ns (Levels of Logic = 1)
Clock Path Skew: -0.054ns (1.331 - 1.385)
Source Clock: clk_i_BUFGP rising at 0.000ns
Destination Clock: clk_i_BUFGP rising at 3.000ns
Clock Uncertainty: 0.035ns
 
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
 
Maximum Data Path: proc[5].sbox/g0[1].g1[1].sub/byteout_2 to proc[5].mix/g0[0].mix/out1_3
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X0Y32.BQ Tcko 0.471 proc[5].sbox/g0[1].g1[1].sub/byteout<2>
proc[5].sbox/g0[1].g1[1].sub/byteout_2
SLICE_X10Y18.B6 net (fanout=7) 2.260 proc[5].sbox/g0[1].g1[1].sub/byteout<2>
SLICE_X10Y18.CLK Tas 0.139 proc[5].mix/g0[0].mix/out1<3>
proc[5].mix/g0[0].mix/out1_xor0000<3>2
proc[5].mix/g0[0].mix/out1_xor0000<3>_f7
proc[5].mix/g0[0].mix/out1_3
------------------------------------------------- ---------------------------
Total 2.870ns (0.610ns logic, 2.260ns route)
(21.3% logic, 78.7% route)
 
--------------------------------------------------------------------------------
 
Hold Paths: TS_clk = PERIOD TIMEGRP "clk_i" 3 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack (hold path): 0.296ns (requirement - (clock path skew + uncertainty - data path))
Source: proc[0].sbox/nextkey<0>_2_5 (FF)
Destination: proc[0].mix/outrkey<0>_2_5 (FF)
Requirement: 0.000ns
Data Path Delay: 0.452ns (Levels of Logic = 0)
Clock Path Skew: 0.156ns (1.377 - 1.221)
Source Clock: clk_i_BUFGP rising at 3.000ns
Destination Clock: clk_i_BUFGP rising at 3.000ns
Clock Uncertainty: 0.000ns
 
Minimum Data Path: proc[0].sbox/nextkey<0>_2_5 to proc[0].mix/outrkey<0>_2_5
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X55Y79.BQ Tcko 0.414 proc[0].sbox/nextkey<0>_2_7
proc[0].sbox/nextkey<0>_2_5
SLICE_X56Y80.BX net (fanout=1) 0.280 proc[0].sbox/nextkey<0>_2_5
SLICE_X56Y80.CLK Tckdi (-Th) 0.242 proc[0].mix/outrkey<0>_2_7
proc[0].mix/outrkey<0>_2_5
------------------------------------------------- ---------------------------
Total 0.452ns (0.172ns logic, 0.280ns route)
(38.1% logic, 61.9% route)
 
--------------------------------------------------------------------------------
Slack (hold path): 0.339ns (requirement - (clock path skew + uncertainty - data path))
Source: proc[1].sbox/nextkey<0>_0_5 (FF)
Destination: proc[1].mix/outrkey<0>_0_5 (FF)
Requirement: 0.000ns
Data Path Delay: 0.472ns (Levels of Logic = 0)
Clock Path Skew: 0.133ns (1.348 - 1.215)
Source Clock: clk_i_BUFGP rising at 3.000ns
Destination Clock: clk_i_BUFGP rising at 3.000ns
Clock Uncertainty: 0.000ns
 
Minimum Data Path: proc[1].sbox/nextkey<0>_0_5 to proc[1].mix/outrkey<0>_0_5
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X43Y99.BQ Tcko 0.414 proc[1].sbox/nextkey<0>_0_7
proc[1].sbox/nextkey<0>_0_5
SLICE_X43Y101.BX net (fanout=1) 0.289 proc[1].sbox/nextkey<0>_0_5
SLICE_X43Y101.CLK Tckdi (-Th) 0.231 proc[1].mix/outrkey<0>_0_7
proc[1].mix/outrkey<0>_0_5
------------------------------------------------- ---------------------------
Total 0.472ns (0.183ns logic, 0.289ns route)
(38.8% logic, 61.2% route)
 
--------------------------------------------------------------------------------
Slack (hold path): 0.412ns (requirement - (clock path skew + uncertainty - data path))
Source: proc[0].add/step1/sub1/byteout_5 (FF)
Destination: proc[0].sbox/nextkey<0>_0_5 (FF)
Requirement: 0.000ns
Data Path Delay: 0.499ns (Levels of Logic = 1)
Clock Path Skew: 0.087ns (0.577 - 0.490)
Source Clock: clk_i_BUFGP rising at 3.000ns
Destination Clock: clk_i_BUFGP rising at 3.000ns
Clock Uncertainty: 0.000ns
 
Minimum Data Path: proc[0].add/step1/sub1/byteout_5 to proc[0].sbox/nextkey<0>_0_5
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X45Y79.BQ Tcko 0.414 proc[0].add/step1/sub1/byteout<5>
proc[0].add/step1/sub1/byteout_5
SLICE_X46Y79.B6 net (fanout=4) 0.281 proc[0].add/step1/sub1/byteout<5>
SLICE_X46Y79.CLK Tah (-Th) 0.196 proc[0].sbox/nextkey<0>_0_7
proc[0].sbox/Mxor_nextkey<0>_0_xor0000_Result<5>1
proc[0].sbox/nextkey<0>_0_5
------------------------------------------------- ---------------------------
Total 0.499ns (0.218ns logic, 0.281ns route)
(43.7% logic, 56.3% route)
 
--------------------------------------------------------------------------------
Slack (hold path): 0.419ns (requirement - (clock path skew + uncertainty - data path))
Source: proc[1].sbox/nextkey<1>_1_2 (FF)
Destination: proc[1].mix/outrkey<1>_1_2 (FF)
Requirement: 0.000ns
Data Path Delay: 0.491ns (Levels of Logic = 0)
Clock Path Skew: 0.072ns (0.543 - 0.471)
Source Clock: clk_i_BUFGP rising at 3.000ns
Destination Clock: clk_i_BUFGP rising at 3.000ns
Clock Uncertainty: 0.000ns
 
Minimum Data Path: proc[1].sbox/nextkey<1>_1_2 to proc[1].mix/outrkey<1>_1_2
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X27Y108.CQ Tcko 0.414 proc[1].sbox/nextkey<1>_1_3
proc[1].sbox/nextkey<1>_1_2
SLICE_X22Y108.CX net (fanout=1) 0.295 proc[1].sbox/nextkey<1>_1_2
SLICE_X22Y108.CLK Tckdi (-Th) 0.218 proc[1].mix/outrkey<1>_1_3
proc[1].mix/outrkey<1>_1_2
------------------------------------------------- ---------------------------
Total 0.491ns (0.196ns logic, 0.295ns route)
(39.9% logic, 60.1% route)
 
--------------------------------------------------------------------------------
Slack (hold path): 0.420ns (requirement - (clock path skew + uncertainty - data path))
Source: proc[6].add/step1/c0_3_4 (FF)
Destination: proc[6].sbox/nextkey<3>_0_4 (FF)
Requirement: 0.000ns
Data Path Delay: 0.474ns (Levels of Logic = 1)
Clock Path Skew: 0.054ns (0.493 - 0.439)
Source Clock: clk_i_BUFGP rising at 3.000ns
Destination Clock: clk_i_BUFGP rising at 3.000ns
Clock Uncertainty: 0.000ns
 
Minimum Data Path: proc[6].add/step1/c0_3_4 to proc[6].sbox/nextkey<3>_0_4
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X31Y24.AQ Tcko 0.414 proc[6].add/step1/c0_3_7
proc[6].add/step1/c0_3_4
SLICE_X33Y24.A6 net (fanout=1) 0.257 proc[6].add/step1/c0_3_4
SLICE_X33Y24.CLK Tah (-Th) 0.197 proc[6].sbox/nextkey<3>_0_7
proc[6].sbox/Mxor_nextkey<3>_0_xor0000_Result<4>1
proc[6].sbox/nextkey<3>_0_4
------------------------------------------------- ---------------------------
Total 0.474ns (0.217ns logic, 0.257ns route)
(45.8% logic, 54.2% route)
 
--------------------------------------------------------------------------------
Slack (hold path): 0.421ns (requirement - (clock path skew + uncertainty - data path))
Source: proc[8].add/step1/c0_3_0 (FF)
Destination: proc[8].sbox/nextkey<3>_0_0 (FF)
Requirement: 0.000ns
Data Path Delay: 0.461ns (Levels of Logic = 1)
Clock Path Skew: 0.040ns (0.546 - 0.506)
Source Clock: clk_i_BUFGP rising at 3.000ns
Destination Clock: clk_i_BUFGP rising at 3.000ns
Clock Uncertainty: 0.000ns
 
Minimum Data Path: proc[8].add/step1/c0_3_0 to proc[8].sbox/nextkey<3>_0_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X51Y36.AQ Tcko 0.414 proc[8].add/step1/c0_3_3
proc[8].add/step1/c0_3_0
SLICE_X48Y36.A6 net (fanout=1) 0.266 proc[8].add/step1/c0_3_0
SLICE_X48Y36.CLK Tah (-Th) 0.219 proc[8].sbox/nextkey<3>_0_3
proc[8].sbox/Mxor_nextkey<3>_0_xor0000_Result<0>1
proc[8].sbox/nextkey<3>_0_0
------------------------------------------------- ---------------------------
Total 0.461ns (0.195ns logic, 0.266ns route)
(42.3% logic, 57.7% route)
 
--------------------------------------------------------------------------------
Slack (hold path): 0.422ns (requirement - (clock path skew + uncertainty - data path))
Source: proc[3].add/step1/c0_3_4 (FF)
Destination: proc[3].sbox/nextkey<3>_0_4 (FF)
Requirement: 0.000ns
Data Path Delay: 0.480ns (Levels of Logic = 1)
Clock Path Skew: 0.058ns (0.470 - 0.412)
Source Clock: clk_i_BUFGP rising at 3.000ns
Destination Clock: clk_i_BUFGP rising at 3.000ns
Clock Uncertainty: 0.000ns
 
Minimum Data Path: proc[3].add/step1/c0_3_4 to proc[3].sbox/nextkey<3>_0_4
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X33Y70.AQ Tcko 0.414 proc[3].add/step1/c0_3_7
proc[3].add/step1/c0_3_4
SLICE_X30Y70.A6 net (fanout=1) 0.263 proc[3].add/step1/c0_3_4
SLICE_X30Y70.CLK Tah (-Th) 0.197 proc[3].sbox/nextkey<3>_0_7
proc[3].sbox/Mxor_nextkey<3>_0_xor0000_Result<4>1
proc[3].sbox/nextkey<3>_0_4
------------------------------------------------- ---------------------------
Total 0.480ns (0.217ns logic, 0.263ns route)
(45.2% logic, 54.8% route)
 
--------------------------------------------------------------------------------
Slack (hold path): 0.422ns (requirement - (clock path skew + uncertainty - data path))
Source: proc[6].mix/g0[2].mix/out1_1 (FF)
Destination: proc[7].add/dataout<1>_2_1 (FF)
Requirement: 0.000ns
Data Path Delay: 0.464ns (Levels of Logic = 1)
Clock Path Skew: 0.042ns (0.542 - 0.500)
Source Clock: clk_i_BUFGP rising at 3.000ns
Destination Clock: clk_i_BUFGP rising at 3.000ns
Clock Uncertainty: 0.000ns
 
Minimum Data Path: proc[6].mix/g0[2].mix/out1_1 to proc[7].add/dataout<1>_2_1
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X27Y20.AQ Tcko 0.414 proc[6].mix/g0[2].mix/out1<2>
proc[6].mix/g0[2].mix/out1_1
SLICE_X24Y20.B6 net (fanout=1) 0.272 proc[6].mix/g0[2].mix/out1<1>
SLICE_X24Y20.CLK Tah (-Th) 0.222 proc[7].add/dataout<1>_2_3
proc[7].add/Mxor_added<1><2>_Result<1>1
proc[7].add/dataout<1>_2_1
------------------------------------------------- ---------------------------
Total 0.464ns (0.192ns logic, 0.272ns route)
(41.4% logic, 58.6% route)
 
--------------------------------------------------------------------------------
Slack (hold path): 0.422ns (requirement - (clock path skew + uncertainty - data path))
Source: add_f_1/step1/c2_3_2 (FF)
Destination: sbox_f_1/nextkey<3>_2_2 (FF)
Requirement: 0.000ns
Data Path Delay: 0.486ns (Levels of Logic = 1)
Clock Path Skew: 0.064ns (0.559 - 0.495)
Source Clock: clk_i_BUFGP rising at 3.000ns
Destination Clock: clk_i_BUFGP rising at 3.000ns
Clock Uncertainty: 0.000ns
 
Minimum Data Path: add_f_1/step1/c2_3_2 to sbox_f_1/nextkey<3>_2_2
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X49Y45.CQ Tcko 0.414 add_f_1/step1/c2_3_3
add_f_1/step1/c2_3_2
SLICE_X50Y44.C6 net (fanout=1) 0.267 add_f_1/step1/c2_3_2
SLICE_X50Y44.CLK Tah (-Th) 0.195 sbox_f_1/nextkey<3>_2_3
sbox_f_1/Mxor_nextkey<3>_2_xor0000_Result<2>1
sbox_f_1/nextkey<3>_2_2
------------------------------------------------- ---------------------------
Total 0.486ns (0.219ns logic, 0.267ns route)
(45.1% logic, 54.9% route)
 
--------------------------------------------------------------------------------
Slack (hold path): 0.423ns (requirement - (clock path skew + uncertainty - data path))
Source: proc[6].add/step1/c0_3_7 (FF)
Destination: proc[6].sbox/nextkey<3>_0_7 (FF)
Requirement: 0.000ns
Data Path Delay: 0.477ns (Levels of Logic = 1)
Clock Path Skew: 0.054ns (0.493 - 0.439)
Source Clock: clk_i_BUFGP rising at 3.000ns
Destination Clock: clk_i_BUFGP rising at 3.000ns
Clock Uncertainty: 0.000ns
 
Minimum Data Path: proc[6].add/step1/c0_3_7 to proc[6].sbox/nextkey<3>_0_7
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X31Y24.DQ Tcko 0.414 proc[6].add/step1/c0_3_7
proc[6].add/step1/c0_3_7
SLICE_X33Y24.D6 net (fanout=1) 0.258 proc[6].add/step1/c0_3_7
SLICE_X33Y24.CLK Tah (-Th) 0.195 proc[6].sbox/nextkey<3>_0_7
proc[6].sbox/Mxor_nextkey<3>_0_xor0000_Result<7>1
proc[6].sbox/nextkey<3>_0_7
------------------------------------------------- ---------------------------
Total 0.477ns (0.219ns logic, 0.258ns route)
(45.9% logic, 54.1% route)
 
--------------------------------------------------------------------------------
 
Component Switching Limit Checks: TS_clk = PERIOD TIMEGRP "clk_i" 3 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 1.946ns (period - (min low pulse limit / (low pulse / period)))
Period: 3.000ns
Low pulse: 1.500ns
Low pulse limit: 0.527ns (Trpw)
Physical resource: proc[8].sbox/g0[0].g1[3].sub/byteout<3>/SR
Logical resource: proc[8].sbox/g0[0].g1[3].sub/byteout_3/SR
Location pin: SLICE_X38Y26.SR
Clock network: rst_i_BUFGP
--------------------------------------------------------------------------------
Slack: 1.946ns (period - (min high pulse limit / (high pulse / period)))
Period: 3.000ns
High pulse: 1.500ns
High pulse limit: 0.527ns (Trpw)
Physical resource: proc[8].sbox/g0[0].g1[3].sub/byteout<3>/SR
Logical resource: proc[8].sbox/g0[0].g1[3].sub/byteout_3/SR
Location pin: SLICE_X38Y26.SR
Clock network: rst_i_BUFGP
--------------------------------------------------------------------------------
Slack: 1.946ns (period - (min low pulse limit / (low pulse / period)))
Period: 3.000ns
Low pulse: 1.500ns
Low pulse limit: 0.527ns (Trpw)
Physical resource: proc[8].sbox/g0[2].g1[3].sub/byteout<3>/SR
Logical resource: proc[8].sbox/g0[2].g1[3].sub/byteout_3/SR
Location pin: SLICE_X59Y24.SR
Clock network: rst_i_BUFGP
--------------------------------------------------------------------------------
Slack: 1.946ns (period - (min high pulse limit / (high pulse / period)))
Period: 3.000ns
High pulse: 1.500ns
High pulse limit: 0.527ns (Trpw)
Physical resource: proc[8].sbox/g0[2].g1[3].sub/byteout<3>/SR
Logical resource: proc[8].sbox/g0[2].g1[3].sub/byteout_3/SR
Location pin: SLICE_X59Y24.SR
Clock network: rst_i_BUFGP
--------------------------------------------------------------------------------
Slack: 1.946ns (period - (min low pulse limit / (low pulse / period)))
Period: 3.000ns
Low pulse: 1.500ns
Low pulse limit: 0.527ns (Trpw)
Physical resource: proc[8].sbox/g0[3].g1[3].sub/byteout<3>/SR
Logical resource: proc[8].sbox/g0[3].g1[3].sub/byteout_3/SR
Location pin: SLICE_X58Y42.SR
Clock network: rst_i_BUFGP
--------------------------------------------------------------------------------
Slack: 1.946ns (period - (min high pulse limit / (high pulse / period)))
Period: 3.000ns
High pulse: 1.500ns
High pulse limit: 0.527ns (Trpw)
Physical resource: proc[8].sbox/g0[3].g1[3].sub/byteout<3>/SR
Logical resource: proc[8].sbox/g0[3].g1[3].sub/byteout_3/SR
Location pin: SLICE_X58Y42.SR
Clock network: rst_i_BUFGP
--------------------------------------------------------------------------------
Slack: 1.946ns (period - (min low pulse limit / (low pulse / period)))
Period: 3.000ns
Low pulse: 1.500ns
Low pulse limit: 0.527ns (Trpw)
Physical resource: proc[7].sbox/g0[1].g1[3].sub/byteout<3>/SR
Logical resource: proc[7].sbox/g0[1].g1[3].sub/byteout_3/SR
Location pin: SLICE_X42Y7.SR
Clock network: rst_i_BUFGP
--------------------------------------------------------------------------------
Slack: 1.946ns (period - (min high pulse limit / (high pulse / period)))
Period: 3.000ns
High pulse: 1.500ns
High pulse limit: 0.527ns (Trpw)
Physical resource: proc[7].sbox/g0[1].g1[3].sub/byteout<3>/SR
Logical resource: proc[7].sbox/g0[1].g1[3].sub/byteout_3/SR
Location pin: SLICE_X42Y7.SR
Clock network: rst_i_BUFGP
--------------------------------------------------------------------------------
Slack: 1.946ns (period - (min low pulse limit / (low pulse / period)))
Period: 3.000ns
Low pulse: 1.500ns
Low pulse limit: 0.527ns (Trpw)
Physical resource: proc[7].sbox/g0[2].g1[3].sub/byteout<3>/SR
Logical resource: proc[7].sbox/g0[2].g1[3].sub/byteout_3/SR
Location pin: SLICE_X33Y11.SR
Clock network: rst_i_BUFGP
--------------------------------------------------------------------------------
Slack: 1.946ns (period - (min high pulse limit / (high pulse / period)))
Period: 3.000ns
High pulse: 1.500ns
High pulse limit: 0.527ns (Trpw)
Physical resource: proc[7].sbox/g0[2].g1[3].sub/byteout<3>/SR
Logical resource: proc[7].sbox/g0[2].g1[3].sub/byteout_3/SR
Location pin: SLICE_X33Y11.SR
Clock network: rst_i_BUFGP
--------------------------------------------------------------------------------
 
 
All constraints were met.
 
 
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
 
Clock to Setup on destination clock clk_i
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk_i | 2.974| | | |
---------------+---------+---------+---------+---------+
 
 
Timing summary:
---------------
 
Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0)
 
Constraints cover 59472 paths, 0 nets, and 69148 connections
 
Design statistics:
Minimum period: 2.974ns{1} (Maximum frequency: 336.247MHz)
 
 
------------------------------------Footnotes-----------------------------------
1) The minimum period statistic assumes all single cycle delays.
 
Analysis completed Thu Mar 25 15:34:03 2010
--------------------------------------------------------------------------------
 
Trace Settings:
-------------------------
Trace Settings
 
Peak Memory Usage: 381 MB
 
 
 
/aes_pipe/trunk/syn/Xilinx/log/aes_top_map.xrpt
0,0 → 1,2856
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="lin" product="ISE" version="11.1">
 
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
 
<application stringID="Map" timeStamp="Thu Mar 25 14:30:27 2010">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
<item stringID="variable" value="XILINX_PLANAHEAD"/>
<item stringID="value" value="/opt/Xilinx/11.1/PlanAhead"/>
</row>
<row stringID="row" value="1">
<item stringID="variable" value="XILINX"/>
<item stringID="value" value="/opt/Xilinx/11.1/ISE"/>
</row>
<row stringID="row" value="2">
<item stringID="variable" value="XILINX_DSP"/>
<item stringID="value" value="/opt/Xilinx/11.1/DSP_Tools/lin"/>
</row>
</table>
<item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Ubuntu"/>
<item stringID="User_EnvOsrelease" value="Ubuntu 9.04"/>
</item>
<item stringID="User_EnvHost" value="blackpearl-laptop"/>
<table stringID="User_EnvCpu">
<column stringID="arch"/>
<column stringID="speed"/>
<row stringID="row" value="0">
<item stringID="arch" value="Intel(R) Core(TM)2 Duo CPU T5550 @ 1.83GHz"/>
<item stringID="speed" value="1833.000 MHz"/>
</row>
<row stringID="row" value="1">
<item stringID="arch" value="Intel(R) Core(TM)2 Duo CPU T5550 @ 1.83GHz"/>
<item stringID="speed" value="1000.000 MHz"/>
</row>
</table>
</section>
<task stringID="MAP_PACK_REPORT">
<item AVAILABLE="28800" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="7873">
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="7873"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
</item>
<item AVAILABLE="28800" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="14724">
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="0"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="14724"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_DPRAM_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_DPRAM_O6ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_DPRAM_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_SPRAM_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_SPRAM_O6ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_SPRAM_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_SRL_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_SRL_O6ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_SRL_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO5" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_O6" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_O5" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_O5ANDO6" value="0"/>
</item>
<item AVAILABLE="480" dataType="int" stringID="MAP_AGG_BONDED_IO" value="386"/>
<item AVAILABLE="80" dataType="int" stringID="MAP_AGG_UNBONDED_IO" value="0"/>
<item AVAILABLE="0" dataType="int" label="IOB Flip Flops" stringID="MAP_NUM_IOB_FF" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IOB_LATCH" value="0"/>
<item AVAILABLE="40" dataType="int" stringID="MAP_NUM_IOBM" value="0"/>
<item AVAILABLE="240" dataType="int" stringID="MAP_NUM_BONDED_IOBM" value="0"/>
<item AVAILABLE="40" dataType="int" stringID="MAP_NUM_IOBS" value="0"/>
<item AVAILABLE="240" dataType="int" stringID="MAP_NUM_BONDED_IOBS" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IPAD" value="0"/>
<item AVAILABLE="38" dataType="int" stringID="MAP_NUM_BONDED_IPAD" value="0"/>
<item AVAILABLE="24" dataType="int" stringID="MAP_NUM_BONDED_OPAD" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_OPAD" value="0"/>
<section stringID="MAP_DESIGN_INFORMATION">
<item stringID="MAP_PART" value="5vlx50tff1136-1"/>
<item stringID="MAP_DEVICE" value="xc5vlx50t"/>
<item stringID="MAP_ARCHITECTURE" value="virtex5"/>
<item stringID="MAP_PACKAGE" value="ff1136"/>
<item stringID="MAP_SPEED" value="-1"/>
</section>
<section stringID="MAP_DESIGN_SUMMARY">
<item dataType="int" stringID="MAP_NUM_ERRORS" value="0"/>
<item dataType="int" stringID="MAP_FILTERED_WARNINGS" value="0"/>
<item dataType="int" stringID="MAP_NUM_WARNINGS" value="0"/>
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="547912"/>
<item stringID="MAP_TOTAL_REAL_TIME" value="13 mins 31 secs "/>
<item stringID="MAP_TOTAL_CPU_TIME" value="13 mins "/>
</section>
<section stringID="MAP_SLICE_REPORTING">
<item AVAILABLE="28800" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="7873">
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="7873"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
</item>
<item AVAILABLE="28800" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="14724">
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="0"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="14724"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_DPRAM_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_DPRAM_O6ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_DPRAM_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_SPRAM_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_SPRAM_O6ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_SPRAM_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_SRL_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_SRL_O6ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_SRL_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO5" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_O6" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_O5" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_O5ANDO6" value="0"/>
</item>
<item AVAILABLE="7200" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="4656">
<item AVAILABLE="5280" dataType="int" stringID="MAP_NUM_SLICEL" value="4656"/>
<item AVAILABLE="1920" dataType="int" stringID="MAP_NUM_SLICEM" value="0"/>
</item>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="MAP_OCCUPIED_LUT_AND_FF" value="15770">
<item dataType="int" stringID="MAP_OCCUPIED_LUT_ONLY" value="7897"/>
<item dataType="int" label="Number with an unused LUT" stringID="MAP_OCCUPIED_FF_ONLY" value="1046"/>
<item dataType="int" label="Number of fully used LUT-FF pairs" stringID="MAP_OCCUPIED_FF_AND_LUT" value="6827"/>
</item>
</section>
<section stringID="MAP_IOB_REPORTING">
<item AVAILABLE="480" dataType="int" stringID="MAP_AGG_BONDED_IO" value="386"/>
<item AVAILABLE="80" dataType="int" stringID="MAP_AGG_UNBONDED_IO" value="0"/>
<item AVAILABLE="0" dataType="int" label="IOB Flip Flops" stringID="MAP_NUM_IOB_FF" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IOB_LATCH" value="0"/>
<item AVAILABLE="40" dataType="int" stringID="MAP_NUM_IOBM" value="0"/>
<item AVAILABLE="240" dataType="int" stringID="MAP_NUM_BONDED_IOBM" value="0"/>
<item AVAILABLE="40" dataType="int" stringID="MAP_NUM_IOBS" value="0"/>
<item AVAILABLE="240" dataType="int" stringID="MAP_NUM_BONDED_IOBS" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IPAD" value="0"/>
<item AVAILABLE="38" dataType="int" stringID="MAP_NUM_BONDED_IPAD" value="0"/>
<item AVAILABLE="24" dataType="int" stringID="MAP_NUM_BONDED_OPAD" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_OPAD" value="0"/>
</section>
<section stringID="MAP_HARD_IP_REPORTING"/>
<section stringID="MAP_RAM_FIFO_DATA">
<item AVAILABLE="60" dataType="int" label="Number of Block RAM/FIFO" stringID="MAP_NUM_RAMBFIFO36" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_RAMB36_EXP" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_RAMB36SDP_EXP" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_FIFO36_EXPNUM_FIFO36_72_EXP" value="0"/>
<item AVAILABLE="0" dataType="int" label="Number of 18k BlockRAM used" stringID="MAP_NUM_RAMB18X2" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_RAMB18X2SDP" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_RAMBFIFO18NUM_RAMBFIFO18_36" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_RAMB18X2_UPPER" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_RAMB18X2_LOWER" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_RAMBFIFO18_UPPER" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_RAMBFIFO18_LOWER" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_RAMB18X2SDP_UPPERNUM_RAMB18X2SDP_LOWER" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_RAMBFIFO18_36_UPPER" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_RAMBFIFO18_36_LOWER" value="0"/>
</section>
<section stringID="MAP_IP_DATA">
<item AVAILABLE="4" dataType="int" stringID="MAP_NUM_BSCAN" value="0"/>
<item AVAILABLE="6" dataType="int" stringID="MAP_NUM_BUFDS" value="0"/>
<item AVAILABLE="56" dataType="int" stringID="MAP_NUM_BUFIO" value="0"/>
<item AVAILABLE="24" dataType="int" stringID="MAP_NUM_BUFR" value="0"/>
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_CAPTURE" value="0"/>
<item AVAILABLE="24" dataType="int" stringID="MAP_NUM_CRC32" value="0"/>
<item AVAILABLE="12" dataType="int" stringID="MAP_NUM_CRC64" value="0"/>
<item AVAILABLE="12" dataType="int" label="Number of DCM_ADVs" stringID="MAP_NUM_DCM_ADV" value="0"/>
<item AVAILABLE="48" dataType="int" stringID="MAP_NUM_DSP48E" value="0"/>
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_EFUSE_USR" value="0"/>
<item AVAILABLE="6" dataType="int" stringID="MAP_NUM_GTP_DUAL" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_GTX_DUAL" value="0"/>
<item AVAILABLE="2" dataType="int" stringID="MAP_NUM_ICAP" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_ISERDES" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_OSERDES" value="0"/>
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_PCIE" value="0"/>
<item AVAILABLE="6" dataType="int" stringID="MAP_NUM_PLL_ADV" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_PPC440" value="0"/>
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_STARTUP" value="0"/>
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_SYSMON" value="0"/>
<item AVAILABLE="2" dataType="int" stringID="MAP_NUM_TEMAC" value="0"/>
</section>
<section stringID="MAP_BUFG_DATA">
<item dataType="int" label="Number used as BUFGs" stringID="MAP_NUM_BUFG" value="2"/>
<item dataType="int" stringID="MAP_NUM_BUFGCTR" value="0"/>
<item dataType="int" stringID="MAP_AVAILABLE" value="32"/>
</section>
<section stringID="MAP_MACRO_RPM_REPORTING">
<item dataType="int" stringID="MAP_HARD_MACROS" value="0"/>
<item dataType="int" stringID="MAP_RPMS" value="0"/>
</section>
<section stringID="MAP_IOB_PROPERTIES">
<table stringID="MAP_IOB_TABLE">
<column label="IOB&#xA;Name" stringID="IOB_NAME"/>
<column stringID="Type"/>
<column label="Direction" stringID="Direction"/>
<column label="IO&#xA;Standard" stringID="IO_STANDARD"/>
<column label="Diff&#xA;Term" stringID="DIFF_TERM"/>
<column label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH"/>
<column label="Slew&#xA;Rate" stringID="SLEW_RATE"/>
<column label="Reg&#xA;(s)" stringID="REGS"/>
<column stringID="Resistor"/>
<column label="IOB&#xA;Delay" stringID="IOB_DELAY"/>
<row stringID="row" value="1">
<item label="IOB&#xA;Name" stringID="IOB_NAME" value="ciphertext_o&lt;0>&lt;0>&lt;0>"/>
<item stringID="Type" value="IOB"/>
<item label="Direction" stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="2">
<item label="IOB&#xA;Name" stringID="IOB_NAME" value="ciphertext_o&lt;0>&lt;0>&lt;1>"/>
<item stringID="Type" value="IOB"/>
<item label="Direction" stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="3">
<item label="IOB&#xA;Name" stringID="IOB_NAME" value="ciphertext_o&lt;0>&lt;0>&lt;2>"/>
<item stringID="Type" value="IOB"/>
<item label="Direction" stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="4">
<item label="IOB&#xA;Name" stringID="IOB_NAME" value="ciphertext_o&lt;0>&lt;0>&lt;3>"/>
<item stringID="Type" value="IOB"/>
<item label="Direction" stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="5">
<item label="IOB&#xA;Name" stringID="IOB_NAME" value="ciphertext_o&lt;0>&lt;0>&lt;4>"/>
<item stringID="Type" value="IOB"/>
<item label="Direction" stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="6">
<item label="IOB&#xA;Name" stringID="IOB_NAME" value="ciphertext_o&lt;0>&lt;0>&lt;5>"/>
<item stringID="Type" value="IOB"/>
<item label="Direction" stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="7">
<item label="IOB&#xA;Name" stringID="IOB_NAME" value="ciphertext_o&lt;0>&lt;0>&lt;6>"/>
<item stringID="Type" value="IOB"/>
<item label="Direction" stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="8">
<item label="IOB&#xA;Name" stringID="IOB_NAME" value="ciphertext_o&lt;0>&lt;0>&lt;7>"/>
<item stringID="Type" value="IOB"/>
<item label="Direction" stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="9">
<item label="IOB&#xA;Name" stringID="IOB_NAME" value="ciphertext_o&lt;0>&lt;1>&lt;0>"/>
<item stringID="Type" value="IOB"/>
<item label="Direction" stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="10">
<item label="IOB&#xA;Name" stringID="IOB_NAME" value="ciphertext_o&lt;0>&lt;1>&lt;1>"/>
<item stringID="Type" value="IOB"/>
<item label="Direction" stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="11">
<item label="IOB&#xA;Name" stringID="IOB_NAME" value="ciphertext_o&lt;0>&lt;1>&lt;2>"/>
<item stringID="Type" value="IOB"/>
<item label="Direction" stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="12">
<item label="IOB&#xA;Name" stringID="IOB_NAME" value="ciphertext_o&lt;0>&lt;1>&lt;3>"/>
<item stringID="Type" value="IOB"/>
<item label="Direction" stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="13">
<item label="IOB&#xA;Name" stringID="IOB_NAME" value="ciphertext_o&lt;0>&lt;1>&lt;4>"/>
<item stringID="Type" value="IOB"/>
<item label="Direction" stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="14">
<item label="IOB&#xA;Name" stringID="IOB_NAME" value="ciphertext_o&lt;0>&lt;1>&lt;5>"/>
<item stringID="Type" value="IOB"/>
<item label="Direction" stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="15">
<item label="IOB&#xA;Name" stringID="IOB_NAME" value="ciphertext_o&lt;0>&lt;1>&lt;6>"/>
<item stringID="Type" value="IOB"/>
<item label="Direction" stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="16">
<item label="IOB&#xA;Name" stringID="IOB_NAME" value="ciphertext_o&lt;0>&lt;1>&lt;7>"/>
<item stringID="Type" value="IOB"/>
<item label="Direction" stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="17">
<item label="IOB&#xA;Name" stringID="IOB_NAME" value="ciphertext_o&lt;0>&lt;2>&lt;0>"/>
<item stringID="Type" value="IOB"/>
<item label="Direction" stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="18">
<item label="IOB&#xA;Name" stringID="IOB_NAME" value="ciphertext_o&lt;0>&lt;2>&lt;1>"/>
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<item label="Direction" stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="19">
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<item label="Direction" stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="20">
<item label="IOB&#xA;Name" stringID="IOB_NAME" value="ciphertext_o&lt;0>&lt;2>&lt;3>"/>
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<item label="Direction" stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="21">
<item label="IOB&#xA;Name" stringID="IOB_NAME" value="ciphertext_o&lt;0>&lt;2>&lt;4>"/>
<item stringID="Type" value="IOB"/>
<item label="Direction" stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="22">
<item label="IOB&#xA;Name" stringID="IOB_NAME" value="ciphertext_o&lt;0>&lt;2>&lt;5>"/>
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<item label="IO&#xA;Standard" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="23">
<item label="IOB&#xA;Name" stringID="IOB_NAME" value="ciphertext_o&lt;0>&lt;2>&lt;6>"/>
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<item label="IO&#xA;Standard" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="24">
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<item label="IO&#xA;Standard" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
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</row>
<row stringID="row" value="25">
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<item label="IO&#xA;Standard" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="26">
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<item label="IO&#xA;Standard" stringID="IO_STANDARD" value="LVCMOS25"/>
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</row>
<row stringID="row" value="27">
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<item label="IO&#xA;Standard" stringID="IO_STANDARD" value="LVCMOS25"/>
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</row>
<row stringID="row" value="28">
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</row>
<row stringID="row" value="29">
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<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
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</row>
<row stringID="row" value="30">
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<item label="IO&#xA;Standard" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
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<row stringID="row" value="31">
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<item label="IO&#xA;Standard" stringID="IO_STANDARD" value="LVCMOS25"/>
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<row stringID="row" value="32">
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<item label="IO&#xA;Standard" stringID="IO_STANDARD" value="LVCMOS25"/>
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<row stringID="row" value="33">
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<row stringID="row" value="34">
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<item label="IO&#xA;Standard" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="35">
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<section stringID="MAP_SHAPE_SECTION">
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</section>
<section stringID="MAP_GUIDE_REPORT"/>
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<section stringID="MAP_CONFIGURATION_STRING_DETAILS"/>
<section stringID="MAP_GENERAL_CONFIG_DATA"/>
<section stringID="MAP_CONTROL_SET_INFORMATION">
<item dataType="int" label="Number of unique control sets" stringID="MAP_NUM_CONTROL_SETS" value="1"/>
<tree stringID="MAP_CONTROL_SET_HIERARCHY">
<property stringID="MAP_CLOCK_SIGNAL"/>
<property stringID="MAP_RESET_SIGNAL"/>
<property stringID="MAP_SET_SIGNAL"/>
<property stringID="MAP_ENABLE_SIGNAL"/>
<property label="Slice&#xA;Load Count" stringID="MAP_SLICE_LOAD_COUNT"/>
<property label="Bel&#xA;Load Count" stringID="MAP_BEL_LOAD_COUNT"/>
</tree>
</section>
</task>
<section stringID="MAP_RAM_FIFO_DATA">
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<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_RAMB36_EXP" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_RAMB36SDP_EXP" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_FIFO36_EXPNUM_FIFO36_72_EXP" value="0"/>
<item AVAILABLE="0" dataType="int" label="Number of 18k BlockRAM used" stringID="MAP_NUM_RAMB18X2" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_RAMB18X2SDP" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_RAMBFIFO18NUM_RAMBFIFO18_36" value="0"/>
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<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_RAMB18X2SDP_UPPERNUM_RAMB18X2SDP_LOWER" value="0"/>
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<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_RAMBFIFO18_36_LOWER" value="0"/>
</section>
<section stringID="MAP_IP_DATA">
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<item AVAILABLE="6" dataType="int" stringID="MAP_NUM_BUFDS" value="0"/>
<item AVAILABLE="56" dataType="int" stringID="MAP_NUM_BUFIO" value="0"/>
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<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_PPC440" value="0"/>
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<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_SYSMON" value="0"/>
<item AVAILABLE="2" dataType="int" stringID="MAP_NUM_TEMAC" value="0"/>
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<section stringID="MAP_BUFG_DATA">
<item dataType="int" label="Number used as BUFGs" stringID="MAP_NUM_BUFG" value="2"/>
<item dataType="int" stringID="MAP_NUM_BUFGCTR" value="0"/>
<item dataType="int" stringID="MAP_AVAILABLE" value="32"/>
<item dataType="int" stringID="MAP_HARD_MACROS" value="0"/>
<item dataType="int" stringID="MAP_RPMS" value="0"/>
</section>
</application>
 
</document>
/aes_pipe/trunk/syn/Xilinx/log/aes.map.par
0,0 → 1,131
Release 11.1 par L.33 (lin)
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
 
blackpearl-laptop:: Thu Mar 25 14:30:35 2010
 
par -w -ol high ../out/aes.ncd ../out/aes.map.ncd
 
 
Constraints file: ../out/aes.pcf.
Loading device for application Rf_Device from file '5vlx50t.nph' in environment /opt/Xilinx/11.1/ISE.
"aes_top" is an NCD, version 3.2, device xc5vlx50t, package ff1136, speed -1
 
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)
 
 
Device speed data version: "PRODUCTION 1.64 2009-03-03".
 
 
 
Device Utilization Summary:
 
Number of BUFGs 2 out of 32 6%
Number of External IOBs 386 out of 480 80%
Number of LOCed IOBs 0 out of 386 0%
 
Number of Slice Registers 7873 out of 28800 27%
Number used as Flip Flops 7873
Number used as Latches 0
Number used as LatchThrus 0
 
Number of Slice LUTS 14724 out of 28800 51%
Number of Slice LUT-Flip Flop pairs 15770 out of 28800 54%
 
 
Overall effort level (-ol): High
Router effort level (-rl): High
 
Starting initial Timing Analysis. REAL time: 47 secs
Finished initial Timing Analysis. REAL time: 48 secs
 
Starting Router
 
 
Phase 1 : 77449 unrouted; REAL time: 52 secs
 
Phase 2 : 67441 unrouted; REAL time: 1 mins 5 secs
 
Phase 3 : 11182 unrouted; REAL time: 4 mins 3 secs
 
Phase 4 : 11253 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 4 mins 26 secs
 
Updating file: ../out/aes.map.ncd with current fully routed design.
 
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 5 mins 14 secs
 
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 5 mins 14 secs
 
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 5 mins 14 secs
 
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 5 mins 14 secs
 
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 5 mins 14 secs
 
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 5 mins 24 secs
Total REAL time to Router completion: 5 mins 24 secs
Total CPU time to Router completion: 5 mins 13 secs
 
Partition Implementation Status
-------------------------------
 
No Partitions were found in this design.
 
-------------------------------
 
Generating "PAR" statistics.
 
**************************
Generating Clock Report
**************************
 
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| clk_i_BUFGP | BUFGCTRL_X0Y1| No | 3403 | 0.334 | 1.843 |
+---------------------+--------------+------+------+------------+-------------+
 
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
 
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
 
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
 
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_clk = PERIOD TIMEGRP "clk_i" 3 ns HIGH | SETUP | 0.026ns| 2.974ns| 0| 0
50% | HOLD | 0.296ns| | 0| 0
------------------------------------------------------------------------------------------------------
 
 
All constraints were met.
 
 
Generating Pad Report.
 
All signals are completely routed.
 
Total REAL time to PAR completion: 5 mins 42 secs
Total CPU time to PAR completion: 5 mins 30 secs
 
Peak Memory Usage: 425 MB
 
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
 
Number of error messages: 0
Number of warning messages: 0
Number of info messages: 0
 
Writing design to file ../out/aes.map.ncd
 
 
 
PAR done!
/aes_pipe/trunk/syn/Xilinx/log/aes.mrp
0,0 → 1,552
Release 11.1 Map L.33 (lin)
Xilinx Mapping Report File for Design 'aes_top'
 
Design Information
------------------
Command Line : map -w -timing -ol high -cm speed -o ../out/aes.ncd
../out/aes.ngd
Target Device : xc5vlx50t
Target Package : ff1136
Target Speed : -1
Mapper Version : virtex5 -- $Revision: 1.51 $
Mapped Date : Thu Mar 25 14:16:56 2010
 
Design Summary
--------------
Number of errors: 0
Number of warnings: 0
Slice Logic Utilization:
Number of Slice Registers: 7,873 out of 28,800 27%
Number used as Flip Flops: 7,873
Number of Slice LUTs: 14,724 out of 28,800 51%
Number used as logic: 14,724 out of 28,800 51%
Number using O6 output only: 14,724
 
Slice Logic Distribution:
Number of occupied Slices: 4,656 out of 7,200 64%
Number of occupied SLICEMs: 0 out of 1,920 0%
Number of LUT Flip Flop pairs used: 15,770
Number with an unused Flip Flop: 7,897 out of 15,770 50%
Number with an unused LUT: 1,046 out of 15,770 6%
Number of fully used LUT-FF pairs: 6,827 out of 15,770 43%
Number of unique control sets: 1
Number of slice register sites lost
to control set restrictions: 3 out of 28,800 1%
 
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
OVERMAPPING of BRAM resources should be ignored if the design is
over-mapped for a non-BRAM resource or if placement fails.
 
IO Utilization:
Number of bonded IOBs: 386 out of 480 80%
 
Specific Feature Utilization:
Number of BUFG/BUFGCTRLs: 2 out of 32 6%
Number used as BUFGs: 2
 
Average Fanout of Non-Clock Nets: 5.14
 
Peak Memory Usage: 535 MB
Total REAL time to MAP completion: 13 mins 31 secs
Total CPU time to MAP completion: 13 mins
 
Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information
Section 13 - Control Set Information
Section 14 - Utilization by Hierarchy
 
Section 1 - Errors
------------------
 
Section 2 - Warnings
--------------------
 
Section 3 - Informational
-------------------------
INFO:Map:220 - The command line option -timing is automatically supported for
this architecture. Therefore, it is not necessary to specify this option.
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs.
INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
0.000 to 85.000 Celsius)
INFO:Pack:1720 - Initializing voltage to 0.950 Volts. (default - Range: 0.950 to
1.050 Volts)
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
INFO:Pack:1650 - Map created a placed design.
 
Section 4 - Removed Logic Summary
---------------------------------
1 block(s) optimized away
 
Section 5 - Removed Logic
-------------------------
 
Optimized Block(s):
TYPE BLOCK
VCC XST_VCC
 
Section 6 - IOB Properties
--------------------------
 
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB |
| | | | | Term | Strength | Rate | | | Delay |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| ciphertext_o<0><0><0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<0><0><1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<0><0><2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<0><0><3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<0><0><4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<0><0><5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<0><0><6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<0><0><7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<0><1><0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<0><1><1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<0><1><2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<0><1><3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<0><1><4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<0><1><5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<0><1><6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<0><1><7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<0><2><0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<0><2><1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<0><2><2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<0><2><3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<0><2><4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<0><2><5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<0><2><6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<0><2><7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<0><3><0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<0><3><1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<0><3><2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<0><3><3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<0><3><4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<0><3><5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<0><3><6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<0><3><7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<1><0><0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<1><0><1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<1><0><2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<1><0><3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<1><0><4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<1><0><5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<1><0><6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<1><0><7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<1><1><0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<1><1><1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<1><1><2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<1><1><3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<1><1><4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<1><1><5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<1><1><6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<1><1><7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<1><2><0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<1><2><1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<1><2><2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<1><2><3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<1><2><4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<1><2><5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<1><2><6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<1><2><7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<1><3><0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<1><3><1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<1><3><2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<1><3><3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<1><3><4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<1><3><5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<1><3><6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<1><3><7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<2><0><0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<2><0><1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<2><0><2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<2><0><3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<2><0><4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<2><0><5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<2><0><6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<2><0><7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<2><1><0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<2><1><1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<2><1><2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<2><1><3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<2><1><4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<2><1><5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<2><1><6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<2><1><7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<2><2><0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<2><2><1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<2><2><2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<2><2><3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<2><2><4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<2><2><5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<2><2><6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<2><2><7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<2><3><0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<2><3><1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<2><3><2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<2><3><3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<2><3><4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<2><3><5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<2><3><6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<2><3><7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<3><0><0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<3><0><1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<3><0><2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<3><0><3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<3><0><4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<3><0><5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<3><0><6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<3><0><7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<3><1><0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<3><1><1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<3><1><2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<3><1><3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<3><1><4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<3><1><5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<3><1><6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<3><1><7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<3><2><0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<3><2><1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<3><2><2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<3><2><3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<3><2><4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<3><2><5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<3><2><6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<3><2><7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<3><3><0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<3><3><1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<3><3><2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<3><3><3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<3><3><4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<3><3><5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<3><3><6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| ciphertext_o<3><3><7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| clk_i | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<0><0><0> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<0><0><1> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<0><0><2> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<0><0><3> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<0><0><4> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<0><0><5> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<0><0><6> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<0><0><7> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<0><1><0> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<0><1><1> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<0><1><2> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<0><1><3> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<0><1><4> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<0><1><5> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<0><1><6> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<0><1><7> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<0><2><0> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<0><2><1> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<0><2><2> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<0><2><3> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<0><2><4> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<0><2><5> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<0><2><6> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<0><2><7> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<0><3><0> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<0><3><1> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<0><3><2> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<0><3><3> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<0><3><4> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<0><3><5> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<0><3><6> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<0><3><7> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<1><0><0> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<1><0><1> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<1><0><2> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<1><0><3> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<1><0><4> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<1><0><5> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<1><0><6> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<1><0><7> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<1><1><0> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<1><1><1> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<1><1><2> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<1><1><3> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<1><1><4> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<1><1><5> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<1><1><6> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<1><1><7> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<1><2><0> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<1><2><1> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<1><2><2> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<1><2><3> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<1><2><4> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<1><2><5> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<1><2><6> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<1><2><7> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<1><3><0> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<1><3><1> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<1><3><2> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<1><3><3> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<1><3><4> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<1><3><5> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<1><3><6> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<1><3><7> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<2><0><0> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<2><0><1> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<2><0><2> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<2><0><3> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<2><0><4> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<2><0><5> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<2><0><6> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<2><0><7> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<2><1><0> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<2><1><1> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<2><1><2> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<2><1><3> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<2><1><4> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<2><1><5> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<2><1><6> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<2><1><7> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<2><2><0> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<2><2><1> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<2><2><2> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<2><2><3> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<2><2><4> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<2><2><5> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<2><2><6> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<2><2><7> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<2><3><0> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<2><3><1> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<2><3><2> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<2><3><3> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<2><3><4> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<2><3><5> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<2><3><6> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<2><3><7> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<3><0><0> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<3><0><1> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<3><0><2> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<3><0><3> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<3><0><4> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<3><0><5> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<3><0><6> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<3><0><7> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<3><1><0> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<3><1><1> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<3><1><2> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<3><1><3> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<3><1><4> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<3><1><5> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<3><1><6> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<3><1><7> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<3><2><0> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<3><2><1> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<3><2><2> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<3><2><3> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<3><2><4> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<3><2><5> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<3><2><6> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<3><2><7> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<3><3><0> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<3><3><1> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<3><3><2> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<3><3><3> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<3><3><4> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<3><3><5> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<3><3><6> | IOB | INPUT | LVCMOS25 | | | | | | |
| keyblock_i<3><3><7> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<0><0><0> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<0><0><1> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<0><0><2> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<0><0><3> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<0><0><4> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<0><0><5> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<0><0><6> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<0><0><7> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<0><1><0> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<0><1><1> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<0><1><2> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<0><1><3> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<0><1><4> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<0><1><5> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<0><1><6> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<0><1><7> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<0><2><0> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<0><2><1> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<0><2><2> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<0><2><3> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<0><2><4> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<0><2><5> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<0><2><6> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<0><2><7> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<0><3><0> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<0><3><1> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<0><3><2> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<0><3><3> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<0><3><4> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<0><3><5> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<0><3><6> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<0><3><7> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<1><0><0> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<1><0><1> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<1><0><2> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<1><0><3> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<1><0><4> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<1><0><5> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<1><0><6> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<1><0><7> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<1><1><0> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<1><1><1> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<1><1><2> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<1><1><3> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<1><1><4> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<1><1><5> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<1><1><6> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<1><1><7> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<1><2><0> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<1><2><1> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<1><2><2> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<1><2><3> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<1><2><4> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<1><2><5> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<1><2><6> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<1><2><7> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<1><3><0> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<1><3><1> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<1><3><2> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<1><3><3> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<1><3><4> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<1><3><5> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<1><3><6> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<1><3><7> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<2><0><0> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<2><0><1> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<2><0><2> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<2><0><3> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<2><0><4> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<2><0><5> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<2><0><6> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<2><0><7> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<2><1><0> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<2><1><1> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<2><1><2> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<2><1><3> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<2><1><4> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<2><1><5> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<2><1><6> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<2><1><7> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<2><2><0> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<2><2><1> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<2><2><2> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<2><2><3> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<2><2><4> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<2><2><5> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<2><2><6> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<2><2><7> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<2><3><0> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<2><3><1> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<2><3><2> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<2><3><3> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<2><3><4> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<2><3><5> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<2><3><6> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<2><3><7> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<3><0><0> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<3><0><1> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<3><0><2> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<3><0><3> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<3><0><4> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<3><0><5> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<3><0><6> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<3><0><7> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<3><1><0> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<3><1><1> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<3><1><2> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<3><1><3> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<3><1><4> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<3><1><5> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<3><1><6> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<3><1><7> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<3><2><0> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<3><2><1> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<3><2><2> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<3><2><3> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<3><2><4> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<3><2><5> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<3><2><6> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<3><2><7> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<3><3><0> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<3><3><1> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<3><3><2> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<3><3><3> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<3><3><4> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<3><3><5> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<3><3><6> | IOB | INPUT | LVCMOS25 | | | | | | |
| plaintext_i<3><3><7> | IOB | INPUT | LVCMOS25 | | | | | | |
| rst_i | IOB | INPUT | LVCMOS25 | | | | | | |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
 
Section 7 - RPMs
----------------
 
Section 8 - Guide Report
------------------------
Guide not run on this design.
 
Section 9 - Area Group and Partition Summary
--------------------------------------------
 
Partition Implementation Status
-------------------------------
 
No Partitions were found in this design.
 
-------------------------------
 
Area Group Information
----------------------
 
No area groups were found in this design.
 
----------------------
 
Section 10 - Modular Design Summary
-----------------------------------
Modular Design not used for this design.
 
Section 11 - Timing Report
--------------------------
A logic-level (pre-route) timing report can be generated by using Xilinx static
timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the
mapped NCD and PCF files. Please note that this timing report will be generated
using estimated delay information. For accurate numbers, please generate a
timing report with the post Place and Route NCD file.
 
For more information about the Timing Analyzer, consult the Xilinx Timing
Analyzer Reference Manual; for more information about TRCE, consult the Xilinx
Command Line Tools User Guide "TRACE" chapter.
 
Section 12 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings
 
Section 13 - Control Set Information
------------------------------------
Use the "-detail" map option to print out Control Set Information.
 
Section 14 - Utilization by Hierarchy
-------------------------------------
Use the "-detail" map option to print out the Utilization by Hierarchy section.
/aes_pipe/trunk/syn/Xilinx/log/aes.bld
0,0 → 1,36
Release 11.1 ngdbuild L.33 (lin)
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
 
Command Line: /opt/Xilinx/11.1/ISE/bin/lin/unwrapped/ngdbuild -dd ../out -uc
aes.ucf ../out/aes.ngc ../out/aes.ngd
 
Reading NGO file
"/home/subhasis/programming/vhdl/aes/pipe/trunk/syn/Xilinx/out/aes.ngc" ...
Gathering constraint information from source properties...
Done.
 
Applying constraints in "aes.ucf" to the design...
Resolving constraint associations...
Checking Constraint Associations...
Done...
 
Checking expanded design ...
 
Partition Implementation Status
-------------------------------
 
No Partitions were found in this design.
 
-------------------------------
 
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
 
Total memory usage is 125904 kilobytes
 
Writing NGD file "../out/aes.ngd" ...
Total REAL time to NGDBUILD completion: 27 sec
Total CPU time to NGDBUILD completion: 25 sec
 
Writing NGDBUILD log file "../out/aes.bld"...
/aes_pipe/trunk/syn/Xilinx/log/aes.log
0,0 → 1,806
Release 11.1 - xst L.33 (lin)
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
-->
 
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT
 
 
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "aes.prj"
Input Format : vhdl
 
---- Target Parameters
Output File Name : "../out/aes.ngc"
Output Format : NGC
Target Device : xc5vlx50t-1ff1136
 
---- Source Options
Top Module Name : aes_top
Decoder Extraction : YES
Priority Encoder Extraction : YES
Automatic Register Balancing : NO
Resource Sharing : YES
 
---- Target Options
Pack IO Registers into IOBs : FALSE
 
---- General Options
Optimization Goal : area
Optimization Effort : 2
Global Optimization : ALLCLOCKNETS
RTL Output : YES
 
---- Other Options
hdl_compilation_order : USER
 
=========================================================================
 
 
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "/home/subhasis/programming/vhdl/aes/pipe/trunk/syn/Xilinx/run/../../../rtl/vhdl/aes_pkg.vhdl" in Library work.
Compiling vhdl file "/home/subhasis/programming/vhdl/aes/pipe/trunk/syn/Xilinx/run/../../../rtl/vhdl/mixcol.vhdl" in Library work.
Architecture rtl of Entity mixcol is up to date.
Compiling vhdl file "/home/subhasis/programming/vhdl/aes/pipe/trunk/syn/Xilinx/run/../../../rtl/vhdl/colmix.vhdl" in Library work.
Architecture rtl of Entity colmix is up to date.
Compiling vhdl file "/home/subhasis/programming/vhdl/aes/pipe/trunk/syn/Xilinx/run/../../../rtl/vhdl/sbox.vhdl" in Library work.
Architecture rtl of Entity sbox is up to date.
Compiling vhdl file "/home/subhasis/programming/vhdl/aes/pipe/trunk/syn/Xilinx/run/../../../rtl/vhdl/subsh.vhdl" in Library work.
Architecture rtl of Entity sboxshr is up to date.
Compiling vhdl file "/home/subhasis/programming/vhdl/aes/pipe/trunk/syn/Xilinx/run/../../../rtl/vhdl/keysched1.vhdl" in Library work.
Architecture rtl of Entity keysched1 is up to date.
Compiling vhdl file "/home/subhasis/programming/vhdl/aes/pipe/trunk/syn/Xilinx/run/../../../rtl/vhdl/addkey.vhdl" in Library work.
Architecture rtl of Entity addkey is up to date.
Compiling vhdl file "/home/subhasis/programming/vhdl/aes/pipe/trunk/syn/Xilinx/run/../../../rtl/vhdl/aes_top.vhdl" in Library work.
Architecture rtl of Entity aes_top is up to date.
 
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for entity <aes_top> in library <work> (architecture <rtl>).
 
Analyzing hierarchy for entity <addkey> in library <work> (architecture <rtl>).
 
Analyzing hierarchy for entity <sboxshr> in library <work> (architecture <rtl>).
 
Analyzing hierarchy for entity <colmix> in library <work> (architecture <rtl>).
 
Analyzing hierarchy for entity <keysched1> in library <work> (architecture <rtl>).
 
Analyzing hierarchy for entity <sbox> in library <work> (architecture <rtl>).
 
Analyzing hierarchy for entity <mixcol> in library <work> (architecture <rtl>).
 
 
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <aes_top> in library <work> (Architecture <rtl>).
WARNING:Xst:753 - "/home/subhasis/programming/vhdl/aes/pipe/trunk/syn/Xilinx/run/../../../rtl/vhdl/aes_top.vhdl" line 192: Unconnected output port 'fc3' of component 'addkey'.
WARNING:Xst:753 - "/home/subhasis/programming/vhdl/aes/pipe/trunk/syn/Xilinx/run/../../../rtl/vhdl/aes_top.vhdl" line 192: Unconnected output port 'c0' of component 'addkey'.
WARNING:Xst:753 - "/home/subhasis/programming/vhdl/aes/pipe/trunk/syn/Xilinx/run/../../../rtl/vhdl/aes_top.vhdl" line 192: Unconnected output port 'c1' of component 'addkey'.
WARNING:Xst:753 - "/home/subhasis/programming/vhdl/aes/pipe/trunk/syn/Xilinx/run/../../../rtl/vhdl/aes_top.vhdl" line 192: Unconnected output port 'c2' of component 'addkey'.
WARNING:Xst:753 - "/home/subhasis/programming/vhdl/aes/pipe/trunk/syn/Xilinx/run/../../../rtl/vhdl/aes_top.vhdl" line 192: Unconnected output port 'c3' of component 'addkey'.
Entity <aes_top> analyzed. Unit <aes_top> generated.
 
Analyzing Entity <addkey> in library <work> (Architecture <rtl>).
Entity <addkey> analyzed. Unit <addkey> generated.
 
Analyzing Entity <keysched1> in library <work> (Architecture <rtl>).
Entity <keysched1> analyzed. Unit <keysched1> generated.
 
Analyzing Entity <sbox> in library <work> (Architecture <rtl>).
Entity <sbox> analyzed. Unit <sbox> generated.
 
Analyzing Entity <sboxshr> in library <work> (Architecture <rtl>).
Entity <sboxshr> analyzed. Unit <sboxshr> generated.
 
Analyzing Entity <colmix> in library <work> (Architecture <rtl>).
Entity <colmix> analyzed. Unit <colmix> generated.
 
Analyzing Entity <mixcol> in library <work> (Architecture <rtl>).
Entity <mixcol> analyzed. Unit <mixcol> generated.
 
 
=========================================================================
* HDL Synthesis *
=========================================================================
 
Performing bidirectional port resolution...
 
Synthesizing Unit <sbox>.
Related source file is "/home/subhasis/programming/vhdl/aes/pipe/trunk/syn/Xilinx/run/../../../rtl/vhdl/sbox.vhdl".
Found 256x8-bit ROM for signal <byteout$rom0000> created at line 106.
Found 8-bit register for signal <byteout>.
Summary:
inferred 1 ROM(s).
inferred 8 D-type flip-flop(s).
Unit <sbox> synthesized.
 
 
Synthesizing Unit <mixcol>.
Related source file is "/home/subhasis/programming/vhdl/aes/pipe/trunk/syn/Xilinx/run/../../../rtl/vhdl/mixcol.vhdl".
Found 8-bit register for signal <out0>.
Found 8-bit register for signal <out1>.
Found 8-bit register for signal <out2>.
Found 8-bit register for signal <out3>.
Found 8-bit xor4 for signal <out0$xor0000> created at line 137.
Found 8-bit xor4 for signal <out1$xor0000> created at line 138.
Found 8-bit xor4 for signal <out2$xor0000> created at line 139.
Found 8-bit xor4 for signal <out3$xor0000> created at line 140.
Found 8-bit xor4 for signal <xored>.
Summary:
inferred 32 D-type flip-flop(s).
inferred 40 Xor(s).
Unit <mixcol> synthesized.
 
 
Synthesizing Unit <sboxshr>.
Related source file is "/home/subhasis/programming/vhdl/aes/pipe/trunk/syn/Xilinx/run/../../../rtl/vhdl/subsh.vhdl".
Found 32-bit register for signal <nextkey<0>>.
Found 32-bit register for signal <nextkey<1>>.
Found 32-bit register for signal <nextkey<2>>.
Found 32-bit register for signal <nextkey<3>>.
Found 8-bit xor2 for signal <nextkey<0>_0$xor0000> created at line 118.
Found 8-bit xor2 for signal <nextkey<0>_1$xor0000> created at line 119.
Found 8-bit xor2 for signal <nextkey<0>_2$xor0000> created at line 120.
Found 8-bit xor2 for signal <nextkey<0>_3$xor0000> created at line 121.
Found 8-bit xor2 for signal <nextkey<1>_0$xor0000> created at line 118.
Found 8-bit xor2 for signal <nextkey<1>_1$xor0000> created at line 119.
Found 8-bit xor2 for signal <nextkey<1>_2$xor0000> created at line 120.
Found 8-bit xor2 for signal <nextkey<1>_3$xor0000> created at line 121.
Found 8-bit xor2 for signal <nextkey<2>_0$xor0000> created at line 118.
Found 8-bit xor2 for signal <nextkey<2>_1$xor0000> created at line 119.
Found 8-bit xor2 for signal <nextkey<2>_2$xor0000> created at line 120.
Found 8-bit xor2 for signal <nextkey<2>_3$xor0000> created at line 121.
Found 8-bit xor2 for signal <nextkey<3>_0$xor0000> created at line 118.
Found 8-bit xor2 for signal <nextkey<3>_1$xor0000> created at line 119.
Found 8-bit xor2 for signal <nextkey<3>_2$xor0000> created at line 120.
Found 8-bit xor2 for signal <nextkey<3>_3$xor0000> created at line 121.
Summary:
inferred 128 D-type flip-flop(s).
Unit <sboxshr> synthesized.
 
 
Synthesizing Unit <colmix>.
Related source file is "/home/subhasis/programming/vhdl/aes/pipe/trunk/syn/Xilinx/run/../../../rtl/vhdl/colmix.vhdl".
Found 32-bit register for signal <outrkey<0>>.
Found 32-bit register for signal <outrkey<1>>.
Found 32-bit register for signal <outrkey<2>>.
Found 32-bit register for signal <outrkey<3>>.
Summary:
inferred 128 D-type flip-flop(s).
Unit <colmix> synthesized.
 
 
Synthesizing Unit <keysched1>.
Related source file is "/home/subhasis/programming/vhdl/aes/pipe/trunk/syn/Xilinx/run/../../../rtl/vhdl/keysched1.vhdl".
WARNING:Xst:1780 - Signal <key3> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <key2> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <key1> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <key0> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
Found 32-bit register for signal <c3>.
Found 8-bit xor2 for signal <fc3<0>>.
Found 32-bit register for signal <c0>.
Found 32-bit register for signal <c1>.
Found 32-bit register for signal <c2>.
Found 8-bit xor2 for signal <c1_0$xor0000> created at line 138.
Found 8-bit xor2 for signal <c1_1$xor0000> created at line 138.
Found 8-bit xor2 for signal <c1_2$xor0000> created at line 138.
Found 8-bit xor2 for signal <c1_3$xor0000> created at line 138.
Found 8-bit xor2 for signal <c2_0$xor0000> created at line 139.
Found 8-bit xor2 for signal <c2_1$xor0000> created at line 139.
Found 8-bit xor2 for signal <c2_2$xor0000> created at line 139.
Found 8-bit xor2 for signal <c2_3$xor0000> created at line 139.
Found 8-bit xor3 for signal <c3_0$xor0000> created at line 140.
Found 8-bit xor3 for signal <c3_1$xor0000> created at line 140.
Found 8-bit xor2 for signal <c3_2$xor0000> created at line 140.
Found 8-bit xor2 for signal <c3_3$xor0000> created at line 140.
Found 8-bit register for signal <rcon_d>.
Summary:
inferred 136 D-type flip-flop(s).
inferred 16 Xor(s).
Unit <keysched1> synthesized.
 
 
Synthesizing Unit <addkey>.
Related source file is "/home/subhasis/programming/vhdl/aes/pipe/trunk/syn/Xilinx/run/../../../rtl/vhdl/addkey.vhdl".
Found 32-bit register for signal <dataout<0>>.
Found 32-bit register for signal <dataout<1>>.
Found 32-bit register for signal <dataout<2>>.
Found 32-bit register for signal <dataout<3>>.
Found 32-bit xor2 for signal <added<0>>.
Found 32-bit xor2 for signal <added<1>>.
Found 32-bit xor2 for signal <added<2>>.
Found 32-bit xor2 for signal <added<3>>.
Summary:
inferred 128 D-type flip-flop(s).
Unit <addkey> synthesized.
 
 
Synthesizing Unit <aes_top>.
Related source file is "/home/subhasis/programming/vhdl/aes/pipe/trunk/syn/Xilinx/run/../../../rtl/vhdl/aes_top.vhdl".
WARNING:Xst:1780 - Signal <textnet_s_m<9><3>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <textnet_s_m<9><2>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <textnet_s_m<9><1>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <textnet_s_m<9><0>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
Unit <aes_top> synthesized.
 
 
=========================================================================
HDL Synthesis Report
 
Macro Statistics
# ROMs : 204
256x8-bit ROM : 204
# Registers : 1015
8-bit register : 1015
# Xors : 659
8-bit xor2 : 457
8-bit xor3 : 22
8-bit xor4 : 180
 
=========================================================================
 
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
 
WARNING:Xst:1290 - Hierarchical block <step1> is unconnected in block <add_f>.
It will be removed from the design.
WARNING:Xst:1710 - FF/Latch <rcon_d_0> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_1> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_2> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_4> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_5> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_6> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_7> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_0> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_1> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_3> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_4> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_5> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_6> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_7> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_0> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_2> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_3> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_4> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_5> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_6> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_7> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_1> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_2> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_3> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_4> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_5> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_6> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_7> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_0> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_3> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_6> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_7> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_2> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_5> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_6> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_7> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_0> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_1> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_2> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_3> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_4> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_5> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_6> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_0> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_1> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_2> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_3> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_4> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_5> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_7> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_0> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_1> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_2> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_3> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_4> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_6> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_7> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_0> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_1> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_2> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_3> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_5> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_6> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rcon_d_7> (without init value) has a constant value of 0 in block <step1>. This FF/Latch will be trimmed during the optimization process.
 
=========================================================================
Advanced HDL Synthesis Report
 
Macro Statistics
# ROMs : 204
256x8-bit ROM : 204
# Registers : 8120
Flip-Flops : 8120
# Xors : 659
8-bit xor2 : 457
8-bit xor3 : 22
8-bit xor4 : 180
 
=========================================================================
 
=========================================================================
* Low Level Synthesis *
=========================================================================
 
Optimizing unit <aes_top> ...
 
Optimizing unit <sbox> ...
 
Optimizing unit <mixcol> ...
 
Optimizing unit <sboxshr> ...
 
Optimizing unit <colmix> ...
 
Optimizing unit <keysched1> ...
 
Optimizing unit <addkey> ...
WARNING:Xst:1710 - FF/Latch <proc[4].add/step1/rcon_d_0> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[4].add/step1/rcon_d_1> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[4].add/step1/rcon_d_2> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[4].add/step1/rcon_d_3> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[4].add/step1/rcon_d_5> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[4].add/step1/rcon_d_6> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[4].add/step1/rcon_d_7> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[5].add/step1/rcon_d_0> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[5].add/step1/rcon_d_1> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[5].add/step1/rcon_d_2> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[5].add/step1/rcon_d_3> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[5].add/step1/rcon_d_4> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[5].add/step1/rcon_d_6> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[5].add/step1/rcon_d_7> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[6].add/step1/rcon_d_0> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[6].add/step1/rcon_d_1> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[6].add/step1/rcon_d_2> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[6].add/step1/rcon_d_3> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[6].add/step1/rcon_d_4> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[6].add/step1/rcon_d_5> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[6].add/step1/rcon_d_7> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[7].add/step1/rcon_d_0> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[7].add/step1/rcon_d_1> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[7].add/step1/rcon_d_2> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[7].add/step1/rcon_d_3> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[7].add/step1/rcon_d_4> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[7].add/step1/rcon_d_5> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[7].add/step1/rcon_d_6> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[8].add/step1/rcon_d_2> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[8].add/step1/rcon_d_5> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[8].add/step1/rcon_d_6> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[8].add/step1/rcon_d_7> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <add_f_1/step1/rcon_d_0> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <add_f_1/step1/rcon_d_3> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <add_f_1/step1/rcon_d_6> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <add_f_1/step1/rcon_d_7> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[0].add/step1/rcon_d_1> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[0].add/step1/rcon_d_2> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[0].add/step1/rcon_d_3> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[0].add/step1/rcon_d_4> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[0].add/step1/rcon_d_5> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[0].add/step1/rcon_d_6> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[0].add/step1/rcon_d_7> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[1].add/step1/rcon_d_0> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[1].add/step1/rcon_d_2> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[1].add/step1/rcon_d_3> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[1].add/step1/rcon_d_4> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[1].add/step1/rcon_d_5> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[1].add/step1/rcon_d_6> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[1].add/step1/rcon_d_7> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[2].add/step1/rcon_d_0> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[2].add/step1/rcon_d_1> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[2].add/step1/rcon_d_3> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[2].add/step1/rcon_d_4> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[2].add/step1/rcon_d_5> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[2].add/step1/rcon_d_6> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[2].add/step1/rcon_d_7> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[3].add/step1/rcon_d_0> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[3].add/step1/rcon_d_1> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[3].add/step1/rcon_d_2> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[3].add/step1/rcon_d_4> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[3].add/step1/rcon_d_5> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[3].add/step1/rcon_d_6> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <proc[3].add/step1/rcon_d_7> (without init value) has a constant value of 0 in block <aes_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <add_f/step1/c0_0_0> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c0_0_1> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c0_0_2> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c0_0_3> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c0_0_4> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c0_0_5> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c0_0_6> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c0_0_7> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c0_1_0> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c0_1_1> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c0_1_2> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c0_1_3> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c0_1_4> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c0_1_5> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c0_1_6> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c0_1_7> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c0_2_0> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c0_2_1> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c0_2_2> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c0_2_3> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c0_2_4> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c0_2_5> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c0_2_6> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c0_2_7> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c0_3_0> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c0_3_1> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c0_3_2> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c0_3_3> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c0_3_4> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c0_3_5> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c0_3_6> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c0_3_7> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/rcon_d_0> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/rcon_d_1> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/rcon_d_2> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/rcon_d_3> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/rcon_d_4> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/rcon_d_5> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/rcon_d_6> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/rcon_d_7> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c1_0_0> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c1_0_1> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c1_0_2> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c1_0_3> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c1_0_4> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c1_0_5> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c1_0_6> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c1_0_7> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c1_1_0> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c1_1_1> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c1_1_2> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c1_1_3> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c1_1_4> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c1_1_5> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c1_1_6> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c1_1_7> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c1_2_0> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c1_2_1> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c1_2_2> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c1_2_3> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c1_2_4> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c1_2_5> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c1_2_6> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c1_2_7> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c1_3_0> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c1_3_1> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c1_3_2> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c1_3_3> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c1_3_4> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c1_3_5> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c1_3_6> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c1_3_7> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c2_0_0> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c2_0_1> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c2_0_2> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c2_0_3> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c2_0_4> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c2_0_5> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c2_0_6> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c2_0_7> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c2_1_0> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c2_1_1> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c2_1_2> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c2_1_3> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c2_1_4> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c2_1_5> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c2_1_6> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c2_1_7> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c2_2_0> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c2_2_1> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c2_2_2> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c2_2_3> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c2_2_4> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c2_2_5> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c2_2_6> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c2_2_7> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c2_3_0> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c2_3_1> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c2_3_2> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c2_3_3> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c2_3_4> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c2_3_5> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c2_3_6> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c2_3_7> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c3_0_0> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c3_0_1> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c3_0_2> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c3_0_3> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c3_0_4> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c3_0_5> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c3_0_6> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c3_0_7> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c3_1_0> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c3_1_1> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c3_1_2> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c3_1_3> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c3_1_4> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c3_1_5> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c3_1_6> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c3_1_7> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c3_2_0> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c3_2_1> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c3_2_2> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c3_2_3> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c3_2_4> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c3_2_5> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c3_2_6> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c3_2_7> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c3_3_0> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c3_3_1> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c3_3_2> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c3_3_3> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c3_3_4> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c3_3_5> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c3_3_6> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/c3_3_7> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/sub3/byteout_7> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/sub3/byteout_6> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/sub3/byteout_5> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/sub3/byteout_4> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/sub3/byteout_3> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/sub3/byteout_2> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/sub3/byteout_1> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/sub3/byteout_0> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/sub2/byteout_7> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/sub2/byteout_6> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/sub2/byteout_5> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/sub2/byteout_4> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/sub2/byteout_3> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/sub2/byteout_2> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/sub2/byteout_1> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/sub2/byteout_0> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/sub1/byteout_7> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/sub1/byteout_6> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/sub1/byteout_5> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/sub1/byteout_4> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/sub1/byteout_3> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/sub1/byteout_2> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/sub1/byteout_1> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/sub1/byteout_0> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/sub0/byteout_7> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/sub0/byteout_6> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/sub0/byteout_5> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/sub0/byteout_4> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/sub0/byteout_3> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/sub0/byteout_2> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/sub0/byteout_1> of sequential type is unconnected in block <aes_top>.
WARNING:Xst:2677 - Node <add_f/step1/sub0/byteout_0> of sequential type is unconnected in block <aes_top>.
 
Mapping all equations...
Building and optimizing final netlist ...
INFO:Xst:2261 - The FF/Latch <add_f_1/step1/rcon_d_1> in Unit <aes_top> is equivalent to the following 15 FFs/Latches, which will be removed : <add_f_1/step1/rcon_d_2> <add_f_1/step1/rcon_d_4> <add_f_1/step1/rcon_d_5> <proc[0].add/step1/rcon_d_0> <proc[1].add/step1/rcon_d_1> <proc[2].add/step1/rcon_d_2> <proc[3].add/step1/rcon_d_3> <proc[4].add/step1/rcon_d_4> <proc[5].add/step1/rcon_d_5> <proc[6].add/step1/rcon_d_6> <proc[7].add/step1/rcon_d_7> <proc[8].add/step1/rcon_d_0> <proc[8].add/step1/rcon_d_1> <proc[8].add/step1/rcon_d_3> <proc[8].add/step1/rcon_d_4>
 
Final Macro Processing ...
 
=========================================================================
Final Register Report
 
Macro Statistics
# Registers : 7873
Flip-Flops : 7873
 
=========================================================================
 
=========================================================================
* Partition Report *
=========================================================================
 
Partition Implementation Status
-------------------------------
 
No Partitions were found in this design.
 
-------------------------------
 
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : ../out/aes.ngr
Top Level Output File Name : ../out/aes.ngc
Output Format : NGC
Optimization Goal : area
Keep Hierarchy : no
 
Design Statistics
# IOs : 386
 
Cell Usage :
# BELS : 16541
# LUT2 : 3052
# LUT3 : 3584
# LUT4 : 320
# LUT5 : 720
# LUT6 : 7048
# MUXF7 : 216
# MUXF8 : 1600
# VCC : 1
# FlipFlops/Latches : 7873
# FDC : 7873
# Clock Buffers : 2
# BUFGP : 2
# IO Buffers : 384
# IBUF : 256
# OBUF : 128
=========================================================================
 
Device utilization summary:
---------------------------
 
Selected Device : 5vlx50tff1136-1
 
 
Slice Logic Utilization:
Number of Slice Registers: 7873 out of 28800 27%
Number of Slice LUTs: 14724 out of 28800 51%
Number used as Logic: 14724 out of 28800 51%
 
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 15770
Number with an unused Flip Flop: 7897 out of 15770 50%
Number with an unused LUT: 1046 out of 15770 6%
Number of fully used LUT-FF pairs: 6827 out of 15770 43%
Number of unique control sets: 1
 
IO Utilization:
Number of IOs: 386
Number of bonded IOBs: 386 out of 480 80%
 
Specific Feature Utilization:
Number of BUFG/BUFGCTRLs: 2 out of 32 6%
 
---------------------------
Partition Resource Summary:
---------------------------
 
No Partitions were found in this design.
 
---------------------------
 
 
=========================================================================
TIMING REPORT
 
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
 
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk_i | BUFGP | 7873 |
-----------------------------------+------------------------+-------+
 
Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------+------------------------+-------+
Control Signal | Buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
rst_i | BUFGP | 7873 |
-----------------------------------+------------------------+-------+
 
Timing Summary:
---------------
Speed Grade: -1
 
Minimum period: 2.614ns (Maximum Frequency: 382.604MHz)
Minimum input arrival time before clock: 2.961ns
Maximum output required time after clock: 3.259ns
Maximum combinational path delay: No path found
 
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
 
=========================================================================
Timing constraint: Default period analysis for Clock 'clk_i'
Clock period: 2.614ns (frequency: 382.604MHz)
Total number of paths / destination ports: 59472 / 7584
-------------------------------------------------------------------------
Delay: 2.614ns (Levels of Logic = 3)
Source: proc[8].mix/outrkey<3>_3_0 (FF)
Destination: add_f_1/step1/sub3/byteout_7 (FF)
Source Clock: clk_i rising
Destination Clock: clk_i rising
 
Data Path: proc[8].mix/outrkey<3>_3_0 to add_f_1/step1/sub3/byteout_7
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDC:C->Q 34 0.471 1.197 proc[8].mix/outrkey<3>_3_0 (proc[8].mix/outrkey<3>_3_0)
LUT6:I0->O 1 0.094 0.576 add_f_1/step1/sub3_Mrom_byteout_rom00004 (add_f_1/step1/sub3_Mrom_byteout_rom00003)
LUT3:I1->O 1 0.094 0.000 add_f_1/step1/sub3_Mrom_byteout_rom0000_f7_0 (add_f_1/step1/sub3_Mrom_byteout_rom0000_f71)
MUXF8:I0->O 1 0.182 0.000 add_f_1/step1/sub3_Mrom_byteout_rom0000_f8 (add_f_1/step1/sub3/byteout_rom0000<0>)
FDC:D -0.018 add_f_1/step1/sub3/byteout_0
----------------------------------------
Total 2.614ns (0.841ns logic, 1.773ns route)
(32.2% logic, 67.8% route)
 
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk_i'
Total number of paths / destination ports: 1440 / 288
-------------------------------------------------------------------------
Offset: 2.961ns (Levels of Logic = 4)
Source: keyblock_i<3><3><0> (PAD)
Destination: proc[0].add/step1/sub3/byteout_7 (FF)
Destination Clock: clk_i rising
 
Data Path: keyblock_i<3><3><0> to proc[0].add/step1/sub3/byteout_7
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 34 0.818 1.197 keyblock_i_3__3__0_IBUF (keyblock_i_3__3__0_IBUF)
LUT6:I0->O 1 0.094 0.576 proc[0].add/step1/sub3_Mrom_byteout_rom00004 (proc[0].add/step1/sub3_Mrom_byteout_rom00003)
LUT3:I1->O 1 0.094 0.000 proc[0].add/step1/sub3_Mrom_byteout_rom0000_f7_0 (proc[0].add/step1/sub3_Mrom_byteout_rom0000_f71)
MUXF8:I0->O 1 0.182 0.000 proc[0].add/step1/sub3_Mrom_byteout_rom0000_f8 (proc[0].add/step1/sub3/byteout_rom0000<0>)
FDC:D -0.018 proc[0].add/step1/sub3/byteout_0
----------------------------------------
Total 2.961ns (1.188ns logic, 1.773ns route)
(40.1% logic, 59.9% route)
 
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk_i'
Total number of paths / destination ports: 128 / 128
-------------------------------------------------------------------------
Offset: 3.259ns (Levels of Logic = 1)
Source: add_f/dataout<0>_3_7 (FF)
Destination: ciphertext_o<0><3><7> (PAD)
Source Clock: clk_i rising
 
Data Path: add_f/dataout<0>_3_7 to ciphertext_o<0><3><7>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDC:C->Q 1 0.471 0.336 add_f/dataout<0>_3_7 (add_f/dataout<0>_3_7)
OBUF:I->O 2.452 ciphertext_o_0__3__7_OBUF (ciphertext_o<0><3><7>)
----------------------------------------
Total 3.259ns (2.923ns logic, 0.336ns route)
(89.7% logic, 10.3% route)
 
=========================================================================
 
 
Total REAL time to Xst completion: 200.00 secs
Total CPU time to Xst completion: 197.33 secs
-->
 
 
Total memory usage is 242988 kilobytes
 
Number of errors : 0 ( 0 filtered)
Number of warnings : 310 ( 0 filtered)
Number of infos : 1 ( 0 filtered)
 
/aes_pipe/trunk/syn/Xilinx/log/aes_top_par.xrpt
0,0 → 1,8847
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="lin" product="ISE" version="11.1">
 
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
 
<application stringID="par" timeStamp="Thu Mar 25 14:31:21 2010">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
<item stringID="variable" value="XILINX_PLANAHEAD"/>
<item stringID="value" value="/opt/Xilinx/11.1/PlanAhead"/>
</row>
<row stringID="row" value="1">
<item stringID="variable" value="XILINX"/>
<item stringID="value" value="/opt/Xilinx/11.1/ISE"/>
</row>
<row stringID="row" value="2">
<item stringID="variable" value="XILINX_DSP"/>
<item stringID="value" value="/opt/Xilinx/11.1/DSP_Tools/lin"/>
</row>
</table>
<item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Ubuntu"/>
<item stringID="User_EnvOsrelease" value="Ubuntu 9.04"/>
</item>
<item stringID="User_EnvHost" value="blackpearl-laptop"/>
<table stringID="User_EnvCpu">
<column stringID="arch"/>
<column stringID="speed"/>
<row stringID="row" value="0">
<item stringID="arch" value="Intel(R) Core(TM)2 Duo CPU T5550 @ 1.83GHz"/>
<item stringID="speed" value="1333.000 MHz"/>
</row>
<row stringID="row" value="1">
<item stringID="arch" value="Intel(R) Core(TM)2 Duo CPU T5550 @ 1.83GHz"/>
<item stringID="speed" value="1000.000 MHz"/>
</row>
</table>
</section>
<task stringID="PAR_DEVICE_UTILIZATION">
<section label="Device Utilization Summary" stringID="PAR_DEVICE_UTLIZATION">
<item AVAILABLE="32" dataType="int" label="Number of BUFGs" stringID="PAR_BUFG" value="2"/>
<item AVAILABLE="480" dataType="int" label="Number of External IOBs" stringID="PAR_EXTERNAL_IOB" value="386">
<item AVAILABLE="386" dataType="int" label="Number of LOCed IOBs" stringID="PAR_LOC_IOB" value="0"/>
</item>
<item AVAILABLE="28800" dataType="int" label="Number of Slice Registers" stringID="PAR_SLICE_REGISTERS" value="7873">
<item dataType="int" label="Number used as Flip Flops" stringID="PAR_FLIP_FLOPS" value="7873"/>
<item dataType="int" label="Number used as Latches" stringID="PAR_LATCHES" value="0"/>
<item dataType="int" label="Number used as LatchThrus" stringID="PAR_LATCH_THRUS" value="0"/>
</item>
<item AVAILABLE="28800" dataType="int" label="Number of Slice LUTS" stringID="PAR_SLICE_LUTS" value="14724"/>
<item AVAILABLE="28800" dataType="int" label="Number of Slice LUT-Flip Flop pairs" stringID="PAR_SLICE_LUT_FLIPFLOP_PAIRS" value="15770"/>
</section>
</task>
<task stringID="PAR_PAR">
<section stringID="PAR_DESIGN_SUMMARY">
<item stringID="PAR_REAL_TIME_COMPLETION_ROUTER" value="5 mins 24 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_ROUTER" value="5 mins 13 secs "/>
<item dataType="int" stringID="PAR_UNROUTES" value="0"/>
<item dataType="float" stringID="PAR_TIMING_SCORE" value="0.000000"/>
<item stringID="PAR_REAL_TIME_COMPLETION_PAR" value="5 mins 42 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_PAR" value="5 mins 30 secs "/>
</section>
</task>
<task stringID="PAR_par">
<section stringID="PAR_DLY_CLK_REPORT"/>
<section stringID="PAR_CLOCK_REPORT">
<table stringID="PAR_CLOCK_TABLE">
<column label="Clock Net" stringID="CLOCK_NET"/>
<column label="Routed" stringID="ROUTED"/>
<column label="Resource" stringID="RESOURCE"/>
<column label="Locked" stringID="LOCKED"/>
<column label="Fanout" stringID="FANOUT"/>
<column label="Net Skew(ns)" stringID="NET_SKEW"/>
<column label="Max Delay(ns)" stringID="MAX_DELAY"/>
<row stringID="row" value="1">
<item label="Clock Net" stringID="CLOCK_NET" value="clk_i_BUFGP"/>
<item label="Routed" stringID="ROUTED" value="ROUTED"/>
<item label="Resource" stringID="RESOURCE" value="BUFGCTRL_X0Y1"/>
<item label="Locked" stringID="LOCKED" value="No"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="3403.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.334000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.843000"/>
</row>
</table>
</section>
<section stringID="PAR_PAD_PIN_REPORT">
<table stringID="PAR_PINOUT_BY_PIN_NUMBER">
<column label="Pin&#xA;Number" stringID="Pin_Number"/>
<column label="Signal&#xA;Name" stringID="Signal_Name"/>
<column label="Pin&#xA;Usage" stringID="Pin_Usage"/>
<column label="Pin&#xA;Name" stringID="Pin_Name"/>
<column label="Direction" stringID="Direction"/>
<column label="IO&#xA;Standard" stringID="IO_Standard"/>
<column label="IO Bank&#xA;Number" stringID="IO_Bank_Number"/>
<column label="Drive&#xA;(mA)" stringID="Drive"/>
<column label="Slew&#xA;Rate" stringID="Slew_Rate"/>
<column label="Termination" stringID="Termination"/>
<column label="IOB&#xA;Delay" stringID="IOB_Delay"/>
<column label="Voltage" stringID="Voltage"/>
<column label="Constraint" stringID="Constraint"/>
<column label="IO&#xA;Register" stringID="IO_Register"/>
<column label="Signal&#xA;Integrity" stringID="Signal_Integrity"/>
<row stringID="row" value="1">
<item label="Pin&#xA;Number" stringID="Pin_Number" value="A2"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IPAD"/>
<item label="Pin&#xA;Name" stringID="Pin_Name" value="MGTRXN0_120"/>
<item label="Direction" stringID="Direction" value="UNUSED"/>
</row>
<row stringID="row" value="2">
<item label="Pin&#xA;Number" stringID="Pin_Number" value="A3"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IPAD"/>
<item label="Pin&#xA;Name" stringID="Pin_Name" value="MGTRXP0_120"/>
<item label="Direction" stringID="Direction" value="UNUSED"/>
</row>
<row stringID="row" value="3">
<item label="Pin&#xA;Number" stringID="Pin_Number" value="A6"/>
<item label="Pin&#xA;Name" stringID="Pin_Name" value="NC"/>
</row>
<row stringID="row" value="4">
<item label="Pin&#xA;Number" stringID="Pin_Number" value="A7"/>
<item label="Pin&#xA;Name" stringID="Pin_Name" value="NC"/>
</row>
<row stringID="row" value="5">
<item label="Pin&#xA;Number" stringID="Pin_Number" value="A8"/>
<item label="Pin&#xA;Name" stringID="Pin_Name" value="NC"/>
</row>
<row stringID="row" value="6">
<item label="Pin&#xA;Number" stringID="Pin_Number" value="A9"/>
<item label="Pin&#xA;Name" stringID="Pin_Name" value="NC"/>
</row>
<row stringID="row" value="7">
<item label="Pin&#xA;Number" stringID="Pin_Number" value="A11"/>
<item label="Pin&#xA;Name" stringID="Pin_Name" value="GND"/>
</row>
<row stringID="row" value="8">
<item label="Pin&#xA;Number" stringID="Pin_Number" value="A12"/>
<item label="Pin&#xA;Name" stringID="Pin_Name" value="GND"/>
</row>
<row stringID="row" value="9">
<item label="Pin&#xA;Number" stringID="Pin_Number" value="A13"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBM"/>
<item label="Pin&#xA;Name" stringID="Pin_Name" value="IO_L8P_CC_20"/>
<item label="Direction" stringID="Direction" value="UNUSED"/>
<item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="20"/>
</row>
<row stringID="row" value="10">
<item label="Pin&#xA;Number" stringID="Pin_Number" value="A14"/>
<item label="Pin&#xA;Name" stringID="Pin_Name" value="NC"/>
</row>
<row stringID="row" value="11">
<item label="Pin&#xA;Number" stringID="Pin_Number" value="A15"/>
<item label="Pin&#xA;Name" stringID="Pin_Name" value="NC"/>
</row>
<row stringID="row" value="12">
<item label="Pin&#xA;Number" stringID="Pin_Number" value="A16"/>
<item label="Pin&#xA;Name" stringID="Pin_Name" value="NC"/>
</row>
<row stringID="row" value="13">
<item label="Pin&#xA;Number" stringID="Pin_Number" value="A17"/>
<item label="Pin&#xA;Name" stringID="Pin_Name" value="GND"/>
</row>
<row stringID="row" value="14">
<item label="Pin&#xA;Number" stringID="Pin_Number" value="A18"/>
<item label="Pin&#xA;Name" stringID="Pin_Name" value="NC"/>
</row>
<row stringID="row" value="15">
<item label="Pin&#xA;Number" stringID="Pin_Number" value="A19"/>
<item label="Pin&#xA;Name" stringID="Pin_Name" value="NC"/>
</row>
<row stringID="row" value="16">
<item label="Pin&#xA;Number" stringID="Pin_Number" value="A20"/>
<item label="Pin&#xA;Name" stringID="Pin_Name" value="NC"/>
</row>
<row stringID="row" value="17">
<item label="Pin&#xA;Number" stringID="Pin_Number" value="A21"/>
<item label="Pin&#xA;Name" stringID="Pin_Name" value="NC"/>
</row>
<row stringID="row" value="18">
<item label="Pin&#xA;Number" stringID="Pin_Number" value="A22"/>
<item label="Pin&#xA;Name" stringID="Pin_Name" value="GND"/>
</row>
<row stringID="row" value="19">
<item label="Pin&#xA;Number" stringID="Pin_Number" value="A23"/>
<item label="Pin&#xA;Name" stringID="Pin_Name" value="NC"/>
</row>
<row stringID="row" value="20">
<item label="Pin&#xA;Number" stringID="Pin_Number" value="A24"/>
<item label="Pin&#xA;Name" stringID="Pin_Name" value="NC"/>
</row>
<row stringID="row" value="21">
<item label="Pin&#xA;Number" stringID="Pin_Number" value="A25"/>
<item label="Pin&#xA;Name" stringID="Pin_Name" value="NC"/>
</row>
<row stringID="row" value="22">
<item label="Pin&#xA;Number" stringID="Pin_Number" value="A26"/>
<item label="Pin&#xA;Name" stringID="Pin_Name" value="NC"/>
</row>
<row stringID="row" value="23">
<item label="Pin&#xA;Number" stringID="Pin_Number" value="A27"/>
<item label="Pin&#xA;Name" stringID="Pin_Name" value="GND"/>
</row>
<row stringID="row" value="24">
<item label="Pin&#xA;Number" stringID="Pin_Number" value="A28"/>
<item label="Pin&#xA;Name" stringID="Pin_Name" value="NC"/>
</row>
<row stringID="row" value="25">
<item label="Pin&#xA;Number" stringID="Pin_Number" value="A29"/>
<item label="Pin&#xA;Name" stringID="Pin_Name" value="NC"/>
</row>
<row stringID="row" value="26">
<item label="Pin&#xA;Number" stringID="Pin_Number" value="A30"/>
<item label="Pin&#xA;Name" stringID="Pin_Name" value="NC"/>
</row>
<row stringID="row" value="27">
<item label="Pin&#xA;Number" stringID="Pin_Number" value="A31"/>
<item label="Pin&#xA;Name" stringID="Pin_Name" value="NC"/>
</row>
<row stringID="row" value="28">
<item label="Pin&#xA;Number" stringID="Pin_Number" value="A32"/>
<item label="Pin&#xA;Name" stringID="Pin_Name" value="GND"/>
</row>
<row stringID="row" value="29">
<item label="Pin&#xA;Number" stringID="Pin_Number" value="A33"/>
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<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
<item label="Pin&#xA;Name" stringID="Pin_Name" value="IO_L4P_13"/>
<item label="Direction" stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" stringID="IO_Standard" value="LVCMOS25*"/>
<item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="13"/>
<item label="Drive&#xA;(mA)" stringID="Drive" value="12"/>
<item label="Slew&#xA;Rate" stringID="Slew_Rate" value="SLOW"/>
<item label="Constraint" stringID="Constraint" value="UNLOCATED"/>
<item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
<item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
</row>
<row stringID="row" value="1135">
<item label="Pin&#xA;Number" stringID="Pin_Number" value="Y33"/>
<item label="Signal&#xA;Name" stringID="Signal_Name" value="ciphertext_o&lt;0>&lt;3>&lt;5>"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
<item label="Pin&#xA;Name" stringID="Pin_Name" value="IO_L2P_SM6P_13"/>
<item label="Direction" stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" stringID="IO_Standard" value="LVCMOS25*"/>
<item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="13"/>
<item label="Drive&#xA;(mA)" stringID="Drive" value="12"/>
<item label="Slew&#xA;Rate" stringID="Slew_Rate" value="SLOW"/>
<item label="Constraint" stringID="Constraint" value="UNLOCATED"/>
<item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
<item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
</row>
<row stringID="row" value="1136">
<item label="Pin&#xA;Number" stringID="Pin_Number" value="Y34"/>
<item label="Signal&#xA;Name" stringID="Signal_Name" value="ciphertext_o&lt;0>&lt;1>&lt;4>"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
<item label="Pin&#xA;Name" stringID="Pin_Name" value="IO_L3N_SM5N_13"/>
<item label="Direction" stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" stringID="IO_Standard" value="LVCMOS25*"/>
<item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="13"/>
<item label="Drive&#xA;(mA)" stringID="Drive" value="12"/>
<item label="Slew&#xA;Rate" stringID="Slew_Rate" value="SLOW"/>
<item label="Constraint" stringID="Constraint" value="UNLOCATED"/>
<item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
<item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
</row>
</table>
<table stringID="PAR_PSEUDO_LOGIC">
<column label="Signal&#xA;Name" stringID="Signal_Name"/>
<column stringID="Type"/>
<column stringID="Site"/>
</table>
</section>
<section stringID="PAR_UNROUTES_REPORT">
<item dataType="int" stringID="PAR_UNROUTED_NETS" value="0"/>
<item dataType="int" stringID="PAR_TOTAL_SOURCELESS_NETS" value="0"/>
<item dataType="int" stringID="PAR_TOTAL_LOADLESS_NETS" value="0"/>
</section>
</task>
</application>
 
</document>
/aes_pipe/trunk/syn/Xilinx/log/aes.twx
0,0 → 1,339
<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE twReport [
<!ELEMENT twReport (twHead?, (twWarn | twDebug | twInfo)*, twBody, twSum?,
twDebug*, twFoot?, twClientInfo?)>
<!ATTLIST twReport version CDATA "10,4">
<!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
<!ELEMENT twExecVer (#PCDATA)>
<!ELEMENT twCopyright (#PCDATA)>
<!ELEMENT twCmdLine (#PCDATA)>
<!ELEMENT twDesign (#PCDATA)>
<!ELEMENT twPCF (#PCDATA)>
<!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
<!ELEMENT twDevName (#PCDATA)>
<!ATTLIST twDevInfo arch CDATA #IMPLIED pkg CDATA #IMPLIED>
<!ELEMENT twSpeedGrade (#PCDATA)>
<!ELEMENT twSpeedVer (#PCDATA)>
<!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
<!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
<!ATTLIST twRptInfo twAdvRpt (TRUE | FALSE) "FALSE">
<!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
<!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
<!ATTLIST twRptInfo twReportMinPaths CDATA #IMPLIED>
<!ELEMENT twItemLimit (#PCDATA)>
<!ELEMENT twUnconst EMPTY>
<!ELEMENT twUnconstLimit (#PCDATA)>
<!ELEMENT twEnvVar EMPTY>
<!ATTLIST twEnvVar name CDATA #REQUIRED>
<!ATTLIST twEnvVar description CDATA #REQUIRED>
<!ELEMENT twWarn (#PCDATA)>
<!ELEMENT twInfo (#PCDATA)>
<!ELEMENT twDebug (#PCDATA)>
<!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
<!ATTLIST twBody twFastPaths CDATA #IMPLIED>
<!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
<!ELEMENT twProc (#PCDATA)>
<!ELEMENT twTemp (#PCDATA)>
<!ELEMENT twVolt (#PCDATA)>
<!ELEMENT twSumRpt (twConstRollupTable*, twConstList?, twConstSummaryTable?, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?)>
<!ELEMENT twErrRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
<!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
<!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
<!ELEMENT twCycles (twSigConn+)>
<!ATTLIST twCycles twNum CDATA #REQUIRED>
<!ELEMENT twSigConn (twSig, twDriver, twLoad)>
<!ELEMENT twSig (#PCDATA)>
<!ELEMENT twDriver (#PCDATA)>
<!ELEMENT twLoad (#PCDATA)>
<!ELEMENT twConst (twConstHead, ((twPathRpt?,twRacePathRpt?, twPathRptBanner?)* | (twPathRpt*, twRacePathRpt?) | twNetRpt* | twClkSkewLimit*))>
<!ATTLIST twConst twConstType (NET |
NETDELAY |
NETSKEW |
PATH |
DEFPERIOD |
UNCONSTPATH |
DEFPATH |
PATH2SETUP |
UNCONSTPATH2SETUP |
PATHCLASS |
PATHDELAY |
PERIOD |
FREQUENCY |
PATHBLOCK |
OFFSET |
OFFSETIN |
OFFSETINCLOCK |
UNCONSTOFFSETINCLOCK |
OFFSETINDELAY |
OFFSETINMOD |
OFFSETOUT |
OFFSETOUTCLOCK |
UNCONSTOFFSETOUTCLOCK |
OFFSETOUTDELAY |
OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED>
<!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntEndPt?, twErrCntHold,
twEndPtCnt?,
twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
<!ELEMENT twConstName (#PCDATA)>
<!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
<!ATTLIST twConstHead uID CDATA #IMPLIED>
<!ELEMENT twItemCnt (#PCDATA)>
<!ELEMENT twErrCnt (#PCDATA)>
<!ELEMENT twErrCntEndPt (#PCDATA)>
<!ELEMENT twErrCntSetup (#PCDATA)>
<!ELEMENT twErrCntHold (#PCDATA)>
<!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
<!ELEMENT twEndPtCnt (#PCDATA)>
<!ELEMENT twPathErrCnt (#PCDATA)>
<!ELEMENT twMinPer (#PCDATA) >
<!ELEMENT twFootnote EMPTY>
<!ATTLIST twFootnote number CDATA #REQUIRED>
<!ELEMENT twMaxDel (#PCDATA)>
<!ELEMENT twMaxFreq (#PCDATA)>
<!ELEMENT twMinOff (#PCDATA)>
<!ELEMENT twMaxOff (#PCDATA)>
<!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
<!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
<!ELEMENT twTIGName (#PCDATA)>
<!ELEMENT twInstantiated (#PCDATA)>
<!ELEMENT twBlocked (#PCDATA)>
<!ELEMENT twRacePathRpt (twRacePath+)>
<!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
<!ELEMENT twUnconstPath (twTotDel, twSrc, twDest, (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
<!ATTLIST twUnconstPath twDataPathType CDATA #IMPLIED
twSimpleMinPath CDATA #IMPLIED>
<!ELEMENT twTotDel (#PCDATA)>
<!ELEMENT twSrc (#PCDATA)>
<!ATTLIST twSrc BELType CDATA #IMPLIED>
<!ELEMENT twDest (#PCDATA)>
<!ATTLIST twDest BELType CDATA #IMPLIED>
<!ELEMENT twDel (#PCDATA)>
<!ELEMENT twSUTime (#PCDATA)>
<!ELEMENT twTotPathDel (#PCDATA)>
<!ELEMENT twClkSkew (#PCDATA)>
<!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
<!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
<!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
<!ELEMENT twSlack (#PCDATA)>
<!ELEMENT twDelConst (#PCDATA)>
<!ELEMENT tw2Phase EMPTY>
<!ELEMENT twClkUncert (#PCDATA)>
<!ATTLIST twClkUncert fSysJit CDATA #IMPLIED fInputJit CDATA #IMPLIED
fDCMJit CDATA #IMPLIED
fPhaseErr CDATA #IMPLIED
sEqu CDATA #IMPLIED>
<!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
<!ELEMENT twPathRptBanner (#PCDATA)>
<!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
<!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
<!ELEMENT twOff (#PCDATA)>
<!ELEMENT twGuaranteed EMPTY>
<!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
<!ELEMENT twClkDel (#PCDATA)>
<!ELEMENT twClkSrc (#PCDATA)>
<!ELEMENT twClkDest (#PCDATA)>
<!ELEMENT twGuarInSetup (#PCDATA)>
<!ELEMENT twOffSrc (#PCDATA)>
<!ELEMENT twOffDest (#PCDATA)>
<!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
<!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
<!ELEMENT twDataDel (#PCDATA)>
<!ELEMENT twDataSrc (#PCDATA)>
<!ELEMENT twDataDest (#PCDATA)>
<!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
<!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twLogLvls (#PCDATA)>
<!ELEMENT twSrcSite (#PCDATA)>
<!ELEMENT twSrcClk (#PCDATA)>
<!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
<!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
<!ELEMENT twDelInfo (#PCDATA)>
<!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twSite (#PCDATA)>
<!ELEMENT twDelType (#PCDATA)>
<!ELEMENT twFanCnt (#PCDATA)>
<!ELEMENT twComp (#PCDATA)>
<!ELEMENT twNet (#PCDATA)>
<!ELEMENT twBEL (#PCDATA)>
<!ELEMENT twLogDel (#PCDATA)>
<!ELEMENT twRouteDel (#PCDATA)>
<!ELEMENT twDestClk (#PCDATA)>
<!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPctLog (#PCDATA)>
<!ELEMENT twPctRoute (#PCDATA)>
<!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
<!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
<!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
<!ELEMENT twTimeConst (#PCDATA)>
<!ELEMENT twAbsSlack (#PCDATA)>
<!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
<!ELEMENT twSkew (#PCDATA)>
<!ELEMENT twDetNet (twNetDel*)>
<!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
<!ELEMENT twNetDelInfo (#PCDATA)>
<!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twDetSkewNet (twNetSkew*)>
<!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
<!ELEMENT twClkSkewLimit EMPTY>
<!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED arrv1 CDATA #IMPLIED
arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
<!ELEMENT twConstRollupTable (twConstRollup*)>
<!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
<!ELEMENT twConstRollup EMPTY>
<!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
<!ATTLIST twConstRollup actualRollup CDATA #IMPLIED errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED itemsRollup CDATA #IMPLIED>
<!ELEMENT twConstList (twConstListItem)*>
<!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)>
<!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
<!ELEMENT twNotMet EMPTY>
<!ELEMENT twReqVal (#PCDATA)>
<!ELEMENT twActVal (#PCDATA)>
<!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
<!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
<!ELEMENT twConstStats (twConstName)>
<!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
<!ATTLIST twConstStats twRequired CDATA #IMPLIED>
<!ATTLIST twConstStats twActual CDATA #IMPLIED>
<!ATTLIST twConstStats twSlack CDATA #IMPLIED>
<!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
<!ATTLIST twConstStats twErrors CDATA #IMPLIED>
<!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twTCType CDATA #IMPLIED>
<!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
<!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED slackIndex CDATA #IMPLIED>
<!ELEMENT twConstData EMPTY>
<!ATTLIST twConstData type CDATA #IMPLIED units (MHz | ns) "ns" slack CDATA #IMPLIED
best CDATA #IMPLIED requested CDATA #IMPLIED
errors CDATA #IMPLIED
score CDATA #IMPLIED>
<!ELEMENT twTimeGrpRpt (twTimeGrp)*>
<!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
<!ELEMENT twTimeGrpName (#PCDATA)>
<!ELEMENT twCompList (twCompName+)>
<!ELEMENT twCompName (#PCDATA)>
<!ELEMENT twSigList (twSigName+)>
<!ELEMENT twSigName (#PCDATA)>
<!ELEMENT twBELList (twBELName+)>
<!ELEMENT twBELName (#PCDATA)>
<!ELEMENT twBlockList (twBlockName+)>
<!ELEMENT twBlockName (#PCDATA)>
<!ELEMENT twMacList (twMacName+)>
<!ELEMENT twMacName (#PCDATA)>
<!ELEMENT twPinList (twPinName+)>
<!ELEMENT twPinName (#PCDATA)>
<!ELEMENT twUnmetConstCnt (#PCDATA)>
<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)>
<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
<!ELEMENT twSU2ClkTime (#PCDATA)>
<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twH2ClkTime (#PCDATA)>
<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
<!ELEMENT twClk2Pad (twDest, twTime)>
<!ELEMENT twTime (#PCDATA)>
<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
<!ELEMENT twClk2Out EMPTY>
<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
<!ELEMENT twRiseRise (#PCDATA)>
<!ELEMENT twFallRise (#PCDATA)>
<!ELEMENT twRiseFall (#PCDATA)>
<!ELEMENT twFallFall (#PCDATA)>
<!ELEMENT twPad2PadList (twPad2Pad+)>
<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
<!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>
<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED twHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffOutTblRow EMPTY>
<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
<!ELEMENT twNonDedClk (#PCDATA)>
<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
<!ELEMENT twScore (#PCDATA)>
<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
<!ELEMENT twPathCnt (#PCDATA)>
<!ELEMENT twNetCnt (#PCDATA)>
<!ELEMENT twConnCnt (#PCDATA)>
<!ELEMENT twPct (#PCDATA)>
<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
<!ELEMENT twMaxCombDel (#PCDATA)>
<!ELEMENT twMaxFromToDel (#PCDATA)>
<!ELEMENT twMaxNetDel (#PCDATA)>
<!ELEMENT twMaxNetSkew (#PCDATA)>
<!ELEMENT twMaxInAfterClk (#PCDATA)>
<!ELEMENT twMinInBeforeClk (#PCDATA)>
<!ELEMENT twMaxOutBeforeClk (#PCDATA)>
<!ELEMENT twMinOutAfterClk (#PCDATA)>
<!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
<!ELEMENT twTimestamp (#PCDATA)>
<!ELEMENT twFootnoteExplanation EMPTY>
<!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
<!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
<!ELEMENT twClientInfo (twClientName, twAttrList?)>
<!ELEMENT twClientName (#PCDATA)>
<!ELEMENT twAttrList (twAttrListItem)*>
<!ELEMENT twAttrListItem (twName, twValue*)>
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twHead anchorID="1"><twExecVer>Release 11.1 Trace (lin)</twExecVer><twCopyright>Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.</twCopyright><twCmdLine>/opt/Xilinx/11.1/ISE/bin/lin/unwrapped/trce -v 10 -fastpaths -xml
../log/aes.twx ../out/aes.map.ncd -o ../log/aes.twr ../out/aes.pcf
 
</twCmdLine><twDesign>aes.map.ncd</twDesign><twDesignPath>../out/aes.map.ncd</twDesignPath><twPCF>aes.pcf</twPCF><twPcfPath>../out/aes.pcf</twPcfPath><twDevInfo arch="virtex5" pkg="ff1136"><twDevName>xc5vlx50t</twDevName><twSpeedGrade>-1</twSpeedGrade><twSpeedVer>PRODUCTION 1.64 2009-03-03, STEPPING level 0</twSpeedVer></twDevInfo><twRptInfo twRptLvl="twVerbose" twReportMinPaths="true" dlyHyperLnks="t" ><twItemLimit>10</twItemLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo anchorID="3">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twBody><twVerboseRpt><twConst anchorID="4" twConstType="PERIOD" ><twConstHead uID="1"><twConstName UCFConstName="" ScopeName="">TS_clk = PERIOD TIMEGRP &quot;clk_i&quot; 3 ns HIGH 50%;</twConstName><twItemCnt>59472</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>27896</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>2.974</twMinPer></twConstHead><twPathRpt anchorID="5"><twConstPath anchorID="6" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.026</twSlack><twSrc BELType="FF">proc[0].mix/outrkey&lt;2&gt;_1_5</twSrc><twDest BELType="FF">proc[1].add/dataout&lt;2&gt;_1_5</twDest><twTotPathDel>2.793</twTotPathDel><twClkSkew dest = "1.244" src = "1.390">0.146</twClkSkew><twDelConst>3.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="17"><twSrc BELType='FF'>proc[0].mix/outrkey&lt;2&gt;_1_5</twSrc><twDest BELType='FF'>proc[1].add/dataout&lt;2&gt;_1_5</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X20Y103.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">clk_i_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X20Y103.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.471</twDelInfo><twComp>proc[0].mix/outrkey&lt;2&gt;_1_7</twComp><twBEL>proc[0].mix/outrkey&lt;2&gt;_1_5</twBEL></twPathDel><twPathDel><twSite>SLICE_X47Y110.B6</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">2.295</twDelInfo><twComp>proc[0].mix/outrkey&lt;2&gt;_1_5</twComp></twPathDel><twPathDel><twSite>SLICE_X47Y110.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.027</twDelInfo><twComp>proc[1].add/dataout&lt;2&gt;_1_7</twComp><twBEL>proc[1].add/Mxor_added&lt;2&gt;&lt;1&gt;_Result&lt;5&gt;1</twBEL><twBEL>proc[1].add/dataout&lt;2&gt;_1_5</twBEL></twPathDel><twLogDel>0.498</twLogDel><twRouteDel>2.295</twRouteDel><twTotDel>2.793</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="3.000">clk_i_BUFGP</twDestClk><twPctLog>17.8</twPctLog><twPctRoute>82.2</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="7"><twConstPath anchorID="8" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.026</twSlack><twSrc BELType="FF">add_f_1/dataout&lt;1&gt;_1_1</twSrc><twDest BELType="FF">sbox_f_1/g0[1].g1[1].sub/byteout_5</twDest><twTotPathDel>2.850</twTotPathDel><twClkSkew dest = "1.226" src = "1.315">0.089</twClkSkew><twDelConst>3.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16"><twSrc BELType='FF'>add_f_1/dataout&lt;1&gt;_1_1</twSrc><twDest BELType='FF'>sbox_f_1/g0[1].g1[1].sub/byteout_5</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X52Y59.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">clk_i_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X52Y59.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.471</twDelInfo><twComp>add_f_1/dataout&lt;1&gt;_1_3</twComp><twBEL>add_f_1/dataout&lt;1&gt;_1_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X59Y62.C1</twSite><twDelType>net</twDelType><twFanCnt>32</twFanCnt><twDelInfo twEdge="twRising">1.538</twDelInfo><twComp>add_f_1/dataout&lt;1&gt;_1_1</twComp></twPathDel><twPathDel><twSite>SLICE_X59Y62.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.094</twDelInfo><twComp>sbox_f_1/g0[2].g1[0].sub_Mrom_byteout_rom000022</twComp><twBEL>sbox_f_1/g0[1].g1[1].sub_Mrom_byteout_rom0000101</twBEL></twPathDel><twPathDel><twSite>SLICE_X56Y61.B5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.546</twDelInfo><twComp>sbox_f_1/g0[1].g1[1].sub_Mrom_byteout_rom0000101</twComp></twPathDel><twPathDel><twSite>SLICE_X56Y61.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.201</twDelInfo><twComp>sbox_f_1/g0[1].g1[1].sub/byteout&lt;5&gt;</twComp><twBEL>sbox_f_1/g0[1].g1[1].sub_Mrom_byteout_rom000010_f7</twBEL><twBEL>sbox_f_1/g0[1].g1[1].sub_Mrom_byteout_rom000010_f7_rt</twBEL><twBEL>sbox_f_1/g0[1].g1[1].sub_Mrom_byteout_rom000010_f8</twBEL><twBEL>sbox_f_1/g0[1].g1[1].sub/byteout_5</twBEL></twPathDel><twLogDel>0.766</twLogDel><twRouteDel>2.084</twRouteDel><twTotDel>2.850</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="3.000">clk_i_BUFGP</twDestClk><twPctLog>26.9</twPctLog><twPctRoute>73.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="9"><twConstPath anchorID="10" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.027</twSlack><twSrc BELType="FF">proc[3].add/dataout&lt;3&gt;_1_4</twSrc><twDest BELType="FF">proc[3].sbox/g0[3].g1[1].sub/byteout_4</twDest><twTotPathDel>2.814</twTotPathDel><twClkSkew dest = "1.168" src = "1.292">0.124</twClkSkew><twDelConst>3.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16"><twSrc BELType='FF'>proc[3].add/dataout&lt;3&gt;_1_4</twSrc><twDest BELType='FF'>proc[3].sbox/g0[3].g1[1].sub/byteout_4</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X24Y89.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">clk_i_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X24Y89.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.471</twDelInfo><twComp>proc[3].add/dataout&lt;3&gt;_1_7</twComp><twBEL>proc[3].add/dataout&lt;3&gt;_1_4</twBEL></twPathDel><twPathDel><twSite>SLICE_X29Y84.B1</twSite><twDelType>net</twDelType><twFanCnt>32</twFanCnt><twDelInfo twEdge="twRising">1.591</twDelInfo><twComp>proc[3].add/dataout&lt;3&gt;_1_4</twComp></twPathDel><twPathDel><twSite>SLICE_X29Y84.B</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.094</twDelInfo><twComp>proc[3].sbox/g0[3].g1[1].sub_Mrom_byteout_rom000083</twComp><twBEL>proc[3].sbox/g0[3].g1[1].sub_Mrom_byteout_rom000083</twBEL></twPathDel><twPathDel><twSite>SLICE_X28Y84.D6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.433</twDelInfo><twComp>proc[3].sbox/g0[3].g1[1].sub_Mrom_byteout_rom000083</twComp></twPathDel><twPathDel><twSite>SLICE_X28Y84.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.225</twDelInfo><twComp>proc[3].sbox/g0[3].g1[1].sub/byteout&lt;4&gt;</twComp><twBEL>proc[3].sbox/g0[3].g1[1].sub_Mrom_byteout_rom00008_f7_0</twBEL><twBEL>proc[3].sbox/g0[3].g1[1].sub_Mrom_byteout_rom00008_f71_rt</twBEL><twBEL>proc[3].sbox/g0[3].g1[1].sub_Mrom_byteout_rom00008_f8</twBEL><twBEL>proc[3].sbox/g0[3].g1[1].sub/byteout_4</twBEL></twPathDel><twLogDel>0.790</twLogDel><twRouteDel>2.024</twRouteDel><twTotDel>2.814</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="3.000">clk_i_BUFGP</twDestClk><twPctLog>28.1</twPctLog><twPctRoute>71.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="11"><twConstPath anchorID="12" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.029</twSlack><twSrc BELType="FF">proc[4].add/dataout&lt;0&gt;_3_5</twSrc><twDest BELType="FF">proc[4].sbox/g0[0].g1[3].sub/byteout_1</twDest><twTotPathDel>2.833</twTotPathDel><twClkSkew dest = "1.169" src = "1.272">0.103</twClkSkew><twDelConst>3.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16"><twSrc BELType='FF'>proc[4].add/dataout&lt;0&gt;_3_5</twSrc><twDest BELType='FF'>proc[4].sbox/g0[0].g1[3].sub/byteout_1</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X24Y60.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">clk_i_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X24Y60.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.471</twDelInfo><twComp>proc[4].add/dataout&lt;0&gt;_3_7</twComp><twBEL>proc[4].add/dataout&lt;0&gt;_3_5</twBEL></twPathDel><twPathDel><twSite>SLICE_X19Y52.A4</twSite><twDelType>net</twDelType><twFanCnt>32</twFanCnt><twDelInfo twEdge="twRising">1.447</twDelInfo><twComp>proc[4].add/dataout&lt;0&gt;_3_5</twComp></twPathDel><twPathDel><twSite>SLICE_X19Y52.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.094</twDelInfo><twComp>proc[4].sbox/g0[0].g1[3].sub_Mrom_byteout_rom0000141</twComp><twBEL>proc[4].sbox/g0[0].g1[3].sub_Mrom_byteout_rom000024</twBEL></twPathDel><twPathDel><twSite>SLICE_X15Y51.D6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.569</twDelInfo><twComp>proc[4].sbox/g0[0].g1[3].sub_Mrom_byteout_rom000024</twComp></twPathDel><twPathDel><twSite>SLICE_X15Y51.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.252</twDelInfo><twComp>proc[4].sbox/g0[0].g1[3].sub/byteout&lt;1&gt;</twComp><twBEL>proc[4].sbox/g0[0].g1[3].sub_Mrom_byteout_rom00002_f7_0</twBEL><twBEL>proc[4].sbox/g0[0].g1[3].sub_Mrom_byteout_rom00002_f71_rt</twBEL><twBEL>proc[4].sbox/g0[0].g1[3].sub_Mrom_byteout_rom00002_f8</twBEL><twBEL>proc[4].sbox/g0[0].g1[3].sub/byteout_1</twBEL></twPathDel><twLogDel>0.817</twLogDel><twRouteDel>2.016</twRouteDel><twTotDel>2.833</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="3.000">clk_i_BUFGP</twDestClk><twPctLog>28.8</twPctLog><twPctRoute>71.2</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="13"><twConstPath anchorID="14" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.031</twSlack><twSrc BELType="FF">proc[7].add/dataout&lt;0&gt;_1_4</twSrc><twDest BELType="FF">proc[7].sbox/g0[0].g1[1].sub/byteout_3</twDest><twTotPathDel>2.875</twTotPathDel><twClkSkew dest = "1.245" src = "1.304">0.059</twClkSkew><twDelConst>3.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16"><twSrc BELType='FF'>proc[7].add/dataout&lt;0&gt;_1_4</twSrc><twDest BELType='FF'>proc[7].sbox/g0[0].g1[1].sub/byteout_3</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X29Y13.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">clk_i_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X29Y13.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.450</twDelInfo><twComp>proc[7].add/dataout&lt;0&gt;_1_7</twComp><twBEL>proc[7].add/dataout&lt;0&gt;_1_4</twBEL></twPathDel><twPathDel><twSite>SLICE_X27Y8.A1</twSite><twDelType>net</twDelType><twFanCnt>32</twFanCnt><twDelInfo twEdge="twRising">1.693</twDelInfo><twComp>proc[7].add/dataout&lt;0&gt;_1_4</twComp></twPathDel><twPathDel><twSite>SLICE_X27Y8.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.094</twDelInfo><twComp>proc[7].sbox/g0[0].g1[1].sub_Mrom_byteout_rom000063</twComp><twBEL>proc[7].sbox/g0[0].g1[1].sub_Mrom_byteout_rom000063</twBEL></twPathDel><twPathDel><twSite>SLICE_X27Y10.D5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.386</twDelInfo><twComp>proc[7].sbox/g0[0].g1[1].sub_Mrom_byteout_rom000063</twComp></twPathDel><twPathDel><twSite>SLICE_X27Y10.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.252</twDelInfo><twComp>proc[7].sbox/g0[0].g1[1].sub/byteout&lt;3&gt;</twComp><twBEL>proc[7].sbox/g0[0].g1[1].sub_Mrom_byteout_rom00006_f7_0</twBEL><twBEL>proc[7].sbox/g0[0].g1[1].sub_Mrom_byteout_rom00006_f71_rt</twBEL><twBEL>proc[7].sbox/g0[0].g1[1].sub_Mrom_byteout_rom00006_f8</twBEL><twBEL>proc[7].sbox/g0[0].g1[1].sub/byteout_3</twBEL></twPathDel><twLogDel>0.796</twLogDel><twRouteDel>2.079</twRouteDel><twTotDel>2.875</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="3.000">clk_i_BUFGP</twDestClk><twPctLog>27.7</twPctLog><twPctRoute>72.3</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="15"><twConstPath anchorID="16" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.036</twSlack><twSrc BELType="FF">proc[8].add/dataout&lt;1&gt;_3_4</twSrc><twDest BELType="FF">proc[8].sbox/g0[1].g1[3].sub/byteout_3</twDest><twTotPathDel>2.786</twTotPathDel><twClkSkew dest = "1.130" src = "1.273">0.143</twClkSkew><twDelConst>3.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16"><twSrc BELType='FF'>proc[8].add/dataout&lt;1&gt;_3_4</twSrc><twDest BELType='FF'>proc[8].sbox/g0[1].g1[3].sub/byteout_3</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X36Y35.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">clk_i_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X36Y35.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.471</twDelInfo><twComp>proc[8].add/dataout&lt;1&gt;_3_7</twComp><twBEL>proc[8].add/dataout&lt;1&gt;_3_4</twBEL></twPathDel><twPathDel><twSite>SLICE_X35Y42.C3</twSite><twDelType>net</twDelType><twFanCnt>32</twFanCnt><twDelInfo twEdge="twRising">1.552</twDelInfo><twComp>proc[8].add/dataout&lt;1&gt;_3_4</twComp></twPathDel><twPathDel><twSite>SLICE_X35Y42.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.094</twDelInfo><twComp>sbox_f_1/g0[3].g1[2].sub_Mrom_byteout_rom000083</twComp><twBEL>proc[8].sbox/g0[1].g1[3].sub_Mrom_byteout_rom000063</twBEL></twPathDel><twPathDel><twSite>SLICE_X32Y42.D6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.444</twDelInfo><twComp>proc[8].sbox/g0[1].g1[3].sub_Mrom_byteout_rom000063</twComp></twPathDel><twPathDel><twSite>SLICE_X32Y42.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.225</twDelInfo><twComp>proc[8].sbox/g0[1].g1[3].sub/byteout&lt;3&gt;</twComp><twBEL>proc[8].sbox/g0[1].g1[3].sub_Mrom_byteout_rom00006_f7_0</twBEL><twBEL>proc[8].sbox/g0[1].g1[3].sub_Mrom_byteout_rom00006_f71_rt</twBEL><twBEL>proc[8].sbox/g0[1].g1[3].sub_Mrom_byteout_rom00006_f8</twBEL><twBEL>proc[8].sbox/g0[1].g1[3].sub/byteout_3</twBEL></twPathDel><twLogDel>0.790</twLogDel><twRouteDel>1.996</twRouteDel><twTotDel>2.786</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="3.000">clk_i_BUFGP</twDestClk><twPctLog>28.4</twPctLog><twPctRoute>71.6</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="17"><twConstPath anchorID="18" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.036</twSlack><twSrc BELType="FF">proc[8].mix/g0[1].mix/out2_2</twSrc><twDest BELType="FF">add_f_1/dataout&lt;2&gt;_1_2</twDest><twTotPathDel>2.762</twTotPathDel><twClkSkew dest = "1.208" src = "1.375">0.167</twClkSkew><twDelConst>3.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16"><twSrc BELType='FF'>proc[8].mix/g0[1].mix/out2_2</twSrc><twDest BELType='FF'>add_f_1/dataout&lt;2&gt;_1_2</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X55Y36.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">clk_i_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X55Y36.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.450</twDelInfo><twComp>proc[8].mix/g0[1].mix/out2&lt;5&gt;</twComp><twBEL>proc[8].mix/g0[1].mix/out2_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X57Y73.C5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">2.283</twDelInfo><twComp>proc[8].mix/g0[1].mix/out2&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X57Y73.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.029</twDelInfo><twComp>add_f_1/dataout&lt;2&gt;_1_3</twComp><twBEL>add_f_1/Mxor_added&lt;2&gt;&lt;1&gt;_Result&lt;2&gt;1</twBEL><twBEL>add_f_1/dataout&lt;2&gt;_1_2</twBEL></twPathDel><twLogDel>0.479</twLogDel><twRouteDel>2.283</twRouteDel><twTotDel>2.762</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="3.000">clk_i_BUFGP</twDestClk><twPctLog>17.3</twPctLog><twPctRoute>82.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="19"><twConstPath anchorID="20" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.040</twSlack><twSrc BELType="FF">proc[5].sbox/g0[1].g1[1].sub/byteout_2</twSrc><twDest BELType="FF">proc[5].mix/g0[0].mix/out1_3</twDest><twTotPathDel>2.871</twTotPathDel><twClkSkew dest = "1.331" src = "1.385">0.054</twClkSkew><twDelConst>3.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16"><twSrc BELType='FF'>proc[5].sbox/g0[1].g1[1].sub/byteout_2</twSrc><twDest BELType='FF'>proc[5].mix/g0[0].mix/out1_3</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X0Y32.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">clk_i_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X0Y32.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.471</twDelInfo><twComp>proc[5].sbox/g0[1].g1[1].sub/byteout&lt;2&gt;</twComp><twBEL>proc[5].sbox/g0[1].g1[1].sub/byteout_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X10Y18.A6</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">2.253</twDelInfo><twComp>proc[5].sbox/g0[1].g1[1].sub/byteout&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X10Y18.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.147</twDelInfo><twComp>proc[5].mix/g0[0].mix/out1&lt;3&gt;</twComp><twBEL>proc[5].mix/g0[0].mix/out1_xor0000&lt;3&gt;1</twBEL><twBEL>proc[5].mix/g0[0].mix/out1_xor0000&lt;3&gt;_f7</twBEL><twBEL>proc[5].mix/g0[0].mix/out1_3</twBEL></twPathDel><twLogDel>0.618</twLogDel><twRouteDel>2.253</twRouteDel><twTotDel>2.871</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="3.000">clk_i_BUFGP</twDestClk><twPctLog>21.5</twPctLog><twPctRoute>78.5</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="21"><twConstPath anchorID="22" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.041</twSlack><twSrc BELType="FF">proc[6].add/dataout&lt;2&gt;_0_5</twSrc><twDest BELType="FF">proc[6].sbox/g0[2].g1[0].sub/byteout_4</twDest><twTotPathDel>2.742</twTotPathDel><twClkSkew dest = "1.254" src = "1.436">0.182</twClkSkew><twDelConst>3.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16"><twSrc BELType='FF'>proc[6].add/dataout&lt;2&gt;_0_5</twSrc><twDest BELType='FF'>proc[6].sbox/g0[2].g1[0].sub/byteout_4</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X14Y16.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">clk_i_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X14Y16.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.450</twDelInfo><twComp>proc[6].add/dataout&lt;2&gt;_0_7</twComp><twBEL>proc[6].add/dataout&lt;2&gt;_0_5</twBEL></twPathDel><twPathDel><twSite>SLICE_X20Y20.C2</twSite><twDelType>net</twDelType><twFanCnt>32</twFanCnt><twDelInfo twEdge="twRising">1.524</twDelInfo><twComp>proc[6].add/dataout&lt;2&gt;_0_5</twComp></twPathDel><twPathDel><twSite>SLICE_X20Y20.C</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.094</twDelInfo><twComp>proc[6].sbox/g0[2].g1[0].sub/byteout&lt;4&gt;</twComp><twBEL>proc[6].sbox/g0[2].g1[0].sub_Mrom_byteout_rom000082</twBEL></twPathDel><twPathDel><twSite>SLICE_X20Y20.D6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.449</twDelInfo><twComp>proc[6].sbox/g0[2].g1[0].sub_Mrom_byteout_rom000082</twComp></twPathDel><twPathDel><twSite>SLICE_X20Y20.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.225</twDelInfo><twComp>proc[6].sbox/g0[2].g1[0].sub/byteout&lt;4&gt;</twComp><twBEL>proc[6].sbox/g0[2].g1[0].sub_Mrom_byteout_rom00008_f7_0</twBEL><twBEL>proc[6].sbox/g0[2].g1[0].sub_Mrom_byteout_rom00008_f71_rt</twBEL><twBEL>proc[6].sbox/g0[2].g1[0].sub_Mrom_byteout_rom00008_f8</twBEL><twBEL>proc[6].sbox/g0[2].g1[0].sub/byteout_4</twBEL></twPathDel><twLogDel>0.769</twLogDel><twRouteDel>1.973</twRouteDel><twTotDel>2.742</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="3.000">clk_i_BUFGP</twDestClk><twPctLog>28.0</twPctLog><twPctRoute>72.0</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="23"><twConstPath anchorID="24" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.041</twSlack><twSrc BELType="FF">proc[5].sbox/g0[1].g1[1].sub/byteout_2</twSrc><twDest BELType="FF">proc[5].mix/g0[0].mix/out1_3</twDest><twTotPathDel>2.870</twTotPathDel><twClkSkew dest = "1.331" src = "1.385">0.054</twClkSkew><twDelConst>3.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="16"><twSrc BELType='FF'>proc[5].sbox/g0[1].g1[1].sub/byteout_2</twSrc><twDest BELType='FF'>proc[5].mix/g0[0].mix/out1_3</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X0Y32.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">clk_i_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X0Y32.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.471</twDelInfo><twComp>proc[5].sbox/g0[1].g1[1].sub/byteout&lt;2&gt;</twComp><twBEL>proc[5].sbox/g0[1].g1[1].sub/byteout_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X10Y18.B6</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">2.260</twDelInfo><twComp>proc[5].sbox/g0[1].g1[1].sub/byteout&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X10Y18.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.139</twDelInfo><twComp>proc[5].mix/g0[0].mix/out1&lt;3&gt;</twComp><twBEL>proc[5].mix/g0[0].mix/out1_xor0000&lt;3&gt;2</twBEL><twBEL>proc[5].mix/g0[0].mix/out1_xor0000&lt;3&gt;_f7</twBEL><twBEL>proc[5].mix/g0[0].mix/out1_3</twBEL></twPathDel><twLogDel>0.610</twLogDel><twRouteDel>2.260</twRouteDel><twTotDel>2.870</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="3.000">clk_i_BUFGP</twDestClk><twPctLog>21.3</twPctLog><twPctRoute>78.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner sType="PathClass">Hold Paths: TS_clk = PERIOD TIMEGRP &quot;clk_i&quot; 3 ns HIGH 50%;
</twPathRptBanner><twPathRpt anchorID="25"><twConstPath anchorID="26" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.296</twSlack><twSrc BELType="FF">proc[0].sbox/nextkey&lt;0&gt;_2_5</twSrc><twDest BELType="FF">proc[0].mix/outrkey&lt;0&gt;_2_5</twDest><twTotPathDel>0.452</twTotPathDel><twClkSkew dest = "1.377" src = "1.221">-0.156</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16"><twSrc BELType='FF'>proc[0].sbox/nextkey&lt;0&gt;_2_5</twSrc><twDest BELType='FF'>proc[0].mix/outrkey&lt;0&gt;_2_5</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X55Y79.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="3.000">clk_i_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X55Y79.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.414</twDelInfo><twComp>proc[0].sbox/nextkey&lt;0&gt;_2_7</twComp><twBEL>proc[0].sbox/nextkey&lt;0&gt;_2_5</twBEL></twPathDel><twPathDel><twSite>SLICE_X56Y80.BX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.280</twDelInfo><twComp>proc[0].sbox/nextkey&lt;0&gt;_2_5</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X56Y80.CLK</twSite><twDelType>Tckdi</twDelType><twDelInfo twEdge="twFalling">-0.242</twDelInfo><twComp>proc[0].mix/outrkey&lt;0&gt;_2_7</twComp><twBEL>proc[0].mix/outrkey&lt;0&gt;_2_5</twBEL></twPathDel><twLogDel>0.172</twLogDel><twRouteDel>0.280</twRouteDel><twTotDel>0.452</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="3.000">clk_i_BUFGP</twDestClk><twPctLog>38.1</twPctLog><twPctRoute>61.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="27"><twConstPath anchorID="28" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.339</twSlack><twSrc BELType="FF">proc[1].sbox/nextkey&lt;0&gt;_0_5</twSrc><twDest BELType="FF">proc[1].mix/outrkey&lt;0&gt;_0_5</twDest><twTotPathDel>0.472</twTotPathDel><twClkSkew dest = "1.348" src = "1.215">-0.133</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="17"><twSrc BELType='FF'>proc[1].sbox/nextkey&lt;0&gt;_0_5</twSrc><twDest BELType='FF'>proc[1].mix/outrkey&lt;0&gt;_0_5</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X43Y99.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="3.000">clk_i_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X43Y99.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.414</twDelInfo><twComp>proc[1].sbox/nextkey&lt;0&gt;_0_7</twComp><twBEL>proc[1].sbox/nextkey&lt;0&gt;_0_5</twBEL></twPathDel><twPathDel><twSite>SLICE_X43Y101.BX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.289</twDelInfo><twComp>proc[1].sbox/nextkey&lt;0&gt;_0_5</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X43Y101.CLK</twSite><twDelType>Tckdi</twDelType><twDelInfo twEdge="twFalling">-0.231</twDelInfo><twComp>proc[1].mix/outrkey&lt;0&gt;_0_7</twComp><twBEL>proc[1].mix/outrkey&lt;0&gt;_0_5</twBEL></twPathDel><twLogDel>0.183</twLogDel><twRouteDel>0.289</twRouteDel><twTotDel>0.472</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="3.000">clk_i_BUFGP</twDestClk><twPctLog>38.8</twPctLog><twPctRoute>61.2</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="29"><twConstPath anchorID="30" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.412</twSlack><twSrc BELType="FF">proc[0].add/step1/sub1/byteout_5</twSrc><twDest BELType="FF">proc[0].sbox/nextkey&lt;0&gt;_0_5</twDest><twTotPathDel>0.499</twTotPathDel><twClkSkew dest = "0.577" src = "0.490">-0.087</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16"><twSrc BELType='FF'>proc[0].add/step1/sub1/byteout_5</twSrc><twDest BELType='FF'>proc[0].sbox/nextkey&lt;0&gt;_0_5</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X45Y79.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="3.000">clk_i_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X45Y79.BQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.414</twDelInfo><twComp>proc[0].add/step1/sub1/byteout&lt;5&gt;</twComp><twBEL>proc[0].add/step1/sub1/byteout_5</twBEL></twPathDel><twPathDel><twSite>SLICE_X46Y79.B6</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twFalling">0.281</twDelInfo><twComp>proc[0].add/step1/sub1/byteout&lt;5&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X46Y79.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">-0.196</twDelInfo><twComp>proc[0].sbox/nextkey&lt;0&gt;_0_7</twComp><twBEL>proc[0].sbox/Mxor_nextkey&lt;0&gt;_0_xor0000_Result&lt;5&gt;1</twBEL><twBEL>proc[0].sbox/nextkey&lt;0&gt;_0_5</twBEL></twPathDel><twLogDel>0.218</twLogDel><twRouteDel>0.281</twRouteDel><twTotDel>0.499</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="3.000">clk_i_BUFGP</twDestClk><twPctLog>43.7</twPctLog><twPctRoute>56.3</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="31"><twConstPath anchorID="32" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.419</twSlack><twSrc BELType="FF">proc[1].sbox/nextkey&lt;1&gt;_1_2</twSrc><twDest BELType="FF">proc[1].mix/outrkey&lt;1&gt;_1_2</twDest><twTotPathDel>0.491</twTotPathDel><twClkSkew dest = "0.543" src = "0.471">-0.072</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="17"><twSrc BELType='FF'>proc[1].sbox/nextkey&lt;1&gt;_1_2</twSrc><twDest BELType='FF'>proc[1].mix/outrkey&lt;1&gt;_1_2</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X27Y108.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="3.000">clk_i_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X27Y108.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.414</twDelInfo><twComp>proc[1].sbox/nextkey&lt;1&gt;_1_3</twComp><twBEL>proc[1].sbox/nextkey&lt;1&gt;_1_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X22Y108.CX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.295</twDelInfo><twComp>proc[1].sbox/nextkey&lt;1&gt;_1_2</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X22Y108.CLK</twSite><twDelType>Tckdi</twDelType><twDelInfo twEdge="twFalling">-0.218</twDelInfo><twComp>proc[1].mix/outrkey&lt;1&gt;_1_3</twComp><twBEL>proc[1].mix/outrkey&lt;1&gt;_1_2</twBEL></twPathDel><twLogDel>0.196</twLogDel><twRouteDel>0.295</twRouteDel><twTotDel>0.491</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="3.000">clk_i_BUFGP</twDestClk><twPctLog>39.9</twPctLog><twPctRoute>60.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="33"><twConstPath anchorID="34" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.420</twSlack><twSrc BELType="FF">proc[6].add/step1/c0_3_4</twSrc><twDest BELType="FF">proc[6].sbox/nextkey&lt;3&gt;_0_4</twDest><twTotPathDel>0.474</twTotPathDel><twClkSkew dest = "0.493" src = "0.439">-0.054</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16"><twSrc BELType='FF'>proc[6].add/step1/c0_3_4</twSrc><twDest BELType='FF'>proc[6].sbox/nextkey&lt;3&gt;_0_4</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X31Y24.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="3.000">clk_i_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X31Y24.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.414</twDelInfo><twComp>proc[6].add/step1/c0_3_7</twComp><twBEL>proc[6].add/step1/c0_3_4</twBEL></twPathDel><twPathDel><twSite>SLICE_X33Y24.A6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.257</twDelInfo><twComp>proc[6].add/step1/c0_3_4</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X33Y24.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">-0.197</twDelInfo><twComp>proc[6].sbox/nextkey&lt;3&gt;_0_7</twComp><twBEL>proc[6].sbox/Mxor_nextkey&lt;3&gt;_0_xor0000_Result&lt;4&gt;1</twBEL><twBEL>proc[6].sbox/nextkey&lt;3&gt;_0_4</twBEL></twPathDel><twLogDel>0.217</twLogDel><twRouteDel>0.257</twRouteDel><twTotDel>0.474</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="3.000">clk_i_BUFGP</twDestClk><twPctLog>45.8</twPctLog><twPctRoute>54.2</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="35"><twConstPath anchorID="36" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.421</twSlack><twSrc BELType="FF">proc[8].add/step1/c0_3_0</twSrc><twDest BELType="FF">proc[8].sbox/nextkey&lt;3&gt;_0_0</twDest><twTotPathDel>0.461</twTotPathDel><twClkSkew dest = "0.546" src = "0.506">-0.040</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16"><twSrc BELType='FF'>proc[8].add/step1/c0_3_0</twSrc><twDest BELType='FF'>proc[8].sbox/nextkey&lt;3&gt;_0_0</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X51Y36.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="3.000">clk_i_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X51Y36.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.414</twDelInfo><twComp>proc[8].add/step1/c0_3_3</twComp><twBEL>proc[8].add/step1/c0_3_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X48Y36.A6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.266</twDelInfo><twComp>proc[8].add/step1/c0_3_0</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X48Y36.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">-0.219</twDelInfo><twComp>proc[8].sbox/nextkey&lt;3&gt;_0_3</twComp><twBEL>proc[8].sbox/Mxor_nextkey&lt;3&gt;_0_xor0000_Result&lt;0&gt;1</twBEL><twBEL>proc[8].sbox/nextkey&lt;3&gt;_0_0</twBEL></twPathDel><twLogDel>0.195</twLogDel><twRouteDel>0.266</twRouteDel><twTotDel>0.461</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="3.000">clk_i_BUFGP</twDestClk><twPctLog>42.3</twPctLog><twPctRoute>57.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="37"><twConstPath anchorID="38" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.422</twSlack><twSrc BELType="FF">proc[3].add/step1/c0_3_4</twSrc><twDest BELType="FF">proc[3].sbox/nextkey&lt;3&gt;_0_4</twDest><twTotPathDel>0.480</twTotPathDel><twClkSkew dest = "0.470" src = "0.412">-0.058</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16"><twSrc BELType='FF'>proc[3].add/step1/c0_3_4</twSrc><twDest BELType='FF'>proc[3].sbox/nextkey&lt;3&gt;_0_4</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X33Y70.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="3.000">clk_i_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X33Y70.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.414</twDelInfo><twComp>proc[3].add/step1/c0_3_7</twComp><twBEL>proc[3].add/step1/c0_3_4</twBEL></twPathDel><twPathDel><twSite>SLICE_X30Y70.A6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.263</twDelInfo><twComp>proc[3].add/step1/c0_3_4</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X30Y70.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">-0.197</twDelInfo><twComp>proc[3].sbox/nextkey&lt;3&gt;_0_7</twComp><twBEL>proc[3].sbox/Mxor_nextkey&lt;3&gt;_0_xor0000_Result&lt;4&gt;1</twBEL><twBEL>proc[3].sbox/nextkey&lt;3&gt;_0_4</twBEL></twPathDel><twLogDel>0.217</twLogDel><twRouteDel>0.263</twRouteDel><twTotDel>0.480</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="3.000">clk_i_BUFGP</twDestClk><twPctLog>45.2</twPctLog><twPctRoute>54.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="39"><twConstPath anchorID="40" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.422</twSlack><twSrc BELType="FF">proc[6].mix/g0[2].mix/out1_1</twSrc><twDest BELType="FF">proc[7].add/dataout&lt;1&gt;_2_1</twDest><twTotPathDel>0.464</twTotPathDel><twClkSkew dest = "0.542" src = "0.500">-0.042</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16"><twSrc BELType='FF'>proc[6].mix/g0[2].mix/out1_1</twSrc><twDest BELType='FF'>proc[7].add/dataout&lt;1&gt;_2_1</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X27Y20.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="3.000">clk_i_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X27Y20.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.414</twDelInfo><twComp>proc[6].mix/g0[2].mix/out1&lt;2&gt;</twComp><twBEL>proc[6].mix/g0[2].mix/out1_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X24Y20.B6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.272</twDelInfo><twComp>proc[6].mix/g0[2].mix/out1&lt;1&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X24Y20.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">-0.222</twDelInfo><twComp>proc[7].add/dataout&lt;1&gt;_2_3</twComp><twBEL>proc[7].add/Mxor_added&lt;1&gt;&lt;2&gt;_Result&lt;1&gt;1</twBEL><twBEL>proc[7].add/dataout&lt;1&gt;_2_1</twBEL></twPathDel><twLogDel>0.192</twLogDel><twRouteDel>0.272</twRouteDel><twTotDel>0.464</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="3.000">clk_i_BUFGP</twDestClk><twPctLog>41.4</twPctLog><twPctRoute>58.6</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="41"><twConstPath anchorID="42" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.422</twSlack><twSrc BELType="FF">add_f_1/step1/c2_3_2</twSrc><twDest BELType="FF">sbox_f_1/nextkey&lt;3&gt;_2_2</twDest><twTotPathDel>0.486</twTotPathDel><twClkSkew dest = "0.559" src = "0.495">-0.064</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16"><twSrc BELType='FF'>add_f_1/step1/c2_3_2</twSrc><twDest BELType='FF'>sbox_f_1/nextkey&lt;3&gt;_2_2</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X49Y45.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="3.000">clk_i_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X49Y45.CQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.414</twDelInfo><twComp>add_f_1/step1/c2_3_3</twComp><twBEL>add_f_1/step1/c2_3_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X50Y44.C6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.267</twDelInfo><twComp>add_f_1/step1/c2_3_2</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X50Y44.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">-0.195</twDelInfo><twComp>sbox_f_1/nextkey&lt;3&gt;_2_3</twComp><twBEL>sbox_f_1/Mxor_nextkey&lt;3&gt;_2_xor0000_Result&lt;2&gt;1</twBEL><twBEL>sbox_f_1/nextkey&lt;3&gt;_2_2</twBEL></twPathDel><twLogDel>0.219</twLogDel><twRouteDel>0.267</twRouteDel><twTotDel>0.486</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="3.000">clk_i_BUFGP</twDestClk><twPctLog>45.1</twPctLog><twPctRoute>54.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="43"><twConstPath anchorID="44" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.423</twSlack><twSrc BELType="FF">proc[6].add/step1/c0_3_7</twSrc><twDest BELType="FF">proc[6].sbox/nextkey&lt;3&gt;_0_7</twDest><twTotPathDel>0.477</twTotPathDel><twClkSkew dest = "0.493" src = "0.439">-0.054</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16"><twSrc BELType='FF'>proc[6].add/step1/c0_3_7</twSrc><twDest BELType='FF'>proc[6].sbox/nextkey&lt;3&gt;_0_7</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X31Y24.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="3.000">clk_i_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X31Y24.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.414</twDelInfo><twComp>proc[6].add/step1/c0_3_7</twComp><twBEL>proc[6].add/step1/c0_3_7</twBEL></twPathDel><twPathDel><twSite>SLICE_X33Y24.D6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.258</twDelInfo><twComp>proc[6].add/step1/c0_3_7</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X33Y24.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">-0.195</twDelInfo><twComp>proc[6].sbox/nextkey&lt;3&gt;_0_7</twComp><twBEL>proc[6].sbox/Mxor_nextkey&lt;3&gt;_0_xor0000_Result&lt;7&gt;1</twBEL><twBEL>proc[6].sbox/nextkey&lt;3&gt;_0_7</twBEL></twPathDel><twLogDel>0.219</twLogDel><twRouteDel>0.258</twRouteDel><twTotDel>0.477</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="3.000">clk_i_BUFGP</twDestClk><twPctLog>45.9</twPctLog><twPctRoute>54.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="45"><twPinLimitBanner>Component Switching Limit Checks: TS_clk = PERIOD TIMEGRP &quot;clk_i&quot; 3 ns HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="46" type="MINLOWPULSE" name="Trpw" slack="1.946" period="3.000" constraintValue="1.500" deviceLimit="0.527" physResource="proc[8].sbox/g0[0].g1[3].sub/byteout&lt;3&gt;/SR" logResource="proc[8].sbox/g0[0].g1[3].sub/byteout_3/SR" locationPin="SLICE_X38Y26.SR" clockNet="rst_i_BUFGP"/><twPinLimit anchorID="47" type="MINHIGHPULSE" name="Trpw" slack="1.946" period="3.000" constraintValue="1.500" deviceLimit="0.527" physResource="proc[8].sbox/g0[0].g1[3].sub/byteout&lt;3&gt;/SR" logResource="proc[8].sbox/g0[0].g1[3].sub/byteout_3/SR" locationPin="SLICE_X38Y26.SR" clockNet="rst_i_BUFGP"/><twPinLimit anchorID="48" type="MINLOWPULSE" name="Trpw" slack="1.946" period="3.000" constraintValue="1.500" deviceLimit="0.527" physResource="proc[8].sbox/g0[2].g1[3].sub/byteout&lt;3&gt;/SR" logResource="proc[8].sbox/g0[2].g1[3].sub/byteout_3/SR" locationPin="SLICE_X59Y24.SR" clockNet="rst_i_BUFGP"/><twPinLimit anchorID="49" type="MINHIGHPULSE" name="Trpw" slack="1.946" period="3.000" constraintValue="1.500" deviceLimit="0.527" physResource="proc[8].sbox/g0[2].g1[3].sub/byteout&lt;3&gt;/SR" logResource="proc[8].sbox/g0[2].g1[3].sub/byteout_3/SR" locationPin="SLICE_X59Y24.SR" clockNet="rst_i_BUFGP"/><twPinLimit anchorID="50" type="MINLOWPULSE" name="Trpw" slack="1.946" period="3.000" constraintValue="1.500" deviceLimit="0.527" physResource="proc[8].sbox/g0[3].g1[3].sub/byteout&lt;3&gt;/SR" logResource="proc[8].sbox/g0[3].g1[3].sub/byteout_3/SR" locationPin="SLICE_X58Y42.SR" clockNet="rst_i_BUFGP"/><twPinLimit anchorID="51" type="MINHIGHPULSE" name="Trpw" slack="1.946" period="3.000" constraintValue="1.500" deviceLimit="0.527" physResource="proc[8].sbox/g0[3].g1[3].sub/byteout&lt;3&gt;/SR" logResource="proc[8].sbox/g0[3].g1[3].sub/byteout_3/SR" locationPin="SLICE_X58Y42.SR" clockNet="rst_i_BUFGP"/><twPinLimit anchorID="52" type="MINLOWPULSE" name="Trpw" slack="1.946" period="3.000" constraintValue="1.500" deviceLimit="0.527" physResource="proc[7].sbox/g0[1].g1[3].sub/byteout&lt;3&gt;/SR" logResource="proc[7].sbox/g0[1].g1[3].sub/byteout_3/SR" locationPin="SLICE_X42Y7.SR" clockNet="rst_i_BUFGP"/><twPinLimit anchorID="53" type="MINHIGHPULSE" name="Trpw" slack="1.946" period="3.000" constraintValue="1.500" deviceLimit="0.527" physResource="proc[7].sbox/g0[1].g1[3].sub/byteout&lt;3&gt;/SR" logResource="proc[7].sbox/g0[1].g1[3].sub/byteout_3/SR" locationPin="SLICE_X42Y7.SR" clockNet="rst_i_BUFGP"/><twPinLimit anchorID="54" type="MINLOWPULSE" name="Trpw" slack="1.946" period="3.000" constraintValue="1.500" deviceLimit="0.527" physResource="proc[7].sbox/g0[2].g1[3].sub/byteout&lt;3&gt;/SR" logResource="proc[7].sbox/g0[2].g1[3].sub/byteout_3/SR" locationPin="SLICE_X33Y11.SR" clockNet="rst_i_BUFGP"/><twPinLimit anchorID="55" type="MINHIGHPULSE" name="Trpw" slack="1.946" period="3.000" constraintValue="1.500" deviceLimit="0.527" physResource="proc[7].sbox/g0[2].g1[3].sub/byteout&lt;3&gt;/SR" logResource="proc[7].sbox/g0[2].g1[3].sub/byteout_3/SR" locationPin="SLICE_X33Y11.SR" clockNet="rst_i_BUFGP"/></twPinLimitRpt></twConst><twUnmetConstCnt anchorID="56">0</twUnmetConstCnt><twDataSheet anchorID="57" twNameLen="15"><twClk2SUList anchorID="58" twDestWidth="5"><twDest>clk_i</twDest><twClk2SU><twSrc>clk_i</twSrc><twRiseRise>2.974</twRiseRise></twClk2SU></twClk2SUList><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twSum anchorID="59"><twErrCnt>0</twErrCnt><twScore>0</twScore><twSetupScore>0</twSetupScore><twHoldScore>0</twHoldScore><twConstCov><twPathCnt>59472</twPathCnt><twNetCnt>0</twNetCnt><twConnCnt>69148</twConnCnt></twConstCov><twStats anchorID="60"><twMinPer>2.974</twMinPer><twFootnote number="1" /><twMaxFreq>336.247</twMaxFreq></twStats></twSum><twFoot><twFootnoteExplanation number="1" text="The minimum period statistic assumes all single cycle delays."></twFootnoteExplanation><twTimestamp>Thu Mar 25 15:34:03 2010 </twTimestamp></twFoot><twClientInfo anchorID="61"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>
 
Peak Memory Usage: 381 MB
</twValue></twAttrListItem></twAttrList></twClientInfo></twReport>
/aes_pipe/trunk/syn/Xilinx/run/aes.prj
0,0 → 1,8
vhdl work ../../../rtl/vhdl/aes_pkg.vhdl
vhdl work ../../../rtl/vhdl/mixcol.vhdl
vhdl work ../../../rtl/vhdl/colmix.vhdl
vhdl work ../../../rtl/vhdl/sbox.vhdl
vhdl work ../../../rtl/vhdl/subsh.vhdl
vhdl work ../../../rtl/vhdl/keysched1.vhdl
vhdl work ../../../rtl/vhdl/addkey.vhdl
vhdl work ../../../rtl/vhdl/aes_top.vhdl
aes_pipe/trunk/syn/Xilinx/run/aes.prj Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: aes_pipe/trunk/syn/Xilinx/run/aes.ucf =================================================================== --- aes_pipe/trunk/syn/Xilinx/run/aes.ucf (nonexistent) +++ aes_pipe/trunk/syn/Xilinx/run/aes.ucf (revision 10) @@ -0,0 +1,2 @@ +NET "clk_i" TNM_NET = clk_i; +TIMESPEC TS_clk = PERIOD "clk_i" 3 ns HIGH 50%; Index: aes_pipe/trunk/syn/Xilinx/run/aes.xst =================================================================== --- aes_pipe/trunk/syn/Xilinx/run/aes.xst (nonexistent) +++ aes_pipe/trunk/syn/Xilinx/run/aes.xst (revision 10) @@ -0,0 +1,17 @@ +run +-ifn aes.prj +-ifmt vhdl +-top aes_top +-ofn ../out/aes.ngc +-ofmt NGC +-opt_mode area +-opt_level 2 +-decoder_extract YES +-priority_extract YES +-register_balancing NO +-resource_sharing YES +-iob FALSE +-glob_opt ALLCLOCKNETS +-rtlview YES +-hdl_compilation_order USER +-p xc5vlx50t-1ff1136
aes_pipe/trunk/syn/Xilinx/run/aes.xst Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: aes_pipe/trunk/syn/Xilinx/run/synth.sh =================================================================== --- aes_pipe/trunk/syn/Xilinx/run/synth.sh (nonexistent) +++ aes_pipe/trunk/syn/Xilinx/run/synth.sh (revision 10) @@ -0,0 +1,12 @@ +#!/bin/sh +xst -ifn aes.xst -ofn ../log/aes.log +ngdbuild -dd ../out -uc aes.ucf ../out/aes.ngc ../out/aes.ngd +map -w -timing -ol high -cm speed ../out/aes.ngd -o ../out/aes.ncd +par -w -ol high ../out/aes.ncd ../out/aes.map.ncd +mv ../out/aes.bld ../log/aes.bld +mv ../out/aes.mrp ../log/aes.mrp +mv ../out/aes.map.par ../log/aes.map.par +mv *.xrpt ../log/ +mv *.twr ../log/ +mv *.xml ../log/ +trce -v 10 -fastpaths -xml ../log/aes.twx ../out/aes.map.ncd -o ../log/aes.twr ../out/aes.pcf
aes_pipe/trunk/syn/Xilinx/run/synth.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

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