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Rev 9 → Rev 10

/trunk/src/encoder/ARITHMETICCODER.vhd
1,37 → 1,38
-- ***** BEGIN LICENSE BLOCK *****
-- ***** BEGIN LICENSE BLOCK *****
--
--
-- Version: MPL 1.1/GPL 2.0/LGPL 2.1
--
-- The contents of this file are subject to the Mozilla Public License
-- Version 1.1 (the "License"); you may not use this file except in compliance
-- with the License. You may obtain a copy of the License at
-- http://www.mozilla.org/MPL/
--
-- Software distributed under the License is distributed on an "AS IS" basis,
-- WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
-- the specific language governing rights and limitations under the License.
--
-- The Original Code is BBC Research and Development code.
--
-- The Initial Developer of the Original Code is the British Broadcasting
-- Corporation.
-- Portions created by the Initial Developer are Copyright (C) 2006.
-- All Rights Reserved.
--
-- Contributor(s): Peter Bleackley (Original author)
--
-- Alternatively, the contents of this file may be used under the terms of
-- the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
-- Public License Version 2.1 (the "LGPL"), in which case the provisions of
-- the GPL or the LGPL are applicable instead of those above. If you wish to
-- allow use of your version of this file only under the terms of the either
-- the GPL or LGPL and not to allow others to use your version of this file
-- under the MPL, indicate your decision by deleting the provisions above
-- and replace them with the notice and other provisions required by the GPL
-- or LGPL. If you do not delete the provisions above, a recipient may use
-- your version of this file under the terms of any one of the MPL, the GPL
-- or the LGPL.
-- $Id: ARITHMETICCODER.vhd,v 1.4 2006-10-05 16:17:13 petebleackley Exp $ $Name: not supported by cvs2svn $
-- *
-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
-- *
-- * The contents of this file are subject to the Mozilla Public License
-- * Version 1.1 (the "License"); you may not use this file except in compliance
-- * with the License. You may obtain a copy of the License at
-- * http://www.mozilla.org/MPL/
-- *
-- * Software distributed under the License is distributed on an "AS IS" basis,
-- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
-- * the specific language governing rights and limitations under the License.
-- *
-- * The Original Code is BBC Research and Development code.
-- *
-- * The Initial Developer of the Original Code is the British Broadcasting
-- * Corporation.
-- * Portions created by the Initial Developer are Copyright (C) 2004.
-- * All Rights Reserved.
-- *
-- * Contributor(s): Peter Bleackley (Original author)
-- *
-- * Alternatively, the contents of this file may be used under the terms of
-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of
-- * the GPL or the LGPL are applicable instead of those above. If you wish to
-- * allow use of your version of this file only under the terms of the either
-- * the GPL or LGPL and not to allow others to use your version of this file
-- * under the MPL, indicate your decision by deleting the provisions above
-- * and replace them with the notice and other provisions required by the GPL
-- * or LGPL. If you do not delete the provisions above, a recipient may use
-- * your version of this file under the terms of any one of the MPL, the GPL
-- * or the LGPL.
-- * ***** END LICENSE BLOCK ***** */
 
library IEEE;
88,7 → 89,7
end component CONVERGENCE_CHECK;
component ARITHMETIC_UNIT
port ( DIFFERENCE : in std_logic_vector(15 downto 0);
PROB : in std_logic_vector(9 downto 0);
PROB : in std_logic_vector(7 downto 0);
LOW : in std_logic_vector(15 downto 0);
ENABLE : in std_logic;
RESET : in std_logic;
129,7 → 130,7
HALVECOUNTS : in std_logic;
RESET : in std_logic;
CLOCK : in std_logic;
PROB : out std_logic_vector(9 downto 0);
PROB : out std_logic_vector(7 downto 0);
READY : out std_logic);
end component CONTEXT_MANAGER;
signal HIGH_SET : std_logic;
161,7 → 162,7
signal DIFFERENCE_OUT : std_logic_vector (15 downto 0);
signal HIGH_OUT : std_logic_vector (15 downto 0);
signal LOW_OUT : std_logic_vector (15 downto 0);
signal PROB : std_logic_vector (9 downto 0);
signal PROB : std_logic_vector (7 downto 0);
signal CONTEXT_SELECT : std_logic_vector (5 downto 0);
signal PROB_AVAILABLE : std_logic;
signal BUFFERCONTEXT : std_logic;
/trunk/src/testbench/test1.dr0 Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/src/testbench/test1.dr1 Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/src/testbench/test1.ctx.bz2 Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/src/testbench/test1.hdr Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/src/decoder/ARITHMETICDECODER.vhd
1,3 → 1,41
-- ***** BEGIN LICENSE BLOCK *****
--
-- $Id: ARITHMETICDECODER.vhd,v 1.4 2006-10-05 16:17:12 petebleackley Exp $ $Name: not supported by cvs2svn $
-- *
-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
-- *
-- * The contents of this file are subject to the Mozilla Public License
-- * Version 1.1 (the "License"); you may not use this file except in compliance
-- * with the License. You may obtain a copy of the License at
-- * http://www.mozilla.org/MPL/
-- *
-- * Software distributed under the License is distributed on an "AS IS" basis,
-- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
-- * the specific language governing rights and limitations under the License.
-- *
-- * The Original Code is BBC Research and Development code.
-- *
-- * The Initial Developer of the Original Code is the British Broadcasting
-- * Corporation.
-- * Portions created by the Initial Developer are Copyright (C) 2004.
-- * All Rights Reserved.
-- *
-- * Contributor(s): Peter Bleackley (Original author)
-- *
-- * Alternatively, the contents of this file may be used under the terms of
-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of
-- * the GPL or the LGPL are applicable instead of those above. If you wish to
-- * allow use of your version of this file only under the terms of the either
-- * the GPL or LGPL and not to allow others to use your version of this file
-- * under the MPL, indicate your decision by deleting the provisions above
-- * and replace them with the notice and other provisions required by the GPL
-- * or LGPL. If you do not delete the provisions above, a recipient may use
-- * your version of this file under the terms of any one of the MPL, the GPL
-- * or the LGPL.
-- * ***** END LICENSE BLOCK ***** */
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
53,7 → 91,7
end component CONVERGENCE_CHECK;
component ARITHMETIC_UNIT
port ( DIFFERENCE : in std_logic_vector(15 downto 0);
PROB : in std_logic_vector(9 downto 0);
PROB : in std_logic_vector(7 downto 0);
LOW : in std_logic_vector(15 downto 0);
ENABLE : in std_logic;
RESET : in std_logic;
78,7 → 116,7
HALVECOUNTS : in std_logic;
RESET : in std_logic;
CLOCK : in std_logic;
PROB : out std_logic_vector(9 downto 0);
PROB : out std_logic_vector(7 downto 0);
READY : out std_logic);
end component CONTEXT_MANAGER;
signal HIGH_SET : std_logic;
107,7 → 145,7
signal HIGH_VALUE : std_logic_vector (15 downto 0);
signal LOW_VALUE : std_logic_vector (15 downto 0);
signal CURRENT_VALUE : std_logic_vector (15 downto 0);
signal PROB : std_logic_vector (9 downto 0);
signal PROB : std_logic_vector (7 downto 0);
signal DATA_IN2 : std_logic_vector(0 downto 0);
signal BUFFERED_DATA2 : std_logic_vector(0 downto 0);
 
/trunk/src/common/UPDATER.vhd
1,37 → 1,38
-- ***** BEGIN LICENSE BLOCK *****
--
--
-- Version: MPL 1.1/GPL 2.0/LGPL 2.1
--
-- The contents of this file are subject to the Mozilla Public License
-- Version 1.1 (the "License"); you may not use this file except in compliance
-- with the License. You may obtain a copy of the License at
-- http://www.mozilla.org/MPL/
--
-- Software distributed under the License is distributed on an "AS IS" basis,
-- WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
-- the specific language governing rights and limitations under the License.
--
-- The Original Code is BBC Research and Development code.
--
-- The Initial Developer of the Original Code is the British Broadcasting
-- Corporation.
-- Portions created by the Initial Developer are Copyright (C) 2006.
-- All Rights Reserved.
--
-- Contributor(s): Peter Bleackley (Original author)
--
-- Alternatively, the contents of this file may be used under the terms of
-- the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
-- Public License Version 2.1 (the "LGPL"), in which case the provisions of
-- the GPL or the LGPL are applicable instead of those above. If you wish to
-- allow use of your version of this file only under the terms of the either
-- the GPL or LGPL and not to allow others to use your version of this file
-- under the MPL, indicate your decision by deleting the provisions above
-- and replace them with the notice and other provisions required by the GPL
-- or LGPL. If you do not delete the provisions above, a recipient may use
-- your version of this file under the terms of any one of the MPL, the GPL
-- or the LGPL.
-- $Id: UPDATER.vhd,v 1.2 2006-10-05 16:17:11 petebleackley Exp $ $Name: not supported by cvs2svn $
-- *
-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
-- *
-- * The contents of this file are subject to the Mozilla Public License
-- * Version 1.1 (the "License"); you may not use this file except in compliance
-- * with the License. You may obtain a copy of the License at
-- * http://www.mozilla.org/MPL/
-- *
-- * Software distributed under the License is distributed on an "AS IS" basis,
-- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
-- * the specific language governing rights and limitations under the License.
-- *
-- * The Original Code is BBC Research and Development code.
-- *
-- * The Initial Developer of the Original Code is the British Broadcasting
-- * Corporation.
-- * Portions created by the Initial Developer are Copyright (C) 2004.
-- * All Rights Reserved.
-- *
-- * Contributor(s): Peter Bleackley (Original author)
-- *
-- * Alternatively, the contents of this file may be used under the terms of
-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of
-- * the GPL or the LGPL are applicable instead of those above. If you wish to
-- * allow use of your version of this file only under the terms of the either
-- * the GPL or LGPL and not to allow others to use your version of this file
-- * under the MPL, indicate your decision by deleting the provisions above
-- * and replace them with the notice and other provisions required by the GPL
-- * or LGPL. If you do not delete the provisions above, a recipient may use
-- * your version of this file under the terms of any one of the MPL, the GPL
-- * or the LGPL.
-- * ***** END LICENSE BLOCK ***** */
 
library IEEE;
45,25 → 46,24
--use UNISIM.VComponents.all;
 
entity UPDATER is
Port ( NUMERATOR : in std_logic_vector(9 downto 0);
DENOMINATOR : in std_logic_vector(9 downto 0);
Port ( NUMERATOR : in std_logic_vector(7 downto 0);
DENOMINATOR : in std_logic_vector(7 downto 0);
ENABLE : in std_logic;
DATA_IN : in std_logic;
RESET : in std_logic;
CLOCK : in std_logic;
NUMERATOR_OUT : out std_logic_vector(9 downto 0);
DENOMINATOR_OUT : out std_logic_vector(9 downto 0);
NUMERATOR_OUT : out std_logic_vector(7 downto 0);
DENOMINATOR_OUT : out std_logic_vector(7 downto 0);
UPDATE : out std_logic);
end UPDATER;
 
architecture RTL of UPDATER is
signal NUMERATOR1 : std_logic_vector(9 downto 0);
signal NUMERATOR2 : std_logic_vector(9 downto 0);
signal NUMERATOR3 : std_logic_vector(9 downto 0);
signal NUMERATOR4 : std_logic_vector(9 downto 0);
signal DENOMINATOR2 : std_logic_vector(9 downto 0);
signal NUMERATOR1 : std_logic_vector(7 downto 0);
signal NUMERATOR2 : std_logic_vector(7 downto 0);
signal NUMERATOR3 : std_logic_vector(7 downto 0);
signal NUMERATOR4 : std_logic_vector(7 downto 0);
signal DENOMINATOR2 : std_logic_vector(7 downto 0);
signal HALVE_VALUES : std_logic;
signal HALVING_ALLOWED : std_logic;
signal UPDATE_SWITCH : std_logic;
begin
 
71,7 → 71,7
begin
if CLOCK'event and CLOCK='1' then
if RESET='1' then
NUMERATOR1<="0000000001";
NUMERATOR1<="00000001";
else
NUMERATOR1<=NUMERATOR;
end if;
82,9 → 82,9
begin
if CLOCK'event and CLOCK = '1' then
if RESET = '1' then
NUMERATOR2 <= "0000000001";
NUMERATOR2 <= "00000001";
else
NUMERATOR2 <= NUMERATOR + "0000000001";
NUMERATOR2 <= NUMERATOR + "00000001";
end if;
end if;
end process INCREMENT_NUMERATOR;
93,9 → 93,9
begin
if CLOCK'event and CLOCK='1' then
if RESET='1' then
NUMERATOR3 <= "0000000001";
NUMERATOR3 <= "00000001";
else
NUMERATOR3 <= ('0' & NUMERATOR(9 downto 1)) + "0000000001";
NUMERATOR3 <= ('0' & NUMERATOR(7 downto 1)) + "00000001";
end if;
end if;
end process HALVE_NUMERATOR;
104,9 → 104,9
begin
if CLOCK'event and CLOCK='1' then
if RESET='1' then
NUMERATOR4 <= "0000000001";
NUMERATOR4 <= "00000001";
else
NUMERATOR4 <= ('0' & NUMERATOR(9 downto 1)) + "0000000001" + ("000000000" & NUMERATOR(0));
NUMERATOR4 <= ('0' & NUMERATOR(7 downto 1)) + "00000001" + ("0000000" & NUMERATOR(0));
end if;
end if;
end process INCREMENT_AND_HALVE_NUMERATOR;
115,9 → 115,9
begin
if CLOCK'event and CLOCK='1' then
if RESET='1' then
DENOMINATOR2 <= "0000000010";
DENOMINATOR2 <= "00000010";
else
DENOMINATOR2 <= DENOMINATOR + "0000000001";
DENOMINATOR2 <= DENOMINATOR + "00000001";
end if;
end if;
end process INCREMENT_DENOMINATOR;
124,7 → 124,7
 
HALVE_DENOMINATOR : process (DENOMINATOR)
begin
if (DENOMINATOR = "1111111111") then
if (DENOMINATOR = "11111111") then
HALVE_VALUES <= '1';
else
HALVE_VALUES <= '0';
150,13 → 150,13
 
UPDATE_SWITCH <= DATA_IN xor NUMERATOR(0);
 
OUTPUT_DENOMINATOR : process(HALVING_ALLOWED,DENOMINATOR,DENOMINATOR2,UPDATE_SWITCH,HALVE_VALUES,NUMERATOR)
OUTPUT_DENOMINATOR : process(DENOMINATOR,DENOMINATOR2,UPDATE_SWITCH,HALVE_VALUES)
begin
if HALVE_VALUES='1' then
if UPDATE_SWITCH = '1' then
DENOMINATOR_OUT <= "1000000010";
DENOMINATOR_OUT <= "10000010";
else
DENOMINATOR_OUT <= "1000000001";
DENOMINATOR_OUT <= "10000001";
end if;
else
DENOMINATOR_OUT<=DENOMINATOR2;
/trunk/src/common/CONTEXT_MANAGER.vhd
1,6 → 1,6
-- ***** BEGIN LICENSE BLOCK *****
--
-- $Id: CONTEXT_MANAGER.vhd,v 1.2 2006-08-18 14:29:32 petebleackley Exp $ $Name: not supported by cvs2svn $
-- $Id: CONTEXT_MANAGER.vhd,v 1.3 2006-10-05 16:17:11 petebleackley Exp $ $Name: not supported by cvs2svn $
-- *
-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
-- *
53,20 → 53,20
HALVECOUNTS : in std_logic;
RESET : in std_logic;
CLOCK : in std_logic;
PROB : out std_logic_vector(9 downto 0);
PROB : out std_logic_vector(7 downto 0);
READY : out std_logic);
end CONTEXT_MANAGER;
 
architecture RTL of CONTEXT_MANAGER is
type MATRIX is array (45 downto 0) of std_logic_vector(19 downto 0);
signal PROBABILITY : MATRIX;
constant HALF : std_logic_vector(19 downto 0) := "00000000010000000010";
signal FRACTION : std_logic_vector(19 downto 0);
signal FRACTION2 : std_logic_vector(19 downto 0);
signal RESET_FLAGS : std_logic_vector (63 downto 0);
signal NEWPROB : std_logic_vector(19 downto 0);
signal RATIO : std_logic_vector(19 downto 0);
type MATRIX is array (45 downto 0) of std_logic_vector(15 downto 0);
signal PROBABILITY : MATRIX;
constant HALF : std_logic_vector(15 downto 0) := "0000000100000010";
signal FRACTION : std_logic_vector(15 downto 0);
signal FRACTION2 : std_logic_vector(15 downto 0);
signal RESET_FLAGS : std_logic_vector (45 downto 0);
signal NEWPROB : std_logic_vector(15 downto 0);
signal RATIO : std_logic_vector(15 downto 0);
signal UPDATE_PROB : std_logic;
signal PROB_CHANGED : std_logic;
signal LOAD_DATA : std_logic;
77,33 → 77,33
signal DATA_READY : std_logic_vector (1 downto 0);
 
component DIVIDER
port ( NUMERATOR : in std_logic_vector(9 downto 0);
DENOMINATOR : in std_logic_vector(9 downto 0);
port ( NUMERATOR : in std_logic_vector(7 downto 0);
DENOMINATOR : in std_logic_vector(7 downto 0);
RESET : in std_logic;
CLOCK : in std_logic;
QUOTIENT : out std_logic_vector(9 downto 0));
QUOTIENT : out std_logic_vector(7 downto 0));
end component DIVIDER;
component UPDATER
port ( NUMERATOR : in std_logic_vector(9 downto 0);
DENOMINATOR : in std_logic_vector(9 downto 0);
port ( NUMERATOR : in std_logic_vector(7 downto 0);
DENOMINATOR : in std_logic_vector(7 downto 0);
ENABLE : in std_logic;
DATA_IN : in std_logic;
RESET : in std_logic;
CLOCK : in std_logic;
NUMERATOR_OUT : out std_logic_vector(9 downto 0);
DENOMINATOR_OUT : out std_logic_vector(9 downto 0);
NUMERATOR_OUT : out std_logic_vector(7 downto 0);
DENOMINATOR_OUT : out std_logic_vector(7 downto 0);
UPDATE : out std_logic);
end component UPDATER;
component HALVING_MANAGER
port ( TRIGGER_HALVING : in std_logic;
INPUT_READY : in std_logic;
NUMERATOR_IN : in std_logic_vector(9 downto 0);
DENOMINATOR_IN : in std_logic_vector(9 downto 0);
NUMERATOR_IN : in std_logic_vector(7 downto 0);
DENOMINATOR_IN : in std_logic_vector(7 downto 0);
CONTEXT : in std_logic_vector(5 downto 0);
RESET : in std_logic;
CLOCK : in std_logic;
NUMERATOR_OUT : out std_logic_vector(9 downto 0);
DENOMINATOR_OUT : out std_logic_vector(9 downto 0);
NUMERATOR_OUT : out std_logic_vector(7 downto 0);
DENOMINATOR_OUT : out std_logic_vector(7 downto 0);
OUTPUT_READY : out std_logic);
end component HALVING_MANAGER;
 
147,33 → 147,33
 
 
DIVISION : DIVIDER
port map (NUMERATOR => FRACTION2(19 downto 10),
DENOMINATOR => FRACTION2(9 downto 0),
port map (NUMERATOR => FRACTION2(15 downto 8),
DENOMINATOR => FRACTION2(7 downto 0),
RESET => RESET,
CLOCK => CLOCK,
QUOTIENT => PROB);
 
PROBUPDATE : UPDATER
port map (NUMERATOR => FRACTION2(19 downto 10),
DENOMINATOR => FRACTION2(9 downto 0),
port map (NUMERATOR => FRACTION2(15 downto 8),
DENOMINATOR => FRACTION2(7 downto 0),
ENABLE => PROB_CHANGED,
DATA_IN => DATA_IN,
RESET => RESET,
CLOCK => CLOCK,
NUMERATOR_OUT => NEWPROB(19 downto 10),
DENOMINATOR_OUT => NEWPROB(9 downto 0),
NUMERATOR_OUT => NEWPROB(15 downto 8),
DENOMINATOR_OUT => NEWPROB(7 downto 0),
UPDATE => UPDATE_PROB);
 
REFRESH: HALVING_MANAGER
port map (TRIGGER_HALVING => HALVECOUNTS,
INPUT_READY => DATA_FETCHED,
NUMERATOR_IN => FRACTION(19 downto 10),
DENOMINATOR_IN => FRACTION(9 downto 0),
NUMERATOR_IN => FRACTION(15 downto 8),
DENOMINATOR_IN => FRACTION(7 downto 0),
CONTEXT => CONTEXT_NUMBER,
RESET => RESET,
CLOCK => CLOCK,
NUMERATOR_OUT => FRACTION2(19 downto 10),
DENOMINATOR_OUT => FRACTION2(9 downto 0),
NUMERATOR_OUT => FRACTION2(15 downto 8),
DENOMINATOR_OUT => FRACTION2(7 downto 0),
OUTPUT_READY => PROB_CHANGED);
 
 
/trunk/src/common/HALVING_MANAGER.vhd
1,37 → 1,38
-- ***** BEGIN LICENSE BLOCK *****
--
--
-- Version: MPL 1.1/GPL 2.0/LGPL 2.1
--
-- The contents of this file are subject to the Mozilla Public License
-- Version 1.1 (the "License"); you may not use this file except in compliance
-- with the License. You may obtain a copy of the License at
-- http://www.mozilla.org/MPL/
--
-- Software distributed under the License is distributed on an "AS IS" basis,
-- WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
-- the specific language governing rights and limitations under the License.
--
-- The Original Code is BBC Research and Development code.
--
-- The Initial Developer of the Original Code is the British Broadcasting
-- Corporation.
-- Portions created by the Initial Developer are Copyright (C) 2006.
-- All Rights Reserved.
--
-- Contributor(s): Peter Bleackley (Original author)
--
-- Alternatively, the contents of this file may be used under the terms of
-- the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
-- Public License Version 2.1 (the "LGPL"), in which case the provisions of
-- the GPL or the LGPL are applicable instead of those above. If you wish to
-- allow use of your version of this file only under the terms of the either
-- the GPL or LGPL and not to allow others to use your version of this file
-- under the MPL, indicate your decision by deleting the provisions above
-- and replace them with the notice and other provisions required by the GPL
-- or LGPL. If you do not delete the provisions above, a recipient may use
-- your version of this file under the terms of any one of the MPL, the GPL
-- or the LGPL.
-- $Id: HALVING_MANAGER.vhd,v 1.2 2006-10-05 16:17:11 petebleackley Exp $ $Name: not supported by cvs2svn $
-- *
-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
-- *
-- * The contents of this file are subject to the Mozilla Public License
-- * Version 1.1 (the "License"); you may not use this file except in compliance
-- * with the License. You may obtain a copy of the License at
-- * http://www.mozilla.org/MPL/
-- *
-- * Software distributed under the License is distributed on an "AS IS" basis,
-- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
-- * the specific language governing rights and limitations under the License.
-- *
-- * The Original Code is BBC Research and Development code.
-- *
-- * The Initial Developer of the Original Code is the British Broadcasting
-- * Corporation.
-- * Portions created by the Initial Developer are Copyright (C) 2004.
-- * All Rights Reserved.
-- *
-- * Contributor(s): Peter Bleackley (Original author)
-- *
-- * Alternatively, the contents of this file may be used under the terms of
-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of
-- * the GPL or the LGPL are applicable instead of those above. If you wish to
-- * allow use of your version of this file only under the terms of the either
-- * the GPL or LGPL and not to allow others to use your version of this file
-- * under the MPL, indicate your decision by deleting the provisions above
-- * and replace them with the notice and other provisions required by the GPL
-- * or LGPL. If you do not delete the provisions above, a recipient may use
-- * your version of this file under the terms of any one of the MPL, the GPL
-- * or the LGPL.
-- * ***** END LICENSE BLOCK ***** */
 
library IEEE;
47,13 → 48,13
entity HALVING_MANAGER is
Port ( TRIGGER_HALVING : in std_logic;
INPUT_READY : in std_logic;
NUMERATOR_IN : in std_logic_vector(9 downto 0);
DENOMINATOR_IN : in std_logic_vector(9 downto 0);
NUMERATOR_IN : in std_logic_vector(7 downto 0);
DENOMINATOR_IN : in std_logic_vector(7 downto 0);
CONTEXT : in std_logic_vector(5 downto 0);
RESET : in std_logic;
CLOCK : in std_logic;
NUMERATOR_OUT : out std_logic_vector(9 downto 0);
DENOMINATOR_OUT : out std_logic_vector(9 downto 0);
NUMERATOR_OUT : out std_logic_vector(7 downto 0);
DENOMINATOR_OUT : out std_logic_vector(7 downto 0);
OUTPUT_READY : out std_logic);
end HALVING_MANAGER;
 
60,11 → 61,11
architecture RTL of HALVING_MANAGER is
type COUNTARRAY is array(45 downto 0) of std_logic_vector(2 downto 0);
signal SHIFTS : COUNTARRAY;
signal NUMERATOR : std_logic_vector (9 downto 0);
signal DENOMINATOR : std_logic_vector (9 downto 0);
signal NUMERATOR2 : std_logic_vector (9 downto 0);
signal DENOMINATOR2 : std_logic_vector (9 downto 0);
signal DENOMINATOR_INCREMENT : std_logic_vector (9 downto 0);
signal NUMERATOR : std_logic_vector (7 downto 0);
signal DENOMINATOR : std_logic_vector (7 downto 0);
signal NUMERATOR2 : std_logic_vector (7 downto 0);
signal DENOMINATOR2 : std_logic_vector (7 downto 0);
signal DENOMINATOR_INCREMENT : std_logic_vector (7 downto 0);
signal GREATER_THAN_16 : std_logic;
signal PERFORM_HALVING : std_logic;
signal AFTER_TRIGGER : std_logic;
92,15 → 93,15
end if;
end process COUNT_HALVING_EVENTS;
 
NUMERATOR2 <= ('0' & NUMERATOR (9 downto 1)) + "0000000001";
DENOMINATOR2 <= ('0' & DENOMINATOR(9 downto 1)) + DENOMINATOR_INCREMENT;
NUMERATOR2 <= ('0' & NUMERATOR (7 downto 1)) + "0000000001";
DENOMINATOR2 <= ('0' & DENOMINATOR(7 downto 1)) + DENOMINATOR_INCREMENT;
 
HALVE_COUNTS : process (CLOCK)
begin
if CLOCK'event and CLOCK='1' then
if RESET = '1' then
NUMERATOR <= "0000000001";
DENOMINATOR <= "0000000010";
NUMERATOR <= "00000001";
DENOMINATOR <= "00000010";
elsif CALCULATE_VALUES = '1' then
NUMERATOR <= NUMERATOR2;
DENOMINATOR <= DENOMINATOR2;
113,7 → 114,7
 
HALVING_PERMITTED : process (DENOMINATOR)
begin
if DENOMINATOR > "0000010000" then
if DENOMINATOR > "00010000" then
GREATER_THAN_16 <= '1';
else
GREATER_THAN_16 <= '0';
154,9 → 155,9
CHOOSE_DENOMINATOR_INCREMENT : process (NUMERATOR, DENOMINATOR)
begin
if (NUMERATOR (0) = '1') and (DENOMINATOR (0) = '0') then
DENOMINATOR_INCREMENT <= "0000000001";
DENOMINATOR_INCREMENT <= "00000001";
else
DENOMINATOR_INCREMENT <= "0000000010";
DENOMINATOR_INCREMENT <= "00000010";
end if;
end process CHOOSE_DENOMINATOR_INCREMENT;
 
/trunk/src/common/Divider.vhd
1,37 → 1,38
-- ***** BEGIN LICENSE BLOCK *****
--
--
-- Version: MPL 1.1/GPL 2.0/LGPL 2.1
--
-- The contents of this file are subject to the Mozilla Public License
-- Version 1.1 (the "License"); you may not use this file except in compliance
-- with the License. You may obtain a copy of the License at
-- http://www.mozilla.org/MPL/
--
-- Software distributed under the License is distributed on an "AS IS" basis,
-- WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
-- the specific language governing rights and limitations under the License.
--
-- The Original Code is BBC Research and Development code.
--
-- The Initial Developer of the Original Code is the British Broadcasting
-- Corporation.
-- Portions created by the Initial Developer are Copyright (C) 2006.
-- All Rights Reserved.
--
-- Contributor(s): Peter Bleackley (Original author)
--
-- Alternatively, the contents of this file may be used under the terms of
-- the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
-- Public License Version 2.1 (the "LGPL"), in which case the provisions of
-- the GPL or the LGPL are applicable instead of those above. If you wish to
-- allow use of your version of this file only under the terms of the either
-- the GPL or LGPL and not to allow others to use your version of this file
-- under the MPL, indicate your decision by deleting the provisions above
-- and replace them with the notice and other provisions required by the GPL
-- or LGPL. If you do not delete the provisions above, a recipient may use
-- your version of this file under the terms of any one of the MPL, the GPL
-- or the LGPL.
-- $Id: Divider.vhd,v 1.2 2006-10-05 16:17:11 petebleackley Exp $ $Name: not supported by cvs2svn $
-- *
-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
-- *
-- * The contents of this file are subject to the Mozilla Public License
-- * Version 1.1 (the "License"); you may not use this file except in compliance
-- * with the License. You may obtain a copy of the License at
-- * http://www.mozilla.org/MPL/
-- *
-- * Software distributed under the License is distributed on an "AS IS" basis,
-- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
-- * the specific language governing rights and limitations under the License.
-- *
-- * The Original Code is BBC Research and Development code.
-- *
-- * The Initial Developer of the Original Code is the British Broadcasting
-- * Corporation.
-- * Portions created by the Initial Developer are Copyright (C) 2004.
-- * All Rights Reserved.
-- *
-- * Contributor(s): Peter Bleackley (Original author)
-- *
-- * Alternatively, the contents of this file may be used under the terms of
-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of
-- * the GPL or the LGPL are applicable instead of those above. If you wish to
-- * allow use of your version of this file only under the terms of the either
-- * the GPL or LGPL and not to allow others to use your version of this file
-- * under the MPL, indicate your decision by deleting the provisions above
-- * and replace them with the notice and other provisions required by the GPL
-- * or LGPL. If you do not delete the provisions above, a recipient may use
-- * your version of this file under the terms of any one of the MPL, the GPL
-- * or the LGPL.
-- * ***** END LICENSE BLOCK ***** */
 
library IEEE;
45,1051 → 46,280
--use UNISIM.VComponents.all;
 
entity Divider is
Port ( NUMERATOR : in std_logic_vector(9 downto 0);
DENOMINATOR : in std_logic_vector(9 downto 0);
Port ( NUMERATOR : in std_logic_vector(7 downto 0);
DENOMINATOR : in std_logic_vector(7 downto 0);
RESET : in std_logic;
CLOCK : in std_logic;
QUOTIENT : out std_logic_vector(9 downto 0));
QUOTIENT : out std_logic_vector(7 downto 0));
end Divider;
 
architecture RTL of Divider is
signal NUMERATOR2 : std_logic_vector(9 downto 0);
signal DENOMINATOR2 : std_logic_vector( 9 downto 0);
signal RECIPROCAL : std_logic_vector(31 downto 0);
signal PRODUCT1 : std_logic_vector(25 downto 0);
signal PRODUCT2 : std_logic_vector(25 downto 0);
signal TOTAL : std_logic_vector(41 downto 0);
signal INDEX : std_logic_vector (9 downto 0);
type ROM is array (1021 downto 0) of std_logic_vector(31 downto 0);
constant LUT : ROM := ("00000000010000000001000000000100",
"00000000010000000010000000010000",
"00000000010000000011000000100100",
"00000000010000000100000001000000",
"00000000010000000101000001100100",
"00000000010000000110000010010000",
"00000000010000000111000011000101",
"00000000010000001000000100000010",
"00000000010000001001000101000110",
"00000000010000001010000110010011",
"00000000010000001011000111101001",
"00000000010000001100001001000110",
"00000000010000001101001010101100",
"00000000010000001110001100011010",
"00000000010000001111001110010001",
"00000000010000010000010000010000",
"00000000010000010001010010010111",
"00000000010000010010010100100111",
"00000000010000010011010110111111",
"00000000010000010100011001011111",
"00000000010000010101011100001000",
"00000000010000010110011110111010",
"00000000010000010111100001110100",
"00000000010000011000100100110111",
"00000000010000011001101000000010",
"00000000010000011010101011010110",
"00000000010000011011101110110010",
"00000000010000011100110010011000",
"00000000010000011101110110000110",
"00000000010000011110111001111100",
"00000000010000011111111101111100",
"00000000010000100001000010000100",
"00000000010000100010000110010101",
"00000000010000100011001010101110",
"00000000010000100100001111010001",
"00000000010000100101010011111100",
"00000000010000100110011000110001",
"00000000010000100111011101101110",
"00000000010000101000100010110100",
"00000000010000101001101000000100",
"00000000010000101010101101011100",
"00000000010000101011110010111101",
"00000000010000101100111000101000",
"00000000010000101101111110011011",
"00000000010000101111000100011000",
"00000000010000110000001010011110",
"00000000010000110001010000101101",
"00000000010000110010010111000101",
"00000000010000110011011101100110",
"00000000010000110100100100010001",
"00000000010000110101101011000101",
"00000000010000110110110010000010",
"00000000010000110111111001001001",
"00000000010000111001000000011001",
"00000000010000111010000111110010",
"00000000010000111011001111010101",
"00000000010000111100010111000010",
"00000000010000111101011110110111",
"00000000010000111110100110110111",
"00000000010000111111101111000000",
"00000000010001000000110111010010",
"00000000010001000001111111101110",
"00000000010001000011001000010100",
"00000000010001000100010001000100",
"00000000010001000101011001111101",
"00000000010001000110100011000000",
"00000000010001000111101100001101",
"00000000010001001000110101100011",
"00000000010001001001111111000011",
"00000000010001001011001000101110",
"00000000010001001100010010100010",
"00000000010001001101011100100000",
"00000000010001001110100110101000",
"00000000010001001111110000111010",
"00000000010001010000111011010110",
"00000000010001010010000101111100",
"00000000010001010011010000101100",
"00000000010001010100011011100110",
"00000000010001010101100110101010",
"00000000010001010110110001111001",
"00000000010001010111111101010010",
"00000000010001011001001000110101",
"00000000010001011010010100100010",
"00000000010001011011100000011010",
"00000000010001011100101100011100",
"00000000010001011101111000101000",
"00000000010001011111000100111111",
"00000000010001100000010001100000",
"00000000010001100001011110001011",
"00000000010001100010101011000010",
"00000000010001100011111000000010",
"00000000010001100101000101001110",
"00000000010001100110010010100011",
"00000000010001100111100000000100",
"00000000010001101000101101101111",
"00000000010001101001111011100101",
"00000000010001101011001001100110",
"00000000010001101100010111110001",
"00000000010001101101100110000111",
"00000000010001101110110100101001",
"00000000010001110000000011010101",
"00000000010001110001010010001011",
"00000000010001110010100001001101",
"00000000010001110011110000011010",
"00000000010001110100111111110010",
"00000000010001110110001111010101",
"00000000010001110111011111000011",
"00000000010001111000101110111100",
"00000000010001111001111111000001",
"00000000010001111011001111010000",
"00000000010001111100011111101011",
"00000000010001111101110000010001",
"00000000010001111111000001000011",
"00000000010010000000010010000000",
"00000000010010000001100011001000",
"00000000010010000010110100011100",
"00000000010010000100000101111011",
"00000000010010000101010111100110",
"00000000010010000110101001011100",
"00000000010010000111111011011110",
"00000000010010001001001101101011",
"00000000010010001010100000000100",
"00000000010010001011110010101001",
"00000000010010001101000101011001",
"00000000010010001110011000010110",
"00000000010010001111101011011110",
"00000000010010010000111110110010",
"00000000010010010010010010010010",
"00000000010010010011100101111110",
"00000000010010010100111001110101",
"00000000010010010110001101111001",
"00000000010010010111100010001001",
"00000000010010011000110110100101",
"00000000010010011010001011001101",
"00000000010010011011100000000010",
"00000000010010011100110101000010",
"00000000010010011110001010001111",
"00000000010010011111011111101000",
"00000000010010100000110101001110",
"00000000010010100010001011000000",
"00000000010010100011100000111110",
"00000000010010100100110111001001",
"00000000010010100110001101100000",
"00000000010010100111100100000100",
"00000000010010101000111010110101",
"00000000010010101010010001110010",
"00000000010010101011101000111100",
"00000000010010101101000000010010",
"00000000010010101110010111110110",
"00000000010010101111101111100110",
"00000000010010110001000111100011",
"00000000010010110010011111101101",
"00000000010010110011111000000100",
"00000000010010110101010000101000",
"00000000010010110110101001011000",
"00000000010010111000000010010111",
"00000000010010111001011011100010",
"00000000010010111010110100111010",
"00000000010010111100001110100000",
"00000000010010111101101000010010",
"00000000010010111111000010010011",
"00000000010011000000011100100000",
"00000000010011000001110110111011",
"00000000010011000011010001100100",
"00000000010011000100101100011001",
"00000000010011000110000111011101",
"00000000010011000111100010101110",
"00000000010011001000111110001101",
"00000000010011001010011001111001",
"00000000010011001011110101110011",
"00000000010011001101010001111011",
"00000000010011001110101110010001",
"00000000010011010000001010110101",
"00000000010011010001100111100110",
"00000000010011010011000100100110",
"00000000010011010100100001110011",
"00000000010011010101111111001111",
"00000000010011010111011100111001",
"00000000010011011000111010110001",
"00000000010011011010011000110111",
"00000000010011011011110111001100",
"00000000010011011101010101101111",
"00000000010011011110110100100000",
"00000000010011100000010011100000",
"00000000010011100001110010101110",
"00000000010011100011010010001011",
"00000000010011100100110001110110",
"00000000010011100110010001110000",
"00000000010011100111110001111001",
"00000000010011101001010010010000",
"00000000010011101010110010110111",
"00000000010011101100010011101100",
"00000000010011101101110100110000",
"00000000010011101111010110000011",
"00000000010011110000110111100101",
"00000000010011110010011001010110",
"00000000010011110011111011010110",
"00000000010011110101011101100110",
"00000000010011110111000000000100",
"00000000010011111000100010110010",
"00000000010011111010000101110000",
"00000000010011111011101000111101",
"00000000010011111101001100011001",
"00000000010011111110110000000100",
"00000000010100000000010100000000",
"00000000010100000001111000001011",
"00000000010100000011011100100101",
"00000000010100000101000001010000",
"00000000010100000110100110001010",
"00000000010100001000001011010100",
"00000000010100001001110000101110",
"00000000010100001011010110011000",
"00000000010100001100111100010010",
"00000000010100001110100010011100",
"00000000010100010000001000110111",
"00000000010100010001101111100001",
"00000000010100010011010110011100",
"00000000010100010100111101100111",
"00000000010100010110100101000011",
"00000000010100011000001100101111",
"00000000010100011001110100101011",
"00000000010100011011011100111000",
"00000000010100011101000101010110",
"00000000010100011110101110000101",
"00000000010100100000010111000100",
"00000000010100100010000000010100",
"00000000010100100011101001110101",
"00000000010100100101010011100111",
"00000000010100100110111101101010",
"00000000010100101000100111111110",
"00000000010100101010010010100011",
"00000000010100101011111101011010",
"00000000010100101101101000100010",
"00000000010100101111010011111011",
"00000000010100110000111111100110",
"00000000010100110010101011100010",
"00000000010100110100010111101111",
"00000000010100110110000100001110",
"00000000010100110111110000111111",
"00000000010100111001011110000010",
"00000000010100111011001011010111",
"00000000010100111100111000111101",
"00000000010100111110100110110101",
"00000000010101000000010101000000",
"00000000010101000010000011011100",
"00000000010101000011110010001011",
"00000000010101000101100001001100",
"00000000010101000111010000011111",
"00000000010101001001000000000101",
"00000000010101001010101111111101",
"00000000010101001100100000000111",
"00000000010101001110010000100101",
"00000000010101010000000001010101",
"00000000010101010001110010010111",
"00000000010101010011100011101101",
"00000000010101010101010101010101",
"00000000010101010111000111010000",
"00000000010101011000111001011110",
"00000000010101011010101100000000",
"00000000010101011100011110110100",
"00000000010101011110010001111100",
"00000000010101100000000101011000",
"00000000010101100001111001000110",
"00000000010101100011101101001000",
"00000000010101100101100001011110",
"00000000010101100111010110000111",
"00000000010101101001001011000100",
"00000000010101101011000000010101",
"00000000010101101100110101111010",
"00000000010101101110101011110011",
"00000000010101110000100001111111",
"00000000010101110010011000100000",
"00000000010101110100001111010101",
"00000000010101110110000110011111",
"00000000010101110111111101111100",
"00000000010101111001110101101110",
"00000000010101111011101101110101",
"00000000010101111101100110010000",
"00000000010101111111011111000000",
"00000000010110000001011000000101",
"00000000010110000011010001011111",
"00000000010110000101001011001101",
"00000000010110000111000101010001",
"00000000010110001000111111101001",
"00000000010110001010111010010111",
"00000000010110001100110101011010",
"00000000010110001110110000110011",
"00000000010110010000101100100001",
"00000000010110010010101000100100",
"00000000010110010100100100111110",
"00000000010110010110100001101100",
"00000000010110011000011110110001",
"00000000010110011010011100001100",
"00000000010110011100011001111100",
"00000000010110011110011000000011",
"00000000010110100000010110100000",
"00000000010110100010010101010011",
"00000000010110100100010100011100",
"00000000010110100110010011111100",
"00000000010110101000010011110011",
"00000000010110101010010100000000",
"00000000010110101100010100100100",
"00000000010110101110010101011110",
"00000000010110110000010110110000",
"00000000010110110010011000011000",
"00000000010110110100011010011000",
"00000000010110110110011100101111",
"00000000010110111000011111011101",
"00000000010110111010100010100011",
"00000000010110111100100110000000",
"00000000010110111110101001110101",
"00000000010111000000101110000001",
"00000000010111000010110010100101",
"00000000010111000100110111100001",
"00000000010111000110111100110101",
"00000000010111001001000010100001",
"00000000010111001011001000100110",
"00000000010111001101001111000011",
"00000000010111001111010101111000",
"00000000010111010001011101000101",
"00000000010111010011100100101100",
"00000000010111010101101100101011",
"00000000010111010111110101000010",
"00000000010111011001111101110011",
"00000000010111011100000110111101",
"00000000010111011110010000100000",
"00000000010111100000011010011100",
"00000000010111100010100100110010",
"00000000010111100100101111100001",
"00000000010111100110111010101001",
"00000000010111101001000110001100",
"00000000010111101011010010001000",
"00000000010111101101011110011110",
"00000000010111101111101011001110",
"00000000010111110001111000011000",
"00000000010111110100000101111101",
"00000000010111110110010011111011",
"00000000010111111000100010010101",
"00000000010111111010110001001001",
"00000000010111111101000000010111",
"00000000010111111111010000000001",
"00000000011000000001100000000110",
"00000000011000000011110000100101",
"00000000011000000110000001100000",
"00000000011000001000010010110110",
"00000000011000001010100100101000",
"00000000011000001100110110110101",
"00000000011000001111001001011101",
"00000000011000010001011100100010",
"00000000011000010011110000000011",
"00000000011000010110000011111111",
"00000000011000011000011000011000",
"00000000011000011010101101001101",
"00000000011000011101000010011110",
"00000000011000011111011000001101",
"00000000011000100001101110010111",
"00000000011000100100000100111111",
"00000000011000100110011100000011",
"00000000011000101000110011100101",
"00000000011000101011001011100100",
"00000000011000101101100100000000",
"00000000011000101111111100111010",
"00000000011000110010010110010001",
"00000000011000110100110000000110",
"00000000011000110111001010011001",
"00000000011000111001100101001001",
"00000000011000111100000000011000",
"00000000011000111110011100000110",
"00000000011001000000111000010001",
"00000000011001000011010100111100",
"00000000011001000101110010000101",
"00000000011001001000001111101101",
"00000000011001001010101101110100",
"00000000011001001101001100011001",
"00000000011001001111101011011111",
"00000000011001010010001011000011",
"00000000011001010100101011001000",
"00000000011001010111001011101100",
"00000000011001011001101100110000",
"00000000011001011100001110010011",
"00000000011001011110110000010111",
"00000000011001100001010010111100",
"00000000011001100011110110000000",
"00000000011001100110011001100110",
"00000000011001101000111101101100",
"00000000011001101011100010010011",
"00000000011001101110000111011011",
"00000000011001110000101101000101",
"00000000011001110011010011010000",
"00000000011001110101111001111100",
"00000000011001111000100001001010",
"00000000011001111011001000111010",
"00000000011001111101110001001100",
"00000000011010000000011010000000",
"00000000011010000011000011010110",
"00000000011010000101101101001111",
"00000000011010001000010111101011",
"00000000011010001011000010101010",
"00000000011010001101101110001011",
"00000000011010010000011010010000",
"00000000011010010011000110111000",
"00000000011010010101110100000100",
"00000000011010011000100001110011",
"00000000011010011011010000000110",
"00000000011010011101111110111101",
"00000000011010100000101110011001",
"00000000011010100011011110011001",
"00000000011010100110001110111101",
"00000000011010101001000000000110",
"00000000011010101011110001110100",
"00000000011010101110100100000111",
"00000000011010110001010111000000",
"00000000011010110100001010011110",
"00000000011010110110111110100001",
"00000000011010111001110011001011",
"00000000011010111100101000011010",
"00000000011010111111011110010000",
"00000000011011000010010100101100",
"00000000011011000101001011101111",
"00000000011011001000000011011001",
"00000000011011001010111011101001",
"00000000011011001101110100100001",
"00000000011011010000101110000000",
"00000000011011010011101000000110",
"00000000011011010110100010110101",
"00000000011011011001011110001011",
"00000000011011011100011010001010",
"00000000011011011111010110110000",
"00000000011011100010010100000000",
"00000000011011100101010001111000",
"00000000011011101000010000011001",
"00000000011011101011001111100100",
"00000000011011101110001111011000",
"00000000011011110001001111110101",
"00000000011011110100010000111100",
"00000000011011110111010010101110",
"00000000011011111010010101001001",
"00000000011011111101011000001111",
"00000000011100000000011100000000",
"00000000011100000011100000011100",
"00000000011100000110100101100010",
"00000000011100001001101011010100",
"00000000011100001100110001110010",
"00000000011100001111111000111100",
"00000000011100010011000000110001",
"00000000011100010110001001010011",
"00000000011100011001010010100001",
"00000000011100011100011100011100",
"00000000011100011111100111000100",
"00000000011100100010110010011001",
"00000000011100100101111110011011",
"00000000011100101001001011001100",
"00000000011100101100011000101010",
"00000000011100101111100110110110",
"00000000011100110010110101110000",
"00000000011100110110000101011010",
"00000000011100111001010101110010",
"00000000011100111100100110111001",
"00000000011100111111111000110000",
"00000000011101000011001011010110",
"00000000011101000110011110101100",
"00000000011101001001110010110010",
"00000000011101001101000111101001",
"00000000011101010000011101010000",
"00000000011101010011110011101000",
"00000000011101010111001010110010",
"00000000011101011010100010101100",
"00000000011101011101111011011001",
"00000000011101100001010100110111",
"00000000011101100100101111001000",
"00000000011101101000001010001011",
"00000000011101101011100110000001",
"00000000011101101111000010101010",
"00000000011101110010100000000111",
"00000000011101110101111110010111",
"00000000011101111001011101011011",
"00000000011101111100111101010011",
"00000000011110000000011110000000",
"00000000011110000011111111100001",
"00000000011110000111100001111000",
"00000000011110001011000101000100",
"00000000011110001110101001000101",
"00000000011110010010001101111101",
"00000000011110010101110011101011",
"00000000011110011001011010001111",
"00000000011110011101000001101010",
"00000000011110100000101001111100",
"00000000011110100100010011000110",
"00000000011110100111111101001000",
"00000000011110101011101000000001",
"00000000011110101111010011110011",
"00000000011110110011000000011110",
"00000000011110110110101110000010",
"00000000011110111010011100011111",
"00000000011110111110001011110110",
"00000000011111000001111100000111",
"00000000011111000101101101010011",
"00000000011111001001011111011001",
"00000000011111001101010010011010",
"00000000011111010001000110010110",
"00000000011111010100111011001110",
"00000000011111011000110001000010",
"00000000011111011100100111110011",
"00000000011111100000011111100000",
"00000000011111100100011000001010",
"00000000011111101000010001110010",
"00000000011111101100001100011000",
"00000000011111110000000111111100",
"00000000011111110100000100011110",
"00000000011111111000000001111111",
"00000000011111111100000000011111",
"00000000100000000000000000000000",
"00000000100000000100000000100000",
"00000000100000001000000010000000",
"00000000100000001100000100100001",
"00000000100000010000001000000100",
"00000000100000010100001100100111",
"00000000100000011000010010001101",
"00000000100000011100011000110101",
"00000000100000100000100000100000",
"00000000100000100100101001001110",
"00000000100000101000110010111111",
"00000000100000101100111101110101",
"00000000100000110001001001101110",
"00000000100000110101010110101100",
"00000000100000111001100100110000",
"00000000100000111101110011111001",
"00000000100001000010000100001000",
"00000000100001000110010101011101",
"00000000100001001010100111111001",
"00000000100001001110111011011101",
"00000000100001010011010000001000",
"00000000100001010111100101111011",
"00000000100001011011111100110111",
"00000000100001100000010100111100",
"00000000100001100100101110001010",
"00000000100001101001001000100010",
"00000000100001101101100100000101",
"00000000100001110010000000110010",
"00000000100001110110011110101011",
"00000000100001111010111101101111",
"00000000100001111111011110000000",
"00000000100010000011111111011101",
"00000000100010001000100010001000",
"00000000100010001101000110000000",
"00000000100010010001101011000111",
"00000000100010010110010001011100",
"00000000100010011010111001000000",
"00000000100010011111100001110100",
"00000000100010100100001011111000",
"00000000100010101000110111001101",
"00000000100010101101100011110010",
"00000000100010110010010001101010",
"00000000100010110111000000110100",
"00000000100010111011110001010000",
"00000000100011000000100011000000",
"00000000100011000101010110000100",
"00000000100011001010001010011100",
"00000000100011001111000000001000",
"00000000100011010011110111001011",
"00000000100011011000101111100011",
"00000000100011011101101001010010",
"00000000100011100010100100010111",
"00000000100011100111100000110101",
"00000000100011101100011110101011",
"00000000100011110001011101111001",
"00000000100011110110011110100001",
"00000000100011111011100000100011",
"00000000100100000000100100000000",
"00000000100100000101101000111000",
"00000000100100001010101111001100",
"00000000100100001111110110111100",
"00000000100100010101000000001001",
"00000000100100011010001010110011",
"00000000100100011111010110111100",
"00000000100100100100100100100100",
"00000000100100101001110011101011",
"00000000100100101111000100010011",
"00000000100100110100010110011011",
"00000000100100111001101010000101",
"00000000100100111110111111010001",
"00000000100101000100010110000000",
"00000000100101001001101110010010",
"00000000100101001111001000001001",
"00000000100101010100100011100100",
"00000000100101011010000000100101",
"00000000100101011111011111001100",
"00000000100101100100111111011010",
"00000000100101101010100001010000",
"00000000100101110000000100101110",
"00000000100101110101101001110101",
"00000000100101111011010000100101",
"00000000100110000000111001000001",
"00000000100110000110100011001000",
"00000000100110001100001110111010",
"00000000100110010001111100011010",
"00000000100110010111101011100111",
"00000000100110011101011100100010",
"00000000100110100011001111001101",
"00000000100110101001000011100111",
"00000000100110101110111001110010",
"00000000100110110100110001101111",
"00000000100110111010101011011110",
"00000000100111000000100111000000",
"00000000100111000110100100010110",
"00000000100111001100100011100001",
"00000000100111010010100100100001",
"00000000100111011000100111011000",
"00000000100111011110101100000110",
"00000000100111100100110010101101",
"00000000100111101010111011001100",
"00000000100111110001000101100101",
"00000000100111110111010001111010",
"00000000100111111101100000001001",
"00000000101000000011110000010110",
"00000000101000001010000010100000",
"00000000101000010000010110101001",
"00000000101000010110101100110001",
"00000000101000011101000100111001",
"00000000101000100011011111000011",
"00000000101000101001111011001111",
"00000000101000110000011001011110",
"00000000101000110110111001110001",
"00000000101000111101011100001010",
"00000000101001000100000000101001",
"00000000101001001010100111001111",
"00000000101001010001001111111101",
"00000000101001010111111010110101",
"00000000101001011110100111110110",
"00000000101001100101010111000100",
"00000000101001101100001000011101",
"00000000101001110010111100000101",
"00000000101001111001110001111011",
"00000000101010000000101010000000",
"00000000101010000111100100010111",
"00000000101010001110100000111111",
"00000000101010010101011111111010",
"00000000101010011100100001001010",
"00000000101010100011100100101111",
"00000000101010101010101010101010",
"00000000101010110001110010111101",
"00000000101010111000111101101001",
"00000000101011000000001010110000",
"00000000101011000111011010010001",
"00000000101011001110101100001111",
"00000000101011010110000000101011",
"00000000101011011101010111100110",
"00000000101011100100110001000001",
"00000000101011101100001100111110",
"00000000101011110011101011011101",
"00000000101011111011001100100001",
"00000000101100000010110000001011",
"00000000101100001010010110011011",
"00000000101100010001111111010011",
"00000000101100011001101010110101",
"00000000101100100001011001000010",
"00000000101100101001001001111100",
"00000000101100110000111101100011",
"00000000101100111000110011111001",
"00000000101101000000101101000000",
"00000000101101001000101000111001",
"00000000101101010000100111100110",
"00000000101101011000101001001000",
"00000000101101100000101101100000",
"00000000101101101000110100110001",
"00000000101101110000111110111011",
"00000000101101111001001100000000",
"00000000101110000001011100000010",
"00000000101110001001101111000011",
"00000000101110010010000101000011",
"00000000101110011010011110000110",
"00000000101110100010111010001011",
"00000000101110101011011001010110",
"00000000101110110011111011100111",
"00000000101110111100100001000000",
"00000000101111000101001001100100",
"00000000101111001101110101010011",
"00000000101111010110100100010000",
"00000000101111011111010110011100",
"00000000101111101000001011111010",
"00000000101111110001000100101010",
"00000000101111111010000000101111",
"00000000110000000011000000001100",
"00000000110000001100000011000000",
"00000000110000010101001001010000",
"00000000110000011110010010111011",
"00000000110000100111100000000110",
"00000000110000110000110000110000",
"00000000110000111010000100111101",
"00000000110001000011011100101111",
"00000000110001001100111000000111",
"00000000110001010110010111001000",
"00000000110001011111111001110100",
"00000000110001101001100000001100",
"00000000110001110011001010010011",
"00000000110001111100111000001100",
"00000000110010000110101001111000",
"00000000110010010000011111011010",
"00000000110010011010011000110011",
"00000000110010100100010110000111",
"00000000110010101110010111011000",
"00000000110010111000011100100111",
"00000000110011000010100101111000",
"00000000110011001100110011001100",
"00000000110011010111000100100111",
"00000000110011100001011010001010",
"00000000110011101011110011111000",
"00000000110011110110010001110100",
"00000000110100000000110100000000",
"00000000110100001011011010011111",
"00000000110100010110000101010100",
"00000000110100100000110100100000",
"00000000110100101011101000001000",
"00000000110100110110100000001101",
"00000000110101000001011100110010",
"00000000110101001100011101111011",
"00000000110101010111100011101001",
"00000000110101100010101110000000",
"00000000110101101101111101000011",
"00000000110101111001010000110101",
"00000000110110000100101001011001",
"00000000110110010000000110110010",
"00000000110110011011101001000010",
"00000000110110100111010000001101",
"00000000110110110010111100010111",
"00000000110110111110101101100001",
"00000000110111001010100011110001",
"00000000110111010110011111001000",
"00000000110111100010011111101011",
"00000000110111101110100101011100",
"00000000110111111010110000011111",
"00000000111000000111000000111000",
"00000000111000010011010110101001",
"00000000111000011111110001111000",
"00000000111000101100010010100110",
"00000000111000111000111000111000",
"00000000111001000101100100110010",
"00000000111001010010010110011000",
"00000000111001011111001101101100",
"00000000111001101100001010110100",
"00000000111001111001001101110010",
"00000000111010000110010110101100",
"00000000111010010011100101100101",
"00000000111010100000111010100000",
"00000000111010101110010101100100",
"00000000111010111011110110110010",
"00000000111011001001011110010001",
"00000000111011010111001100000011",
"00000000111011100101000000001110",
"00000000111011110010111010110111",
"00000000111100000000111100000000",
"00000000111100001111000011110000",
"00000000111100011101010010001011",
"00000000111100101011100111010110",
"00000000111100111010000011010101",
"00000000111101001000100110001101",
"00000000111101010111010000000011",
"00000000111101100110000000111101",
"00000000111101110100111000111111",
"00000000111110000011111000001111",
"00000000111110010010111110110010",
"00000000111110100010001100101100",
"00000000111110110001100010000101",
"00000000111111000000111111000000",
"00000000111111010000100011100101",
"00000000111111100000001111111000",
"00000000111111110000000011111111",
"00000001000000000000000000000000",
"00000001000000010000000100000001",
"00000001000000100000010000001000",
"00000001000000110000100100011011",
"00000001000001000001000001000001",
"00000001000001010001100101111111",
"00000001000001100010010011011101",
"00000001000001110011001001100000",
"00000001000010000100001000010000",
"00000001000010010101001111110011",
"00000001000010100110100000010000",
"00000001000010110111111001101110",
"00000001000011001001011100010100",
"00000001000011011011001000001010",
"00000001000011101100111101010110",
"00000001000011111110111100000001",
"00000001000100010001000100010001",
"00000001000100100011010110001110",
"00000001000100110101110010000001",
"00000001000101001000010111110000",
"00000001000101011011000111100101",
"00000001000101101110000001101000",
"00000001000110000001000110000001",
"00000001000110010100010100111000",
"00000001000110100111101110010110",
"00000001000110111011010010100100",
"00000001000111001111000001101010",
"00000001000111100010111011110011",
"00000001000111110111000001000111",
"00000001001000001011010001110000",
"00000001001000011111101101111000",
"00000001001000110100010101100111",
"00000001001001001001001001001001",
"00000001001001011110001000100111",
"00000001001001110011010100001011",
"00000001001010001000101100000001",
"00000001001010011110010000010010",
"00000001001010110100000001001010",
"00000001001011001001111110110100",
"00000001001011100000001001011100",
"00000001001011110110100001001011",
"00000001001100001101000110010000",
"00000001001100100011111000110100",
"00000001001100111010111001000101",
"00000001001101010010000111001111",
"00000001001101101001100011011111",
"00000001001110000001001110000001",
"00000001001110011001000111000010",
"00000001001110110001001110110001",
"00000001001111001001100101011010",
"00000001001111100010001011001011",
"00000001001111111011000000010011",
"00000001010000010100000101000001",
"00000001010000101101011001100010",
"00000001010001000110111110000110",
"00000001010001100000110010111100",
"00000001010001111010111000010100",
"00000001010010010101001110011110",
"00000001010010101111110101101010",
"00000001010011001010101110001000",
"00000001010011100101111000001010",
"00000001010100000001010100000001",
"00000001010100011101000001111110",
"00000001010100111001000010010100",
"00000001010101010101010101010101",
"00000001010101110001111011010011",
"00000001010110001110110100100011",
"00000001010110101100000001010110",
"00000001010111001001100010000010",
"00000001010111100111010110111011",
"00000001011000000101100000010110",
"00000001011000100011111110100111",
"00000001011001000010110010000101",
"00000001011001100001111011000110",
"00000001011010000001011010000001",
"00000001011010100001001111001101",
"00000001011011000001011011000001",
"00000001011011100001111101110110",
"00000001011100000010111000000101",
"00000001011100100100001010000111",
"00000001011101000101110100010111",
"00000001011101100111110111001110",
"00000001011110001010010011001000",
"00000001011110101101001000100000",
"00000001011111010000010111110100",
"00000001011111110100000001011111",
"00000001100000011000000110000001",
"00000001100000111100100101110111",
"00000001100001100001100001100001",
"00000001100010000110111001011111",
"00000001100010101100101110010000",
"00000001100011010011000000011000",
"00000001100011111001110000011000",
"00000001100100100000111110110100",
"00000001100101001000101100001111",
"00000001100101110000111001001111",
"00000001100110011001100110011001",
"00000001100111000010110100010100",
"00000001100111101100100011101001",
"00000001101000010110110100111111",
"00000001101001000001101001000001",
"00000001101001101101000000011010",
"00000001101010011000111011110110",
"00000001101011000101011100000001",
"00000001101011110010100001101011",
"00000001101100100000001101100100",
"00000001101101001110100000011011",
"00000001101101111101011011000011",
"00000001101110101100111110010001",
"00000001101111011101001010111000",
"00000001110000001110000001110000",
"00000001110000111111100011110000",
"00000001110001110001110001110001",
"00000001110010100100101100110000",
"00000001110011011000010101101000",
"00000001110100001100101101011000",
"00000001110101000001110101000001",
"00000001110101110111101101100101",
"00000001110110101110011000000111",
"00000001110111100101110101101110",
"00000001111000011110000111100001",
"00000001111001010111001110101100",
"00000001111010010001001100011010",
"00000001111011001100000001111011",
"00000001111100000111110000011111",
"00000001111101000100011001011001",
"00000001111110000001111110000001",
"00000001111111000000011111110000",
"00000010000000000000000000000000",
"00000010000001000000100000010000",
"00000010000010000010000010000010",
"00000010000011000100100110111010",
"00000010000100001000010000100001",
"00000010000101001101000000100001",
"00000010000110010010111000101001",
"00000010000111011001111010101101",
"00000010001000100010001000100010",
"00000010001001101011100100000010",
"00000010001010110110001111001011",
"00000010001100000010001100000010",
"00000010001101001111011100101100",
"00000010001110011110000011010101",
"00000010001111101110000010001111",
"00000010010000111111011011110000",
"00000010010010010010010010010010",
"00000010010011100110101000010111",
"00000010010100111100100000100101",
"00000010010110010011111101101001",
"00000010010111101101000010010111",
"00000010011001000111110001101001",
"00000010011010100100001110011111",
"00000010011100000010011100000010",
"00000010011101100010011101100010",
"00000010011111000100010110010111",
"00000010100000101000001010000010",
"00000010100010001101111100001100",
"00000010100011110101110000101000",
"00000010100101011111101011010100",
"00000010100111001011110000010100",
"00000010101000111010000011111101",
"00000010101010101010101010101010",
"00000010101100011101101001000110",
"00000010101110010011000100000101",
"00000010110000001011000000101100",
"00000010110010000101100100001011",
"00000010110100000010110100000010",
"00000010110110000010110110000010",
"00000010111000000101110000001011",
"00000010111010001011101000101110",
"00000010111100010100100110010000",
"00000010111110100000101111101000",
"00000011000000110000001100000011",
"00000011000011000011000011000011",
"00000011000101011001011100100001",
"00000011000111110011100000110001",
"00000011001010010001011000011111",
"00000011001100110011001100110011",
"00000011001111011001000111010010",
"00000011010010000011010010000011",
"00000011010100110001110111101100",
"00000011010111100101000011010111",
"00000011011010011101000000110110",
"00000011011101011001111100100010",
"00000011100000011100000011100000",
"00000011100011100011100011100011",
"00000011100110110000101011010001",
"00000011101010000011101010000011",
"00000011101101011100110000001110",
"00000011110000111100001111000011",
"00000011110100100010011000110101",
"00000011111000001111100000111110",
"00000011111100000011111100000011",
"00000100000000000000000000000000",
"00000100000100000100000100000100",
"00000100001000010000100001000010",
"00000100001100100101110001010011",
"00000100010001000100010001000100",
"00000100010101101100011110010111",
"00000100011010011110111001011000",
"00000100011111011100000100011111",
"00000100100100100100100100100100",
"00000100101001111001000001001010",
"00000100101111011010000100101111",
"00000100110101001000011100111110",
"00000100111011000100111011000100",
"00000101000001010000010100000101",
"00000101000111101011100001010001",
"00000101001110010111100000101001",
"00000101010101010101010101010101",
"00000101011100100110001000001010",
"00000101100100001011001000010110",
"00000101101100000101101100000101",
"00000101110100010111010001011101",
"00000101111101000001011111010000",
"00000110000110000110000110000110",
"00000110001111100111000001100011",
"00000110011001100110011001100110",
"00000110100100000110100100000110",
"00000110101111001010000110101111",
"00000110111010110011111001000101",
"00000111000111000111000111000111",
"00000111010100000111010100000111",
"00000111100001111000011110000111",
"00000111110000011111000001111100",
"00001000000000000000000000000000",
"00001000010000100001000010000100",
"00001000100010001000100010001000",
"00001000110100111101110010110000",
"00001001001001001001001001001001",
"00001001011110110100001001011110",
"00001001110110001001110110001001",
"00001010001111010111000010100011",
"00001010101010101010101010101010",
"00001011001000010110010000101100",
"00001011101000101110100010111010",
"00001100001100001100001100001100",
"00001100110011001100110011001100",
"00001101011110010100001101011110",
"00001110001110001110001110001110",
"00001111000011110000111100001111",
"00010000000000000000000000000000",
"00010001000100010001000100010001",
"00010010010010010010010010010010",
"00010011101100010011101100010011",
"00010101010101010101010101010101",
"00010111010001011101000101110100",
"00011001100110011001100110011001",
"00011100011100011100011100011100",
"00100000000000000000000000000000",
"00100100100100100100100100100100",
"00101010101010101010101010101010",
"00110011001100110011001100110011",
"01000000000000000000000000000000",
"01010101010101010101010101010101",
"10000000000000000000000000000000"
);
signal NUMERATOR2 : std_logic_vector(7 downto 0);
signal DENOMINATOR2 : std_logic_vector(7 downto 0);
signal RECIPROCAL : std_logic_vector(15 downto 0);
signal PRODUCT : std_logic_vector(23 downto 0);
signal INDEX : std_logic_vector (7 downto 0);
type ROM is array (253 downto 0) of std_logic_vector(15 downto 0);
constant LUT : ROM := ( "0000000100000001",
"0000000100000010",
"0000000100000011",
"0000000100000100",
"0000000100000101",
"0000000100000110",
"0000000100000111",
"0000000100001000",
"0000000100001001",
"0000000100001010",
"0000000100001011",
"0000000100001101",
"0000000100001110",
"0000000100001111",
"0000000100010000",
"0000000100010001",
"0000000100010010",
"0000000100010011",
"0000000100010101",
"0000000100010110",
"0000000100010111",
"0000000100011000",
"0000000100011001",
"0000000100011010",
"0000000100011100",
"0000000100011101",
"0000000100011110",
"0000000100011111",
"0000000100100001",
"0000000100100010",
"0000000100100011",
"0000000100100101",
"0000000100100110",
"0000000100100111",
"0000000100101001",
"0000000100101010",
"0000000100101011",
"0000000100101101",
"0000000100101110",
"0000000100101111",
"0000000100110001",
"0000000100110010",
"0000000100110100",
"0000000100110101",
"0000000100110111",
"0000000100111000",
"0000000100111010",
"0000000100111011",
"0000000100111101",
"0000000100111110",
"0000000101000000",
"0000000101000001",
"0000000101000011",
"0000000101000100",
"0000000101000110",
"0000000101001000",
"0000000101001001",
"0000000101001011",
"0000000101001101",
"0000000101001110",
"0000000101010000",
"0000000101010010",
"0000000101010100",
"0000000101010101",
"0000000101010111",
"0000000101011001",
"0000000101011011",
"0000000101011101",
"0000000101011110",
"0000000101100000",
"0000000101100010",
"0000000101100100",
"0000000101100110",
"0000000101101000",
"0000000101101010",
"0000000101101100",
"0000000101101110",
"0000000101110000",
"0000000101110010",
"0000000101110100",
"0000000101110110",
"0000000101111001",
"0000000101111011",
"0000000101111101",
"0000000101111111",
"0000000110000010",
"0000000110000100",
"0000000110000110",
"0000000110001000",
"0000000110001011",
"0000000110001101",
"0000000110010000",
"0000000110010010",
"0000000110010101",
"0000000110010111",
"0000000110011010",
"0000000110011100",
"0000000110011111",
"0000000110100001",
"0000000110100100",
"0000000110100111",
"0000000110101010",
"0000000110101100",
"0000000110101111",
"0000000110110010",
"0000000110110101",
"0000000110111000",
"0000000110111011",
"0000000110111110",
"0000000111000001",
"0000000111000100",
"0000000111000111",
"0000000111001010",
"0000000111001110",
"0000000111010001",
"0000000111010100",
"0000000111010111",
"0000000111011011",
"0000000111011110",
"0000000111100010",
"0000000111100101",
"0000000111101001",
"0000000111101101",
"0000000111110000",
"0000000111110100",
"0000000111111000",
"0000000111111100",
"0000001000000000",
"0000001000000100",
"0000001000001000",
"0000001000001100",
"0000001000010001",
"0000001000010101",
"0000001000011001",
"0000001000011110",
"0000001000100010",
"0000001000100111",
"0000001000101011",
"0000001000110000",
"0000001000110101",
"0000001000111010",
"0000001000111111",
"0000001001000100",
"0000001001001001",
"0000001001001110",
"0000001001010100",
"0000001001011001",
"0000001001011111",
"0000001001100100",
"0000001001101010",
"0000001001110000",
"0000001001110110",
"0000001001111100",
"0000001010000011",
"0000001010001001",
"0000001010001111",
"0000001010010110",
"0000001010011101",
"0000001010100100",
"0000001010101011",
"0000001010110010",
"0000001010111001",
"0000001011000001",
"0000001011001000",
"0000001011010000",
"0000001011011000",
"0000001011100000",
"0000001011101001",
"0000001011110001",
"0000001011111010",
"0000001100000011",
"0000001100001100",
"0000001100010110",
"0000001100011111",
"0000001100101001",
"0000001100110011",
"0000001100111110",
"0000001101001000",
"0000001101010011",
"0000001101011110",
"0000001101101010",
"0000001101110110",
"0000001110000010",
"0000001110001110",
"0000001110011011",
"0000001110101000",
"0000001110110110",
"0000001111000100",
"0000001111010010",
"0000001111100001",
"0000001111110000",
"0000010000000000",
"0000010000010000",
"0000010000100001",
"0000010000110010",
"0000010001000100",
"0000010001010111",
"0000010001101010",
"0000010001111110",
"0000010010010010",
"0000010010101000",
"0000010010111110",
"0000010011010101",
"0000010011101100",
"0000010100000101",
"0000010100011111",
"0000010100111001",
"0000010101010101",
"0000010101110010",
"0000010110010001",
"0000010110110000",
"0000010111010001",
"0000010111110100",
"0000011000011000",
"0000011000111110",
"0000011001100110",
"0000011010010000",
"0000011010111101",
"0000011011101011",
"0000011100011100",
"0000011101010000",
"0000011110001000",
"0000011111000010",
"0000100000000000",
"0000100001000010",
"0000100010001001",
"0000100011010100",
"0000100100100101",
"0000100101111011",
"0000100111011001",
"0000101000111101",
"0000101010101011",
"0000101100100001",
"0000101110100011",
"0000110000110001",
"0000110011001101",
"0000110101111001",
"0000111000111001",
"0000111100001111",
"0001000000000000",
"0001000100010001",
"0001001001001001",
"0001001110110001",
"0001010101010101",
"0001011101000110",
"0001100110011010",
"0001110001110010",
"0010000000000000",
"0010010010010010",
"0010101010101011",
"0011001100110011",
"0100000000000000",
"0101010101010101",
"1000000000000000");
begin
 
INIT : process(DENOMINATOR,RESET)
begin
if RESET = '1' then
DENOMINATOR2 <= "0000000010";
DENOMINATOR2 <= "00000010";
else
DENOMINATOR2 <= DENOMINATOR;
end if;
1099,7 → 329,7
begin
if CLOCK'event and CLOCK = '1' then
if RESET = '1' then
NUMERATOR2 <= "0000000001";
NUMERATOR2 <= "00000001";
else
NUMERATOR2 <= NUMERATOR;
end if;
1107,7 → 337,7
end process SETNUMERATOR;
 
INDEX <= DENOMINATOR2 - "0000000010";
INDEX <= DENOMINATOR2 - "00000010";
 
LOOKUP: process(CLOCK)
begin
1116,22 → 346,15
end if;
end process LOOKUP;
 
DIVIDE1: process(CLOCK)
DIVIDE: process(CLOCK)
begin
if CLOCK'event and CLOCK='1' then
PRODUCT1<=NUMERATOR2*RECIPROCAL(31 downto 16);
PRODUCT<=NUMERATOR2*RECIPROCAL;
end if;
end process DIVIDE1;
end process DIVIDE;
 
DIVIDE2: process(CLOCK)
begin
if CLOCK'event and CLOCK='1' then
PRODUCT2<=NUMERATOR2*RECIPROCAL(15 downto 0);
end if;
end process DIVIDE2;
 
TOTAL<=((PRODUCT1 & "0000000000000000") + ("0000000000000000" & PRODUCT2));
QUOTIENT <= TOTAL(31 downto 22);
QUOTIENT <= PRODUCT(15 downto 8);
 
 
end RTL;
/trunk/src/common/ARITHMETIC_UNIT.vhd
1,6 → 1,6
-- ***** BEGIN LICENSE BLOCK *****
--
-- $Id: ARITHMETIC_UNIT.vhd,v 1.3 2005-05-27 16:00:28 petebleackley Exp $ $Name: not supported by cvs2svn $
-- $Id: ARITHMETIC_UNIT.vhd,v 1.4 2006-10-05 16:17:11 petebleackley Exp $ $Name: not supported by cvs2svn $
-- *
-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
-- *
20,7 → 20,7
-- * Portions created by the Initial Developer are Copyright (C) 2004.
-- * All Rights Reserved.
-- *
 
-- * Contributor(s): Peter Bleackley (Original author)
-- *
-- * Alternatively, the contents of this file may be used under the terms of
-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
35,7 → 35,6
-- * or the LGPL.
-- * ***** END LICENSE BLOCK ***** */
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
47,9 → 46,9
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity ARITHMETIC_UNIT is
entity ARITHMETIC_UNIT is
Port ( DIFFERENCE : in std_logic_vector(15 downto 0);
PROB : in std_logic_vector(9 downto 0);
PROB : in std_logic_vector(7 downto 0);
LOW : in std_logic_vector(15 downto 0);
ENABLE : in std_logic;
RESET : in std_logic;
64,7 → 63,7
architecture RTL of ARITHMETIC_UNIT is
 
signal LOW2 : std_logic_vector(16 downto 0);
signal PRODUCT : std_logic_vector (26 downto 0);
signal PRODUCT : std_logic_vector (24 downto 0);
signal PRODUCT2 : std_logic_vector (16 downto 0);
signal RESULT : std_logic_vector (16 downto 0);
signal RESULT0 : std_logic_vector (16 downto 0);
73,19 → 72,22
signal DIFFERENCE3 : std_logic_vector(16 downto 0);
signal DIFFERENCE4 : std_logic_vector(16 downto 0);
signal DELAY1 : std_logic;
signal DELAY2 : std_logic;
-- signal DELAY2 : std_logic;
signal CALCULATE : std_logic;
begin
 
-- The arithmetic
DIFFERENCE2 <= ('0' & DIFFERENCE) + "00000000000000001";
MULTIPLY : process (CLOCK, DIFFERENCE2, PROB)
MULTIPLY : process (CLOCK)
begin
if CLOCK'event and CLOCK = '1' then
PRODUCT <= DIFFERENCE2 * PROB;
if ENABLE = '1' then
PRODUCT <= DIFFERENCE2 * PROB;
end if;
end if;
end process MULTIPLY;
PRODUCT2 <= PRODUCT(26 downto 10);
end process MULTIPLY;
 
PRODUCT2 <= PRODUCT(24 downto 8);
RESULT <= LOW2 + PRODUCT2;
RESULT_OUT1 <= RESULT(15 downto 0);
RESULT0 <= (RESULT - "00000000000000001");
93,13 → 95,13
DIFFERENCE3 <= (PRODUCT2 - "00000000000000001");
DIFFERENCE4 <= (DIFFERENCE1 - PRODUCT2);
DIFFERENCE_OUT1 <= DIFFERENCE4(15 downto 0);
DIFFERENCE_OUT0 <= DIFFERENCE3(15 downto 0);
 
 
 
 
-- Control logic
CALCULATE <= ENABLE and not RESET;
DATA_LOAD <= DELAY1 and DELAY2;
DATA_LOAD <= DELAY1;-- and DELAY2;
 
-- Sequential control logic
 
107,10 → 109,12
begin
if CLOCK'event and CLOCK = '1' then
DELAY1 <= CALCULATE;
DELAY2 <= DELAY1;
DIFFERENCE1 <= '0' & DIFFERENCE;
LOW2 <= '0' & LOW;
DIFFERENCE_OUT0 <= DIFFERENCE3(15 downto 0);
-- DELAY2 <= DELAY1;
if ENABLE = '1' then
DIFFERENCE1 <= '0' & DIFFERENCE;
LOW2 <= '0' & LOW;
end if;
 
end if;
end process DELAYS;
 
/trunk/src/expgolomb/EXP_GOLOMB_DECODER.vhd
33,6 → 33,8
-- your version of this file under the terms of any one of the MPL, the GPL
-- or the LGPL.
-- * ***** END LICENSE BLOCK ***** */
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
53,11 → 55,7
end EXP_GOLOMB_DECODER;
 
architecture RTL of EXP_GOLOMB_DECODER is
signal DATA_1 : std_logic_vector(31 downto 0);
signal DATA_2 : std_logic_vector(31 downto 0);
signal SUM : std_logic_vector(31 downto 0);
signal NUMBITS_1 : std_logic_vector(4 downto 0);
signal NUMBITS_2 : std_logic_vector(4 downto 0);
signal DATA : std_logic_vector(31 downto 0);
signal MODE : std_logic;
signal CALC_COMPLETE : std_logic;
begin
66,38 → 64,29
begin
if CLOCK'event and CLOCK = '1' then --WHEN CLOCK EDGE DETECTED
if RESET = '1' then --SET ALL REGISTERS TO ZERO
DATA_1 <= (others => '0');
DATA_2 <= (others => '0');
NUMBITS_1 <= (others => '0');
NUMBITS_2 <= (others => '0');
DATA <= ((0)=>'1', others => '0');
DATA_OUT <= (others => '0');
CALC_COMPLETE <= '0';
MODE <= '0';
elsif CALC_COMPLETE = '1' then
DATA <= ((0)=> '1',others => '0');
CALC_COMPLETE <= '0';
elsif CALC_COMPLETE = '1' then
DATA_1 <= (others => '0');
DATA_2 <= (others => '0');
NUMBITS_1 <= (others => '0');
NUMBITS_2 <= (others => '0');
MODE <= '0';
CALC_COMPLETE <= '0';
elsif (NUMBITS_2 = NUMBITS_1) and (MODE = '1') then --IF CALCULATION IS COMPLETE
DATA_OUT <= SUM;
CALC_COMPLETE <= '1';
elsif ENABLE = '1' then --IF DATA IS BEING INPUT
if MODE = '1' then --READ INPUT DATA INTO REGISTER DATA_2, AND COUNT THE NUMBER OF BITS READ IN
DATA_2 <= DATA_2 (30 downto 0) & DATA_IN;
NUMBITS_2 <= NUMBITS_2 + "00001";
elsif DATA_IN = '1' then --DETECT END OF EXPONENT, SWITCH TO MODE 1, FOR READING DATA
if MODE = '0' then --FOR "FOLLOW_ON" BITS
CALC_COMPLETE <= DATA_IN;
MODE <= '1';
else --IN MODE 0 (FOR READING EXPONENT)
DATA_1 <= DATA_1 (30 downto 0) & '1';
NUMBITS_1 <= NUMBITS_1 + "00001";
if DATA_IN = '1' then
DATA_OUT <= DATA - "00000000000000000000000000000001";
end if;
else --IN MODE 1 (FOR DATA_BITS)
DATA <= DATA (30 downto 0) & DATA_IN;
MODE <= '0';
end if;
end if;
end if;
end process READ_DATA;
 
SUM <= DATA_1 + DATA_2;
READY <= CALC_COMPLETE;
 
end RTL;
/trunk/src/expgolomb/EXP_GOLOMB_COUNTER.vhd
55,9 → 55,9
 
architecture RTL of EXP_GOLOMB_COUNTER is
signal DATA2 : std_logic_vector (32 downto 0);
signal LOG : std_logic_vector (5 downto 0);
signal OUT_ADDRESS : std_logic_vector( 5 downto 0);
signal UPDOWN : std_logic;
signal LOG : std_logic_vector (4 downto 0);
signal OUT_ADDRESS : std_logic_vector( 4 downto 0);
signal MODE : std_logic;
signal OUTPUT_ACTIVE : std_logic;
begin
 
67,110 → 67,100
begin
if CLOCK'event and CLOCK = '1' then
if DATA2(32) = '1' then
LOG <= "100000";
LOG <= "11111";
elsif DATA2(31) = '1' then
LOG <= "011111";
LOG <= "11110";
elsif DATA2(30) = '1' then
LOG <= "011110";
LOG <= "11101";
elsif DATA2(29) = '1' then
LOG <= "011101";
LOG <= "11100";
elsif DATA2(28) = '1' then
LOG <= "011100";
LOG <= "11011";
elsif DATA2(27) = '1' then
LOG <= "011011";
LOG <= "11010";
elsif DATA2(26) = '1' then
LOG <= "011010";
LOG <= "11001";
elsif DATA2(25) = '1' then
LOG <= "011001";
LOG <= "11000";
elsif DATA2(24) = '1' then
LOG <= "011000";
LOG <= "10111";
elsif DATA2(23) = '1' then
LOG <= "010111";
LOG <= "10110";
elsif DATA2(22) = '1' then
LOG <= "010110";
LOG <= "10101";
elsif DATA2(21) = '1' then
LOG <= "010101";
LOG <= "10100";
elsif DATA2(20) = '1' then
LOG <= "010100";
LOG <= "10011";
elsif DATA2(19) = '1' then
LOG <= "010011";
LOG <= "10010";
elsif DATA2(18) = '1' then
LOG <= "010010";
LOG <= "10001";
elsif DATA2(17) = '1' then
LOG <= "010001";
LOG <= "10000";
elsif DATA2(16) = '1' then
LOG <= "010000";
LOG <= "01111";
elsif DATA2(15) = '1' then
LOG <= "001111";
LOG <= "01110";
elsif DATA2(14) = '1' then
LOG <= "001110";
LOG <= "01101";
elsif DATA2(13) = '1' then
LOG <= "001101";
LOG <= "01100";
elsif DATA2(12) = '1' then
LOG <= "001100";
LOG <= "01011";
elsif DATA2(11) = '1' then
LOG <= "001011";
LOG <= "01010";
elsif DATA2(10) = '1' then
LOG <= "001010";
LOG <= "01001";
elsif DATA2(9) = '1' then
LOG <= "001001";
LOG <= "01000";
elsif DATA2(8) = '1' then
LOG <= "001000";
LOG <= "00111";
elsif DATA2(7) = '1' then
LOG <= "000111";
LOG <= "00110";
elsif DATA2(6) = '1' then
LOG <= "000110";
LOG <= "00101";
elsif DATA2(5) = '1' then
LOG <= "000101";
LOG <= "00100";
elsif DATA2(4) = '1' then
LOG <= "000100";
LOG <= "00011";
elsif DATA2(3) = '1' then
LOG <= "000011";
LOG <= "00010";
elsif DATA2(2) = '1' then
LOG <= "000010";
elsif DATA2(1) = '1' then
LOG <= "000001";
LOG <= "00001";
else
LOG <= "000000";
LOG <= "00000";
end if;
end if;
end process LOGARITHM;
 
 
MODE : process (CLOCK)
begin
if CLOCK'event and CLOCK = '1' then
if RESET = '1' then
OUTPUT_ACTIVE <= '0';
elsif TEST = '1' then
OUTPUT_ACTIVE <= '1';
elsif OUT_ADDRESS = "000000" then
OUTPUT_ACTIVE <= '0';
end if;
end if;
end process MODE;
 
 
OUTPUT: process (CLOCK)
begin
if CLOCK'event and CLOCK = '1' then
if RESET = '1' then
UPDOWN <= '0';
OUT_ADDRESS <= "000000";
MODE <= '0';
OUT_ADDRESS <= "00000";
DATA_OUT <= '0';
OUTPUT_ACTIVE <= '0';
elsif OUTPUT_ACTIVE = '1' then
if UPDOWN = '0' then
if OUT_ADDRESS = LOG then
if MODE = '1' then
DATA_OUT <= DATA2(conv_integer(OUT_ADDRESS));
MODE <= '0';
else
if OUT_ADDRESS = "00000" then
DATA_OUT <= '1';
UPDOWN <= '1';
OUTPUT_ACTIVE <= '0';
else
DATA_OUT <= '0';
OUT_ADDRESS <= OUT_ADDRESS + "000001";
OUT_ADDRESS <= OUT_ADDRESS - "00001";
MODE <= '1';
end if;
else
OUT_ADDRESS <= OUT_ADDRESS - "000001";
DATA_OUT <= DATA2(conv_integer(OUT_ADDRESS));
end if;
elsif TEST = '1' then
OUTPUT_ACTIVE <= '1';
OUT_ADDRESS <= LOG;
MODE <= '0';
end if;
end if;
end process OUTPUT;
/trunk/docs/Specification/DiracSpec0.10.1.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/docs/Specification/DiracSpec0.10.1.pdf
trunk/docs/Specification/DiracSpec0.10.1.pdf Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/docs/synthesis_reports/encoder/arithmeticcoder.syr =================================================================== --- trunk/docs/synthesis_reports/encoder/arithmeticcoder.syr (revision 9) +++ trunk/docs/synthesis_reports/encoder/arithmeticcoder.syr (revision 10) @@ -1,10 +1,10 @@ Release 7.1.04i - xst H.42 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to __projnav -CPU : 0.00 / 0.34 s | Elapsed : 0.00 / 0.00 s +CPU : 0.00 / 0.36 s | Elapsed : 0.00 / 0.00 s --> Parameter xsthdpdir set to ./xst -CPU : 0.00 / 0.34 s | Elapsed : 0.00 / 0.00 s +CPU : 0.00 / 0.36 s | Elapsed : 0.00 / 0.00 s --> Reading design: arithmeticcoder.prj @@ -98,8 +98,7 @@ Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/Divider.vhd" in Library work. Architecture rtl of Entity divider is up to date. Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/UPDATER.vhd" in Library work. -Entity compiled. -Entity (Architecture ) compiled. +Architecture rtl of Entity updater is up to date. Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" in Library work. Architecture rtl of Entity halving_manager is up to date. Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/FIFO.vhd" in Library work. @@ -166,12 +165,14 @@ Entity analyzed. Unit generated. Analyzing Entity (Architecture ). +WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/CONTEXT_MANAGER.vhd" line 118: Index value(s) does not match array range, simulation mismatch. WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/CONTEXT_MANAGER.vhd" line 133: Index value(s) does not match array range, simulation mismatch. WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/CONTEXT_MANAGER.vhd" line 137: Index value(s) does not match array range, simulation mismatch. +WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/CONTEXT_MANAGER.vhd" line 141: Index value(s) does not match array range, simulation mismatch. Entity analyzed. Unit generated. Analyzing Entity (Architecture ). -WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/Divider.vhd" line 1079: Index value(s) does not match array range, simulation mismatch. +WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/Divider.vhd" line 308: Index value(s) does not match array range, simulation mismatch. Entity analyzed. Unit generated. Analyzing Entity (Architecture ). @@ -181,6 +182,7 @@ WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" line 71: Index value(s) does not match array range, simulation mismatch. WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" line 71: Index value(s) does not match array range, simulation mismatch. WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" line 73: Index value(s) does not match array range, simulation mismatch. +WARNING:Xst:1610 - "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" line 78: Width mismatch. has a width of 8 bits but assigned expression is 10-bit wide. WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" line 108: Index value(s) does not match array range, simulation mismatch. Entity analyzed. Unit generated. @@ -284,13 +286,13 @@ Found 3-bit addsub for signal <$n0142>. Found 3-bit addsub for signal <$n0143>. Found 3-bit addsub for signal <$n0144>. - Found 10-bit comparator greater for signal <$n0147> created at line 99. + Found 8-bit comparator greater for signal <$n0147> created at line 99. Found 3-bit comparator greater for signal <$n0241> created at line 108. Found 1-bit register for signal . - Found 10-bit register for signal . - Found 10-bit adder for signal . - Found 10-bit register for signal . - Found 10-bit adder for signal . + Found 8-bit register for signal . + Found 8-bit adder for signal . + Found 8-bit register for signal . + Found 8-bit adder for signal . Found 138-bit register for signal . Summary: inferred 139 D-type flip-flop(s). @@ -302,45 +304,41 @@ Synthesizing Unit . Related source file is "C:/Xilinx/bin/ArithmeticCoder/UPDATER.vhd". -WARNING:Xst:1780 - Signal is never used or assigned. Found 1-bit register for signal . - Found 10-bit 4-to-1 multiplexer for signal . - Found 10-bit 4-to-1 multiplexer for signal . - Found 10-bit adder for signal <$n0009> created at line 51. - Found 10-bit adder for signal <$n0011> created at line 73. - Found 10-bit adder for signal <$n0012> created at line 84. - Found 10-bit adder for signal <$n0013> created at line 62. - Found 10-bit register for signal . - Found 10-bit register for signal . - Found 10-bit register for signal . - Found 10-bit register for signal . - Found 10-bit register for signal . + Found 8-bit 4-to-1 multiplexer for signal . + Found 8-bit 4-to-1 multiplexer for signal . + Found 8-bit adder for signal <$n0009> created at line 50. + Found 8-bit adder for signal <$n0011> created at line 72. + Found 8-bit adder for signal <$n0012> created at line 83. + Found 8-bit adder for signal <$n0013> created at line 61. + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . Found 1-bit xor2 for signal . Summary: inferred 1 D-type flip-flop(s). inferred 4 Adder/Subtractor(s). - inferred 20 Multiplexer(s). + inferred 16 Multiplexer(s). Unit synthesized. Synthesizing Unit . Related source file is "C:/Xilinx/bin/ArithmeticCoder/Divider.vhd". -WARNING:Xst:646 - Signal > is assigned but never used. -WARNING:Xst:646 - Signal > is assigned but never used. - Found 1022x32-bit ROM for signal <$n0002> created at line 1079. - Found 16x10-bit multiplier for signal <$n0003> created at line 1086. - Found 16x10-bit multiplier for signal <$n0004> created at line 1093. - Found 10-bit subtractor for signal . - Found 10-bit register for signal . - Found 26-bit register for signal . - Found 26-bit register for signal . - Found 32-bit register for signal . - Found 42-bit adder for signal . +WARNING:Xst:646 - Signal > is assigned but never used. +WARNING:Xst:646 - Signal > is assigned but never used. + Found 254x16-bit ROM for signal <$n0002> created at line 308. + Found 16x8-bit multiplier for signal <$n0003> created at line 315. + Found 8-bit subtractor for signal . + Found 8-bit register for signal . + Found 24-bit register for signal . + Found 16-bit register for signal . Summary: inferred 1 ROM(s). - inferred 84 D-type flip-flop(s). - inferred 2 Adder/Subtractor(s). - inferred 2 Multiplier(s). + inferred 40 D-type flip-flop(s). + inferred 1 Adder/Subtractor(s). + inferred 1 Multiplier(s). Unit synthesized. @@ -396,10 +394,10 @@ Synthesizing Unit . Related source file is "C:/Xilinx/bin/ArithmeticCoder/CONTEXT_MANAGER.vhd". - Found 46x20-bit dual-port block RAM for signal . + Found 46x16-bit dual-port block RAM for signal . ----------------------------------------------------------------------- | mode | write-first | | - | aspect ratio | 46-word x 20-bit | | + | aspect ratio | 46-word x 16-bit | | | clock | connected to signal | rise | | dual clock | connected to signal | rise | | dual enable | connected to signal | high | @@ -411,15 +409,15 @@ | dual data out | connected to signal | | | ram_style | Auto | | ----------------------------------------------------------------------- - Found 1-bit 64-to-1 multiplexer for signal <$n0003> created at line 141. + Found 1-bit 46-to-1 multiplexer for signal <$n0003> created at line 141. Found 1-bit register for signal . Found 2-bit register for signal . Found 6-bit register for signal . Found 6-bit register for signal . - Found 64-bit register for signal . + Found 46-bit register for signal . Summary: inferred 1 RAM(s). - inferred 79 D-type flip-flop(s). + inferred 61 D-type flip-flop(s). inferred 1 Multiplexer(s). Unit synthesized. @@ -451,11 +449,11 @@ Synthesizing Unit . Related source file is "C:/Xilinx/bin/ArithmeticCoder/ARITHMETIC_UNIT.vhd". -WARNING:Xst:646 - Signal > is assigned but never used. +WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. - Found 17x10-bit multiplier for signal <$n0000> created at line 48. + Found 17x8-bit multiplier for signal <$n0000> created at line 48. Found 1-bit register for signal . Found 17-bit register for signal . Found 17-bit adder for signal . @@ -462,11 +460,11 @@ Found 17-bit subtractor for signal . Found 17-bit subtractor for signal . Found 17-bit register for signal . - Found 27-bit register for signal . + Found 25-bit register for signal . Found 17-bit adder for signal . Found 17-bit subtractor for signal . Summary: - inferred 62 D-type flip-flop(s). + inferred 60 D-type flip-flop(s). inferred 5 Adder/Subtractor(s). inferred 1 Multiplier(s). Unit synthesized. @@ -536,9 +534,6 @@ Found registered multiplier on signal <_n0003>: - 1 register level(s) found in a register connected to the multiplier macro ouput. Pushing register(s) into the multiplier macro. - Found registered multiplier on signal <_n0004>: - - 1 register level(s) found in a register connected to the multiplier macro ouput. - Pushing register(s) into the multiplier macro. Advanced Registered AddSub inference ... Dynamic shift register inference ... @@ -547,44 +542,40 @@ Macro Statistics # Block RAMs : 2 - 1022x32-bit single-port block RAM : 1 - 46x20-bit dual-port block RAM : 1 + 254x16-bit single-port block RAM : 1 + 46x16-bit dual-port block RAM : 1 # LUT RAMs : 2 256x1-bit dual-port distributed RAM: 1 256x8-bit dual-port distributed RAM: 1 -# Multipliers : 3 - 16x10-bit registered multiplier : 2 - 17x10-bit registered multiplier : 1 -# Adders/Subtractors : 59 - 10-bit adder : 6 - 10-bit subtractor : 1 +# Multipliers : 2 + 16x8-bit registered multiplier : 1 + 17x8-bit registered multiplier : 1 +# Adders/Subtractors : 58 17-bit adder : 2 17-bit subtractor : 3 3-bit addsub : 46 - 42-bit adder : 1 + 8-bit adder : 6 + 8-bit subtractor : 1 # Counters : 5 8-bit up counter : 4 8-bit updown counter : 1 -# Registers : 184 - 1-bit register : 125 - 10-bit register : 8 +# Registers : 166 + 1-bit register : 107 17-bit register : 2 3-bit register : 46 6-bit register : 2 - 8-bit register : 1 + 8-bit register : 9 # Comparators : 6 - 10-bit comparator greater : 1 3-bit comparator greater : 1 8-bit comparator equal : 2 - 8-bit comparator greater : 1 + 8-bit comparator greater : 2 8-bit comparator lessequal : 1 # Multiplexers : 52 1-bit 4-to-1 multiplexer : 1 - 1-bit 64-to-1 multiplexer : 1 - 10-bit 4-to-1 multiplexer : 2 + 1-bit 46-to-1 multiplexer : 1 3-bit 4-to-1 multiplexer : 46 3-bit 46-to-1 multiplexer : 1 - 8-bit 4-to-1 multiplexer : 1 + 8-bit 4-to-1 multiplexer : 3 # Xors : 2 1-bit xor2 : 2 @@ -640,24 +631,22 @@ WARNING:Xst:637 - Naming conflict between signal SHIFT_ALL of unit DIFFERENCE and signal DIFFERENCE_SHIFT_ALL of unit arithmeticcoder : renaming DIFFERENCE_SHIFT_ALL to DIFFERENCE_SHIFT_ALL1. Building and optimizing final netlist ... Register equivalent to has been removed +Register equivalent to has been removed Register equivalent to has been removed -Register equivalent to has been removed -Register equivalent to has been removed +Register equivalent to has been removed Register equivalent to has been removed Register equivalent to has been removed Register equivalent to has been removed Register equivalent to has been removed Register equivalent to has been removed -Register equivalent to has been removed -Register equivalent to has been removed Found area constraint ratio of 100 (+ 5) on block arithmeticcoder, actual ratio is 6. FlipFlop ARITH_DELAY1 has been replicated 1 time(s) -FlipFlop CONTEXT_BUFFER_STORAGE_READ_ADDRESS_0 has been replicated 14 time(s) -FlipFlop CONTEXT_BUFFER_STORAGE_READ_ADDRESS_1 has been replicated 14 time(s) -FlipFlop CONTEXT_BUFFER_STORAGE_READ_ADDRESS_2 has been replicated 14 time(s) -FlipFlop CONTEXT_BUFFER_STORAGE_READ_ADDRESS_3 has been replicated 14 time(s) -FlipFlop CONTEXT_BUFFER_STORAGE_READ_ADDRESS_4 has been replicated 7 time(s) -FlipFlop CONTEXT_BUFFER_STORAGE_READ_ADDRESS_5 has been replicated 2 time(s) +FlipFlop CONTEXT_BUFFER_STORAGE_READ_ADDRESS_0 has been replicated 15 time(s) +FlipFlop CONTEXT_BUFFER_STORAGE_READ_ADDRESS_1 has been replicated 15 time(s) +FlipFlop CONTEXT_BUFFER_STORAGE_READ_ADDRESS_2 has been replicated 15 time(s) +FlipFlop CONTEXT_BUFFER_STORAGE_READ_ADDRESS_3 has been replicated 15 time(s) +FlipFlop CONTEXT_BUFFER_STORAGE_READ_ADDRESS_4 has been replicated 5 time(s) +FlipFlop CONTEXT_BUFFER_STORAGE_READ_ADDRESS_5 has been replicated 3 time(s) FlipFlop CONTEXT_BUFFER_STORAGE_WRITE_ADDRESS_0 has been replicated 1 time(s) FlipFlop CONTEXT_BUFFER_STORAGE_WRITE_ADDRESS_1 has been replicated 1 time(s) FlipFlop CONTEXT_BUFFER_STORAGE_WRITE_ADDRESS_2 has been replicated 1 time(s) @@ -684,12 +673,12 @@ Macro Statistics : # RAM : 4 -# 1022x32-bit single-port block RAM: 1 +# 254x16-bit single-port block RAM: 1 # 256x1-bit dual-port distributed RAM: 1 # 256x8-bit dual-port distributed RAM: 1 -# 46x20-bit dual-port block RAM: 1 -# Registers : 261 -# 1-bit register : 205 +# 46x16-bit dual-port block RAM: 1 +# Registers : 227 +# 1-bit register : 171 # 17-bit register : 2 # 3-bit register : 46 # 6-bit register : 2 @@ -696,63 +685,59 @@ # 8-bit register : 6 # Multiplexers : 52 # 1-bit 4-to-1 multiplexer : 1 -# 1-bit 64-to-1 multiplexer : 1 -# 10-bit 4-to-1 multiplexer : 2 +# 1-bit 46-to-1 multiplexer : 1 # 3-bit 4-to-1 multiplexer : 46 # 3-bit 46-to-1 multiplexer : 1 -# 8-bit 4-to-1 multiplexer : 1 -# Adders/Subtractors : 18 -# 10-bit adder : 6 -# 10-bit subtractor : 1 +# 8-bit 4-to-1 multiplexer : 3 +# Adders/Subtractors : 17 # 17-bit adder : 2 # 17-bit subtractor : 3 -# 42-bit adder : 1 -# 8-bit adder : 5 -# Multipliers : 3 -# 16x10-bit registered multiplier: 2 -# 17x10-bit registered multiplier: 1 +# 8-bit adder : 11 +# 8-bit subtractor : 1 +# Multipliers : 2 +# 16x8-bit registered multiplier: 1 +# 17x8-bit registered multiplier: 1 # Comparators : 6 -# 10-bit comparator greater : 1 # 3-bit comparator greater : 1 # 8-bit comparator equal : 2 -# 8-bit comparator greater : 1 +# 8-bit comparator greater : 2 # 8-bit comparator lessequal : 1 # Xors : 92 # 1-bit xor3 : 92 Cell Usage : -# BELS : 1489 +# BELS : 1336 # GND : 1 # INV : 36 -# LUT1 : 64 -# LUT1_L : 9 -# LUT2 : 60 -# LUT2_D : 2 -# LUT2_L : 2 -# LUT3 : 108 -# LUT3_D : 10 -# LUT3_L : 246 -# LUT4 : 272 -# LUT4_D : 33 -# LUT4_L : 158 -# MUXCY : 196 -# MUXF5 : 69 -# MUXF6 : 23 -# MUXF7 : 10 -# MUXF8 : 5 +# LUT1 : 55 +# LUT1_L : 7 +# LUT2 : 58 +# LUT2_D : 1 +# LUT2_L : 10 +# LUT3 : 147 +# LUT3_D : 9 +# LUT3_L : 142 +# LUT4 : 252 +# LUT4_D : 24 +# LUT4_L : 185 +# MUXCY : 161 +# MUXF5 : 62 +# MUXF6 : 20 +# MUXF7 : 8 +# MUXF8 : 4 # VCC : 1 -# XORCY : 184 -# FlipFlops/Latches : 500 +# XORCY : 153 +# FlipFlops/Latches : 471 # FD : 7 # FDE : 86 -# FDR : 50 -# FDRE : 281 +# FDR : 40 +# FDRE : 280 # FDRSE : 2 # FDS : 7 -# FDSE : 67 -# RAMS : 39 +# FDSE : 49 +# RAMS : 38 # RAM64X1D : 36 -# RAMB16_S18 : 2 +# RAMB16_S36 : 1 # RAMB16_S36_S36 : 1 # Clock Buffers : 1 # BUFGP : 1 @@ -759,8 +744,8 @@ # IO Buffers : 15 # IBUF : 12 # OBUF : 3 -# MULTs : 3 -# MULT18X18S : 3 +# MULTs : 2 +# MULT18X18S : 2 ========================================================================= Device utilization summary: @@ -768,12 +753,12 @@ Selected Device : 2v2000bg575-6 - Number of Slices: 750 out of 10752 6% - Number of Slice Flip Flops: 500 out of 21504 2% - Number of 4 input LUTs: 1108 out of 21504 5% + Number of Slices: 719 out of 10752 6% + Number of Slice Flip Flops: 471 out of 21504 2% + Number of 4 input LUTs: 1034 out of 21504 4% Number of bonded IOBs: 16 out of 408 3% - Number of BRAMs: 3 out of 56 5% - Number of MULT18X18s: 3 out of 56 5% + Number of BRAMs: 2 out of 56 3% + Number of MULT18X18s: 2 out of 56 3% Number of GCLKs: 1 out of 16 6% @@ -789,7 +774,7 @@ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ -CLOCK | BUFGP | 540 | +CLOCK | BUFGP | 510 | -----------------------------------+------------------------+-------+ Timing Summary: @@ -796,10 +781,10 @@ --------------- Speed Grade: -6 - Minimum period: 16.221ns (Maximum Frequency: 61.648MHz) - Minimum input arrival time before clock: 15.527ns + Minimum period: 16.315ns (Maximum Frequency: 61.291MHz) + Minimum input arrival time before clock: 15.562ns Maximum output required time after clock: 8.122ns - Maximum combinational path delay: 7.764ns + Maximum combinational path delay: 7.705ns Timing Detail: -------------- @@ -807,16 +792,16 @@ ========================================================================= Timing constraint: Default period analysis for Clock 'CLOCK' - Clock period: 16.221ns (frequency: 61.648MHz) - Total number of paths / destination ports: 30998811 / 1448 + Clock period: 16.315ns (frequency: 61.291MHz) + Total number of paths / destination ports: 23899270 / 1400 ------------------------------------------------------------------------- -Delay: 16.221ns (Levels of Logic = 30) +Delay: 16.315ns (Levels of Logic = 28) Source: INBUFFER_STORAGE_READ_ADDRESS_1 (FF) - Destination: PROBABILITY_PROBUPDATE_NUMERATOR4_9 (FF) + Destination: PROBABILITY_PROBUPDATE_NUMERATOR4_7 (FF) Source Clock: CLOCK rising Destination Clock: CLOCK rising - Data Path: INBUFFER_STORAGE_READ_ADDRESS_1 to PROBABILITY_PROBUPDATE_NUMERATOR4_9 + Data Path: INBUFFER_STORAGE_READ_ADDRESS_1 to PROBABILITY_PROBUPDATE_NUMERATOR4_7 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ @@ -826,19 +811,19 @@ MUXCY:CI->O 1 0.042 0.000 INBUFFER_STORAGE_Eq_stagecy_rn_0 (INBUFFER_STORAGE_Eq_stage_cyo1) MUXCY:CI->O 1 0.042 0.000 INBUFFER_STORAGE_Eq_stagecy_rn_1 (INBUFFER_STORAGE_Eq_stage_cyo2) MUXCY:CI->O 10 0.601 0.819 INBUFFER_STORAGE_Eq_stagecy_rn_2 (INBUFFER_FIFO_EMPTY) - LUT2:I1->O 1 0.347 0.547 BUFFER_INPUT1_SW1 (N827) + LUT2:I1->O 1 0.347 0.547 BUFFER_INPUT1_SW1 (N835) LUT4_D:I1->O 12 0.347 0.715 INBUFFER_SENDING1 (DATA_AVAILABLE) - LUT4:I2->O 8 0.347 0.653 CONTEXT_BUFFER_Ker01 (CONTEXT_BUFFER_N01) - LUT4_D:I3->O 6 0.347 0.613 CONTEXT_BUFFER_DATA_OUT<6>_SW0_SW0 (N829) + LUT4_D:I2->O 13 0.347 0.738 CONTEXT_BUFFER_Ker31 (CONTEXT_BUFFER_N3) + LUT4_D:I3->O 6 0.347 0.613 CONTEXT_BUFFER_DATA_OUT<6>_SW0_SW0 (N849) LUT3:I2->O 9 0.347 0.665 CONTEXT_BUFFER_DATA_OUT<6>_2 (CONTEXT_BUFFER_DATA_OUT<6>_1) - LUT3_L:I2->LO 1 0.347 0.000 PROBABILITY_REFRESH_CONTEXT<4>3 (PROBABILITY_REFRESH_MUX_BLOCK_N4) - MUXF5:I0->O 1 0.345 0.000 PROBABILITY_REFRESH_CONTEXT<1>_rn_0 (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<1>_MUXF51) - MUXF6:I0->O 1 0.354 0.000 PROBABILITY_REFRESH_CONTEXT<0> (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<0>_MUXF6) - MUXF7:I1->O 1 0.354 0.000 PROBABILITY_REFRESH_CONTEXT<2> (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<2>_MUXF7) + LUT3_L:I2->LO 1 0.347 0.000 PROBABILITY_REFRESH_CONTEXT<4>5 (PROBABILITY_REFRESH_MUX_BLOCK_N6) + MUXF5:I0->O 1 0.345 0.000 PROBABILITY_REFRESH_CONTEXT<1>_rn_1 (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<1>_MUXF52) + MUXF6:I1->O 1 0.354 0.000 PROBABILITY_REFRESH_CONTEXT<0>_rn_0 (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<0>_MUXF61) + MUXF7:I0->O 1 0.354 0.000 PROBABILITY_REFRESH_CONTEXT<2> (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<2>_MUXF7) MUXF8:I1->O 1 0.354 0.548 PROBABILITY_REFRESH_CONTEXT<3> (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<3>_MUXF8) - LUT4_D:I1->LO 1 0.347 0.132 PROBABILITY_REFRESH__n0241106 (N969) - LUT4:I3->O 11 0.347 0.699 PROBABILITY_REFRESH__n0241109_1 (PROBABILITY_REFRESH__n0241109) - LUT4_D:I2->LO 2 0.347 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<0>lut (N979) + LUT4_L:I1->LO 1 0.347 0.132 PROBABILITY_REFRESH__n0241106 (CHOICE621) + LUT4:I3->O 19 0.347 0.792 PROBABILITY_REFRESH__n0241109 (PROBABILITY_REFRESH__n0241) + LUT4_D:I2->LO 2 0.347 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<0>lut (N991) MUXCY:S->O 1 0.235 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<0>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<0>_cyo) MUXCY:CI->O 1 0.042 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<1>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<1>_cyo) MUXCY:CI->O 1 0.042 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<2>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<2>_cyo) @@ -845,44 +830,42 @@ MUXCY:CI->O 1 0.042 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<3>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<3>_cyo) MUXCY:CI->O 1 0.042 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<4>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<4>_cyo) MUXCY:CI->O 1 0.042 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<5>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<5>_cyo) - MUXCY:CI->O 1 0.042 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<6>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<6>_cyo) - MUXCY:CI->O 1 0.042 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<7>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<7>_cyo) - XORCY:CI->O 2 0.824 0.744 PROBABILITY_PROBUPDATE_UPDATER__n0013<8>_xor (PROBABILITY_PROBUPDATE__n0013<8>) - LUT1_L:I0->LO 1 0.347 0.000 PROBABILITY_PROBUPDATE__n0013<8>_rt (PROBABILITY_PROBUPDATE__n0013<8>_rt) - MUXCY:S->O 0 0.235 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0011<8>cy (PROBABILITY_PROBUPDATE_UPDATER__n0011<8>_cyo) - XORCY:CI->O 1 0.824 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0011<9>_xor (PROBABILITY_PROBUPDATE__n0011<9>) - FDR:D 0.293 PROBABILITY_PROBUPDATE_NUMERATOR4_9 + XORCY:CI->O 2 0.824 0.744 PROBABILITY_PROBUPDATE_UPDATER__n0013<6>_xor (PROBABILITY_PROBUPDATE__n0013<6>) + LUT1_L:I0->LO 1 0.347 0.000 PROBABILITY_PROBUPDATE__n0013<6>_rt (PROBABILITY_PROBUPDATE__n0013<6>_rt) + MUXCY:S->O 0 0.235 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0011<6>cy (PROBABILITY_PROBUPDATE_UPDATER__n0011<6>_cyo) + XORCY:CI->O 1 0.824 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0011<7>_xor (PROBABILITY_PROBUPDATE__n0011<7>) + FDR:D 0.293 PROBABILITY_PROBUPDATE_NUMERATOR4_7 ---------------------------------------- - Total 16.221ns (9.298ns logic, 6.923ns route) - (57.3% logic, 42.7% route) + Total 16.315ns (9.214ns logic, 7.101ns route) + (56.5% logic, 43.5% route) ========================================================================= Timing constraint: Default OFFSET IN BEFORE for Clock 'CLOCK' - Total number of paths / destination ports: 1938326 / 1222 + Total number of paths / destination ports: 1496299 / 1156 ------------------------------------------------------------------------- -Offset: 15.527ns (Levels of Logic = 26) +Offset: 15.562ns (Levels of Logic = 24) Source: RESET (PAD) - Destination: PROBABILITY_PROBUPDATE_NUMERATOR4_9 (FF) + Destination: PROBABILITY_PROBUPDATE_NUMERATOR4_7 (FF) Destination Clock: CLOCK rising - Data Path: RESET to PROBABILITY_PROBUPDATE_NUMERATOR4_9 + Data Path: RESET to PROBABILITY_PROBUPDATE_NUMERATOR4_7 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ - IBUF:I->O 475 0.653 1.877 RESET_IBUF (RESET_IBUF) + IBUF:I->O 444 0.653 1.818 RESET_IBUF (RESET_IBUF) LUT4:I0->O 8 0.347 0.648 OUTPUT_SENDING1 (SENDING_OBUF) LUT4_D:I2->O 12 0.347 0.715 INBUFFER_SENDING1 (DATA_AVAILABLE) - LUT4:I2->O 8 0.347 0.653 CONTEXT_BUFFER_Ker01 (CONTEXT_BUFFER_N01) - LUT4_D:I3->O 6 0.347 0.613 CONTEXT_BUFFER_DATA_OUT<6>_SW0_SW0 (N829) + LUT4_D:I2->O 13 0.347 0.738 CONTEXT_BUFFER_Ker31 (CONTEXT_BUFFER_N3) + LUT4_D:I3->O 6 0.347 0.613 CONTEXT_BUFFER_DATA_OUT<6>_SW0_SW0 (N849) LUT3:I2->O 9 0.347 0.665 CONTEXT_BUFFER_DATA_OUT<6>_2 (CONTEXT_BUFFER_DATA_OUT<6>_1) - LUT3_L:I2->LO 1 0.347 0.000 PROBABILITY_REFRESH_CONTEXT<4>3 (PROBABILITY_REFRESH_MUX_BLOCK_N4) - MUXF5:I0->O 1 0.345 0.000 PROBABILITY_REFRESH_CONTEXT<1>_rn_0 (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<1>_MUXF51) - MUXF6:I0->O 1 0.354 0.000 PROBABILITY_REFRESH_CONTEXT<0> (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<0>_MUXF6) - MUXF7:I1->O 1 0.354 0.000 PROBABILITY_REFRESH_CONTEXT<2> (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<2>_MUXF7) + LUT3_L:I2->LO 1 0.347 0.000 PROBABILITY_REFRESH_CONTEXT<4>5 (PROBABILITY_REFRESH_MUX_BLOCK_N6) + MUXF5:I0->O 1 0.345 0.000 PROBABILITY_REFRESH_CONTEXT<1>_rn_1 (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<1>_MUXF52) + MUXF6:I1->O 1 0.354 0.000 PROBABILITY_REFRESH_CONTEXT<0>_rn_0 (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<0>_MUXF61) + MUXF7:I0->O 1 0.354 0.000 PROBABILITY_REFRESH_CONTEXT<2> (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<2>_MUXF7) MUXF8:I1->O 1 0.354 0.548 PROBABILITY_REFRESH_CONTEXT<3> (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<3>_MUXF8) - LUT4_D:I1->LO 1 0.347 0.132 PROBABILITY_REFRESH__n0241106 (N969) - LUT4:I3->O 11 0.347 0.699 PROBABILITY_REFRESH__n0241109_1 (PROBABILITY_REFRESH__n0241109) - LUT4_D:I2->LO 2 0.347 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<0>lut (N979) + LUT4_L:I1->LO 1 0.347 0.132 PROBABILITY_REFRESH__n0241106 (CHOICE621) + LUT4:I3->O 19 0.347 0.792 PROBABILITY_REFRESH__n0241109 (PROBABILITY_REFRESH__n0241) + LUT4_D:I2->LO 2 0.347 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<0>lut (N991) MUXCY:S->O 1 0.235 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<0>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<0>_cyo) MUXCY:CI->O 1 0.042 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<1>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<1>_cyo) MUXCY:CI->O 1 0.042 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<2>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<2>_cyo) @@ -889,16 +872,14 @@ MUXCY:CI->O 1 0.042 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<3>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<3>_cyo) MUXCY:CI->O 1 0.042 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<4>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<4>_cyo) MUXCY:CI->O 1 0.042 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<5>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<5>_cyo) - MUXCY:CI->O 1 0.042 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<6>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<6>_cyo) - MUXCY:CI->O 1 0.042 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<7>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<7>_cyo) - XORCY:CI->O 2 0.824 0.744 PROBABILITY_PROBUPDATE_UPDATER__n0013<8>_xor (PROBABILITY_PROBUPDATE__n0013<8>) - LUT1_L:I0->LO 1 0.347 0.000 PROBABILITY_PROBUPDATE__n0013<8>_rt (PROBABILITY_PROBUPDATE__n0013<8>_rt) - MUXCY:S->O 0 0.235 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0011<8>cy (PROBABILITY_PROBUPDATE_UPDATER__n0011<8>_cyo) - XORCY:CI->O 1 0.824 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0011<9>_xor (PROBABILITY_PROBUPDATE__n0011<9>) - FDR:D 0.293 PROBABILITY_PROBUPDATE_NUMERATOR4_9 + XORCY:CI->O 2 0.824 0.744 PROBABILITY_PROBUPDATE_UPDATER__n0013<6>_xor (PROBABILITY_PROBUPDATE__n0013<6>) + LUT1_L:I0->LO 1 0.347 0.000 PROBABILITY_PROBUPDATE__n0013<6>_rt (PROBABILITY_PROBUPDATE__n0013<6>_rt) + MUXCY:S->O 0 0.235 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0011<6>cy (PROBABILITY_PROBUPDATE_UPDATER__n0011<6>_cyo) + XORCY:CI->O 1 0.824 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0011<7>_xor (PROBABILITY_PROBUPDATE__n0011<7>) + FDR:D 0.293 PROBABILITY_PROBUPDATE_NUMERATOR4_7 ---------------------------------------- - Total 15.527ns (8.235ns logic, 7.292ns route) - (53.0% logic, 47.0% route) + Total 15.562ns (8.151ns logic, 7.411ns route) + (52.4% logic, 47.6% route) ========================================================================= Timing constraint: Default OFFSET OUT AFTER for Clock 'CLOCK' @@ -927,7 +908,7 @@ Timing constraint: Default path analysis Total number of paths / destination ports: 2 / 2 ------------------------------------------------------------------------- -Delay: 7.764ns (Levels of Logic = 4) +Delay: 7.705ns (Levels of Logic = 4) Source: RESET (PAD) Destination: DATA_OUT (PAD) @@ -935,22 +916,22 @@ Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ - IBUF:I->O 475 0.653 1.877 RESET_IBUF (RESET_IBUF) + IBUF:I->O 444 0.653 1.818 RESET_IBUF (RESET_IBUF) LUT2:I0->O 1 0.347 0.414 OUTPUT_DATA_OUT1 (OUTPUT_N0) LUT4:I3->O 1 0.347 0.383 OUTPUT_DATA_OUT2 (DATA_OUT_OBUF) OBUF:I->O 3.743 DATA_OUT_OBUF (DATA_OUT) ---------------------------------------- - Total 7.764ns (5.090ns logic, 2.674ns route) - (65.6% logic, 34.4% route) + Total 7.705ns (5.090ns logic, 2.615ns route) + (66.1% logic, 33.9% route) ========================================================================= -CPU : 34.83 / 35.22 s | Elapsed : 35.00 / 35.00 s +CPU : 32.67 / 33.06 s | Elapsed : 33.00 / 33.00 s --> -Total memory usage is 130364 kilobytes +Total memory usage is 129340 kilobytes Number of errors : 0 ( 0 filtered) -Number of warnings : 27 ( 0 filtered) +Number of warnings : 29 ( 0 filtered) Number of infos : 5 ( 0 filtered)
/trunk/docs/synthesis_reports/decoder/arithmeticdecoder.syr
1,10 → 1,10
Release 7.1.04i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 2.34 s | Elapsed : 0.00 / 2.00 s
CPU : 0.00 / 0.36 s | Elapsed : 0.00 / 1.00 s
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 2.34 s | Elapsed : 0.00 / 2.00 s
CPU : 0.00 / 0.36 s | Elapsed : 0.00 / 1.00 s
--> Reading design: arithmeticdecoder.prj
 
32,7 → 32,7
---- Target Parameters
Output File Name : "arithmeticdecoder"
Output Format : NGC
Target Device : xc2v250-6-cs144
Target Device : xc2v2000-6-bf957
 
---- Source Options
Top Module Name : arithmeticdecoder
95,30 → 95,30
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/Divider.vhd" in Library work.
Architecture rtl of Entity divider is up to date.
Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/UPDATER.vhd" in Library work.
Compiling vhdl file "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/Divider.vhd" in Library work.
Entity <divider> compiled.
Entity <divider> (Architecture <rtl>) compiled.
Compiling vhdl file "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/UPDATER.vhd" in Library work.
Architecture rtl of Entity updater is up to date.
Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd" in Library work.
Compiling vhdl file "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/HALVING_MANAGER.vhd" in Library work.
Architecture rtl of Entity halving_manager is up to date.
Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/FIFO.vhd" in Library work.
Architecture rtl of Entity fifo is up to date.
Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/INPUT_CONTROL.vhd" in Library work.
Compiling vhdl file "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/FIFO.vhd" in Library work.
Entity <fifo> compiled.
Entity <fifo> (Architecture <rtl>) compiled.
Compiling vhdl file "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/INPUT_CONTROL.vhd" in Library work.
Architecture rtl of Entity input_control is up to date.
Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/CONTEXT_MANAGER.vhd" in Library work.
Compiling vhdl file "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/CONTEXT_MANAGER.vhd" in Library work.
Architecture rtl of Entity context_manager is up to date.
Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/STORAGE_REGISTER.vhd" in Library work.
Entity <storage_register> compiled.
Entity <storage_register> (Architecture <rtl>) compiled.
Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/ARITHMETIC_UNIT.vhd" in Library work.
Compiling vhdl file "c:/xilinx/bin/arithmeticdecoder/STORAGE_REGISTER.vhd" in Library work.
Architecture rtl of Entity storage_register is up to date.
Compiling vhdl file "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/ARITHMETIC_UNIT.vhd" in Library work.
Architecture rtl of Entity arithmetic_unit is up to date.
Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/CONVERGENCE_CHECK.vhd" in Library work.
Compiling vhdl file "c:/xilinx/bin/arithmeticdecoder/CONVERGENCE_CHECK.vhd" in Library work.
Architecture rtl of Entity convergence_check is up to date.
Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/SYMBOL_DETECTOR.vhd" in Library work.
Compiling vhdl file "c:/xilinx/bin/arithmeticdecoder/SYMBOL_DETECTOR.vhd" in Library work.
Architecture rtl of Entity symbol_detector is up to date.
Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/ARITHMETICDECODER.vhd" in Library work.
Entity <arithmeticdecoder> compiled.
Entity <arithmeticdecoder> (Architecture <rtl>) compiled.
Compiling vhdl file "c:/xilinx/bin/arithmeticdecoder/ARITHMETICDECODER.vhd" in Library work.
Architecture rtl of Entity arithmeticdecoder is up to date.
 
=========================================================================
* HDL Analysis *
136,12 → 136,14
Entity <FIFO> analyzed. Unit <FIFO> generated.
 
Analyzing Entity <CONTEXT_MANAGER> (Architecture <rtl>).
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/CONTEXT_MANAGER.vhd" line 133: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/CONTEXT_MANAGER.vhd" line 137: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/CONTEXT_MANAGER.vhd" line 118: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/CONTEXT_MANAGER.vhd" line 133: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/CONTEXT_MANAGER.vhd" line 137: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/CONTEXT_MANAGER.vhd" line 141: Index value(s) does not match array range, simulation mismatch.
Entity <CONTEXT_MANAGER> analyzed. Unit <CONTEXT_MANAGER> generated.
 
Analyzing Entity <DIVIDER> (Architecture <rtl>).
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/Divider.vhd" line 1079: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/Divider.vhd" line 308: Index value(s) does not match array range, simulation mismatch.
Entity <DIVIDER> analyzed. Unit <DIVIDER> generated.
 
Analyzing Entity <UPDATER> (Architecture <rtl>).
148,10 → 150,11
Entity <UPDATER> analyzed. Unit <UPDATER> generated.
 
Analyzing Entity <HALVING_MANAGER> (Architecture <rtl>).
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd" line 71: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd" line 71: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd" line 73: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd" line 108: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/HALVING_MANAGER.vhd" line 71: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/HALVING_MANAGER.vhd" line 71: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/HALVING_MANAGER.vhd" line 73: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:1610 - "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/HALVING_MANAGER.vhd" line 78: Width mismatch. <NUMERATOR2> has a width of 8 bits but assigned expression is 10-bit wide.
WARNING:Xst:790 - "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/HALVING_MANAGER.vhd" line 108: Index value(s) does not match array range, simulation mismatch.
Entity <HALVING_MANAGER> analyzed. Unit <HALVING_MANAGER> generated.
 
Analyzing Entity <STORAGE_REGISTER> (Architecture <rtl>).
172,7 → 175,7
=========================================================================
 
Synthesizing Unit <HALVING_MANAGER>.
Related source file is "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd".
Related source file is "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/HALVING_MANAGER.vhd".
Found 3-bit 46-to-1 multiplexer for signal <$n0002> created at line 108.
Found 3-bit 4-to-1 multiplexer for signal <$n0050>.
Found 3-bit 4-to-1 multiplexer for signal <$n0051>.
266,13 → 269,13
Found 3-bit addsub for signal <$n0142>.
Found 3-bit addsub for signal <$n0143>.
Found 3-bit addsub for signal <$n0144>.
Found 10-bit comparator greater for signal <$n0147> created at line 99.
Found 8-bit comparator greater for signal <$n0147> created at line 99.
Found 3-bit comparator greater for signal <$n0241> created at line 108.
Found 1-bit register for signal <AFTER_TRIGGER>.
Found 10-bit register for signal <DENOMINATOR>.
Found 10-bit adder for signal <DENOMINATOR2>.
Found 10-bit register for signal <NUMERATOR>.
Found 10-bit adder for signal <NUMERATOR2>.
Found 8-bit register for signal <DENOMINATOR>.
Found 8-bit adder for signal <DENOMINATOR2>.
Found 8-bit register for signal <NUMERATOR>.
Found 8-bit adder for signal <NUMERATOR2>.
Found 138-bit register for signal <SHIFTS>.
Summary:
inferred 139 D-type flip-flop(s).
283,51 → 286,48
 
 
Synthesizing Unit <UPDATER>.
Related source file is "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/UPDATER.vhd".
Related source file is "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/UPDATER.vhd".
WARNING:Xst:1780 - Signal <HALVING_ALLOWED> is never used or assigned.
Found 1-bit register for signal <UPDATE>.
Found 10-bit 4-to-1 multiplexer for signal <DENOMINATOR_OUT>.
Found 10-bit 4-to-1 multiplexer for signal <NUMERATOR_OUT>.
Found 10-bit adder for signal <$n0009> created at line 51.
Found 10-bit adder for signal <$n0011> created at line 73.
Found 10-bit adder for signal <$n0012> created at line 84.
Found 10-bit adder for signal <$n0013> created at line 62.
Found 10-bit register for signal <DENOMINATOR2>.
Found 10-bit register for signal <NUMERATOR1>.
Found 10-bit register for signal <NUMERATOR2>.
Found 10-bit register for signal <NUMERATOR3>.
Found 10-bit register for signal <NUMERATOR4>.
Found 8-bit 4-to-1 multiplexer for signal <DENOMINATOR_OUT>.
Found 8-bit 4-to-1 multiplexer for signal <NUMERATOR_OUT>.
Found 8-bit adder for signal <$n0009> created at line 51.
Found 8-bit adder for signal <$n0011> created at line 73.
Found 8-bit adder for signal <$n0012> created at line 84.
Found 8-bit adder for signal <$n0013> created at line 62.
Found 8-bit register for signal <DENOMINATOR2>.
Found 8-bit register for signal <NUMERATOR1>.
Found 8-bit register for signal <NUMERATOR2>.
Found 8-bit register for signal <NUMERATOR3>.
Found 8-bit register for signal <NUMERATOR4>.
Found 1-bit xor2 for signal <UPDATE_SWITCH>.
Summary:
inferred 1 D-type flip-flop(s).
inferred 4 Adder/Subtractor(s).
inferred 20 Multiplexer(s).
inferred 16 Multiplexer(s).
Unit <UPDATER> synthesized.
 
 
Synthesizing Unit <DIVIDER>.
Related source file is "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/Divider.vhd".
WARNING:Xst:646 - Signal <TOTAL<41:32>> is assigned but never used.
WARNING:Xst:646 - Signal <TOTAL<21:0>> is assigned but never used.
Found 1022x32-bit ROM for signal <$n0002> created at line 1079.
Found 16x10-bit multiplier for signal <$n0003> created at line 1086.
Found 16x10-bit multiplier for signal <$n0004> created at line 1093.
Found 10-bit subtractor for signal <INDEX>.
Found 10-bit register for signal <NUMERATOR2>.
Found 26-bit register for signal <PRODUCT1>.
Found 26-bit register for signal <PRODUCT2>.
Found 32-bit register for signal <RECIPROCAL>.
Found 42-bit adder for signal <TOTAL>.
Related source file is "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/Divider.vhd".
WARNING:Xst:646 - Signal <PRODUCT<23:16>> is assigned but never used.
WARNING:Xst:646 - Signal <PRODUCT<7:0>> is assigned but never used.
Found 254x16-bit ROM for signal <$n0002> created at line 308.
Found 16x8-bit multiplier for signal <$n0003> created at line 315.
Found 8-bit subtractor for signal <INDEX>.
Found 8-bit register for signal <NUMERATOR2>.
Found 24-bit register for signal <PRODUCT>.
Found 16-bit register for signal <RECIPROCAL>.
Summary:
inferred 1 ROM(s).
inferred 84 D-type flip-flop(s).
inferred 2 Adder/Subtractor(s).
inferred 2 Multiplier(s).
inferred 40 D-type flip-flop(s).
inferred 1 Adder/Subtractor(s).
inferred 1 Multiplier(s).
Unit <DIVIDER> synthesized.
 
 
Synthesizing Unit <FIFO>.
Related source file is "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/FIFO.vhd".
Related source file is "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/FIFO.vhd".
Found 256x1-bit dual-port distributed RAM for signal <GET_OUTPUT>.
-----------------------------------------------------------------------
| aspect ratio | 256-word x 1-bit | |
352,7 → 352,7
 
 
Synthesizing Unit <SYMBOL_DETECTOR>.
Related source file is "C:/Xilinx/bin/ArithmeticDecoder/SYMBOL_DETECTOR.vhd".
Related source file is "c:/xilinx/bin/arithmeticdecoder/SYMBOL_DETECTOR.vhd".
Found 16-bit comparator greatequal for signal <$n0001> created at line 23.
Summary:
inferred 1 Comparator(s).
360,17 → 360,17
 
 
Synthesizing Unit <CONVERGENCE_CHECK>.
Related source file is "C:/Xilinx/bin/ArithmeticDecoder/CONVERGENCE_CHECK.vhd".
Related source file is "c:/xilinx/bin/arithmeticdecoder/CONVERGENCE_CHECK.vhd".
Unit <CONVERGENCE_CHECK> synthesized.
 
 
Synthesizing Unit <ARITHMETIC_UNIT>.
Related source file is "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/ARITHMETIC_UNIT.vhd".
WARNING:Xst:646 - Signal <PRODUCT<9:0>> is assigned but never used.
Related source file is "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/ARITHMETIC_UNIT.vhd".
WARNING:Xst:646 - Signal <PRODUCT<7:0>> is assigned but never used.
WARNING:Xst:646 - Signal <DIFFERENCE3<16>> is assigned but never used.
WARNING:Xst:646 - Signal <DIFFERENCE4<16>> is assigned but never used.
WARNING:Xst:646 - Signal <RESULT0<16>> is assigned but never used.
Found 17x10-bit multiplier for signal <$n0000> created at line 48.
Found 17x8-bit multiplier for signal <$n0000> created at line 48.
Found 1-bit register for signal <DELAY1>.
Found 17-bit register for signal <DIFFERENCE1>.
Found 17-bit adder for signal <DIFFERENCE2>.
377,11 → 377,11
Found 17-bit subtractor for signal <DIFFERENCE3>.
Found 17-bit subtractor for signal <DIFFERENCE4>.
Found 17-bit register for signal <LOW2>.
Found 27-bit register for signal <PRODUCT>.
Found 25-bit register for signal <PRODUCT>.
Found 17-bit adder for signal <RESULT>.
Found 17-bit subtractor for signal <RESULT0>.
Summary:
inferred 62 D-type flip-flop(s).
inferred 60 D-type flip-flop(s).
inferred 5 Adder/Subtractor(s).
inferred 1 Multiplier(s).
Unit <ARITHMETIC_UNIT> synthesized.
388,7 → 388,7
 
 
Synthesizing Unit <STORAGE_REGISTER>.
Related source file is "C:/Xilinx/bin/ArithmeticDecoder/STORAGE_REGISTER.vhd".
Related source file is "c:/xilinx/bin/arithmeticdecoder/STORAGE_REGISTER.vhd".
Found 16-bit 4-to-1 multiplexer for signal <$n0001>.
Found 16-bit register for signal <Q>.
Summary:
398,11 → 398,11
 
 
Synthesizing Unit <CONTEXT_MANAGER>.
Related source file is "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/CONTEXT_MANAGER.vhd".
Found 46x20-bit dual-port block RAM for signal <PROBABILITY>.
Related source file is "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/CONTEXT_MANAGER.vhd".
Found 46x16-bit dual-port block RAM for signal <PROBABILITY>.
-----------------------------------------------------------------------
| mode | write-first | |
| aspect ratio | 46-word x 20-bit | |
| aspect ratio | 46-word x 16-bit | |
| clock | connected to signal <CLOCK> | rise |
| dual clock | connected to signal <CLOCK> | rise |
| dual enable | connected to signal <SET> | high |
414,21 → 414,21
| dual data out | connected to signal <RATIO> | |
| ram_style | Auto | |
-----------------------------------------------------------------------
Found 1-bit 64-to-1 multiplexer for signal <$n0003> created at line 141.
Found 1-bit 46-to-1 multiplexer for signal <$n0003> created at line 141.
Found 1-bit register for signal <CONTEXT_VALID>.
Found 2-bit register for signal <DATA_READY>.
Found 6-bit register for signal <OLD_CONTEXT>.
Found 6-bit register for signal <READ_ADDRESS>.
Found 64-bit register for signal <RESET_FLAGS>.
Found 46-bit register for signal <RESET_FLAGS>.
Summary:
inferred 1 RAM(s).
inferred 79 D-type flip-flop(s).
inferred 61 D-type flip-flop(s).
inferred 1 Multiplexer(s).
Unit <CONTEXT_MANAGER> synthesized.
 
 
Synthesizing Unit <INPUT_CONTROL>.
Related source file is "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/INPUT_CONTROL.vhd".
Related source file is "c:/xilinx/bin/arithmeticdecoder/../ArithmeticCoder/INPUT_CONTROL.vhd".
Found 1-bit register for signal <HELD<0>>.
Found 1-bit 4-to-1 multiplexer for signal <OUTPUT<0>>.
Summary:
438,7 → 438,7
 
 
Synthesizing Unit <arithmeticdecoder>.
Related source file is "C:/Xilinx/bin/ArithmeticDecoder/ARITHMETICDECODER.vhd".
Related source file is "c:/xilinx/bin/arithmeticdecoder/ARITHMETICDECODER.vhd".
WARNING:Xst:646 - Signal <HIGH_VALUE<13:0>> is assigned but never used.
Unit <arithmeticdecoder> synthesized.
 
458,9 → 458,6
Found registered multiplier on signal <_n0003>:
- 1 register level(s) found in a register connected to the multiplier macro ouput.
Pushing register(s) into the multiplier macro.
Found registered multiplier on signal <_n0004>:
- 1 register level(s) found in a register connected to the multiplier macro ouput.
Pushing register(s) into the multiplier macro.
Advanced Registered AddSub inference ...
Dynamic shift register inference ...
 
469,41 → 466,40
 
Macro Statistics
# Block RAMs : 2
1022x32-bit single-port block RAM : 1
46x20-bit dual-port block RAM : 1
254x16-bit single-port block RAM : 1
46x16-bit dual-port block RAM : 1
# LUT RAMs : 1
256x1-bit dual-port distributed RAM: 1
# Multipliers : 3
16x10-bit registered multiplier : 2
17x10-bit registered multiplier : 1
# Adders/Subtractors : 59
10-bit adder : 6
10-bit subtractor : 1
# Multipliers : 2
16x8-bit registered multiplier : 1
17x8-bit registered multiplier : 1
# Adders/Subtractors : 58
17-bit adder : 2
17-bit subtractor : 3
3-bit addsub : 46
42-bit adder : 1
8-bit adder : 6
8-bit subtractor : 1
# Counters : 2
8-bit up counter : 2
# Registers : 133
1-bit register : 71
10-bit register : 8
# Registers : 115
1-bit register : 53
16-bit register : 4
17-bit register : 2
3-bit register : 46
6-bit register : 2
8-bit register : 8
# Comparators : 4
10-bit comparator greater : 1
16-bit comparator greatequal : 1
3-bit comparator greater : 1
8-bit comparator equal : 1
8-bit comparator greater : 1
# Multiplexers : 55
1-bit 4-to-1 multiplexer : 1
1-bit 64-to-1 multiplexer : 1
10-bit 4-to-1 multiplexer : 2
1-bit 46-to-1 multiplexer : 1
16-bit 4-to-1 multiplexer : 4
3-bit 4-to-1 multiplexer : 46
3-bit 46-to-1 multiplexer : 1
8-bit 4-to-1 multiplexer : 2
# Xors : 1
1-bit xor2 : 1
 
533,23 → 529,20
Optimizing unit <FIFO> ...
 
Optimizing unit <ARITHMETIC_UNIT> ...
Loading device for application Rf_Device from file '2v250.nph' in environment C:/Xilinx.
Loading device for application Rf_Device from file '2v2000.nph' in environment C:/Xilinx.
 
Mapping all equations...
Building and optimizing final netlist ...
Register <PROBABILITY_PROBUPDATE_UPDATE> equivalent to <PROBABILITY_DATA_READY_0> has been removed
Register <PROBABILITY_DIVISION_NUMERATOR2_5> equivalent to <PROBABILITY_PROBUPDATE_NUMERATOR1_5> has been removed
Register <PROBABILITY_DIVISION_NUMERATOR2_7> equivalent to <PROBABILITY_PROBUPDATE_NUMERATOR1_7> has been removed
Register <PROBABILITY_DIVISION_NUMERATOR2_9> equivalent to <PROBABILITY_PROBUPDATE_NUMERATOR1_9> has been removed
Register <PROBABILITY_DIVISION_NUMERATOR2_8> equivalent to <PROBABILITY_PROBUPDATE_NUMERATOR1_8> has been removed
Register <PROBABILITY_DIVISION_NUMERATOR2_6> equivalent to <PROBABILITY_PROBUPDATE_NUMERATOR1_6> has been removed
Register <PROBABILITY_DIVISION_NUMERATOR2_0> equivalent to <PROBABILITY_PROBUPDATE_NUMERATOR1_0> has been removed
Register <PROBABILITY_DIVISION_NUMERATOR2_1> equivalent to <PROBABILITY_PROBUPDATE_NUMERATOR1_1> has been removed
Register <PROBABILITY_DIVISION_NUMERATOR2_2> equivalent to <PROBABILITY_PROBUPDATE_NUMERATOR1_2> has been removed
Register <PROBABILITY_DIVISION_NUMERATOR2_3> equivalent to <PROBABILITY_PROBUPDATE_NUMERATOR1_3> has been removed
Register <PROBABILITY_DIVISION_NUMERATOR2_4> equivalent to <PROBABILITY_PROBUPDATE_NUMERATOR1_4> has been removed
Register <PROBABILITY_DIVISION_NUMERATOR2_5> equivalent to <PROBABILITY_PROBUPDATE_NUMERATOR1_5> has been removed
Register <PROBABILITY_DIVISION_NUMERATOR2_6> equivalent to <PROBABILITY_PROBUPDATE_NUMERATOR1_6> has been removed
Found area constraint ratio of 100 (+ 5) on block arithmeticdecoder, actual ratio is 33.
FlipFlop PROBABILITY_READ_ADDRESS_0 has been replicated 3 time(s)
Found area constraint ratio of 100 (+ 5) on block arithmeticdecoder, actual ratio is 4.
 
=========================================================================
* Final Report *
566,11 → 559,11
 
Macro Statistics :
# RAM : 3
# 1022x32-bit single-port block RAM: 1
# 254x16-bit single-port block RAM: 1
# 256x1-bit dual-port distributed RAM: 1
# 46x20-bit dual-port block RAM: 1
# Registers : 207
# 1-bit register : 151
# 46x16-bit dual-port block RAM: 1
# Registers : 173
# 1-bit register : 117
# 16-bit register : 4
# 17-bit register : 2
# 3-bit register : 46
578,62 → 571,60
# 8-bit register : 2
# Multiplexers : 55
# 1-bit 4-to-1 multiplexer : 1
# 1-bit 64-to-1 multiplexer : 1
# 10-bit 4-to-1 multiplexer : 2
# 1-bit 46-to-1 multiplexer : 1
# 16-bit 4-to-1 multiplexer : 4
# 3-bit 4-to-1 multiplexer : 46
# 3-bit 46-to-1 multiplexer : 1
# Adders/Subtractors : 15
# 10-bit adder : 6
# 10-bit subtractor : 1
# 8-bit 4-to-1 multiplexer : 2
# Adders/Subtractors : 14
# 17-bit adder : 2
# 17-bit subtractor : 3
# 42-bit adder : 1
# 8-bit adder : 2
# Multipliers : 3
# 16x10-bit registered multiplier: 2
# 17x10-bit registered multiplier: 1
# 8-bit adder : 8
# 8-bit subtractor : 1
# Multipliers : 2
# 16x8-bit registered multiplier: 1
# 17x8-bit registered multiplier: 1
# Comparators : 4
# 10-bit comparator greater : 1
# 16-bit comparator greatequal: 1
# 3-bit comparator greater : 1
# 8-bit comparator equal : 1
# 8-bit comparator greater : 1
# Xors : 92
# 1-bit xor3 : 92
 
Cell Usage :
# BELS : 1384
# BELS : 1220
# GND : 1
# INV : 34
# LUT1 : 31
# LUT1_L : 28
# LUT1 : 30
# LUT1_L : 18
# LUT2 : 40
# LUT2_D : 1
# LUT2_L : 41
# LUT3 : 109
# LUT3_D : 4
# LUT3_L : 154
# LUT4 : 332
# LUT4_D : 26
# LUT4_L : 72
# MUXCY : 187
# MUXF5 : 123
# MUXF6 : 23
# MUXF7 : 10
# MUXF8 : 5
# LUT2_L : 31
# LUT3 : 67
# LUT3_D : 3
# LUT3_L : 124
# LUT4 : 287
# LUT4_D : 14
# LUT4_L : 139
# MUXCY : 152
# MUXF5 : 116
# MUXF6 : 19
# MUXF7 : 8
# MUXF8 : 4
# VCC : 1
# XORCY : 162
# FlipFlops/Latches : 405
# XORCY : 131
# FlipFlops/Latches : 370
# FD : 6
# FDE : 41
# FDR : 49
# FDRE : 237
# FDE : 38
# FDR : 39
# FDRE : 233
# FDRSE : 1
# FDS : 5
# FDSE : 66
# RAMS : 7
# FDSE : 48
# RAMS : 6
# RAM64X1D : 4
# RAMB16_S18 : 2
# RAMB16_S36 : 1
# RAMB16_S36_S36 : 1
# Clock Buffers : 1
# BUFGP : 1
640,21 → 631,21
# IO Buffers : 13
# IBUF : 11
# OBUF : 2
# MULTs : 3
# MULT18X18S : 3
# MULTs : 2
# MULT18X18S : 2
=========================================================================
 
Device utilization summary:
---------------------------
 
Selected Device : 2v250cs144-6
Selected Device : 2v2000bf957-6
 
Number of Slices: 490 out of 1536 31%
Number of Slice Flip Flops: 405 out of 3072 13%
Number of 4 input LUTs: 854 out of 3072 27%
Number of bonded IOBs: 14 out of 92 15%
Number of BRAMs: 3 out of 24 12%
Number of MULT18X18s: 3 out of 24 12%
Number of Slices: 447 out of 10752 4%
Number of Slice Flip Flops: 370 out of 21504 1%
Number of 4 input LUTs: 770 out of 21504 3%
Number of bonded IOBs: 14 out of 624 2%
Number of BRAMs: 2 out of 56 3%
Number of MULT18X18s: 2 out of 56 3%
Number of GCLKs: 1 out of 16 6%
 
 
670,7 → 661,7
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
CLOCK | BUFGP | 413 |
CLOCK | BUFGP | 377 |
-----------------------------------+------------------------+-------+
 
Timing Summary:
677,9 → 668,9
---------------
Speed Grade: -6
 
Minimum period: 9.680ns (Maximum Frequency: 103.303MHz)
Minimum input arrival time before clock: 10.225ns
Maximum output required time after clock: 11.576ns
Minimum period: 9.935ns (Maximum Frequency: 100.654MHz)
Minimum input arrival time before clock: 10.481ns
Maximum output required time after clock: 11.374ns
Maximum combinational path delay: No path found
 
Timing Detail:
688,101 → 679,111
 
=========================================================================
Timing constraint: Default period analysis for Clock 'CLOCK'
Clock period: 9.680ns (frequency: 103.303MHz)
Total number of paths / destination ports: 273761 / 786
Clock period: 9.935ns (frequency: 100.654MHz)
Total number of paths / destination ports: 196171 / 732
-------------------------------------------------------------------------
Delay: 9.680ns (Levels of Logic = 12)
Source: PROBABILITY_REFRESH_SHIFTS_0_1 (FF)
Destination: PROBABILITY_Mram_PROBABILITY_inst_ramb_0 (RAM)
Delay: 9.935ns (Levels of Logic = 17)
Source: PROBABILITY_REFRESH_SHIFTS_32_2 (FF)
Destination: PROBABILITY_PROBUPDATE_NUMERATOR4_7 (FF)
Source Clock: CLOCK rising
Destination Clock: CLOCK rising
 
Data Path: PROBABILITY_REFRESH_SHIFTS_0_1 to PROBABILITY_Mram_PROBABILITY_inst_ramb_0
Data Path: PROBABILITY_REFRESH_SHIFTS_32_2 to PROBABILITY_PROBUPDATE_NUMERATOR4_7
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDRE:C->Q 5 0.449 0.734 PROBABILITY_REFRESH_SHIFTS_0_1 (PROBABILITY_REFRESH_SHIFTS_0_1)
LUT3_L:I1->LO 1 0.347 0.000 PROBABILITY_REFRESH_CONTEXT<4>31 (PROBABILITY_REFRESH_MUX_BLOCK_N38)
MUXF5:I0->O 1 0.345 0.000 PROBABILITY_REFRESH_CONTEXT<1>_rn_14 (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<1>_MUXF515)
MUXF6:I0->O 1 0.354 0.000 PROBABILITY_REFRESH_CONTEXT<0>_rn_9 (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<0>_MUXF67)
MUXF7:I0->O 1 0.354 0.000 PROBABILITY_REFRESH_CONTEXT<2>_rn_3 (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<2>_MUXF73)
MUXF8:I0->O 1 0.354 0.608 PROBABILITY_REFRESH_CONTEXT<3>_rn_0 (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<3>_MUXF81)
LUT3_L:I0->LO 1 0.347 0.000 PROBABILITY_REFRESH__n0241109_F (N961)
MUXF5:I0->O 15 0.345 0.763 PROBABILITY_REFRESH__n0241109 (PROBABILITY_REFRESH__n0241)
LUT4_D:I3->O 7 0.347 0.630 PROBABILITY_REFRESH__n0145_1 (PROBABILITY_REFRESH__n01451)
LUT3:I2->O 1 0.347 0.548 PROBABILITY_REFRESH_DENOMINATOR_OUT<3>1 (PROBABILITY_FRACTION2<3>)
LUT4:I1->O 1 0.347 0.409 PROBABILITY_PROBUPDATE__n00144 (CHOICE132)
LUT4:I2->O 20 0.347 0.769 PROBABILITY_PROBUPDATE__n001417 (PROBABILITY_PROBUPDATE_HALVE_VALUES)
MUXF5:S->O 1 0.553 0.382 PROBABILITY_PROBUPDATE_DENOMINATOR_OUT<0>_DENOMINATOR_OUT<0>_rn_4111 (PROBABILITY_NEWPROB<15>)
RAMB16_S36_S36:DIA15 0.000 PROBABILITY_Mram_PROBABILITY_inst_ramb_0
FDRE:C->Q 4 0.449 0.717 PROBABILITY_REFRESH_SHIFTS_32_2 (PROBABILITY_REFRESH_SHIFTS_32_2)
LUT3_L:I1->LO 1 0.347 0.000 PROBABILITY_REFRESH_CONTEXT<1>16 (PROBABILITY_REFRESH_MUX_BLOCK_N64)
MUXF5:I0->O 1 0.345 0.000 PROBABILITY_REFRESH_CONTEXT<0>_rn_18 (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<0>_MUXF57)
MUXF6:I0->O 1 0.354 0.548 PROBABILITY_REFRESH_CONTEXT<2>_rn_7 (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<2>_MUXF62)
LUT4:I1->O 2 0.347 0.545 PROBABILITY_REFRESH__n024172 (CHOICE371)
LUT4_L:I2->LO 1 0.347 0.000 PROBABILITY_REFRESH__n0241109_SW11_F (N988)
MUXF5:I0->O 3 0.345 0.563 PROBABILITY_REFRESH__n0241109_SW11 (N826)
LUT4_D:I2->O 9 0.347 0.665 PROBABILITY_REFRESH__n0145_1 (PROBABILITY_REFRESH__n01451)
LUT4_L:I2->LO 1 0.347 0.000 PROBABILITY_REFRESH_NUMERATOR_OUT<2>12 (N650)
MUXCY:S->O 1 0.235 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<1>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<1>_cyo)
MUXCY:CI->O 1 0.042 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<2>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<2>_cyo)
MUXCY:CI->O 1 0.042 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<3>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<3>_cyo)
MUXCY:CI->O 1 0.042 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<4>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<4>_cyo)
MUXCY:CI->O 1 0.042 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<5>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<5>_cyo)
XORCY:CI->O 2 0.824 0.744 PROBABILITY_PROBUPDATE_UPDATER__n0013<6>_xor (PROBABILITY_PROBUPDATE__n0013<6>)
LUT1_L:I0->LO 1 0.347 0.000 PROBABILITY_PROBUPDATE__n0013<6>_rt (PROBABILITY_PROBUPDATE__n0013<6>_rt)
MUXCY:S->O 0 0.235 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0011<6>cy (PROBABILITY_PROBUPDATE_UPDATER__n0011<6>_cyo)
XORCY:CI->O 1 0.824 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0011<7>_xor (PROBABILITY_PROBUPDATE__n0011<7>)
FDR:D 0.293 PROBABILITY_PROBUPDATE_NUMERATOR4_7
----------------------------------------
Total 9.680ns (4.836ns logic, 4.844ns route)
(50.0% logic, 50.0% route)
Total 9.935ns (6.154ns logic, 3.781ns route)
(61.9% logic, 38.1% route)
 
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLOCK'
Total number of paths / destination ports: 124379 / 894
Total number of paths / destination ports: 94958 / 834
-------------------------------------------------------------------------
Offset: 10.225ns (Levels of Logic = 13)
Source: CONTEXT_SELECT<4> (PAD)
Destination: PROBABILITY_Mram_PROBABILITY_inst_ramb_0 (RAM)
Offset: 10.481ns (Levels of Logic = 18)
Source: CONTEXT_SELECT<1> (PAD)
Destination: PROBABILITY_PROBUPDATE_NUMERATOR4_7 (FF)
Destination Clock: CLOCK rising
 
Data Path: CONTEXT_SELECT<4> to PROBABILITY_Mram_PROBABILITY_inst_ramb_0
Data Path: CONTEXT_SELECT<1> to PROBABILITY_PROBUPDATE_NUMERATOR4_7
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 56 0.653 1.075 CONTEXT_SELECT_4_IBUF (CONTEXT_SELECT_4_IBUF)
LUT3_L:I0->LO 1 0.347 0.000 PROBABILITY_REFRESH_CONTEXT<4>19 (PROBABILITY_REFRESH_MUX_BLOCK_N26)
MUXF5:I0->O 1 0.345 0.000 PROBABILITY_REFRESH_CONTEXT<1>_rn_8 (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<1>_MUXF59)
MUXF6:I0->O 1 0.354 0.000 PROBABILITY_REFRESH_CONTEXT<0>_rn_6 (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<0>_MUXF64)
MUXF7:I1->O 1 0.354 0.000 PROBABILITY_REFRESH_CONTEXT<2>_rn_2 (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<2>_MUXF72)
MUXF8:I1->O 1 0.354 0.608 PROBABILITY_REFRESH_CONTEXT<3>_rn_0 (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<3>_MUXF81)
LUT3_L:I0->LO 1 0.347 0.000 PROBABILITY_REFRESH__n0241109_F (N961)
MUXF5:I0->O 15 0.345 0.763 PROBABILITY_REFRESH__n0241109 (PROBABILITY_REFRESH__n0241)
LUT4_D:I3->O 7 0.347 0.630 PROBABILITY_REFRESH__n0145_1 (PROBABILITY_REFRESH__n01451)
LUT3:I2->O 1 0.347 0.548 PROBABILITY_REFRESH_DENOMINATOR_OUT<3>1 (PROBABILITY_FRACTION2<3>)
LUT4:I1->O 1 0.347 0.409 PROBABILITY_PROBUPDATE__n00144 (CHOICE132)
LUT4:I2->O 20 0.347 0.769 PROBABILITY_PROBUPDATE__n001417 (PROBABILITY_PROBUPDATE_HALVE_VALUES)
MUXF5:S->O 1 0.553 0.382 PROBABILITY_PROBUPDATE_DENOMINATOR_OUT<0>_DENOMINATOR_OUT<0>_rn_4111 (PROBABILITY_NEWPROB<15>)
RAMB16_S36_S36:DIA15 0.000 PROBABILITY_Mram_PROBABILITY_inst_ramb_0
IBUF:I->O 48 0.653 1.060 CONTEXT_SELECT_1_IBUF (CONTEXT_SELECT_1_IBUF)
LUT3_L:I0->LO 1 0.347 0.000 PROBABILITY_REFRESH_CONTEXT<1>15 (PROBABILITY_REFRESH_MUX_BLOCK_N63)
MUXF5:I1->O 1 0.345 0.000 PROBABILITY_REFRESH_CONTEXT<0>_rn_18 (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<0>_MUXF57)
MUXF6:I0->O 1 0.354 0.548 PROBABILITY_REFRESH_CONTEXT<2>_rn_7 (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<2>_MUXF62)
LUT4:I1->O 2 0.347 0.545 PROBABILITY_REFRESH__n024172 (CHOICE371)
LUT4_L:I2->LO 1 0.347 0.000 PROBABILITY_REFRESH__n0241109_SW11_F (N988)
MUXF5:I0->O 3 0.345 0.563 PROBABILITY_REFRESH__n0241109_SW11 (N826)
LUT4_D:I2->O 9 0.347 0.665 PROBABILITY_REFRESH__n0145_1 (PROBABILITY_REFRESH__n01451)
LUT4_L:I2->LO 1 0.347 0.000 PROBABILITY_REFRESH_NUMERATOR_OUT<2>12 (N650)
MUXCY:S->O 1 0.235 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<1>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<1>_cyo)
MUXCY:CI->O 1 0.042 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<2>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<2>_cyo)
MUXCY:CI->O 1 0.042 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<3>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<3>_cyo)
MUXCY:CI->O 1 0.042 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<4>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<4>_cyo)
MUXCY:CI->O 1 0.042 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0013<5>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<5>_cyo)
XORCY:CI->O 2 0.824 0.744 PROBABILITY_PROBUPDATE_UPDATER__n0013<6>_xor (PROBABILITY_PROBUPDATE__n0013<6>)
LUT1_L:I0->LO 1 0.347 0.000 PROBABILITY_PROBUPDATE__n0013<6>_rt (PROBABILITY_PROBUPDATE__n0013<6>_rt)
MUXCY:S->O 0 0.235 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0011<6>cy (PROBABILITY_PROBUPDATE_UPDATER__n0011<6>_cyo)
XORCY:CI->O 1 0.824 0.000 PROBABILITY_PROBUPDATE_UPDATER__n0011<7>_xor (PROBABILITY_PROBUPDATE__n0011<7>)
FDR:D 0.293 PROBABILITY_PROBUPDATE_NUMERATOR4_7
----------------------------------------
Total 10.225ns (5.040ns logic, 5.185ns route)
(49.3% logic, 50.7% route)
Total 10.481ns (6.358ns logic, 4.123ns route)
(60.7% logic, 39.3% route)
 
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLOCK'
Total number of paths / destination ports: 426 / 2
-------------------------------------------------------------------------
Offset: 11.576ns (Levels of Logic = 7)
Source: ARITH_Mmult__n00001_inst_mult_2 (MULT)
Offset: 11.374ns (Levels of Logic = 7)
Source: ARITH_Mmult__n00001_inst_mult_1 (MULT)
Destination: DATA_OUT (PAD)
Source Clock: CLOCK rising
 
Data Path: ARITH_Mmult__n00001_inst_mult_2 to DATA_OUT
Data Path: ARITH_Mmult__n00001_inst_mult_1 to DATA_OUT
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
MULT18X18S:C->P24 3 1.976 0.701 ARITH_Mmult__n00001_inst_mult_2 (ARITH_PRODUCT<24>)
MULT18X18S:C->P22 3 1.782 0.700 ARITH_Mmult__n00001_inst_mult_1 (ARITH_PRODUCT<22>)
LUT2_L:I1->LO 1 0.347 0.000 ARITH_ARITHMETIC_UNIT_RESULT_OUT1<14>lut (ARITH_N55)
MUXCY:S->O 0 0.235 0.000 ARITH_ARITHMETIC_UNIT_RESULT_OUT1<14>cy (ARITH_ARITHMETIC_UNIT_RESULT_OUT1<14>_cyo)
XORCY:CI->O 3 0.824 0.701 ARITH_ARITHMETIC_UNIT_RESULT_OUT1<15>_xor (ARITHMETIC_UNIT_RESULT_OUT1<15>)
LUT2_L:I1->LO 1 0.347 0.000 XNor_stagelut15 (N17)
MUXCY:S->O 71 0.794 1.044 XNor_stagecy_rn_14 (OUTPUT__n0001)
MUXCY:S->O 67 0.794 1.036 XNor_stagecy_rn_14 (OUTPUT__n0001)
LUT2_D:I1->O 2 0.347 0.518 DATA_OUT1 (DATA_OUT_OBUF)
OBUF:I->O 3.743 DATA_OUT_OBUF (DATA_OUT)
----------------------------------------
Total 11.576ns (8.613ns logic, 2.963ns route)
(74.4% logic, 25.6% route)
Total 11.374ns (8.419ns logic, 2.955ns route)
(74.0% logic, 26.0% route)
 
=========================================================================
CPU : 27.55 / 29.98 s | Elapsed : 28.00 / 30.00 s
CPU : 25.86 / 26.25 s | Elapsed : 26.00 / 27.00 s
-->
 
Total memory usage is 109820 kilobytes
Total memory usage is 128316 kilobytes
 
Number of errors : 0 ( 0 filtered)
Number of warnings : 18 ( 0 filtered)
Number of warnings : 21 ( 0 filtered)
Number of infos : 4 ( 0 filtered)
 
/trunk/docs/synthesis_reports/common/updater.syr
1,10 → 1,10
Release 7.1.04i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.33 s | Elapsed : 0.00 / 1.00 s
CPU : 0.00 / 2.52 s | Elapsed : 0.00 / 2.00 s
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.33 s | Elapsed : 0.00 / 1.00 s
CPU : 0.00 / 2.52 s | Elapsed : 0.00 / 2.00 s
--> Reading design: updater.prj
 
32,7 → 32,7
---- Target Parameters
Output File Name : "updater"
Output Format : NGC
Target Device : xc2v250-6-cs144
Target Device : xc2v2000-6-bg575
 
---- Source Options
Top Module Name : updater
65,7 → 65,7
 
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Optimization Effort : 2
Keep Hierarchy : NO
Global Optimization : AllClockNets
RTL Output : Yes
95,8 → 95,9
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/UPDATER.vhd" in Library work.
Architecture rtl of Entity updater is up to date.
Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/UPDATER.vhd" in Library work.
Entity <updater> compiled.
Entity <updater> (Architecture <rtl>) compiled.
 
=========================================================================
* HDL Analysis *
110,25 → 111,24
=========================================================================
 
Synthesizing Unit <updater>.
Related source file is "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/UPDATER.vhd".
WARNING:Xst:1780 - Signal <HALVING_ALLOWED> is never used or assigned.
Found 10-bit 4-to-1 multiplexer for signal <NUMERATOR_OUT>.
Found 10-bit 4-to-1 multiplexer for signal <DENOMINATOR_OUT>.
Related source file is "C:/Xilinx/bin/ArithmeticCoder/UPDATER.vhd".
Found 8-bit 4-to-1 multiplexer for signal <NUMERATOR_OUT>.
Found 8-bit 4-to-1 multiplexer for signal <DENOMINATOR_OUT>.
Found 1-bit register for signal <UPDATE>.
Found 10-bit adder for signal <$n0009> created at line 51.
Found 10-bit adder for signal <$n0011> created at line 73.
Found 10-bit adder for signal <$n0012> created at line 84.
Found 10-bit adder for signal <$n0013> created at line 62.
Found 10-bit register for signal <DENOMINATOR2>.
Found 10-bit register for signal <NUMERATOR1>.
Found 10-bit register for signal <NUMERATOR2>.
Found 10-bit register for signal <NUMERATOR3>.
Found 10-bit register for signal <NUMERATOR4>.
Found 8-bit adder for signal <$n0009> created at line 50.
Found 8-bit adder for signal <$n0011> created at line 72.
Found 8-bit adder for signal <$n0012> created at line 83.
Found 8-bit adder for signal <$n0013> created at line 61.
Found 8-bit register for signal <DENOMINATOR2>.
Found 8-bit register for signal <NUMERATOR1>.
Found 8-bit register for signal <NUMERATOR2>.
Found 8-bit register for signal <NUMERATOR3>.
Found 8-bit register for signal <NUMERATOR4>.
Found 1-bit xor2 for signal <UPDATE_SWITCH>.
Summary:
inferred 1 D-type flip-flop(s).
inferred 4 Adder/Subtractor(s).
inferred 20 Multiplexer(s).
inferred 16 Multiplexer(s).
Unit <updater> synthesized.
 
 
146,12 → 146,12
 
Macro Statistics
# Adders/Subtractors : 4
10-bit adder : 4
8-bit adder : 4
# Registers : 6
1-bit register : 1
10-bit register : 5
8-bit register : 5
# Multiplexers : 2
10-bit 4-to-1 multiplexer : 2
8-bit 4-to-1 multiplexer : 2
# Xors : 1
1-bit xor2 : 1
 
162,11 → 162,11
=========================================================================
 
Optimizing unit <updater> ...
Loading device for application Rf_Device from file '2v250.nph' in environment C:/Xilinx.
Loading device for application Rf_Device from file '2v2000.nph' in environment C:/Xilinx.
 
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block updater, actual ratio is 2.
Found area constraint ratio of 100 (+ 5) on block updater, actual ratio is 0.
 
=========================================================================
* Final Report *
179,47 → 179,47
Keep Hierarchy : NO
 
Design Statistics
# IOs : 45
# IOs : 37
 
Macro Statistics :
# Registers : 51
# 1-bit register : 51
# Registers : 41
# 1-bit register : 41
# Multiplexers : 2
# 10-bit 4-to-1 multiplexer : 2
# 8-bit 4-to-1 multiplexer : 2
# Adders/Subtractors : 4
# 10-bit adder : 4
# 8-bit adder : 4
 
Cell Usage :
# BELS : 155
# BELS : 123
# GND : 1
# INV : 3
# LUT1 : 35
# LUT2 : 9
# LUT3 : 20
# LUT4 : 5
# MUXCY : 36
# MUXF5 : 10
# LUT1 : 27
# LUT2 : 2
# LUT3 : 6
# LUT4 : 20
# MUXCY : 28
# MUXF5 : 8
# VCC : 1
# XORCY : 35
# FlipFlops/Latches : 51
# FDR : 46
# XORCY : 27
# FlipFlops/Latches : 41
# FDR : 36
# FDS : 5
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 44
# IBUF : 23
# OBUF : 21
# IO Buffers : 36
# IBUF : 19
# OBUF : 17
=========================================================================
 
Device utilization summary:
---------------------------
 
Selected Device : 2v250cs144-6
Selected Device : 2v2000bg575-6
 
Number of Slices: 40 out of 1536 2%
Number of Slice Flip Flops: 51 out of 3072 1%
Number of 4 input LUTs: 69 out of 3072 2%
Number of bonded IOBs: 45 out of 92 48%
Number of Slices: 32 out of 10752 0%
Number of Slice Flip Flops: 41 out of 21504 0%
Number of 4 input LUTs: 55 out of 21504 0%
Number of bonded IOBs: 37 out of 408 9%
Number of GCLKs: 1 out of 16 6%
 
 
235,7 → 235,7
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
CLOCK | BUFGP | 51 |
CLOCK | BUFGP | 41 |
-----------------------------------+------------------------+-------+
 
Timing Summary:
243,9 → 243,9
Speed Grade: -6
 
Minimum period: No path found
Minimum input arrival time before clock: 5.514ns
Minimum input arrival time before clock: 5.430ns
Maximum output required time after clock: 5.814ns
Maximum combinational path delay: 8.733ns
Maximum combinational path delay: 8.314ns
 
Timing Detail:
--------------
253,14 → 253,14
 
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLOCK'
Total number of paths / destination ports: 464 / 102
Total number of paths / destination ports: 291 / 82
-------------------------------------------------------------------------
Offset: 5.514ns (Levels of Logic = 13)
Offset: 5.430ns (Levels of Logic = 11)
Source: NUMERATOR<2> (PAD)
Destination: NUMERATOR4_9 (FF)
Destination: NUMERATOR4_7 (FF)
Destination Clock: CLOCK rising
 
Data Path: NUMERATOR<2> to NUMERATOR4_9
Data Path: NUMERATOR<2> to NUMERATOR4_7
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
271,34 → 271,32
MUXCY:CI->O 1 0.042 0.000 updater__n0013<3>cy (updater__n0013<3>_cyo)
MUXCY:CI->O 1 0.042 0.000 updater__n0013<4>cy (updater__n0013<4>_cyo)
MUXCY:CI->O 1 0.042 0.000 updater__n0013<5>cy (updater__n0013<5>_cyo)
MUXCY:CI->O 1 0.042 0.000 updater__n0013<6>cy (updater__n0013<6>_cyo)
MUXCY:CI->O 1 0.042 0.000 updater__n0013<7>cy (updater__n0013<7>_cyo)
XORCY:CI->O 2 0.824 0.744 updater__n0013<8>_xor (_n0013<8>)
LUT1:I0->O 1 0.347 0.000 _n0013<8>_rt (_n0013<8>_rt)
MUXCY:S->O 0 0.235 0.000 updater__n0011<8>cy (updater__n0011<8>_cyo)
XORCY:CI->O 1 0.824 0.000 updater__n0011<9>_xor (_n0011<9>)
FDR:D 0.293 NUMERATOR4_9
XORCY:CI->O 2 0.824 0.744 updater__n0013<6>_xor (_n0013<6>)
LUT1:I0->O 1 0.347 0.000 _n0013<6>_rt (_n0013<6>_rt)
MUXCY:S->O 0 0.235 0.000 updater__n0011<6>cy (updater__n0011<6>_cyo)
XORCY:CI->O 1 0.824 0.000 updater__n0011<7>_xor (_n0011<7>)
FDR:D 0.293 NUMERATOR4_7
----------------------------------------
Total 5.514ns (4.010ns logic, 1.504ns route)
(72.7% logic, 27.3% route)
Total 5.430ns (3.926ns logic, 1.504ns route)
(72.3% logic, 27.7% route)
 
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLOCK'
Total number of paths / destination ports: 51 / 21
Total number of paths / destination ports: 41 / 17
-------------------------------------------------------------------------
Offset: 5.814ns (Levels of Logic = 3)
Source: NUMERATOR2_9 (FF)
Destination: NUMERATOR_OUT<9> (PAD)
Source: NUMERATOR2_7 (FF)
Destination: NUMERATOR_OUT<7> (PAD)
Source Clock: CLOCK rising
 
Data Path: NUMERATOR2_9 to NUMERATOR_OUT<9>
Data Path: NUMERATOR2_7 to NUMERATOR_OUT<7>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDR:C->Q 1 0.449 0.548 NUMERATOR2_9 (NUMERATOR2_9)
LUT3:I1->O 1 0.347 0.000 DATA_IN19 (MUX_BLOCK_N19)
MUXF5:I0->O 1 0.345 0.383 DENOMINATOR_OUT<0>_DENOMINATOR_OUT<0>_rn_8 (NUMERATOR_OUT_9_OBUF)
OBUF:I->O 3.743 NUMERATOR_OUT_9_OBUF (NUMERATOR_OUT<9>)
FDR:C->Q 1 0.449 0.548 NUMERATOR2_7 (NUMERATOR2_7)
LUT4:I1->O 1 0.347 0.000 DENOMINATOR_OUT<0>_DENOMINATOR_OUT<0>_rn_6_F (N25)
MUXF5:I0->O 1 0.345 0.383 DENOMINATOR_OUT<0>_DENOMINATOR_OUT<0>_rn_6 (NUMERATOR_OUT_7_OBUF)
OBUF:I->O 3.743 NUMERATOR_OUT_7_OBUF (NUMERATOR_OUT<7>)
----------------------------------------
Total 5.814ns (4.884ns logic, 0.930ns route)
(84.0% logic, 16.0% route)
305,34 → 303,33
 
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 224 / 20
Total number of paths / destination ports: 204 / 16
-------------------------------------------------------------------------
Delay: 8.733ns (Levels of Logic = 6)
Delay: 8.314ns (Levels of Logic = 5)
Source: DENOMINATOR<0> (PAD)
Destination: DENOMINATOR_OUT<9> (PAD)
Destination: DENOMINATOR_OUT<1> (PAD)
 
Data Path: DENOMINATOR<0> to DENOMINATOR_OUT<9>
Data Path: DENOMINATOR<0> to DENOMINATOR_OUT<1>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 2 0.653 0.743 DENOMINATOR_0_IBUF (DENOMINATOR_0_IBUF)
LUT4:I0->O 1 0.347 0.415 _n001410 (CHOICE6)
LUT4:I3->O 1 0.347 0.415 _n001416_SW0 (N27)
LUT4:I3->O 20 0.347 0.994 _n001416 (HALVE_VALUES)
LUT2:I0->O 1 0.347 0.383 DENOMINATOR_OUT<9>1 (DENOMINATOR_OUT_9_OBUF)
OBUF:I->O 3.743 DENOMINATOR_OUT_9_OBUF (DENOMINATOR_OUT<9>)
LUT4:I0->O 23 0.347 1.007 _n00144 (CHOICE167)
LUT2:I0->O 2 0.347 0.744 _n001410 (HALVE_VALUES)
LUT4:I0->O 1 0.347 0.383 DENOMINATOR_OUT<1>1 (DENOMINATOR_OUT_1_OBUF)
OBUF:I->O 3.743 DENOMINATOR_OUT_1_OBUF (DENOMINATOR_OUT<1>)
----------------------------------------
Total 8.733ns (5.784ns logic, 2.949ns route)
(66.2% logic, 33.8% route)
Total 8.314ns (5.437ns logic, 2.877ns route)
(65.4% logic, 34.6% route)
 
=========================================================================
CPU : 4.88 / 5.23 s | Elapsed : 5.00 / 6.00 s
CPU : 6.39 / 8.98 s | Elapsed : 7.00 / 9.00 s
-->
 
Total memory usage is 100604 kilobytes
Total memory usage is 121148 kilobytes
 
Number of errors : 0 ( 0 filtered)
Number of warnings : 1 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
 
/trunk/docs/synthesis_reports/common/divider.syr
1,10 → 1,10
Release 7.1.04i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.34 s | Elapsed : 0.00 / 0.00 s
CPU : 0.00 / 0.36 s | Elapsed : 0.00 / 0.00 s
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.34 s | Elapsed : 0.00 / 0.00 s
CPU : 0.00 / 0.36 s | Elapsed : 0.00 / 0.00 s
--> Reading design: divider.prj
 
32,7 → 32,7
---- Target Parameters
Output File Name : "divider"
Output Format : NGC
Target Device : xc2v250-6-cs144
Target Device : xc2v2000-6-bg575
 
---- Source Options
Top Module Name : divider
65,7 → 65,7
 
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Optimization Effort : 2
Keep Hierarchy : NO
Global Optimization : AllClockNets
RTL Output : Yes
95,7 → 95,7
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/Divider.vhd" in Library work.
Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/Divider.vhd" in Library work.
Architecture rtl of Entity divider is up to date.
 
=========================================================================
102,7 → 102,7
* HDL Analysis *
=========================================================================
Analyzing Entity <divider> (Architecture <rtl>).
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/Divider.vhd" line 1079: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/Divider.vhd" line 308: Index value(s) does not match array range, simulation mismatch.
Entity <divider> analyzed. Unit <divider> generated.
 
 
111,23 → 111,20
=========================================================================
 
Synthesizing Unit <divider>.
Related source file is "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/Divider.vhd".
WARNING:Xst:646 - Signal <TOTAL<41:32>> is assigned but never used.
WARNING:Xst:646 - Signal <TOTAL<21:0>> is assigned but never used.
Found 1022x32-bit ROM for signal <$n0002> created at line 1079.
Found 16x10-bit multiplier for signal <$n0003> created at line 1086.
Found 16x10-bit multiplier for signal <$n0004> created at line 1093.
Found 10-bit subtractor for signal <INDEX>.
Found 10-bit register for signal <NUMERATOR2>.
Found 26-bit register for signal <PRODUCT1>.
Found 26-bit register for signal <PRODUCT2>.
Found 32-bit register for signal <RECIPROCAL>.
Found 42-bit adder for signal <TOTAL>.
Related source file is "C:/Xilinx/bin/ArithmeticCoder/Divider.vhd".
WARNING:Xst:646 - Signal <PRODUCT<23:16>> is assigned but never used.
WARNING:Xst:646 - Signal <PRODUCT<7:0>> is assigned but never used.
Found 254x16-bit ROM for signal <$n0002> created at line 308.
Found 16x8-bit multiplier for signal <$n0003> created at line 315.
Found 8-bit subtractor for signal <INDEX>.
Found 8-bit register for signal <NUMERATOR2>.
Found 24-bit register for signal <PRODUCT>.
Found 16-bit register for signal <RECIPROCAL>.
Summary:
inferred 1 ROM(s).
inferred 84 D-type flip-flop(s).
inferred 2 Adder/Subtractor(s).
inferred 2 Multiplier(s).
inferred 40 D-type flip-flop(s).
inferred 1 Adder/Subtractor(s).
inferred 1 Multiplier(s).
Unit <divider> synthesized.
 
 
142,9 → 139,6
Found registered multiplier on signal <_n0003>:
- 1 register level(s) found in a register connected to the multiplier macro ouput.
Pushing register(s) into the multiplier macro.
Found registered multiplier on signal <_n0004>:
- 1 register level(s) found in a register connected to the multiplier macro ouput.
Pushing register(s) into the multiplier macro.
Advanced Registered AddSub inference ...
Dynamic shift register inference ...
 
153,14 → 147,13
 
Macro Statistics
# Block RAMs : 1
1022x32-bit single-port block RAM : 1
# Multipliers : 2
16x10-bit registered multiplier : 2
# Adders/Subtractors : 2
10-bit subtractor : 1
42-bit adder : 1
254x16-bit single-port block RAM : 1
# Multipliers : 1
16x8-bit registered multiplier : 1
# Adders/Subtractors : 1
8-bit subtractor : 1
# Registers : 1
10-bit register : 1
8-bit register : 1
 
=========================================================================
 
169,11 → 162,11
=========================================================================
 
Optimizing unit <divider> ...
Loading device for application Rf_Device from file '2v250.nph' in environment C:/Xilinx.
Loading device for application Rf_Device from file '2v2000.nph' in environment C:/Xilinx.
 
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block divider, actual ratio is 1.
Found area constraint ratio of 100 (+ 5) on block divider, actual ratio is 0.
 
=========================================================================
* Final Report *
186,52 → 179,50
Keep Hierarchy : NO
 
Design Statistics
# IOs : 32
# IOs : 26
 
Macro Statistics :
# RAM : 1
# 1022x32-bit single-port block RAM: 1
# Registers : 10
# 1-bit register : 10
# Adders/Subtractors : 2
# 10-bit subtractor : 1
# 42-bit adder : 1
# Multipliers : 2
# 16x10-bit registered multiplier: 2
# 254x16-bit single-port block RAM: 1
# Registers : 8
# 1-bit register : 8
# Adders/Subtractors : 1
# 8-bit subtractor : 1
# Multipliers : 1
# 16x8-bit registered multiplier: 1
 
Cell Usage :
# BELS : 69
# BELS : 13
# GND : 1
# LUT1 : 5
# LUT2 : 20
# MUXCY : 23
# LUT2 : 4
# LUT3 : 2
# LUT4 : 5
# VCC : 1
# XORCY : 19
# FlipFlops/Latches : 10
# FDR : 9
# FlipFlops/Latches : 8
# FDR : 7
# FDS : 1
# RAMS : 2
# RAMB16_S18 : 2
# RAMS : 1
# RAMB16_S36 : 1
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 31
# IBUF : 21
# OBUF : 10
# MULTs : 2
# MULT18X18S : 2
# IO Buffers : 25
# IBUF : 17
# OBUF : 8
# MULTs : 1
# MULT18X18S : 1
=========================================================================
 
Device utilization summary:
---------------------------
 
Selected Device : 2v250cs144-6
Selected Device : 2v2000bg575-6
 
Number of Slices: 19 out of 1536 1%
Number of Slice Flip Flops: 10 out of 3072 0%
Number of 4 input LUTs: 25 out of 3072 0%
Number of bonded IOBs: 32 out of 92 34%
Number of BRAMs: 2 out of 24 8%
Number of MULT18X18s: 2 out of 24 8%
Number of Slices: 6 out of 10752 0%
Number of Slice Flip Flops: 8 out of 21504 0%
Number of 4 input LUTs: 11 out of 21504 0%
Number of bonded IOBs: 26 out of 408 6%
Number of BRAMs: 1 out of 56 1%
Number of MULT18X18s: 1 out of 56 1%
Number of GCLKs: 1 out of 16 6%
 
 
247,7 → 238,7
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
CLOCK | BUFGP | 12 |
CLOCK | BUFGP | 9 |
-----------------------------------+------------------------+-------+
 
Timing Summary:
254,9 → 245,9
---------------
Speed Grade: -6
 
Minimum period: 3.967ns (Maximum Frequency: 252.048MHz)
Minimum input arrival time before clock: 1.644ns
Maximum output required time after clock: 8.362ns
Minimum period: 3.832ns (Maximum Frequency: 260.994MHz)
Minimum input arrival time before clock: 1.615ns
Maximum output required time after clock: 5.229ns
Maximum combinational path delay: No path found
 
Timing Detail:
265,77 → 256,69
 
=========================================================================
Timing constraint: Default period analysis for Clock 'CLOCK'
Clock period: 3.967ns (frequency: 252.048MHz)
Total number of paths / destination ports: 20 / 20
Clock period: 3.832ns (frequency: 260.994MHz)
Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Delay: 3.967ns (Levels of Logic = 0)
Source: NUMERATOR2_9 (FF)
Destination: Mmult__n00041_inst_mult_0 (MULT)
Delay: 3.832ns (Levels of Logic = 0)
Source: NUMERATOR2_7 (FF)
Destination: Mmult__n00031_inst_mult_0 (MULT)
Source Clock: CLOCK rising
Destination Clock: CLOCK rising
 
Data Path: NUMERATOR2_9 to Mmult__n00041_inst_mult_0
Data Path: NUMERATOR2_7 to Mmult__n00031_inst_mult_0
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDR:C->Q 2 0.449 0.519 NUMERATOR2_9 (NUMERATOR2_9)
MULT18X18S:B9 3.000 Mmult__n00041_inst_mult_0
FDR:C->Q 1 0.449 0.382 NUMERATOR2_7 (NUMERATOR2_7)
MULT18X18S:B7 3.000 Mmult__n00031_inst_mult_0
----------------------------------------
Total 3.967ns (3.449ns logic, 0.519ns route)
(86.9% logic, 13.1% route)
Total 3.832ns (3.449ns logic, 0.382ns route)
(90.0% logic, 10.0% route)
 
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLOCK'
Total number of paths / destination ports: 20 / 20
Total number of paths / destination ports: 16 / 16
-------------------------------------------------------------------------
Offset: 1.644ns (Levels of Logic = 1)
Offset: 1.615ns (Levels of Logic = 1)
Source: RESET (PAD)
Destination: NUMERATOR2_7 (FF)
Destination: NUMERATOR2_5 (FF)
Destination Clock: CLOCK rising
 
Data Path: RESET to NUMERATOR2_7
Data Path: RESET to NUMERATOR2_5
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 20 0.653 0.769 RESET_IBUF (RESET_IBUF)
IBUF:I->O 16 0.653 0.740 RESET_IBUF (RESET_IBUF)
FDR:R 0.222 NUMERATOR2_2
----------------------------------------
Total 1.644ns (0.875ns logic, 0.769ns route)
(53.2% logic, 46.8% route)
Total 1.615ns (0.875ns logic, 0.740ns route)
(54.2% logic, 45.8% route)
 
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLOCK'
Total number of paths / destination ports: 299 / 10
Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Offset: 8.362ns (Levels of Logic = 9)
Source: Mmult__n00041_inst_mult_0 (MULT)
Destination: QUOTIENT<9> (PAD)
Offset: 5.229ns (Levels of Logic = 1)
Source: Mmult__n00031_inst_mult_0 (MULT)
Destination: QUOTIENT<7> (PAD)
Source Clock: CLOCK rising
 
Data Path: Mmult__n00041_inst_mult_0 to QUOTIENT<9>
Data Path: Mmult__n00031_inst_mult_0 to QUOTIENT<7>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
MULT18X18S:C->P25 1 2.073 0.548 Mmult__n00041_inst_mult_0 (PRODUCT2<25>)
LUT2:I1->O 1 0.347 0.000 divider_QUOTIENT<3>lut (N23)
MUXCY:S->O 1 0.235 0.000 divider_QUOTIENT<3>cy (divider_QUOTIENT<3>_cyo)
MUXCY:CI->O 1 0.042 0.000 divider_QUOTIENT<4>cy (divider_QUOTIENT<4>_cyo)
MUXCY:CI->O 1 0.042 0.000 divider_QUOTIENT<5>cy (divider_QUOTIENT<5>_cyo)
MUXCY:CI->O 1 0.042 0.000 divider_QUOTIENT<6>cy (divider_QUOTIENT<6>_cyo)
MUXCY:CI->O 1 0.042 0.000 divider_QUOTIENT<7>cy (divider_QUOTIENT<7>_cyo)
MUXCY:CI->O 0 0.042 0.000 divider_QUOTIENT<8>cy (divider_QUOTIENT<8>_cyo)
XORCY:CI->O 1 0.824 0.383 divider_QUOTIENT<9>_xor (QUOTIENT_9_OBUF)
OBUF:I->O 3.743 QUOTIENT_9_OBUF (QUOTIENT<9>)
MULT18X18S:C->P15 1 1.103 0.383 Mmult__n00031_inst_mult_0 (QUOTIENT_7_OBUF)
OBUF:I->O 3.743 QUOTIENT_7_OBUF (QUOTIENT<7>)
----------------------------------------
Total 8.362ns (7.432ns logic, 0.930ns route)
(88.9% logic, 11.1% route)
Total 5.229ns (4.846ns logic, 0.383ns route)
(92.7% logic, 7.3% route)
 
=========================================================================
CPU : 5.28 / 5.66 s | Elapsed : 5.00 / 5.00 s
CPU : 4.83 / 5.22 s | Elapsed : 5.00 / 5.00 s
-->
 
Total memory usage is 101628 kilobytes
Total memory usage is 121148 kilobytes
 
Number of errors : 0 ( 0 filtered)
Number of warnings : 3 ( 0 filtered)
/trunk/docs/synthesis_reports/common/context_manager.syr
1,10 → 1,10
Release 7.1.04i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.33 s | Elapsed : 0.00 / 0.00 s
CPU : 0.02 / 0.36 s | Elapsed : 0.00 / 0.00 s
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.33 s | Elapsed : 0.00 / 0.00 s
CPU : 0.00 / 0.36 s | Elapsed : 0.00 / 0.00 s
--> Reading design: context_manager.prj
 
32,7 → 32,7
---- Target Parameters
Output File Name : "context_manager"
Output Format : NGC
Target Device : xc2v250-6-cs144
Target Device : xc2v2000-6-bg575
 
---- Source Options
Top Module Name : context_manager
65,7 → 65,7
 
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Optimization Effort : 2
Keep Hierarchy : NO
Global Optimization : AllClockNets
RTL Output : Yes
95,13 → 95,13
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/Divider.vhd" in Library work.
Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/Divider.vhd" in Library work.
Architecture rtl of Entity divider is up to date.
Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/UPDATER.vhd" in Library work.
Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/UPDATER.vhd" in Library work.
Architecture rtl of Entity updater is up to date.
Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd" in Library work.
Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" in Library work.
Architecture rtl of Entity halving_manager is up to date.
Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/CONTEXT_MANAGER.vhd" in Library work.
Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/CONTEXT_MANAGER.vhd" in Library work.
Architecture rtl of Entity context_manager is up to date.
 
=========================================================================
108,12 → 108,14
* HDL Analysis *
=========================================================================
Analyzing Entity <context_manager> (Architecture <rtl>).
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/CONTEXT_MANAGER.vhd" line 133: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/CONTEXT_MANAGER.vhd" line 137: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/CONTEXT_MANAGER.vhd" line 118: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/CONTEXT_MANAGER.vhd" line 133: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/CONTEXT_MANAGER.vhd" line 137: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/CONTEXT_MANAGER.vhd" line 141: Index value(s) does not match array range, simulation mismatch.
Entity <context_manager> analyzed. Unit <context_manager> generated.
 
Analyzing Entity <DIVIDER> (Architecture <rtl>).
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/Divider.vhd" line 1079: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/Divider.vhd" line 308: Index value(s) does not match array range, simulation mismatch.
Entity <DIVIDER> analyzed. Unit <DIVIDER> generated.
 
Analyzing Entity <UPDATER> (Architecture <rtl>).
120,10 → 122,11
Entity <UPDATER> analyzed. Unit <UPDATER> generated.
 
Analyzing Entity <HALVING_MANAGER> (Architecture <rtl>).
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd" line 71: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd" line 71: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd" line 73: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd" line 108: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" line 71: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" line 71: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" line 73: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:1610 - "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" line 78: Width mismatch. <NUMERATOR2> has a width of 8 bits but assigned expression is 10-bit wide.
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" line 108: Index value(s) does not match array range, simulation mismatch.
Entity <HALVING_MANAGER> analyzed. Unit <HALVING_MANAGER> generated.
 
 
132,7 → 135,7
=========================================================================
 
Synthesizing Unit <HALVING_MANAGER>.
Related source file is "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd".
Related source file is "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd".
Found 3-bit 46-to-1 multiplexer for signal <$n0002> created at line 108.
Found 3-bit 4-to-1 multiplexer for signal <$n0050>.
Found 3-bit 4-to-1 multiplexer for signal <$n0051>.
226,13 → 229,13
Found 3-bit addsub for signal <$n0142>.
Found 3-bit addsub for signal <$n0143>.
Found 3-bit addsub for signal <$n0144>.
Found 10-bit comparator greater for signal <$n0147> created at line 99.
Found 8-bit comparator greater for signal <$n0147> created at line 99.
Found 3-bit comparator greater for signal <$n0241> created at line 108.
Found 1-bit register for signal <AFTER_TRIGGER>.
Found 10-bit register for signal <DENOMINATOR>.
Found 10-bit adder for signal <DENOMINATOR2>.
Found 10-bit register for signal <NUMERATOR>.
Found 10-bit adder for signal <NUMERATOR2>.
Found 8-bit register for signal <DENOMINATOR>.
Found 8-bit adder for signal <DENOMINATOR2>.
Found 8-bit register for signal <NUMERATOR>.
Found 8-bit adder for signal <NUMERATOR2>.
Found 138-bit register for signal <SHIFTS>.
Summary:
inferred 139 D-type flip-flop(s).
243,55 → 246,51
 
 
Synthesizing Unit <UPDATER>.
Related source file is "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/UPDATER.vhd".
WARNING:Xst:1780 - Signal <HALVING_ALLOWED> is never used or assigned.
Related source file is "C:/Xilinx/bin/ArithmeticCoder/UPDATER.vhd".
Found 1-bit register for signal <UPDATE>.
Found 10-bit 4-to-1 multiplexer for signal <DENOMINATOR_OUT>.
Found 10-bit 4-to-1 multiplexer for signal <NUMERATOR_OUT>.
Found 10-bit adder for signal <$n0009> created at line 51.
Found 10-bit adder for signal <$n0011> created at line 73.
Found 10-bit adder for signal <$n0012> created at line 84.
Found 10-bit adder for signal <$n0013> created at line 62.
Found 10-bit register for signal <DENOMINATOR2>.
Found 10-bit register for signal <NUMERATOR1>.
Found 10-bit register for signal <NUMERATOR2>.
Found 10-bit register for signal <NUMERATOR3>.
Found 10-bit register for signal <NUMERATOR4>.
Found 8-bit 4-to-1 multiplexer for signal <DENOMINATOR_OUT>.
Found 8-bit 4-to-1 multiplexer for signal <NUMERATOR_OUT>.
Found 8-bit adder for signal <$n0009> created at line 50.
Found 8-bit adder for signal <$n0011> created at line 72.
Found 8-bit adder for signal <$n0012> created at line 83.
Found 8-bit adder for signal <$n0013> created at line 61.
Found 8-bit register for signal <DENOMINATOR2>.
Found 8-bit register for signal <NUMERATOR1>.
Found 8-bit register for signal <NUMERATOR2>.
Found 8-bit register for signal <NUMERATOR3>.
Found 8-bit register for signal <NUMERATOR4>.
Found 1-bit xor2 for signal <UPDATE_SWITCH>.
Summary:
inferred 1 D-type flip-flop(s).
inferred 4 Adder/Subtractor(s).
inferred 20 Multiplexer(s).
inferred 16 Multiplexer(s).
Unit <UPDATER> synthesized.
 
 
Synthesizing Unit <DIVIDER>.
Related source file is "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/Divider.vhd".
WARNING:Xst:646 - Signal <TOTAL<41:32>> is assigned but never used.
WARNING:Xst:646 - Signal <TOTAL<21:0>> is assigned but never used.
Found 1022x32-bit ROM for signal <$n0002> created at line 1079.
Found 16x10-bit multiplier for signal <$n0003> created at line 1086.
Found 16x10-bit multiplier for signal <$n0004> created at line 1093.
Found 10-bit subtractor for signal <INDEX>.
Found 10-bit register for signal <NUMERATOR2>.
Found 26-bit register for signal <PRODUCT1>.
Found 26-bit register for signal <PRODUCT2>.
Found 32-bit register for signal <RECIPROCAL>.
Found 42-bit adder for signal <TOTAL>.
Related source file is "C:/Xilinx/bin/ArithmeticCoder/Divider.vhd".
WARNING:Xst:646 - Signal <PRODUCT<23:16>> is assigned but never used.
WARNING:Xst:646 - Signal <PRODUCT<7:0>> is assigned but never used.
Found 254x16-bit ROM for signal <$n0002> created at line 308.
Found 16x8-bit multiplier for signal <$n0003> created at line 315.
Found 8-bit subtractor for signal <INDEX>.
Found 8-bit register for signal <NUMERATOR2>.
Found 24-bit register for signal <PRODUCT>.
Found 16-bit register for signal <RECIPROCAL>.
Summary:
inferred 1 ROM(s).
inferred 84 D-type flip-flop(s).
inferred 2 Adder/Subtractor(s).
inferred 2 Multiplier(s).
inferred 40 D-type flip-flop(s).
inferred 1 Adder/Subtractor(s).
inferred 1 Multiplier(s).
Unit <DIVIDER> synthesized.
 
 
Synthesizing Unit <context_manager>.
Related source file is "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/CONTEXT_MANAGER.vhd".
Found 46x20-bit dual-port block RAM for signal <PROBABILITY>.
Related source file is "C:/Xilinx/bin/ArithmeticCoder/CONTEXT_MANAGER.vhd".
Found 46x16-bit dual-port block RAM for signal <PROBABILITY>.
-----------------------------------------------------------------------
| mode | write-first | |
| aspect ratio | 46-word x 20-bit | |
| aspect ratio | 46-word x 16-bit | |
| clock | connected to signal <CLOCK> | rise |
| dual clock | connected to signal <CLOCK> | rise |
| dual enable | connected to signal <SET> | high |
303,15 → 302,15
| dual data out | connected to signal <RATIO> | |
| ram_style | Auto | |
-----------------------------------------------------------------------
Found 1-bit 64-to-1 multiplexer for signal <$n0003> created at line 141.
Found 1-bit 46-to-1 multiplexer for signal <$n0003> created at line 141.
Found 1-bit register for signal <CONTEXT_VALID>.
Found 2-bit register for signal <DATA_READY>.
Found 6-bit register for signal <OLD_CONTEXT>.
Found 6-bit register for signal <READ_ADDRESS>.
Found 64-bit register for signal <RESET_FLAGS>.
Found 46-bit register for signal <RESET_FLAGS>.
Summary:
inferred 1 RAM(s).
inferred 79 D-type flip-flop(s).
inferred 61 D-type flip-flop(s).
inferred 1 Multiplexer(s).
Unit <context_manager> synthesized.
 
328,9 → 327,6
Found registered multiplier on signal <_n0003>:
- 1 register level(s) found in a register connected to the multiplier macro ouput.
Pushing register(s) into the multiplier macro.
Found registered multiplier on signal <_n0004>:
- 1 register level(s) found in a register connected to the multiplier macro ouput.
Pushing register(s) into the multiplier macro.
Advanced Registered AddSub inference ...
Dynamic shift register inference ...
 
339,28 → 335,27
 
Macro Statistics
# Block RAMs : 2
1022x32-bit single-port block RAM : 1
46x20-bit dual-port block RAM : 1
# Multipliers : 2
16x10-bit registered multiplier : 2
# Adders/Subtractors : 54
10-bit adder : 6
10-bit subtractor : 1
254x16-bit single-port block RAM : 1
46x16-bit dual-port block RAM : 1
# Multipliers : 1
16x8-bit registered multiplier : 1
# Adders/Subtractors : 53
3-bit addsub : 46
42-bit adder : 1
# Registers : 125
1-bit register : 69
10-bit register : 8
8-bit adder : 6
8-bit subtractor : 1
# Registers : 107
1-bit register : 51
3-bit register : 46
6-bit register : 2
8-bit register : 8
# Comparators : 2
10-bit comparator greater : 1
3-bit comparator greater : 1
8-bit comparator greater : 1
# Multiplexers : 50
1-bit 64-to-1 multiplexer : 1
10-bit 4-to-1 multiplexer : 2
1-bit 46-to-1 multiplexer : 1
3-bit 4-to-1 multiplexer : 46
3-bit 46-to-1 multiplexer : 1
8-bit 4-to-1 multiplexer : 2
# Xors : 1
1-bit xor2 : 1
 
377,23 → 372,20
Optimizing unit <UPDATER> ...
 
Optimizing unit <DIVIDER> ...
Loading device for application Rf_Device from file '2v250.nph' in environment C:/Xilinx.
Loading device for application Rf_Device from file '2v2000.nph' in environment C:/Xilinx.
 
Mapping all equations...
Building and optimizing final netlist ...
Register <PROBUPDATE_UPDATE> equivalent to <DATA_READY_0> has been removed
Register <DIVISION_NUMERATOR2_5> equivalent to <PROBUPDATE_NUMERATOR1_5> has been removed
Register <DIVISION_NUMERATOR2_7> equivalent to <PROBUPDATE_NUMERATOR1_7> has been removed
Register <DIVISION_NUMERATOR2_9> equivalent to <PROBUPDATE_NUMERATOR1_9> has been removed
Register <DIVISION_NUMERATOR2_8> equivalent to <PROBUPDATE_NUMERATOR1_8> has been removed
Register <DIVISION_NUMERATOR2_6> equivalent to <PROBUPDATE_NUMERATOR1_6> has been removed
Register <DIVISION_NUMERATOR2_0> equivalent to <PROBUPDATE_NUMERATOR1_0> has been removed
Register <DIVISION_NUMERATOR2_1> equivalent to <PROBUPDATE_NUMERATOR1_1> has been removed
Register <DIVISION_NUMERATOR2_2> equivalent to <PROBUPDATE_NUMERATOR1_2> has been removed
Register <DIVISION_NUMERATOR2_3> equivalent to <PROBUPDATE_NUMERATOR1_3> has been removed
Register <DIVISION_NUMERATOR2_4> equivalent to <PROBUPDATE_NUMERATOR1_4> has been removed
Register <DIVISION_NUMERATOR2_5> equivalent to <PROBUPDATE_NUMERATOR1_5> has been removed
Register <DIVISION_NUMERATOR2_6> equivalent to <PROBUPDATE_NUMERATOR1_6> has been removed
Found area constraint ratio of 100 (+ 5) on block context_manager, actual ratio is 24.
FlipFlop READ_ADDRESS_0 has been replicated 3 time(s)
Found area constraint ratio of 100 (+ 5) on block context_manager, actual ratio is 3.
 
=========================================================================
* Final Report *
406,84 → 398,83
Keep Hierarchy : NO
 
Design Statistics
# IOs : 23
# IOs : 21
 
Macro Statistics :
# RAM : 2
# 1022x32-bit single-port block RAM: 1
# 46x20-bit dual-port block RAM: 1
# Registers : 197
# 1-bit register : 149
# 254x16-bit single-port block RAM: 1
# 46x16-bit dual-port block RAM: 1
# Registers : 163
# 1-bit register : 115
# 3-bit register : 46
# 6-bit register : 2
# Multiplexers : 50
# 1-bit 64-to-1 multiplexer : 1
# 10-bit 4-to-1 multiplexer : 2
# 1-bit 46-to-1 multiplexer : 1
# 3-bit 4-to-1 multiplexer : 46
# 3-bit 46-to-1 multiplexer : 1
# Adders/Subtractors : 8
# 10-bit adder : 6
# 10-bit subtractor : 1
# 42-bit adder : 1
# Multipliers : 2
# 16x10-bit registered multiplier: 2
# 8-bit 4-to-1 multiplexer : 2
# Adders/Subtractors : 7
# 8-bit adder : 6
# 8-bit subtractor : 1
# Multipliers : 1
# 16x8-bit registered multiplier: 1
# Comparators : 2
# 10-bit comparator greater : 1
# 3-bit comparator greater : 1
# 8-bit comparator greater : 1
# Xors : 92
# 1-bit xor3 : 92
 
Cell Usage :
# BELS : 960
# BELS : 799
# GND : 1
# INV : 1
# LUT1 : 20
# LUT1_L : 9
# LUT2 : 33
# LUT3 : 89
# LUT1 : 11
# LUT1_L : 7
# LUT2 : 23
# LUT3 : 87
# LUT3_D : 4
# LUT3_L : 151
# LUT4 : 319
# LUT4_D : 24
# LUT4_L : 16
# MUXCY : 77
# MUXF5 : 107
# MUXF6 : 23
# MUXF7 : 10
# MUXF8 : 5
# LUT3_L : 89
# LUT4 : 293
# LUT4_D : 12
# LUT4_L : 56
# MUXCY : 42
# MUXF5 : 102
# MUXF6 : 19
# MUXF7 : 8
# MUXF8 : 4
# VCC : 1
# XORCY : 70
# FlipFlops/Latches : 291
# XORCY : 39
# FlipFlops/Latches : 256
# FD : 6
# FDE : 9
# FDR : 48
# FDRE : 156
# FDE : 6
# FDR : 38
# FDRE : 152
# FDRSE : 1
# FDS : 5
# FDSE : 66
# RAMS : 3
# RAMB16_S18 : 2
# FDSE : 48
# RAMS : 2
# RAMB16_S36 : 1
# RAMB16_S36_S36 : 1
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 22
# IO Buffers : 20
# IBUF : 11
# OBUF : 11
# MULTs : 2
# MULT18X18S : 2
# OBUF : 9
# MULTs : 1
# MULT18X18S : 1
=========================================================================
 
Device utilization summary:
---------------------------
 
Selected Device : 2v250cs144-6
Selected Device : 2v2000bg575-6
 
Number of Slices: 359 out of 1536 23%
Number of Slice Flip Flops: 291 out of 3072 9%
Number of 4 input LUTs: 665 out of 3072 21%
Number of bonded IOBs: 23 out of 92 25%
Number of BRAMs: 3 out of 24 12%
Number of MULT18X18s: 2 out of 24 8%
Number of Slices: 316 out of 10752 2%
Number of Slice Flip Flops: 256 out of 21504 1%
Number of 4 input LUTs: 582 out of 21504 2%
Number of bonded IOBs: 21 out of 408 5%
Number of BRAMs: 2 out of 56 3%
Number of MULT18X18s: 1 out of 56 1%
Number of GCLKs: 1 out of 16 6%
 
 
499,7 → 490,7
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
CLOCK | BUFGP | 294 |
CLOCK | BUFGP | 258 |
-----------------------------------+------------------------+-------+
 
Timing Summary:
506,9 → 497,9
---------------
Speed Grade: -6
 
Minimum period: 9.680ns (Maximum Frequency: 103.303MHz)
Minimum input arrival time before clock: 10.225ns
Maximum output required time after clock: 8.362ns
Minimum period: 10.073ns (Maximum Frequency: 99.275MHz)
Minimum input arrival time before clock: 10.619ns
Maximum output required time after clock: 5.682ns
Maximum combinational path delay: No path found
 
Timing Detail:
517,103 → 508,106
 
=========================================================================
Timing constraint: Default period analysis for Clock 'CLOCK'
Clock period: 9.680ns (frequency: 103.303MHz)
Total number of paths / destination ports: 223210 / 475
Clock period: 10.073ns (frequency: 99.275MHz)
Total number of paths / destination ports: 147629 / 423
-------------------------------------------------------------------------
Delay: 9.680ns (Levels of Logic = 12)
Source: REFRESH_SHIFTS_0_1 (FF)
Destination: Mram_PROBABILITY_inst_ramb_0 (RAM)
Delay: 10.073ns (Levels of Logic = 17)
Source: REFRESH_SHIFTS_32_2 (FF)
Destination: PROBUPDATE_NUMERATOR4_7 (FF)
Source Clock: CLOCK rising
Destination Clock: CLOCK rising
 
Data Path: REFRESH_SHIFTS_0_1 to Mram_PROBABILITY_inst_ramb_0
Data Path: REFRESH_SHIFTS_32_2 to PROBUPDATE_NUMERATOR4_7
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDRE:C->Q 5 0.449 0.734 REFRESH_SHIFTS_0_1 (REFRESH_SHIFTS_0_1)
LUT3_L:I1->LO 1 0.347 0.000 REFRESH_CONTEXT<4>31 (REFRESH_MUX_BLOCK_N38)
MUXF5:I0->O 1 0.345 0.000 REFRESH_CONTEXT<1>_rn_14 (REFRESH_MUX_BLOCK_CONTEXT<1>_MUXF515)
MUXF6:I0->O 1 0.354 0.000 REFRESH_CONTEXT<0>_rn_9 (REFRESH_MUX_BLOCK_CONTEXT<0>_MUXF67)
MUXF7:I0->O 1 0.354 0.000 REFRESH_CONTEXT<2>_rn_3 (REFRESH_MUX_BLOCK_CONTEXT<2>_MUXF73)
MUXF8:I0->O 1 0.354 0.608 REFRESH_CONTEXT<3>_rn_0 (REFRESH_MUX_BLOCK_CONTEXT<3>_MUXF81)
LUT3_L:I0->LO 1 0.347 0.000 REFRESH__n0241109_F (N797)
MUXF5:I0->O 15 0.345 0.763 REFRESH__n0241109 (REFRESH__n0241)
LUT4_D:I3->O 7 0.347 0.630 REFRESH__n0145_1 (REFRESH__n01451)
LUT3:I2->O 1 0.347 0.548 REFRESH_DENOMINATOR_OUT<3>1 (FRACTION2<3>)
LUT4:I1->O 1 0.347 0.409 PROBUPDATE__n00144 (CHOICE11)
LUT4:I2->O 20 0.347 0.769 PROBUPDATE__n001417 (PROBUPDATE_HALVE_VALUES)
MUXF5:S->O 1 0.553 0.382 PROBUPDATE_DENOMINATOR_OUT<0>_DENOMINATOR_OUT<0>_rn_6111 (NEWPROB<17>)
RAMB16_S36_S36:DIA17 0.000 Mram_PROBABILITY_inst_ramb_0
FDRE:C->Q 4 0.449 0.717 REFRESH_SHIFTS_32_2 (REFRESH_SHIFTS_32_2)
LUT3_L:I1->LO 1 0.347 0.000 REFRESH_CONTEXT<1>16 (REFRESH_MUX_BLOCK_N64)
MUXF5:I0->O 1 0.345 0.000 REFRESH_CONTEXT<0>_rn_18 (REFRESH_MUX_BLOCK_CONTEXT<0>_MUXF57)
MUXF6:I0->O 1 0.354 0.548 REFRESH_CONTEXT<2>_rn_7 (REFRESH_MUX_BLOCK_CONTEXT<2>_MUXF62)
LUT4:I1->O 2 0.347 0.684 REFRESH__n024172 (CHOICE250)
LUT4_L:I1->LO 1 0.347 0.000 REFRESH__n0241109_SW11_F (N764)
MUXF5:I0->O 3 0.345 0.563 REFRESH__n0241109_SW11 (N673)
LUT4_D:I2->O 9 0.347 0.665 REFRESH__n0145_1 (REFRESH__n01451)
LUT4_L:I2->LO 1 0.347 0.000 REFRESH_NUMERATOR_OUT<2>12 (N590)
MUXCY:S->O 1 0.235 0.000 PROBUPDATE_UPDATER__n0013<1>cy (PROBUPDATE_UPDATER__n0013<1>_cyo)
MUXCY:CI->O 1 0.042 0.000 PROBUPDATE_UPDATER__n0013<2>cy (PROBUPDATE_UPDATER__n0013<2>_cyo)
MUXCY:CI->O 1 0.042 0.000 PROBUPDATE_UPDATER__n0013<3>cy (PROBUPDATE_UPDATER__n0013<3>_cyo)
MUXCY:CI->O 1 0.042 0.000 PROBUPDATE_UPDATER__n0013<4>cy (PROBUPDATE_UPDATER__n0013<4>_cyo)
MUXCY:CI->O 1 0.042 0.000 PROBUPDATE_UPDATER__n0013<5>cy (PROBUPDATE_UPDATER__n0013<5>_cyo)
XORCY:CI->O 2 0.824 0.744 PROBUPDATE_UPDATER__n0013<6>_xor (PROBUPDATE__n0013<6>)
LUT1_L:I0->LO 1 0.347 0.000 PROBUPDATE__n0013<6>_rt (PROBUPDATE__n0013<6>_rt)
MUXCY:S->O 0 0.235 0.000 PROBUPDATE_UPDATER__n0011<6>cy (PROBUPDATE_UPDATER__n0011<6>_cyo)
XORCY:CI->O 1 0.824 0.000 PROBUPDATE_UPDATER__n0011<7>_xor (PROBUPDATE__n0011<7>)
FDR:D 0.293 PROBUPDATE_NUMERATOR4_7
----------------------------------------
Total 9.680ns (4.836ns logic, 4.844ns route)
(50.0% logic, 50.0% route)
Total 10.073ns (6.154ns logic, 3.919ns route)
(61.1% logic, 38.9% route)
 
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLOCK'
Total number of paths / destination ports: 124256 / 757
Total number of paths / destination ports: 94125 / 679
-------------------------------------------------------------------------
Offset: 10.225ns (Levels of Logic = 13)
Source: CONTEXT_NUMBER<4> (PAD)
Destination: Mram_PROBABILITY_inst_ramb_0 (RAM)
Offset: 10.619ns (Levels of Logic = 18)
Source: CONTEXT_NUMBER<1> (PAD)
Destination: PROBUPDATE_NUMERATOR4_7 (FF)
Destination Clock: CLOCK rising
 
Data Path: CONTEXT_NUMBER<4> to Mram_PROBABILITY_inst_ramb_0
Data Path: CONTEXT_NUMBER<1> to PROBUPDATE_NUMERATOR4_7
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 56 0.653 1.075 CONTEXT_NUMBER_4_IBUF (CONTEXT_NUMBER_4_IBUF)
LUT3_L:I0->LO 1 0.347 0.000 REFRESH_CONTEXT<4>19 (REFRESH_MUX_BLOCK_N26)
MUXF5:I0->O 1 0.345 0.000 REFRESH_CONTEXT<1>_rn_8 (REFRESH_MUX_BLOCK_CONTEXT<1>_MUXF59)
MUXF6:I0->O 1 0.354 0.000 REFRESH_CONTEXT<0>_rn_6 (REFRESH_MUX_BLOCK_CONTEXT<0>_MUXF64)
MUXF7:I1->O 1 0.354 0.000 REFRESH_CONTEXT<2>_rn_2 (REFRESH_MUX_BLOCK_CONTEXT<2>_MUXF72)
MUXF8:I1->O 1 0.354 0.608 REFRESH_CONTEXT<3>_rn_0 (REFRESH_MUX_BLOCK_CONTEXT<3>_MUXF81)
LUT3_L:I0->LO 1 0.347 0.000 REFRESH__n0241109_F (N797)
MUXF5:I0->O 15 0.345 0.763 REFRESH__n0241109 (REFRESH__n0241)
LUT4_D:I3->O 7 0.347 0.630 REFRESH__n0145_1 (REFRESH__n01451)
LUT3:I2->O 1 0.347 0.548 REFRESH_DENOMINATOR_OUT<3>1 (FRACTION2<3>)
LUT4:I1->O 1 0.347 0.409 PROBUPDATE__n00144 (CHOICE11)
LUT4:I2->O 20 0.347 0.769 PROBUPDATE__n001417 (PROBUPDATE_HALVE_VALUES)
MUXF5:S->O 1 0.553 0.382 PROBUPDATE_DENOMINATOR_OUT<0>_DENOMINATOR_OUT<0>_rn_6111 (NEWPROB<17>)
RAMB16_S36_S36:DIA17 0.000 Mram_PROBABILITY_inst_ramb_0
IBUF:I->O 48 0.653 1.060 CONTEXT_NUMBER_1_IBUF (CONTEXT_NUMBER_1_IBUF)
LUT3_L:I0->LO 1 0.347 0.000 REFRESH_CONTEXT<1>15 (REFRESH_MUX_BLOCK_N63)
MUXF5:I1->O 1 0.345 0.000 REFRESH_CONTEXT<0>_rn_18 (REFRESH_MUX_BLOCK_CONTEXT<0>_MUXF57)
MUXF6:I0->O 1 0.354 0.548 REFRESH_CONTEXT<2>_rn_7 (REFRESH_MUX_BLOCK_CONTEXT<2>_MUXF62)
LUT4:I1->O 2 0.347 0.684 REFRESH__n024172 (CHOICE250)
LUT4_L:I1->LO 1 0.347 0.000 REFRESH__n0241109_SW11_F (N764)
MUXF5:I0->O 3 0.345 0.563 REFRESH__n0241109_SW11 (N673)
LUT4_D:I2->O 9 0.347 0.665 REFRESH__n0145_1 (REFRESH__n01451)
LUT4_L:I2->LO 1 0.347 0.000 REFRESH_NUMERATOR_OUT<2>12 (N590)
MUXCY:S->O 1 0.235 0.000 PROBUPDATE_UPDATER__n0013<1>cy (PROBUPDATE_UPDATER__n0013<1>_cyo)
MUXCY:CI->O 1 0.042 0.000 PROBUPDATE_UPDATER__n0013<2>cy (PROBUPDATE_UPDATER__n0013<2>_cyo)
MUXCY:CI->O 1 0.042 0.000 PROBUPDATE_UPDATER__n0013<3>cy (PROBUPDATE_UPDATER__n0013<3>_cyo)
MUXCY:CI->O 1 0.042 0.000 PROBUPDATE_UPDATER__n0013<4>cy (PROBUPDATE_UPDATER__n0013<4>_cyo)
MUXCY:CI->O 1 0.042 0.000 PROBUPDATE_UPDATER__n0013<5>cy (PROBUPDATE_UPDATER__n0013<5>_cyo)
XORCY:CI->O 2 0.824 0.744 PROBUPDATE_UPDATER__n0013<6>_xor (PROBUPDATE__n0013<6>)
LUT1_L:I0->LO 1 0.347 0.000 PROBUPDATE__n0013<6>_rt (PROBUPDATE__n0013<6>_rt)
MUXCY:S->O 0 0.235 0.000 PROBUPDATE_UPDATER__n0011<6>cy (PROBUPDATE_UPDATER__n0011<6>_cyo)
XORCY:CI->O 1 0.824 0.000 PROBUPDATE_UPDATER__n0011<7>_xor (PROBUPDATE__n0011<7>)
FDR:D 0.293 PROBUPDATE_NUMERATOR4_7
----------------------------------------
Total 10.225ns (5.040ns logic, 5.185ns route)
(49.3% logic, 50.7% route)
Total 10.619ns (6.358ns logic, 4.261ns route)
(59.9% logic, 40.1% route)
 
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLOCK'
Total number of paths / destination ports: 301 / 11
Total number of paths / destination ports: 10 / 9
-------------------------------------------------------------------------
Offset: 8.362ns (Levels of Logic = 9)
Source: DIVISION_Mmult__n00041_inst_mult_0 (MULT)
Destination: PROB<9> (PAD)
Offset: 5.682ns (Levels of Logic = 2)
Source: DATA_READY_0 (FF)
Destination: READY (PAD)
Source Clock: CLOCK rising
 
Data Path: DIVISION_Mmult__n00041_inst_mult_0 to PROB<9>
Data Path: DATA_READY_0 to READY
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
MULT18X18S:C->P25 1 2.073 0.548 DIVISION_Mmult__n00041_inst_mult_0 (DIVISION_PRODUCT2<25>)
LUT2:I1->O 1 0.347 0.000 DIVISION_DIVIDER_QUOTIENT<3>lut (DIVISION_N23)
MUXCY:S->O 1 0.235 0.000 DIVISION_DIVIDER_QUOTIENT<3>cy (DIVISION_DIVIDER_QUOTIENT<3>_cyo)
MUXCY:CI->O 1 0.042 0.000 DIVISION_DIVIDER_QUOTIENT<4>cy (DIVISION_DIVIDER_QUOTIENT<4>_cyo)
MUXCY:CI->O 1 0.042 0.000 DIVISION_DIVIDER_QUOTIENT<5>cy (DIVISION_DIVIDER_QUOTIENT<5>_cyo)
MUXCY:CI->O 1 0.042 0.000 DIVISION_DIVIDER_QUOTIENT<6>cy (DIVISION_DIVIDER_QUOTIENT<6>_cyo)
MUXCY:CI->O 1 0.042 0.000 DIVISION_DIVIDER_QUOTIENT<7>cy (DIVISION_DIVIDER_QUOTIENT<7>_cyo)
MUXCY:CI->O 0 0.042 0.000 DIVISION_DIVIDER_QUOTIENT<8>cy (DIVISION_DIVIDER_QUOTIENT<8>_cyo)
XORCY:CI->O 1 0.824 0.383 DIVISION_DIVIDER_QUOTIENT<9>_xor (PROB_9_OBUF)
OBUF:I->O 3.743 PROB_9_OBUF (PROB<9>)
FDR:C->Q 3 0.449 0.760 DATA_READY_0 (DATA_READY_0)
LUT2:I0->O 1 0.347 0.383 READY1 (READY_OBUF)
OBUF:I->O 3.743 READY_OBUF (READY)
----------------------------------------
Total 8.362ns (7.432ns logic, 0.930ns route)
(88.9% logic, 11.1% route)
Total 5.682ns (4.539ns logic, 1.143ns route)
(79.9% logic, 20.1% route)
 
=========================================================================
CPU : 18.47 / 18.83 s | Elapsed : 18.00 / 18.00 s
CPU : 19.81 / 20.20 s | Elapsed : 20.00 / 20.00 s
-->
 
Total memory usage is 106748 kilobytes
Total memory usage is 126268 kilobytes
 
Number of errors : 0 ( 0 filtered)
Number of warnings : 10 ( 0 filtered)
Number of warnings : 12 ( 0 filtered)
Number of infos : 3 ( 0 filtered)
 
/trunk/docs/synthesis_reports/common/halving_manager.syr
1,10 → 1,10
Release 7.1.04i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.31 s | Elapsed : 0.00 / 0.00 s
CPU : 0.00 / 0.34 s | Elapsed : 0.00 / 0.00 s
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.31 s | Elapsed : 0.00 / 0.00 s
CPU : 0.00 / 0.34 s | Elapsed : 0.00 / 0.00 s
--> Reading design: halving_manager.prj
 
32,7 → 32,7
---- Target Parameters
Output File Name : "halving_manager"
Output Format : NGC
Target Device : xc2v250-6-cs144
Target Device : xc2v2000-6-bg575
 
---- Source Options
Top Module Name : halving_manager
65,7 → 65,7
 
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Optimization Effort : 2
Keep Hierarchy : NO
Global Optimization : AllClockNets
RTL Output : Yes
95,7 → 95,7
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd" in Library work.
Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" in Library work.
Architecture rtl of Entity halving_manager is up to date.
 
=========================================================================
102,10 → 102,11
* HDL Analysis *
=========================================================================
Analyzing Entity <halving_manager> (Architecture <rtl>).
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd" line 71: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd" line 71: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd" line 73: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd" line 108: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" line 71: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" line 71: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" line 73: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:1610 - "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" line 78: Width mismatch. <NUMERATOR2> has a width of 8 bits but assigned expression is 10-bit wide.
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" line 108: Index value(s) does not match array range, simulation mismatch.
Entity <halving_manager> analyzed. Unit <halving_manager> generated.
 
 
114,7 → 115,7
=========================================================================
 
Synthesizing Unit <halving_manager>.
Related source file is "C:/Xilinx/bin/ArithmeticDecoder/HALVING_MANAGER.vhd".
Related source file is "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd".
Found 3-bit 46-to-1 multiplexer for signal <$n0002> created at line 108.
Found 3-bit 4-to-1 multiplexer for signal <$n0050>.
Found 3-bit 4-to-1 multiplexer for signal <$n0051>.
208,13 → 209,13
Found 3-bit addsub for signal <$n0142>.
Found 3-bit addsub for signal <$n0143>.
Found 3-bit addsub for signal <$n0144>.
Found 10-bit comparator greater for signal <$n0147> created at line 99.
Found 8-bit comparator greater for signal <$n0147> created at line 99.
Found 3-bit comparator greater for signal <$n0241> created at line 108.
Found 1-bit register for signal <AFTER_TRIGGER>.
Found 10-bit register for signal <DENOMINATOR>.
Found 10-bit adder for signal <DENOMINATOR2>.
Found 10-bit register for signal <NUMERATOR>.
Found 10-bit adder for signal <NUMERATOR2>.
Found 8-bit register for signal <DENOMINATOR>.
Found 8-bit adder for signal <DENOMINATOR2>.
Found 8-bit register for signal <NUMERATOR>.
Found 8-bit adder for signal <NUMERATOR2>.
Found 138-bit register for signal <SHIFTS>.
Summary:
inferred 139 D-type flip-flop(s).
239,15 → 240,15
 
Macro Statistics
# Adders/Subtractors : 48
10-bit adder : 2
3-bit addsub : 46
8-bit adder : 2
# Registers : 49
1-bit register : 1
10-bit register : 2
3-bit register : 46
8-bit register : 2
# Comparators : 2
10-bit comparator greater : 1
3-bit comparator greater : 1
8-bit comparator greater : 1
# Multiplexers : 47
3-bit 4-to-1 multiplexer : 46
3-bit 46-to-1 multiplexer : 1
259,11 → 260,11
=========================================================================
 
Optimizing unit <halving_manager> ...
Loading device for application Rf_Device from file '2v250.nph' in environment C:/Xilinx.
Loading device for application Rf_Device from file '2v2000.nph' in environment C:/Xilinx.
 
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block halving_manager, actual ratio is 16.
Found area constraint ratio of 100 (+ 5) on block halving_manager, actual ratio is 2.
 
=========================================================================
* Final Report *
276,61 → 277,62
Keep Hierarchy : NO
 
Design Statistics
# IOs : 51
# IOs : 43
 
Macro Statistics :
# Registers : 67
# 1-bit register : 21
# Registers : 63
# 1-bit register : 17
# 3-bit register : 46
# Multiplexers : 47
# 3-bit 4-to-1 multiplexer : 46
# 3-bit 46-to-1 multiplexer : 1
# Adders/Subtractors : 2
# 10-bit adder : 2
# 8-bit adder : 2
# Comparators : 2
# 10-bit comparator greater : 1
# 3-bit comparator greater : 1
# 8-bit comparator greater : 1
# Xors : 92
# 1-bit xor3 : 92
 
Cell Usage :
# BELS : 570
# BELS : 550
# GND : 1
# INV : 1
# LUT1 : 15
# LUT1 : 11
# LUT2 : 9
# LUT3 : 70
# LUT3_L : 132
# LUT4 : 118
# LUT4_D : 18
# LUT3 : 68
# LUT3_D : 1
# LUT3_L : 127
# LUT4 : 117
# LUT4_D : 17
# LUT4_L : 112
# MUXCY : 18
# MUXCY : 14
# MUXF5 : 35
# MUXF6 : 15
# MUXF7 : 6
# MUXF8 : 3
# VCC : 1
# XORCY : 16
# FlipFlops/Latches : 159
# XORCY : 12
# FlipFlops/Latches : 155
# FDR : 1
# FDRE : 156
# FDRE : 152
# FDSE : 2
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 50
# IBUF : 29
# OBUF : 21
# IO Buffers : 42
# IBUF : 25
# OBUF : 17
=========================================================================
 
Device utilization summary:
---------------------------
 
Selected Device : 2v250cs144-6
Selected Device : 2v2000bg575-6
 
Number of Slices: 263 out of 1536 17%
Number of Slice Flip Flops: 159 out of 3072 5%
Number of 4 input LUTs: 474 out of 3072 15%
Number of bonded IOBs: 51 out of 92 55%
Number of Slices: 256 out of 10752 2%
Number of Slice Flip Flops: 155 out of 21504 0%
Number of 4 input LUTs: 462 out of 21504 2%
Number of bonded IOBs: 43 out of 408 10%
Number of GCLKs: 1 out of 16 6%
 
 
346,7 → 348,7
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
CLOCK | BUFGP | 159 |
CLOCK | BUFGP | 155 |
-----------------------------------+------------------------+-------+
 
Timing Summary:
355,8 → 357,8
 
Minimum period: 6.759ns (Maximum Frequency: 147.951MHz)
Minimum input arrival time before clock: 7.315ns
Maximum output required time after clock: 11.278ns
Maximum combinational path delay: 11.850ns
Maximum output required time after clock: 11.248ns
Maximum combinational path delay: 11.821ns
 
Timing Detail:
--------------
365,15 → 367,15
=========================================================================
Timing constraint: Default period analysis for Clock 'CLOCK'
Clock period: 6.759ns (frequency: 147.951MHz)
Total number of paths / destination ports: 44219 / 316
Total number of paths / destination ports: 42357 / 308
-------------------------------------------------------------------------
Delay: 6.759ns (Levels of Logic = 8)
Source: SHIFTS_0_1 (FF)
Destination: SHIFTS_8_2 (FF)
Destination: SHIFTS_0_2 (FF)
Source Clock: CLOCK rising
Destination Clock: CLOCK rising
 
Data Path: SHIFTS_0_1 to SHIFTS_8_2
Data Path: SHIFTS_0_1 to SHIFTS_0_2
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
382,11 → 384,11
MUXF5:I0->O 1 0.345 0.000 CONTEXT<1>_rn_14 (MUX_BLOCK_CONTEXT<1>_MUXF515)
MUXF6:I0->O 1 0.354 0.000 CONTEXT<0>_rn_9 (MUX_BLOCK_CONTEXT<0>_MUXF67)
MUXF7:I0->O 2 0.354 0.743 CONTEXT<2>_rn_3 (MUX_BLOCK_CONTEXT<2>_MUXF73)
LUT4_L:I0->LO 1 0.347 0.000 _n0241106_1_F (N760)
LUT4_L:I0->LO 1 0.347 0.000 _n0241106_1_F (N744)
MUXF5:I0->O 4 0.345 0.579 _n0241106_1 (_n0241106)
LUT4_D:I2->O 15 0.347 0.758 Ker601 (N60)
LUT4:I2->O 3 0.347 0.535 _n0484 (_n0484)
FDRE:CE 0.190 SHIFTS_20_0
LUT4:I2->O 3 0.347 0.535 _n0486 (_n0486)
FDRE:CE 0.190 SHIFTS_16_0
----------------------------------------
Total 6.759ns (3.425ns logic, 3.334ns route)
(50.7% logic, 49.3% route)
393,27 → 395,27
 
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLOCK'
Total number of paths / destination ports: 39794 / 476
Total number of paths / destination ports: 38734 / 464
-------------------------------------------------------------------------
Offset: 7.315ns (Levels of Logic = 9)
Source: CONTEXT<4> (PAD)
Destination: SHIFTS_8_2 (FF)
Destination: SHIFTS_0_2 (FF)
Destination Clock: CLOCK rising
 
Data Path: CONTEXT<4> to SHIFTS_8_2
Data Path: CONTEXT<4> to SHIFTS_0_2
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 53 0.653 1.069 CONTEXT_4_IBUF (CONTEXT_4_IBUF)
LUT3_L:I0->LO 1 0.347 0.000 CONTEXT<4>19 (MUX_BLOCK_N26)
MUXF5:I0->O 1 0.345 0.000 CONTEXT<1>_rn_8 (MUX_BLOCK_CONTEXT<1>_MUXF59)
MUXF6:I0->O 1 0.354 0.000 CONTEXT<0>_rn_6 (MUX_BLOCK_CONTEXT<0>_MUXF64)
MUXF7:I1->O 2 0.354 0.743 CONTEXT<2>_rn_2 (MUX_BLOCK_CONTEXT<2>_MUXF72)
LUT4_L:I0->LO 1 0.347 0.000 _n0241106_1_G (N761)
MUXF5:I1->O 4 0.345 0.579 _n0241106_1 (_n0241106)
LUT3_L:I0->LO 1 0.347 0.000 CONTEXT<4>25 (MUX_BLOCK_N32)
MUXF5:I0->O 1 0.345 0.000 CONTEXT<1>_rn_11 (MUX_BLOCK_CONTEXT<1>_MUXF512)
MUXF6:I1->O 1 0.354 0.000 CONTEXT<0>_rn_8 (MUX_BLOCK_CONTEXT<0>_MUXF66)
MUXF7:I1->O 2 0.354 0.743 CONTEXT<2>_rn_3 (MUX_BLOCK_CONTEXT<2>_MUXF73)
LUT4_L:I0->LO 1 0.347 0.000 _n0241106_1_F (N744)
MUXF5:I0->O 4 0.345 0.579 _n0241106_1 (_n0241106)
LUT4_D:I2->O 15 0.347 0.758 Ker601 (N60)
LUT4:I2->O 3 0.347 0.535 _n0484 (_n0484)
FDRE:CE 0.190 SHIFTS_20_0
LUT4:I2->O 3 0.347 0.535 _n0486 (_n0486)
FDRE:CE 0.190 SHIFTS_16_0
----------------------------------------
Total 7.315ns (3.629ns logic, 3.686ns route)
(49.6% logic, 50.4% route)
420,67 → 422,67
 
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLOCK'
Total number of paths / destination ports: 3148 / 21
Total number of paths / destination ports: 2514 / 17
-------------------------------------------------------------------------
Offset: 11.278ns (Levels of Logic = 10)
Offset: 11.248ns (Levels of Logic = 10)
Source: SHIFTS_0_2 (FF)
Destination: DENOMINATOR_OUT<9> (PAD)
Destination: DENOMINATOR_OUT<7> (PAD)
Source Clock: CLOCK rising
 
Data Path: SHIFTS_0_2 to DENOMINATOR_OUT<9>
Data Path: SHIFTS_0_2 to DENOMINATOR_OUT<7>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDRE:C->Q 3 0.449 0.700 SHIFTS_0_2 (SHIFTS_0_2)
FDRE:C->Q 3 0.449 0.701 SHIFTS_0_2 (SHIFTS_0_2)
LUT3_L:I1->LO 1 0.347 0.000 CONTEXT<4>47 (MUX_BLOCK_N60)
MUXF5:I0->O 1 0.345 0.000 CONTEXT<1>_rn_22 (MUX_BLOCK_CONTEXT<1>_MUXF523)
MUXF6:I0->O 1 0.354 0.000 CONTEXT<0>_rn_16 (MUX_BLOCK_CONTEXT<0>_MUXF611)
MUXF7:I0->O 2 0.354 0.000 CONTEXT<2>_rn_6 (MUX_BLOCK_CONTEXT<2>_MUXF75)
MUXF8:I0->O 1 0.354 0.547 CONTEXT<3>_rn_1 (MUX_BLOCK_CONTEXT<3>_MUXF82)
LUT4:I1->O 16 0.347 0.905 _n0241106 (CHOICE33)
LUT4:I1->O 1 0.347 0.415 _n0145_SW1 (N718)
LUT4:I3->O 20 0.347 0.994 _n0145 (_n0145)
LUT4:I1->O 16 0.347 0.905 _n0241106 (CHOICE31)
LUT4:I1->O 1 0.347 0.415 _n0145_SW1 (N702)
LUT4:I3->O 16 0.347 0.964 _n0145 (_n0145)
LUT3:I0->O 1 0.347 0.383 NUMERATOR_OUT<0>1 (NUMERATOR_OUT_0_OBUF)
OBUF:I->O 3.743 NUMERATOR_OUT_0_OBUF (NUMERATOR_OUT<0>)
----------------------------------------
Total 11.278ns (7.334ns logic, 3.944ns route)
(65.0% logic, 35.0% route)
Total 11.248ns (7.334ns logic, 3.914ns route)
(65.2% logic, 34.8% route)
 
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 2813 / 21
Total number of paths / destination ports: 2277 / 17
-------------------------------------------------------------------------
Delay: 11.850ns (Levels of Logic = 11)
Delay: 11.821ns (Levels of Logic = 11)
Source: CONTEXT<4> (PAD)
Destination: DENOMINATOR_OUT<9> (PAD)
Destination: DENOMINATOR_OUT<7> (PAD)
 
Data Path: CONTEXT<4> to DENOMINATOR_OUT<9>
Data Path: CONTEXT<4> to DENOMINATOR_OUT<7>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 53 0.653 1.069 CONTEXT_4_IBUF (CONTEXT_4_IBUF)
LUT3_L:I0->LO 1 0.347 0.000 CONTEXT<4>35 (MUX_BLOCK_N48)
MUXF5:I0->O 1 0.345 0.000 CONTEXT<1>_rn_16 (MUX_BLOCK_CONTEXT<1>_MUXF517)
MUXF6:I0->O 1 0.354 0.000 CONTEXT<0>_rn_13 (MUX_BLOCK_CONTEXT<0>_MUXF68)
MUXF7:I1->O 2 0.354 0.000 CONTEXT<2>_rn_5 (MUX_BLOCK_CONTEXT<2>_MUXF74)
MUXF8:I1->O 1 0.354 0.547 CONTEXT<3>_rn_1 (MUX_BLOCK_CONTEXT<3>_MUXF82)
LUT4:I1->O 16 0.347 0.905 _n0241106 (CHOICE33)
LUT4:I1->O 1 0.347 0.415 _n0145_SW1 (N718)
LUT4:I3->O 20 0.347 0.994 _n0145 (_n0145)
LUT3_L:I0->LO 1 0.347 0.000 CONTEXT<4>41 (MUX_BLOCK_N54)
MUXF5:I0->O 1 0.345 0.000 CONTEXT<1>_rn_19 (MUX_BLOCK_CONTEXT<1>_MUXF520)
MUXF6:I1->O 1 0.354 0.000 CONTEXT<0>_rn_15 (MUX_BLOCK_CONTEXT<0>_MUXF610)
MUXF7:I1->O 2 0.354 0.000 CONTEXT<2>_rn_6 (MUX_BLOCK_CONTEXT<2>_MUXF75)
MUXF8:I0->O 1 0.354 0.547 CONTEXT<3>_rn_1 (MUX_BLOCK_CONTEXT<3>_MUXF82)
LUT4:I1->O 16 0.347 0.905 _n0241106 (CHOICE31)
LUT4:I1->O 1 0.347 0.415 _n0145_SW1 (N702)
LUT4:I3->O 16 0.347 0.964 _n0145 (_n0145)
LUT3:I0->O 1 0.347 0.383 NUMERATOR_OUT<0>1 (NUMERATOR_OUT_0_OBUF)
OBUF:I->O 3.743 NUMERATOR_OUT_0_OBUF (NUMERATOR_OUT<0>)
----------------------------------------
Total 11.850ns (7.538ns logic, 4.312ns route)
(63.6% logic, 36.4% route)
Total 11.821ns (7.538ns logic, 4.283ns route)
(63.8% logic, 36.2% route)
 
=========================================================================
CPU : 13.28 / 13.63 s | Elapsed : 14.00 / 14.00 s
CPU : 15.17 / 15.55 s | Elapsed : 15.00 / 15.00 s
-->
 
Total memory usage is 103676 kilobytes
Total memory usage is 124220 kilobytes
 
Number of errors : 0 ( 0 filtered)
Number of warnings : 4 ( 0 filtered)
Number of warnings : 5 ( 0 filtered)
Number of infos : 1 ( 0 filtered)
 

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