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URL https://opencores.org/ocsvn/hpc-16/hpc-16/trunk

Subversion Repositories hpc-16

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  • This comparison shows the changes necessary to convert path 
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    from Rev 9 to Rev 10
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Rev 9 → Rev 10

/trunk/impl0/rtl/vhdl/con1.vhd
106,6 → 106,7
signal asopsel : std_logic_vector(3 downto 0);
 
signal rsync_stage0 : std_logic;
signal rsync_stage1 : std_logic;
 
signal isync_stage0 : std_logic;
signal isync_stage1 : std_logic;
112,8 → 113,7
signal isync_stage2 : std_logic;
signal isync : std_logic;
signal intr_sync_rst : std_logic;
signal isync_status : std_logic_vector(1 downto 0);
begin
process(CLK_I)
120,7 → 120,8
begin
if rising_edge(CLK_I) then
rsync_stage0 <= RST_I;
rst_sync <= rsync_stage0;
rsync_stage1 <= rsync_stage0;
rst_sync <= rsync_stage1;
end if;
end process;
 
148,21 → 149,19
isync <= isync_stage0 and isync_stage1 and not isync_stage2;
isync_status <= intr_sync_rst & isync;
process(CLK_I, rst_sync)
begin
if rst_sync = '1' then
intr_sync <= '0';
elsif rising_edge(CLK_I) then
case isync_status is
when "10" | "00"=> intr_sync <= '0';
when "11" | "01"=> intr_sync <= '1';
when others => intr_sync <= '0';
end case;
end if;
end process;
elsif rising_edge(CLK_I) then
if intr_sync_rst = '1' then
intr_sync <= '0';
elsif isync = '1' then
intr_sync <= '1';
end if;
end if;
end process;
process(CLK_I, rst_sync)
begin
if rst_sync = '1' then
/trunk/impl0/rtl/vhdl/nontri/con1.vhd
110,6 → 110,7
signal asopsel : std_logic_vector(3 downto 0);
signal rsync_stage0 : std_logic;
signal rsync_stage1 : std_logic;
 
signal isync_stage0 : std_logic;
signal isync_stage1 : std_logic;
116,14 → 117,14
signal isync_stage2 : std_logic;
signal isync : std_logic;
signal intr_sync_rst : std_logic;
signal isync_status : std_logic_vector(1 downto 0);
begin
process(CLK_I)
begin
if rising_edge(CLK_I) then
rsync_stage0 <= RST_I;
rst_sync <= rsync_stage0;
rsync_stage1 <= rsync_stage0;
rst_sync <= rsync_stage1;
end if;
end process;
 
151,20 → 152,18
isync <= isync_stage0 and isync_stage1 and not isync_stage2;
isync_status <= intr_sync_rst & isync;
process(CLK_I, rst_sync)
begin
if rst_sync = '1' then
intr_sync <= '0';
elsif rising_edge(CLK_I) then
case isync_status is
when "10" | "00"=> intr_sync <= '0';
when "11" | "01"=> intr_sync <= '1';
when others => intr_sync <= '0';
end case;
end if;
end process;
elsif rising_edge(CLK_I) then
if intr_sync_rst = '1' then
intr_sync <= '0';
elsif isync = '1' then
intr_sync <= '1';
end if;
end if;
end process;
 
process(CLK_I, rst_sync)
begin

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