Subversion Repositories lwrisc

/trunk/QU2/db/ClaiRISC_core.(3).cnf.cdb

/trunk/QU2/db/ClaiRISC_core.(5).cnf.cdb

/trunk/QU2/db/ClaiRISC_core.(1).cnf.hdb +­–’Y·\Sˉ!€Í–“xפ³Ñ½iˆf°L“žæܦ�yòÍS +¯¿M&¯‘ðÚð2à¼Ü�½›v/ñÖýûøyðð/¡Ñ1‘sÔ#|ÏÓ{iÄÖˆEÖó}Ü¿C»5š¬¼tŠk \ No newline at end of file

/trunk/QU2/db/ClaiRISC_core.(7).cnf.cdb

/trunk/QU2/db/ClaiRISC_core.rtlv.hdb +€=Âø-kJ¤=�_>uêdèÀ6h�Úà^ß,hÁª„Yk™…;É,üšE"�¡Ãk§¿

/trunk/QU2/db/ClaiRISC_core.(3).cnf.hdb

/trunk/QU2/db/ClaiRISC_core.(9).cnf.cdb +t“ÎÌo’™Lg3¹þ«®Õu}MñúãúÀòt‹D$Î-Þ"è?º±ŸAá´gaø©ÌŠD \ No newline at end of file

/trunk/QU2/db/ClaiRISC_core_cmp.qrpt --- trunk/QU2/db/ClaiRISC_core.asm.qmsg (nonexistent) +++ trunk/QU2/db/ClaiRISC_core.asm.qmsg (revision 10) @@ -0,0 +1,4 @@ +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" { } { } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 10 16:27:15 2008 " "Info: Processing started: Mon Mar 10 16:27:15 2008" { } { } 0} } { } 4} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --import_settings_files=off --export_settings_files=off ClaiRISC -c ClaiRISC_core " "Info: Command: quartus_asm --import_settings_files=off --export_settings_files=off ClaiRISC -c ClaiRISC_core" { } { } 0} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 10 16:27:19 2008 " "Info: Processing ended: Mon Mar 10 16:27:19 2008" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" { } { } 0} } { } 0}

/trunk/QU2/db/ClaiRISC_core.(5).cnf.hdb +åÁ�)K®Ø¼®–EŠÏO×îe�=þÿÿx
ºÆÌl@,ÄÁî~ñ>þÎŽ!žþ@†gpÈ[!­Èk`%L@i¨’× ` ¤«_H|pH�§Ÿ{<�xÞàå°b $ó|]ƒƒÝ]!J”÷Š_ºV¢T" +5Ï=È?4 >$2ªJEû£Îy°*N  +vG8,ØÙÃÕ×±¢'þ-PŠ�
d?ƒyº�âéæé \ No newline at end of file

/trunk/QU2/db/ClaiRISC_core.cmp0.ddb +=üh‚Þ`Ã<&íU“¼ä£w~‹1|�e¯;�Ar˜a>ø'ØZ, \ No newline at end of file

/trunk/QU2/db/altsyncram_u8r.tdf

/trunk/QU2/db/ClaiRISC_core.fit.qmsg

/trunk/QU2/db/ClaiRISC_core.(7).cnf.hdb +Rz»ˆ¯4¿H|¹9EtÃœ":dN]SGMå_à°”¹Žý…)S¦ÜoŒÕ¡eµ¼ãA7ðAHÜ”P5ä*î\ªDs{à \ No newline at end of file

/trunk/QU2/db/ClaiRISC_core.tan.qmsg

/trunk/QU2/db/ClaiRISC_core.sgdiff.cdb

/trunk/QU2/db/ClaiRISC_core.(9).cnf.hdb

/trunk/QU2/db/ClaiRISC_core.syn_hier_info --- trunk/QU2/db/ClaiRISC_core.(10).cnf.cdb (nonexistent) +++ trunk/QU2/db/ClaiRISC_core.(10).cnf.cdb (revision 10) @@ -0,0 +1 @@ +­
PP1Version 4.2 Build 157 12/07/2004 SJ Full Versionz$ja
Fx
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4¡Óå%$ $€D•¥ \ No newline at end of file

/trunk/QU2/db/ClaiRISC_core.eco.cdb

/trunk/QU2/db/ClaiRISC_core.sgdiff.hdb +ʈBH¢Å8JøNß TÇN£pËiÜÙv \ No newline at end of file

/trunk/QU2/db/ClaiRISC_core.db_info

/trunk/QU2/db/ClaiRISC_core.rtlv_sg_swap.cdb +{ü;¢�Zj󩜲¾´ï´}ă=¿Ô÷´ýŸdè/ç{—?ŽÇK쟊u‚^�ÿ=µQã +ò/æïQÆ·×ïì.ìõ{÷è®ú½]ð軩QÃ@Oäùƒw™Y¦œ•~ë„ïKž¥Ïdyafþáü¶êoÝSw·w¶b ¼™ \ No newline at end of file

/trunk/QU2/db/ClaiRISC_core.psp --- trunk/QU2/db/ClaiRISC_core.hier_info (nonexistent) +++ trunk/QU2/db/ClaiRISC_core.hier_info (revision 10) @@ -0,0 +1,827 @@ +|ClaiRISC_core +clk => clk_in.PADIO +rst => rst_in.PADIO +wb_din[0] => ~NO_FANOUT~ +wb_din[1] => ~NO_FANOUT~ +wb_din[2] => ~NO_FANOUT~ +wb_din[3] => ~NO_FANOUT~ +wb_din[4] => ~NO_FANOUT~ +wb_din[5] => ~NO_FANOUT~ +wb_din[6] => ~NO_FANOUT~ +wb_din[7] => ~NO_FANOUT~ +in0[0] => in0_in_0_.PADIO +in0[1] => in0_in_1_.PADIO +in0[2] => in0_in_2_.PADIO +in0[3] => in0_in_3_.PADIO +in0[4] => in0_in_4_.PADIO +in0[5] => in0_in_5_.PADIO +in0[6] => in0_in_6_.PADIO +in0[7] => in0_in_7_.PADIO +in1[0] => in1_in_0_.PADIO +in1[1] => in1_in_1_.PADIO +in1[2] => in1_in_2_.PADIO +in1[3] => in1_in_3_.PADIO +in1[4] => in1_in_4_.PADIO +in1[5] => in1_in_5_.PADIO +in1[6] => in1_in_6_.PADIO +in1[7] => in1_in_7_.PADIO +out0[0] <= out0_out_0_.PADIO +out0[1] <= out0_out_1_.PADIO +out0[2] <= out0_out_2_.PADIO +out0[3] <= out0_out_3_.PADIO +out0[4] <= out0_out_4_.PADIO +out0[5] <= out0_out_5_.PADIO +out0[6] <= out0_out_6_.PADIO +out0[7] <= out0_out_7_.PADIO +out1[0] <= out1_out_0_.PADIO +out1[1] <= out1_out_1_.PADIO +out1[2] <= out1_out_2_.PADIO +out1[3] <= out1_out_3_.PADIO +out1[4] <= out1_out_4_.PADIO +out1[5] <= out1_out_5_.PADIO +out1[6] <= out1_out_6_.PADIO +out1[7] <= out1_out_7_.PADIO + + +|ClaiRISC_core|wb_mem_man:mem_man +w_ins_0 => ram128x8:i_reg_file.w_ins_0 +w_ins_1 => ram128x8:i_reg_file.w_ins_1 +w_ins_2 => ram128x8:i_reg_file.w_ins_2 +w_ins_3 => ram128x8:i_reg_file.w_ins_3 +w_ins_4 => ram128x8:i_reg_file.w_ins_4 +out0_0 <= out0_0__Z.REGOUT +out0_1 <= out0_1__Z.REGOUT +out0_2 <= out0_2__Z.REGOUT +out0_3 <= out0_3__Z.REGOUT +out0_4 <= out0_4__Z.REGOUT +out0_5 <= out0_5__Z.REGOUT +out0_6 <= out0_6__Z.REGOUT +out0_7 <= out0_7__Z.REGOUT +out1_0 <= out1_0__Z.REGOUT +out1_1 <= out1_1__Z.REGOUT +out1_2 <= out1_2__Z.REGOUT +out1_3 <= out1_3__Z.REGOUT +out1_4 <= out1_4__Z.REGOUT +out1_5 <= out1_5__Z.REGOUT +out1_6 <= out1_6__Z.REGOUT +out1_7 <= out1_7__Z.REGOUT +w_alu_res_1_1_0 => status_3__Z.DATAD +w_alu_res_1_1_0 => ram128x8:i_reg_file.w_alu_res_1_1_0 +w_alu_res_1_3_0 => status_4__Z.DATAD +w_alu_res_1_3_0 => ram128x8:i_reg_file.w_alu_res_1_3_0 +w_alu_res_1_6_0 => status_5__Z.DATAD +w_alu_res_1_6_0 => ram128x8:i_reg_file.w_alu_res_1_6_0 +w_alu_res_1_6_1 => status_6__Z.DATAD +w_alu_res_1_6_1 => ram128x8:i_reg_file.w_alu_res_1_6_1 +w_alu_res_1_6_2 => status_7__Z.DATAD +w_alu_res_1_6_2 => ram128x8:i_reg_file.w_alu_res_1_6_2 +in0_c_0 => reg_in0_0__Z.DATAD +in0_c_1 => reg_in0_1__Z.DATAD +in0_c_2 => reg_in0_2__Z.DATAD +in0_c_3 => reg_in0_3__Z.DATAD +in0_c_4 => reg_in0_4__Z.DATAD +in0_c_5 => reg_in0_5__Z.DATAD +in0_c_6 => reg_in0_6__Z.DATAD +in0_c_7 => reg_in0_7__Z.DATAD +w_alu_res_1_0_1 => status_1__Z.DATAD +w_alu_res_1_0_1 => ram128x8:i_reg_file.w_alu_res_1_0_1 +w_alu_res_1_0_2 => status_2__Z.DATAC +w_alu_res_1_0_2 => ram128x8:i_reg_file.w_alu_res_1_0_2 +w_alu_res_1_0_0 <= din_r_0__Z.COMBOUT +w_alu_res_1_0_a2_1_0 => din_r_0__Z.DATAD +w_alu_res_1_0_a2_1_0 => out1_0__Z.DATAC +w_alu_res_1_0_a2_1_0 => out0_0__Z.DATAC +w_alu_res_1_0_a2_1_0 => fsr_0__Z.DATAC +w_alu_res_1_0_a2_1_1 => din_r_1__Z.DATAC +w_alu_res_1_0_a2_1_1 => out1_1__Z.DATAC +w_alu_res_1_0_a2_1_1 => out0_1__Z.DATAC +w_alu_res_1_0_a2_1_1 => fsr_1__Z.DATAC +dout_4 <= dout_4_.COMBOUT +dout_7 <= dout_7_.COMBOUT +dout_5 <= dout_5_.COMBOUT +dout_3 <= dout_3_.COMBOUT +dout_2 <= dout_2_.COMBOUT +dout_6 <= dout_6_.COMBOUT +dout_0 <= dout_0_.COMBOUT +dout_1 <= dout_1_.COMBOUT +w_alu_res_1_0_a2_2_0_0 => din_r_0__Z.DATAA +w_alu_res_1_0_a2_2_0_0 => out1_0__Z.DATAA +w_alu_res_1_0_a2_2_0_0 => out0_0__Z.DATAA +w_alu_res_1_0_a2_2_0_0 => fsr_0__Z.DATAA +w_alu_res_1_0_a2_2_0_1 => din_r_1__Z.DATAA +w_alu_res_1_0_a2_2_0_1 => out1_1__Z.DATAA +w_alu_res_1_0_a2_2_0_1 => out0_1__Z.DATAA +w_alu_res_1_0_a2_2_0_1 => fsr_1__Z.DATAA +w_alu_res_1_0_0_0 => din_r_2__Z.DATAD +w_alu_res_1_0_0_0 => out1_2__Z.DATAD +w_alu_res_1_0_0_0 => out0_2__Z.DATAD +w_alu_res_1_0_0_0 => fsr_2__Z.DATAD +w_alu_res_1_0_a2_0_0 => din_r_0__Z.DATAC +w_alu_res_1_0_a2_0_0 => out1_0__Z.DATAD +w_alu_res_1_0_a2_0_0 => out0_0__Z.DATAD +w_alu_res_1_0_a2_0_0 => fsr_0__Z.DATAD +w_alu_res_1_0_a2_0_1 => din_r_1__Z.DATAD +w_alu_res_1_0_a2_0_1 => out1_1__Z.DATAD +w_alu_res_1_0_a2_0_1 => out0_1__Z.DATAD +w_alu_res_1_0_a2_0_1 => fsr_1__Z.DATAD +w_alu_res_1_0_a2_0_2 => din_r_2__Z.DATAC +w_alu_res_1_0_a2_0_2 => out1_2__Z.DATAC +w_alu_res_1_0_a2_0_2 => out0_2__Z.DATAC +w_alu_res_1_0_a2_0_2 => fsr_2__Z.DATAC +w_alu_res_1_1_a_0 => din_r_3__Z.DATAD +w_alu_res_1_1_a_0 => out1_3__Z.DATAD +w_alu_res_1_1_a_0 => out0_3__Z.DATAD +w_alu_res_1_1_a_0 => fsr_3__Z.DATAD +w_alu_res_1_1_1_0 => din_r_3__Z.DATAC +w_alu_res_1_1_1_0 => out1_3__Z.DATAC +w_alu_res_1_1_1_0 => out0_3__Z.DATAC +w_alu_res_1_1_1_0 => fsr_3__Z.DATAC +w_alu_res_1_3_a_0 => din_r_4__Z.DATAD +w_alu_res_1_3_a_0 => out1_4__Z.DATAD +w_alu_res_1_3_a_0 => out0_4__Z.DATAD +w_alu_res_1_3_a_0 => fsr_4__Z.DATAD +w_alu_res_1_3_1_0 => din_r_4__Z.DATAC +w_alu_res_1_3_1_0 => out1_4__Z.DATAC +w_alu_res_1_3_1_0 => out0_4__Z.DATAC +w_alu_res_1_3_1_0 => fsr_4__Z.DATAC +w_alu_res_1_6_a_2 => out1_7__Z.DATAD +w_alu_res_1_6_a_2 => out0_7__Z.DATAD +w_alu_res_1_6_a_2 => fsr_7__Z.DATAD +w_alu_res_1_6_a_0 => din_r_5__Z.DATAD +w_alu_res_1_6_a_0 => out1_5__Z.DATAD +w_alu_res_1_6_a_0 => out0_5__Z.DATAD +w_alu_res_1_6_a_0 => fsr_5__Z.DATAD +w_alu_res_1_6_a_1 => din_r_6__Z.DATAD +w_alu_res_1_6_a_1 => out1_6__Z.DATAD +w_alu_res_1_6_a_1 => out0_6__Z.DATAD +w_alu_res_1_6_a_1 => fsr_6__Z.DATAD +w_alu_res_1_6_1_2 => out1_7__Z.DATAC +w_alu_res_1_6_1_2 => out0_7__Z.DATAC +w_alu_res_1_6_1_2 => fsr_7__Z.DATAC +w_alu_res_1_6_1_0 => din_r_5__Z.DATAC +w_alu_res_1_6_1_0 => out1_5__Z.DATAC +w_alu_res_1_6_1_0 => out0_5__Z.DATAC +w_alu_res_1_6_1_0 => fsr_5__Z.DATAC +w_alu_res_1_6_1_1 => din_r_6__Z.DATAC +w_alu_res_1_6_1_1 => out1_6__Z.DATAC +w_alu_res_1_6_1_1 => out0_6__Z.DATAC +w_alu_res_1_6_1_1 => fsr_6__Z.DATAC +in1_c_7 => reg_in1_7__Z.DATAC +in1_c_6 => reg_in1_6__Z.DATAC +in1_c_5 => reg_in1_5__Z.DATAC +in1_c_4 => reg_in1_4__Z.DATAC +in1_c_3 => reg_in1_3__Z.DATAC +in1_c_2 => reg_in1_2__Z.DATAC +in1_c_1 => reg_in1_1__Z.DATAC +in1_c_0 => reg_in1_0__Z.DATAC +w_ek_r_4 => wr_addr_r_3__Z.DATAD +w_ek_r_4 => wr_addr_r_4__Z.DATAD +w_ek_r_4 => dout_sn_m5_e_0_a2_a_cZ.DATAB +w_ek_r_4 => dout10_cZ.DATAA +w_ek_r_4 => dout8_cZ.DATAA +w_ek_r_4 => dout_sn_m6_0_a2_cZ.DATAA +w_ek_r_4 => write_out0_0_a3_0_o2_cZ.DATAC +w_ek_r_4 => ram128x8:i_reg_file.w_ek_r_4 +w_ek_r_3 => wr_addr_r_3__Z.DATAC +w_ek_r_3 => wr_addr_r_3__Z.DATAB +w_ek_r_3 => dout_sn_m5_e_0_a2_cZ.DATAA +w_ek_r_3 => write_out0_0_a3_0_o2_cZ.DATAB +w_ek_r_3 => dout7_1_cZ.DATAA +w_ek_r_3 => dout10_2_cZ.DATAC +w_ek_r_3 => ram128x8:i_reg_file.w_ek_r_3 +w_ek_r_2 => wr_addr_r_2__Z.DATAC +w_ek_r_2 => wr_addr_r_2__Z.DATAA +w_ek_r_2 => status_0_0_0_a2_1_6_.DATAB +w_ek_r_2 => status_0_0_0_a2_2_6_.DATAB +w_ek_r_2 => dout_sn_m5_e_0_a2_cZ.DATAB +w_ek_r_2 => dout7_1_cZ.DATAC +w_ek_r_2 => dout10_2_cZ.DATAD +w_ek_r_2 => ram128x8:i_reg_file.w_ek_r_2 +w_ek_r_1 => wr_addr_r_1__Z.DATAC +w_ek_r_1 => wr_addr_r_1__Z.DATAA +w_ek_r_1 => dout_sn_m5_e_0_a2_a_cZ.DATAC +w_ek_r_1 => dout10_cZ.DATAB +w_ek_r_1 => dout8_cZ.DATAB +w_ek_r_1 => write_out0_0_a3_0_o2_cZ.DATAD +w_ek_r_1 => dout7_1_cZ.DATAB +w_ek_r_1 => ram128x8:i_reg_file.w_ek_r_1 +w_ek_r_0 => wr_en_r_Z.DATAB +w_ek_r_0 => wr_addr_r_0__Z.DATAD +w_ek_r_0 => status_0_0_0_a2_1_6_.DATAC +w_ek_r_0 => status_0_0_0_a2_2_6_.DATAC +w_ek_r_0 => dout_sn_m5_e_0_a2_a_cZ.DATAD +w_ek_r_0 => dout10_cZ.DATAC +w_ek_r_0 => dout8_cZ.DATAC +w_ek_r_0 => dout7_1_cZ.DATAD +w_ek_r_0 => ram128x8:i_reg_file.w_ek_r_0 +write_out0_0_a3_0_o2 <= write_out0_0_a3_0_o2_cZ.COMBOUT +rst_c => status_0_0_0_a2_1_6_.DATAA +rst_c => status_0_0_0_a2_2_6_.DATAA +un11_w_alu_res_carry_7 => status_6_a_0_.DATAD +w_c_2mem_i_a2_0_0 => status_6_a_0_.DATAB +N_796 => status_6_0_.DATAD +w_c_wr_r => status_6_0_.DATAB +w_z_0_a2 => status_0_i_0_a_2_.DATAD +w_z_wr_r => status_0_i_0_a_2_.DATAC +G_287 => fsr_7__Z.ENA +G_287 => fsr_6__Z.ENA +G_287 => fsr_5__Z.ENA +G_287 => fsr_4__Z.ENA +G_287 => fsr_3__Z.ENA +G_287 => fsr_2__Z.ENA +G_287 => fsr_1__Z.ENA +G_287 => fsr_0__Z.ENA +G_279 => out0_7__Z.ENA +G_279 => out0_6__Z.ENA +G_279 => out0_5__Z.ENA +G_279 => out0_4__Z.ENA +G_279 => out0_3__Z.ENA +G_279 => out0_2__Z.ENA +G_279 => out0_1__Z.ENA +G_279 => out0_0__Z.ENA +G_271 => out1_7__Z.ENA +G_271 => out1_6__Z.ENA +G_271 => out1_5__Z.ENA +G_271 => out1_4__Z.ENA +G_271 => out1_3__Z.ENA +G_271 => out1_2__Z.ENA +G_271 => out1_1__Z.ENA +G_271 => out1_0__Z.ENA +rst_i_i => rst_i_i_i.IN0 +un11_w_alu_res_add7 => out1_7__Z.DATAB +un11_w_alu_res_add7 => out0_7__Z.DATAB +un11_w_alu_res_add7 => fsr_7__Z.DATAB +un11_w_alu_res_add3 => din_r_3__Z.DATAB +un11_w_alu_res_add3 => out1_3__Z.DATAB +un11_w_alu_res_add3 => out0_3__Z.DATAB +un11_w_alu_res_add3 => fsr_3__Z.DATAB +un11_w_alu_res_add4 => din_r_4__Z.DATAB +un11_w_alu_res_add4 => out1_4__Z.DATAB +un11_w_alu_res_add4 => out0_4__Z.DATAB +un11_w_alu_res_add4 => fsr_4__Z.DATAB +un11_w_alu_res_add5 => din_r_5__Z.DATAB +un11_w_alu_res_add5 => out1_5__Z.DATAB +un11_w_alu_res_add5 => out0_5__Z.DATAB +un11_w_alu_res_add5 => fsr_5__Z.DATAB +un11_w_alu_res_add6 => din_r_6__Z.DATAB +un11_w_alu_res_add6 => out1_6__Z.DATAB +un11_w_alu_res_add6 => out0_6__Z.DATAB +un11_w_alu_res_add6 => fsr_6__Z.DATAB +w_c_2mem_i_a3 => din_r_6__Z.DATAA +w_c_2mem_i_a3 => din_r_5__Z.DATAA +w_c_2mem_i_a3 => din_r_4__Z.DATAA +w_c_2mem_i_a3 => din_r_3__Z.DATAA +w_c_2mem_i_a3 => out1_7__Z.DATAA +w_c_2mem_i_a3 => out1_6__Z.DATAA +w_c_2mem_i_a3 => out1_5__Z.DATAA +w_c_2mem_i_a3 => out1_4__Z.DATAA +w_c_2mem_i_a3 => out1_3__Z.DATAA +w_c_2mem_i_a3 => out0_7__Z.DATAA +w_c_2mem_i_a3 => out0_6__Z.DATAA +w_c_2mem_i_a3 => out0_5__Z.DATAA +w_c_2mem_i_a3 => out0_4__Z.DATAA +w_c_2mem_i_a3 => out0_3__Z.DATAA +w_c_2mem_i_a3 => fsr_7__Z.DATAA +w_c_2mem_i_a3 => fsr_6__Z.DATAA +w_c_2mem_i_a3 => fsr_5__Z.DATAA +w_c_2mem_i_a3 => fsr_4__Z.DATAA +w_c_2mem_i_a3 => fsr_3__Z.DATAA +w_c_2mem_i_a3 => status_6_a_0_.DATAC +w_mem_wr_r => wr_en_r_Z.DATAC +w_mem_wr_r => write_out0_0_a3_0_o2_cZ.DATAA +w_mem_wr_r => ram128x8:i_reg_file.w_mem_wr_r +clk_c => wr_en_r_Z.CLK +clk_c => reg_in1_0__Z.CLK +clk_c => reg_in1_1__Z.CLK +clk_c => reg_in1_2__Z.CLK +clk_c => reg_in1_3__Z.CLK +clk_c => reg_in1_4__Z.CLK +clk_c => reg_in1_5__Z.CLK +clk_c => reg_in1_6__Z.CLK +clk_c => reg_in1_7__Z.CLK +clk_c => wr_addr_r_1__Z.CLK +clk_c => wr_addr_r_2__Z.CLK +clk_c => wr_addr_r_3__Z.CLK +clk_c => din_r_6__Z.CLK +clk_c => din_r_5__Z.CLK +clk_c => din_r_4__Z.CLK +clk_c => din_r_3__Z.CLK +clk_c => din_r_2__Z.CLK +clk_c => din_r_1__Z.CLK +clk_c => din_r_0__Z.CLK +clk_c => wr_addr_r_4__Z.CLK +clk_c => wr_addr_r_0__Z.CLK +clk_c => reg_in0_7__Z.CLK +clk_c => reg_in0_6__Z.CLK +clk_c => reg_in0_5__Z.CLK +clk_c => reg_in0_4__Z.CLK +clk_c => reg_in0_3__Z.CLK +clk_c => reg_in0_2__Z.CLK +clk_c => reg_in0_1__Z.CLK +clk_c => reg_in0_0__Z.CLK +clk_c => status_7__Z.CLK +clk_c => status_6__Z.CLK +clk_c => status_5__Z.CLK +clk_c => status_4__Z.CLK +clk_c => status_3__Z.CLK +clk_c => status_2__Z.CLK +clk_c => status_1__Z.CLK +clk_c => status_0__Z.CLK +clk_c => out1_7__Z.CLK +clk_c => out1_6__Z.CLK +clk_c => out1_5__Z.CLK +clk_c => out1_4__Z.CLK +clk_c => out1_3__Z.CLK +clk_c => out1_2__Z.CLK +clk_c => out1_1__Z.CLK +clk_c => out1_0__Z.CLK +clk_c => out0_7__Z.CLK +clk_c => out0_6__Z.CLK +clk_c => out0_5__Z.CLK +clk_c => out0_4__Z.CLK +clk_c => out0_3__Z.CLK +clk_c => out0_2__Z.CLK +clk_c => out0_1__Z.CLK +clk_c => out0_0__Z.CLK +clk_c => fsr_7__Z.CLK +clk_c => fsr_6__Z.CLK +clk_c => fsr_5__Z.CLK +clk_c => fsr_4__Z.CLK +clk_c => fsr_3__Z.CLK +clk_c => fsr_2__Z.CLK +clk_c => fsr_1__Z.CLK +clk_c => fsr_0__Z.CLK +clk_c => ram128x8:i_reg_file.clk_c + + +|ClaiRISC_core|wb_mem_man:mem_man|ram128x8:i_reg_file +alt_ram_q_7 <= altsyncram_Z1:altsyncram_component_Z.q_b[7] +alt_ram_q_6 <= altsyncram_Z1:altsyncram_component_Z.q_b[6] +alt_ram_q_5 <= altsyncram_Z1:altsyncram_component_Z.q_b[5] +alt_ram_q_4 <= altsyncram_Z1:altsyncram_component_Z.q_b[4] +alt_ram_q_3 <= altsyncram_Z1:altsyncram_component_Z.q_b[3] +alt_ram_q_2 <= altsyncram_Z1:altsyncram_component_Z.q_b[2] +alt_ram_q_1 <= altsyncram_Z1:altsyncram_component_Z.q_b[1] +alt_ram_q_0 <= altsyncram_Z1:altsyncram_component_Z.q_b[0] +w_ins_4 => altsyncram_Z1:altsyncram_component_Z.address_b[4] +w_ins_3 => altsyncram_Z1:altsyncram_component_Z.address_b[3] +w_ins_2 => altsyncram_Z1:altsyncram_component_Z.address_b[2] +w_ins_1 => altsyncram_Z1:altsyncram_component_Z.address_b[1] +w_ins_0 => altsyncram_Z1:altsyncram_component_Z.address_b[0] +fsr_1 => altsyncram_Z1:altsyncram_component_Z.address_b[6] +fsr_1 => altsyncram_Z1:altsyncram_component_Z.address_a[6] +fsr_0 => altsyncram_Z1:altsyncram_component_Z.address_b[5] +fsr_0 => altsyncram_Z1:altsyncram_component_Z.address_a[5] +w_ek_r_4 => altsyncram_Z1:altsyncram_component_Z.address_a[4] +w_ek_r_3 => altsyncram_Z1:altsyncram_component_Z.address_a[3] +w_ek_r_2 => altsyncram_Z1:altsyncram_component_Z.address_a[2] +w_ek_r_1 => altsyncram_Z1:altsyncram_component_Z.address_a[1] +w_ek_r_0 => altsyncram_Z1:altsyncram_component_Z.address_a[0] +w_alu_res_1_6_2 => altsyncram_Z1:altsyncram_component_Z.data_a[7] +w_alu_res_1_6_1 => altsyncram_Z1:altsyncram_component_Z.data_a[6] +w_alu_res_1_6_0 => altsyncram_Z1:altsyncram_component_Z.data_a[5] +w_alu_res_1_3_0 => altsyncram_Z1:altsyncram_component_Z.data_a[4] +w_alu_res_1_1_0 => altsyncram_Z1:altsyncram_component_Z.data_a[3] +w_alu_res_1_0_2 => altsyncram_Z1:altsyncram_component_Z.data_a[2] +w_alu_res_1_0_1 => altsyncram_Z1:altsyncram_component_Z.data_a[1] +w_alu_res_1_0_0 => altsyncram_Z1:altsyncram_component_Z.data_a[0] +clk_c => altsyncram_Z1:altsyncram_component_Z.clock0 +w_mem_wr_r => altsyncram_Z1:altsyncram_component_Z.wren_a + + +|ClaiRISC_core|wb_mem_man:mem_man|ram128x8:i_reg_file|altsyncram_Z1:altsyncram_component_Z +wren_a => altsyncram:U1.wren_a +data_a[0] => altsyncram:U1.data_a +data_a[1] => altsyncram:U1.data_a +data_a[2] => altsyncram:U1.data_a +data_a[3] => altsyncram:U1.data_a +data_a[4] => altsyncram:U1.data_a +data_a[5] => altsyncram:U1.data_a +data_a[6] => altsyncram:U1.data_a +data_a[7] => altsyncram:U1.data_a +address_a[0] => altsyncram:U1.address_a +address_a[1] => altsyncram:U1.address_a +address_a[2] => altsyncram:U1.address_a +address_a[3] => altsyncram:U1.address_a +address_a[4] => altsyncram:U1.address_a +address_a[5] => altsyncram:U1.address_a +address_a[6] => altsyncram:U1.address_a +address_b[0] => altsyncram:U1.address_b +address_b[1] => altsyncram:U1.address_b +address_b[2] => altsyncram:U1.address_b +address_b[3] => altsyncram:U1.address_b +address_b[4] => altsyncram:U1.address_b +address_b[5] => altsyncram:U1.address_b +address_b[6] => altsyncram:U1.address_b +clock0 => altsyncram:U1.clock0 +q_a[0] <= altsyncram:U1.q_a +q_a[1] <= altsyncram:U1.q_a +q_a[2] <= altsyncram:U1.q_a +q_a[3] <= altsyncram:U1.q_a +q_a[4] <= altsyncram:U1.q_a +q_a[5] <= altsyncram:U1.q_a +q_a[6] <= altsyncram:U1.q_a +q_a[7] <= altsyncram:U1.q_a +q_b[0] <= altsyncram:U1.q_b +q_b[1] <= altsyncram:U1.q_b +q_b[2] <= altsyncram:U1.q_b +q_b[3] <= altsyncram:U1.q_b +q_b[4] <= altsyncram:U1.q_b +q_b[5] <= altsyncram:U1.q_b +q_b[6] <= altsyncram:U1.q_b +q_b[7] <= altsyncram:U1.q_b + + +|ClaiRISC_core|wb_mem_man:mem_man|ram128x8:i_reg_file|altsyncram_Z1:altsyncram_component_Z|altsyncram:U1 +wren_a => altsyncram_hg91:auto_generated.wren_a +wren_b => ~NO_FANOUT~ +rden_b => ~NO_FANOUT~ +data_a[0] => altsyncram_hg91:auto_generated.data_a[0] +data_a[1] => altsyncram_hg91:auto_generated.data_a[1] +data_a[2] => altsyncram_hg91:auto_generated.data_a[2] +data_a[3] => altsyncram_hg91:auto_generated.data_a[3] +data_a[4] => altsyncram_hg91:auto_generated.data_a[4] +data_a[5] => altsyncram_hg91:auto_generated.data_a[5] +data_a[6] => altsyncram_hg91:auto_generated.data_a[6] +data_a[7] => altsyncram_hg91:auto_generated.data_a[7] +data_b[0] => ~NO_FANOUT~ +data_b[1] => ~NO_FANOUT~ +data_b[2] => ~NO_FANOUT~ +data_b[3] => ~NO_FANOUT~ +data_b[4] => ~NO_FANOUT~ +data_b[5] => ~NO_FANOUT~ +data_b[6] => ~NO_FANOUT~ +data_b[7] => ~NO_FANOUT~ +address_a[0] => altsyncram_hg91:auto_generated.address_a[0] +address_a[1] => altsyncram_hg91:auto_generated.address_a[1] +address_a[2] => altsyncram_hg91:auto_generated.address_a[2] +address_a[3] => altsyncram_hg91:auto_generated.address_a[3] +address_a[4] => altsyncram_hg91:auto_generated.address_a[4] +address_a[5] => altsyncram_hg91:auto_generated.address_a[5] +address_a[6] => altsyncram_hg91:auto_generated.address_a[6] +address_b[0] => altsyncram_hg91:auto_generated.address_b[0] +address_b[1] => altsyncram_hg91:auto_generated.address_b[1] +address_b[2] => altsyncram_hg91:auto_generated.address_b[2] +address_b[3] => altsyncram_hg91:auto_generated.address_b[3] +address_b[4] => altsyncram_hg91:auto_generated.address_b[4] +address_b[5] => altsyncram_hg91:auto_generated.address_b[5] +address_b[6] => altsyncram_hg91:auto_generated.address_b[6] +addressstall_a => ~NO_FANOUT~ +addressstall_b => ~NO_FANOUT~ +clock0 => altsyncram_hg91:auto_generated.clock0 +clock1 => ~NO_FANOUT~ +clocken0 => ~NO_FANOUT~ +clocken1 => ~NO_FANOUT~ +aclr0 => ~NO_FANOUT~ +aclr1 => ~NO_FANOUT~ +byteena_a[0] => ~NO_FANOUT~ +byteena_b[0] => ~NO_FANOUT~ +q_a[0] <= altsyncram_hg91:auto_generated.q_a[0] +q_a[1] <= altsyncram_hg91:auto_generated.q_a[1] +q_a[2] <= altsyncram_hg91:auto_generated.q_a[2] +q_a[3] <= altsyncram_hg91:auto_generated.q_a[3] +q_a[4] <= altsyncram_hg91:auto_generated.q_a[4] +q_a[5] <= altsyncram_hg91:auto_generated.q_a[5] +q_a[6] <= altsyncram_hg91:auto_generated.q_a[6] +q_a[7] <= altsyncram_hg91:auto_generated.q_a[7] +q_b[0] <= altsyncram_hg91:auto_generated.q_b[0] +q_b[1] <= altsyncram_hg91:auto_generated.q_b[1] +q_b[2] <= altsyncram_hg91:auto_generated.q_b[2] +q_b[3] <= altsyncram_hg91:auto_generated.q_b[3] +q_b[4] <= altsyncram_hg91:auto_generated.q_b[4] +q_b[5] <= altsyncram_hg91:auto_generated.q_b[5] +q_b[6] <= altsyncram_hg91:auto_generated.q_b[6] +q_b[7] <= altsyncram_hg91:auto_generated.q_b[7] + + +|ClaiRISC_core|wb_mem_man:mem_man|ram128x8:i_reg_file|altsyncram_Z1:altsyncram_component_Z|altsyncram:U1|altsyncram_hg91:auto_generated +address_a[0] => ram_block1a0.PORTAADDR +address_a[0] => ram_block1a1.PORTAADDR +address_a[0] => ram_block1a2.PORTAADDR +address_a[0] => ram_block1a3.PORTAADDR +address_a[0] => ram_block1a4.PORTAADDR +address_a[0] => ram_block1a5.PORTAADDR +address_a[0] => ram_block1a6.PORTAADDR +address_a[0] => ram_block1a7.PORTAADDR +address_a[1] => ram_block1a0.PORTAADDR1 +address_a[1] => ram_block1a1.PORTAADDR1 +address_a[1] => ram_block1a2.PORTAADDR1 +address_a[1] => ram_block1a3.PORTAADDR1 +address_a[1] => ram_block1a4.PORTAADDR1 +address_a[1] => ram_block1a5.PORTAADDR1 +address_a[1] => ram_block1a6.PORTAADDR1 +address_a[1] => ram_block1a7.PORTAADDR1 +address_a[2] => ram_block1a0.PORTAADDR2 +address_a[2] => ram_block1a1.PORTAADDR2 +address_a[2] => ram_block1a2.PORTAADDR2 +address_a[2] => ram_block1a3.PORTAADDR2 +address_a[2] => ram_block1a4.PORTAADDR2 +address_a[2] => ram_block1a5.PORTAADDR2 +address_a[2] => ram_block1a6.PORTAADDR2 +address_a[2] => ram_block1a7.PORTAADDR2 +address_a[3] => ram_block1a0.PORTAADDR3 +address_a[3] => ram_block1a1.PORTAADDR3 +address_a[3] => ram_block1a2.PORTAADDR3 +address_a[3] => ram_block1a3.PORTAADDR3 +address_a[3] => ram_block1a4.PORTAADDR3 +address_a[3] => ram_block1a5.PORTAADDR3 +address_a[3] => ram_block1a6.PORTAADDR3 +address_a[3] => ram_block1a7.PORTAADDR3 +address_a[4] => ram_block1a0.PORTAADDR4 +address_a[4] => ram_block1a1.PORTAADDR4 +address_a[4] => ram_block1a2.PORTAADDR4 +address_a[4] => ram_block1a3.PORTAADDR4 +address_a[4] => ram_block1a4.PORTAADDR4 +address_a[4] => ram_block1a5.PORTAADDR4 +address_a[4] => ram_block1a6.PORTAADDR4 +address_a[4] => ram_block1a7.PORTAADDR4 +address_a[5] => ram_block1a0.PORTAADDR5 +address_a[5] => ram_block1a1.PORTAADDR5 +address_a[5] => ram_block1a2.PORTAADDR5 +address_a[5] => ram_block1a3.PORTAADDR5 +address_a[5] => ram_block1a4.PORTAADDR5 +address_a[5] => ram_block1a5.PORTAADDR5 +address_a[5] => ram_block1a6.PORTAADDR5 +address_a[5] => ram_block1a7.PORTAADDR5 +address_a[6] => ram_block1a0.PORTAADDR6 +address_a[6] => ram_block1a1.PORTAADDR6 +address_a[6] => ram_block1a2.PORTAADDR6 +address_a[6] => ram_block1a3.PORTAADDR6 +address_a[6] => ram_block1a4.PORTAADDR6 +address_a[6] => ram_block1a5.PORTAADDR6 +address_a[6] => ram_block1a6.PORTAADDR6 +address_a[6] => ram_block1a7.PORTAADDR6 +address_b[0] => ram_block1a0.PORTBADDR +address_b[0] => ram_block1a1.PORTBADDR +address_b[0] => ram_block1a2.PORTBADDR +address_b[0] => ram_block1a3.PORTBADDR +address_b[0] => ram_block1a4.PORTBADDR +address_b[0] => ram_block1a5.PORTBADDR +address_b[0] => ram_block1a6.PORTBADDR +address_b[0] => ram_block1a7.PORTBADDR +address_b[1] => ram_block1a0.PORTBADDR1 +address_b[1] => ram_block1a1.PORTBADDR1 +address_b[1] => ram_block1a2.PORTBADDR1 +address_b[1] => ram_block1a3.PORTBADDR1 +address_b[1] => ram_block1a4.PORTBADDR1 +address_b[1] => ram_block1a5.PORTBADDR1 +address_b[1] => ram_block1a6.PORTBADDR1 +address_b[1] => ram_block1a7.PORTBADDR1 +address_b[2] => ram_block1a0.PORTBADDR2 +address_b[2] => ram_block1a1.PORTBADDR2 +address_b[2] => ram_block1a2.PORTBADDR2 +address_b[2] => ram_block1a3.PORTBADDR2 +address_b[2] => ram_block1a4.PORTBADDR2 +address_b[2] => ram_block1a5.PORTBADDR2 +address_b[2] => ram_block1a6.PORTBADDR2 +address_b[2] => ram_block1a7.PORTBADDR2 +address_b[3] => ram_block1a0.PORTBADDR3 +address_b[3] => ram_block1a1.PORTBADDR3 +address_b[3] => ram_block1a2.PORTBADDR3 +address_b[3] => ram_block1a3.PORTBADDR3 +address_b[3] => ram_block1a4.PORTBADDR3 +address_b[3] => ram_block1a5.PORTBADDR3 +address_b[3] => ram_block1a6.PORTBADDR3 +address_b[3] => ram_block1a7.PORTBADDR3 +address_b[4] => ram_block1a0.PORTBADDR4 +address_b[4] => ram_block1a1.PORTBADDR4 +address_b[4] => ram_block1a2.PORTBADDR4 +address_b[4] => ram_block1a3.PORTBADDR4 +address_b[4] => ram_block1a4.PORTBADDR4 +address_b[4] => ram_block1a5.PORTBADDR4 +address_b[4] => ram_block1a6.PORTBADDR4 +address_b[4] => ram_block1a7.PORTBADDR4 +address_b[5] => ram_block1a0.PORTBADDR5 +address_b[5] => ram_block1a1.PORTBADDR5 +address_b[5] => ram_block1a2.PORTBADDR5 +address_b[5] => ram_block1a3.PORTBADDR5 +address_b[5] => ram_block1a4.PORTBADDR5 +address_b[5] => ram_block1a5.PORTBADDR5 +address_b[5] => ram_block1a6.PORTBADDR5 +address_b[5] => ram_block1a7.PORTBADDR5 +address_b[6] => ram_block1a0.PORTBADDR6 +address_b[6] => ram_block1a1.PORTBADDR6 +address_b[6] => ram_block1a2.PORTBADDR6 +address_b[6] => ram_block1a3.PORTBADDR6 +address_b[6] => ram_block1a4.PORTBADDR6 +address_b[6] => ram_block1a5.PORTBADDR6 +address_b[6] => ram_block1a6.PORTBADDR6 +address_b[6] => ram_block1a7.PORTBADDR6 +clock0 => ram_block1a0.CLK0 +clock0 => ram_block1a1.CLK0 +clock0 => ram_block1a2.CLK0 +clock0 => ram_block1a3.CLK0 +clock0 => ram_block1a4.CLK0 +clock0 => ram_block1a5.CLK0 +clock0 => ram_block1a6.CLK0 +clock0 => ram_block1a7.CLK0 +data_a[0] => ram_block1a0.PORTADATAIN +data_a[1] => ram_block1a1.PORTADATAIN +data_a[2] => ram_block1a2.PORTADATAIN +data_a[3] => ram_block1a3.PORTADATAIN +data_a[4] => ram_block1a4.PORTADATAIN +data_a[5] => ram_block1a5.PORTADATAIN +data_a[6] => ram_block1a6.PORTADATAIN +data_a[7] => ram_block1a7.PORTADATAIN +q_a[0] <= +q_a[1] <= +q_a[2] <= +q_a[3] <= +q_a[4] <= +q_a[5] <= +q_a[6] <= +q_a[7] <= +q_b[0] <= ram_block1a0.PORTBDATAOUT +q_b[1] <= ram_block1a1.PORTBDATAOUT +q_b[2] <= ram_block1a2.PORTBDATAOUT +q_b[3] <= ram_block1a3.PORTBDATAOUT +q_b[4] <= ram_block1a4.PORTBDATAOUT +q_b[5] <= ram_block1a5.PORTBDATAOUT +q_b[6] <= ram_block1a6.PORTBDATAOUT +q_b[7] <= ram_block1a7.PORTBDATAOUT +wren_a => ram_block1a0.PORTAWE +wren_a => ram_block1a1.PORTAWE +wren_a => ram_block1a2.PORTAWE +wren_a => ram_block1a3.PORTAWE +wren_a => ram_block1a4.PORTAWE +wren_a => ram_block1a5.PORTAWE +wren_a => ram_block1a6.PORTAWE +wren_a => ram_block1a7.PORTAWE + + +|ClaiRISC_core|pram:program_rom +sclrsclrw_pc_nxt_0_0_a2_x_0 => rom128x12:i_alt_ram.sclrsclrw_pc_nxt_0_0_a2_x_0 +sclrsclrw_pc_nxt_0_0_a2_x_1 => rom128x12:i_alt_ram.sclrsclrw_pc_nxt_0_0_a2_x_1 +sclrsclrw_pc_nxt_0_0_a2_x_2 => rom128x12:i_alt_ram.sclrsclrw_pc_nxt_0_0_a2_x_2 +sclrsclrw_pc_nxt_0_0_a2_x_3 => rom128x12:i_alt_ram.sclrsclrw_pc_nxt_0_0_a2_x_3 +sclrsclrw_pc_nxt_0_0_a2_x_4 => rom128x12:i_alt_ram.sclrsclrw_pc_nxt_0_0_a2_x_4 +sclrsclrw_pc_nxt_0_0_a2_x_5 => rom128x12:i_alt_ram.sclrsclrw_pc_nxt_0_0_a2_x_5 +sclrsclrw_pc_nxt_0_0_a2_x_6 => rom128x12:i_alt_ram.sclrsclrw_pc_nxt_0_0_a2_x_6 +w_ins_0 <= rom128x12:i_alt_ram.w_ins_0 +w_ins_1 <= rom128x12:i_alt_ram.w_ins_1 +w_ins_2 <= rom128x12:i_alt_ram.w_ins_2 +w_ins_3 <= rom128x12:i_alt_ram.w_ins_3 +w_ins_4 <= rom128x12:i_alt_ram.w_ins_4 +w_ins_6 <= rom128x12:i_alt_ram.w_ins_6 +w_ins_7 <= rom128x12:i_alt_ram.w_ins_7 +clk_c => rom128x12:i_alt_ram.clk_c +w_mem_wr <= rom128x12:i_alt_ram.w_mem_wr + + +|ClaiRISC_core|pram:program_rom|rom128x12:i_alt_ram +w_ins_7 <= altsyncram_Z2:altsyncram_component_Z.q_a[7] +w_ins_6 <= altsyncram_Z2:altsyncram_component_Z.q_a[6] +w_ins_4 <= altsyncram_Z2:altsyncram_component_Z.q_a[4] +w_ins_3 <= altsyncram_Z2:altsyncram_component_Z.q_a[3] +w_ins_2 <= altsyncram_Z2:altsyncram_component_Z.q_a[2] +w_ins_1 <= altsyncram_Z2:altsyncram_component_Z.q_a[1] +w_ins_0 <= altsyncram_Z2:altsyncram_component_Z.q_a[0] +sclrsclrw_pc_nxt_0_0_a2_x_6 => altsyncram_Z2:altsyncram_component_Z.address_a[6] +sclrsclrw_pc_nxt_0_0_a2_x_5 => altsyncram_Z2:altsyncram_component_Z.address_a[5] +sclrsclrw_pc_nxt_0_0_a2_x_4 => altsyncram_Z2:altsyncram_component_Z.address_a[4] +sclrsclrw_pc_nxt_0_0_a2_x_3 => altsyncram_Z2:altsyncram_component_Z.address_a[3] +sclrsclrw_pc_nxt_0_0_a2_x_2 => altsyncram_Z2:altsyncram_component_Z.address_a[2] +sclrsclrw_pc_nxt_0_0_a2_x_1 => altsyncram_Z2:altsyncram_component_Z.address_a[1] +sclrsclrw_pc_nxt_0_0_a2_x_0 => altsyncram_Z2:altsyncram_component_Z.address_a[0] +w_mem_wr <= altsyncram_Z2:altsyncram_component_Z.q_a[5] +clk_c => altsyncram_Z2:altsyncram_component_Z.clock0 + + +|ClaiRISC_core|pram:program_rom|rom128x12:i_alt_ram|altsyncram_Z2:altsyncram_component_Z +address_a[0] => altsyncram:U1.address_a +address_a[1] => altsyncram:U1.address_a +address_a[2] => altsyncram:U1.address_a +address_a[3] => altsyncram:U1.address_a +address_a[4] => altsyncram:U1.address_a +address_a[5] => altsyncram:U1.address_a +address_a[6] => altsyncram:U1.address_a +clock0 => altsyncram:U1.clock0 +q_a[0] <= altsyncram:U1.q_a +q_a[1] <= altsyncram:U1.q_a +q_a[2] <= altsyncram:U1.q_a +q_a[3] <= altsyncram:U1.q_a +q_a[4] <= altsyncram:U1.q_a +q_a[5] <= altsyncram:U1.q_a +q_a[6] <= altsyncram:U1.q_a +q_a[7] <= altsyncram:U1.q_a +q_b[0] <= altsyncram:U1.q_b + + +|ClaiRISC_core|pram:program_rom|rom128x12:i_alt_ram|altsyncram_Z2:altsyncram_component_Z|altsyncram:U1 +wren_a => ~NO_FANOUT~ +wren_b => ~NO_FANOUT~ +rden_b => ~NO_FANOUT~ +data_a[0] => ~NO_FANOUT~ +data_a[1] => ~NO_FANOUT~ +data_a[2] => ~NO_FANOUT~ +data_a[3] => ~NO_FANOUT~ +data_a[4] => ~NO_FANOUT~ +data_a[5] => ~NO_FANOUT~ +data_a[6] => ~NO_FANOUT~ +data_a[7] => ~NO_FANOUT~ +data_b[0] => ~NO_FANOUT~ +address_a[0] => altsyncram_u8r:auto_generated.address_a[0] +address_a[1] => altsyncram_u8r:auto_generated.address_a[1] +address_a[2] => altsyncram_u8r:auto_generated.address_a[2] +address_a[3] => altsyncram_u8r:auto_generated.address_a[3] +address_a[4] => altsyncram_u8r:auto_generated.address_a[4] +address_a[5] => altsyncram_u8r:auto_generated.address_a[5] +address_a[6] => altsyncram_u8r:auto_generated.address_a[6] +address_b[0] => ~NO_FANOUT~ +addressstall_a => ~NO_FANOUT~ +addressstall_b => ~NO_FANOUT~ +clock0 => altsyncram_u8r:auto_generated.clock0 +clock1 => ~NO_FANOUT~ +clocken0 => ~NO_FANOUT~ +clocken1 => ~NO_FANOUT~ +aclr0 => ~NO_FANOUT~ +aclr1 => ~NO_FANOUT~ +byteena_a[0] => ~NO_FANOUT~ +byteena_b[0] => ~NO_FANOUT~ +q_a[0] <= altsyncram_u8r:auto_generated.q_a[0] +q_a[1] <= altsyncram_u8r:auto_generated.q_a[1] +q_a[2] <= altsyncram_u8r:auto_generated.q_a[2] +q_a[3] <= altsyncram_u8r:auto_generated.q_a[3] +q_a[4] <= altsyncram_u8r:auto_generated.q_a[4] +q_a[5] <= altsyncram_u8r:auto_generated.q_a[5] +q_a[6] <= altsyncram_u8r:auto_generated.q_a[6] +q_a[7] <= altsyncram_u8r:auto_generated.q_a[7] +q_b[0] <= altsyncram_u8r:auto_generated.q_b[0] + + +|ClaiRISC_core|pram:program_rom|rom128x12:i_alt_ram|altsyncram_Z2:altsyncram_component_Z|altsyncram:U1|altsyncram_u8r:auto_generated +address_a[0] => ram_block1a0.PORTAADDR +address_a[0] => ram_block1a1.PORTAADDR +address_a[0] => ram_block1a2.PORTAADDR +address_a[0] => ram_block1a3.PORTAADDR +address_a[0] => ram_block1a4.PORTAADDR +address_a[0] => ram_block1a5.PORTAADDR +address_a[0] => ram_block1a6.PORTAADDR +address_a[0] => ram_block1a7.PORTAADDR +address_a[1] => ram_block1a0.PORTAADDR1 +address_a[1] => ram_block1a1.PORTAADDR1 +address_a[1] => ram_block1a2.PORTAADDR1 +address_a[1] => ram_block1a3.PORTAADDR1 +address_a[1] => ram_block1a4.PORTAADDR1 +address_a[1] => ram_block1a5.PORTAADDR1 +address_a[1] => ram_block1a6.PORTAADDR1 +address_a[1] => ram_block1a7.PORTAADDR1 +address_a[2] => ram_block1a0.PORTAADDR2 +address_a[2] => ram_block1a1.PORTAADDR2 +address_a[2] => ram_block1a2.PORTAADDR2 +address_a[2] => ram_block1a3.PORTAADDR2 +address_a[2] => ram_block1a4.PORTAADDR2 +address_a[2] => ram_block1a5.PORTAADDR2 +address_a[2] => ram_block1a6.PORTAADDR2 +address_a[2] => ram_block1a7.PORTAADDR2 +address_a[3] => ram_block1a0.PORTAADDR3 +address_a[3] => ram_block1a1.PORTAADDR3 +address_a[3] => ram_block1a2.PORTAADDR3 +address_a[3] => ram_block1a3.PORTAADDR3 +address_a[3] => ram_block1a4.PORTAADDR3 +address_a[3] => ram_block1a5.PORTAADDR3 +address_a[3] => ram_block1a6.PORTAADDR3 +address_a[3] => ram_block1a7.PORTAADDR3 +address_a[4] => ram_block1a0.PORTAADDR4 +address_a[4] => ram_block1a1.PORTAADDR4 +address_a[4] => ram_block1a2.PORTAADDR4 +address_a[4] => ram_block1a3.PORTAADDR4 +address_a[4] => ram_block1a4.PORTAADDR4 +address_a[4] => ram_block1a5.PORTAADDR4 +address_a[4] => ram_block1a6.PORTAADDR4 +address_a[4] => ram_block1a7.PORTAADDR4 +address_a[5] => ram_block1a0.PORTAADDR5 +address_a[5] => ram_block1a1.PORTAADDR5 +address_a[5] => ram_block1a2.PORTAADDR5 +address_a[5] => ram_block1a3.PORTAADDR5 +address_a[5] => ram_block1a4.PORTAADDR5 +address_a[5] => ram_block1a5.PORTAADDR5 +address_a[5] => ram_block1a6.PORTAADDR5 +address_a[5] => ram_block1a7.PORTAADDR5 +address_a[6] => ram_block1a0.PORTAADDR6 +address_a[6] => ram_block1a1.PORTAADDR6 +address_a[6] => ram_block1a2.PORTAADDR6 +address_a[6] => ram_block1a3.PORTAADDR6 +address_a[6] => ram_block1a4.PORTAADDR6 +address_a[6] => ram_block1a5.PORTAADDR6 +address_a[6] => ram_block1a6.PORTAADDR6 +address_a[6] => ram_block1a7.PORTAADDR6 +clock0 => ram_block1a0.CLK0 +clock0 => ram_block1a1.CLK0 +clock0 => ram_block1a2.CLK0 +clock0 => ram_block1a3.CLK0 +clock0 => ram_block1a4.CLK0 +clock0 => ram_block1a5.CLK0 +clock0 => ram_block1a6.CLK0 +clock0 => ram_block1a7.CLK0 +q_a[0] <= ram_block1a0.PORTADATAOUT +q_a[1] <= ram_block1a1.PORTADATAOUT +q_a[2] <= ram_block1a2.PORTADATAOUT +q_a[3] <= ram_block1a3.PORTADATAOUT +q_a[4] <= ram_block1a4.PORTADATAOUT +q_a[5] <= ram_block1a5.PORTADATAOUT +q_a[6] <= ram_block1a6.PORTADATAOUT +q_a[7] <= ram_block1a7.PORTADATAOUT +q_b[0] <= + +

/trunk/QU2/db/ClaiRISC_core.(10).cnf.hdb +vG8,ØÙÃÕ×±¢'þ-PŠ�
dƒyº�âéæé \ No newline at end of file

/trunk/QU2/db/ClaiRISC_core.map.cdb

/trunk/QU2/db/ClaiRISC_core.cmp.cdb +q`eÚæ�¥5mÚ=óµZäôÞšªëåiB†tì&g"×'Ò×ðë&£ š�1=­¯Zow^/Ï7Ñc/»WYu}ë®59N•,�_VÅoºå¯Ç\ó}�ßh¦K^®�{~£Y[wM<1²Ëd”ÑlÌ&Û^Æñ¶Tõó

/trunk/QU2/db/ClaiRISC_core.rtlv_sg.cdb

0,0 → 1,6

+ ΄2ÆñÛuuÑʾ»uëÅÉ´ýw.ôºªæOÒV�‹Ê‹åcœÄåF|X‡¾$\Ä›.³(M_ßöêêJô>çYØ2hþÇÁ�ŒÃÝÍEãtçßoŽ¸âÇèšÿ3Rf]W4êþ¤Ë_ÅLJ¨§.?aºÁß·†Xoݦ;îtâ"Æ]oQ}šŸa„uEuöï\Û^#tm;Ô(ûÁHó— +óüY=4ùº×T
ÕZö{÷¬!Æ žwÕ‡‚Ïï�HUuUZ•ÎYÝÃÇ ÒA!Ñù‡
Ïá�ùó-‡§ +¾~èêIi=‹FÜz0ëhúxLç pVe?ˆPÇçÖI³ʺ±ÄZËÄ¡?GÆY@�êê¤Ù,•u7•°»#Øù3èâòkj +Ùj­U�5ÔOûˆ¥u \ No newline at end of file

/trunk/QU2/db/ClaiRISC_core.cmp.ddb

0,0 → 1,6

/trunk/QU2/db/ClaiRISC_core.sld_design_entry.sci

0,0 → 1,2

+ÄÁΞñ.®Ážî~Ö}Ü5ÛÁrL @ÿÿ \ No newline at end of file

/trunk/QU2/db/ClaiRISC_core.map.hdb

0,0 → 1,2

/trunk/QU2/db/ClaiRISC_core.pre_map.cdb

0,0 → 1,3

+wC80Ž®ì=<<<ˆ��}pN×í±1Â#q©¿ñ¨ëEÈò›ááÅÁTýw,ô:«ä�ӆ¼ò|ùè \ No newline at end of file

/trunk/QU2/db/ClaiRISC_core.cmp.hdb

0,0 → 1,3

+R.[†1—� “(«”±+�0gÊ¥^×.l‡*†¸�'çÓAís•§
04×_Ðœ7J'“rê!ó$.D©so²Kñ;¿Ýûv(' ©`+’5**äOІ_aˆ‚ÆawúNÀÚï4‚�ÆÂb§±”;]k�×¾3|nYÿÄõÎ_�Ë.…�‚«}ìÞZ+”F!^thÒ($[¿ï.gpg8l¥)áåëÜšR/lï©Â!©¡p¡7¿ãÔ�–N±7GôŽòU)µuˆuV‡X€ž›/Hö÷’e­7�NpE‚ÿèi8^eo€ÿ4×|6 \ No newline at end of file

/trunk/QU2/db/ClaiRISC_core.(0).cnf.cdb

0,0 → 1,3

/trunk/QU2/db/ClaiRISC_core.(2).cnf.cdb

0,0 → 1,5

+ö÷†ýá¡Ú"/öñsûP‘;MÕí>€d{Wî‘J:­·ÄG¨9º´vNc'i+5´Õ \ No newline at end of file

/trunk/QU2/db/ClaiRISC_core.pre_map.hdb

0,0 → 1,5

/trunk/QU2/db/ClaiRISC_core.(4).cnf.cdb

0,0 → 1,5

/trunk/QU2/db/ClaiRISC_core.(0).cnf.hdb

0,0 → 1,5

+oÂFg±–¡6y9EIÔ>Ú§ó5Ç©ÖK¦ÍÓX+X„lƒŒ¾5[î¬Ú]‰�¸[˜Ô¯§ó/V´­Û"¥sÍJ±IÛ \ No newline at end of file

/trunk/QU2/db/altsyncram_hg91.tdf

0,0 → 1,317

--altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone" INDATA_ACLR_A="NONE" NUMWORDS_A=128 NUMWORDS_B=128 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=8 WIDTH_B=8 WIDTH_BYTEENA_A=1 WIDTHAD_A=7 WIDTHAD_B=7 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 data_a q_a q_b wren_a

--VERSION_BEGIN 4.2 cbx_altsyncram 2004:11:16:15:31:02:SJ cbx_cycloneii 2004:08:25:19:39:42:SJ cbx_lpm_add_sub 2004:10:25:10:56:48:SJ cbx_lpm_compare 2004:10:18:11:29:46:SJ cbx_lpm_decode 2004:08:15:21:16:20:SJ cbx_lpm_mux 2004:08:15:21:16:24:SJ cbx_mgl 2004:10:26:10:32:18:SJ cbx_stratix 2004:09:23:18:28:34:SJ cbx_stratixii 2004:08:10:15:01:36:SJ cbx_util_mgl 2004:09:29:16:04:00:SJ VERSION_END

-- Copyright (C) 1988-2002 Altera Corporation

-- Any megafunction design, and related netlist (encrypted or decrypted),

-- support information, device programming or simulation file, and any other

-- associated documentation or information provided by Altera or a partner

-- under Altera's Megafunction Partnership Program may be used only

-- to program PLD devices (but not masked PLD devices) from Altera. Any

-- other use of such megafunction design, netlist, support information,

-- device programming or simulation file, or any other related documentation

-- or information is prohibited for any other purpose, including, but not

-- limited to modification, reverse engineering, de-compiling, or use with

-- any other silicon devices, unless such use is explicitly licensed under

-- a separate agreement with Altera or a megafunction partner. Title to the

-- intellectual property, including patents, copyrights, trademarks, trade

-- secrets, or maskworks, embodied in any such megafunction design, netlist,

-- support information, device programming or simulation file, or any other

-- related documentation or information provided by Altera or a megafunction

-- partner, remains with Altera, the megafunction partner, or their respective

-- licensors. No other licenses, including any licenses needed under any third

-- party's intellectual property, are provided herein.

PARAMETERS

(

PORT_A_ADDRESS_WIDTH = 1,

PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,

PORT_A_DATA_WIDTH = 1,

PORT_B_ADDRESS_WIDTH = 1,

PORT_B_BYTE_ENABLE_MASK_WIDTH = 1,

PORT_B_DATA_WIDTH = 1

);

FUNCTION cyclone_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbrewe)

WITH ( CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH, PORT_A_BYTE_ENABLE_CLEAR, PORT_A_BYTE_ENABLE_MASK_WIDTH, PORT_A_DATA_IN_CLEAR, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_WRITE_ENABLE_CLEAR, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH, PORT_B_BYTE_ENABLE_CLEAR, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH, PORT_B_DATA_IN_CLEAR, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_ENABLE_WRITE_ENABLE_CLEAR, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE)

RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);

--synthesis_resources = M4K 1

SUBDESIGN altsyncram_hg91

(

address_a[6..0] : input;

address_b[6..0] : input;

clock0 : input;

data_a[7..0] : input;

q_a[7..0] : output;

q_b[7..0] : output;

wren_a : input;

)

VARIABLE

ram_block1a0 : cyclone_ram_block

WITH (

CONNECTIVITY_CHECKING = "OFF",

LOGICAL_RAM_NAME = "ALTSYNCRAM",

MIXED_PORT_FEED_THROUGH_MODE = "dont_care",

OPERATION_MODE = "dual_port",

PORT_A_ADDRESS_CLEAR = "none",

PORT_A_ADDRESS_WIDTH = 7,

PORT_A_DATA_IN_CLEAR = "none",

PORT_A_DATA_WIDTH = 1,

PORT_A_FIRST_ADDRESS = 0,

PORT_A_FIRST_BIT_NUMBER = 0,

PORT_A_LAST_ADDRESS = 127,

PORT_A_LOGICAL_RAM_DEPTH = 128,

PORT_A_LOGICAL_RAM_WIDTH = 8,

PORT_A_WRITE_ENABLE_CLEAR = "none",

PORT_B_ADDRESS_CLEAR = "none",

PORT_B_ADDRESS_CLOCK = "clock0",

PORT_B_ADDRESS_WIDTH = 7,

PORT_B_DATA_WIDTH = 1,

PORT_B_FIRST_ADDRESS = 0,

PORT_B_FIRST_BIT_NUMBER = 0,

PORT_B_LAST_ADDRESS = 127,

PORT_B_LOGICAL_RAM_DEPTH = 128,

PORT_B_LOGICAL_RAM_WIDTH = 8,

PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",

RAM_BLOCK_TYPE = "auto"

);

ram_block1a1 : cyclone_ram_block

WITH (

CONNECTIVITY_CHECKING = "OFF",

LOGICAL_RAM_NAME = "ALTSYNCRAM",

MIXED_PORT_FEED_THROUGH_MODE = "dont_care",

OPERATION_MODE = "dual_port",

PORT_A_ADDRESS_CLEAR = "none",

PORT_A_ADDRESS_WIDTH = 7,

PORT_A_DATA_IN_CLEAR = "none",

PORT_A_DATA_WIDTH = 1,

PORT_A_FIRST_ADDRESS = 0,

PORT_A_FIRST_BIT_NUMBER = 1,

PORT_A_LAST_ADDRESS = 127,

PORT_A_LOGICAL_RAM_DEPTH = 128,

PORT_A_LOGICAL_RAM_WIDTH = 8,

PORT_A_WRITE_ENABLE_CLEAR = "none",

PORT_B_ADDRESS_CLEAR = "none",

PORT_B_ADDRESS_CLOCK = "clock0",

PORT_B_ADDRESS_WIDTH = 7,

PORT_B_DATA_WIDTH = 1,

PORT_B_FIRST_ADDRESS = 0,

PORT_B_FIRST_BIT_NUMBER = 1,

PORT_B_LAST_ADDRESS = 127,

PORT_B_LOGICAL_RAM_DEPTH = 128,

PORT_B_LOGICAL_RAM_WIDTH = 8,

PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",

RAM_BLOCK_TYPE = "auto"

);

ram_block1a2 : cyclone_ram_block

WITH (

CONNECTIVITY_CHECKING = "OFF",

LOGICAL_RAM_NAME = "ALTSYNCRAM",

MIXED_PORT_FEED_THROUGH_MODE = "dont_care",

OPERATION_MODE = "dual_port",

PORT_A_ADDRESS_CLEAR = "none",

PORT_A_ADDRESS_WIDTH = 7,

PORT_A_DATA_IN_CLEAR = "none",

PORT_A_DATA_WIDTH = 1,

PORT_A_FIRST_ADDRESS = 0,

PORT_A_FIRST_BIT_NUMBER = 2,

PORT_A_LAST_ADDRESS = 127,

PORT_A_LOGICAL_RAM_DEPTH = 128,

PORT_A_LOGICAL_RAM_WIDTH = 8,

PORT_A_WRITE_ENABLE_CLEAR = "none",

PORT_B_ADDRESS_CLEAR = "none",

PORT_B_ADDRESS_CLOCK = "clock0",

PORT_B_ADDRESS_WIDTH = 7,

PORT_B_DATA_WIDTH = 1,

PORT_B_FIRST_ADDRESS = 0,

PORT_B_FIRST_BIT_NUMBER = 2,

PORT_B_LAST_ADDRESS = 127,

PORT_B_LOGICAL_RAM_DEPTH = 128,

PORT_B_LOGICAL_RAM_WIDTH = 8,

PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",

RAM_BLOCK_TYPE = "auto"

);

ram_block1a3 : cyclone_ram_block

WITH (

CONNECTIVITY_CHECKING = "OFF",

LOGICAL_RAM_NAME = "ALTSYNCRAM",

MIXED_PORT_FEED_THROUGH_MODE = "dont_care",

OPERATION_MODE = "dual_port",

PORT_A_ADDRESS_CLEAR = "none",

PORT_A_ADDRESS_WIDTH = 7,

PORT_A_DATA_IN_CLEAR = "none",

PORT_A_DATA_WIDTH = 1,

PORT_A_FIRST_ADDRESS = 0,

PORT_A_FIRST_BIT_NUMBER = 3,

PORT_A_LAST_ADDRESS = 127,

PORT_A_LOGICAL_RAM_DEPTH = 128,

PORT_A_LOGICAL_RAM_WIDTH = 8,

PORT_A_WRITE_ENABLE_CLEAR = "none",

PORT_B_ADDRESS_CLEAR = "none",

PORT_B_ADDRESS_CLOCK = "clock0",

PORT_B_ADDRESS_WIDTH = 7,

PORT_B_DATA_WIDTH = 1,

PORT_B_FIRST_ADDRESS = 0,

PORT_B_FIRST_BIT_NUMBER = 3,

PORT_B_LAST_ADDRESS = 127,

PORT_B_LOGICAL_RAM_DEPTH = 128,

PORT_B_LOGICAL_RAM_WIDTH = 8,

PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",

RAM_BLOCK_TYPE = "auto"

);

ram_block1a4 : cyclone_ram_block

WITH (

CONNECTIVITY_CHECKING = "OFF",

LOGICAL_RAM_NAME = "ALTSYNCRAM",

MIXED_PORT_FEED_THROUGH_MODE = "dont_care",

OPERATION_MODE = "dual_port",

PORT_A_ADDRESS_CLEAR = "none",

PORT_A_ADDRESS_WIDTH = 7,

PORT_A_DATA_IN_CLEAR = "none",

PORT_A_DATA_WIDTH = 1,

PORT_A_FIRST_ADDRESS = 0,

PORT_A_FIRST_BIT_NUMBER = 4,

PORT_A_LAST_ADDRESS = 127,

PORT_A_LOGICAL_RAM_DEPTH = 128,

PORT_A_LOGICAL_RAM_WIDTH = 8,

PORT_A_WRITE_ENABLE_CLEAR = "none",

PORT_B_ADDRESS_CLEAR = "none",

PORT_B_ADDRESS_CLOCK = "clock0",

PORT_B_ADDRESS_WIDTH = 7,

PORT_B_DATA_WIDTH = 1,

PORT_B_FIRST_ADDRESS = 0,

PORT_B_FIRST_BIT_NUMBER = 4,

PORT_B_LAST_ADDRESS = 127,

PORT_B_LOGICAL_RAM_DEPTH = 128,

PORT_B_LOGICAL_RAM_WIDTH = 8,

PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",

RAM_BLOCK_TYPE = "auto"

);

ram_block1a5 : cyclone_ram_block

WITH (

CONNECTIVITY_CHECKING = "OFF",

LOGICAL_RAM_NAME = "ALTSYNCRAM",

MIXED_PORT_FEED_THROUGH_MODE = "dont_care",

OPERATION_MODE = "dual_port",

PORT_A_ADDRESS_CLEAR = "none",

PORT_A_ADDRESS_WIDTH = 7,

PORT_A_DATA_IN_CLEAR = "none",

PORT_A_DATA_WIDTH = 1,

PORT_A_FIRST_ADDRESS = 0,

PORT_A_FIRST_BIT_NUMBER = 5,

PORT_A_LAST_ADDRESS = 127,

PORT_A_LOGICAL_RAM_DEPTH = 128,

PORT_A_LOGICAL_RAM_WIDTH = 8,

PORT_A_WRITE_ENABLE_CLEAR = "none",

PORT_B_ADDRESS_CLEAR = "none",

PORT_B_ADDRESS_CLOCK = "clock0",

PORT_B_ADDRESS_WIDTH = 7,

PORT_B_DATA_WIDTH = 1,

PORT_B_FIRST_ADDRESS = 0,

PORT_B_FIRST_BIT_NUMBER = 5,

PORT_B_LAST_ADDRESS = 127,

PORT_B_LOGICAL_RAM_DEPTH = 128,

PORT_B_LOGICAL_RAM_WIDTH = 8,

PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",

RAM_BLOCK_TYPE = "auto"

);

ram_block1a6 : cyclone_ram_block

WITH (

CONNECTIVITY_CHECKING = "OFF",

LOGICAL_RAM_NAME = "ALTSYNCRAM",

MIXED_PORT_FEED_THROUGH_MODE = "dont_care",

OPERATION_MODE = "dual_port",

PORT_A_ADDRESS_CLEAR = "none",

PORT_A_ADDRESS_WIDTH = 7,

PORT_A_DATA_IN_CLEAR = "none",

PORT_A_DATA_WIDTH = 1,

PORT_A_FIRST_ADDRESS = 0,

PORT_A_FIRST_BIT_NUMBER = 6,

PORT_A_LAST_ADDRESS = 127,

PORT_A_LOGICAL_RAM_DEPTH = 128,

PORT_A_LOGICAL_RAM_WIDTH = 8,

PORT_A_WRITE_ENABLE_CLEAR = "none",

PORT_B_ADDRESS_CLEAR = "none",

PORT_B_ADDRESS_CLOCK = "clock0",

PORT_B_ADDRESS_WIDTH = 7,

PORT_B_DATA_WIDTH = 1,

PORT_B_FIRST_ADDRESS = 0,

PORT_B_FIRST_BIT_NUMBER = 6,

PORT_B_LAST_ADDRESS = 127,

PORT_B_LOGICAL_RAM_DEPTH = 128,

PORT_B_LOGICAL_RAM_WIDTH = 8,

PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",

RAM_BLOCK_TYPE = "auto"

);

ram_block1a7 : cyclone_ram_block

WITH (

CONNECTIVITY_CHECKING = "OFF",

LOGICAL_RAM_NAME = "ALTSYNCRAM",

MIXED_PORT_FEED_THROUGH_MODE = "dont_care",

OPERATION_MODE = "dual_port",

PORT_A_ADDRESS_CLEAR = "none",

PORT_A_ADDRESS_WIDTH = 7,

PORT_A_DATA_IN_CLEAR = "none",

PORT_A_DATA_WIDTH = 1,

PORT_A_FIRST_ADDRESS = 0,

PORT_A_FIRST_BIT_NUMBER = 7,

PORT_A_LAST_ADDRESS = 127,

PORT_A_LOGICAL_RAM_DEPTH = 128,

PORT_A_LOGICAL_RAM_WIDTH = 8,

PORT_A_WRITE_ENABLE_CLEAR = "none",

PORT_B_ADDRESS_CLEAR = "none",

PORT_B_ADDRESS_CLOCK = "clock0",

PORT_B_ADDRESS_WIDTH = 7,

PORT_B_DATA_WIDTH = 1,

PORT_B_FIRST_ADDRESS = 0,

PORT_B_FIRST_BIT_NUMBER = 7,

PORT_B_LAST_ADDRESS = 127,

PORT_B_LOGICAL_RAM_DEPTH = 128,

PORT_B_LOGICAL_RAM_WIDTH = 8,

PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",

RAM_BLOCK_TYPE = "auto"

);

address_a_wire[6..0] : WIRE;

address_b_wire[6..0] : WIRE;

BEGIN

ram_block1a[7..0].clk0 = clock0;

ram_block1a[0].portaaddr[] = ( address_a_wire[6..0]);

ram_block1a[1].portaaddr[] = ( address_a_wire[6..0]);

ram_block1a[2].portaaddr[] = ( address_a_wire[6..0]);

ram_block1a[3].portaaddr[] = ( address_a_wire[6..0]);

ram_block1a[4].portaaddr[] = ( address_a_wire[6..0]);

ram_block1a[5].portaaddr[] = ( address_a_wire[6..0]);

ram_block1a[6].portaaddr[] = ( address_a_wire[6..0]);

ram_block1a[7].portaaddr[] = ( address_a_wire[6..0]);

ram_block1a[0].portadatain[] = ( data_a[0..0]);

ram_block1a[1].portadatain[] = ( data_a[1..1]);

ram_block1a[2].portadatain[] = ( data_a[2..2]);

ram_block1a[3].portadatain[] = ( data_a[3..3]);

ram_block1a[4].portadatain[] = ( data_a[4..4]);

ram_block1a[5].portadatain[] = ( data_a[5..5]);

ram_block1a[6].portadatain[] = ( data_a[6..6]);

ram_block1a[7].portadatain[] = ( data_a[7..7]);

ram_block1a[7..0].portawe = wren_a;

ram_block1a[0].portbaddr[] = ( address_b_wire[6..0]);

ram_block1a[1].portbaddr[] = ( address_b_wire[6..0]);

ram_block1a[2].portbaddr[] = ( address_b_wire[6..0]);

ram_block1a[3].portbaddr[] = ( address_b_wire[6..0]);

ram_block1a[4].portbaddr[] = ( address_b_wire[6..0]);

ram_block1a[5].portbaddr[] = ( address_b_wire[6..0]);

ram_block1a[6].portbaddr[] = ( address_b_wire[6..0]);

ram_block1a[7].portbaddr[] = ( address_b_wire[6..0]);

ram_block1a[0].portbrewe = B"1";

ram_block1a[1].portbrewe = B"1";

ram_block1a[2].portbrewe = B"1";

ram_block1a[3].portbrewe = B"1";

ram_block1a[4].portbrewe = B"1";

ram_block1a[5].portbrewe = B"1";

ram_block1a[6].portbrewe = B"1";

ram_block1a[7].portbrewe = B"1";

address_a_wire[] = address_a[];

address_b_wire[] = address_b[];

q_b[] = ( ram_block1a[7].portbdataout[0..0], ram_block1a[6].portbdataout[0..0], ram_block1a[5].portbdataout[0..0], ram_block1a[4].portbdataout[0..0], ram_block1a[3].portbdataout[0..0], ram_block1a[2].portbdataout[0..0], ram_block1a[1].portbdataout[0..0], ram_block1a[0].portbdataout[0..0]);

END;

--VALID FILE

/trunk/QU2/db/ClaiRISC_core.(6).cnf.cdb

0,0 → 1,2

/trunk/QU2/db/ClaiRISC_core.(2).cnf.hdb

0,0 → 1,5

+ðf%�ž�éÄ¿³¥Ï$Iì{©I©*¥Š”ÊRr¥äHI“”ÝpŽ�²w°mv€-3º`ÇgÓ¬ðZJxÅ68—18×18›|^‰/ŽZ¶/�™$v•2›K™k,ʘ½

/trunk/QU2/db/ClaiRISC_core.map.qmsg

0,0 → 1,11

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}

{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" { } { } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 10 16:26:40 2008 " "Info: Processing started: Mon Mar 10 16:26:40 2008" { } { } 0} } { } 4}

{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off ClaiRISC -c ClaiRISC_core " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off ClaiRISC -c ClaiRISC_core" { } { } 0}

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../SYN/rev_1/ClaiRISC_core.vqm 7 7 " "Info: Found 7 design units, including 7 entities, in source file ../SYN/rev_1/ClaiRISC_core.vqm" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_Z1 " "Info: Found entity 1: altsyncram_Z1" { } { { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 30 21 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "2 ram128x8 " "Info: Found entity 2: ram128x8" { } { { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 75 16 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "3 wb_mem_man " "Info: Found entity 3: wb_mem_man" { } { { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 206 18 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "4 altsyncram_Z2 " "Info: Found entity 4: altsyncram_Z2" { } { { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 2731 21 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "5 rom128x12 " "Info: Found entity 5: rom128x12" { } { { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 2761 17 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "6 pram " "Info: Found entity 6: pram" { } { { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 2851 12 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "7 ClaiRISC_core " "Info: Found entity 7: ClaiRISC_core" { } { { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 2927 21 0 } } } 0} } { } 0}

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus42/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus42/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" { } { { "altsyncram.tdf" "" { Text "c:/altera/quartus42/libraries/megafunctions/altsyncram.tdf" 431 1 0 } } } 0} } { } 0}

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_hg91.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_hg91.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_hg91 " "Info: Found entity 1: altsyncram_hg91" { } { { "db/altsyncram_hg91.tdf" "" { Text "D:/LWRISC/QU2/db/altsyncram_hg91.tdf" 40 1 0 } } } 0} } { } 0}

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_u8r.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_u8r.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_u8r " "Info: Found entity 1: altsyncram_u8r" { } { { "db/altsyncram_u8r.tdf" "" { Text "D:/LWRISC/QU2/db/altsyncram_u8r.tdf" 40 1 0 } } } 0} } { } 0}

{ "Warning" "WCDB_CDB_FILE_NOT_FOUND" "D:/LWRISC/QU2/init_file.mif " "Warning: Can't find Memory Initialization File or Hexadecimal (Intel-Format) File D:/LWRISC/QU2/init_file.mif -- setting all initial values to 0" { } { } 0}

{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "8 " "Warning: Design contains 8 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "wb_din\[0\] " "Warning: No output dependent on input pin \"wb_din\[0\]\"" { } { { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 2938 21 0 } } } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "wb_din\[1\] " "Warning: No output dependent on input pin \"wb_din\[1\]\"" { } { { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 2938 21 0 } } } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "wb_din\[2\] " "Warning: No output dependent on input pin \"wb_din\[2\]\"" { } { { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 2938 21 0 } } } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "wb_din\[3\] " "Warning: No output dependent on input pin \"wb_din\[3\]\"" { } { { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 2938 21 0 } } } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "wb_din\[4\] " "Warning: No output dependent on input pin \"wb_din\[4\]\"" { } { { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 2938 21 0 } } } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "wb_din\[5\] " "Warning: No output dependent on input pin \"wb_din\[5\]\"" { } { { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 2938 21 0 } } } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "wb_din\[6\] " "Warning: No output dependent on input pin \"wb_din\[6\]\"" { } { { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 2938 21 0 } } } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "wb_din\[7\] " "Warning: No output dependent on input pin \"wb_din\[7\]\"" { } { { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 2938 21 0 } } } 0} } { } 0}

{ "Info" "ISCL_SCL_TM_SUMMARY" "305 " "Info: Implemented 305 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "26 " "Info: Implemented 26 input pins" { } { } 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" { } { } 0} { "Info" "ISCL_SCL_TM_LCELLS" "247 " "Info: Implemented 247 logic cells" { } { } 0} { "Info" "ISCL_SCL_TM_RAMS" "16 " "Info: Implemented 16 RAM segments" { } { } 0} } { } 0}

{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 10 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 10 16:26:47 2008 " "Info: Processing ended: Mon Mar 10 16:26:47 2008" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" { } { } 0} } { } 0}

/trunk/QU2/db/ClaiRISC_core.(8).cnf.cdb

0,0 → 1,11

/trunk/QU2/db/ClaiRISC_core.cmp.rdb

0,0 → 1,11

/trunk/QU2/db/ClaiRISC_core.(4).cnf.hdb

0,0 → 1,9

+ÔŽydÈQ`=ҧ̒1�í{E©£Ï&¦wÔ4ŠV"^±næõC�*•'‚l[$¸<„^Ýt…€åôÂYÛrK©£˜yR.}�/×/Úº£Gu?»)oéÙÍÕ̶¶#g͘¸Ë‰04#6J‰›ÞHSH£‚#KIï¬]!>†°VðÓ„� +2y- +˜�$a­:¯ýÉ…§~Å/oÂ5`V`9à3b…è…MBr¬ç¹•Ý ä¬D£NØä$;R,ù%|YOŠã™lÄHM¾Òß›ƒÏ¾ù¼òîì�“¯öå ø®ð;Å*4+Vñ'Ѫw/gPb=#ÁæE3é¬�Œù·óÆ +^Ä¿Tü�];s÷ÿÿx
ºÆÌl@,ÄÁî~ñ>þÎŽ!žþ@†gpÈ[!­Èk`%L@i¨’× ` ¤«_H|pH�§Ÿ{<�xÞàå°b $ó|]ƒƒÝ]!J”÷Š_ºW" +5Ï=È?4 >$2ªJEû£Îy°*N  +vG8,ØÙÃÕ×±¢'þ-PŠ�
d?ƒyº�âéæé \ No newline at end of file

/trunk/QU2/db/ClaiRISC_core.cmp.tdb

0,0 → 1,3

/trunk/QU2/db/ClaiRISC_core.(6).cnf.hdb

0,0 → 1,3

/trunk/QU2/db/ClaiRISC_core.(8).cnf.hdb

0,0 → 1,7

+õ�s3ƒ<ƒ�ã“ó‹RõÊ +s
ÿÿx
ºÆÌl@,ÄÁî~ñ>þÎŽ!žþ@†gpÈ[!­Èk`%L@i¨’× ` ¤«_H|pH�§Ÿ{<�xÞàå°bN$ó|]ƒƒÝ]!J”÷Š_ºW" +5Ï=È?4 >$2ªJEû£Îy°*V  +vG8,ØÙÃÕ×±¢'þ-PŠ�
d?ƒyº�âéæé \ No newline at end of file

/trunk/QU2/db/ClaiRISC_core.signalprobe.cdb

0,0 → 1,4

/trunk/QU2/db/ClaiRISC_core.icc

0,0 → 1,1541

EP1C6Q240C6

9.88119e-007

301

0 30 30 2126293 0 0 2 1 0 -1 -1

1 30 30 21262b2 0 0 18 0 0 -1 -1

2 30 30 21262d1 0 35 6 0 0 -1 -1

3 30 30 21262f0 0 34 21 0 0 -1 -1

4 30 30 212630f 0 8 0 0 0 -1 -1

5 30 30 212632e 0 24 0 1 0 -1 -1

6 30 30 212634d 0 30 21 2 0 -1 -1

7 30 30 212636c 0 35 20 0 0 -1 -1

8 30 30 bdf485e6 0 10 0 2 0 -1 -1

9 30 30 bdf48605 0 12 0 1 0 -1 -1

10 30 30 bdf48624 0 12 0 0 0 -1 -1

11 30 30 bdf48643 0 8 21 2 0 -1 -1

12 30 30 bdf48662 0 10 21 1 0 -1 -1

13 30 30 bdf48681 0 12 21 1 0 -1 -1

14 30 30 bdf486a0 0 12 21 2 0 -1 -1

15 30 30 bdf486bf 0 12 21 0 0 -1 -1

16 30 30 bdf4fa45 0 14 0 0 0 -1 -1

17 30 30 bdf4fa64 0 12 0 2 0 -1 -1

18 30 30 bdf4fa83 0 0 8 0 0 -1 -1

19 30 30 bdf4faa2 0 10 0 0 0 -1 -1

20 30 30 bdf4fac1 0 10 21 2 0 -1 -1

21 30 30 bdf4fae0 0 10 21 0 0 -1 -1

22 30 30 bdf4faff 0 0 14 2 0 -1 -1

23 30 30 bdf4fb1e 0 10 0 1 0 -1 -1

24 3 1 29c8b8f2 6394d94f 13 9 -1 0 24 0 fff8 0 0

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8a051183 2 258 230

3f7a936b 1 191 231

3f7a938a 1 192 231

a6106827 2 229 231

4c0d66af 2 229 231

3f7a93a9 1 193 232

3f7a93c8 1 194 232

a6106846 2 230 232

b3ee938e 2 230 232

3f7a93a9 1 193 233

3f7a93c8 1 194 233

a6106865 2 231 233

66e164df 2 231 233

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a6106884 2 232 234

5b2ad600 2 232 234

18122 0 40 235

791b9eba 0 41 235

20d123e5 0 42 235

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4451600d 0 44 235

1ba53 0 45 235

41476b9 0 188 235

18122 0 40 236

1871198f 0 259 236

18718dee 0 260 236

87f5bd4d 0 121 236

e721eff5 0 261 236

18122 0 40 237

b952203d 0 262 237

18122 0 40 239

88a1ac2b 1 239 239

1871198f 0 259 239

18718dee 0 260 239

18d44c01 0 143 239

18122 0 40 240

791b9ed9 0 47 240

20d123e6 0 48 240

4451d48b 0 49 240

4451602c 0 50 240

1ba53 0 45 240

41476b9 0 188 240

18122 0 40 241

b952205c 0 263 241

88a1ac4a 1 264 243

247172eb 1 265 243

f952c875 0 134 243

18122 0 40 244

ead887d0 1 266 244

20d11e53 0 198 244

b95294da 0 267 244

20d123e5 0 42 245

20d123e6 0 48 245

88a1ac69 1 268 246

2471730a 1 269 246

f952c875 0 134 246

18122 0 40 247

ead887ef 1 270 247

20d11e53 0 198 247

b95294f9 0 271 247

24717329 1 272 248

88a1ac88 1 273 248

9511184 0 135 248

18122 0 40 249

ead8880e 1 274 249

20d11e53 0 198 249

b9529518 0 275 249

88a1aca7 1 276 250

24717348 1 127 250

f952c875 0 134 250

18122 0 40 251

ead8882d 1 277 251

20d11e53 0 198 251

b9529537 0 278 251

24717367 1 128 252

88a1acc6 1 279 252

9511184 0 135 252

18122 0 40 253

ead8884c 1 280 253

20d11e53 0 198 253

b9529556 0 281 253

18122 0 40 254

c405c940 0 53 254

3ca35438 0 66 254

3f66c103 0 67 254

3f7c92d3 0 68 254

1ba53 0 45 254

41476b9 0 188 254

18122 0 40 255

88a1ace5 1 255 255

1871198f 0 259 255

18718dee 0 260 255

18d706f5 0 226 255

18122 0 40 256

b9522116 0 282 256

3f7a932d 1 189 258

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1ba53 0 45 259

133b1285 1 134 259

133b1247 1 197 259

2c64fafd 0 82 259

1ba53 0 45 260

133b1285 1 134 260

133b1247 1 197 260

2c64fafd 0 82 260

88a1ac0c 1 236 261

997e2732 1 97 261

a6b46993 0 283 261

4772e23 0 284 261

18122 0 40 264

18718dee 0 260 264

1871198f 0 259 264

18d44c20 0 206 264

55a2b85c 0 285 264

18122 0 40 265

4451604b 0 51 265

3529384f 0 52 265

1ba53 0 45 265

41476b9 0 188 265

18122 0 40 266

b952207b 0 286 266

18122 0 40 268

88a1ac69 1 268 268

1871198f 0 259 268

18718dee 0 260 268

18d4c09e 0 212 268

18122 0 40 269

c405c940 0 53 269

3ca35434 0 54 269

36de856c 0 55 269

36f4573c 0 56 269

1ba53 0 45 269

41476b9 0 188 269

18122 0 40 270

b952209a 0 287 270

18122 0 40 272

c405c940 0 53 272

3ca35435 0 57 272

3a4836c9 0 58 272

3a5e0899 0 59 272

1ba53 0 45 272

41476b9 0 188 272

18122 0 40 273

88a1ac88 1 273 273

1871198f 0 259 273

18718dee 0 260 273

18d5a97b 0 215 273

18122 0 40 274

b95220b9 0 288 274

18122 0 40 276

88a1aca7 1 276 276

1871198f 0 259 276

18718dee 0 260 276

18d706b7 0 218 276

18122 0 40 277

b95220d8 0 289 277

18122 0 40 279

88a1acc6 1 279 279

1871198f 0 259 279

18718dee 0 260 279

18d706d6 0 221 279

18122 0 40 280

b95220f7 0 290 280

4d9d00e1 0 291 283

c405c940 0 53 283

e8557a51 0 292 283

37b098b4 1 96 284

50608aa4 0 293 284

88a1ac4a 1 264 285

c0bd9d7b 1 294 285

c09d0fcd 0 295 285

37b098d3 1 87 291

37b09857 1 78 291

37b098b4 1 96 291

997e2732 1 97 291

e8557a4e 2 57 292

ed49f7b2 2 66 292

37b1572c 2 66 292

27cf33f4 2 179 293

60df3172 2 179 293

18122 0 40 294

65ffc8a4 0 148 294

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18d706d6 0 221 295

d985c6f 0 296 295

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d985c3f 0 297 295

87f5bd4d 0 121 296

18d44c01 0 143 296

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18d706b7 0 218 296

18d4c09e 0 212 297

18d5a97b 0 215 297

26

2126293 0

21262b2 1

21262d1 2

21262f0 3

212630f 4

212632e 5

212634d 6

212636c 7

4375b8fd 8

4375b91c 9

4375b93b 10

4375b95a 11

4375b979 12

4375b998 13

4375b9b7 14

4375b9d6 15

ab56e5dc 16

ab56e5fb 17

ab56e61a 18

ab56e639 19

ab56e658 20

ab56e677 21

ab56e696 22

ab56e6b5 23

dd306e2f 299

dabd5a23 300

2

20

4

/trunk/QU2/db/ClaiRISC_core.sld_design_entry_dsc.sci

0,0 → 1,2

+ÄÁΞñ.®Ážî~Ö}Ü5GÁrL @ÿÿ \ No newline at end of file

/trunk/QU2/db/ClaiRISC_core.hif

0,0 → 1,739

Version 4.2 Build 157 12/07/2004 SJ Full Version

32

1575

OFF

OFF

OFF

OFF

OFF

FV_OFF

VRSM_ON

VHSM_ON

RETIME_OFF

REMAP_OFF

-- Start Partition --

|

ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP

Off

ADV_NETLIST_OPT_SYNTH_GATE_RETIME

Off

STATE_MACHINE_PROCESSING

Auto

STRATIXII_OPTIMIZATION_TECHNIQUE

Balanced

CYCLONE_OPTIMIZATION_TECHNIQUE

Balanced

CYCLONEII_OPTIMIZATION_TECHNIQUE

Balanced

STRATIX_OPTIMIZATION_TECHNIQUE

Balanced

MAXII_OPTIMIZATION_TECHNIQUE

Balanced

----

-- End Partition --

# entity

ClaiRISC_core

# case_sensitive

# source_file

..|SYN|rev_1|ClaiRISC_core.vqm

1205137544

25

# storage

db|ClaiRISC_core.(0).cnf

db|ClaiRISC_core.(0).cnf

# end

# entity

wb_mem_man

# case_sensitive

# source_file

..|SYN|rev_1|ClaiRISC_core.vqm

1205137544

25

# storage

db|ClaiRISC_core.(1).cnf

db|ClaiRISC_core.(1).cnf

# end

# entity

ram128x8

# case_sensitive

# source_file

..|SYN|rev_1|ClaiRISC_core.vqm

1205137544

25

# storage

db|ClaiRISC_core.(2).cnf

db|ClaiRISC_core.(2).cnf

# end

# entity

altsyncram_Z1

# case_sensitive

# source_file

..|SYN|rev_1|ClaiRISC_core.vqm

1205137544

25

# storage

db|ClaiRISC_core.(3).cnf

db|ClaiRISC_core.(3).cnf

# end

# entity

altsyncram

# case_insensitive

# source_file

c:|altera|quartus42|libraries|megafunctions|altsyncram.tdf

1101745298

6

# storage

db|ClaiRISC_core.(4).cnf

db|ClaiRISC_core.(4).cnf

# user_parameter {

BYTE_SIZE_BLOCK

8

PARAMETER_UNKNOWN

DEF

AUTO_CARRY_CHAINS

ON

AUTO_CARRY

USR

IGNORE_CARRY_BUFFERS

OFF

IGNORE_CARRY

USR

AUTO_CASCADE_CHAINS

ON

AUTO_CASCADE

USR

IGNORE_CASCADE_BUFFERS

OFF

IGNORE_CASCADE

USR

OPERATION_MODE

DUAL_PORT

PARAMETER_UNKNOWN

USR

WIDTH_A

8

PARAMETER_UNKNOWN

USR

WIDTHAD_A

7

PARAMETER_UNKNOWN

USR

NUMWORDS_A

128

PARAMETER_UNKNOWN

USR

OUTDATA_REG_A

UNREGISTERED

PARAMETER_UNKNOWN

DEF

ADDRESS_ACLR_A

NONE

PARAMETER_UNKNOWN

USR

OUTDATA_ACLR_A

NONE

PARAMETER_UNKNOWN

DEF

WRCONTROL_ACLR_A

NONE

PARAMETER_UNKNOWN

USR

INDATA_ACLR_A

NONE

PARAMETER_UNKNOWN

USR

BYTEENA_ACLR_A

NONE

PARAMETER_UNKNOWN

DEF

WIDTH_B

8

PARAMETER_UNKNOWN

USR

WIDTHAD_B

7

PARAMETER_UNKNOWN

USR

NUMWORDS_B

128

PARAMETER_UNKNOWN

USR

INDATA_REG_B

CLOCK1

PARAMETER_UNKNOWN

DEF

WRCONTROL_WRADDRESS_REG_B

CLOCK1

PARAMETER_UNKNOWN

DEF

RDCONTROL_REG_B

CLOCK1

PARAMETER_UNKNOWN

DEF

ADDRESS_REG_B

CLOCK0

PARAMETER_UNKNOWN

USR

OUTDATA_REG_B

UNREGISTERED

PARAMETER_UNKNOWN

USR

BYTEENA_REG_B

CLOCK1

PARAMETER_UNKNOWN

DEF

INDATA_ACLR_B

NONE

PARAMETER_UNKNOWN

DEF

WRCONTROL_ACLR_B

NONE

PARAMETER_UNKNOWN

DEF

ADDRESS_ACLR_B

NONE

PARAMETER_UNKNOWN

USR

OUTDATA_ACLR_B

NONE

PARAMETER_UNKNOWN

USR

RDCONTROL_ACLR_B

NONE

PARAMETER_UNKNOWN

DEF

BYTEENA_ACLR_B

NONE

PARAMETER_UNKNOWN

DEF

WIDTH_BYTEENA_A

1

PARAMETER_UNKNOWN

USR

WIDTH_BYTEENA_B

1

PARAMETER_UNKNOWN

DEF

RAM_BLOCK_TYPE

AUTO

PARAMETER_UNKNOWN

DEF

BYTE_SIZE

8

PARAMETER_UNKNOWN

DEF

READ_DURING_WRITE_MODE_MIXED_PORTS

DONT_CARE

PARAMETER_UNKNOWN

USR

INIT_FILE

UNUSED

PARAMETER_UNKNOWN

DEF

INIT_FILE_LAYOUT

PORT_A

PARAMETER_UNKNOWN

DEF

MAXIMUM_DEPTH

PARAMETER_UNKNOWN

DEF

CLOCK_ENABLE_INPUT_A

NORMAL

PARAMETER_UNKNOWN

DEF

CLOCK_ENABLE_INPUT_B

NORMAL

PARAMETER_UNKNOWN

DEF

CLOCK_ENABLE_OUTPUT_A

NORMAL

PARAMETER_UNKNOWN

DEF

CLOCK_ENABLE_OUTPUT_B

NORMAL

PARAMETER_UNKNOWN

DEF

DEVICE_FAMILY

Cyclone

PARAMETER_UNKNOWN

USR

CBXI_PARAMETER

altsyncram_hg91

PARAMETER_UNKNOWN

USR

}

# used_port {

address_a

address_a

address_a

address_a

address_a

address_a

address_a

address_b

address_b

address_b

address_b

address_b

address_b

address_b

clock0

data_a

data_a

data_a

data_a

data_a

data_a

data_a

data_a

q_a

q_a

q_a

q_a

q_a

q_a

q_a

q_a

q_b

q_b

q_b

q_b

q_b

q_b

q_b

q_b

wren_a

}

# include_file {

c:|altera|quartus42|libraries|megafunctions|stratix_ram_block.inc

1094871114

c:|altera|quartus42|libraries|megafunctions|lpm_mux.inc

1094870318

c:|altera|quartus42|libraries|megafunctions|lpm_decode.inc

1094870100

c:|altera|quartus42|libraries|megafunctions|aglobal42.inc

1101745276

c:|altera|quartus42|libraries|megafunctions|altsyncram.inc

1094868954

c:|altera|quartus42|libraries|megafunctions|a_rdenreg.inc

1094867530

c:|altera|quartus42|libraries|megafunctions|altrom.inc

1094868876

c:|altera|quartus42|libraries|megafunctions|altram.inc

1094868838

c:|altera|quartus42|libraries|megafunctions|altdpram.inc

1094868494

c:|altera|quartus42|libraries|megafunctions|altqpram.inc

1094868820

}

# end

# entity

altsyncram_hg91

# case_insensitive

# source_file

db|altsyncram_hg91.tdf

1205137604

6

# storage

db|ClaiRISC_core.(5).cnf

db|ClaiRISC_core.(5).cnf

# user_parameter {

PORT_A_ADDRESS_WIDTH

1

PARAMETER_UNKNOWN

DEF

PORT_A_BYTE_ENABLE_MASK_WIDTH

1

PARAMETER_UNKNOWN

DEF

PORT_A_DATA_WIDTH

1

PARAMETER_UNKNOWN

DEF

PORT_B_ADDRESS_WIDTH

1

PARAMETER_UNKNOWN

DEF

PORT_B_BYTE_ENABLE_MASK_WIDTH

1

PARAMETER_UNKNOWN

DEF

PORT_B_DATA_WIDTH

1

PARAMETER_UNKNOWN

DEF

}

# used_port {

wren_a

data_a0

data_a1

data_a2

data_a3

data_a4

data_a5

data_a6

data_a7

address_a0

address_a1

address_a2

address_a3

address_a4

address_a5

address_a6

address_b0

address_b1

address_b2

address_b3

address_b4

address_b5

address_b6

clock0

q_a0

q_a1

q_a2

q_a3

q_a4

q_a5

q_a6

q_a7

q_b0

q_b1

q_b2

q_b3

q_b4

q_b5

q_b6

q_b7

}

# memory_file {

none

}

# end

# entity

pram

# case_sensitive

# source_file

..|SYN|rev_1|ClaiRISC_core.vqm

1205137544

25

# storage

db|ClaiRISC_core.(6).cnf

db|ClaiRISC_core.(6).cnf

# end

# entity

rom128x12

# case_sensitive

# source_file

..|SYN|rev_1|ClaiRISC_core.vqm

1205137544

25

# storage

db|ClaiRISC_core.(7).cnf

db|ClaiRISC_core.(7).cnf

# end

# entity

altsyncram_Z2

# case_sensitive

# source_file

..|SYN|rev_1|ClaiRISC_core.vqm

1205137544

25

# storage

db|ClaiRISC_core.(8).cnf

db|ClaiRISC_core.(8).cnf

# end

# entity

altsyncram

# case_insensitive

# source_file

c:|altera|quartus42|libraries|megafunctions|altsyncram.tdf

1101745298

6

# storage

db|ClaiRISC_core.(9).cnf

db|ClaiRISC_core.(9).cnf

# user_parameter {

BYTE_SIZE_BLOCK

8

PARAMETER_UNKNOWN

DEF

AUTO_CARRY_CHAINS

ON

AUTO_CARRY

USR

IGNORE_CARRY_BUFFERS

OFF

IGNORE_CARRY

USR

AUTO_CASCADE_CHAINS

ON

AUTO_CASCADE

USR

IGNORE_CASCADE_BUFFERS

OFF

IGNORE_CASCADE

USR

OPERATION_MODE

ROM

PARAMETER_UNKNOWN

USR

WIDTH_A

8

PARAMETER_UNKNOWN

USR

WIDTHAD_A

7

PARAMETER_UNKNOWN

USR

NUMWORDS_A

128

PARAMETER_UNKNOWN

USR

OUTDATA_REG_A

UNREGISTERED

PARAMETER_UNKNOWN

USR

ADDRESS_ACLR_A

NONE

PARAMETER_UNKNOWN

USR

OUTDATA_ACLR_A

NONE

PARAMETER_UNKNOWN

USR

WRCONTROL_ACLR_A

NONE

PARAMETER_UNKNOWN

DEF

INDATA_ACLR_A

NONE

PARAMETER_UNKNOWN

DEF

BYTEENA_ACLR_A

NONE

PARAMETER_UNKNOWN

DEF

WIDTH_B

1

PARAMETER_UNKNOWN

DEF

WIDTHAD_B

1

PARAMETER_UNKNOWN

DEF

NUMWORDS_B

1

PARAMETER_UNKNOWN

DEF

INDATA_REG_B

CLOCK1

PARAMETER_UNKNOWN

DEF

WRCONTROL_WRADDRESS_REG_B

CLOCK1

PARAMETER_UNKNOWN

DEF

RDCONTROL_REG_B

CLOCK1

PARAMETER_UNKNOWN

DEF

ADDRESS_REG_B

CLOCK1

PARAMETER_UNKNOWN

DEF

OUTDATA_REG_B

UNREGISTERED

PARAMETER_UNKNOWN

DEF

BYTEENA_REG_B

CLOCK1

PARAMETER_UNKNOWN

DEF

INDATA_ACLR_B

NONE

PARAMETER_UNKNOWN

DEF

WRCONTROL_ACLR_B

NONE

PARAMETER_UNKNOWN

DEF

ADDRESS_ACLR_B

NONE

PARAMETER_UNKNOWN

DEF

OUTDATA_ACLR_B

NONE

PARAMETER_UNKNOWN

DEF

RDCONTROL_ACLR_B

NONE

PARAMETER_UNKNOWN

DEF

BYTEENA_ACLR_B

NONE

PARAMETER_UNKNOWN

DEF

WIDTH_BYTEENA_A

1

PARAMETER_UNKNOWN

USR

WIDTH_BYTEENA_B

1

PARAMETER_UNKNOWN

DEF

RAM_BLOCK_TYPE

AUTO

PARAMETER_UNKNOWN

DEF

BYTE_SIZE

8

PARAMETER_UNKNOWN

DEF

READ_DURING_WRITE_MODE_MIXED_PORTS

DONT_CARE

PARAMETER_UNKNOWN

DEF

INIT_FILE

init_file.mif

PARAMETER_UNKNOWN

USR

INIT_FILE_LAYOUT

PORT_A

PARAMETER_UNKNOWN

DEF

MAXIMUM_DEPTH

PARAMETER_UNKNOWN

DEF

CLOCK_ENABLE_INPUT_A

NORMAL

PARAMETER_UNKNOWN

DEF

CLOCK_ENABLE_INPUT_B

NORMAL

PARAMETER_UNKNOWN

DEF

CLOCK_ENABLE_OUTPUT_A

NORMAL

PARAMETER_UNKNOWN

DEF

CLOCK_ENABLE_OUTPUT_B

NORMAL

PARAMETER_UNKNOWN

DEF

DEVICE_FAMILY

Cyclone

PARAMETER_UNKNOWN

USR

CBXI_PARAMETER

altsyncram_u8r

PARAMETER_UNKNOWN

USR

}

# used_port {

address_a

address_a

address_a

address_a

address_a

address_a

address_a

clock0

q_a

q_a

q_a

q_a

q_a

q_a

q_a

q_a

q_b

}

# include_file {

c:|altera|quartus42|libraries|megafunctions|stratix_ram_block.inc

1094871114

c:|altera|quartus42|libraries|megafunctions|lpm_mux.inc

1094870318

c:|altera|quartus42|libraries|megafunctions|lpm_decode.inc

1094870100

c:|altera|quartus42|libraries|megafunctions|aglobal42.inc

1101745276

c:|altera|quartus42|libraries|megafunctions|altsyncram.inc

1094868954

c:|altera|quartus42|libraries|megafunctions|a_rdenreg.inc

1094867530

c:|altera|quartus42|libraries|megafunctions|altrom.inc

1094868876

c:|altera|quartus42|libraries|megafunctions|altram.inc

1094868838

c:|altera|quartus42|libraries|megafunctions|altdpram.inc

1094868494

c:|altera|quartus42|libraries|megafunctions|altqpram.inc

1094868820

}

# end

# entity

altsyncram_u8r

# case_insensitive

# source_file

db|altsyncram_u8r.tdf

1205137606

6

# storage

db|ClaiRISC_core.(10).cnf

db|ClaiRISC_core.(10).cnf

# user_parameter {

PORT_A_ADDRESS_WIDTH

1

PARAMETER_UNKNOWN

DEF

PORT_A_BYTE_ENABLE_MASK_WIDTH

1

PARAMETER_UNKNOWN

DEF

PORT_A_DATA_WIDTH

1

PARAMETER_UNKNOWN

DEF

PORT_B_ADDRESS_WIDTH

1

PARAMETER_UNKNOWN

DEF

PORT_B_BYTE_ENABLE_MASK_WIDTH

1

PARAMETER_UNKNOWN

DEF

PORT_B_DATA_WIDTH

1

PARAMETER_UNKNOWN

DEF

}

# used_port {

address_a0

address_a1

address_a2

address_a3

address_a4

address_a5

address_a6

clock0

q_a0

q_a1

q_a2

q_a3

q_a4

q_a5

q_a6

q_a7

q_b0

}

# memory_file {

init_file.mif

}

# end

# complete

/trunk/QU2/db/ClaiRISC_core.(1).cnf.cdb

0,0 → 1,739