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/nextz80/trunk/NextZ80Reg.v
1,7 → 1,7
//////////////////////////////////////////////////////////////////////////////////
//
// This file is part of the NextZ80 project
// http://www.opencores.org/cores/nextz80/
// This file is part of the NextZ80 project
// http://www.opencores.org/cores/nextz80/
//
// Filename: NextZ80Regs.v
// Description: Implementation of Z80 compatible CPU - registers
10,32 → 10,32
//
// Author: Nicolae Dumitrache
// e-mail: ndumitrache@opencores.org
//
/////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2011 Nicolae Dumitrache
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//
/////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2011 Nicolae Dumitrache
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//
///////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
 
82,25 → 82,25
reg [15:0]mux_rdor; // (3)A reversed mixed with TL, (4)I mixed with R (5)SP
//------------------------------------ RAM block registers ----------------------------------
// 0:BC, 1:DE, 2:HL, 3:A-x, 4:I-x, 5:IX, 6:IY, 7:x-x, 8:BC', 9:DE', 10:HL', 11:A'-x, 12: tmpSP, 13:zero
RAM16X8D_regs regs_lo (
.DPO(rdor[7:0]), // Read-only data output
.SPO(rdow[7:0]), // R/W data output
.A(SELW), // R/W address
.D(DIN[7:0]), // Write data input
.DPRA(SELR), // Read-only address
.WCLK(CLK), // Write clock input
.WE(WE[0] & !WAIT) // Write enable input
// 0:BC, 1:DE, 2:HL, 3:A-x, 4:I-x, 5:IX, 6:IY, 7:x-x, 8:BC', 9:DE', 10:HL', 11:A'-x, 12: tmpSP, 13:zero
RAM16X8D_regs regs_lo (
.DPO(rdor[7:0]), // Read-only data output
.SPO(rdow[7:0]), // R/W data output
.A(SELW), // R/W address
.D(DIN[7:0]), // Write data input
.DPRA(SELR), // Read-only address
.WCLK(CLK), // Write clock input
.WE(WE[0] & !WAIT) // Write enable input
);
 
RAM16X8D_regs regs_hi (
.DPO(rdor[15:8]), // Read-only data output
.SPO(rdow[15:8]), // R/W data output
.A(SELW), // R/W address
.D(DIN[15:8]), // Write data input
.DPRA(SELR), // Read-only address
.WCLK(CLK), // Write clock input
.WE(WE[1] & !WAIT) // Write enable input
RAM16X8D_regs regs_hi (
.DPO(rdor[15:8]), // Read-only data output
.SPO(rdow[15:8]), // R/W data output
.A(SELW), // R/W address
.D(DIN[15:8]), // Write data input
.DPRA(SELR), // Read-only address
.WCLK(CLK), // Write clock input
.WE(WE[1] & !WAIT) // Write enable input
);
 
wire [15:0]ADDR1 = ADDR + !ALU16OP[2]; // address post increment
179,14 → 179,14
end
endmodule
 
module RAM16X8D_regs(
output [7:0]DPO, // Read-only data output
output [7:0]SPO, // R/W data output
input [3:0]A, // R/W address
input [7:0]D, // Write data input
input [3:0]DPRA, // Read-only address
input WCLK, // Write clock
input [1:0]WE // Write enable
module RAM16X8D_regs(
output [7:0]DPO, // Read-only data output
output [7:0]SPO, // R/W data output
input [3:0]A, // R/W address
input [7:0]D, // Write data input
input [3:0]DPRA, // Read-only address
input WCLK, // Write clock
input WE // Write enable
);
reg [7:0]data[15:0];

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