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URL https://opencores.org/ocsvn/ppx16/ppx16/trunk

Subversion Repositories ppx16

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  • This comparison shows the changes necessary to convert path 
    /
    from Rev 9 to Rev 10
    ↔ Reverse comparison
  •

Rev 9 → Rev 10

/trunk/rtl/vhdl/P16C55.vhd
93,6 → 93,7
signal Tris_A_Wr : std_logic;
signal Tris_B_Wr : std_logic;
signal Tris_C_Wr : std_logic;
signal RAM_Data : std_logic_vector(7 downto 0);
signal Op_Bus : std_logic_vector(7 downto 0);
signal Res_Bus : std_logic_vector(7 downto 0);
signal OPTION : std_logic_vector(5 downto 0);
137,6 → 138,7
File_CS(7) <= '1' when to_integer(unsigned(File_Addr_r(4 downto 0))) = 7 else '0';
 
-- Register File
Op_Bus <= RAM_Data when RAM_CS = '1' and File_Rd = '1' ELSE "ZZZZZZZZ";
pr : PPX_RAM
generic map(Bottom => 8, Top => 31, AddrWidth => 5)
port map(
143,10 → 145,9
Clk => Clk,
CS => RAM_CS,
Wr => File_Wr,
Rd => File_Rd,
Addr => File_Addr(4 downto 0),
Data_In => Res_Bus,
Data_Out => Op_Bus);
Data_Out => RAM_Data);
 
-- Option Register
process (Clk)
/trunk/rtl/vhdl/PPX_Pack.vhd
1,7 → 1,7
--
-- PIC16xx compatible microcontroller core
--
-- Version : 0220
-- Version : 0221
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
151,7 → 151,6
Clk : in std_logic;
CS : in std_logic;
Wr : in std_logic;
Rd : in std_logic;
Addr : in std_logic_vector(AddrWidth - 1 downto 0);
Data_In : in std_logic_vector(7 downto 0);
Data_Out : out std_logic_vector(7 downto 0)
/trunk/rtl/vhdl/PPX_RAM.vhd
1,7 → 1,7
--
-- PIC16xx compatible microcontroller core
--
-- Version : 0146
-- Version : 0221
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
61,7 → 61,6
Clk : in std_logic;
CS : in std_logic;
Wr : in std_logic;
Rd : in std_logic;
Addr : in std_logic_vector(AddrWidth - 1 downto 0);
Data_In : in std_logic_vector(7 downto 0);
Data_Out : out std_logic_vector(7 downto 0)
70,9 → 69,10
 
architecture rtl of PPX_RAM is
 
type RAM_Image is array (Top downto Bottom) of std_logic_vector(7 downto 0);
type RAM_Image is array (Top downto 0) of std_logic_vector(7 downto 0);
signal RAM : RAM_Image;
signal AddrReg : std_logic_vector(AddrWidth - 1 downto 0);
signal AddrRd : std_logic_vector(AddrWidth - 1 downto 0);
signal AddrWr : std_logic_vector(AddrWidth - 1 downto 0);
signal Tmp_Data : std_logic_vector(7 downto 0);
 
begin
80,23 → 80,18
process (Clk)
begin
if Clk'event and Clk = '1' then
AddrReg <= Addr;
-- pragma translate_off
if to_integer(unsigned(Addr)) >= Bottom and to_integer(unsigned(Addr)) <= Top then
-- pragma translate_on
Tmp_Data <= RAM(to_integer(unsigned(Addr)));
-- pragma translate_off
end if;
-- pragma translate_on
AddrRd <= Addr;
AddrWr <= Addr;
if CS = '1' and Wr = '1' then
RAM(to_integer(unsigned(AddrReg))) <= Data_In;
if AddrReg = Addr then
Tmp_Data <= Data_In;
end if;
RAM(to_integer(unsigned(AddrWr))) <= Data_In;
end if;
end if;
end process;
 
Data_Out <= Tmp_Data when CS = '1' and Rd = '1' ELSE "ZZZZZZZZ";
Data_Out <= RAM(to_integer(unsigned(AddrRd)))
-- pragma translate_off
when to_integer(unsigned(Addr)) >= Bottom and to_integer(unsigned(Addr)) <= Top else "--------"
-- pragma translate_on
;
 
end;
/trunk/rtl/vhdl/P16F84.vhd
95,6 → 95,7
signal Tris_A_Wr : std_logic;
signal Tris_B_Rd : std_logic;
signal Tris_B_Wr : std_logic;
signal RAM_Data : std_logic_vector(7 downto 0);
signal Op_Bus : std_logic_vector(7 downto 0);
signal Res_Bus : std_logic_vector(7 downto 0);
signal OPTION : std_logic_vector(7 downto 0);
142,6 → 143,7
TMR_CS <= '1' when to_integer(unsigned(File_Addr_r(7 downto 0))) = 1 else '0';
 
-- Register File
Op_Bus <= RAM_Data when RAM_CS = '1' and File_Rd = '1' else "ZZZZZZZZ";
pr : PPX_RAM
generic map(Bottom => 12, Top => 79, AddrWidth => 7)
port map(
148,10 → 150,9
Clk => Clk,
CS => RAM_CS,
Wr => File_Wr,
Rd => File_Rd,
Addr => File_Addr(6 downto 0),
Data_In => Res_Bus,
Data_Out => Op_Bus);
Data_Out => RAM_Data);
 
-- Option Register
Op_Bus <= OPTION when

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