Subversion Repositories wb_prefetch_spram

trunk/sim/rtl_sim/bin/sim.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/bench/verilog/tb_defines.v =================================================================== --- trunk/bench/verilog/tb_defines.v (revision 9) +++ trunk/bench/verilog/tb_defines.v (nonexistent) @@ -1,76 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Test Bench Definitions //// -//// //// -//// This file is part of the WISHBONE prefetch memory block: //// -//// http://www.opencores.org/cvsweb.shtml/wb_prefetch_spram/ //// -//// //// -//// Description //// -//// Test bench definitions. //// -//// //// -//// To Do: //// -//// Nothing //// -//// //// -//// Author(s): //// -//// - Damjan Lampret, lampret@opencores.org //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: not supported by cvs2svn $ -// Revision 1.2 2001/07/30 05:38:02 lampret -// Adding empty directories required by HDL coding guidelines -// -// - -// -// Half of clock period -// -`define Thper 5 - -// -// Reset time -// -`define Trst (`Thper*2+1) - -// -// Number of words in RAM -// -`define RAM_ADDRWIDTH 12 -`define RAM_WORDS (2<<`RAM_ADDRWIDTH) - -// -// RAM data width -// -`define RAM_DATAWIDTH 32 - -// -// Define to get VCD output -// -`define VCD_DUMP Index: trunk/bench/verilog/wb_master.v =================================================================== --- trunk/bench/verilog/wb_master.v (revision 9) +++ trunk/bench/verilog/wb_master.v (nonexistent) @@ -1,313 +0,0 @@ -`include "timescale.v" - -// -*- Mode: Verilog -*- -// Filename : wb_master.v -// Description : Wishbone Master Behavorial -// Author : Winefred Washington -// Created On : Thu Jan 11 21:18:41 2001 -// Last Modified By: . -// Last Modified On: . -// Update Count : 0 -// Status : Unknown, Use with caution! - -// Description Specification -// General Description: 8, 16, 32-bit WISHBONE Master -// Supported cycles: MASTER, READ/WRITE -// MASTER, BLOCK READ/WRITE -// MASTER, RMW -// Data port, size: 8, 16, 32-bit -// Data port, granularity 8-bit -// Data port, Max. operand size 32-bit -// Data transfer ordering: little endian -// Data transfer sequencing: undefined -// - -module wb_master(CLK_I, RST_I, TAG_I, TAG_O, - ACK_I, ADR_O, CYC_O, DAT_I, DAT_O, ERR_I, RTY_I, SEL_O, STB_O, WE_O); - -parameter aw = 16; -parameter dw = 32; - - input CLK_I; - input RST_I; - input [3:0] TAG_I; - output [3:0] TAG_O; - input ACK_I; - output [aw-1:0] ADR_O; - output CYC_O; - input [dw-1:0] DAT_I; - output [dw-1:0] DAT_O; - input ERR_I; - input RTY_I; - output [3:0] SEL_O; - output STB_O; - output WE_O; - - reg [aw-1:0] ADR_O; - reg [3:0] SEL_O; - reg CYC_O; - reg STB_O; - reg WE_O; - reg [dw-1:0] DAT_O; - - wire [15:0] mem_sizes; // determines the data width of an address range - reg [31:0] write_burst_buffer[0:7]; - reg [31:0] read_burst_buffer[0:7]; - - reg GO; - integer cycle_end; - integer address; - integer data; - integer selects; - integer write_flag; - - // - // mem_sizes determines the data widths of memory space - // The memory space is divided into eight regions. Each - // region is controlled by a two bit field. - // - // Bits - // 00 = 8 bit memory space - // 01 = 16 bit - // 10 = 32 bit - // 11 = 64 bit (not supported in this model - // - - assign mem_sizes = 16'b10_10_10_10_10_10_10_10; - - function [1:0] data_width; - input [31:0] adr; - begin - casex (adr[31:29]) - 3'b000: data_width = mem_sizes[15:14]; - 3'b001: data_width = mem_sizes[13:12]; - 3'b010: data_width = mem_sizes[11:10]; - 3'b011: data_width = mem_sizes[9:8]; - 3'b100: data_width = mem_sizes[7:6]; - 3'b101: data_width = mem_sizes[5:4]; - 3'b110: data_width = mem_sizes[3:2]; - 3'b111: data_width = mem_sizes[1:0]; - 3'bxxx: data_width = 2'bxx; - endcase // casex (adr[31:29]) - end - endfunction - - always @(posedge CLK_I or posedge RST_I) - begin - if (RST_I) - begin - GO = 1'b0; - end - end - - // read single - task rd; - input [31:0] adr; - output [31:0] result; - - begin - #1; - cycle_end = 1; - address = adr; - selects = 255; - write_flag = 0; - - GO <= 1; -// @(posedge CLK_I); -// GO <= 0; // DL - - // wait for cycle to start - while (~CYC_O) - @(posedge CLK_I); - - // wait for cycle to end - while (CYC_O) - @(posedge CLK_I); - - result = data; -// $display(" Reading %h from address %h", result, address); - - end - endtask // read - - task wr; - input [31:0] adr; - input [31:0] dat; - input [3:0] sel; - begin - #1; - cycle_end = 1; - address = adr; - selects = sel; - write_flag = 1; - data = dat; - - GO <= 1; -// @(posedge CLK_I); -// GO <= 0; // DL - - // wait for cycle to start - while (~CYC_O) - @(posedge CLK_I); - - // wait for cycle to end - while (CYC_O) - @(posedge CLK_I); -// $display(" Writing %h to address %h", data, address); - - end - endtask // wr - - // block read - task blkrd; - input [31:0] adr; - input end_flag; - output [31:0] result; - - begin - #1; - write_flag = 0; - cycle_end = end_flag; - address = adr; - GO <= 1; -// @(posedge CLK_I); -// GO <= 0; // DL - - while (~(ACK_I & STB_O)) - @(posedge CLK_I); - - result = data; - end - endtask // blkrd - - // block write - task blkwr; - input [31:0] adr; - input [31:0] dat; - input [3:0] sel; - input end_flag; - begin - #1; - write_flag = 1; - cycle_end = end_flag; - address = adr; - data = dat; - selects = sel; - GO <= 1; -// @(posedge CLK_I); -// GO <= 0; // DL - - while (~(ACK_I & STB_O)) - @(posedge CLK_I); - - end - endtask // blkwr - - // RMW - task rmw; - input [31:0] adr; - input [31:0] dat; - input [3:0] sel; - output [31:0] result; - - begin - // read phase - write_flag = 0; - cycle_end = 0; - address = adr; - GO <= 1; - @(posedge CLK_I); - GO <= 0; // DL - - while (~(ACK_I & STB_O)) - @(posedge CLK_I); - - result = data; - - // write phase - write_flag = 1; - address = adr; - selects = sel; - GO <= 1; - data <= dat; - cycle_end <= 1; - @(posedge CLK_I); - GO <= 0; // DL - - while (~(ACK_I & STB_O)) - @(posedge CLK_I); - - end - endtask // rmw - - always @(posedge CLK_I) - begin - if (RST_I) - ADR_O <= {aw{1'b0}}; - else - ADR_O <= #1 address[aw-1:0]; - end - - always @(posedge CLK_I) - begin - if (RST_I | ERR_I | RTY_I) - CYC_O <= #1 1'b0; - else if ((cycle_end == 1) & ACK_I) - CYC_O <= #1 1'b0; - else if (GO | CYC_O) begin - CYC_O <= #1 1'b1; - GO <= 1'b0; - end - end - - // stb control - always @(posedge CLK_I) - begin - if (RST_I | ERR_I | RTY_I) - STB_O <= #1 1'b0; - else if (STB_O & ACK_I) - STB_O <= #1 1'b0; - else if (GO | STB_O) - STB_O <= #1 1'b1; - end - - // selects & data - always @(posedge CLK_I) - begin - if (write_flag == 0) begin - SEL_O <= #1 4'b1111; - if (STB_O & ACK_I) - data <= #1 DAT_I; - end - else begin - case (data_width(address)) - 2'b00: begin - SEL_O <= #1 {3'b000, selects[0]}; - DAT_O <= #1 {data[7:0], data[7:0], data[7:0], data[7:0]}; - end - 2'b01: begin - SEL_O <= #1 {2'b00, selects[1:0]}; - DAT_O <= #1 {data[15:0], data[15:0]}; - end - 2'b10: begin - SEL_O <= #1 selects; - DAT_O <= #1 data[dw-1:0]; - end - endcase - end - end - - always @(posedge CLK_I) - begin - if (RST_I) - WE_O <= 1'b0; - else if (GO) - WE_O <= #1 write_flag; - end - -endmodule - - - - - Index: trunk/bench/verilog/tb_clkrst.v =================================================================== --- trunk/bench/verilog/tb_clkrst.v (revision 9) +++ trunk/bench/verilog/tb_clkrst.v (nonexistent) @@ -1,82 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// WISHBONE Clock and Reset Generator //// -//// //// -//// This file is part of the WISHBONE prefetch memory block: //// -//// http://www.opencores.org/cvsweb.shtml/wb_prefetch_spram/ //// -//// //// -//// Description //// -//// Clock and reset generator. //// -//// //// -//// To Do: //// -//// Nothing //// -//// //// -//// Author(s): //// -//// - Damjan Lampret, lampret@opencores.org //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: not supported by cvs2svn $ -// - -`include "timescale.v" - -module wb_clkrst( - // Clk & Rst Interface - clk_o, rst_o -); - -// -// Clock and Reset Interface -// -output clk_o; -output rst_o; - -// -// Internal registers -// -reg clk_o; -reg rst_o; - -initial begin - clk_o = 0; - rst_o = 0; - #1; - rst_o = 1; - #`Trst; - rst_o = 0; -end - -// -// Clock generator -// -always clk_o = #`Thper ~clk_o; - -endmodule Index: trunk/bench/verilog/tb_top.v =================================================================== --- trunk/bench/verilog/tb_top.v (revision 9) +++ trunk/bench/verilog/tb_top.v (nonexistent) @@ -1,125 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// WISHBONE Prefetch Single-Port RAM Top Level Test Bench //// -//// //// -//// This file is part of the WISHBONE prefetch memory block: //// -//// http://www.opencores.org/cvsweb.shtml/wb_prefetch_spram/ //// -//// //// -//// Description //// -//// Top level test bench. //// -//// //// -//// To Do: //// -//// Nothing //// -//// //// -//// Author(s): //// -//// - Damjan Lampret, lampret@opencores.org //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: not supported by cvs2svn $ -// Revision 1.2 2001/07/30 05:38:02 lampret -// Adding empty directories required by HDL coding guidelines -// -// - -`include "timescale.v" - -module tb_top; - -// -// Width of address and data buses -// -parameter aw = `RAM_ADDRWIDTH; -parameter dw = `RAM_DATAWIDTH; - -// -// Internal wires -// -wire clk; -wire rst; -wire cyc; -wire [aw-1:0] adr; -wire [dw-1:0] dat_prefetch; -wire [dw-1:0] dat_bfm; -wire [3:0] sel; -wire we; -wire stb; -wire ack; -wire err; - -// -// WISHBONE Prefetch single-port SRAM block -// -wb_prefetch_spram #(aw, dw) wb_prefetch_spram( - // WISHBONE Interface - .clk_i(clk), - .rst_i(rst), - .cyc_i(cyc), - .adr_i(adr), - .dat_i(dat_prefetch), - .sel_i(sel), - .we_i(we), - .stb_i(stb), - .dat_o(dat_bfm), - .ack_o(ack), - .err_o(err) -); - -// -// WISHBONE Bus Functional Model -// -wb_master #(aw, dw) wb_master( - // WISHBONE Interface - .CLK_I(clk), - .RST_I(rst), - .TAG_I(4'b0000), - .TAG_O(), - .CYC_O(cyc), - .ADR_O(adr), - .DAT_O(dat_prefetch), - .SEL_O(sel), - .WE_O(we), - .STB_O(stb), - .DAT_I(dat_bfm), - .ACK_I(ack), - .ERR_I(err), - .RTY_I(1'b0) -); - -// -// WISHBONE Clock & Reset Generator -// -wb_clkrst wb_clkrst( - // Clk & Rst Interface - .clk_o(clk), - .rst_o(rst) -); - -endmodule Index: trunk/bench/verilog/tb_tasks.v =================================================================== --- trunk/bench/verilog/tb_tasks.v (revision 9) +++ trunk/bench/verilog/tb_tasks.v (nonexistent) @@ -1,296 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Test Tasks for WISHBONE Prefetching Single-Port RAM //// -//// //// -//// This file is part of the WISHBONE prefetch memory block: //// -//// http://www.opencores.org/cvsweb.shtml/wb_prefetch_spram/ //// -//// //// -//// Description //// -//// First half of the RAM is initialized with random data //// -//// and then it is copied to second half of the RAM. During //// -//// copy random delays are inserted. //// -//// //// -//// To Do: //// -//// Nothing //// -//// //// -//// Author(s): //// -//// - Damjan Lampret, lampret@opencores.org //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: not supported by cvs2svn $ -// Revision 1.2 2001/07/30 05:38:02 lampret -// Adding empty directories required by HDL coding guidelines -// -// - -`include "timescale.v" - -module tb_tasks; - -integer errors; - -// -// Tests description -// -task describe_test; -begin - $display; - $display(" Verification of the WISHBONE Prefetch Single-Port Synchronous RAM"); - $display; - $display(" Abbrev:"); - $display(" w single write transfer"); - $display(" r single read transfer"); - $display(" Brr block read transfer with two reads"); - $display(" Bww block write transfer with two writes"); - $display(" . inserted clock cycle delay"); - $display; - $display(" I. One half of the RAM is preinitialized with random data. RAM is "); - $display(" written using WISHBONE single writes."); - $display; - $display(" II. After that main part of the test is performed. Preinitialized "); - $display(" half of the RAM is read with randomly long WISHBONE block reads. "); - $display(" Between each beat of a block read zero or random number of clock "); - $display(" cycles are inserted."); - $display(" Each block of data is then written into second half of the RAM. "); - $display(" Data is written using WISHBONE block writes with randomly inserted "); - $display(" clock cycle delays between two writes."); - $display(" "); - $display(" III. To verify correct operation of prefetch logic, both halfs of "); - $display(" prefetching RAM are compared. To pass the test they must match."); - $display(" "); - $display(" Total RAM size: %d words by 32 bits", `RAM_WORDS); -end -endtask - -// -// Init 1st half of RAM -// -task init_1sthalf; -reg [31:0] addr; -reg [31:0] data; -begin - $display; - $display("I. Initializing 1st half of the RAM: "); - for (addr = 0; addr < `RAM_WORDS/2; addr = addr + 1) begin - $write("w"); -// data = $random; - data = addr; - tb_top.wb_master.wr(addr, data, 4'b1111); - end - $display(" Done."); -end -endtask - -// -// Copy 1st half of RAM into 2nd half -// -task copy_1stto2ndhalf; -reg [31:0] saddr; -reg [31:0] daddr; -reg [31:0] data [63:0]; -reg [3:0] rndnum; -reg [1:0] delay; -reg end_flag; -reg [2:0] beats; -reg [2:0] current_beat; -integer start_time; -integer end_time; -begin - $display; - $display("II. Copying 1st half of the RAM into 2nd half:"); - daddr = `RAM_WORDS/2; - start_time = $time; - for (saddr = 0; saddr < `RAM_WORDS/2; saddr = saddr) begin - beats = $random; - if (!beats) - beats = 1; - - // - // Block read from first half of RAM. Beats are spaced with random delays. - // - $write("B"); - for (current_beat = beats; current_beat; current_beat = current_beat - 1) begin - $write("r"); - if (current_beat == 1) - end_flag = 1; - else - end_flag = 0; - rndnum = $random; - if (rndnum == 0) - delay = $random; - else - delay = 0; - while (delay) - @(posedge tb_top.clk) begin - delay = delay - 1; - $write("."); - end - tb_top.wb_master.blkrd(saddr, end_flag, data[current_beat]); - saddr = saddr + 1; - end - - // - // Block write into second half of RAM. Beats are spaced with random delays. - // - $write("B"); - for (current_beat = beats; current_beat; current_beat = current_beat - 1) begin - $write("w"); - if (current_beat == 1) - end_flag = 1; - else - end_flag = 0; - rndnum = $random; - if (rndnum == 0) - delay = $random; - else - delay = 0; - while (delay) - @(posedge tb_top.clk) begin - delay = delay - 1; - $write("."); - end - if (daddr < `RAM_WORDS) begin - tb_top.wb_master.blkwr(daddr, data[current_beat], 4'b1111, end_flag); - daddr = daddr + 1; - end - end - end - $display(" Done."); - end_time = $time; - $display; - $display(" Clock cycles to complete copy: %d", (end_time - start_time) / (`Thper*2)); -end -endtask - - -// -// Read and write same addresses in first half (to check for bug reported by Avi) -// -task read_write_1sthalf; -reg [31:0] saddr; -reg [31:0] daddr; -reg [31:0] data [63:0]; -reg [3:0] rndnum; -reg [1:0] delay; -reg [2:0] beats; -integer start_time; -integer end_time; -begin - $display; - $display("III. Reading and writing same locations in the first half"); - start_time = $time; - for (saddr = 0; saddr < `RAM_WORDS/2; saddr = saddr) begin - - // - // Read and write same locations. Beats are spaced with random delays. - // - rndnum = $random; - if (rndnum == 0) - delay = $random; - else - delay = 0; - while (delay) - @(posedge tb_top.clk) begin - delay = delay - 1; - $write("."); - end - $write("r"); - tb_top.wb_master.rd(saddr, data[1]); - daddr = saddr; - $write("w"); - tb_top.wb_master.wr(daddr, data[1], 4'b1111); - $write("r"); - tb_top.wb_master.rd(saddr, data[2]); - if (data[1] != data[2]) begin - $write("Read/Write/Read sequence performing accesses "); - $write("to address %h failed. First read %h != second read %h", saddr, data[1], data[2]); - errors = errors + 1; - end - saddr = saddr + 1; - end - - $display(" Done."); - end_time = $time; - $display; - $display(" Clock cycles to complete copy: %d", (end_time - start_time) / (`Thper*2)); -end -endtask - -// -// Compare 1st half and 2nd half of the RAM and return result of the comparison -// -task comp_1stand2ndhalf; -reg [31:0] saddr; -reg [31:0] sdata; -reg [31:0] daddr; -reg [31:0] ddata; -begin - $display; - $display("III. Comparing 1st half and 2nd half of the RAM."); - for (saddr = 0; saddr < `RAM_WORDS/2; saddr = saddr + 1) begin - daddr = saddr + `RAM_WORDS/2; - tb_top.wb_master.rd(saddr, sdata); - tb_top.wb_master.rd(daddr, ddata); - if (sdata != ddata) begin - $write("Locations %h and %h are different. ", saddr, daddr); - $display("First data %h and second data %h.", sdata, ddata); - errors = errors + 1; - end - end - $display; - if (!errors) - $display(" Test Passed"); - else - $display(" ERRORS: %d", errors); - $display; -end -endtask - -// -// Run the test -// -initial begin -`ifdef VCD_DUMP - $dumpfile("../out/dump.vcd"); - $dumpvars(0); -`endif - #`Trst; - describe_test; - init_1sthalf; - errors = 0; - copy_1stto2ndhalf; - read_write_1sthalf; - comp_1stand2ndhalf; - $finish; -end - -endmodule - Index: trunk/rtl/verilog/wb_prefetch_spram.v =================================================================== --- trunk/rtl/verilog/wb_prefetch_spram.v (revision 9) +++ trunk/rtl/verilog/wb_prefetch_spram.v (nonexistent) @@ -1,182 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// WISHBONE Prefetch Single-Port RAM //// -//// //// -//// This file is part of the WISHBONE prefetch memory block: //// -//// http://www.opencores.org/cvsweb.shtml/wb_prefetch_spram/ //// -//// //// -//// Description //// -//// WISHBONE prefetching single-port RAM. //// -//// This block uses special prefetching technique to reduce //// -//// latency and increase bandwidth when reading internal //// -//// single-port synchronous memory with sequential bursts. //// -//// Compared to asynchronous memories this block uses //// -//// synchronous memory and thus meets timing much easier. //// -//// Compared to reading sync memory w/o prefetching this block //// -//// has the same clock->q data output timing as w/o prefetch. //// -//// //// -//// Latency/bandwidth for 4-beat WISHBONE read block transfer: //// -//// - async memory: 4 clock cycles //// -//// - sync memory w/o prefetching: 8 clock cycles //// -//// - sync memory w/ prefetching: 4+1 clock cycles //// -//// //// -//// To Do: //// -//// Nothing //// -//// //// -//// Author(s): //// -//// - Damjan Lampret, lampret@opencores.org //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: not supported by cvs2svn $ -// Revision 1.2 2001/07/30 05:38:02 lampret -// Adding empty directories required by HDL coding guidelines -// -// - -`include "timescale.v" - -// -// Bits in address that are incremented in a burst. -// -// Example for default of 1:0 can be: -// 2,3,0,1 -// -`define BURST_BITS 1:0 -`define FIXED_LOW_BIT 2 - -// -// Define this to check for strict 32-bit access -// -`define STRICT_32BIT_ACCESS - -module wb_prefetch_spram( - // WISHBONE Interface - clk_i, rst_i, cyc_i, adr_i, dat_i, sel_i, we_i, stb_i, - dat_o, ack_o, err_o -); - -// -// Default width of address and data buses -// -parameter aw = 12; -parameter dw = 32; - -// -// WISHBONE Interface -// -input clk_i; // Clock -input rst_i; // Reset -input cyc_i; // cycle valid input -input [aw-1:0] adr_i; // address bus inputs -input [dw-1:0] dat_i; // input data bus -input [3:0] sel_i; // byte select inputs -input we_i; // indicates write transfer -input stb_i; // strobe input -output [dw-1:0] dat_o; // output data bus -output ack_o; // normal termination -output err_o; // termination w/ error - -// -// Internal wires and registers -// -wire [aw-1:0] predicted_addr; // Predicted address -wire [aw-1:0] ram_addr; // Address used to address RAM block -wire correct_data; // Current RAM output data is valid -reg [aw-1:0] last_addr; // Saved ram_addr -wire valid_cycle; // Valid WISHBONE cycle - -// -// Combinatorial logic -// - -// -// If STRICT_32BIT_ACCESS is defined, assert err_o when access is -// not completely 32-bit. -// -`ifdef STRICT_32BIT_ACCESS -assign err_o = valid_cycle & (sel_i != 4'b1111); -`else -assign err_o = 1'b0; -`endif - -// -// Valid WSIHBONE cycles when both cyc_i and stb_i are assrted -// -assign valid_cycle = cyc_i & stb_i; - -// -// Generate prefetch address by using address from the last RAM access and -// incrementing burst part of the address -// -assign predicted_addr = { last_addr[aw-1:`FIXED_LOW_BIT], last_addr[`BURST_BITS] + 1'b1 }; - -// -// Address RAM with WISHBONE address if last RAM access was mispredicted -// or if current WISHBONE access is write -// -assign ram_addr = (~correct_data | we_i) ? adr_i : predicted_addr; - -// -// Assert correct_data if RAM's current output data is the same as data -// requested by WISHBONE master -// -assign correct_data = (adr_i == last_addr); - -// -// Acknowledge current WISHBONE transfer if correct data was delivered -// or if it is write transfer -// -assign ack_o = (correct_data | we_i) & valid_cycle; - -// -// Address used to address RAM at the last WISHBONE read beat -// -always @(posedge clk_i or posedge rst_i) - if (rst_i) - last_addr <= #1 {aw{1'b0}}; - else if (valid_cycle) - last_addr <= #1 ram_addr; - -// -// Instantiation of single-port synchronous RAM -// -generic_spram #(aw, dw) spram ( - .clk(clk_i), - .rst(rst_i), - .addr(ram_addr), - .di(dat_i), - .ce(valid_cycle), - .we(we_i), - .oe(valid_cycle), - .do(dat_o) -); - -endmodule Index: trunk/rtl/verilog/generic_spram.v =================================================================== --- trunk/rtl/verilog/generic_spram.v (revision 9) +++ trunk/rtl/verilog/generic_spram.v (nonexistent) @@ -1,232 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Generic Single-Port Synchronous RAM //// -//// //// -//// This file is part of memory library available from //// -//// http://www.opencores.org/cvsweb.shtml/generic_memories/ //// -//// //// -//// Description //// -//// This block is a wrapper with common single-port //// -//// synchronous memory interface for different //// -//// types of ASIC and FPGA RAMs. Beside universal memory //// -//// interface it also provides behavioral model of generic //// -//// single-port synchronous RAM. //// -//// It should be used in all OPENCORES designs that want to be //// -//// portable accross different target technologies and //// -//// independent of target memory. //// -//// //// -//// Supported ASIC RAMs are: //// -//// - Artisan Single-Port Sync RAM //// -//// - Avant! Two-Port Sync RAM (*) //// -//// - Virage Single-Port Sync RAM //// -//// - Virtual Silicon Single-Port Sync RAM //// -//// //// -//// Supported FPGA RAMs are: //// -//// - Xilinx Virtex RAMB4_S16 //// -//// //// -//// To Do: //// -//// - xilinx rams need external tri-state logic //// -//// - fix avant! two-port ram //// -//// - add additional RAMs (Altera etc) //// -//// //// -//// Author(s): //// -//// - Damjan Lampret, lampret@opencores.org //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: not supported by cvs2svn $ -// Revision 1.3 2001/09/23 05:02:12 lampret -// Temporarily changed artisan memory cell name to art_hssp_8192x32 -// -// Revision 1.2 2001/07/30 05:38:02 lampret -// Adding empty directories required by HDL coding guidelines -// -// - -`include "timescale.v" - -module generic_spram( - // Generic synchronous single-port RAM interface - clk, rst, ce, we, oe, addr, di, do -); - -// -// Default address and data buses width -// -parameter aw = 13; -parameter dw = 32; - -// -// Generic synchronous single-port RAM interface -// -input clk; // Clock -input rst; // Reset -input ce; // Chip enable input -input we; // Write enable input -input oe; // Output enable input -input [aw-1:0] addr; // address bus inputs -input [dw-1:0] di; // input data bus -output [dw-1:0] do; // output data bus - -// -// Internal wires and registers -// - - -`ifdef ARTISAN_SSP - -// -// Instantiation of ASIC memory: -// -// Artisan Synchronous Single-Port RAM (ra1sh) -// -art_hssp_8192x32 #(dw, 2<q data output timing as w/o prefetch. //// +//// //// +//// Latency/bandwidth for 4-beat WISHBONE read block transfer: //// +//// - async memory: 4 clock cycles //// +//// - sync memory w/o prefetching: 8 clock cycles //// +//// - sync memory w/ prefetching: 4+1 clock cycles //// +//// //// +//// To Do: //// +//// Nothing //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.2 2001/07/30 05:38:02 lampret +// Adding empty directories required by HDL coding guidelines +// +// + +`include "timescale.v" + +// +// Bits in address that are incremented in a burst. +// +// Example for default of 1:0 can be: +// 2,3,0,1 +// +`define BURST_BITS 1:0 +`define FIXED_LOW_BIT 2 + +// +// Define this to check for strict 32-bit access +// +`define STRICT_32BIT_ACCESS + +module wb_prefetch_spram( + // WISHBONE Interface + clk_i, rst_i, cyc_i, adr_i, dat_i, sel_i, we_i, stb_i, + dat_o, ack_o, err_o +); + +// +// Default width of address and data buses +// +parameter aw = 12; +parameter dw = 32; + +// +// WISHBONE Interface +// +input clk_i; // Clock +input rst_i; // Reset +input cyc_i; // cycle valid input +input [aw-1:0] adr_i; // address bus inputs +input [dw-1:0] dat_i; // input data bus +input [3:0] sel_i; // byte select inputs +input we_i; // indicates write transfer +input stb_i; // strobe input +output [dw-1:0] dat_o; // output data bus +output ack_o; // normal termination +output err_o; // termination w/ error + +// +// Internal wires and registers +// +wire [aw-1:0] predicted_addr; // Predicted address +wire [aw-1:0] ram_addr; // Address used to address RAM block +wire correct_data; // Current RAM output data is valid +reg [aw-1:0] last_addr; // Saved ram_addr +wire valid_cycle; // Valid WISHBONE cycle + +// +// Combinatorial logic +// + +// +// If STRICT_32BIT_ACCESS is defined, assert err_o when access is +// not completely 32-bit. +// +`ifdef STRICT_32BIT_ACCESS +assign err_o = valid_cycle & (sel_i != 4'b1111); +`else +assign err_o = 1'b0; +`endif + +// +// Valid WSIHBONE cycles when both cyc_i and stb_i are assrted +// +assign valid_cycle = cyc_i & stb_i; + +// +// Generate prefetch address by using address from the last RAM access and +// incrementing burst part of the address +// +assign predicted_addr = { last_addr[aw-1:`FIXED_LOW_BIT], last_addr[`BURST_BITS] + 1'b1 }; + +// +// Address RAM with WISHBONE address if last RAM access was mispredicted +// or if current WISHBONE access is write +// +assign ram_addr = (~correct_data | we_i) ? adr_i : predicted_addr; + +// +// Assert correct_data if RAM's current output data is the same as data +// requested by WISHBONE master +// +assign correct_data = (adr_i == last_addr); + +// +// Acknowledge current WISHBONE transfer if correct data was delivered +// or if it is write transfer +// +assign ack_o = (correct_data | we_i) & valid_cycle; + +// +// Address used to address RAM at the last WISHBONE read beat +// +always @(posedge clk_i or posedge rst_i) + if (rst_i) + last_addr <= #1 {aw{1'b0}}; + else if (valid_cycle) + last_addr <= #1 ram_addr; + +// +// Instantiation of single-port synchronous RAM +// +generic_spram #(aw, dw) spram ( + .clk(clk_i), + .rst(rst_i), + .addr(ram_addr), + .di(dat_i), + .ce(valid_cycle), + .we(we_i), + .oe(valid_cycle), + .do(dat_o) +); + +endmodule Index: wb_prefetch_spram/trunk/bench/verilog/tb_tasks.v =================================================================== --- wb_prefetch_spram/trunk/bench/verilog/tb_tasks.v (nonexistent) +++ wb_prefetch_spram/trunk/bench/verilog/tb_tasks.v (revision 10) @@ -0,0 +1,296 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Test Tasks for WISHBONE Prefetching Single-Port RAM //// +//// //// +//// This file is part of the WISHBONE prefetch memory block: //// +//// http://www.opencores.org/cvsweb.shtml/wb_prefetch_spram/ //// +//// //// +//// Description //// +//// First half of the RAM is initialized with random data //// +//// and then it is copied to second half of the RAM. During //// +//// copy random delays are inserted. //// +//// //// +//// To Do: //// +//// Nothing //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.2 2001/07/30 05:38:02 lampret +// Adding empty directories required by HDL coding guidelines +// +// + +`include "timescale.v" + +module tb_tasks; + +integer errors; + +// +// Tests description +// +task describe_test; +begin + $display; + $display(" Verification of the WISHBONE Prefetch Single-Port Synchronous RAM"); + $display; + $display(" Abbrev:"); + $display(" w single write transfer"); + $display(" r single read transfer"); + $display(" Brr block read transfer with two reads"); + $display(" Bww block write transfer with two writes"); + $display(" . inserted clock cycle delay"); + $display; + $display(" I. One half of the RAM is preinitialized with random data. RAM is "); + $display(" written using WISHBONE single writes."); + $display; + $display(" II. After that main part of the test is performed. Preinitialized "); + $display(" half of the RAM is read with randomly long WISHBONE block reads. "); + $display(" Between each beat of a block read zero or random number of clock "); + $display(" cycles are inserted."); + $display(" Each block of data is then written into second half of the RAM. "); + $display(" Data is written using WISHBONE block writes with randomly inserted "); + $display(" clock cycle delays between two writes."); + $display(" "); + $display(" III. To verify correct operation of prefetch logic, both halfs of "); + $display(" prefetching RAM are compared. To pass the test they must match."); + $display(" "); + $display(" Total RAM size: %d words by 32 bits", `RAM_WORDS); +end +endtask + +// +// Init 1st half of RAM +// +task init_1sthalf; +reg [31:0] addr; +reg [31:0] data; +begin + $display; + $display("I. Initializing 1st half of the RAM: "); + for (addr = 0; addr < `RAM_WORDS/2; addr = addr + 1) begin + $write("w"); +// data = $random; + data = addr; + tb_top.wb_master.wr(addr, data, 4'b1111); + end + $display(" Done."); +end +endtask + +// +// Copy 1st half of RAM into 2nd half +// +task copy_1stto2ndhalf; +reg [31:0] saddr; +reg [31:0] daddr; +reg [31:0] data [63:0]; +reg [3:0] rndnum; +reg [1:0] delay; +reg end_flag; +reg [2:0] beats; +reg [2:0] current_beat; +integer start_time; +integer end_time; +begin + $display; + $display("II. Copying 1st half of the RAM into 2nd half:"); + daddr = `RAM_WORDS/2; + start_time = $time; + for (saddr = 0; saddr < `RAM_WORDS/2; saddr = saddr) begin + beats = $random; + if (!beats) + beats = 1; + + // + // Block read from first half of RAM. Beats are spaced with random delays. + // + $write("B"); + for (current_beat = beats; current_beat; current_beat = current_beat - 1) begin + $write("r"); + if (current_beat == 1) + end_flag = 1; + else + end_flag = 0; + rndnum = $random; + if (rndnum == 0) + delay = $random; + else + delay = 0; + while (delay) + @(posedge tb_top.clk) begin + delay = delay - 1; + $write("."); + end + tb_top.wb_master.blkrd(saddr, end_flag, data[current_beat]); + saddr = saddr + 1; + end + + // + // Block write into second half of RAM. Beats are spaced with random delays. + // + $write("B"); + for (current_beat = beats; current_beat; current_beat = current_beat - 1) begin + $write("w"); + if (current_beat == 1) + end_flag = 1; + else + end_flag = 0; + rndnum = $random; + if (rndnum == 0) + delay = $random; + else + delay = 0; + while (delay) + @(posedge tb_top.clk) begin + delay = delay - 1; + $write("."); + end + if (daddr < `RAM_WORDS) begin + tb_top.wb_master.blkwr(daddr, data[current_beat], 4'b1111, end_flag); + daddr = daddr + 1; + end + end + end + $display(" Done."); + end_time = $time; + $display; + $display(" Clock cycles to complete copy: %d", (end_time - start_time) / (`Thper*2)); +end +endtask + + +// +// Read and write same addresses in first half (to check for bug reported by Avi) +// +task read_write_1sthalf; +reg [31:0] saddr; +reg [31:0] daddr; +reg [31:0] data [63:0]; +reg [3:0] rndnum; +reg [1:0] delay; +reg [2:0] beats; +integer start_time; +integer end_time; +begin + $display; + $display("III. Reading and writing same locations in the first half"); + start_time = $time; + for (saddr = 0; saddr < `RAM_WORDS/2; saddr = saddr) begin + + // + // Read and write same locations. Beats are spaced with random delays. + // + rndnum = $random; + if (rndnum == 0) + delay = $random; + else + delay = 0; + while (delay) + @(posedge tb_top.clk) begin + delay = delay - 1; + $write("."); + end + $write("r"); + tb_top.wb_master.rd(saddr, data[1]); + daddr = saddr; + $write("w"); + tb_top.wb_master.wr(daddr, data[1], 4'b1111); + $write("r"); + tb_top.wb_master.rd(saddr, data[2]); + if (data[1] != data[2]) begin + $write("Read/Write/Read sequence performing accesses "); + $write("to address %h failed. First read %h != second read %h", saddr, data[1], data[2]); + errors = errors + 1; + end + saddr = saddr + 1; + end + + $display(" Done."); + end_time = $time; + $display; + $display(" Clock cycles to complete copy: %d", (end_time - start_time) / (`Thper*2)); +end +endtask + +// +// Compare 1st half and 2nd half of the RAM and return result of the comparison +// +task comp_1stand2ndhalf; +reg [31:0] saddr; +reg [31:0] sdata; +reg [31:0] daddr; +reg [31:0] ddata; +begin + $display; + $display("III. Comparing 1st half and 2nd half of the RAM."); + for (saddr = 0; saddr < `RAM_WORDS/2; saddr = saddr + 1) begin + daddr = saddr + `RAM_WORDS/2; + tb_top.wb_master.rd(saddr, sdata); + tb_top.wb_master.rd(daddr, ddata); + if (sdata != ddata) begin + $write("Locations %h and %h are different. ", saddr, daddr); + $display("First data %h and second data %h.", sdata, ddata); + errors = errors + 1; + end + end + $display; + if (!errors) + $display(" Test Passed"); + else + $display(" ERRORS: %d", errors); + $display; +end +endtask + +// +// Run the test +// +initial begin +`ifdef VCD_DUMP + $dumpfile("../out/dump.vcd"); + $dumpvars(0); +`endif + #`Trst; + describe_test; + init_1sthalf; + errors = 0; + copy_1stto2ndhalf; + read_write_1sthalf; + comp_1stand2ndhalf; + $finish; +end + +endmodule + Index: wb_prefetch_spram/trunk/bench/verilog/tb_defines.v =================================================================== --- wb_prefetch_spram/trunk/bench/verilog/tb_defines.v (nonexistent) +++ wb_prefetch_spram/trunk/bench/verilog/tb_defines.v (revision 10) @@ -0,0 +1,76 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Test Bench Definitions //// +//// //// +//// This file is part of the WISHBONE prefetch memory block: //// +//// http://www.opencores.org/cvsweb.shtml/wb_prefetch_spram/ //// +//// //// +//// Description //// +//// Test bench definitions. //// +//// //// +//// To Do: //// +//// Nothing //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.2 2001/07/30 05:38:02 lampret +// Adding empty directories required by HDL coding guidelines +// +// + +// +// Half of clock period +// +`define Thper 5 + +// +// Reset time +// +`define Trst (`Thper*2+1) + +// +// Number of words in RAM +// +`define RAM_ADDRWIDTH 12 +`define RAM_WORDS (2<<`RAM_ADDRWIDTH) + +// +// RAM data width +// +`define RAM_DATAWIDTH 32 + +// +// Define to get VCD output +// +`define VCD_DUMP Index: wb_prefetch_spram/trunk/bench/verilog/wb_master.v =================================================================== --- wb_prefetch_spram/trunk/bench/verilog/wb_master.v (nonexistent) +++ wb_prefetch_spram/trunk/bench/verilog/wb_master.v (revision 10) @@ -0,0 +1,313 @@ +`include "timescale.v" + +// -*- Mode: Verilog -*- +// Filename : wb_master.v +// Description : Wishbone Master Behavorial +// Author : Winefred Washington +// Created On : Thu Jan 11 21:18:41 2001 +// Last Modified By: . +// Last Modified On: . +// Update Count : 0 +// Status : Unknown, Use with caution! + +// Description Specification +// General Description: 8, 16, 32-bit WISHBONE Master +// Supported cycles: MASTER, READ/WRITE +// MASTER, BLOCK READ/WRITE +// MASTER, RMW +// Data port, size: 8, 16, 32-bit +// Data port, granularity 8-bit +// Data port, Max. operand size 32-bit +// Data transfer ordering: little endian +// Data transfer sequencing: undefined +// + +module wb_master(CLK_I, RST_I, TAG_I, TAG_O, + ACK_I, ADR_O, CYC_O, DAT_I, DAT_O, ERR_I, RTY_I, SEL_O, STB_O, WE_O); + +parameter aw = 16; +parameter dw = 32; + + input CLK_I; + input RST_I; + input [3:0] TAG_I; + output [3:0] TAG_O; + input ACK_I; + output [aw-1:0] ADR_O; + output CYC_O; + input [dw-1:0] DAT_I; + output [dw-1:0] DAT_O; + input ERR_I; + input RTY_I; + output [3:0] SEL_O; + output STB_O; + output WE_O; + + reg [aw-1:0] ADR_O; + reg [3:0] SEL_O; + reg CYC_O; + reg STB_O; + reg WE_O; + reg [dw-1:0] DAT_O; + + wire [15:0] mem_sizes; // determines the data width of an address range + reg [31:0] write_burst_buffer[0:7]; + reg [31:0] read_burst_buffer[0:7]; + + reg GO; + integer cycle_end; + integer address; + integer data; + integer selects; + integer write_flag; + + // + // mem_sizes determines the data widths of memory space + // The memory space is divided into eight regions. Each + // region is controlled by a two bit field. + // + // Bits + // 00 = 8 bit memory space + // 01 = 16 bit + // 10 = 32 bit + // 11 = 64 bit (not supported in this model + // + + assign mem_sizes = 16'b10_10_10_10_10_10_10_10; + + function [1:0] data_width; + input [31:0] adr; + begin + casex (adr[31:29]) + 3'b000: data_width = mem_sizes[15:14]; + 3'b001: data_width = mem_sizes[13:12]; + 3'b010: data_width = mem_sizes[11:10]; + 3'b011: data_width = mem_sizes[9:8]; + 3'b100: data_width = mem_sizes[7:6]; + 3'b101: data_width = mem_sizes[5:4]; + 3'b110: data_width = mem_sizes[3:2]; + 3'b111: data_width = mem_sizes[1:0]; + 3'bxxx: data_width = 2'bxx; + endcase // casex (adr[31:29]) + end + endfunction + + always @(posedge CLK_I or posedge RST_I) + begin + if (RST_I) + begin + GO = 1'b0; + end + end + + // read single + task rd; + input [31:0] adr; + output [31:0] result; + + begin + #1; + cycle_end = 1; + address = adr; + selects = 255; + write_flag = 0; + + GO <= 1; +// @(posedge CLK_I); +// GO <= 0; // DL + + // wait for cycle to start + while (~CYC_O) + @(posedge CLK_I); + + // wait for cycle to end + while (CYC_O) + @(posedge CLK_I); + + result = data; +// $display(" Reading %h from address %h", result, address); + + end + endtask // read + + task wr; + input [31:0] adr; + input [31:0] dat; + input [3:0] sel; + begin + #1; + cycle_end = 1; + address = adr; + selects = sel; + write_flag = 1; + data = dat; + + GO <= 1; +// @(posedge CLK_I); +// GO <= 0; // DL + + // wait for cycle to start + while (~CYC_O) + @(posedge CLK_I); + + // wait for cycle to end + while (CYC_O) + @(posedge CLK_I); +// $display(" Writing %h to address %h", data, address); + + end + endtask // wr + + // block read + task blkrd; + input [31:0] adr; + input end_flag; + output [31:0] result; + + begin + #1; + write_flag = 0; + cycle_end = end_flag; + address = adr; + GO <= 1; +// @(posedge CLK_I); +// GO <= 0; // DL + + while (~(ACK_I & STB_O)) + @(posedge CLK_I); + + result = data; + end + endtask // blkrd + + // block write + task blkwr; + input [31:0] adr; + input [31:0] dat; + input [3:0] sel; + input end_flag; + begin + #1; + write_flag = 1; + cycle_end = end_flag; + address = adr; + data = dat; + selects = sel; + GO <= 1; +// @(posedge CLK_I); +// GO <= 0; // DL + + while (~(ACK_I & STB_O)) + @(posedge CLK_I); + + end + endtask // blkwr + + // RMW + task rmw; + input [31:0] adr; + input [31:0] dat; + input [3:0] sel; + output [31:0] result; + + begin + // read phase + write_flag = 0; + cycle_end = 0; + address = adr; + GO <= 1; + @(posedge CLK_I); + GO <= 0; // DL + + while (~(ACK_I & STB_O)) + @(posedge CLK_I); + + result = data; + + // write phase + write_flag = 1; + address = adr; + selects = sel; + GO <= 1; + data <= dat; + cycle_end <= 1; + @(posedge CLK_I); + GO <= 0; // DL + + while (~(ACK_I & STB_O)) + @(posedge CLK_I); + + end + endtask // rmw + + always @(posedge CLK_I) + begin + if (RST_I) + ADR_O <= {aw{1'b0}}; + else + ADR_O <= #1 address[aw-1:0]; + end + + always @(posedge CLK_I) + begin + if (RST_I | ERR_I | RTY_I) + CYC_O <= #1 1'b0; + else if ((cycle_end == 1) & ACK_I) + CYC_O <= #1 1'b0; + else if (GO | CYC_O) begin + CYC_O <= #1 1'b1; + GO <= 1'b0; + end + end + + // stb control + always @(posedge CLK_I) + begin + if (RST_I | ERR_I | RTY_I) + STB_O <= #1 1'b0; + else if (STB_O & ACK_I) + STB_O <= #1 1'b0; + else if (GO | STB_O) + STB_O <= #1 1'b1; + end + + // selects & data + always @(posedge CLK_I) + begin + if (write_flag == 0) begin + SEL_O <= #1 4'b1111; + if (STB_O & ACK_I) + data <= #1 DAT_I; + end + else begin + case (data_width(address)) + 2'b00: begin + SEL_O <= #1 {3'b000, selects[0]}; + DAT_O <= #1 {data[7:0], data[7:0], data[7:0], data[7:0]}; + end + 2'b01: begin + SEL_O <= #1 {2'b00, selects[1:0]}; + DAT_O <= #1 {data[15:0], data[15:0]}; + end + 2'b10: begin + SEL_O <= #1 selects; + DAT_O <= #1 data[dw-1:0]; + end + endcase + end + end + + always @(posedge CLK_I) + begin + if (RST_I) + WE_O <= 1'b0; + else if (GO) + WE_O <= #1 write_flag; + end + +endmodule + + + + + Index: wb_prefetch_spram/trunk/bench/verilog/tb_top.v =================================================================== --- wb_prefetch_spram/trunk/bench/verilog/tb_top.v (nonexistent) +++ wb_prefetch_spram/trunk/bench/verilog/tb_top.v (revision 10) @@ -0,0 +1,125 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Prefetch Single-Port RAM Top Level Test Bench //// +//// //// +//// This file is part of the WISHBONE prefetch memory block: //// +//// http://www.opencores.org/cvsweb.shtml/wb_prefetch_spram/ //// +//// //// +//// Description //// +//// Top level test bench. //// +//// //// +//// To Do: //// +//// Nothing //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.2 2001/07/30 05:38:02 lampret +// Adding empty directories required by HDL coding guidelines +// +// + +`include "timescale.v" + +module tb_top; + +// +// Width of address and data buses +// +parameter aw = `RAM_ADDRWIDTH; +parameter dw = `RAM_DATAWIDTH; + +// +// Internal wires +// +wire clk; +wire rst; +wire cyc; +wire [aw-1:0] adr; +wire [dw-1:0] dat_prefetch; +wire [dw-1:0] dat_bfm; +wire [3:0] sel; +wire we; +wire stb; +wire ack; +wire err; + +// +// WISHBONE Prefetch single-port SRAM block +// +wb_prefetch_spram #(aw, dw) wb_prefetch_spram( + // WISHBONE Interface + .clk_i(clk), + .rst_i(rst), + .cyc_i(cyc), + .adr_i(adr), + .dat_i(dat_prefetch), + .sel_i(sel), + .we_i(we), + .stb_i(stb), + .dat_o(dat_bfm), + .ack_o(ack), + .err_o(err) +); + +// +// WISHBONE Bus Functional Model +// +wb_master #(aw, dw) wb_master( + // WISHBONE Interface + .CLK_I(clk), + .RST_I(rst), + .TAG_I(4'b0000), + .TAG_O(), + .CYC_O(cyc), + .ADR_O(adr), + .DAT_O(dat_prefetch), + .SEL_O(sel), + .WE_O(we), + .STB_O(stb), + .DAT_I(dat_bfm), + .ACK_I(ack), + .ERR_I(err), + .RTY_I(1'b0) +); + +// +// WISHBONE Clock & Reset Generator +// +wb_clkrst wb_clkrst( + // Clk & Rst Interface + .clk_o(clk), + .rst_o(rst) +); + +endmodule Index: wb_prefetch_spram/trunk/bench/verilog/tb_clkrst.v =================================================================== --- wb_prefetch_spram/trunk/bench/verilog/tb_clkrst.v (nonexistent) +++ wb_prefetch_spram/trunk/bench/verilog/tb_clkrst.v (revision 10) @@ -0,0 +1,82 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Clock and Reset Generator //// +//// //// +//// This file is part of the WISHBONE prefetch memory block: //// +//// http://www.opencores.org/cvsweb.shtml/wb_prefetch_spram/ //// +//// //// +//// Description //// +//// Clock and reset generator. //// +//// //// +//// To Do: //// +//// Nothing //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// + +`include "timescale.v" + +module wb_clkrst( + // Clk & Rst Interface + clk_o, rst_o +); + +// +// Clock and Reset Interface +// +output clk_o; +output rst_o; + +// +// Internal registers +// +reg clk_o; +reg rst_o; + +initial begin + clk_o = 0; + rst_o = 0; + #1; + rst_o = 1; + #`Trst; + rst_o = 0; +end + +// +// Clock generator +// +always clk_o = #`Thper ~clk_o; + +endmodule Index: wb_prefetch_spram/trunk/sim/rtl_sim/src/timescale.v =================================================================== --- wb_prefetch_spram/trunk/sim/rtl_sim/src/timescale.v (nonexistent) +++ wb_prefetch_spram/trunk/sim/rtl_sim/src/timescale.v (revision 10) @@ -0,0 +1,3 @@ +// synopsys translate_off +`timescale 1ns/10ps +// synopsys translate_off Index: wb_prefetch_spram/trunk/sim/rtl_sim/bin/sim.sh =================================================================== --- wb_prefetch_spram/trunk/sim/rtl_sim/bin/sim.sh (nonexistent) +++ wb_prefetch_spram/trunk/sim/rtl_sim/bin/sim.sh (revision 10) @@ -0,0 +1,102 @@ +#!/bin/bash + +# +# This script runs RTL and gate-level simulation using different simultion tools. +# Right now Cadence Verilog-XL and NCSim are supported. +# +# Author: Damjan Lampret +# + +# +# User definitions +# + +# Set simulation tool you are using (xl, ncsim) +SIMTOOL=xl + +# Set test bench top module(s) +TB_TOP="tb_tasks" + +# Set include directories +INCLUDE_DIRS="../../../rtl/verilog ../../../bench/verilog ../src" + +# Set test bench files +BENCH_FILES="../../../bench/verilog/tb_defines.v ../../../bench/verilog/wb_master.v" +BENCH_FILES=$BENCH_FILES" ../../../bench/verilog/tb_clkrst.v ../../../bench/verilog/tb_top.v ../../../bench/verilog/tb_tasks.v " + +# Set RTL source files +RTL_FILES="../../../rtl/verilog/wb_prefetch_spram.v ../../../rtl/verilog/generic_spram.v" + +# Set gate-level netlist files +GATE_FILES="../../../syn/out/final_wb_prefetch_spram.v" + +# Set libraries (standard cell etc.) +LIB_FILES="/libs/Virtual_silicon/UMCL18U250D2_2.1/verilog_simulation_models/*.v" + +# Set parameters for simulation tool +if [ $SIMTOOL == xl ]; then + PARAM="+turbo+3 -q -l ../log/verilog.log" + for i in $INCLUDE_DIRS; do + INCDIR=$INCDIR" +incdir+$i" + done +elif [ $SIMTOOL == ncsim ]; then + NCPREP_PARAM="-UPDATE +overwrite -l ../log/ncprep.log" + NCSIM_PARAM="-MESSAGES -NOCOPYRIGHT" + for i in $INCLUDE_DIRS; do + INCDIR=$INCDIR" +incdir+$i" + done +else + echo "$SIMTOOL is unsupported simulation tool." + exit 0 +fi + +# +# Don't change anything below unless you know what you are doing +# + +# Run simulation in sim directory +cd ../run + +# Run actual simulation + +# Cadence Verilog-XL +if [ $SIMTOOL == xl ]; then + + # RTL simulation + if [ "$1" == rtl ]; then + verilog $PARAM $INCDIR $BENCH_FILES $RTL_FILES + + # Gate-level simulation + elif [ "$1" == gate ]; then + verilog $PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES + + # Wrong parameter or no parameter + else + echo "Usage: $0 [rtl|gate]" + exit 0 + fi + +# Cadence Ncsim +elif [ $SIMTOOL == ncsim ]; then + + # RTL simulation + if [ "$1" == rtl ]; then + ncprep $NCPREP_PARAM $INCDIR $BENCH_FILES $RTL_FILES + ./RUN_NC + + # Gate-level simulation + elif [ "$1" == gate ]; then + ncprep $NCPREP_PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES + ./RUN_NC + + # Wrong parameter or no parameter + else + echo "Usage: $0 [rtl|gate]" + exit 0 + fi + +# Unsupported simulation tool +else + echo "$SIMTOOL is unsupported simulation tool." + exit 0; +fi

wb_prefetch_spram/trunk/sim/rtl_sim/bin/sim.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: wb_prefetch_spram/trunk =================================================================== --- wb_prefetch_spram/trunk (nonexistent) +++ wb_prefetch_spram/trunk (revision 10)

wb_prefetch_spram/trunk Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: wb_prefetch_spram/web_uploads =================================================================== --- wb_prefetch_spram/web_uploads (nonexistent) +++ wb_prefetch_spram/web_uploads (revision 10)

wb_prefetch_spram/web_uploads Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: wb_prefetch_spram/branches =================================================================== --- wb_prefetch_spram/branches (nonexistent) +++ wb_prefetch_spram/branches (revision 10)

wb_prefetch_spram/branches Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: wb_prefetch_spram/tags/first/bench/verilog/tb_defines.v =================================================================== --- wb_prefetch_spram/tags/first/bench/verilog/tb_defines.v (nonexistent) +++ wb_prefetch_spram/tags/first/bench/verilog/tb_defines.v (revision 10) @@ -0,0 +1,68 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Test Bench Definitions //// +//// //// +//// This file is part of the WISHBONE prefetch memory block: //// +//// http://www.opencores.org/cvsweb.shtml/wb_prefetch_spram/ //// +//// //// +//// Description //// +//// Test bench definitions. //// +//// //// +//// To Do: //// +//// Nothing //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// + +// +// Half of clock period +// +`define Thper 5 + +// +// Reset time +// +`define Trst (`Thper*2+1) + +// +// Number of words in RAM +// +`define RAM_ADDRWIDTH 12 +`define RAM_WORDS (2<<`RAM_ADDRWIDTH) + +// +// Define to get VCD output +// +//`define VCD_DUMP Index: wb_prefetch_spram/tags/first/bench/verilog/wb_master.v =================================================================== --- wb_prefetch_spram/tags/first/bench/verilog/wb_master.v (nonexistent) +++ wb_prefetch_spram/tags/first/bench/verilog/wb_master.v (revision 10) @@ -0,0 +1,313 @@ +`include "timescale.v" + +// -*- Mode: Verilog -*- +// Filename : wb_master.v +// Description : Wishbone Master Behavorial +// Author : Winefred Washington +// Created On : Thu Jan 11 21:18:41 2001 +// Last Modified By: . +// Last Modified On: . +// Update Count : 0 +// Status : Unknown, Use with caution! + +// Description Specification +// General Description: 8, 16, 32-bit WISHBONE Master +// Supported cycles: MASTER, READ/WRITE +// MASTER, BLOCK READ/WRITE +// MASTER, RMW +// Data port, size: 8, 16, 32-bit +// Data port, granularity 8-bit +// Data port, Max. operand size 32-bit +// Data transfer ordering: little endian +// Data transfer sequencing: undefined +// + +module wb_master(CLK_I, RST_I, TAG_I, TAG_O, + ACK_I, ADR_O, CYC_O, DAT_I, DAT_O, ERR_I, RTY_I, SEL_O, STB_O, WE_O); + +parameter aw = 16; +parameter dw = 32; + + input CLK_I; + input RST_I; + input [3:0] TAG_I; + output [3:0] TAG_O; + input ACK_I; + output [aw-1:0] ADR_O; + output CYC_O; + input [dw-1:0] DAT_I; + output [dw-1:0] DAT_O; + input ERR_I; + input RTY_I; + output [3:0] SEL_O; + output STB_O; + output WE_O; + + reg [aw-1:0] ADR_O; + reg [3:0] SEL_O; + reg CYC_O; + reg STB_O; + reg WE_O; + reg [dw-1:0] DAT_O; + + wire [15:0] mem_sizes; // determines the data width of an address range + reg [31:0] write_burst_buffer[0:7]; + reg [31:0] read_burst_buffer[0:7]; + + reg GO; + integer cycle_end; + integer address; + integer data; + integer selects; + integer write_flag; + + // + // mem_sizes determines the data widths of memory space + // The memory space is divided into eight regions. Each + // region is controlled by a two bit field. + // + // Bits + // 00 = 8 bit memory space + // 01 = 16 bit + // 10 = 32 bit + // 11 = 64 bit (not supported in this model + // + + assign mem_sizes = 16'b10_10_10_10_10_10_10_10; + + function [1:0] data_width; + input [31:0] adr; + begin + casex (adr[31:29]) + 3'b000: data_width = mem_sizes[15:14]; + 3'b001: data_width = mem_sizes[13:12]; + 3'b010: data_width = mem_sizes[11:10]; + 3'b011: data_width = mem_sizes[9:8]; + 3'b100: data_width = mem_sizes[7:6]; + 3'b101: data_width = mem_sizes[5:4]; + 3'b110: data_width = mem_sizes[3:2]; + 3'b111: data_width = mem_sizes[1:0]; + 3'bxxx: data_width = 2'bxx; + endcase // casex (adr[31:29]) + end + endfunction + + always @(posedge CLK_I or posedge RST_I) + begin + if (RST_I) + begin + GO = 1'b0; + end + end + + // read single + task rd; + input [31:0] adr; + output [31:0] result; + + begin + #1; + cycle_end = 1; + address = adr; + selects = 255; + write_flag = 0; + + GO <= 1; + @(posedge CLK_I); + GO <= 0; // DL + + // wait for cycle to start + while (~CYC_O) + @(posedge CLK_I); + + // wait for cycle to end + while (CYC_O) + @(posedge CLK_I); + + result = data; +// $display(" Reading %h from address %h", result, address); + + end + endtask // read + + task wr; + input [31:0] adr; + input [31:0] dat; + input [3:0] sel; + begin + #1; + cycle_end = 1; + address = adr; + selects = sel; + write_flag = 1; + data = dat; + + GO <= 1; + @(posedge CLK_I); + GO <= 0; // DL + + // wait for cycle to start + while (~CYC_O) + @(posedge CLK_I); + + // wait for cycle to end + while (CYC_O) + @(posedge CLK_I); +// $display(" Writing %h to address %h", data, address); + + end + endtask // wr + + // block read + task blkrd; + input [31:0] adr; + input end_flag; + output [31:0] result; + + begin + #1; + write_flag = 0; + cycle_end = end_flag; + address = adr; + GO <= 1; + @(posedge CLK_I); + GO <= 0; // DL + + while (~(ACK_I & STB_O)) + @(posedge CLK_I); + + result = data; + end + endtask // blkrd + + // block write + task blkwr; + input [31:0] adr; + input [31:0] dat; + input [3:0] sel; + input end_flag; + begin + #1; + write_flag = 1; + cycle_end = end_flag; + address = adr; + data = dat; + selects = sel; + GO <= 1; + @(posedge CLK_I); + GO <= 0; // DL + + while (~(ACK_I & STB_O)) + @(posedge CLK_I); + + end + endtask // blkwr + + // RMW + task rmw; + input [31:0] adr; + input [31:0] dat; + input [3:0] sel; + output [31:0] result; + + begin + // read phase + write_flag = 0; + cycle_end = 0; + address = adr; + GO <= 1; + @(posedge CLK_I); + GO <= 0; // DL + + while (~(ACK_I & STB_O)) + @(posedge CLK_I); + + result = data; + + // write phase + write_flag = 1; + address = adr; + selects = sel; + GO <= 1; + data <= dat; + cycle_end <= 1; + @(posedge CLK_I); + GO <= 0; // DL + + while (~(ACK_I & STB_O)) + @(posedge CLK_I); + + end + endtask // rmw + + always @(posedge CLK_I) + begin + if (RST_I) + ADR_O <= {aw{1'b0}}; + else + ADR_O <= #1 address[aw-1:0]; + end + + always @(posedge CLK_I) + begin + if (RST_I | ERR_I | RTY_I) + CYC_O <= #1 1'b0; + else if ((cycle_end == 1) & ACK_I) + CYC_O <= #1 1'b0; + else if (GO | CYC_O) begin + CYC_O <= #1 1'b1; + GO <= 1'b0; + end + end + + // stb control + always @(posedge CLK_I) + begin + if (RST_I | ERR_I | RTY_I) + STB_O <= #1 1'b0; + else if (STB_O & ACK_I) + STB_O <= #1 1'b0; + else if (GO | STB_O) + STB_O <= #1 1'b1; + end + + // selects & data + always @(posedge CLK_I) + begin + if (write_flag == 0) begin + SEL_O <= #1 4'b1111; + if (STB_O & ACK_I) + data <= #1 DAT_I; + end + else begin + case (data_width(address)) + 2'b00: begin + SEL_O <= #1 {3'b000, selects[0]}; + DAT_O <= #1 {data[7:0], data[7:0], data[7:0], data[7:0]}; + end + 2'b01: begin + SEL_O <= #1 {2'b00, selects[1:0]}; + DAT_O <= #1 {data[15:0], data[15:0]}; + end + 2'b10: begin + SEL_O <= #1 selects; + DAT_O <= #1 data[dw-1:0]; + end + endcase + end + end + + always @(posedge CLK_I) + begin + if (RST_I) + WE_O <= 1'b0; + else if (GO) + WE_O <= #1 write_flag; + end + +endmodule + + + + + Index: wb_prefetch_spram/tags/first/bench/verilog/tb_clkrst.v =================================================================== --- wb_prefetch_spram/tags/first/bench/verilog/tb_clkrst.v (nonexistent) +++ wb_prefetch_spram/tags/first/bench/verilog/tb_clkrst.v (revision 10) @@ -0,0 +1,82 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Clock and Reset Generator //// +//// //// +//// This file is part of the WISHBONE prefetch memory block: //// +//// http://www.opencores.org/cvsweb.shtml/wb_prefetch_spram/ //// +//// //// +//// Description //// +//// Clock and reset generator. //// +//// //// +//// To Do: //// +//// Nothing //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// + +`include "timescale.v" + +module wb_clkrst( + // Clk & Rst Interface + clk_o, rst_o +); + +// +// Clock and Reset Interface +// +output clk_o; +output rst_o; + +// +// Internal registers +// +reg clk_o; +reg rst_o; + +initial begin + clk_o = 0; + rst_o = 0; + #1; + rst_o = 1; + #`Trst; + rst_o = 0; +end + +// +// Clock generator +// +always clk_o = #`Thper ~clk_o; + +endmodule Index: wb_prefetch_spram/tags/first/bench/verilog/tb_top.v =================================================================== --- wb_prefetch_spram/tags/first/bench/verilog/tb_top.v (nonexistent) +++ wb_prefetch_spram/tags/first/bench/verilog/tb_top.v (revision 10) @@ -0,0 +1,122 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Prefetch Single-Port RAM Top Level Test Bench //// +//// //// +//// This file is part of the WISHBONE prefetch memory block: //// +//// http://www.opencores.org/cvsweb.shtml/wb_prefetch_spram/ //// +//// //// +//// Description //// +//// Top level test bench. //// +//// //// +//// To Do: //// +//// Nothing //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// + +`include "timescale.v" + +module tb_top; + +// +// Width of address and data buses +// +parameter aw = `RAM_ADDRWIDTH; +parameter dw = 16; + +// +// Internal wires +// +wire clk; +wire rst; +wire cyc; +wire [aw-1:0] adr; +wire [dw-1:0] dat_prefetch; +wire [dw-1:0] dat_bfm; +wire [3:0] sel; +wire we; +wire stb; +wire ack; +wire err; + +// +// WISHBONE Prefetch single-port SRAM block +// +wb_prefetch_spram #(aw, dw) wb_prefetch_spram( + // WISHBONE Interface + .clk_i(clk), + .rst_i(rst), + .cyc_i(cyc), + .adr_i(adr), + .dat_i(dat_prefetch), + .sel_i(sel), + .we_i(we), + .stb_i(stb), + .dat_o(dat_bfm), + .ack_o(ack), + .err_o(err) +); + +// +// WISHBONE Bus Functional Model +// +wb_master #(aw, dw) wb_master( + // WISHBONE Interface + .CLK_I(clk), + .RST_I(rst), + .TAG_I(4'b0000), + .TAG_O(), + .CYC_O(cyc), + .ADR_O(adr), + .DAT_O(dat_prefetch), + .SEL_O(sel), + .WE_O(we), + .STB_O(stb), + .DAT_I(dat_bfm), + .ACK_I(ack), + .ERR_I(err), + .RTY_I(1'b0) +); + +// +// WISHBONE Clock & Reset Generator +// +wb_clkrst wb_clkrst( + // Clk & Rst Interface + .clk_o(clk), + .rst_o(rst) +); + +endmodule Index: wb_prefetch_spram/tags/first/bench/verilog/tb_tasks.v =================================================================== --- wb_prefetch_spram/tags/first/bench/verilog/tb_tasks.v (nonexistent) +++ wb_prefetch_spram/tags/first/bench/verilog/tb_tasks.v (revision 10) @@ -0,0 +1,236 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Test Tasks for WISHBONE Prefetching Single-Port RAM //// +//// //// +//// This file is part of the WISHBONE prefetch memory block: //// +//// http://www.opencores.org/cvsweb.shtml/wb_prefetch_spram/ //// +//// //// +//// Description //// +//// First half of the RAM is initialized with random data //// +//// and then it is copied to second half of the RAM. During //// +//// copy random delays are inserted. //// +//// //// +//// To Do: //// +//// Nothing //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// + +`include "timescale.v" + +module tb_tasks; + +// +// Tests description +// +task describe_test; +begin + $display; + $display(" Verification of the WISHBONE Prefetch Single-Port Synchronous RAM"); + $display; + $display(" Abbrev:"); + $display(" w single write transfer"); + $display(" r single read transfer"); + $display(" Brr block read transfer with two reads"); + $display(" Bww block write transfer with two writes"); + $display(" . inserted clock cycle delay"); + $display; + $display(" I. One half of the RAM is preinitialized with random data. RAM is "); + $display(" written using WISHBONE single writes."); + $display; + $display(" II. After that main part of the test is performed. Preinitialized "); + $display(" half of the RAM is read with randomly long WISHBONE block reads. "); + $display(" Between each beat of a block read zero or random number of clock "); + $display(" cycles are inserted."); + $display(" Each block of data is then written into second half of the RAM. "); + $display(" Data is written using WISHBONE block writes with randomly inserted "); + $display(" clock cycle delays between two writes."); + $display(" "); + $display(" III. To verify correct operation of prefetch logic, both halfs of "); + $display(" prefetching RAM are compared. To pass the test they must match."); + $display(" "); + $display(" Total RAM size: %d words by 32 bits", `RAM_WORDS); +end +endtask + +// +// Init 1st half of RAM +// +task init_1sthalf; +reg [31:0] addr; +reg [31:0] data; +begin + $display; + $display("I. Initializing 1st half of the RAM: "); + for (addr = 0; addr < `RAM_WORDS/2; addr = addr + 1) begin + $write("w"); + data = $random; + tb_top.wb_master.wr(addr, data, 4'b1111); + end + $display(" Done."); +end +endtask + +// +// Copy 1st half of RAM into 2nd half +// +task copy_1stto2ndhalf; +reg [31:0] saddr; +reg [31:0] daddr; +reg [31:0] data [63:0]; +reg [3:0] rndnum; +reg [1:0] delay; +reg end_flag; +reg [2:0] beats; +reg [2:0] current_beat; +integer start_time; +integer end_time; +begin + $display; + $display("II. Copying 1st half of the RAM into 2nd half:"); + daddr = `RAM_WORDS/2; + start_time = $time; + for (saddr = 0; saddr < `RAM_WORDS/2; saddr = saddr) begin + beats = $random; + if (!beats) + beats = 1; + + // + // Block read from first half of RAM. Beats are spaced with random delays. + // + $write("B"); + for (current_beat = beats; current_beat; current_beat = current_beat - 1) begin + $write("r"); + if (current_beat == 1) + end_flag = 1; + else + end_flag = 0; + rndnum = $random; + if (rndnum == 0) + delay = $random; + else + delay = 0; + while (delay) + @(posedge tb_top.clk) begin + delay = delay - 1; + $write("."); + end + tb_top.wb_master.blkrd(saddr, end_flag, data[current_beat]); + saddr = saddr + 1; + end + + // + // Block write into second half of RAM. Beats are spaced with random delays. + // + $write("B"); + for (current_beat = beats; current_beat; current_beat = current_beat - 1) begin + $write("w"); + if (current_beat == 1) + end_flag = 1; + else + end_flag = 0; + rndnum = $random; + if (rndnum == 0) + delay = $random; + else + delay = 0; + while (delay) + @(posedge tb_top.clk) begin + delay = delay - 1; + $write("."); + end + if (daddr < `RAM_WORDS) begin + tb_top.wb_master.blkwr(daddr, data[current_beat], 4'b1111, end_flag); + daddr = daddr + 1; + end + end + end + $display(" Done."); + end_time = $time; + $display; + $display(" Clock cycles to complete copy: %d", (end_time - start_time) / (`Thper*2)); +end +endtask + +// +// Compare 1st half and 2nd half of the RAM and return result of the comparison +// +task comp_1stand2ndhalf; +reg [31:0] saddr; +reg [31:0] sdata; +reg [31:0] daddr; +reg [31:0] ddata; +integer errors; +begin + $display; + $display("III. Comparing 1st half and 2nd half of the RAM."); + errors = 0; + for (saddr = 0; saddr < `RAM_WORDS/2; saddr = saddr + 1) begin + daddr = saddr + `RAM_WORDS/2; + tb_top.wb_master.rd(saddr, sdata); + tb_top.wb_master.rd(daddr, ddata); + if (sdata != ddata) begin + $write("Locations %h and %h are different. ", saddr, daddr); + $display("First data %h and second data %h.", sdata, ddata); + errors = errors + 1; + end + end + $display; + if (!errors) + $display(" Test Passed"); + else + $display(" ERRORS: %d", errors); + $display; +end +endtask + +// +// Run the test +// +initial begin +`ifdef VCD_DUMP + $dumpfile("../out/dump.vcd"); + $dumpvars(0); +`endif + #`Trst; + describe_test; + init_1sthalf; + copy_1stto2ndhalf; + comp_1stand2ndhalf; + $finish; +end + +endmodule + Index: wb_prefetch_spram/tags/first/rtl/verilog/generic_spram.v =================================================================== --- wb_prefetch_spram/tags/first/rtl/verilog/generic_spram.v (nonexistent) +++ wb_prefetch_spram/tags/first/rtl/verilog/generic_spram.v (revision 10) @@ -0,0 +1,224 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Generic Single-Port Synchronous RAM //// +//// //// +//// This file is part of memory library available from //// +//// http://www.opencores.org/cvsweb.shtml/generic_memories/ //// +//// //// +//// Description //// +//// This block is a wrapper with common single-port //// +//// synchronous memory interface for different //// +//// types of ASIC and FPGA RAMs. Beside universal memory //// +//// interface it also provides behavioral model of generic //// +//// single-port synchronous RAM. //// +//// It should be used in all OPENCORES designs that want to be //// +//// portable accross different target technologies and //// +//// independent of target memory. //// +//// //// +//// Supported ASIC RAMs are: //// +//// - Artisan Single-Port Sync RAM //// +//// - Avant! Two-Port Sync RAM (*) //// +//// - Virage Single-Port Sync RAM //// +//// - Virtual Silicon Single-Port Sync RAM //// +//// //// +//// Supported FPGA RAMs are: //// +//// - Xilinx Virtex RAMB4_S16 //// +//// //// +//// To Do: //// +//// - xilinx rams need external tri-state logic //// +//// - fix avant! two-port ram //// +//// - add additional RAMs (Altera etc) //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// + +`include "timescale.v" + +module generic_spram( + // Generic synchronous single-port RAM interface + clk, rst, ce, we, oe, addr, di, do +); + +// +// Default address and data buses width +// +parameter aw = 12; +parameter dw = 16; + +// +// Generic synchronous single-port RAM interface +// +input clk; // Clock +input rst; // Reset +input ce; // Chip enable input +input we; // Write enable input +input oe; // Output enable input +input [aw-1:0] addr; // address bus inputs +input [dw-1:0] di; // input data bus +output [dw-1:0] do; // output data bus + +// +// Internal wires and registers +// + + +`ifdef ARTISAN_SSP + +// +// Instantiation of ASIC memory: +// +// Artisan Synchronous Single-Port RAM (ra1sh) +// +artisan_ssp #(dw, 2<q data output timing as w/o prefetch. //// +//// //// +//// Latency/bandwidth for 4-beat WISHBONE read block transfer: //// +//// - async memory: 4 clock cycles //// +//// - sync memory w/o prefetching: 8 clock cycles //// +//// - sync memory w/ prefetching: 4+1 clock cycles //// +//// //// +//// To Do: //// +//// Nothing //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// + +`include "timescale.v" + +// +// Bits in address that are incremented in a burst. +// +// Example for default of 1:0 can be: +// 2,3,0,1 +// +`define BURST_BITS 1:0 +`define FIXED_LOW_BIT 2 + +// +// Define this to check for strict 32-bit access +// +`define STRICT_32BIT_ACCESS + +module wb_prefetch_spram( + // WISHBONE Interface + clk_i, rst_i, cyc_i, adr_i, dat_i, sel_i, we_i, stb_i, + dat_o, ack_o, err_o +); + +// +// Default width of address and data buses +// +parameter aw = 12; +parameter dw = 32; + +// +// WISHBONE Interface +// +input clk_i; // Clock +input rst_i; // Reset +input cyc_i; // cycle valid input +input [aw-1:0] adr_i; // address bus inputs +input [dw-1:0] dat_i; // input data bus +input [3:0] sel_i; // byte select inputs +input we_i; // indicates write transfer +input stb_i; // strobe input +output [dw-1:0] dat_o; // output data bus +output ack_o; // normal termination +output err_o; // termination w/ error + +// +// Internal wires and registers +// +wire [aw-1:0] predicted_addr; // Predicted address +wire [aw-1:0] ram_addr; // Address used to address RAM block +wire correct_data; // Current RAM output data is valid +reg [aw-1:0] last_addr; // Saved ram_addr +wire valid_cycle; // Valid WISHBONE cycle + +// +// Combinatorial logic +// + +// +// If STRICT_32BIT_ACCESS is defined, assert err_o when access is +// not completely 32-bit. +// +`ifdef STRICT_32BIT_ACCESS +assign err_o = valid_cycle & (sel_i != 4'b1111); +`else +assign err_o = 1'b0; +`endif + +// +// Valid WSIHBONE cycles when both cyc_i and stb_i are assrted +// +assign valid_cycle = cyc_i & stb_i; + +// +// Generate prefetch address by using address from the last RAM access and +// incrementing burst part of the address +// +assign predicted_addr = { last_addr[aw-1:`FIXED_LOW_BIT], last_addr[`BURST_BITS] + 1'b1 }; + +// +// Address RAM with WISHBONE address if last RAM access was mispredicted +// or if current WISHBONE access is write +// +assign ram_addr = (~correct_data | we_i) ? adr_i : predicted_addr; + +// +// RAM's current output data is the same as data request by WISHBONE master +// +assign correct_data = (adr_i == last_addr); +assign ack_o = correct_data & valid_cycle; + +// +// Address used to address RAM at the last WISHBONE read beat +// +always @(posedge clk_i or posedge rst_i) + if (rst_i) + last_addr <= #1 {aw{1'b0}}; + else if (valid_cycle) + last_addr <= #1 ram_addr; + +// +// Instantiation of single-port synchronous RAM +// +generic_spram #(aw, dw) spram ( + .clk(clk_i), + .rst(rst_i), + .addr(ram_addr), + .di(dat_i), + .ce(valid_cycle), + .we(we_i), + .oe(valid_cycle), + .do(dat_o) +); + +endmodule Index: wb_prefetch_spram/tags/first/sim/rtl_sim/src/timescale.v =================================================================== --- wb_prefetch_spram/tags/first/sim/rtl_sim/src/timescale.v (nonexistent) +++ wb_prefetch_spram/tags/first/sim/rtl_sim/src/timescale.v (revision 10) @@ -0,0 +1,3 @@ +// synopsys translate_off +`timescale 1ns/10ps +// synopsys translate_off Index: wb_prefetch_spram/tags/first/sim/rtl_sim/bin/sim.sh =================================================================== --- wb_prefetch_spram/tags/first/sim/rtl_sim/bin/sim.sh (nonexistent) +++ wb_prefetch_spram/tags/first/sim/rtl_sim/bin/sim.sh (revision 10) @@ -0,0 +1,102 @@ +#!/bin/bash + +# +# This script runs RTL and gate-level simulation using different simultion tools. +# Right now Cadence Verilog-XL and NCSim are supported. +# +# Author: Damjan Lampret +# + +# +# User definitions +# + +# Set simulation tool you are using (xl, ncsim) +SIMTOOL=xl + +# Set test bench top module(s) +TB_TOP="tb_tasks" + +# Set include directories +INCLUDE_DIRS="../../../rtl/verilog ../../../bench/verilog ../src" + +# Set test bench files +BENCH_FILES="../../../bench/verilog/tb_defines.v ../../../bench/verilog/wb_master.v" +BENCH_FILES=$BENCH_FILES" ../../../bench/verilog/tb_clkrst.v ../../../bench/verilog/tb_top.v ../../../bench/verilog/tb_tasks.v " + +# Set RTL source files +RTL_FILES="../../../rtl/verilog/wb_prefetch_spram.v ../../../rtl/verilog/generic_spram.v" + +# Set gate-level netlist files +GATE_FILES="../../../syn/out/final_wb_prefetch_spram.v" + +# Set libraries (standard cell etc.) +LIB_FILES="/libs/Virtual_silicon/UMCL18U250D2_2.1/verilog_simulation_models/*.v" + +# Set parameters for simulation tool +if [ $SIMTOOL == xl ]; then + PARAM="+turbo+3 -q -l ../log/verilog.log" + for i in $INCLUDE_DIRS; do + INCDIR=$INCDIR" +incdir+$i" + done +elif [ $SIMTOOL == ncsim ]; then + NCPREP_PARAM="-UPDATE +overwrite -l ../log/ncprep.log" + NCSIM_PARAM="-MESSAGES -NOCOPYRIGHT" + for i in $INCLUDE_DIRS; do + INCDIR=$INCDIR" +incdir+$i" + done +else + echo "$SIMTOOL is unsupported simulation tool." + exit 0 +fi + +# +# Don't change anything below unless you know what you are doing +# + +# Run simulation in sim directory +cd ../run + +# Run actual simulation + +# Cadence Verilog-XL +if [ $SIMTOOL == xl ]; then + + # RTL simulation + if [ "$1" == rtl ]; then + verilog $PARAM $INCDIR $BENCH_FILES $RTL_FILES + + # Gate-level simulation + elif [ "$1" == gate ]; then + verilog $PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES + + # Wrong parameter or no parameter + else + echo "Usage: $0 [rtl|gate]" + exit 0 + fi + +# Cadence Ncsim +elif [ $SIMTOOL == ncsim ]; then + + # RTL simulation + if [ "$1" == rtl ]; then + ncprep $NCPREP_PARAM $INCDIR $BENCH_FILES $RTL_FILES + ./RUN_NC + + # Gate-level simulation + elif [ "$1" == gate ]; then + ncprep $NCPREP_PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES + ./RUN_NC + + # Wrong parameter or no parameter + else + echo "Usage: $0 [rtl|gate]" + exit 0 + fi + +# Unsupported simulation tool +else + echo "$SIMTOOL is unsupported simulation tool." + exit 0; +fi

wb_prefetch_spram/tags/first/sim/rtl_sim/bin/sim.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: wb_prefetch_spram/tags =================================================================== --- wb_prefetch_spram/tags (nonexistent) +++ wb_prefetch_spram/tags (revision 10)

wb_prefetch_spram/tags Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ##