OpenCores
URL https://opencores.org/ocsvn/s1_core/s1_core/trunk

Subversion Repositories s1_core

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 102 to Rev 103
    ↔ Reverse comparison
  •

Rev 102 → Rev 103

/trunk/tools/src/linker.map
1,6 → 1,6
MEMORY {
rom : ORIGIN = 0xFFF0000020, LENGTH = 4096
ram : ORIGIN = 0x000004C000, LENGTH = 65536
ram : ORIGIN = 0x0000040000, LENGTH = 65536
}
 
SECTIONS {
/trunk/tools/src/dump2hex.c
13,9 → 13,6
char line[200];
char* right;
 
// To start from RAM address 0x00000400C0 (see linker.map)
//printf("@%X\n", (0xC0>>3));
 
// Parse the standard input
while(!feof(stdin)) {
 
/trunk/tools/bin/compile_test
1,13 → 1,13
#!/bin/bash
#
# Compile a test for the S1 and build the memory.hex file.
# Compile a test for the S1 Core and build the files
# rom_harness.hex and ram_harness.hex.
#
# Parameter is test name without extension (e.g. to compile
# $S1_ROOT/tests/hello.c) run "compile_test hello".
# $S1_ROOT/tests/hello.c) just run "compile_test hello".
#
# Notes:
# 1) requires sparc64-linux-gcc (see Download section on srisc.com);
# 2) the generated image is currently not used by simulations.
# Note: requires sparc64-linux-gcc (see Download section on
# http://www.srisc.com).
 
if [ -z "$S1_ROOT" ]; then echo "***ERROR***: S1_ROOT variable is undefined, please set it and run 'source sourceme'."; exit 1; fi
if ! [ -d "$S1_ROOT" ]; then echo "***ERROR***: directory '$S1_ROOT' does not exist, please check it and run 'source sourceme' again."; exit 1; fi
34,13 → 34,13
# Compile the boot code
sparc64-linux-as -ah -am -o boot/boot.bin boot/boot.s
sparc64-linux-objdump -d -EB -w -z boot/boot.bin > boot/boot.dump
grep " " boot/boot.dump | egrep -v "file format" | dump2hex.bin > boot/mem_RED_SEC.image
grep " " boot/boot.dump | egrep -v "file format" | dump2hex.bin > boot/rom_harness.hex
 
# Compile the C test
sparc64-linux-gcc -c -O0 $1.c
sparc64-linux-ld -Ur --script=$S1_ROOT/tools/src/linker.map -EB -o $1.bin $1.o
sparc64-linux-objdump -d -EB -w -z $1.bin > $1.dump
grep " " $1.dump | egrep -v "file format" | dump2hex.bin > boot/mem_RED_EXT_SEC.image
grep " " $1.dump | egrep -v "file format" | dump2hex.bin > ram_harness.hex
 
rm -f *.o *~ *.bin *.dump # Make clean
#rm -f *.o *~ *.bin *.dump # Make clean
 
/trunk/tools/bin/run_icarus
4,5 → 4,13
if ! [ -d "$S1_ROOT" ]; then echo "***ERROR***: directory '$S1_ROOT' does not exist, please check it and run 'source sourceme' again."; exit 1; fi
 
cd $S1_ROOT/run/sim/icarus
ln -f -s ../../../tests/boot/mem_*.image .
./testbench 2>&1 | tee sim.log
ln -f -s $S1_ROOT/tests/boot/rom_harness.hex .
ln -f -s $S1_ROOT/tests/ram_harness.hex .
 
./testbench > sim.log
echo "Simulation completed!"
echo "To see the output:"
echo " less $S1_ROOT/run/sim/icarus/sim.log"
echo "Too watch the waveforms:"
echo " gtkwave $S1_ROOT/run/sim/icarus/trace.vcd"
 
/trunk/sourceme
1,7 → 1,7
 
# General paths settings
export S1_ROOT=~/s1_core
export T1_ROOT=~/opensparc-t1
export T1_ROOT=/opt/opensparc-t1
export PATH=.:$S1_ROOT/tools/bin:$PATH
 
# Filelist names
/trunk/tests/boot/mem_RED_EXT_SEC.image
1,52 → 1,11
@18
0300000023000000
82106000a2146000
83287020a2144001
82102010e2f04840
a3480000819c6820
82102018c0f00a01
c0f00b0103000000
2300000082106000
a214600083287020
a2144001e2f00960
a346800082102300
a20c4001a3347008
0300000005000000
821060008410a000
8328702084108001
a32c7003c4588011
82102080c4f04b00
210000002f000000
a0142000ae15e000
a12c3020ae15c010
8b9dc00021000000
03000000a0142000
82106000a12c3020
821040108528b007
82004002e2584000
e2f006e0e2586008
e2f007e0e2586010
e2f006a0e2586020
e2f006c0e2586018
e2f007a0e2586028
e2f007c0e2586040
e2f00660e2586048
e2f00760e2586050
e2f00620e2586060
e2f00640e2586058
e2f00720e2586068
e2f0074094102080
c0f28ae0c0f28be0
a2102008c0f44420
a2102010c0f44420
a210200ce2f008a0
0300000005000000
821060008410a000
8328702084108001
874800008f902001
0300000009000000
8210600088112000
8328702088110001
839900008f902000
9010200081c08000
8198280081982800
0100000001000000
83287006c277a7e7
c45fa7e703306830
821061a0c2708000
8210232b83287006
c277a7e7c45fa7e7
033eae8482106210
c270800082102000
83386000b0100001
81cfe00801000000
0100000001000000
/trunk/tests/boot/mem_RED_SEC.image
1,29 → 1,35
@0
0100000001000000 0100000001000000 0100000001000000 0100000001000000
0300000005000100 821060008410a0c0 8328702084108001 81c0800001000000
0300000005000100 821060008410a2d0 8328702084108001 81c0800001000000
0300000005000100 821060008410a310 8328702084108001 81c0800001000000
0300000005000100 821060008410a32c 8328702084108001 81c0800001000000
0100000001000000 0100000030680005 0100000001000000 0100000001000000
8210209884102810 8328702084108001 c258800082086004 02c8401c84102096
8528b02007109081 821020428610e005 832870208610c001 c670a02807105041
821020418610e106 832870208610c001 c670a0300300601c 072103838210600a
8610e00283287020 8610c001c6708000 c258800080a04003 0268000301000000
91d0200101000000 0300000005000100 821060008410a0c0 8328702084108001
81c0800001000000 8f46800003000007 821063008e09c001 8f31f0088e09e01f
8c09e0038f31f002 8a09e0078e100005 0ac9802482102098 8410283083287020
84108001c8588000 86103fff8600e001 8209200102f87ffe 8931300480a0c005
126800188c100003 861020a88728f020 84102041c470c000 8600e040c470c000
8600e040c470c000 8600e040c470c000 80a180071268000b 861020a88728f020
821020000ac84000 8220600184102004 c070c0008420a001 0af8bffe8600e040
0300000005000100 821060008410a0c0 8328702084108001 81c0800001000000
821020000ac8400c 0100000084102096 8528b02007080000 8728f020c258a008
880840030ac9003a 0100000086104003 c670a00882102098 8410283083287020
84108001c6588000 a346800003000007 82106300a20c4001 a33470088210203f
822040118728d001 8728f0010ac8c028 01000000ac102097 ad2db02003000004
050000080700000c a005a130a6102001 e6740000e6740001 e6740002e6740003
a005a108e6740000 e6740001e6740002 e6740003a005a218 a610200fe6740000
e6740001e6740002 e6740003a005a1a0 a6102004e6740000 e6740001e6740002
e6740003a6102006 e6740000e6740001 e6740002e6740003 a6102007e6740000
e6740001e6740002 e674000303000000 0500010082106000 8410a0c083287020
8410800181c08000 0100000030680005 0100000001000000 0100000001000000
82102010e2f04840
a2102003e2f008a0
a3480000a40c6820
a41ca800819c4012
82102018c0f00a01
c0f00b0103000000
8210600083287020
23000000a2144001
a2146003e2f00960
0300000082106000
8328702023000200
a2144001a2146000
8b9dc00082102030
84100000c0f04a00
c0f08aa08400a008
80a0a20012bffffc
0100000082102030
84100000c0f04b00
c0f08ba08400a008
80a0a20012bffffc
01000000c0f00c00
82102008c0f00c01
a2102008c0f44420
a2102010c0f44420
a210200fe2f008a0
0300000005000100
8210000184100002
8328702084108001
874800008f902001
0300000082106000
8328702023000000
a2144001a2146000
839900008f902000
9010200081c08000
81c0800081c08000
/trunk/tests/boot/boot.s
82,16 → 82,8
stxa %l1, [%g0] (69)
 
!! Set hpstate.red = 0 and hpstate.enb = 1
/*
!! SunStudio version
rdhpr %hpstate, %l1
wrhpr %l1, 0x820, %hpstate
*/
!! GCC version
rdhpr %hpstate, %l1
and %l1,0x820,%l2
xor %l2,0x800,%l2
wrhpr %l1,%l2,%hpstate !! ensure red=0 and enb=1 leaving the other 2 bits of the register unchanged
 
!! Initialize Interrupt Queue Registers: currently unused in S1 Core
/*
353,7 → 345,7
*/
!! GCC version
sethi %hi(0), %g1
sethi %hi(0x144000), %g2
sethi %hi(0x40000), %g2 !! New jump address in memory (used by last op of this file)
mov %g1, %g1
mov %g2, %g2
sllx %g1, 0x20, %g1
360,7 → 352,7
or %g2, %g1, %g2
rdhpr %hpstate, %g3
wrpr 1, %tl !! current trap level = 1
wrpr 1, %tl !! current trap level = 1
 
!! HTSTATE
/*
/trunk/hdl/filelist.dc
1,139 → 1,139
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/behav/sparc_libs/m1_lib.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/behav/sparc_libs/u1_lib.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_divcntl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/test_stub_bist.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ffu.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_prencoder16.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_rml.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_tlbdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_qdp1.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_irf_register.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_dec.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_milfsm.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_pcx_qmon.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_dc_parity_gen.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_div_yreg.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_eclccr.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ffu_vis.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_rf16x32.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_lfsr5.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_dctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_stb_rwdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc_dec.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrfsm.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_tlb.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/cpx_spc_buf.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_mul_top.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_inc3.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_rf32x152b.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_dcl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_byp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/cpx_spc_rpt.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_tlu_intdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_reg.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_dctldp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_qctl2.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_par16.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/test_stub_scan.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/mul64.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_qdp2.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_dcd.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog_rs1.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_incr64.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/synchronizer_asr.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_irf.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_cmp35.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_hyperv.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_par32.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_tlu_dec64.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_alulogic.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_errdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_swl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_misctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_rrobin_picker.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_rrobin_picker2.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_frf.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ffu_dp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_aluor32.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_mdqctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_scm.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_alu_16eql.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_cwp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_incr46.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_stb_rwctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_par34.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_tdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_div_32eql.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/swrvr_dlib.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_idct.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_dcdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_fdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_rf32x80.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_ctr5.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_tagdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_aluaddsub.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_stb_ctldp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_aluadder64.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_eclcomp7.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_cnt6.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_tlu_intctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_stb_ctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_sscan.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_wseldp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_rndrob.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_icd.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_byp_eccgen.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_mul_cntl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_invctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/cmp_sram_redhdr.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/cluster_header.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_eccctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl_visctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrcmpl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_mul_dp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_mmu_ctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ffu_part_add32.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_qctl1.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_wb.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_lru4.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_mmu_dp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_fcl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_rf16x160.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_div.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_pib.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/swrvr_clib.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_errctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_dcache_lfsr.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_tlu_zcmp64.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_clk_cl_sparc_cmp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_aluzcmp64.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_mbist.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_excpctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_rndrob.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_swpla.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_addern_32.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_tlu_penc64.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_imd.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_aluspr.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_alu.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_tcl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_shft.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_asi_decode.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/s1_top/rst_ctrl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/s1_top/int_ctrl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/s1_top/spc2wbm.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ffazzino/s1_core/hdl/rtl/s1_top/s1_top.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/behav/sparc_libs/m1_lib.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/behav/sparc_libs/u1_lib.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_tdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_asi_decode.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_div_32eql.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_intctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_cmp35.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_idct.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_scm.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_dec.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_ctr5.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_errctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/cpx_spc_rpt.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dctldp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_incr64.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl_visctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_shft.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_tcl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_misctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_pcx_qmon.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluadder64.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_penc64.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_mul_top.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_irf_register.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_rndrob.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_dcd.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/synchronizer_asr.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/cpx_spc_buf.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_zcmp64.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_incr46.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_par32.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/swrvr_clib.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_hyperv.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_mul_dp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/cmp_sram_redhdr.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_lfsr5.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_vis.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_milfsm.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_dp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_mul_cntl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_stb_ctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_rndrob.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_imd.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dcdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_swpla.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_fcl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_byp_eccgen.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_dec64.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_wseldp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_pib.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_qdp2.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluzcmp64.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_prencoder16.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_qdp1.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dcache_lfsr.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_icd.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_par34.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/test_stub_bist.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/cluster_header.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_divcntl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_tlbdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_eccctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_byp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_stb_rwdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_part_add32.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_clk_cl_sparc_cmp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_rf16x32.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_dcl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_intdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_rrobin_picker2.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/swrvr_dlib.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_div.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_addern_32.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_mmu_dp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_inc3.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dc_parity_gen.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_div_yreg.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_alu.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_stb_ctldp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_sscan.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_lru4.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_alulogic.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_eclcomp7.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_qctl1.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluaddsub.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_frf.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_par16.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_alu_16eql.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_errdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_swl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_rf32x80.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_rrobin_picker.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_cnt6.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc_dec.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_excpctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_invctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_cwp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_tlb.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog_rs1.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluspr.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_rml.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrfsm.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_mbist.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_reg.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluor32.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_mdqctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_tagdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_fdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_rf32x152b.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/test_stub_scan.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_irf.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_mmu_ctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_stb_rwctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrcmpl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_eclccr.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_qctl2.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_rf16x160.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/mul64.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_wb.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/s1_top/rst_ctrl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/s1_top/int_ctrl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/s1_top/spc2wbm.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/s1_top/s1_top.v
 
# The Tcl script under $S1_ROOT/tools/src/build_dc.cmd is attached at the end of the filelist for DC;
# if you modify this file *REMEMBER* to run 'update_filelist' or you'll run the old version!!!
/trunk/hdl/filelist.icarus
1,142 → 1,142
/home/ffazzino/s1_core/hdl/behav/sparc_libs/m1_lib.v
/home/ffazzino/s1_core/hdl/behav/sparc_libs/u1_lib.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_divcntl.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/test_stub_bist.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ffu.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_prencoder16.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_rml.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_tlbdp.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_qdp1.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_irf_register.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_dec.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_milfsm.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_pcx_qmon.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_dc_parity_gen.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_div_yreg.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_eclccr.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ffu_vis.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_rf16x32.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_lfsr5.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_dctl.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_stb_rwdp.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc_dec.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrfsm.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_tlb.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/cpx_spc_buf.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_mul_top.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_inc3.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_rf32x152b.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_dcl.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_byp.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/cpx_spc_rpt.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_tlu_intdp.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_reg.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_dctldp.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_qctl2.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_par16.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/test_stub_scan.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/mul64.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_qdp2.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_dcd.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog_rs1.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_incr64.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/synchronizer_asr.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_irf.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_cmp35.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_hyperv.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_par32.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_tlu_dec64.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_alulogic.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_errdp.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_swl.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_misctl.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_rrobin_picker.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_rrobin_picker2.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_frf.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ffu_dp.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_aluor32.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_mdqctl.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_scm.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_alu_16eql.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_cwp.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_incr46.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_stb_rwctl.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_par34.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_tdp.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_div_32eql.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/swrvr_dlib.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_idct.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_dcdp.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_fdp.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_rf32x80.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_ctr5.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_tagdp.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_aluaddsub.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_stb_ctldp.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqdp.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_aluadder64.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_eclcomp7.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_cnt6.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_tlu_intctl.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_stb_ctl.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_sscan.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_wseldp.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_rndrob.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_icd.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_byp_eccgen.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_mul_cntl.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_invctl.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/cmp_sram_redhdr.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/cluster_header.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_eccctl.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl_visctl.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrcmpl.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_mul_dp.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_mmu_ctl.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqctl.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ffu_part_add32.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_qctl1.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_wb.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_lru4.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_mmu_dp.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_fcl.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_rf16x160.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_div.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_pib.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/swrvr_clib.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_errctl.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_dcache_lfsr.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_tlu_zcmp64.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_clk_cl_sparc_cmp.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_aluzcmp64.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_mbist.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_excpctl.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_rndrob.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_swpla.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_addern_32.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_tlu_penc64.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_imd.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_aluspr.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_alu.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_tcl.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_shft.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_asi_decode.v
/home/ffazzino/s1_core/hdl/rtl/s1_top/rst_ctrl.v
/home/ffazzino/s1_core/hdl/rtl/s1_top/int_ctrl.v
/home/ffazzino/s1_core/hdl/rtl/s1_top/spc2wbm.v
/home/ffazzino/s1_core/hdl/rtl/s1_top/s1_top.v
/home/ffazzino/s1_core/hdl/behav/testbench/mem_harness.v
/home/ffazzino/s1_core/hdl/behav/testbench/testbench.v
+incdir+/home/ffazzino/s1_core/hdl/rtl/s1_top
/home/fabrizio/s1_core/hdl/behav/sparc_libs/m1_lib.v
/home/fabrizio/s1_core/hdl/behav/sparc_libs/u1_lib.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_tdp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_asi_decode.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_div_32eql.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_intctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_cmp35.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_idct.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_scm.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_dec.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_ctr5.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_errctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/cpx_spc_rpt.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dctldp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_incr64.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl_visctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_shft.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_tcl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_misctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_pcx_qmon.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluadder64.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_penc64.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_mul_top.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_irf_register.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_rndrob.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_dcd.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/synchronizer_asr.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/cpx_spc_buf.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_zcmp64.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_incr46.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_par32.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/swrvr_clib.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_hyperv.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_mul_dp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/cmp_sram_redhdr.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_lfsr5.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_vis.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_milfsm.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_dp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_mul_cntl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_stb_ctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_rndrob.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_imd.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dcdp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_swpla.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_fcl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_byp_eccgen.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_dec64.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_wseldp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_pib.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_qdp2.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluzcmp64.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_prencoder16.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_qdp1.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dcache_lfsr.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_icd.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_par34.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/test_stub_bist.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/cluster_header.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_divcntl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_tlbdp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqdp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_eccctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_byp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_stb_rwdp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_part_add32.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_clk_cl_sparc_cmp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_rf16x32.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_dcl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_intdp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_rrobin_picker2.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/swrvr_dlib.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_div.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_addern_32.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_mmu_dp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_inc3.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dc_parity_gen.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_div_yreg.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_alu.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_stb_ctldp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_sscan.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_lru4.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_alulogic.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_eclcomp7.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_qctl1.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluaddsub.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_frf.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_par16.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_alu_16eql.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_errdp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_swl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_rf32x80.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_rrobin_picker.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_cnt6.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc_dec.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_excpctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_invctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_cwp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_tlb.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog_rs1.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluspr.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_rml.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrfsm.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_mbist.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_reg.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluor32.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_mdqctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_tagdp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_fdp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_rf32x152b.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/test_stub_scan.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_irf.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_mmu_ctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_stb_rwctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrcmpl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_eclccr.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_qctl2.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_rf16x160.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/mul64.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_wb.v
/home/fabrizio/s1_core/hdl/rtl/s1_top/rst_ctrl.v
/home/fabrizio/s1_core/hdl/rtl/s1_top/int_ctrl.v
/home/fabrizio/s1_core/hdl/rtl/s1_top/spc2wbm.v
/home/fabrizio/s1_core/hdl/rtl/s1_top/s1_top.v
/home/fabrizio/s1_core/hdl/behav/testbench/mem_harness.v
/home/fabrizio/s1_core/hdl/behav/testbench/testbench.v
+incdir+/home/fabrizio/s1_core/hdl/rtl/s1_top
+define+FPGA_SYN
+define+FPGA_SYN_1THREAD
+define+FPGA_SYN_NO_SPU
/trunk/hdl/rtl/sparc_core/sparc_ifu.v
1718,7 → 1718,7
lsu_ifu_cpxpkt_i1, lsu_ifu_asi_vld, lsu_ifu_asi_thrid,
lsu_ifu_asi_state, lsu_ifu_asi_load, lsu_ifu_asi_addr,
lsu_ifu_addr_real_l, grst_l, gdbginit_l, ffu_ifu_tid_w2,
ffu_ifu_stallreq, wbm_spc_stallreq, ffu_ifu_inj_ack, ffu_ifu_fst_ce_w,
ffu_ifu_stallreq,wbm_spc_stall,wbm_spc_resume, ffu_ifu_inj_ack, ffu_ifu_fst_ce_w,
ffu_ifu_fpop_done_w2, ffu_ifu_err_synd_w2, ffu_ifu_err_reg_w2,
ffu_ifu_ecc_ue_w2, ffu_ifu_ecc_ce_w2, ffu_ifu_cc_w2,
ffu_ifu_cc_vld_w2, exu_ifu_va_oor_m, exu_ifu_spill_e,
1808,7 → 1808,7
input ffu_ifu_fpop_done_w2; // To swl of sparc_ifu_swl.v
input ffu_ifu_fst_ce_w; // To swl of sparc_ifu_swl.v, ...
input ffu_ifu_inj_ack; // To errctl of sparc_ifu_errctl.v
input ffu_ifu_stallreq; input wbm_spc_stallreq; // To fcl of sparc_ifu_fcl.v
input ffu_ifu_stallreq;input wbm_spc_stall;input wbm_spc_resume; // To fcl of sparc_ifu_fcl.v
input [1:0] ffu_ifu_tid_w2; // To swl of sparc_ifu_swl.v, ...
input gdbginit_l; // To swl of sparc_ifu_swl.v, ...
input grst_l; // To swl of sparc_ifu_swl.v, ...
2572,7 → 2572,7
 
 
// Pipeline Control and Switch Logic
sparc_ifu_swl swl(
sparc_ifu_swl swl(.wbm_spc_stall(wbm_spc_stall),.wbm_spc_resume(wbm_spc_resume),
.so (scan0_2),
.si (scan0_1),
.thr_config_in_m (exu_tlu_wsr_data_m[2:0]),
2853,7 → 2853,7
.fcl_fdp_ctxt_sel_sw_bf_l(fcl_fdp_ctxt_sel_sw_bf_l),
.fcl_fdp_ctxt_sel_curr_bf_l(fcl_fdp_ctxt_sel_curr_bf_l));
 
sparc_ifu_fcl fcl( .wbm_spc_stallreq(wbm_spc_stallreq),
sparc_ifu_fcl fcl(
.so (short_scan1_1),
.si (short_si1),
.rst_tri_en (mux_drive_disable),
/trunk/hdl/rtl/sparc_core/sparc_ifu_fcl.v
290,7 → 290,7
itlb_fcl_tlbmiss_f_l, itlb_fcl_priv_s1, itlb_fcl_cp_s1,
itlb_fcl_imiss_s_l, fdp_fcl_pc_oor_vec_f, fdp_fcl_pc_oor_e,
fdp_fcl_op_s, fdp_fcl_op3_s, fdp_fcl_ibit_s, lsu_ifu_stallreq,
ffu_ifu_stallreq, wbm_spc_stallreq, ifq_fcl_stallreq, dtu_inst_anull_e,
ffu_ifu_stallreq, ifq_fcl_stallreq, dtu_inst_anull_e,
ifq_fcl_fill_thr, ifq_fcl_flush_sonly_e, tlu_ifu_trap_tid_w1,
tlu_ifu_trappc_vld_w1, tlu_ifu_trapnpc_vld_w1,
tlu_lsu_pstate_priv, tlu_lsu_pstate_am, tlu_hpstate_priv,
383,7 → 383,7
input fdp_fcl_ibit_s;
 
input lsu_ifu_stallreq,
ffu_ifu_stallreq, wbm_spc_stallreq,
ffu_ifu_stallreq,
ifq_fcl_stallreq;
input dtu_inst_anull_e;
2386,7 → 2386,7
ffu_stallreq_d1}),
.clk (clk), .se(se), .si(), .so());
assign all_stallreq = ifq_fcl_stallreq | wbm_spc_stallreq | lsu_stallreq_d1 |
assign all_stallreq = ifq_fcl_stallreq | lsu_stallreq_d1 |
ffu_stallreq_d1 | itlb_starv_alert;
 
// leave out stall from ifq which goes directly to swl
/trunk/hdl/rtl/sparc_core/sparc_ifu_thrcmpl.v
35,7 → 35,7
sw_cond_s, en_spec_g, atr_s, dtu_fcl_thr_active, ifq_dtu_thrrdy,
ifq_dtu_pred_rdy, exu_lop_done, branch_done_d, fixedop_done,
ldmiss, spec_ld_d, trap, retr_thr_wakeup, flush_wake_w2,
ldhit_thr, spec_ld_g, clear_wmo_e, wm_stbwait, stb_retry,
ldhit_thr, spec_ld_g, clear_wmo_e,wbm_spc_stall,wbm_spc_resume,wait_state, wm_stbwait, stb_retry,
rst_thread, trap_thrrdy, thr_s2, thr_e, thr_s1, fp_thrrdy,
lsu_ifu_ldst_cmplt, sta_done_e, killed_inst_done_e
);
63,7 → 63,7
ldhit_thr,
spec_ld_g;
 
input clear_wmo_e;
input clear_wmo_e;input wbm_spc_stall;input wbm_spc_resume;output wait_state;wire wait_next;
input [3:0] wm_stbwait,
stb_retry;
 
179,11 → 179,11
assign pred_ifq_rdy = ifq_dtu_pred_rdy & {4{~atr_s}} & dtu_fcl_thr_active;
assign imiss_thrrdy = pred_ifq_rdy | ifq_dtu_thrrdy;
// assign completion = imiss_thrrdy & (~(wm_other | wm_stbwait) |
// assign completion[0] = imiss_thrrdy & (~(wm_other | wm_stbwait) |
// other_thrrdy) | //see C1
// other_thrrdy & (~(wm_imiss | wmi_nxt));
 
// assign completion = (imiss_thrrdy & ~(wm_other | wm_stbwait) |
// assign completion[0] = (imiss_thrrdy & ~(wm_other | wm_stbwait) |
// other_thrrdy & ~(wm_stbwait | wm_imiss) |
// stb_retry & ~(wm_other | wm_imiss) |
// imiss_thrrdy & other_thrrdy & ~wm_stbwait |
190,10 → 190,10
// imiss_thrrdy & stb_retry & ~wm_other |
// stb_retry & other_thrrdy & ~wm_imiss);
 
assign completion = ((imiss_thrrdy | ~wm_imiss) &
assign completion[0] = ((imiss_thrrdy | ~wm_imiss) &
(other_thrrdy | ~wm_other) &
(stb_retry | ~wm_stbwait) &
(wm_imiss | wm_other | wm_stbwait));
(wm_imiss | wm_other | wm_stbwait|wait_state));
 
// C1: should we do ~(wm_other | wmo_nxt)??
// When an imiss is pending, we cannot be doing another fetch, so I
201,4 → 201,9
// though, unfortunately this results in a timing problem on swc_s
// and trap
assign wait_next=wbm_spc_stall|(wait_state & ~wbm_spc_resume);
dffr wait_ff(.din(wait_next),.q(wait_state),.clk(clk),.rst(reset),.se(se),.si(),.so());
assign completion[1]=completion[0];
assign completion[2]=completion[0];
assign completion[3]=completion[0];
endmodule // sparc_ifu_thrcmpl
/trunk/hdl/rtl/sparc_core/sparc_ifu_swl.v
238,7 → 238,7
fcl_swl_swout_f, fcl_swl_swcvld_s, fdp_fcl_swc_s2,
fcl_ifq_icmiss_s1, fcl_dtu_inst_vld_e, fcl_dtu_intr_vld_e,
fcl_dtu_inst_vld_d, erb_dtu_ifeterr_d1, dtu_inst_anull_e,
const_cpuid, thr_config_in_m, dec_swl_wrt_tcr_w,
const_cpuid, thr_config_in_m,wbm_spc_stall,wbm_spc_resume, dec_swl_wrt_tcr_w,
dec_swl_st_inst_d, extra_longlat_compl
);
 
337,7 → 337,7
input [3:0] const_cpuid; // use 4 bits to allow future
// expansion to 16 cores
 
input [2:0] thr_config_in_m; // write data to thread status reg
input [2:0] thr_config_in_m;input wbm_spc_stall;input wbm_spc_resume;wire wait_state; // write data to thread status reg
input dec_swl_wrt_tcr_w; // write signal for thr status reg
input dec_swl_st_inst_d;
 
732,7 → 732,7
//-----------------
// completion logic
//-----------------
sparc_ifu_thrcmpl compl(
sparc_ifu_thrcmpl compl(.wbm_spc_stall(wbm_spc_stall),.wbm_spc_resume(wbm_spc_resume),.wait_state(wait_state),
.reset (dtu_reset),
/*AUTOINST*/
// Outputs
1129,9 → 1129,9
// resum_thread & (~wm_imiss | ifq_dtu_thrrdy);
//`else
assign start_thread = resum_thread & (~wm_imiss | ifq_dtu_thrrdy) &
(~wm_stbwait | stb_retry);
(~wm_stbwait|stb_retry)&(~wait_state|wbm_spc_resume);
assign thaw_thread = resum_thread & (wm_imiss & ~ifq_dtu_thrrdy |
wm_stbwait & ~stb_retry);
wm_stbwait & ~stb_retry|wait_state & ~wbm_spc_resume);
//`endif
1824,7 → 1824,7
// wm_stbwait & ~stb_retry) & ~trp_no_retr;
 
assign stb_wait_nxt = ({4{switch_store_d}} & thr_d | // set
wm_stbwait & ~stb_retry);
wm_stbwait & ~stb_retry|wait_state & ~wbm_spc_resume);
dffr #(4) stbw_reg(.din (stb_wait_nxt),
.q (wm_stbwait),
/trunk/hdl/rtl/sparc_core/sparc.v
2023,7 → 2023,7
spc_scanout0, spc_scanout1, tst_ctu_mbist_done,
tst_ctu_mbist_fail, spc_efc_ifuse_data, spc_efc_dfuse_data,
// Inputs
pcx_spc_grant_px, wbm_spc_stallreq, cpx_spc_data_rdy_cx2, cpx_spc_data_cx2,
pcx_spc_grant_px,wbm_spc_stall,wbm_spc_resume, cpx_spc_data_rdy_cx2, cpx_spc_data_cx2,
const_cpuid, const_maskid, ctu_tck, ctu_sscan_se, ctu_sscan_snap,
ctu_sscan_tid, ctu_tst_mbist_enable, efc_spc_fuse_clk1,
efc_spc_fuse_clk2, efc_spc_ifuse_ashift, efc_spc_ifuse_dshift,
2056,7 → 2056,7
 
 
// cpx interface
input [4:0] pcx_spc_grant_px; input wbm_spc_stallreq; // pcx to processor grant info
input [4:0] pcx_spc_grant_px;input wbm_spc_stall;input wbm_spc_resume; // pcx to processor grant info
input cpx_spc_data_rdy_cx2; // cpx data inflight to sparc
input [145-1:0] cpx_spc_data_cx2; // cpx to sparc data packet
 
2728,7 → 2728,7
 
 
 
sparc_ifu ifu( .wbm_spc_stallreq(wbm_spc_stallreq),
sparc_ifu ifu(.wbm_spc_stall(wbm_spc_stall),.wbm_spc_resume(wbm_spc_resume),
// scan
.short_si0 (spc_scanin0),
.short_si1 (spc_scanin1),
4859,7 → 4859,6
 
// `ifdef FPGA_SYN_NO_SPU
 
 
 
 
/trunk/hdl/behav/testbench/testbench.v
42,36 → 42,24
wire[`WB_DATA_WIDTH-1:0] wb_dataout; // Data Out
wire[`WB_DATA_WIDTH/8-1:0] wb_sel; // Select Output
 
// Separate Cycle wires for memory harnesses
wire wb_cycle_RED_EXT_SEC;
wire wb_cycle_HTRAPS;
wire wb_cycle_TRAPS;
wire wb_cycle_HPRIV_RESET;
wire wb_cycle_KERNEL_text;
wire wb_cycle_KERNEL_data;
wire wb_cycle_MAIN;
wire wb_cycle_RED_SEC;
// Separate Cycle, Strobe and Ack wires for ROM and RAM memory harnesses
wire wb_cycle_ram;
wire wb_cycle_rom;
wire wb_strobe_ram;
wire wb_strobe_rom;
wire wb_ack_ram;
wire wb_ack_rom;
 
// Separate Strobe wires for memory harnesses
wire wb_strobe_RED_EXT_SEC;
wire wb_strobe_HTRAPS;
wire wb_strobe_TRAPS;
wire wb_strobe_HPRIV_RESET;
wire wb_strobe_KERNEL_text;
wire wb_strobe_KERNEL_data;
wire wb_strobe_MAIN;
wire wb_strobe_RED_SEC;
// Decode the address and select the proper memory bank
 
// Separate Ack wires for memory harnesses
wire wb_ack_RED_EXT_SEC;
wire wb_ack_HTRAPS;
wire wb_ack_TRAPS;
wire wb_ack_HPRIV_RESET;
wire wb_ack_KERNEL_text;
wire wb_ack_KERNEL_data;
wire wb_ack_MAIN;
wire wb_ack_RED_SEC;
assign wb_cycle_rom = ( (wb_addr[39:12]==28'hFFF0000) ? wb_cycle : 0 );
assign wb_strobe_rom = ( (wb_addr[39:12]==28'hFFF0000) ? wb_strobe : 0 );
 
assign wb_cycle_ram = ( (wb_addr[39:16]==24'h000004) ? wb_cycle : 0 );
assign wb_strobe_ram = ( (wb_addr[39:16]==24'h000004) ? wb_strobe : 0 );
 
assign wb_ack = wb_ack_ram | wb_ack_rom;
 
/*
* Registers
*/
99,9 → 87,9
// Run the simulation
sys_clock <= 1'b1;
sys_reset <= 1'b1;
#100
#1000
sys_reset <= 1'b0;
#9900
#49000
$display("INFO: TBENCH: Completed Simply RISC S1 Core simulation!");
$finish;
 
108,9 → 96,10
end
 
/*
* Simply RISC S1 module instance
* Module instances
*/
 
// Simply RISC S1 Core
s1_top s1_top_0 (
 
// System inputs
131,89 → 120,10
.wbm_sel_o(wb_sel)
 
);
// Wishbone memory harness used as ROM
mem_harness rom_harness (
 
/*
* Memory Harnesses with Wishbone Slave interface
*/
 
// Section '.RED_EXT_SEC', segment 'text' - From PA 0000040000 to 0000047FFF and then together with
// Section '.RED_EXT_SEC', segment 'data' - From PA 000004C000 to 000004FFFF => 16-3=13 addr_bits
defparam mem_RED_EXT_SEC.addr_bits = 13;
defparam mem_RED_EXT_SEC.memfilename = "mem_RED_EXT_SEC.image";
defparam mem_RED_EXT_SEC.memdefaultcontent = 64'h0100000001000000;
 
// Section '.HTRAPS', segment 'text' - From PA 0000080000 to 0000087FFF and then together with
// Section '.HTRAPS', segment 'data' - From PA 000008C000 to 000008FFFF (zeroes) => 16-3=13 addr_bits
defparam mem_HTRAPS.addr_bits = 13;
defparam mem_HTRAPS.memfilename = "mem_HTRAPS.image";
defparam mem_HTRAPS.memdefaultcontent = 64'h0100000001000000;
 
// Section '.TRAPS', segment 'text' - From PA 1000120000 to 1000127FFF and then together with
// Section '.TRAPS', segment 'data' - From PA 100012C000 to 100012FFFF (zeroes) => 16-3=13 addr_bits
defparam mem_TRAPS.addr_bits = 13;
defparam mem_TRAPS.memfilename = "mem_TRAPS.image";
defparam mem_TRAPS.memdefaultcontent = 64'h0100000001000000;
 
// Section '.HPRIV_RESET', segment 'text' - From PA 1000144000 to 1000144FFF => 12-3=9 addr_bits
defparam mem_HPRIV_RESET.addr_bits = 9;
defparam mem_HPRIV_RESET.memfilename = "mem_HPRIV_RESET.image";
defparam mem_HPRIV_RESET.memdefaultcontent = 64'h0100000001000000;
 
// Section '.KERNEL', segment 'text' - From PA 1101834000 to 1101834FFF => 12-3=9 addr_bits
defparam mem_KERNEL_text.addr_bits = 9;
defparam mem_KERNEL_text.memfilename = "mem_KERNEL_text.image";
defparam mem_KERNEL_text.memdefaultcontent = 64'h0100000001000000;
 
// Section '.KERNEL', segment 'data' - From PA 1101C34000 to 1101C34FFF => 12-3=9 addr_bits
defparam mem_KERNEL_data.addr_bits = 9;
defparam mem_KERNEL_data.memfilename = "mem_KERNEL_data.image";
defparam mem_KERNEL_data.memdefaultcontent = 64'h0000000000000000;
 
// Section '.MAIN', segment 'text' - From PA 1130000000 to 113000FFFF => 16-3=13 addr_bits
// Section '.MAIN', segment 'data' - From PA 1170000000 but should be empty
// Section '.USER_HEAP', segment 'data' - From PA 1178020000 but should be empty
// Section '.MAIN', segment 'bss' - From PA 1178030000 but should be empty
defparam mem_MAIN.addr_bits = 13;
defparam mem_MAIN.memfilename = "mem_MAIN.image";
defparam mem_MAIN.memdefaultcontent = 64'h0100000001000000;
 
// Section '.RED_SEC', segment 'text' - From PA FFF0000000 to FFF0000FFF => 12-3=9 addr_bits
// Section '.RED_SEC', segment 'data' - From PA FFF0010000 but should contain only an unused word
defparam mem_RED_SEC.addr_bits = 9;
defparam mem_RED_SEC.memfilename = "mem_RED_SEC.image";
defparam mem_RED_SEC.memdefaultcontent = 64'h0100000001000000;
 
// Decode the address and select the proper memory bank
 
assign wb_cycle_RED_EXT_SEC = ( (wb_addr[39:16]==24'h000004) ? wb_cycle : 0 );
assign wb_strobe_RED_EXT_SEC = ( (wb_addr[39:16]==24'h000004) ? wb_strobe : 0 );
 
assign wb_cycle_HTRAPS = ( (wb_addr[39:16]==24'h000008) ? wb_cycle : 0 );
assign wb_strobe_HTRAPS = ( (wb_addr[39:16]==24'h000008) ? wb_strobe : 0 );
 
assign wb_cycle_TRAPS = ( (wb_addr[39:16]==24'h100012) ? wb_cycle : 0 );
assign wb_strobe_TRAPS = ( (wb_addr[39:16]==24'h100012) ? wb_strobe : 0 );
 
assign wb_cycle_HPRIV_RESET = ( (wb_addr[39:12]==28'h1000144) ? wb_cycle : 0 );
assign wb_strobe_HPRIV_RESET = ( (wb_addr[39:12]==28'h1000144) ? wb_strobe : 0 );
 
assign wb_cycle_KERNEL_text = ( (wb_addr[39:12]==28'h1101834) ? wb_cycle : 0 );
assign wb_strobe_KERNEL_text = ( (wb_addr[39:12]==28'h1101834) ? wb_strobe : 0 );
 
assign wb_cycle_KERNEL_data = ( (wb_addr[39:12]==28'h1101C34) ? wb_cycle : 0 );
assign wb_strobe_KERNEL_data = ( (wb_addr[39:12]==28'h1101C34) ? wb_strobe : 0 );
 
assign wb_cycle_MAIN = ( (wb_addr[39:16]==24'h113000) ? wb_cycle : 0 );
assign wb_strobe_MAIN = ( (wb_addr[39:16]==24'h113000) ? wb_strobe : 0 );
 
assign wb_cycle_RED_SEC = ( (wb_addr[39:12]==28'hFFF0000) ? wb_cycle : 0 );
assign wb_strobe_RED_SEC = ( (wb_addr[39:12]==28'hFFF0000) ? wb_strobe : 0 );
 
assign wb_ack = wb_ack_RED_EXT_SEC | wb_ack_HTRAPS | wb_ack_TRAPS | wb_ack_HPRIV_RESET |
wb_ack_KERNEL_text | wb_ack_KERNEL_data | wb_ack_MAIN | wb_ack_RED_SEC;
 
mem_harness mem_RED_EXT_SEC (
 
// System inputs
.sys_clock_i(sys_clock),
.sys_reset_i(sys_reset),
221,18 → 131,19
// Wishbone Slave inputs
.wbs_addr_i(wb_addr),
.wbs_data_i(wb_dataout),
.wbs_cycle_i(wb_cycle_RED_EXT_SEC),
.wbs_strobe_i(wb_strobe_RED_EXT_SEC),
.wbs_cycle_i(wb_cycle_rom),
.wbs_strobe_i(wb_strobe_rom),
.wbs_sel_i(wb_sel),
.wbs_we_i(wb_we),
 
// Wishbone Slave outputs
.wbs_data_o(wb_datain),
.wbs_ack_o(wb_ack_RED_EXT_SEC)
.wbs_ack_o(wb_ack_rom)
 
);
 
mem_harness mem_HTRAPS (
// Wishbone memory harness used as RAM
mem_harness ram_harness (
 
// System inputs
.sys_clock_i(sys_clock),
241,135 → 152,35
// Wishbone Slave inputs
.wbs_addr_i(wb_addr),
.wbs_data_i(wb_dataout),
.wbs_cycle_i(wb_cycle_HTRAPS),
.wbs_strobe_i(wb_strobe_HTRAPS),
.wbs_cycle_i(wb_cycle_ram),
.wbs_strobe_i(wb_strobe_ram),
.wbs_sel_i(wb_sel),
.wbs_we_i(wb_we),
 
// Wishbone Slave outputs
.wbs_data_o(wb_datain),
.wbs_ack_o(wb_ack_HTRAPS)
.wbs_ack_o(wb_ack_ram)
 
);
 
mem_harness mem_TRAPS (
/*
* Parameters for memory harnesses
*/
 
// System inputs
.sys_clock_i(sys_clock),
.sys_reset_i(sys_reset),
// ROM has Physical Address range [0xFFF0000000:0xFFF0000FFF]
// so size is 4 KByte and requires 12 address bits
// 3 of which are ignored being a 64-bit memory => addr_bits=9
// (it was section RED_SEC in the official OpenSPARC-T1 testbench)
defparam rom_harness.addr_bits = 9;
defparam rom_harness.memfilename = "rom_harness.hex";
defparam rom_harness.memdefaultcontent = 64'h0100000001000000;
 
// Wishbone Slave inputs
.wbs_addr_i(wb_addr),
.wbs_data_i(wb_dataout),
.wbs_cycle_i(wb_cycle_TRAPS),
.wbs_strobe_i(wb_strobe_TRAPS),
.wbs_sel_i(wb_sel),
.wbs_we_i(wb_we),
 
// Wishbone Slave outputs
.wbs_data_o(wb_datain),
.wbs_ack_o(wb_ack_TRAPS)
 
);
 
mem_harness mem_HPRIV_RESET (
 
// System inputs
.sys_clock_i(sys_clock),
.sys_reset_i(sys_reset),
 
// Wishbone Slave inputs
.wbs_addr_i(wb_addr),
.wbs_data_i(wb_dataout),
.wbs_cycle_i(wb_cycle_HPRIV_RESET),
.wbs_strobe_i(wb_strobe_HPRIV_RESET),
.wbs_sel_i(wb_sel),
.wbs_we_i(wb_we),
 
// Wishbone Slave outputs
.wbs_data_o(wb_datain),
.wbs_ack_o(wb_ack_HPRIV_RESET)
 
);
 
mem_harness mem_KERNEL_text (
 
// System inputs
.sys_clock_i(sys_clock),
.sys_reset_i(sys_reset),
 
// Wishbone Slave inputs
.wbs_addr_i(wb_addr),
.wbs_data_i(wb_dataout),
.wbs_cycle_i(wb_cycle_KERNEL_text),
.wbs_strobe_i(wb_strobe_KERNEL_text),
.wbs_sel_i(wb_sel),
.wbs_we_i(wb_we),
 
// Wishbone Slave outputs
.wbs_data_o(wb_datain),
.wbs_ack_o(wb_ack_KERNEL_text)
 
);
 
mem_harness mem_KERNEL_data (
 
// System inputs
.sys_clock_i(sys_clock),
.sys_reset_i(sys_reset),
 
// Wishbone Slave inputs
.wbs_addr_i(wb_addr),
.wbs_data_i(wb_dataout),
.wbs_cycle_i(wb_cycle_KERNEL_data),
.wbs_strobe_i(wb_strobe_KERNEL_data),
.wbs_sel_i(wb_sel),
.wbs_we_i(wb_we),
 
// Wishbone Slave outputs
.wbs_data_o(wb_datain),
.wbs_ack_o(wb_ack_KERNEL_data)
 
);
 
mem_harness mem_MAIN (
 
// System inputs
.sys_clock_i(sys_clock),
.sys_reset_i(sys_reset),
 
// Wishbone Slave inputs
.wbs_addr_i(wb_addr),
.wbs_data_i(wb_dataout),
.wbs_cycle_i(wb_cycle_MAIN),
.wbs_strobe_i(wb_strobe_MAIN),
.wbs_sel_i(wb_sel),
.wbs_we_i(wb_we),
 
// Wishbone Slave outputs
.wbs_data_o(wb_datain),
.wbs_ack_o(wb_ack_MAIN)
 
);
 
mem_harness mem_RED_SEC (
 
// System inputs
.sys_clock_i(sys_clock),
.sys_reset_i(sys_reset),
 
// Wishbone Slave inputs
.wbs_addr_i(wb_addr),
.wbs_data_i(wb_dataout),
.wbs_cycle_i(wb_cycle_RED_SEC),
.wbs_strobe_i(wb_strobe_RED_SEC),
.wbs_sel_i(wb_sel),
.wbs_we_i(wb_we),
 
// Wishbone Slave outputs
.wbs_data_o(wb_datain),
.wbs_ack_o(wb_ack_RED_SEC)
 
);
 
// RAM has Physical Address range [0x0000040000:0x000004FFFF]
// so size is 64 KByte and requires 16 address bits
// 3 of which are ignored being a 64-bit memory => addr_bits=13
// (it was section RED_EXT_SEC in the official OpenSPARC-T1 testbench)
defparam ram_harness.addr_bits = 13;
defparam ram_harness.memfilename = "ram_harness.hex";
defparam ram_harness.memdefaultcontent = 64'h0100000001000000;
endmodule
/trunk/hdl/filelist.vcs
1,139 → 1,139
-v /home/ffazzino/s1_core/hdl/behav/sparc_libs/m1_lib.v
-v /home/ffazzino/s1_core/hdl/behav/sparc_libs/u1_lib.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_divcntl.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/test_stub_bist.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ffu.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_prencoder16.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_rml.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_tlbdp.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_qdp1.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_irf_register.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_dec.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_milfsm.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_pcx_qmon.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_dc_parity_gen.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_div_yreg.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_eclccr.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ffu_vis.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_rf16x32.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_lfsr5.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_dctl.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_stb_rwdp.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc_dec.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrfsm.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_tlb.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/cpx_spc_buf.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_mul_top.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_inc3.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_rf32x152b.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_dcl.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_byp.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/cpx_spc_rpt.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_tlu_intdp.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_reg.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_dctldp.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_qctl2.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_par16.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/test_stub_scan.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/mul64.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_qdp2.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_dcd.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog_rs1.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_incr64.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/synchronizer_asr.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_irf.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_cmp35.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_hyperv.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_par32.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_tlu_dec64.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_alulogic.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_errdp.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_swl.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_misctl.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_rrobin_picker.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_rrobin_picker2.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_frf.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ffu_dp.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_aluor32.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_mdqctl.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_scm.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_alu_16eql.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_cwp.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_incr46.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_stb_rwctl.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_par34.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_tdp.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_div_32eql.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/swrvr_dlib.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_idct.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_dcdp.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_fdp.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_rf32x80.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_ctr5.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_tagdp.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_aluaddsub.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_stb_ctldp.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqdp.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_aluadder64.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_eclcomp7.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_cnt6.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_tlu_intctl.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_stb_ctl.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_sscan.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_wseldp.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_rndrob.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_icd.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_byp_eccgen.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_mul_cntl.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_invctl.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/cmp_sram_redhdr.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/cluster_header.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_eccctl.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl_visctl.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrcmpl.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_mul_dp.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_mmu_ctl.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqctl.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ffu_part_add32.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_qctl1.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_wb.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_lru4.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_mmu_dp.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_fcl.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_rf16x160.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_div.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_pib.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/swrvr_clib.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_errctl.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_dcache_lfsr.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_tlu_zcmp64.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_clk_cl_sparc_cmp.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_aluzcmp64.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_mbist.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_excpctl.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_rndrob.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_swpla.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_addern_32.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_tlu_penc64.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_imd.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_aluspr.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_alu.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_tcl.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_shft.v
-v /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_asi_decode.v
/home/ffazzino/s1_core/hdl/rtl/s1_top/rst_ctrl.v
/home/ffazzino/s1_core/hdl/rtl/s1_top/int_ctrl.v
/home/ffazzino/s1_core/hdl/rtl/s1_top/spc2wbm.v
/home/ffazzino/s1_core/hdl/rtl/s1_top/s1_top.v
/home/ffazzino/s1_core/hdl/behav/testbench/mem_harness.v
/home/ffazzino/s1_core/hdl/behav/testbench/testbench.v
+incdir+/home/ffazzino/s1_core/hdl/rtl/s1_top
-v /home/fabrizio/s1_core/hdl/behav/sparc_libs/m1_lib.v
-v /home/fabrizio/s1_core/hdl/behav/sparc_libs/u1_lib.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_tdp.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_asi_decode.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_div_32eql.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_intctl.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_cmp35.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_idct.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqctl.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_scm.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_dec.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_ctr5.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_errctl.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/cpx_spc_rpt.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dctldp.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_incr64.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl_visctl.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_shft.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_tcl.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_misctl.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_pcx_qmon.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluadder64.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_penc64.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_mul_top.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_irf_register.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_rndrob.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_dcd.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/synchronizer_asr.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/cpx_spc_buf.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_zcmp64.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_incr46.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_par32.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/swrvr_clib.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_hyperv.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_mul_dp.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/cmp_sram_redhdr.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_lfsr5.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dctl.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_vis.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_milfsm.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_dp.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_mul_cntl.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_stb_ctl.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_rndrob.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_imd.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dcdp.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_swpla.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_fcl.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_byp_eccgen.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_dec64.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_wseldp.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_pib.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_qdp2.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluzcmp64.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_prencoder16.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_qdp1.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dcache_lfsr.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_icd.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_par34.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/test_stub_bist.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/cluster_header.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_divcntl.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_tlbdp.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqdp.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_eccctl.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_byp.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_stb_rwdp.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_part_add32.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_clk_cl_sparc_cmp.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_rf16x32.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_dcl.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_intdp.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_rrobin_picker2.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/swrvr_dlib.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_div.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_addern_32.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_mmu_dp.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_inc3.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dc_parity_gen.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_div_yreg.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_alu.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_stb_ctldp.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_sscan.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_lru4.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_alulogic.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_eclcomp7.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_qctl1.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluaddsub.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_frf.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_par16.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_alu_16eql.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_errdp.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_swl.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_rf32x80.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_rrobin_picker.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_cnt6.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc_dec.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_excpctl.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_invctl.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_cwp.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_tlb.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog_rs1.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluspr.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_rml.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrfsm.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_mbist.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_reg.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluor32.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_mdqctl.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_tagdp.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_fdp.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_rf32x152b.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/test_stub_scan.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_irf.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_mmu_ctl.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_stb_rwctl.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrcmpl.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_eclccr.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_qctl2.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_rf16x160.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/mul64.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_wb.v
/home/fabrizio/s1_core/hdl/rtl/s1_top/rst_ctrl.v
/home/fabrizio/s1_core/hdl/rtl/s1_top/int_ctrl.v
/home/fabrizio/s1_core/hdl/rtl/s1_top/spc2wbm.v
/home/fabrizio/s1_core/hdl/rtl/s1_top/s1_top.v
/home/fabrizio/s1_core/hdl/behav/testbench/mem_harness.v
/home/fabrizio/s1_core/hdl/behav/testbench/testbench.v
+incdir+/home/fabrizio/s1_core/hdl/rtl/s1_top
/trunk/hdl/filelist.fpga
1,140 → 1,140
/home/ffazzino/s1_core/hdl/behav/sparc_libs/m1_lib.v
/home/ffazzino/s1_core/hdl/behav/sparc_libs/u1_lib.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_divcntl.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/test_stub_bist.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ffu.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_prencoder16.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_rml.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_tlbdp.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_qdp1.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_irf_register.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_dec.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_milfsm.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_pcx_qmon.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_dc_parity_gen.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_div_yreg.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_eclccr.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ffu_vis.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_rf16x32.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_lfsr5.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_dctl.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_stb_rwdp.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc_dec.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrfsm.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_tlb.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/cpx_spc_buf.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_mul_top.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_inc3.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_rf32x152b.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_dcl.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_byp.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/cpx_spc_rpt.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_tlu_intdp.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_reg.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_dctldp.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_qctl2.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_par16.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/test_stub_scan.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/mul64.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_qdp2.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_dcd.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog_rs1.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_incr64.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/synchronizer_asr.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_irf.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_cmp35.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_hyperv.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_par32.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_tlu_dec64.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_alulogic.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_errdp.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_swl.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_misctl.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_rrobin_picker.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_rrobin_picker2.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_frf.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ffu_dp.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_aluor32.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_mdqctl.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_scm.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_alu_16eql.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_cwp.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_incr46.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_stb_rwctl.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_par34.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_tdp.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_div_32eql.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/swrvr_dlib.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_idct.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_dcdp.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_fdp.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_rf32x80.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_ctr5.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_tagdp.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_aluaddsub.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_stb_ctldp.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqdp.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_aluadder64.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_eclcomp7.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_cnt6.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_tlu_intctl.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_stb_ctl.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_sscan.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_wseldp.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_rndrob.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_icd.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_byp_eccgen.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_mul_cntl.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_invctl.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/cmp_sram_redhdr.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/cluster_header.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_eccctl.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl_visctl.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrcmpl.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_mul_dp.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_mmu_ctl.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqctl.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ffu_part_add32.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_qctl1.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_wb.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_lru4.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_mmu_dp.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_fcl.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_rf16x160.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_div.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_pib.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/swrvr_clib.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_errctl.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_dcache_lfsr.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_tlu_zcmp64.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_clk_cl_sparc_cmp.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_aluzcmp64.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_mbist.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_excpctl.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_rndrob.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_swpla.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_addern_32.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_tlu_penc64.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_imd.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_aluspr.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_alu.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_tcl.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_shft.v
/home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_asi_decode.v
/home/ffazzino/s1_core/hdl/rtl/s1_top/rst_ctrl.v
/home/ffazzino/s1_core/hdl/rtl/s1_top/int_ctrl.v
/home/ffazzino/s1_core/hdl/rtl/s1_top/spc2wbm.v
/home/ffazzino/s1_core/hdl/rtl/s1_top/s1_top.v
+incdir+/home/ffazzino/s1_core/hdl/rtl/s1_top
/home/fabrizio/s1_core/hdl/behav/sparc_libs/m1_lib.v
/home/fabrizio/s1_core/hdl/behav/sparc_libs/u1_lib.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_tdp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_asi_decode.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_div_32eql.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_intctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_cmp35.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_idct.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_scm.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_dec.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_ctr5.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_errctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/cpx_spc_rpt.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dctldp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_incr64.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl_visctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_shft.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_tcl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_misctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_pcx_qmon.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluadder64.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_penc64.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_mul_top.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_irf_register.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_rndrob.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_dcd.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/synchronizer_asr.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/cpx_spc_buf.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_zcmp64.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_incr46.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_par32.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/swrvr_clib.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_hyperv.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_mul_dp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/cmp_sram_redhdr.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_lfsr5.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_vis.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_milfsm.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_dp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_mul_cntl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_stb_ctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_rndrob.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_imd.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dcdp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_swpla.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_fcl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_byp_eccgen.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_dec64.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_wseldp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_pib.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_qdp2.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluzcmp64.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_prencoder16.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_qdp1.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dcache_lfsr.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_icd.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_par34.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/test_stub_bist.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/cluster_header.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_divcntl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_tlbdp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqdp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_eccctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_byp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_stb_rwdp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_part_add32.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_clk_cl_sparc_cmp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_rf16x32.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_dcl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_intdp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_rrobin_picker2.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/swrvr_dlib.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_div.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_addern_32.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_mmu_dp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_inc3.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dc_parity_gen.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_div_yreg.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_alu.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_stb_ctldp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_sscan.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_lru4.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_alulogic.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_eclcomp7.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_qctl1.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluaddsub.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_frf.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_par16.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_alu_16eql.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_errdp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_swl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_rf32x80.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_rrobin_picker.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_cnt6.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc_dec.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_excpctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_invctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_cwp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_tlb.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog_rs1.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluspr.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_rml.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrfsm.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_mbist.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_reg.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluor32.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_mdqctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_tagdp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_fdp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_rf32x152b.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/test_stub_scan.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_irf.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_mmu_ctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_stb_rwctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrcmpl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_eclccr.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_qctl2.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_rf16x160.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/mul64.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_wb.v
/home/fabrizio/s1_core/hdl/rtl/s1_top/rst_ctrl.v
/home/fabrizio/s1_core/hdl/rtl/s1_top/int_ctrl.v
/home/fabrizio/s1_core/hdl/rtl/s1_top/spc2wbm.v
/home/fabrizio/s1_core/hdl/rtl/s1_top/s1_top.v
+incdir+/home/fabrizio/s1_core/hdl/rtl/s1_top
+define+FPGA_SYN
+define+FPGA_SYN_1THREAD
+define+FPGA_SYN_NO_SPU
/trunk/hdl/filelist.xst
1,136 → 1,136
verilog work /home/ffazzino/s1_core/hdl/behav/sparc_libs/m1_lib.v
verilog work /home/ffazzino/s1_core/hdl/behav/sparc_libs/u1_lib.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_divcntl.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/test_stub_bist.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ffu.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_prencoder16.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_rml.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_tlbdp.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_qdp1.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_irf_register.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_dec.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_milfsm.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_pcx_qmon.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_dc_parity_gen.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_div_yreg.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_eclccr.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ffu_vis.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_rf16x32.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_lfsr5.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_dctl.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_stb_rwdp.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc_dec.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrfsm.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_tlb.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/cpx_spc_buf.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_mul_top.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_inc3.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_rf32x152b.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_dcl.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_byp.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/cpx_spc_rpt.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_tlu_intdp.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_reg.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_dctldp.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_qctl2.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_par16.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/test_stub_scan.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/mul64.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_qdp2.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_dcd.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog_rs1.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_incr64.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/synchronizer_asr.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_irf.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_cmp35.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_hyperv.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_par32.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_tlu_dec64.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_alulogic.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_errdp.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_swl.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_misctl.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_rrobin_picker.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_rrobin_picker2.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_frf.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ffu_dp.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_aluor32.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_mdqctl.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_scm.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_alu_16eql.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_cwp.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_incr46.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_stb_rwctl.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_par34.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_tdp.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_div_32eql.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/swrvr_dlib.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_idct.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_dcdp.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_fdp.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_rf32x80.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_ctr5.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_tagdp.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_aluaddsub.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_stb_ctldp.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqdp.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_aluadder64.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_eclcomp7.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_cnt6.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_tlu_intctl.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_stb_ctl.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_sscan.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_wseldp.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_rndrob.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_icd.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_byp_eccgen.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_mul_cntl.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_invctl.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/cmp_sram_redhdr.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/cluster_header.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_eccctl.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl_visctl.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrcmpl.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_mul_dp.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_mmu_ctl.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqctl.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ffu_part_add32.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_qctl1.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_wb.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_lru4.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_mmu_dp.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_fcl.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_r_rf16x160.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_div.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_pib.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/swrvr_clib.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_errctl.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_dcache_lfsr.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_tlu_zcmp64.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/bw_clk_cl_sparc_cmp.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_aluzcmp64.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_mbist.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_excpctl.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_rndrob.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_swpla.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_addern_32.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_tlu_penc64.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_ifu_imd.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_aluspr.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_alu.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/tlu_tcl.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/sparc_exu_shft.v
verilog work /home/ffazzino/s1_core/hdl/rtl/sparc_core/lsu_asi_decode.v
verilog work /home/ffazzino/s1_core/hdl/rtl/s1_top/rst_ctrl.v
verilog work /home/ffazzino/s1_core/hdl/rtl/s1_top/int_ctrl.v
verilog work /home/ffazzino/s1_core/hdl/rtl/s1_top/spc2wbm.v
verilog work /home/ffazzino/s1_core/hdl/rtl/s1_top/s1_top.v
verilog work /home/fabrizio/s1_core/hdl/behav/sparc_libs/m1_lib.v
verilog work /home/fabrizio/s1_core/hdl/behav/sparc_libs/u1_lib.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_tdp.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_asi_decode.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_div_32eql.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_intctl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_cmp35.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_idct.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqctl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_scm.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_dec.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_ctr5.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_errctl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/cpx_spc_rpt.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dctldp.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_incr64.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl_visctl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_shft.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_tcl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_misctl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_pcx_qmon.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluadder64.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_penc64.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_mul_top.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_irf_register.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_rndrob.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_dcd.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/synchronizer_asr.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/cpx_spc_buf.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_zcmp64.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_incr46.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_par32.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/swrvr_clib.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_hyperv.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_mul_dp.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/cmp_sram_redhdr.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_lfsr5.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dctl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_vis.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_milfsm.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_dp.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_mul_cntl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_stb_ctl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_rndrob.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_imd.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dcdp.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_swpla.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_fcl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_byp_eccgen.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_dec64.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_wseldp.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_pib.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_qdp2.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluzcmp64.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_prencoder16.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_qdp1.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dcache_lfsr.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_icd.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_par34.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/test_stub_bist.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/cluster_header.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_divcntl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_tlbdp.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqdp.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_eccctl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_byp.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_stb_rwdp.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_part_add32.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_clk_cl_sparc_cmp.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_rf16x32.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_dcl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_intdp.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_rrobin_picker2.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/swrvr_dlib.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_div.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_addern_32.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_mmu_dp.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_inc3.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dc_parity_gen.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_div_yreg.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_alu.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_stb_ctldp.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_sscan.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_lru4.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_alulogic.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_eclcomp7.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_qctl1.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluaddsub.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_frf.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_par16.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_alu_16eql.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_errdp.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_swl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_rf32x80.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_rrobin_picker.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_cnt6.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc_dec.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_excpctl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_invctl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_cwp.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_tlb.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog_rs1.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluspr.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_rml.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrfsm.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_mbist.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_reg.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluor32.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_mdqctl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_tagdp.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_fdp.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_rf32x152b.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/test_stub_scan.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_irf.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_mmu_ctl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_stb_rwctl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrcmpl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_eclccr.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_qctl2.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_rf16x160.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/mul64.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_wb.v
verilog work /home/fabrizio/s1_core/hdl/rtl/s1_top/rst_ctrl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/s1_top/int_ctrl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/s1_top/spc2wbm.v
verilog work /home/fabrizio/s1_core/hdl/rtl/s1_top/s1_top.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.