URL
https://opencores.org/ocsvn/fpga-cf/fpga-cf/trunk
Subversion Repositories fpga-cf
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 11 to Rev 12
- ↔ Reverse comparison
Rev 11 → Rev 12
/fpga-cf/trunk/release/simple.scr
File deleted
\ No newline at end of file
/fpga-cf/trunk/release/simple.prj
File deleted
/fpga-cf/trunk/examples/simple/simple.scr
0,0 → 1,9
run |
-ifn simple.prj |
-ifmt MIXED |
-opt_mode AREA |
-opt_level 1 |
-ofmt NGC |
-ofn simple.ngc |
-p xc5vlx110t |
-top top |
/fpga-cf/trunk/examples/simple/simple.prj
0,0 → 1,28
verilog work "../../hdl/boardsupport/v5/rocketio_wrapper_gtp_tile.v" |
verilog work "../../hdl/boardsupport/v5/rx_elastic_buffer.v" |
verilog work "../../hdl/boardsupport/v5/rocketio_wrapper_gtp.v" |
verilog work "../../hdl/PATLPP/shiftr/gensrl.v" |
verilog work "../../hdl/PATLPP/microcodelogic/microcodesrc/microcodesrc.v" |
verilog work "../../hdl/boardsupport/v5/v5_emac_v1_6.v" |
verilog work "../../hdl/boardsupport/v5/tx_client_fifo_8.v" |
verilog work "../../hdl/boardsupport/v5/rx_client_fifo_8.v" |
verilog work "../../hdl/boardsupport/v5/gtp_dual_1000X.v" |
verilog work "../../hdl/PATLPP/shiftr/shiftr.v" |
verilog work "../../hdl/PATLPP/regfile/regfile.v" |
verilog work "../../hdl/PATLPP/microcodelogic/microcodelogic.v" |
verilog work "../../hdl/PATLPP/comparelogic/comparelogic.v" |
verilog work "../../hdl/PATLPP/checksum/checksum.v" |
verilog work "../../hdl/PATLPP/alunit/alunit.v" |
verilog work "../../hdl/lpm/stopar/lpm_stopar.v" |
verilog work "../../hdl/lpm/mux8/lpm_mux8.v" |
verilog work "../../hdl/lpm/mux4/lpm_mux4.v" |
verilog work "../../hdl/lpm/mux2/lpm_mux2.v" |
verilog work "../../hdl/boardsupport/v5/v5_emac_v1_6_block.v" |
verilog work "../../hdl/boardsupport/v5/eth_fifo_8.v" |
verilog work "../../hdl/PATLPP/shiftr_bram/shiftr_bram.v" |
verilog work "../../hdl/PATLPP/patlpp.v" |
verilog work "../../hdl/port_register/port_register.v" |
verilog work "../../hdl/boardsupport/v5/v5_emac_v1_6_locallink.v" |
verilog work "../../hdl/channelif/channelif2.v" |
verilog work "../../hdl/boardsupport/enetplatformv5.v" |
verilog work "../../hdl/topv5_simple.v" |