URL
https://opencores.org/ocsvn/klc32/klc32/trunk
Subversion Repositories klc32
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 11 to Rev 12
- ↔ Reverse comparison
Rev 11 → Rev 12
/klc32/trunk/rtl/verilog/KLC32.v
307,6 → 307,7
wire [31:0] cr = {cr7,cr6,cr5,cr4,cr3,cr2,cr1,cr0}; |
wire [31:0] sr = {tf,1'b0,sf,2'b00,im,16'd0}; |
reg [31:0] tick; |
reg [31:0] be_addr; |
|
reg [5:0] cnt; |
reg [31:0] div_r0; |
470,6 → 471,9
`include "MULTDIV.v" |
|
endcase |
|
`include "bus_error.v" |
|
end |
|
endmodule |
/klc32/trunk/rtl/verilog/PUSH.v
54,14 → 54,6
usp <= usp - 32'd4; |
state <= PUSH1; |
end |
else if (err_i) begin |
cyc_o <= 1'b0; |
stb_o <= 1'b0; |
we_o <= 1'b0; |
sel_o <= 4'b0000; |
vector <= `BUS_ERR_VECTOR; |
state <= TRAP; |
end |
|
PEA: |
if (!cyc_o) begin |
84,14 → 76,6
usp <= usp - 32'd4; |
state <= IFETCH; |
end |
else if (err_i) begin |
cyc_o <= 1'b0; |
stb_o <= 1'b0; |
we_o <= 1'b0; |
sel_o <= 4'b0000; |
vector <= `BUS_ERR_VECTOR; |
state <= TRAP; |
end |
|
LINK: |
if (!cyc_o) begin |
118,11 → 102,3
end |
state <= WRITEBACK; |
end |
else if (err_i) begin |
cyc_o <= 1'b0; |
stb_o <= 1'b0; |
we_o <= 1'b0; |
sel_o <= 4'b0000; |
vector <= `BUS_ERR_VECTOR; |
state <= TRAP; |
end |
/klc32/trunk/rtl/verilog/JMP.v
35,10 → 35,3
pc <= dat_i; |
state <= IFETCH; |
end |
else if (err_i) begin |
cyc_o <= 1'b0; |
stb_o <= 1'b0; |
sel_o <= 4'b0000; |
vector <= `BUS_ERR_VECTOR; |
state <= TRAP; |
end |
/klc32/trunk/rtl/verilog/JSR.v
37,13 → 37,6
tgt <= dat_i; |
state <= JSR1; |
end |
else if (err_i) begin |
cyc_o <= 1'b0; |
stb_o <= 1'b0; |
sel_o <= 4'b0000; |
vector <= `BUS_ERR_VECTOR; |
state <= TRAP; |
end |
JSR1: |
if (!cyc_o) begin |
fc_o <= {sf,2'b01}; |
69,11 → 62,3
pc <= tgt; |
state <= IFETCH; |
end |
else if (err_i) begin |
cyc_o <= 1'b0; |
stb_o <= 1'b0; |
we_o <= 1'b0; |
sel_o <= 4'b0000; |
vector <= `BUS_ERR_VECTOR; |
state <= TRAP; |
end |
/klc32/trunk/rtl/verilog/POP.v
52,13 → 52,6
res <= dat_i; |
state <= WRITEBACK; |
end |
else if (err_i) begin |
cyc_o <= 1'b0; |
stb_o <= 1'b0; |
sel_o <= 4'b0000; |
vector <= `BUS_ERR_VECTOR; |
state <= TRAP; |
end |
|
UNLK: |
if (!cyc_o) begin |
83,11 → 76,4
res <= dat_i; |
state <= WRITEBACK; |
end |
else if (err_i) begin |
cyc_o <= 1'b0; |
stb_o <= 1'b0; |
sel_o <= 4'b0000; |
vector <= `BUS_ERR_VECTOR; |
state <= TRAP; |
end |
|
/klc32/trunk/rtl/verilog/FETCH_IMM32.v
37,10 → 37,3
pc <= pc + 32'd4; |
state <= EXECUTE; |
end |
else if (err_i) begin |
cyc_o <= 1'b0; |
stb_o <= 1'b0; |
sel_o <= 4'b0000; |
vector <= `BUS_ERR_VECTOR; |
state <= TRAP; |
end |
/klc32/trunk/rtl/verilog/IFETCH.v
69,10 → 69,3
Rn <= dat_i[25:21]; |
state <= REGFETCHA; |
end |
else if (err_i) begin |
cyc_o <= 1'b0; |
stb_o <= 1'b0; |
sel_o <= 4'b0000; |
vector <= `BUS_ERR_VECTOR; |
state <= TRAP; |
end |
/klc32/trunk/rtl/verilog/EXECUTE.v
47,6 → 47,7
else begin |
res <= im; |
end |
5'b01011: res <= be_addr; |
5'b01111: res <= tick; |
endcase |
`MTSPR: |
114,7 → 115,9
`RR: |
begin |
case(func) |
`ADD: res <= a + b; |
`SUB: res <= a - b; |
`CMP: res <= a - b; |
`AND: res <= a & b; |
`ANDC: res <= a & ~b; |
`OR: res <= a | b; |
/klc32/trunk/rtl/verilog/TRAP.v
41,13 → 41,6
ssp <= ssp - 32'd4; |
state <= TRAP2; |
end |
else if (err_i) begin |
cyc_o <= 1'b0; |
stb_o <= 1'b0; |
sel_o <= 4'b0000; |
vector <= `BUS_ERR_VECTOR; |
state <= TRAP; |
end |
TRAP2: |
if (!stb_o) begin |
fc_o <= {3'b101}; |
64,13 → 57,6
ssp <= ssp - 32'd4; |
state <= TRAP3; |
end |
else if (err_i) begin |
cyc_o <= 1'b0; |
stb_o <= 1'b0; |
sel_o <= 4'b0000; |
vector <= `BUS_ERR_VECTOR; |
state <= TRAP; |
end |
TRAP3: |
if (!stb_o) begin |
fc_o <= {3'b101}; |
88,11 → 74,4
ssp <= ssp - 32'd4; |
state <= VECTOR; |
end |
else if (err_i) begin |
cyc_o <= 1'b0; |
stb_o <= 1'b0; |
sel_o <= 4'b0000; |
vector <= `BUS_ERR_VECTOR; |
state <= TRAP; |
end |
|
/klc32/trunk/rtl/verilog/WRITE_FLAGS.v
25,6 → 25,7
begin |
state <= IFETCH; |
if (opcode==`CMPI || (opcode==`RR && func==`CMP)) begin |
$display("Writing flags to Cr%d",Rn[4:2]); |
case(Rn[4:2]) |
3'd0: cr0 <= {nf,zf,vf,cf}; |
3'd1: cr1 <= {nf,zf,vf,cf}; |
/klc32/trunk/rtl/verilog/MEMORY.v
156,14 → 156,6
end |
endcase |
end |
else if (err_i) begin |
cyc_o <= 1'b0; |
stb_o <= 1'b0; |
we_o <= 1'b0; |
sel_o <= 4'b0000; |
vector <= `BUS_ERR_VECTOR; |
state <= TRAP; |
end |
|
TAS: |
if (!cyc_o) begin |
180,14 → 172,6
res <= dat_i; |
state <= TAS2; |
end |
else if (err_i) begin |
cyc_o <= 1'b0; |
stb_o <= 1'b0; |
we_o <= 1'b0; |
sel_o <= 4'b0000; |
vector <= `BUS_ERR_VECTOR; |
state <= TRAP; |
end |
TAS2: |
if (!res[31]) begin |
if (!stb_o) begin |
206,14 → 190,6
sel_o <= 4'b0000; |
state <= WRITEBACK; |
end |
else if (err_i) begin |
cyc_o <= 1'b0; |
stb_o <= 1'b0; |
we_o <= 1'b0; |
sel_o <= 4'b0000; |
vector <= `BUS_ERR_VECTOR; |
state <= TRAP; |
end |
end |
else begin |
cyc_o <= 1'b0; |
/klc32/trunk/rtl/verilog/RTS.v
40,11 → 40,4
pc <= {dat_i[31:2],2'b00}+{ir[25:22],2'b00}; |
state <= IFETCH; |
end |
else if (err_i) begin |
cyc_o <= 1'b0; |
stb_o <= 1'b0; |
sel_o <= 4'b0000; |
vector <= `BUS_ERR_VECTOR; |
state <= TRAP; |
end |
|