OpenCores

/tags/a/doc/src/ptc_spec.doc Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

tags/a/doc/src/ptc_spec.doc Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: tags/a/doc/ptc_spec.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: tags/a/doc/ptc_spec.pdf =================================================================== --- tags/a/doc/ptc_spec.pdf (revision 11) +++ tags/a/doc/ptc_spec.pdf (nonexistent)

tags/a/doc/ptc_spec.pdf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: tags/a/sim/rtl_sim/run/ncverilog.log =================================================================== --- tags/a/sim/rtl_sim/run/ncverilog.log (revision 11) +++ tags/a/sim/rtl_sim/run/ncverilog.log (nonexistent) @@ -1,122 +0,0 @@ -ncverilog: v3.20.(p1): (c) Copyright 1995 - 2000 Cadence Design Systems, Inc. -ncverilog: v3.20.(p1): Started on Aug 22, 2001 at 01:58:37 -ncverilog - +incdir+../../../rtl/verilog/ - +incdir+../../../bench/verilog/ - ../../../bench/verilog/clkrst.v - ../../../bench/verilog/tb_defines.v - ../../../bench/verilog/tb_tasks.v - ../../../bench/verilog/tb_top.v - ../../../bench/verilog/timescale.v - ../../../bench/verilog/wb_master.v - ../../../rtl/verilog/defines.v - ../../../rtl/verilog/ptc.v - -file: ../../../bench/verilog/clkrst.v - module worklib.clkrst:v (up-to-date) - errors: 0, warnings: 0 -file: ../../../bench/verilog/tb_defines.v -file: ../../../bench/verilog/tb_tasks.v - module worklib.tb_tasks:v - errors: 0, warnings: 0 -file: ../../../bench/verilog/tb_top.v - module worklib.tb_top:v (up-to-date) - errors: 0, warnings: 0 -file: ../../../bench/verilog/timescale.v -file: ../../../bench/verilog/wb_master.v - module worklib.wb_master:v (up-to-date) - errors: 0, warnings: 0 -file: ../../../rtl/verilog/defines.v -file: ../../../rtl/verilog/ptc.v - module worklib.ptc:v (up-to-date) - errors: 0, warnings: 0 - Caching library 'worklib' ....... Done - Elaborating the design hierarchy: -wb_master wb_master( - | -ncelab: *W,CUVWSP (/projects/Temp/damjan/ptc/bench/verilog/tb_top.v,95|18): Too few module port connections. - .RTY_I(0), - | -ncelab: *W,CUVMPW (/projects/Temp/damjan/ptc/bench/verilog/tb_top.v,108|8): port sizes differ in port connection. - Building instance overlay tables: .................... - `PTC_RPTC_HRC: wb_dat_o[dw-1:0] <= {{dw-cw{1'b0}}, rptc_hrc}; - | -ncelab: *W,NEGMCV (/projects/Temp/damjan/ptc/rtl/verilog/ptc.v,303|41): zero or negative multiple concatenation multiplier (0). - `PTC_RPTC_LRC: wb_dat_o[dw-1:0] <= {{dw-cw{1'b0}}, rptc_lrc}; - | -ncelab: *W,NEGMCV (/projects/Temp/damjan/ptc/rtl/verilog/ptc.v,304|41): zero or negative multiple concatenation multiplier (0). - default: wb_dat_o[dw-1:0] <= {{dw-cw{1'b0}}, rptc_cntr}; - | -ncelab: *W,NEGMCV (/projects/Temp/damjan/ptc/rtl/verilog/ptc.v,307|35): zero or negative multiple concatenation multiplier (0). - Done - Generating native compiled code: - worklib.clkrst:v <0x4a5775d7> - streams: 3, words: 351 - worklib.ptc:v <0x445302e9> - streams: 43, words: 4150 - worklib.tb_tasks:v <0x7534da37> - streams: 31, words: 2955 - worklib.tb_top:v <0x6bcb5cb6> - streams: 4, words: 150 - worklib.wb_master:v <0x122b0123> - streams: 38, words: 3464 - Loading native compiled code: .................... Done - Building instance specific data structures. - Design hierarchy summary: - Instances Unique - Modules: 5 5 - Registers: 97 97 - Scalar wires: 30 - - Expanded wires: 32 1 - Vectored wires: 5 - - Always blocks: 17 17 - Initial blocks: 3 3 - Cont. assignments: 16 22 - Pseudo assignments: 2 36 - Simulation timescale: 10ps - Writing initial simulation snapshot: worklib.tb_tasks:v -Loading snapshot worklib.tb_tasks:v .................... Done -ncsim> source /software/cadence/tools/inca/files/ncsimrc -ncsim> run - -Warning! some objects excluded from $dumpvars due to access restrictions, use +access+r on comandline for access to all objects - File: /projects/Temp/damjan/ptc/bench/verilog/tb_tasks.v, line = 928, pos = 9 - Scope: tb_tasks - Time: 0 FS + 0 - - -### -### PTC IP Core Verification ### -### - -I. Testing correct operation of RPTC_CTRL control bits - - Testing control bit RPTC_CTRL[ECLK] ... -Warning! Unable to open VCD file ../sim/tb_top.vcd (check file permissions) - Time: 0 FS + 2 - -. OK - Testing control bit RPTC_CTRL[OE] ... OK - Testing control bit RPTC_CTRL[CNTRRST] ... OK - Testing control bit RPTC_CTRL[EN] ... OK - Testing control bit RPTC_CTRL[NEC] ... OK - Testing control bit RPTC_CTRL[CAPTE] ... OK - Testing control bit RPTC_CTRL[SINGLE] ... OK - Testing control bit RPTC_CTRL[INTE] and PTC_RPTC_CTRL[INT]... OK - -II. Testing modes of operation ... - - Testing PWM mode ...FAILED !!! - Testing timer/counter mode ...FAILED !!! - Testing gate feature ... OK - Testing interrupt feature ... OK - Testing capture feature ... OK - -### -### FAILED TESTS: 2 ### -### - -Simulation complete via $finish(1) at time 224476 NS + 1 -/projects/Temp/damjan/ptc/bench/verilog/tb_tasks.v:961 $finish; -ncsim> exit -ncverilog: v3.20.(p1): Exiting on Aug 22, 2001 at 01:58:38 (total: 00:00:01) Index: tags/a/sim/rtl_sim/bin/sim.sh =================================================================== --- tags/a/sim/rtl_sim/bin/sim.sh (revision 11) +++ tags/a/sim/rtl_sim/bin/sim.sh (nonexistent) @@ -1,125 +0,0 @@ -#!/bin/bash - -# -# This script runs RTL and gate-level simulation using different simultion tools. -# Right now Cadence Verilog-XL and NCSim are supported. -# -# Author: Damjan Lampret -# - -# -# User definitions -# - -# Set simulation tool you are using (xl, ncsim, ncver) -SIMTOOL=ncver - -# Set test bench top module(s) -TB_TOP="tb_tasks" - -# Set include directories -INCLUDE_DIRS="../../../rtl/verilog/ ../../../bench/verilog/" - -# Set test bench files -BENCH_FILES="../../../bench/verilog/*.v" - -# Set RTL source files -RTL_FILES="../../../rtl/verilog/*.v" - -# Set gate-level netlist files -GATE_FILES="../syn/out/final_ptc.v" - -# Set libraries (standard cell etc.) -LIB_FILES="/libs/Virtual_silicon/UMCL18U250D2_2.1/verilog_simulation_models/*.v" - -# Set parameters for simulation tool -if [ $SIMTOOL == xl ]; then - PARAM="+turbo+3 -q" - for i in $INCLUDE_DIRS; do - INCDIR=$INCDIR" +incdir+$i" - done -elif [ $SIMTOOL == ncver ]; then - NCVER_PARAM="" - for i in $INCLUDE_DIRS; do - INCDIR=$INCDIR" +incdir+$i" - done -elif [ $SIMTOOL == ncsim ]; then - NCPREP_PARAM="-UPDATE +overwrite" - NCSIM_PARAM="-MESSAGES -NOCOPYRIGHT" - for i in $INCLUDE_DIRS; do - INCDIR=$INCDIR" +incdir+$i" - done -else - echo "$SIMTOOL is unsupported simulation tool." - exit 0 -fi - -# -# Don't change anything below unless you know what you are doing -# - -# Run simulation in sim directory -cd ../sim - -# Run actual simulation - -# Cadence Verilog-XL -if [ $SIMTOOL == xl ]; then - - # RTL simulation - if [ "$1" == rtl ]; then - verilog $PARAM $INCDIR $BENCH_FILES $RTL_FILES - - # Gate-level simulation - elif [ "$1" == gate ]; then - verilog $PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES - - # Wrong parameter or no parameter - else - echo "Usage: $0 [rtl|gate]" - exit 0 - fi - -# Cadence Ncverilog -elif [ $SIMTOOL == ncver ]; then - - # RTL simulation - if [ "$1" == rtl ]; then - ncverilog $NCVER_PARAM $INCDIR $BENCH_FILES $RTL_FILES - cp ncverilog.log ../log - - # Gate-level simulation - elif [ "$1" == gate ]; then - ncverilog $NCVER_PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES - cp ncverilog.log ../log - - # Wrong parameter or no parameter - else - echo "Usage: $0 [rtl|gate]" - exit 0 - fi - -# Cadence Ncsim -elif [ $SIMTOOL == ncsim ]; then - - # RTL simulation - if [ "$1" == rtl ]; then - ncprep $NCPREP_PARAM $INCDIR $BENCH_FILES $RTL_FILES - ./RUN_NC - - # Gate-level simulation - elif [ "$1" == gate ]; then - ncprep $NCPREP_PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES - ./RUN_NC - - # Wrong parameter or no parameter - else - echo "Usage: $0 [rtl|gate]" - exit 0 - fi - -# Unsupported simulation tool -else - echo "$SIMTOOL is unsupported simulation tool." - exit 0; -fi

tags/a/sim/rtl_sim/bin/sim.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: tags/a/syn/run/dodesign =================================================================== --- tags/a/syn/run/dodesign (revision 11) +++ tags/a/syn/run/dodesign (nonexistent) @@ -1,5 +0,0 @@ -#!/bin/sh -f - -# nohup dc_shell -f top.scr | tee ../logs/top.log -dc_shell -f top_ptc.scr > ../logs/top_ptc.log -mv command.log ../logs

tags/a/syn/run/dodesign Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: tags/a/syn/bin/tech_vs_umc18.inc =================================================================== --- tags/a/syn/bin/tech_vs_umc18.inc (revision 11) +++ tags/a/syn/bin/tech_vs_umc18.inc (nonexistent) @@ -1,16 +0,0 @@ -/* Set Virtual Silicon UMC 0.18u standard cell library */ - -search_path = {. /libs/Virtual_silicon/UMCL18U250D2_2.1/design_compiler/ } -snps = get_unix_variable("SYNOPSYS") -synthetic_library = { \ - snps + "/libraries/syn/dw01.sldb" \ - snps + "/libraries/syn/dw02.sldb" \ - snps + "/libraries/syn/dw03.sldb" \ - snps + "/libraries/syn/dw04.sldb" \ - snps + "/libraries/syn/dw05.sldb" \ - snps + "/libraries/syn/dw06.sldb" \ - snps + "/libraries/syn/dw07.sldb" } -target_library = { umcl18u250t2_typ.db } -link_library = target_library + synthetic_library -symbol_library = { umcl18u250t2.sdb } - Index: tags/a/syn/bin/reports.inc =================================================================== --- tags/a/syn/bin/reports.inc (revision 11) +++ tags/a/syn/bin/reports.inc (nonexistent) @@ -1,10 +0,0 @@ -/* Basic reports */ -report_area > LOG_PATH + STAGE + _ + TOPLEVEL + _area.log -report_timing -nworst 10 > LOG_PATH + STAGE + _ + TOPLEVEL + _timing.log -report_hierarchy > LOG_PATH + STAGE + _ + TOPLEVEL + _hierarchy.log -report_resources > LOG_PATH + STAGE + _ + TOPLEVEL + _resources.log -report_constraint > LOG_PATH + STAGE + _ + TOPLEVEL + _constraint.log -/* -report_power > LOG_PATH + STAGE + _ + TOPLEVEL + _power.log -*/ - Index: tags/a/syn/bin/select_tech.inc =================================================================== --- tags/a/syn/bin/select_tech.inc (revision 11) +++ tags/a/syn/bin/select_tech.inc (nonexistent) @@ -1,5 +0,0 @@ -/* Defaults */ - -TECH = vs_umc18 /* vs_umc18, art_umc18 */ -CLK_PERIOD = 5 /* 200 MHz */ -MAX_AREA = 0 /* Push hard */ Index: tags/a/syn/bin/set_env.inc =================================================================== --- tags/a/syn/bin/set_env.inc (revision 11) +++ tags/a/syn/bin/set_env.inc (nonexistent) @@ -1,18 +0,0 @@ -/* Enable Verilog HDL preprocessor */ -hdlin_enable_vpp = true - -/* Set log path */ -LOG_PATH = "../log/" - -/* Set gate-level netlist path */ -GATE_PATH = "../out/" - -/* Set RAMS_PATH */ -RAMS_PATH = "../../../lib/" - -/* Set RTL source path */ -RTL_PATH = "../../rtl/verilog/" - -/* Optimize adders */ -synlib_model_map_effort = high -hlo_share_effort = medium Index: tags/a/syn/bin/read_design.inc =================================================================== --- tags/a/syn/bin/read_design.inc (revision 11) +++ tags/a/syn/bin/read_design.inc (nonexistent) @@ -1,11 +0,0 @@ -/* Set search path for verilog include files */ -search_path = search_path + { RTL_PATH } + { GATE_PATH } - -/* Read verilog files of the PTC IP core */ -if (TOPLEVEL == "ptc") { - read -f verilog ptc.v -} else { - echo "Non-existing top level." - exit -} - Index: tags/a/syn/bin/cons_art_umc18.inc =================================================================== --- tags/a/syn/bin/cons_art_umc18.inc (revision 11) +++ tags/a/syn/bin/cons_art_umc18.inc (nonexistent) @@ -1,51 +0,0 @@ -/* Constraints */ -CLK_UNCERTAINTY = 0.1 /* 100 ps */ -DFFHQX2_CKQ = 0.2 /* Clk to Q in technology time units */ -DFFHQX2_SETUP = 0.1 /* Setup time in technology time units */ - -/* Clocks constraints */ -create_clock CLK -period CLK_PERIOD -create_clock ECLK -period CLK_PERIOD -set_clock_skew all_clocks() -uncertainty CLK_UNCERTAINTY -set_dont_touch_network all_clocks() - -/* Reset constraints */ -set_driving_cell -none RST -set_drive 0 RST -set_dont_touch_network RST - -/* All inputs except reset and clock */ -all_inputs_wo_rst_clk = all_inputs() - CLK - RST - -/* Set output delays and load for output signals - * - * All outputs are assumed to go directly into - * external flip-flops for the purpose of this - * synthesis - */ -set_output_delay DFFHQX2_SETUP -clock CLK all_outputs() -set_load load_of(typical/DFFHQX2/D) * 1 all_outputs() - -/* Input delay and driving cell of all inputs - * - * All these signals are assumed to come directly from - * flip-flops for the purpose of this synthesis - * - */ -set_input_delay DFFHQX2_CKQ -clock CLK all_inputs_wo_rst_clk -set_driving_cell -cell DFFHQX2 -pin Q all_inputs_wo_rst_clk - -/* Set design fanout */ -/* -set_max_fanout 10 TOPLEVEL -*/ - -/* Set area constraint */ -set_max_area MAX_AREA - -/* Optimize all near-critical paths to give extra slack for layout */ -c_range = CLK_PERIOD * 0.05 -group_path -critical_range c_range -name CLK -to CLK - -/* Operating conditions */ -set_operating_conditions typical Index: tags/a/syn/bin/top_ptc.scr =================================================================== --- tags/a/syn/bin/top_ptc.scr (revision 11) +++ tags/a/syn/bin/top_ptc.scr (nonexistent) @@ -1,65 +0,0 @@ -/* - * User defines for synthesizing PTC IP core - * - */ -TOPLEVEL = ptc -include select_tech.inc -CLK = clk_i -ECLK = ptc_ecgt -RST = rst_i -CLK_PERIOD = 5 /* 200 MHz */ -MAX_AREA = 0 /* Push hard */ -DO_UNGROUP = yes /* yes, no */ -DO_VERIFY = yes /* yes, no */ - -/* Starting timestamp */ -sh date - -/* Set some basic variables related to environment */ -include set_env.inc -STAGE = final - -/* Load libraries */ -include tech_ + TECH + .inc - -/* Load HDL source files */ -include read_design.inc > LOG_PATH + read_design_ + TOPLEVEL + .log - -/* Set design top */ -current_design TOPLEVEL - -/* Link all blocks and uniquify them */ -link -uniquify -check_design > LOG_PATH + check_design_ + TOPLEVEL + .log - -/* Apply constraints */ -if (TECH == "vs_umc18") { - include cons_vs_umc18.inc -} else if (TECH == "art_umc18") { - include cons_art_umc18.inc -} else { - echo "Error: Unsupported technology" - exit -} - -/* Lets do basic synthesis */ -if (DO_UNGROUP == "yes") { - ungroup -all -} -compile -boundary_optimization -map_effort low - -/* Dump gate-level from incremental synthesis */ -include save_design.inc - -/* Generate reports for incremental synthesis */ -include reports.inc - -/* Verify design */ -if (DO_VERIFY == "yes") { - compile -no_map -verify > LOG_PATH + verify_ + TOPLEVEL + .log -} - -/* Finish */ -sh date -exit Index: tags/a/syn/bin/tech_art_umc18.inc =================================================================== --- tags/a/syn/bin/tech_art_umc18.inc (revision 11) +++ tags/a/syn/bin/tech_art_umc18.inc (nonexistent) @@ -1,17 +0,0 @@ -/* Set Artisan Sage-X UMC 0.18u standard cell library */ - -search_path = {. /libs/Artisan/aci/sc-x/synopsys/ } + \ - { /libs/Artisan/aci/sc-x/symbols/synopsys/ } -snps = get_unix_variable("SYNOPSYS") -synthetic_library = { \ - snps + "/libraries/syn/dw01.sldb" \ - snps + "/libraries/syn/dw02.sldb" \ - snps + "/libraries/syn/dw03.sldb" \ - snps + "/libraries/syn/dw04.sldb" \ - snps + "/libraries/syn/dw05.sldb" \ - snps + "/libraries/syn/dw06.sldb" \ - snps + "/libraries/syn/dw07.sldb" } -target_library = { typical.db } -link_library = target_library + synthetic_library -symbol_library = { umc18.sdb } - Index: tags/a/syn/bin/cons_vs_umc18.inc =================================================================== --- tags/a/syn/bin/cons_vs_umc18.inc (revision 11) +++ tags/a/syn/bin/cons_vs_umc18.inc (nonexistent) @@ -1,51 +0,0 @@ -/* Constraints */ -CLK_UNCERTAINTY = 0.1 /* 100 ps */ -DFFPQ2_CKQ = 0.2 /* Clk to Q in technology time units */ -DFFPQ2_SETUP = 0.1 /* Setup time in technology time units */ - -/* Clocks constraints */ -create_clock CLK -period CLK_PERIOD -create_clock ECLK -period CLK_PERIOD -set_clock_skew all_clocks() -uncertainty CLK_UNCERTAINTY -set_dont_touch_network all_clocks() - -/* Reset constraints */ -set_driving_cell -none RST -set_drive 0 RST -set_dont_touch_network RST - -/* All inputs except reset and clock */ -all_inputs_wo_rst_clk = all_inputs() - CLK - RST - -/* Set output delays and load for output signals - * - * All outputs are assumed to go directly into - * external flip-flops for the purpose of this - * synthesis - */ -set_output_delay DFFPQ2_SETUP -clock CLK all_outputs() -set_load load_of(umcl18u250t2_typ/DFFPQ2/D) * 4 all_outputs() - -/* Input delay and driving cell of all inputs - * - * All these signals are assumed to come directly from - * flip-flops for the purpose of this synthesis - * - */ -set_input_delay DFFPQ2_CKQ -clock CLK all_inputs_wo_rst_clk -set_driving_cell -cell DFFPQ2 -pin Q all_inputs_wo_rst_clk - -/* Set design fanout */ -/* -set_max_fanout 10 TOPLEVEL -*/ - -/* Set area constraint */ -set_max_area MAX_AREA - -/* Optimize all near-critical paths to give extra slack for layout */ -c_range = CLK_PERIOD * 0.1 -group_path -critical_range c_range -name CLK -to CLK - -/* Operating conditions */ -set_operating_conditions TYPICAL Index: tags/a/syn/bin/save_design.inc =================================================================== --- tags/a/syn/bin/save_design.inc (revision 11) +++ tags/a/syn/bin/save_design.inc (nonexistent) @@ -1,5 +0,0 @@ -/* Save current design using synopsys format */ -write -hierarchy -format db -output GATE_PATH + STAGE + _ + TOPLEVEL + .db - -/* Save current design using verilog format */ -write -hierarchy -format verilog -output GATE_PATH + STAGE + _ + TOPLEVEL + .v Index: tags/a/bench/verilog/clkrst.v =================================================================== --- tags/a/bench/verilog/clkrst.v (revision 11) +++ tags/a/bench/verilog/clkrst.v (nonexistent) @@ -1,101 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Clock and Reset Generator //// -//// //// -//// This file is part of the PTC project //// -//// http://www.opencores.org/cores/ptc/ //// -//// //// -//// Description //// -//// Clock and reset generator. //// -//// //// -//// To Do: //// -//// Nothing //// -//// //// -//// Author(s): //// -//// - Damjan Lampret, lampret@opencores.org //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: not supported by cvs2svn $ -// Revision 1.1 2001/06/05 07:45:32 lampret -// Added initial RTL and test benches. There are still some issues with these files. -// -// - -`include "timescale.v" - -module clkrst(clk_o, rst_o, ptc_ecgt); - -// -// I/O ports -// -output clk_o; // Clock -output rst_o; // Reset -output ptc_ecgt; // (External) PTC clock/gate - -// -// Internal regs -// -reg clk_o; // Clock -reg rst_o; // Reset -reg ptc_ecgt; // PTC clock/gate - -initial begin - clk_o = 0; - rst_o = 1; - ptc_ecgt = 0; - #20; - rst_o = 0; -end - -// -// Clock -// -always #4 clk_o = ~clk_o; - -// -// PTC clock/gate generator -// -task gen_ptc_ecgt; -input [31:0] cycles; -integer i; -begin - if (cycles == -1) - ptc_ecgt = 1; - else - for (i = 2 * cycles; i; i = i - 1) begin - #4 ptc_ecgt = ~ptc_ecgt; - if (i % 20000 == 19999) - $write("."); - end -end -endtask - -endmodule Index: tags/a/bench/verilog/tb_defines.v =================================================================== --- tags/a/bench/verilog/tb_defines.v (revision 11) +++ tags/a/bench/verilog/tb_defines.v (nonexistent) @@ -1,61 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// PTC Testbench Definitions //// -//// //// -//// This file is part of the PTC project //// -//// http://www.opencores.org/cores/ptc/ //// -//// //// -//// Description //// -//// Testbench definitions that affect how testbench simulation //// -//// is performed. //// -//// //// -//// To Do: //// -//// Nothing //// -//// //// -//// Author(s): //// -//// - Damjan Lampret, lampret@opencores.org //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: not supported by cvs2svn $ -// Revision 1.1 2001/06/05 07:45:32 lampret -// Added initial RTL and test benches. There are still some issues with these files. -// -// - -// -// Run test bench with debug output -// -//`define DEBUG - -// -// Dump VCD -// -`define PTC_DUMP_VCD Index: tags/a/bench/verilog/wb_master.v =================================================================== --- tags/a/bench/verilog/wb_master.v (revision 11) +++ tags/a/bench/verilog/wb_master.v (nonexistent) @@ -1,306 +0,0 @@ -`include "timescale.v" - -// -*- Mode: Verilog -*- -// Filename : wb_master.v -// Description : Wishbone Master Behavorial -// Author : Winefred Washington -// Created On : Thu Jan 11 21:18:41 2001 -// Last Modified By: . -// Last Modified On: . -// Update Count : 0 -// Status : Unknown, Use with caution! - -// Description Specification -// General Description: 8, 16, 32-bit WISHBONE Master -// Supported cycles: MASTER, READ/WRITE -// MASTER, BLOCK READ/WRITE -// MASTER, RMW -// Data port, size: 8, 16, 32-bit -// Data port, granularity 8-bit -// Data port, Max. operand size 32-bit -// Data transfer ordering: little endian -// Data transfer sequencing: undefined -// - -module wb_master(CLK_I, RST_I, TAG_I, TAG_O, - ACK_I, ADR_O, CYC_O, DAT_I, DAT_O, ERR_I, RTY_I, SEL_O, STB_O, WE_O); - - input CLK_I; - input RST_I; - input [3:0] TAG_I; - output [3:0] TAG_O; - input ACK_I; - output [31:0] ADR_O; - output CYC_O; - input [31:0] DAT_I; - output [31:0] DAT_O; - input ERR_I; - input RTY_I; - output [3:0] SEL_O; - output STB_O; - output WE_O; - - reg [31:0] ADR_O; - reg [3:0] SEL_O; - reg CYC_O; - reg STB_O; - reg WE_O; - reg [31:0] DAT_O; - - wire [15:0] mem_sizes; // determines the data width of an address range - reg [31:0] write_burst_buffer[0:7]; - reg [31:0] read_burst_buffer[0:7]; - - reg GO; - integer cycle_end; - integer address; - integer data; - integer selects; - integer write_flag; - - // - // mem_sizes determines the data widths of memory space - // The memory space is divided into eight regions. Each - // region is controlled by a two bit field. - // - // Bits - // 00 = 8 bit memory space - // 01 = 16 bit - // 10 = 32 bit - // 11 = 64 bit (not supported in this model - // - - assign mem_sizes = 16'b10_01_10_11_00_01_10_11; - - function [1:0] data_width; - input [31:0] adr; - begin - casex (adr[31:29]) - 3'b000: data_width = mem_sizes[15:14]; - 3'b001: data_width = mem_sizes[13:12]; - 3'b010: data_width = mem_sizes[11:10]; - 3'b011: data_width = mem_sizes[9:8]; - 3'b100: data_width = mem_sizes[7:6]; - 3'b101: data_width = mem_sizes[5:4]; - 3'b110: data_width = mem_sizes[3:2]; - 3'b111: data_width = mem_sizes[1:0]; - 3'bxxx: data_width = 2'bxx; - endcase // casex (adr[31:29]) - end - endfunction - - always @(posedge CLK_I or posedge RST_I) - begin - if (RST_I) - begin - GO = 1'b0; - end - end - - // read single - task rd; - input [31:0] adr; - output [31:0] result; - - begin - cycle_end = 1; - address = adr; - selects = 255; - write_flag = 0; - - GO <= 1; - @(posedge CLK_I); -// GO <= 0; - - // wait for cycle to start - while (~CYC_O) - @(posedge CLK_I); - - // wait for cycle to end - while (CYC_O) - @(posedge CLK_I); - - result = data; -// $display(" Reading %h from address %h", result, address); - - end - endtask // read - - task wr; - input [31:0] adr; - input [31:0] dat; - input [3:0] sel; - begin - cycle_end = 1; - address = adr; - selects = sel; - write_flag = 1; - data = dat; - - GO <= 1; - @(posedge CLK_I); -// GO <= 0; - - // wait for cycle to start - while (~CYC_O) - @(posedge CLK_I); - - // wait for cycle to end - while (CYC_O) - @(posedge CLK_I); -// $display(" Writing %h to address %h", data, address); - - end - endtask // wr - - // block read - task blkrd; - input [31:0] adr; - input end_flag; - output [31:0] result; - - begin - write_flag = 0; - cycle_end = end_flag; - address = adr; - GO <= 1; - @(posedge CLK_I); -// GO <= 0; - - while (~(ACK_I & STB_O)) - @(posedge CLK_I); - - result = data; - end - endtask // blkrd - - // block write - task blkwr; - input [31:0] adr; - input [31:0] dat; - input [3:0] sel; - input end_flag; - begin - write_flag = 1; - cycle_end = end_flag; - address = adr; - data = dat; - selects = sel; - GO <= 1; - @(posedge CLK_I); -// GO <= 0; - - while (~(ACK_I & STB_O)) - @(posedge CLK_I); - - end - endtask // blkwr - - // RMW - task rmw; - input [31:0] adr; - input [31:0] dat; - input [3:0] sel; - output [31:0] result; - - begin - // read phase - write_flag = 0; - cycle_end = 0; - address = adr; - GO <= 1; - @(posedge CLK_I); -// GO <= 0; - - while (~(ACK_I & STB_O)) - @(posedge CLK_I); - - result = data; - - // write phase - write_flag = 1; - address = adr; - selects = sel; - GO <= 1; - data <= dat; - cycle_end <= 1; - @(posedge CLK_I); -// GO <= 0; - - while (~(ACK_I & STB_O)) - @(posedge CLK_I); - - end - endtask // rmw - - always @(posedge CLK_I) - begin - if (RST_I) - ADR_O <= 32'h0000_0000; - else - ADR_O <= address; - end - - always @(posedge CLK_I) - begin - if (RST_I | ERR_I | RTY_I) - CYC_O <= 1'b0; - else if ((cycle_end == 1) & ACK_I) - CYC_O <= 1'b0; - else if (GO | CYC_O) begin - CYC_O <= 1'b1; - GO <= 1'b0; - end - end - - // stb control - always @(posedge CLK_I) - begin - if (RST_I | ERR_I | RTY_I) - STB_O <= 1'b0; - else if (STB_O & ACK_I) - STB_O <= 1'b0; - else if (GO | STB_O) - STB_O <= 1'b1; - end - - // selects & data - always @(posedge CLK_I) - begin - if (write_flag == 0) begin - SEL_O <= 4'b1111; - if (STB_O & ACK_I) - data <= DAT_I; - end - else begin - case (data_width(address)) - 2'b00: begin - SEL_O <= {3'b000, selects[0]}; - DAT_O <= {data[7:0], data[7:0], data[7:0], data[7:0]}; - end - 2'b01: begin - SEL_O <= {2'b00, selects[1:0]}; - DAT_O <= {data[15:0], data[15:0]}; - end - 2'b10: begin - SEL_O <= selects; - DAT_O <= data; - end - endcase - end - end - - always @(posedge CLK_I) - begin - if (RST_I) - WE_O <= 1'b0; - else if (GO) - WE_O <= write_flag; - end - -endmodule - - - - - Index: tags/a/bench/verilog/timescale.v =================================================================== --- tags/a/bench/verilog/timescale.v (revision 11) +++ tags/a/bench/verilog/timescale.v (nonexistent) @@ -1 +0,0 @@ -`timescale 1ns/10ps Index: tags/a/bench/verilog/tb_top.v =================================================================== --- tags/a/bench/verilog/tb_top.v (revision 11) +++ tags/a/bench/verilog/tb_top.v (nonexistent) @@ -1,149 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// PTC Testbench Top //// -//// //// -//// This file is part of the PTC project //// -//// http://www.opencores.org/cores/ptc/ //// -//// //// -//// Description //// -//// Top level of testbench. It instantiates all blocks. //// -//// //// -//// To Do: //// -//// Nothing //// -//// //// -//// Author(s): //// -//// - Damjan Lampret, lampret@opencores.org //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: not supported by cvs2svn $ -// Revision 1.1 2001/06/05 07:45:32 lampret -// Added initial RTL and test benches. There are still some issues with these files. -// -// - -`include "timescale.v" - -module tb_top; - -parameter aw = 32; -parameter dw = 32; - -// -// Interconnect wires -// -wire clk; // Clock -wire rst; // Reset -wire cyc; // Cycle valid -wire [aw-1:0] adr; // Address bus -wire [dw-1:0] dat_m; // Data bus from PTC to WBM -wire [3:0] sel; // Data selects -wire we; // Write enable -wire stb; // Strobe -wire [dw-1:0] dat_ptc;// Data bus from WBM to PTC -wire ack; // Successful cycle termination -wire err; // Failed cycle termination -wire ptc_ecgt;// External PTC clock/gate - -// -// Internal registers -// -reg ptc_capt;// Capture signal - -// -// Instantiation of Clock/Reset Generator -// -clkrst clkrst( - // Clock - .clk_o(clk), - // Reset - .rst_o(rst), - // External clock/gate - .ptc_ecgt(ptc_ecgt) -); - -// -// Instantiation of Master WISHBONE BFM -// -wb_master wb_master( - // WISHBONE Interface - .CLK_I(clk), - .RST_I(rst), - .CYC_O(cyc), - .ADR_O(adr), - .DAT_O(dat_ptc), - .SEL_O(sel), - .WE_O(we), - .STB_O(stb), - .DAT_I(dat_m), - .ACK_I(ack), - .ERR_I(err), - .RTY_I(0), - .TAG_I(4'b0) -); - -// -// Instantiation of PTC core -// -ptc ptc( - // WISHBONE Interface - .wb_clk_i(clk), - .wb_rst_i(rst), - .wb_cyc_i(cyc), - .wb_adr_i(adr[15:0]), - .wb_dat_i(dat_ptc), - .wb_sel_i(sel), - .wb_we_i(we), - .wb_stb_i(stb), - .wb_dat_o(dat_m), - .wb_ack_o(ack), - .wb_err_o(err), - .wb_inta_o(), - - // External PTC Interface - .gate_clk_pad_i(ptc_ecgt), - .capt_pad_i(ptc_capt), - .pwm_pad_o(), - .oen_padoen_o() -); - -initial ptc_capt = 0; - -// -// Task to set ptc_capt -// -task set_ptc_capt; -input bit; -begin - ptc_capt = bit; -end -endtask - -endmodule Index: tags/a/bench/verilog/tb_tasks.v =================================================================== --- tags/a/bench/verilog/tb_tasks.v (revision 11) +++ tags/a/bench/verilog/tb_tasks.v (nonexistent) @@ -1,964 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// PTC Testbench Tasks //// -//// //// -//// This file is part of the PTC project //// -//// http://www.opencores.org/cores/ptc/ //// -//// //// -//// Description //// -//// Testbench tasks. //// -//// //// -//// To Do: //// -//// Nothing //// -//// //// -//// Author(s): //// -//// - Damjan Lampret, lampret@opencores.org //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: not supported by cvs2svn $ -// Revision 1.1 2001/06/05 07:45:32 lampret -// Added initial RTL and test benches. There are still some issues with these files. -// -// - -`include "timescale.v" -`include "defines.v" -`include "tb_defines.v" - -module tb_tasks; - -integer nr_failed; -integer ints_disabled; -integer ints_working; -integer capt_working; -integer monitor_ptc_pwm, pwm_l1, pwm_l2; - -// -// Count/report failed tests -// -task failed; -begin - $display("FAILED !!!"); - nr_failed = nr_failed + 1; -end -endtask - -// -// Set RPTC_CNTR register -// -task setcntr; -input [31:0] val; - -begin - #100 tb_top.wb_master.wr(`PTC_RPTC_CNTR<<2, val, 4'b1111); -end - -endtask - -// -// Set PTC_RPTC_HRC register -// -task sethrc; -input [31:0] val; - -begin - #100 tb_top.wb_master.wr(`PTC_RPTC_HRC<<2, val, 4'b1111); -end - -endtask - -// -// Set PTC_RPTC_LRC register -// -task setlrc; -input [31:0] val; - -begin - #100 tb_top.wb_master.wr(`PTC_RPTC_LRC<<2, val, 4'b1111); -end - -endtask - -// -// Set PTC_RPTC_CTRL register -// -task setctrl; -input [31:0] val; - -begin - #100 tb_top.wb_master.wr(`PTC_RPTC_CTRL<<2, val, 4'b1111); -end - -endtask - -// -// Display RPTC_CNTR register -// -task showcntr; - -reg [31:0] tmp; -begin - tb_top.wb_master.rd(`PTC_RPTC_CNTR<<2, tmp); - $write(" RPTC_CNTR: %h", tmp); -end - -endtask - -// -// Display RPTC_HRC register -// -task showhrc; - -reg [31:0] tmp; -begin - tb_top.wb_master.rd(`PTC_RPTC_HRC<<2, tmp); - $write(" RPTC_HRC: %h", tmp); -end - -endtask -// -// Display RPTC_LRC register -// -task showlrc; - -reg [31:0] tmp; -begin - tb_top.wb_master.rd(`PTC_RPTC_LRC<<2, tmp); - $write(" RPTC_LRC:%h", tmp); -end - -endtask -// -// Display RPTC_CTRL register -// -task showctrl; - -reg [31:0] tmp; -begin - tb_top.wb_master.rd(`PTC_RPTC_CTRL<<2, tmp); - $write(" RPTC_CTRL: %h", tmp); -end - -endtask - -// -// Compare parameter with PTC_RPTC_CNTR register -// -task comp_cntr; -input [31:0] val; -output ret; - -reg [31:0] tmp; -reg ret; -begin - tb_top.wb_master.rd(`PTC_RPTC_CNTR<<2, tmp); - - if (tmp == val) - ret = 1; - else - ret = 0; -end - -endtask - -// -// Compare parameter with PTC_RPTC_HRC register -// -task comp_hrc; -input [31:0] val; -output ret; - -reg [31:0] tmp; -reg ret; -begin - tb_top.wb_master.rd(`PTC_RPTC_HRC<<2, tmp); - - if (tmp == val) - ret = 1; - else - ret = 0; -end - -endtask - - -// -// Compare parameter with PTC_RPTC_LRC register -// -task comp_lrc; -input [31:0] val; -output ret; - -reg [31:0] tmp; -reg ret; -begin - tb_top.wb_master.rd(`PTC_RPTC_LRC<<2, tmp); - - if (tmp == val) - ret = 1; - else - ret = 0; -end - -endtask - -// -// Get PTC_RPTC_CNTR register -// -task getcntr; -output [31:0] tmp; - -begin - tb_top.wb_master.rd(`PTC_RPTC_CNTR<<2, tmp); -end - -endtask - -// -// Get PTC_RPTC_HRC register -// -task gethrc; -output [31:0] tmp; - -begin - tb_top.wb_master.rd(`PTC_RPTC_HRC<<2, tmp); -end - -endtask - -// -// Get PTC_RPTC_LRC register -// -task getlrc; -output [31:0] tmp; - -begin - tb_top.wb_master.rd(`PTC_RPTC_LRC<<2, tmp); -end - -endtask - -// -// Get PTC_RPTC_CTRL register -// -task getctrl; -output [31:0] tmp; - -begin - tb_top.wb_master.rd(`PTC_RPTC_CTRL<<2, tmp); -end - -endtask - -// -// Test operation of control bit PTC_RPTC_CTRL[ECLK] -// -task test_eclk; -integer l1, l2; -begin - $write(" Testing control bit RPTC_CTRL[ECLK] ..."); - - // - // Phase 1 - // - // PTC uses WISHBONE clock - // - - // Disable PTC, reset counter - setctrl(1 << `PTC_RPTC_CTRL_CNTRRST); - - // Set PTC_RPTC_HRC and PTC_RPTC_LRC to some high value - sethrc('hffffffff); - setlrc('hffffffff); - - // Enable PTC - setctrl(1 << `PTC_RPTC_CTRL_EN); - - // Wait for time to advance - #20000; - - // Get counter - getcntr(l1); - - // - // Phase 2 - // - // PTC uses external clock - // - - // Disable PTC, reset counter - setctrl(1 << `PTC_RPTC_CTRL_CNTRRST); - - // Enable PTC, use external clock - setctrl(1 << `PTC_RPTC_CTRL_EN | 1 << `PTC_RPTC_CTRL_ECLK); -`ifdef PTC_DEBUG - showctrl; - showcntr; -`endif - // Do 10000 external clock cyles - tb_top.clkrst.gen_ptc_ecgt(10000); - - // Get counter - getcntr(l2); - - // - // Phase 3 - // - // Compare counter from phase 1 and phase 2 - // - if (l2 - l1 == 7498) - $display(" OK"); - else - failed; -end -endtask - -// -// Test operation of control bit PTC_RPTC_CTRL[EN] -// -task test_en; -integer l1, l2; -begin - $write(" Testing control bit RPTC_CTRL[EN] ..."); - - // - // Phase 1 - // - // PTC does 1000 external clock cycles - // - - // Disable PTC, reset counter - setctrl(1 << `PTC_RPTC_CTRL_CNTRRST); - - // Enable PTC, use external clock - setctrl(1 << `PTC_RPTC_CTRL_EN | 1 << `PTC_RPTC_CTRL_ECLK); -`ifdef PTC_DEBUG - showctrl; - showcntr; -`endif - // Do 1000 external clock cycles - tb_top.clkrst.gen_ptc_ecgt(1000); - - // Get counter - getcntr(l1); - - // - // Phase 2 - // - // Disable PTC and run for another 1000 external clock cycles - // - - // Disable PTC, use external clock - setctrl(1 << `PTC_RPTC_CTRL_ECLK); -`ifdef PTC_DEBUG - showctrl; - showcntr; -`endif - // Do 1000 external clock cycles - tb_top.clkrst.gen_ptc_ecgt(1000); - - // Get counter - getcntr(l2); - - // - // Phase 3 - // - // Compare counter from phase 1 and phase 2. Should be the same. - // - if (l1 == l2 && l2 == 1000) - $display(" OK"); - else - failed; -end -endtask - -// -// Test operation of control bit PTC_RPTC_CTRL[NEC] -// -task test_nec; -integer l1, l2; -begin - $write(" Testing control bit RPTC_CTRL[NEC] ..."); - - // - // Phase 1 - // - // PTC does 1000 external clock cycles - // - - // Disable PTC, reset counter - setctrl(1 << `PTC_RPTC_CTRL_CNTRRST); - - // Enable PTC, use external clock - setctrl(1 << `PTC_RPTC_CTRL_EN | 1 << `PTC_RPTC_CTRL_ECLK); -`ifdef PTC_DEBUG - showctrl; - showcntr; -`endif - // Do 1000 external clock cycles - tb_top.clkrst.gen_ptc_ecgt(1000); - - // Get counter - getcntr(l1); - - // - // Phase 2 - // - // Enable PTC_RPTC_CTRL[NEC] and run for another 1000 external clock cycles - // - - // Enable PTC_RPTC_CTRL[NEC], use external clock - setctrl(1 << `PTC_RPTC_CTRL_EN | 1 << `PTC_RPTC_CTRL_ECLK | 1 << `PTC_RPTC_CTRL_NEC); -`ifdef PTC_DEBUG - showctrl; - showcntr; -`endif - // Do 1000 external clock cycles - tb_top.clkrst.gen_ptc_ecgt(1000); - - // Get counter - getcntr(l2); - - // - // Phase 3 - // - // Compare counter from phase 1 and phase 2. - // - if (l2 - l1 == 1001) - $display(" OK"); - else - failed; -end -endtask - -// -// Test operation of control bit PTC_RPTC_CTRL[CNTRRST] -// -task test_cntrrst; -integer l1, l2; -begin - $write(" Testing control bit RPTC_CTRL[CNTRRST] ..."); - - // - // Phase 1 - // - // Set counter and clear it - // - - // Disable PTC - setctrl(0); - - // Manually set counter - setcntr('d1234); -`ifdef PTC_DEBUG - showctrl; - showcntr; -`endif - - // Get counter - getcntr(l1); - - // Disable PTC, reset counter - setctrl(1 << `PTC_RPTC_CTRL_CNTRRST); - - // Get counter - getcntr(l2); - - // - // Phase 3 - // - // Counter l1 should be 1234 and counter l2 should be zero - // - if (l1 == 1234 && l2 == 0) - $display(" OK"); - else - failed; -end -endtask - -// -// Test operation of control bit PTC_RPTC_CTRL[OE] -// -task test_oe; -integer l1, l2; -begin - $write(" Testing control bit RPTC_CTRL[OE] ..."); - - // - // Phase 1 - // - // Clear PTC_RPTC_CTRL[OE] - // - - // Disable PTC, clear PTC_RPTC_CTRL[OE] - setctrl(0); - -`ifdef PTC_DEBUG - showctrl; -`endif - - // Get ptc_oen - l1 = tb_top.ptc.oen_padoen_o; - - // - // Phase 2 - // - // Set PTC_RPTC_CTRL[OE] - // - - // Disable PTC, set PTC_RPTC_CTRL[OE] - setctrl(1 << `PTC_RPTC_CTRL_OE); - -`ifdef PTC_DEBUG - showctrl; -`endif - - // Get ptc_oen - l2 = tb_top.ptc.oen_padoen_o; - - // - // Phase 3 - // - // l1 should be 1 and l2 should be zero - // - if (l1 && !l2) - $display(" OK"); - else - failed; -end -endtask - -// -// Test operation of control bit PTC_RPTC_CTRL[CAPTE] -// -task test_capte; -integer l1, l2; -begin - $write(" Testing control bit RPTC_CTRL[CAPTE] ..."); - - // - // Phase 1 - // - // Run counter off external clock and capture it into PTC_RPTC_HRC/LRC - // - - // Disable PTC, clear counter - setctrl(1 << `PTC_RPTC_CTRL_CNTRRST); - - // Set PTC_RPTC_HRC/LRC to some high value - sethrc('hffffffff); - setlrc('hffffffff); - - // Enable PTC, use external clock, enable PTC_RPTC_CTRL[CAPTE] - setctrl(1 << `PTC_RPTC_CTRL_EN | 1 << `PTC_RPTC_CTRL_ECLK | 1 << `PTC_RPTC_CTRL_CAPTE); - -`ifdef PTC_DEBUG - showctrl; -`endif - - // Do 1000 external clock cycles - tb_top.clkrst.gen_ptc_ecgt(1000); - - // Do posedge ptc_capt - tb_top.set_ptc_capt(1); - - // Get PTC_RPTC_HRC - gethrc(l1); - - // Do additional 1000 external clock cycles - tb_top.clkrst.gen_ptc_ecgt(1000); - - // Do posedge ptc_capt - tb_top.set_ptc_capt(0); - - // Get PTC_RPTC_LRC - getlrc(l2); - - // - // Phase 3 - // - // l1 should be 1000 and l2 should be 2000 - // - if (l1 == 1000 && l2 == 2000) begin - $display(" OK"); - capt_working = 1; - end else - failed; -end -endtask - -// -// Test operation of control bit PTC_RPTC_CTRL[SINGLE] -// -task test_single; -integer l1, l2; -begin - $write(" Testing control bit RPTC_CTRL[SINGLE] ..."); - - // - // Phase 1 - // - // Run counter off external clock with cleared PTC_RPTC_CTRL[SINGLE]. - // Counter should roll over when it reaches PTC_RPTC_LRC value. - // - - // Disable PTC, clear counter - setctrl(1 << `PTC_RPTC_CTRL_CNTRRST); - - // Set PTC_RPTC_HRC to some high value and PTC_RPTC_LRC to 1000 - sethrc('hffffffff); - setlrc('d1000); - - // Enable PTC, use external clock - setctrl(1 << `PTC_RPTC_CTRL_EN | 1 << `PTC_RPTC_CTRL_ECLK); -`ifdef PTC_DEBUG - showctrl; -`endif - - // Do 1500 external clock cycles - tb_top.clkrst.gen_ptc_ecgt(1500); - - // Get counter - getcntr(l1); - - // - // Phase 2 - // - // Run counter off external clock with PTC_RPTC_CTRL[SINGLE] set. - // Counter should stop when it reaches PTC_RPTC_LRC value. - // - - // Disable PTC, clear counter - setctrl(1 << `PTC_RPTC_CTRL_CNTRRST); - - // Set PTC_RPTC_HRC to some high value and PTC_RPTC_LRC to 1000 - sethrc('hffffffff); - setlrc('d1000); - - // Enable PTC, use external clock, set PTC_RPTC_CTRL[SINGLE] - setctrl(1 << `PTC_RPTC_CTRL_EN | 1 << `PTC_RPTC_CTRL_ECLK | 1 << `PTC_RPTC_CTRL_SINGLE); -`ifdef PTC_DEBUG - showctrl; -`endif - - // Do 1500 external clock cycles - tb_top.clkrst.gen_ptc_ecgt(1500); - - // Get counter - getcntr(l2); - - - // - // Phase 3 - // - // l1 should be 500 and l2 should be 1000 - // - if (l1 == 500 && l2 == 1000) - $display(" OK"); - else - failed; -end -endtask - -// -// Test operation of control bit PTC_RPTC_CTRL[INTE] and PTC_RPTC_CTRL[INT] -// -task test_ints; -integer l1, l2, l3; -begin - $write(" Testing control bit RPTC_CTRL[INTE] and PTC_RPTC_CTRL[INT]..."); - - // - // Phase 1 - // - // Run counter off external clock. - // Counter should generate an interrupt when it reaches PTC_RPTC_LRC value. - // - - // Disable PTC, clear counter - setctrl(1 << `PTC_RPTC_CTRL_CNTRRST); - - // Set PTC_RPTC_HRC to some high value and PTC_RPTC_LRC to 1000 - sethrc('hffffffff); - setlrc('d1000); - - // Disable detection of spurious interrupts - ints_disabled = 0; - - // Enable PTC, use external clock, set PTC_RPTC_CTRL[INTE] - setctrl(1 << `PTC_RPTC_CTRL_EN | 1 << `PTC_RPTC_CTRL_ECLK | 1 << `PTC_RPTC_CTRL_INTE); -`ifdef PTC_DEBUG - showctrl; -`endif - - // Do 999 external clock cycles - tb_top.clkrst.gen_ptc_ecgt(999); - - // Sample interrupt request. It should be zero. - l1 = tb_top.ptc.wb_inta_o; - - // Do 1 additional external clock cycles - tb_top.clkrst.gen_ptc_ecgt(10); - - // Sample interrupt request. It should be one. - l2 = tb_top.ptc.wb_inta_o; - - // - // Phase 2 - // - // Mask interrupt. - // - - // Enable detection of spurious interrupts - ints_disabled = 1; - - // Mask interrupt - setctrl(1 << `PTC_RPTC_CTRL_EN | 1 << `PTC_RPTC_CTRL_ECLK); - - // Sample interrupt request. It should be again zero. - l3 = tb_top.ptc.wb_inta_o; - - // - // Phase 3 - // - // l1 should be zero, l2 should be one and l3 should be zero - // - if (!l1 && l2 && !l3) begin - $display(" OK"); - ints_working = ints_working + 1; - end else - failed; -end -endtask - -always @(posedge tb_top.ptc.gate_clk_pad_i) - if (monitor_ptc_pwm && !tb_top.ptc.pwm_pad_o) - pwm_l1 = pwm_l1 + 1; - -always @(posedge tb_top.ptc.gate_clk_pad_i) - if (monitor_ptc_pwm && tb_top.ptc.pwm_pad_o) - pwm_l2 = pwm_l2 + 1; - -// -// Test PWM mode -// -task test_pwm; -begin - $write(" Testing PWM mode ..."); - - // - // Phase 1 - // - // Run counter off external clock with PWM low for 10 clocks and - // PWM high for 20 clocks - // - - // Disable PTC, clear counter - setctrl(1 << `PTC_RPTC_CTRL_CNTRRST); - - // Set intervals 10 and 20 - sethrc('d10); - setlrc('d30); - - // Enable PTC, use external clock - setctrl(1 << `PTC_RPTC_CTRL_EN | 1 << `PTC_RPTC_CTRL_ECLK); -`ifdef PTC_DEBUG - showctrl; -`endif - // Start monitoring ptc_pwm - monitor_ptc_pwm = 1; - - // Do 3000 external clock cycles - tb_top.clkrst.gen_ptc_ecgt(3000); - - // Stop monitoring ptc_pwm - monitor_ptc_pwm = 0; - - // - // Phase 2 - // - // l1 should be 1000 and l2 should be 2000 - // - if (pwm_l1 == 1000 && pwm_l2 == 2000) - $display(" OK"); - else - failed; -end -endtask - -// -// Test gate feature -// -task test_gate; -integer l1, l2, l3; -begin - $write(" Testing gate feature ..."); - - // - // Phase 1 - // - // Run counter off WB clock and in the middle assert gating - // - - // Disable PTC, clear counter - setctrl(1 << `PTC_RPTC_CTRL_CNTRRST); - - // Set PTC_RPTC_HRC/LRC to some high value - sethrc('hffffffff); - setlrc('hffffffff); - - // Enable PTC - setctrl(1 << `PTC_RPTC_CTRL_EN); -`ifdef PTC_DEBUG - showctrl; -`endif - - // Increment counter - #5000; - - // Get counter - getcntr(l1); - - // Increment counter - #5000; - - // Assert gate - tb_top.clkrst.gen_ptc_ecgt(-1); - - // Get counter - getcntr(l2); - - // Increment counter - #5000; - - // Get counter (should be the same as l2) - getcntr(l3); - - // - // Phase 2 - // - // l1 should be nonzero and l2 and l3 should be the same - // - if (l1 && l1 < l2 && l2 == l3) - $display(" OK"); - else - failed; -end -endtask - -// -// Test operation of control bit PTC_RPTC_CTRL[INTE] and PTC_RPTC_CTRL[INT] -// -task test_modes; -integer l1, l2, l3; -begin - - // Test PWM mode - test_pwm; - - $write(" Testing timer/counter mode ..."); - if (nr_failed == 0) - $display(" OK"); - else - failed; - - // Test gate feature - test_gate; - - $write(" Testing interrupt feature ..."); - if (ints_working == 1) - $display(" OK"); - else - failed; - - $write(" Testing capture feature ..."); - if (capt_working == 1) - $display(" OK"); - else - failed; - -end -endtask - -// -// Do continues check for interrupts -// -always @(posedge tb_top.ptc.wb_inta_o) - if (ints_disabled) begin - $display("Spurious interrupt detected. "); - failed; - ints_working = 9876; - $display; - end - -// -// Start of testbench test tasks -// -initial begin -`ifdef PTC_DUMP_VCD - $dumpfile("../sim/tb_top.vcd"); - $dumpvars(0); -`endif - nr_failed = 0; - ints_disabled = 1; - ints_working = 0; - capt_working = 0; - monitor_ptc_pwm = 0; - pwm_l1 = 0; - pwm_l2 = 0; - $display; - $display("###"); - $display("### PTC IP Core Verification ###"); - $display("###"); - $display; - $display("I. Testing correct operation of RPTC_CTRL control bits"); - $display; - test_eclk; - test_oe; - test_cntrrst; - test_en; - test_nec; - test_capte; - test_single; - test_ints; - $display; - $display("II. Testing modes of operation ..."); - $display; - test_modes; - $display; - $display("###"); - $display("### FAILED TESTS: %d ###", nr_failed); - $display("###"); - $display; - $finish; -end - -endmodule Index: trunk/doc/src/ptc_spec.doc =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/src/ptc_spec.doc =================================================================== --- trunk/doc/src/ptc_spec.doc (revision 11) +++ trunk/doc/src/ptc_spec.doc (nonexistent)

trunk/doc/src/ptc_spec.doc Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/doc/ptc_spec.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/ptc_spec.pdf =================================================================== --- trunk/doc/ptc_spec.pdf (revision 11) +++ trunk/doc/ptc_spec.pdf (nonexistent)

trunk/doc/ptc_spec.pdf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/sim/rtl_sim/bin/sim.sh =================================================================== --- trunk/sim/rtl_sim/bin/sim.sh (revision 11) +++ trunk/sim/rtl_sim/bin/sim.sh (nonexistent) @@ -1,125 +0,0 @@ -#!/bin/bash - -# -# This script runs RTL and gate-level simulation using different simultion tools. -# Right now Cadence Verilog-XL and NCSim are supported. -# -# Author: Damjan Lampret -# - -# -# User definitions -# - -# Set simulation tool you are using (xl, ncsim, ncver) -SIMTOOL=ncsim - -# Set test bench top module(s) -TB_TOP="tb_tasks" - -# Set include directories -INCLUDE_DIRS="../../../rtl/verilog/ ../../../bench/verilog/" - -# Set test bench files -BENCH_FILES="../../../bench/verilog/*.v" - -# Set RTL source files -RTL_FILES="../../../rtl/verilog/*.v" - -# Set gate-level netlist files -GATE_FILES="../syn/out/final_ptc.v" - -# Set libraries (standard cell etc.) -LIB_FILES="/libs/Virtual_silicon/UMCL18U250D2_2.1/verilog_simulation_models/*.v" - -# Set parameters for simulation tool -if [ $SIMTOOL == xl ]; then - PARAM="+turbo+3 -q" - for i in $INCLUDE_DIRS; do - INCDIR=$INCDIR" +incdir+$i" - done -elif [ $SIMTOOL == ncver ]; then - NCVER_PARAM="" - for i in $INCLUDE_DIRS; do - INCDIR=$INCDIR" +incdir+$i" - done -elif [ $SIMTOOL == ncsim ]; then - NCPREP_PARAM="-UPDATE +overwrite" - NCSIM_PARAM="-MESSAGES -NOCOPYRIGHT" - for i in $INCLUDE_DIRS; do - INCDIR=$INCDIR" +incdir+$i" - done -else - echo "$SIMTOOL is unsupported simulation tool." - exit 0 -fi - -# -# Don't change anything below unless you know what you are doing -# - -# Run simulation in sim directory -cd ../sim - -# Run actual simulation - -# Cadence Verilog-XL -if [ $SIMTOOL == xl ]; then - - # RTL simulation - if [ "$1" == rtl ]; then - verilog $PARAM $INCDIR $BENCH_FILES $RTL_FILES - - # Gate-level simulation - elif [ "$1" == gate ]; then - verilog $PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES - - # Wrong parameter or no parameter - else - echo "Usage: $0 [rtl|gate]" - exit 0 - fi - -# Cadence Ncverilog -elif [ $SIMTOOL == ncver ]; then - - # RTL simulation - if [ "$1" == rtl ]; then - ncverilog $NCVER_PARAM $INCDIR $BENCH_FILES $RTL_FILES - cp ncverilog.log ../log - - # Gate-level simulation - elif [ "$1" == gate ]; then - ncverilog $NCVER_PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES - cp ncverilog.log ../log - - # Wrong parameter or no parameter - else - echo "Usage: $0 [rtl|gate]" - exit 0 - fi - -# Cadence Ncsim -elif [ $SIMTOOL == ncsim ]; then - - # RTL simulation - if [ "$1" == rtl ]; then - ncprep $NCPREP_PARAM $INCDIR $BENCH_FILES $RTL_FILES - ./RUN_NC - - # Gate-level simulation - elif [ "$1" == gate ]; then - ncprep $NCPREP_PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES - ./RUN_NC - - # Wrong parameter or no parameter - else - echo "Usage: $0 [rtl|gate]" - exit 0 - fi - -# Unsupported simulation tool -else - echo "$SIMTOOL is unsupported simulation tool." - exit 0; -fi

trunk/sim/rtl_sim/bin/sim.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/syn/run/dodesign =================================================================== --- trunk/syn/run/dodesign (revision 11) +++ trunk/syn/run/dodesign (nonexistent) @@ -1,5 +0,0 @@ -#!/bin/sh -f - -# nohup dc_shell -f top.scr | tee ../logs/top.log -dc_shell -f top_ptc.scr > ../logs/top_ptc.log -mv command.log ../logs

trunk/syn/run/dodesign Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/syn/bin/read_design.inc =================================================================== --- trunk/syn/bin/read_design.inc (revision 11) +++ trunk/syn/bin/read_design.inc (nonexistent) @@ -1,11 +0,0 @@ -/* Set search path for verilog include files */ -search_path = search_path + { RTL_PATH } + { GATE_PATH } - -/* Read verilog files of the PTC IP core */ -if (TOPLEVEL == "ptc") { - read -f verilog ptc.v -} else { - echo "Non-existing top level." - exit -} - Index: trunk/syn/bin/cons_art_umc18.inc =================================================================== --- trunk/syn/bin/cons_art_umc18.inc (revision 11) +++ trunk/syn/bin/cons_art_umc18.inc (nonexistent) @@ -1,51 +0,0 @@ -/* Constraints */ -CLK_UNCERTAINTY = 0.1 /* 100 ps */ -DFFHQX2_CKQ = 0.2 /* Clk to Q in technology time units */ -DFFHQX2_SETUP = 0.1 /* Setup time in technology time units */ - -/* Clocks constraints */ -create_clock CLK -period CLK_PERIOD -create_clock ECLK -period CLK_PERIOD -set_clock_skew all_clocks() -uncertainty CLK_UNCERTAINTY -set_dont_touch_network all_clocks() - -/* Reset constraints */ -set_driving_cell -none RST -set_drive 0 RST -set_dont_touch_network RST - -/* All inputs except reset and clock */ -all_inputs_wo_rst_clk = all_inputs() - CLK - RST - -/* Set output delays and load for output signals - * - * All outputs are assumed to go directly into - * external flip-flops for the purpose of this - * synthesis - */ -set_output_delay DFFHQX2_SETUP -clock CLK all_outputs() -set_load load_of(typical/DFFHQX2/D) * 1 all_outputs() - -/* Input delay and driving cell of all inputs - * - * All these signals are assumed to come directly from - * flip-flops for the purpose of this synthesis - * - */ -set_input_delay DFFHQX2_CKQ -clock CLK all_inputs_wo_rst_clk -set_driving_cell -cell DFFHQX2 -pin Q all_inputs_wo_rst_clk - -/* Set design fanout */ -/* -set_max_fanout 10 TOPLEVEL -*/ - -/* Set area constraint */ -set_max_area MAX_AREA - -/* Optimize all near-critical paths to give extra slack for layout */ -c_range = CLK_PERIOD * 0.05 -group_path -critical_range c_range -name CLK -to CLK - -/* Operating conditions */ -set_operating_conditions typical Index: trunk/syn/bin/top_ptc.scr =================================================================== --- trunk/syn/bin/top_ptc.scr (revision 11) +++ trunk/syn/bin/top_ptc.scr (nonexistent) @@ -1,65 +0,0 @@ -/* - * User defines for synthesizing PTC IP core - * - */ -TOPLEVEL = ptc -include select_tech.inc -CLK = clk_i -ECLK = ptc_ecgt -RST = rst_i -CLK_PERIOD = 5 /* 200 MHz */ -MAX_AREA = 0 /* Push hard */ -DO_UNGROUP = yes /* yes, no */ -DO_VERIFY = yes /* yes, no */ - -/* Starting timestamp */ -sh date - -/* Set some basic variables related to environment */ -include set_env.inc -STAGE = final - -/* Load libraries */ -include tech_ + TECH + .inc - -/* Load HDL source files */ -include read_design.inc > LOG_PATH + read_design_ + TOPLEVEL + .log - -/* Set design top */ -current_design TOPLEVEL - -/* Link all blocks and uniquify them */ -link -uniquify -check_design > LOG_PATH + check_design_ + TOPLEVEL + .log - -/* Apply constraints */ -if (TECH == "vs_umc18") { - include cons_vs_umc18.inc -} else if (TECH == "art_umc18") { - include cons_art_umc18.inc -} else { - echo "Error: Unsupported technology" - exit -} - -/* Lets do basic synthesis */ -if (DO_UNGROUP == "yes") { - ungroup -all -} -compile -boundary_optimization -map_effort low - -/* Dump gate-level from incremental synthesis */ -include save_design.inc - -/* Generate reports for incremental synthesis */ -include reports.inc - -/* Verify design */ -if (DO_VERIFY == "yes") { - compile -no_map -verify > LOG_PATH + verify_ + TOPLEVEL + .log -} - -/* Finish */ -sh date -exit Index: trunk/syn/bin/tech_art_umc18.inc =================================================================== --- trunk/syn/bin/tech_art_umc18.inc (revision 11) +++ trunk/syn/bin/tech_art_umc18.inc (nonexistent) @@ -1,17 +0,0 @@ -/* Set Artisan Sage-X UMC 0.18u standard cell library */ - -search_path = {. /libs/Artisan/aci/sc-x/synopsys/ } + \ - { /libs/Artisan/aci/sc-x/symbols/synopsys/ } -snps = get_unix_variable("SYNOPSYS") -synthetic_library = { \ - snps + "/libraries/syn/dw01.sldb" \ - snps + "/libraries/syn/dw02.sldb" \ - snps + "/libraries/syn/dw03.sldb" \ - snps + "/libraries/syn/dw04.sldb" \ - snps + "/libraries/syn/dw05.sldb" \ - snps + "/libraries/syn/dw06.sldb" \ - snps + "/libraries/syn/dw07.sldb" } -target_library = { typical.db } -link_library = target_library + synthetic_library -symbol_library = { umc18.sdb } - Index: trunk/syn/bin/cons_vs_umc18.inc =================================================================== --- trunk/syn/bin/cons_vs_umc18.inc (revision 11) +++ trunk/syn/bin/cons_vs_umc18.inc (nonexistent) @@ -1,51 +0,0 @@ -/* Constraints */ -CLK_UNCERTAINTY = 0.1 /* 100 ps */ -DFFPQ2_CKQ = 0.2 /* Clk to Q in technology time units */ -DFFPQ2_SETUP = 0.1 /* Setup time in technology time units */ - -/* Clocks constraints */ -create_clock CLK -period CLK_PERIOD -create_clock ECLK -period CLK_PERIOD -set_clock_skew all_clocks() -uncertainty CLK_UNCERTAINTY -set_dont_touch_network all_clocks() - -/* Reset constraints */ -set_driving_cell -none RST -set_drive 0 RST -set_dont_touch_network RST - -/* All inputs except reset and clock */ -all_inputs_wo_rst_clk = all_inputs() - CLK - RST - -/* Set output delays and load for output signals - * - * All outputs are assumed to go directly into - * external flip-flops for the purpose of this - * synthesis - */ -set_output_delay DFFPQ2_SETUP -clock CLK all_outputs() -set_load load_of(umcl18u250t2_typ/DFFPQ2/D) * 4 all_outputs() - -/* Input delay and driving cell of all inputs - * - * All these signals are assumed to come directly from - * flip-flops for the purpose of this synthesis - * - */ -set_input_delay DFFPQ2_CKQ -clock CLK all_inputs_wo_rst_clk -set_driving_cell -cell DFFPQ2 -pin Q all_inputs_wo_rst_clk - -/* Set design fanout */ -/* -set_max_fanout 10 TOPLEVEL -*/ - -/* Set area constraint */ -set_max_area MAX_AREA - -/* Optimize all near-critical paths to give extra slack for layout */ -c_range = CLK_PERIOD * 0.1 -group_path -critical_range c_range -name CLK -to CLK - -/* Operating conditions */ -set_operating_conditions TYPICAL Index: trunk/syn/bin/save_design.inc =================================================================== --- trunk/syn/bin/save_design.inc (revision 11) +++ trunk/syn/bin/save_design.inc (nonexistent) @@ -1,5 +0,0 @@ -/* Save current design using synopsys format */ -write -hierarchy -format db -output GATE_PATH + STAGE + _ + TOPLEVEL + .db - -/* Save current design using verilog format */ -write -hierarchy -format verilog -output GATE_PATH + STAGE + _ + TOPLEVEL + .v Index: trunk/syn/bin/tech_vs_umc18.inc =================================================================== --- trunk/syn/bin/tech_vs_umc18.inc (revision 11) +++ trunk/syn/bin/tech_vs_umc18.inc (nonexistent) @@ -1,16 +0,0 @@ -/* Set Virtual Silicon UMC 0.18u standard cell library */ - -search_path = {. /libs/Virtual_silicon/UMCL18U250D2_2.1/design_compiler/ } -snps = get_unix_variable("SYNOPSYS") -synthetic_library = { \ - snps + "/libraries/syn/dw01.sldb" \ - snps + "/libraries/syn/dw02.sldb" \ - snps + "/libraries/syn/dw03.sldb" \ - snps + "/libraries/syn/dw04.sldb" \ - snps + "/libraries/syn/dw05.sldb" \ - snps + "/libraries/syn/dw06.sldb" \ - snps + "/libraries/syn/dw07.sldb" } -target_library = { umcl18u250t2_typ.db } -link_library = target_library + synthetic_library -symbol_library = { umcl18u250t2.sdb } - Index: trunk/syn/bin/reports.inc =================================================================== --- trunk/syn/bin/reports.inc (revision 11) +++ trunk/syn/bin/reports.inc (nonexistent) @@ -1,10 +0,0 @@ -/* Basic reports */ -report_area > LOG_PATH + STAGE + _ + TOPLEVEL + _area.log -report_timing -nworst 10 > LOG_PATH + STAGE + _ + TOPLEVEL + _timing.log -report_hierarchy > LOG_PATH + STAGE + _ + TOPLEVEL + _hierarchy.log -report_resources > LOG_PATH + STAGE + _ + TOPLEVEL + _resources.log -report_constraint > LOG_PATH + STAGE + _ + TOPLEVEL + _constraint.log -/* -report_power > LOG_PATH + STAGE + _ + TOPLEVEL + _power.log -*/ - Index: trunk/syn/bin/select_tech.inc =================================================================== --- trunk/syn/bin/select_tech.inc (revision 11) +++ trunk/syn/bin/select_tech.inc (nonexistent) @@ -1,5 +0,0 @@ -/* Defaults */ - -TECH = vs_umc18 /* vs_umc18, art_umc18 */ -CLK_PERIOD = 5 /* 200 MHz */ -MAX_AREA = 0 /* Push hard */ Index: trunk/syn/bin/set_env.inc =================================================================== --- trunk/syn/bin/set_env.inc (revision 11) +++ trunk/syn/bin/set_env.inc (nonexistent) @@ -1,18 +0,0 @@ -/* Enable Verilog HDL preprocessor */ -hdlin_enable_vpp = true - -/* Set log path */ -LOG_PATH = "../log/" - -/* Set gate-level netlist path */ -GATE_PATH = "../out/" - -/* Set RAMS_PATH */ -RAMS_PATH = "../../../lib/" - -/* Set RTL source path */ -RTL_PATH = "../../rtl/verilog/" - -/* Optimize adders */ -synlib_model_map_effort = high -hlo_share_effort = medium Index: trunk/bench/verilog/timescale.v =================================================================== --- trunk/bench/verilog/timescale.v (revision 11) +++ trunk/bench/verilog/timescale.v (nonexistent) @@ -1 +0,0 @@ -`timescale 1ns/10ps Index: trunk/bench/verilog/tb_top.v =================================================================== --- trunk/bench/verilog/tb_top.v (revision 11) +++ trunk/bench/verilog/tb_top.v (nonexistent) @@ -1,152 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// PTC Testbench Top //// -//// //// -//// This file is part of the PTC project //// -//// http://www.opencores.org/cores/ptc/ //// -//// //// -//// Description //// -//// Top level of testbench. It instantiates all blocks. //// -//// //// -//// To Do: //// -//// Nothing //// -//// //// -//// Author(s): //// -//// - Damjan Lampret, lampret@opencores.org //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: not supported by cvs2svn $ -// Revision 1.2 2001/08/21 23:23:48 lampret -// Changed directory structure, defines and port names. -// -// Revision 1.1 2001/06/05 07:45:32 lampret -// Added initial RTL and test benches. There are still some issues with these files. -// -// - -`include "timescale.v" - -module tb_top; - -parameter aw = 32; -parameter dw = 32; - -// -// Interconnect wires -// -wire clk; // Clock -wire rst; // Reset -wire cyc; // Cycle valid -wire [aw-1:0] adr; // Address bus -wire [dw-1:0] dat_m; // Data bus from PTC to WBM -wire [3:0] sel; // Data selects -wire we; // Write enable -wire stb; // Strobe -wire [dw-1:0] dat_ptc;// Data bus from WBM to PTC -wire ack; // Successful cycle termination -wire err; // Failed cycle termination -wire ptc_ecgt;// External PTC clock/gate - -// -// Internal registers -// -reg ptc_capt;// Capture signal - -// -// Instantiation of Clock/Reset Generator -// -clkrst clkrst( - // Clock - .clk_o(clk), - // Reset - .rst_o(rst), - // External clock/gate - .ptc_ecgt(ptc_ecgt) -); - -// -// Instantiation of Master WISHBONE BFM -// -wb_master wb_master( - // WISHBONE Interface - .CLK_I(clk), - .RST_I(rst), - .CYC_O(cyc), - .ADR_O(adr), - .DAT_O(dat_ptc), - .SEL_O(sel), - .WE_O(we), - .STB_O(stb), - .DAT_I(dat_m), - .ACK_I(ack), - .ERR_I(err), - .RTY_I(0), - .TAG_I(4'b0) -); - -// -// Instantiation of PTC core -// -ptc_top ptc_top( - // WISHBONE Interface - .wb_clk_i(clk), - .wb_rst_i(rst), - .wb_cyc_i(cyc), - .wb_adr_i(adr[15:0]), - .wb_dat_i(dat_ptc), - .wb_sel_i(sel), - .wb_we_i(we), - .wb_stb_i(stb), - .wb_dat_o(dat_m), - .wb_ack_o(ack), - .wb_err_o(err), - .wb_inta_o(), - - // External PTC Interface - .gate_clk_pad_i(ptc_ecgt), - .capt_pad_i(ptc_capt), - .pwm_pad_o(), - .oen_padoen_o() -); - -initial ptc_capt = 0; - -// -// Task to set ptc_capt -// -task set_ptc_capt; -input bit; -begin - ptc_capt = bit; -end -endtask - -endmodule Index: trunk/bench/verilog/tb_tasks.v =================================================================== --- trunk/bench/verilog/tb_tasks.v (revision 11) +++ trunk/bench/verilog/tb_tasks.v (nonexistent) @@ -1,968 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// PTC Testbench Tasks //// -//// //// -//// This file is part of the PTC project //// -//// http://www.opencores.org/cores/ptc/ //// -//// //// -//// Description //// -//// Testbench tasks. //// -//// //// -//// To Do: //// -//// Nothing //// -//// //// -//// Author(s): //// -//// - Damjan Lampret, lampret@opencores.org //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: not supported by cvs2svn $ -// Revision 1.2 2001/08/21 23:23:48 lampret -// Changed directory structure, defines and port names. -// -// Revision 1.1 2001/06/05 07:45:32 lampret -// Added initial RTL and test benches. There are still some issues with these files. -// -// - -`include "timescale.v" -`include "ptc_defines.v" -`include "tb_defines.v" - -module tb_tasks; - -integer nr_failed; -integer ints_disabled; -integer ints_working; -integer capt_working; -integer monitor_ptc_pwm, pwm_l1, pwm_l2; - -// -// Count/report failed tests -// -task failed; -begin - $display("FAILED !!!"); - nr_failed = nr_failed + 1; -end -endtask - -// -// Set RPTC_CNTR register -// -task setcntr; -input [31:0] val; - -begin - #100 tb_top.wb_master.wr(`PTC_RPTC_CNTR<<2, val, 4'b1111); -end - -endtask - -// -// Set PTC_RPTC_HRC register -// -task sethrc; -input [31:0] val; - -begin - #100 tb_top.wb_master.wr(`PTC_RPTC_HRC<<2, val, 4'b1111); -end - -endtask - -// -// Set PTC_RPTC_LRC register -// -task setlrc; -input [31:0] val; - -begin - #100 tb_top.wb_master.wr(`PTC_RPTC_LRC<<2, val, 4'b1111); -end - -endtask - -// -// Set PTC_RPTC_CTRL register -// -task setctrl; -input [31:0] val; - -begin - #100 tb_top.wb_master.wr(`PTC_RPTC_CTRL<<2, val, 4'b1111); -end - -endtask - -// -// Display RPTC_CNTR register -// -task showcntr; - -reg [31:0] tmp; -begin - tb_top.wb_master.rd(`PTC_RPTC_CNTR<<2, tmp); - $write(" RPTC_CNTR: %h", tmp); -end - -endtask - -// -// Display RPTC_HRC register -// -task showhrc; - -reg [31:0] tmp; -begin - tb_top.wb_master.rd(`PTC_RPTC_HRC<<2, tmp); - $write(" RPTC_HRC: %h", tmp); -end - -endtask -// -// Display RPTC_LRC register -// -task showlrc; - -reg [31:0] tmp; -begin - tb_top.wb_master.rd(`PTC_RPTC_LRC<<2, tmp); - $write(" RPTC_LRC:%h", tmp); -end - -endtask -// -// Display RPTC_CTRL register -// -task showctrl; - -reg [31:0] tmp; -begin - tb_top.wb_master.rd(`PTC_RPTC_CTRL<<2, tmp); - $write(" RPTC_CTRL: %h", tmp); -end - -endtask - -// -// Compare parameter with PTC_RPTC_CNTR register -// -task comp_cntr; -input [31:0] val; -output ret; - -reg [31:0] tmp; -reg ret; -begin - tb_top.wb_master.rd(`PTC_RPTC_CNTR<<2, tmp); - - if (tmp == val) - ret = 1; - else - ret = 0; -end - -endtask - -// -// Compare parameter with PTC_RPTC_HRC register -// -task comp_hrc; -input [31:0] val; -output ret; - -reg [31:0] tmp; -reg ret; -begin - tb_top.wb_master.rd(`PTC_RPTC_HRC<<2, tmp); - - if (tmp == val) - ret = 1; - else - ret = 0; -end - -endtask - - -// -// Compare parameter with PTC_RPTC_LRC register -// -task comp_lrc; -input [31:0] val; -output ret; - -reg [31:0] tmp; -reg ret; -begin - tb_top.wb_master.rd(`PTC_RPTC_LRC<<2, tmp); - - if (tmp == val) - ret = 1; - else - ret = 0; -end - -endtask - -// -// Get PTC_RPTC_CNTR register -// -task getcntr; -output [31:0] tmp; - -begin - tb_top.wb_master.rd(`PTC_RPTC_CNTR<<2, tmp); -end - -endtask - -// -// Get PTC_RPTC_HRC register -// -task gethrc; -output [31:0] tmp; - -begin - tb_top.wb_master.rd(`PTC_RPTC_HRC<<2, tmp); -end - -endtask - -// -// Get PTC_RPTC_LRC register -// -task getlrc; -output [31:0] tmp; - -begin - tb_top.wb_master.rd(`PTC_RPTC_LRC<<2, tmp); -end - -endtask - -// -// Get PTC_RPTC_CTRL register -// -task getctrl; -output [31:0] tmp; - -begin - tb_top.wb_master.rd(`PTC_RPTC_CTRL<<2, tmp); -end - -endtask - -// -// Test operation of control bit PTC_RPTC_CTRL[ECLK] -// -task test_eclk; -integer l1, l2; -begin - $write(" Testing control bit RPTC_CTRL[ECLK] ..."); - - // - // Phase 1 - // - // PTC uses WISHBONE clock - // - - // Disable PTC, reset counter - setctrl(1 << `PTC_RPTC_CTRL_CNTRRST); - - // Set PTC_RPTC_HRC and PTC_RPTC_LRC to some high value - sethrc('hffffffff); - setlrc('hffffffff); - - // Enable PTC - setctrl(1 << `PTC_RPTC_CTRL_EN); - - // Wait for time to advance - #20000; - - // Get counter - getcntr(l1); - - // - // Phase 2 - // - // PTC uses external clock - // - - // Disable PTC, reset counter - setctrl(1 << `PTC_RPTC_CTRL_CNTRRST); - - // Enable PTC, use external clock - setctrl(1 << `PTC_RPTC_CTRL_EN | 1 << `PTC_RPTC_CTRL_ECLK); -`ifdef PTC_DEBUG - showctrl; - showcntr; -`endif - // Do 10000 external clock cyles - tb_top.clkrst.gen_ptc_ecgt(10000); - - // Get counter - getcntr(l2); - - // - // Phase 3 - // - // Compare counter from phase 1 and phase 2 - // - if (l2 - l1 == 7498) - $display(" OK"); - else - failed; -end -endtask - -// -// Test operation of control bit PTC_RPTC_CTRL[EN] -// -task test_en; -integer l1, l2; -begin - $write(" Testing control bit RPTC_CTRL[EN] ..."); - - // - // Phase 1 - // - // PTC does 1000 external clock cycles - // - - // Disable PTC, reset counter - setctrl(1 << `PTC_RPTC_CTRL_CNTRRST); - - // Enable PTC, use external clock - setctrl(1 << `PTC_RPTC_CTRL_EN | 1 << `PTC_RPTC_CTRL_ECLK); -`ifdef PTC_DEBUG - showctrl; - showcntr; -`endif - // Do 1000 external clock cycles - tb_top.clkrst.gen_ptc_ecgt(1000); - - // Get counter - getcntr(l1); - - // - // Phase 2 - // - // Disable PTC and run for another 1000 external clock cycles - // - - // Disable PTC, use external clock - setctrl(1 << `PTC_RPTC_CTRL_ECLK); -`ifdef PTC_DEBUG - showctrl; - showcntr; -`endif - // Do 1000 external clock cycles - tb_top.clkrst.gen_ptc_ecgt(1000); - - // Get counter - getcntr(l2); - - // - // Phase 3 - // - // Compare counter from phase 1 and phase 2. Should be the same. - // - if (l1 == l2 && l2 == 1000) - $display(" OK"); - else - failed; -end -endtask - -// -// Test operation of control bit PTC_RPTC_CTRL[NEC] -// -task test_nec; -integer l1, l2; -begin - $write(" Testing control bit RPTC_CTRL[NEC] ..."); - - // - // Phase 1 - // - // PTC does 1000 external clock cycles - // - - // Disable PTC, reset counter - setctrl(1 << `PTC_RPTC_CTRL_CNTRRST); - - // Enable PTC, use external clock - setctrl(1 << `PTC_RPTC_CTRL_EN | 1 << `PTC_RPTC_CTRL_ECLK); -`ifdef PTC_DEBUG - showctrl; - showcntr; -`endif - // Do 1000 external clock cycles - tb_top.clkrst.gen_ptc_ecgt(1000); - - // Get counter - getcntr(l1); - - // - // Phase 2 - // - // Enable PTC_RPTC_CTRL[NEC] and run for another 1000 external clock cycles - // - - // Enable PTC_RPTC_CTRL[NEC], use external clock - setctrl(1 << `PTC_RPTC_CTRL_EN | 1 << `PTC_RPTC_CTRL_ECLK | 1 << `PTC_RPTC_CTRL_NEC); -`ifdef PTC_DEBUG - showctrl; - showcntr; -`endif - // Do 1000 external clock cycles - tb_top.clkrst.gen_ptc_ecgt(1000); - - // Get counter - getcntr(l2); - - // - // Phase 3 - // - // Compare counter from phase 1 and phase 2. - // - if (l2 - l1 == 1001) - $display(" OK"); - else - failed; -end -endtask - -// -// Test operation of control bit PTC_RPTC_CTRL[CNTRRST] -// -task test_cntrrst; -integer l1, l2; -begin - $write(" Testing control bit RPTC_CTRL[CNTRRST] ..."); - - // - // Phase 1 - // - // Set counter and clear it - // - - // Disable PTC - setctrl(0); - - // Manually set counter - setcntr('d1234); -`ifdef PTC_DEBUG - showctrl; - showcntr; -`endif - - // Get counter - getcntr(l1); - - // Disable PTC, reset counter - setctrl(1 << `PTC_RPTC_CTRL_CNTRRST); - - // Get counter - getcntr(l2); - - // - // Phase 3 - // - // Counter l1 should be 1234 and counter l2 should be zero - // - if (l1 == 1234 && l2 == 0) - $display(" OK"); - else - failed; -end -endtask - -// -// Test operation of control bit PTC_RPTC_CTRL[OE] -// -task test_oe; -integer l1, l2; -begin - $write(" Testing control bit RPTC_CTRL[OE] ..."); - - // - // Phase 1 - // - // Clear PTC_RPTC_CTRL[OE] - // - - // Disable PTC, clear PTC_RPTC_CTRL[OE] - setctrl(0); - -`ifdef PTC_DEBUG - showctrl; -`endif - - // Get ptc_oen - l1 = tb_top.ptc_top.oen_padoen_o; - - // - // Phase 2 - // - // Set PTC_RPTC_CTRL[OE] - // - - // Disable PTC, set PTC_RPTC_CTRL[OE] - setctrl(1 << `PTC_RPTC_CTRL_OE); - -`ifdef PTC_DEBUG - showctrl; -`endif - - // Get ptc_oen - l2 = tb_top.ptc_top.oen_padoen_o; - - // - // Phase 3 - // - // l1 should be 1 and l2 should be zero - // - if (l1 && !l2) - $display(" OK"); - else - failed; -end -endtask - -// -// Test operation of control bit PTC_RPTC_CTRL[CAPTE] -// -task test_capte; -integer l1, l2; -begin - $write(" Testing control bit RPTC_CTRL[CAPTE] ..."); - - // - // Phase 1 - // - // Run counter off external clock and capture it into PTC_RPTC_HRC/LRC - // - - // Disable PTC, clear counter - setctrl(1 << `PTC_RPTC_CTRL_CNTRRST); - - // Set PTC_RPTC_HRC/LRC to some high value - sethrc('hffffffff); - setlrc('hffffffff); - - // Enable PTC, use external clock, enable PTC_RPTC_CTRL[CAPTE] - setctrl(1 << `PTC_RPTC_CTRL_EN | 1 << `PTC_RPTC_CTRL_ECLK | 1 << `PTC_RPTC_CTRL_CAPTE); - -`ifdef PTC_DEBUG - showctrl; -`endif - - // Do 1000 external clock cycles - tb_top.clkrst.gen_ptc_ecgt(1000); - - // Do posedge ptc_capt - tb_top.set_ptc_capt(1); - - // Get PTC_RPTC_HRC - gethrc(l1); - - // Do additional 1000 external clock cycles - tb_top.clkrst.gen_ptc_ecgt(1000); - - // Do posedge ptc_capt - tb_top.set_ptc_capt(0); - - // Get PTC_RPTC_LRC - getlrc(l2); - - // - // Phase 3 - // - // l1 should be 1000 and l2 should be 2000 - // - if (l1 == 1000 && l2 == 2000) begin - $display(" OK"); - capt_working = 1; - end else - failed; -end -endtask - -// -// Test operation of control bit PTC_RPTC_CTRL[SINGLE] -// -task test_single; -integer l1, l2; -begin - $write(" Testing control bit RPTC_CTRL[SINGLE] ..."); - - // - // Phase 1 - // - // Run counter off external clock with cleared PTC_RPTC_CTRL[SINGLE]. - // Counter should roll over when it reaches PTC_RPTC_LRC value. - // - - // Disable PTC, clear counter - setctrl(1 << `PTC_RPTC_CTRL_CNTRRST); - - // Set PTC_RPTC_HRC to some high value and PTC_RPTC_LRC to 1000 - sethrc('hffffffff); - setlrc('d1000); - - // Enable PTC, use external clock - setctrl(1 << `PTC_RPTC_CTRL_EN | 1 << `PTC_RPTC_CTRL_ECLK); -`ifdef PTC_DEBUG - showctrl; -`endif - - // Do 1501 external clock cycles - tb_top.clkrst.gen_ptc_ecgt(1501); - - // Get counter - getcntr(l1); - - // - // Phase 2 - // - // Run counter off external clock with PTC_RPTC_CTRL[SINGLE] set. - // Counter should stop when it reaches PTC_RPTC_LRC value. - // - - // Disable PTC, clear counter - setctrl(1 << `PTC_RPTC_CTRL_CNTRRST); - - // Set PTC_RPTC_HRC to some high value and PTC_RPTC_LRC to 1000 - sethrc('hffffffff); - setlrc('d1000); - - // Enable PTC, use external clock, set PTC_RPTC_CTRL[SINGLE] - setctrl(1 << `PTC_RPTC_CTRL_EN | 1 << `PTC_RPTC_CTRL_ECLK | 1 << `PTC_RPTC_CTRL_SINGLE); -`ifdef PTC_DEBUG - showctrl; -`endif - - // Do 1500 external clock cycles - tb_top.clkrst.gen_ptc_ecgt(1500); - - // Get counter - getcntr(l2); - - - // - // Phase 3 - // - // l1 should be 500 and l2 should be 1000 - // - if (l1 == 500 && l2 == 1000) - $display(" OK"); - else - failed; -end -endtask - -// -// Test operation of control bit PTC_RPTC_CTRL[INTE] and PTC_RPTC_CTRL[INT] -// -task test_ints; -integer l1, l2, l3; -begin - $write(" Testing control bit RPTC_CTRL[INTE] and PTC_RPTC_CTRL[INT]..."); - - // - // Phase 1 - // - // Run counter off external clock. - // Counter should generate an interrupt when it reaches PTC_RPTC_LRC value. - // - - // Disable PTC, clear counter - setctrl(1 << `PTC_RPTC_CTRL_CNTRRST); - - // Set PTC_RPTC_HRC to some high value and PTC_RPTC_LRC to 1000 - sethrc('hffffffff); - setlrc('d1000); - - // Disable detection of spurious interrupts - ints_disabled = 0; - - // Enable PTC, use external clock, set PTC_RPTC_CTRL[INTE] - setctrl(1 << `PTC_RPTC_CTRL_EN | 1 << `PTC_RPTC_CTRL_ECLK | 1 << `PTC_RPTC_CTRL_INTE); -`ifdef PTC_DEBUG - showctrl; -`endif - // Do 999 external clock cycles - tb_top.clkrst.gen_ptc_ecgt(999); - - // Sample interrupt request. It should be zero. - l1 = tb_top.ptc_top.wb_inta_o; - - // Do 4 additional external clock cycles - tb_top.clkrst.gen_ptc_ecgt(4); - - // Sample interrupt request. It should be one. - l2 = tb_top.ptc_top.wb_inta_o; - - // - // Phase 2 - // - // Mask interrupt. - // - - // Enable detection of spurious interrupts - ints_disabled = 1; - - // Mask interrupt - setctrl(1 << `PTC_RPTC_CTRL_EN | 1 << `PTC_RPTC_CTRL_ECLK); - - // Sample interrupt request. It should be again zero. - l3 = tb_top.ptc_top.wb_inta_o; - - // - // Phase 3 - // - // l1 should be zero, l2 should be one and l3 should be zero - // - if (!l1 && l2 && !l3) begin - $display(" OK"); - ints_working = ints_working + 1; - end else - failed; -end -endtask - -always @(posedge tb_top.ptc_top.gate_clk_pad_i) - if (monitor_ptc_pwm && !tb_top.ptc_top.pwm_pad_o) - pwm_l1 = pwm_l1 + 1; - -always @(posedge tb_top.ptc_top.gate_clk_pad_i) - if (monitor_ptc_pwm && tb_top.ptc_top.pwm_pad_o) - pwm_l2 = pwm_l2 + 1; - -// -// Test PWM mode -// -task test_pwm; -begin - $write(" Testing PWM mode ..."); - - // - // Phase 1 - // - // Run counter off external clock with PWM low for 10 clocks and - // PWM high for 20 clocks - // - - // Disable PTC, clear counter - setctrl(1 << `PTC_RPTC_CTRL_CNTRRST); - - // Set intervals 10 and 20 - // HRC must be set with number one less than low period - // because it takes one clock cycle to reset the counter - sethrc('d9); - setlrc('d29); - - // Enable PTC, use external clock - setctrl(1 << `PTC_RPTC_CTRL_EN | 1 << `PTC_RPTC_CTRL_ECLK); -`ifdef PTC_DEBUG - showctrl; -`endif - // Start monitoring ptc_pwm - monitor_ptc_pwm = 1; - - // Do 3000 external clock cycles - tb_top.clkrst.gen_ptc_ecgt(3000); - - // Stop monitoring ptc_pwm - monitor_ptc_pwm = 0; - - // - // Phase 2 - // - // l1 should be 1000 and l2 should be 2000 - // - if (pwm_l1 == 1000 && pwm_l2 == 2000) - $display(" OK"); - else - failed; -end -endtask - -// -// Test gate feature -// -task test_gate; -integer l1, l2, l3; -begin - $write(" Testing gate feature ..."); - - // - // Phase 1 - // - // Run counter off WB clock and in the middle assert gating - // - - // Disable PTC, clear counter - setctrl(1 << `PTC_RPTC_CTRL_CNTRRST); - - // Set PTC_RPTC_HRC/LRC to some high value - sethrc('hffffffff); - setlrc('hffffffff); - - // Enable PTC - setctrl(1 << `PTC_RPTC_CTRL_EN); -`ifdef PTC_DEBUG - showctrl; -`endif - - // Increment counter - #5000; - - // Get counter - getcntr(l1); - - // Increment counter - #5000; - - // Assert gate - tb_top.clkrst.gen_ptc_ecgt(-1); - - // Get counter - getcntr(l2); - - // Increment counter - #5000; - - // Get counter (should be the same as l2) - getcntr(l3); - - // - // Phase 2 - // - // l1 should be nonzero and l2 and l3 should be the same - // - if (l1 && l1 < l2 && l2 == l3) - $display(" OK"); - else - failed; -end -endtask - -// -// Test operation of control bit PTC_RPTC_CTRL[INTE] and PTC_RPTC_CTRL[INT] -// -task test_modes; -integer l1, l2, l3; -begin - - // Test PWM mode - test_pwm; - - $write(" Testing timer/counter mode ..."); - if (nr_failed == 0) - $display(" OK"); - else - failed; - - // Test gate feature - test_gate; - - $write(" Testing interrupt feature ..."); - if (ints_working == 1) - $display(" OK"); - else - failed; - - $write(" Testing capture feature ..."); - if (capt_working == 1) - $display(" OK"); - else - failed; - -end -endtask - -// -// Do continues check for interrupts -// -always @(posedge tb_top.ptc_top.wb_inta_o) - if (ints_disabled) begin - $display("Spurious interrupt detected. "); - failed; - ints_working = 9876; - $display; - end - -// -// Start of testbench test tasks -// -initial begin -`ifdef PTC_DUMP_VCD - $dumpfile("../out/tb_top.vcd"); - $dumpvars(0); -`endif - nr_failed = 0; - ints_disabled = 1; - ints_working = 0; - capt_working = 0; - monitor_ptc_pwm = 0; - pwm_l1 = 0; - pwm_l2 = 0; - $display; - $display("###"); - $display("### PTC IP Core Verification ###"); - $display("###"); - $display; - $display("I. Testing correct operation of RPTC_CTRL control bits"); - $display; - test_eclk; - test_oe; - test_cntrrst; - test_en; - test_nec; - test_capte; - test_single; - test_ints; - $display; - $display("II. Testing modes of operation ..."); - $display; - test_modes; - $display; - $display("###"); - $display("### FAILED TESTS: %d ###", nr_failed); - $display("###"); - $display; - $finish; -end - -endmodule Index: trunk/bench/verilog/clkrst.v =================================================================== --- trunk/bench/verilog/clkrst.v (revision 11) +++ trunk/bench/verilog/clkrst.v (nonexistent) @@ -1,101 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Clock and Reset Generator //// -//// //// -//// This file is part of the PTC project //// -//// http://www.opencores.org/cores/ptc/ //// -//// //// -//// Description //// -//// Clock and reset generator. //// -//// //// -//// To Do: //// -//// Nothing //// -//// //// -//// Author(s): //// -//// - Damjan Lampret, lampret@opencores.org //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: not supported by cvs2svn $ -// Revision 1.1 2001/06/05 07:45:32 lampret -// Added initial RTL and test benches. There are still some issues with these files. -// -// - -`include "timescale.v" - -module clkrst(clk_o, rst_o, ptc_ecgt); - -// -// I/O ports -// -output clk_o; // Clock -output rst_o; // Reset -output ptc_ecgt; // (External) PTC clock/gate - -// -// Internal regs -// -reg clk_o; // Clock -reg rst_o; // Reset -reg ptc_ecgt; // PTC clock/gate - -initial begin - clk_o = 0; - rst_o = 1; - ptc_ecgt = 0; - #20; - rst_o = 0; -end - -// -// Clock -// -always #4 clk_o = ~clk_o; - -// -// PTC clock/gate generator -// -task gen_ptc_ecgt; -input [31:0] cycles; -integer i; -begin - if (cycles == -1) - ptc_ecgt = 1; - else - for (i = 2 * cycles; i; i = i - 1) begin - #4 ptc_ecgt = ~ptc_ecgt; - if (i % 20000 == 19999) - $write("."); - end -end -endtask - -endmodule Index: trunk/bench/verilog/tb_defines.v =================================================================== --- trunk/bench/verilog/tb_defines.v (revision 11) +++ trunk/bench/verilog/tb_defines.v (nonexistent) @@ -1,61 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// PTC Testbench Definitions //// -//// //// -//// This file is part of the PTC project //// -//// http://www.opencores.org/cores/ptc/ //// -//// //// -//// Description //// -//// Testbench definitions that affect how testbench simulation //// -//// is performed. //// -//// //// -//// To Do: //// -//// Nothing //// -//// //// -//// Author(s): //// -//// - Damjan Lampret, lampret@opencores.org //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: not supported by cvs2svn $ -// Revision 1.1 2001/06/05 07:45:32 lampret -// Added initial RTL and test benches. There are still some issues with these files. -// -// - -// -// Run test bench with debug output -// -//`define DEBUG - -// -// Dump VCD -// -`define PTC_DUMP_VCD Index: trunk/bench/verilog/wb_master.v =================================================================== --- trunk/bench/verilog/wb_master.v (revision 11) +++ trunk/bench/verilog/wb_master.v (nonexistent) @@ -1,306 +0,0 @@ -`include "timescale.v" - -// -*- Mode: Verilog -*- -// Filename : wb_master.v -// Description : Wishbone Master Behavorial -// Author : Winefred Washington -// Created On : Thu Jan 11 21:18:41 2001 -// Last Modified By: . -// Last Modified On: . -// Update Count : 0 -// Status : Unknown, Use with caution! - -// Description Specification -// General Description: 8, 16, 32-bit WISHBONE Master -// Supported cycles: MASTER, READ/WRITE -// MASTER, BLOCK READ/WRITE -// MASTER, RMW -// Data port, size: 8, 16, 32-bit -// Data port, granularity 8-bit -// Data port, Max. operand size 32-bit -// Data transfer ordering: little endian -// Data transfer sequencing: undefined -// - -module wb_master(CLK_I, RST_I, TAG_I, TAG_O, - ACK_I, ADR_O, CYC_O, DAT_I, DAT_O, ERR_I, RTY_I, SEL_O, STB_O, WE_O); - - input CLK_I; - input RST_I; - input [3:0] TAG_I; - output [3:0] TAG_O; - input ACK_I; - output [31:0] ADR_O; - output CYC_O; - input [31:0] DAT_I; - output [31:0] DAT_O; - input ERR_I; - input RTY_I; - output [3:0] SEL_O; - output STB_O; - output WE_O; - - reg [31:0] ADR_O; - reg [3:0] SEL_O; - reg CYC_O; - reg STB_O; - reg WE_O; - reg [31:0] DAT_O; - - wire [15:0] mem_sizes; // determines the data width of an address range - reg [31:0] write_burst_buffer[0:7]; - reg [31:0] read_burst_buffer[0:7]; - - reg GO; - integer cycle_end; - integer address; - integer data; - integer selects; - integer write_flag; - - // - // mem_sizes determines the data widths of memory space - // The memory space is divided into eight regions. Each - // region is controlled by a two bit field. - // - // Bits - // 00 = 8 bit memory space - // 01 = 16 bit - // 10 = 32 bit - // 11 = 64 bit (not supported in this model - // - - assign mem_sizes = 16'b10_01_10_11_00_01_10_11; - - function [1:0] data_width; - input [31:0] adr; - begin - casex (adr[31:29]) - 3'b000: data_width = mem_sizes[15:14]; - 3'b001: data_width = mem_sizes[13:12]; - 3'b010: data_width = mem_sizes[11:10]; - 3'b011: data_width = mem_sizes[9:8]; - 3'b100: data_width = mem_sizes[7:6]; - 3'b101: data_width = mem_sizes[5:4]; - 3'b110: data_width = mem_sizes[3:2]; - 3'b111: data_width = mem_sizes[1:0]; - 3'bxxx: data_width = 2'bxx; - endcase // casex (adr[31:29]) - end - endfunction - - always @(posedge CLK_I or posedge RST_I) - begin - if (RST_I) - begin - GO = 1'b0; - end - end - - // read single - task rd; - input [31:0] adr; - output [31:0] result; - - begin - cycle_end = 1; - address = adr; - selects = 255; - write_flag = 0; - - GO <= 1; - @(posedge CLK_I); -// GO <= 0; - - // wait for cycle to start - while (~CYC_O) - @(posedge CLK_I); - - // wait for cycle to end - while (CYC_O) - @(posedge CLK_I); - - result = data; -// $display(" Reading %h from address %h", result, address); - - end - endtask // read - - task wr; - input [31:0] adr; - input [31:0] dat; - input [3:0] sel; - begin - cycle_end = 1; - address = adr; - selects = sel; - write_flag = 1; - data = dat; - - GO <= 1; - @(posedge CLK_I); -// GO <= 0; - - // wait for cycle to start - while (~CYC_O) - @(posedge CLK_I); - - // wait for cycle to end - while (CYC_O) - @(posedge CLK_I); -// $display(" Writing %h to address %h", data, address); - - end - endtask // wr - - // block read - task blkrd; - input [31:0] adr; - input end_flag; - output [31:0] result; - - begin - write_flag = 0; - cycle_end = end_flag; - address = adr; - GO <= 1; - @(posedge CLK_I); -// GO <= 0; - - while (~(ACK_I & STB_O)) - @(posedge CLK_I); - - result = data; - end - endtask // blkrd - - // block write - task blkwr; - input [31:0] adr; - input [31:0] dat; - input [3:0] sel; - input end_flag; - begin - write_flag = 1; - cycle_end = end_flag; - address = adr; - data = dat; - selects = sel; - GO <= 1; - @(posedge CLK_I); -// GO <= 0; - - while (~(ACK_I & STB_O)) - @(posedge CLK_I); - - end - endtask // blkwr - - // RMW - task rmw; - input [31:0] adr; - input [31:0] dat; - input [3:0] sel; - output [31:0] result; - - begin - // read phase - write_flag = 0; - cycle_end = 0; - address = adr; - GO <= 1; - @(posedge CLK_I); -// GO <= 0; - - while (~(ACK_I & STB_O)) - @(posedge CLK_I); - - result = data; - - // write phase - write_flag = 1; - address = adr; - selects = sel; - GO <= 1; - data <= dat; - cycle_end <= 1; - @(posedge CLK_I); -// GO <= 0; - - while (~(ACK_I & STB_O)) - @(posedge CLK_I); - - end - endtask // rmw - - always @(posedge CLK_I) - begin - if (RST_I) - ADR_O <= 32'h0000_0000; - else - ADR_O <= address; - end - - always @(posedge CLK_I) - begin - if (RST_I | ERR_I | RTY_I) - CYC_O <= 1'b0; - else if ((cycle_end == 1) & ACK_I) - CYC_O <= 1'b0; - else if (GO | CYC_O) begin - CYC_O <= 1'b1; - GO <= 1'b0; - end - end - - // stb control - always @(posedge CLK_I) - begin - if (RST_I | ERR_I | RTY_I) - STB_O <= 1'b0; - else if (STB_O & ACK_I) - STB_O <= 1'b0; - else if (GO | STB_O) - STB_O <= 1'b1; - end - - // selects & data - always @(posedge CLK_I) - begin - if (write_flag == 0) begin - SEL_O <= 4'b1111; - if (STB_O & ACK_I) - data <= DAT_I; - end - else begin - case (data_width(address)) - 2'b00: begin - SEL_O <= {3'b000, selects[0]}; - DAT_O <= {data[7:0], data[7:0], data[7:0], data[7:0]}; - end - 2'b01: begin - SEL_O <= {2'b00, selects[1:0]}; - DAT_O <= {data[15:0], data[15:0]}; - end - 2'b10: begin - SEL_O <= selects; - DAT_O <= data; - end - endcase - end - end - - always @(posedge CLK_I) - begin - if (RST_I) - WE_O <= 1'b0; - else if (GO) - WE_O <= write_flag; - end - -endmodule - - - - - Index: trunk/rtl/verilog/ptc_defines.v =================================================================== --- trunk/rtl/verilog/ptc_defines.v (revision 11) +++ trunk/rtl/verilog/ptc_defines.v (nonexistent) @@ -1,163 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// WISHBONE PWM/Timer/Counter Definitions //// -//// //// -//// This file is part of the PTC project //// -//// http://www.opencores.org/cores/ptc/ //// -//// //// -//// Description //// -//// PTC definitions. //// -//// //// -//// To Do: //// -//// Nothing //// -//// //// -//// Author(s): //// -//// - Damjan Lampret, lampret@opencores.org //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: not supported by cvs2svn $ -// Revision 1.2 2001/08/21 23:23:50 lampret -// Changed directory structure, defines and port names. -// -// Revision 1.2 2001/07/17 00:18:08 lampret -// Added new parameters however RTL still has some issues related to hrc_match and int_match -// -// Revision 1.1 2001/06/05 07:45:36 lampret -// Added initial RTL and test benches. There are still some issues with these files. -// -// - -// -// Width of the PTC counter -// -// -`define PTC_CW 32 - -// -// Undefine this one if you don't want to remove PTC block from your design -// but you also don't need it. When it is undefined, all PTC ports still -// remain valid and the core can be synthesized however internally there is -// no PTC funationality. -// -// Defined by default (duhh !). -// -`define PTC_IMPLEMENTED - -// -// Undefine if you don't need to read PTC registers. -// When it is undefined all reads of PTC registers return zero. This -// is usually useful if you want really small area (for example when -// implemented in FPGA). -// -// To follow PTC IP core specification document this one must be defined. -// Also to successfully run the test bench it must be defined. By default -// it is defined. -// -`define PTC_READREGS - -// -// Full WISHBONE address decoding -// -// It is is undefined, partial WISHBONE address decoding is performed. -// Undefine it if you need to save some area. -// -// By default it is defined. -// -`define PTC_FULL_DECODE - -// -// Strict 32-bit WISHBONE access -// -// If this one is defined, all WISHBONE accesses must be 32-bit. If it is -// not defined, err_o is asserted whenever 8- or 16-bit access is made. -// Undefine it if you need to save some area. -// -// By default it is defined. -// -`define PTC_STRICT_32BIT_ACCESS - -// -// WISHBONE address bits used for full decoding of PTC registers. -// -`define PTC_ADDRHH 15 -`define PTC_ADDRHL 5 -`define PTC_ADDRLH 1 -`define PTC_ADDRLL 0 - -// -// Bits of WISHBONE address used for partial decoding of PTC registers. -// -// Default 4:2. -// -`define PTC_OFS_BITS `PTC_ADDRHL-1:`PTC_ADDRLH+1 - -// -// Addresses of PTC registers -// -// To comply with PTC IP core specification document they must go from -// address 0 to address 0xC in the following order: RPTC_CNTR, RPTC_HRC, -// RPTC_LRC and RPTC_CTRL -// -// If particular alarm/ctrl register is not needed, it's address definition -// can be omitted and the register will not be implemented. Instead a fixed -// default value will -// be used. -// -`define PTC_RPTC_CNTR 2'h0 // Address 0x0 -`define PTC_RPTC_HRC 2'h1 // Address 0x4 -`define PTC_RPTC_LRC 2'h2 // Address 0x8 -`define PTC_RPTC_CTRL 2'h3 // Address 0xc - -// -// Default values for unimplemented PTC registers -// -`define PTC_DEF_RPTC_CNTR `PTC_CW'b0 -`define PTC_DEF_RPTC_HRC `PTC_CW'b0 -`define PTC_DEF_RPTC_LRC `PTC_CW'b0 -`define PTC_DEF_RPTC_CTRL 9'h01 // RPTC_CTRL[EN] = 1 - -// -// RPTC_CTRL bits -// -// To comply with the PTC IP core specification document they must go from -// bit 0 to bit 8 in the following order: EN, ECLK, NEC, OE, SINGLE, INTE, -// INT, CNTRRST, CAPTE -// -`define PTC_RPTC_CTRL_EN 0 -`define PTC_RPTC_CTRL_ECLK 1 -`define PTC_RPTC_CTRL_NEC 2 -`define PTC_RPTC_CTRL_OE 3 -`define PTC_RPTC_CTRL_SINGLE 4 -`define PTC_RPTC_CTRL_INTE 5 -`define PTC_RPTC_CTRL_INT 6 -`define PTC_RPTC_CTRL_CNTRRST 7 -`define PTC_RPTC_CTRL_CAPTE 8 - Index: trunk/rtl/verilog/ptc_top.v =================================================================== --- trunk/rtl/verilog/ptc_top.v (revision 11) +++ trunk/rtl/verilog/ptc_top.v (nonexistent) @@ -1,394 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// WISHBONE PWM/Timer/Counter //// -//// //// -//// This file is part of the PTC project //// -//// http://www.opencores.org/cores/ptc/ //// -//// //// -//// Description //// -//// Implementation of PWM/Timer/Counter IP core according to //// -//// PTC IP core specification document. //// -//// //// -//// To Do: //// -//// Nothing //// -//// //// -//// Author(s): //// -//// - Damjan Lampret, lampret@opencores.org //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: not supported by cvs2svn $ -// Revision 1.4 2001/09/18 18:48:29 lampret -// Changed top level ptc into ptc_top. Changed defines.v into ptc_defines.v. Reset of the counter is now synchronous. -// -// Revision 1.3 2001/08/21 23:23:50 lampret -// Changed directory structure, defines and port names. -// -// Revision 1.2 2001/07/17 00:18:10 lampret -// Added new parameters however RTL still has some issues related to hrc_match and int_match -// -// Revision 1.1 2001/06/05 07:45:36 lampret -// Added initial RTL and test benches. There are still some issues with these files. -// -// - -// synopsys translate_off -`include "timescale.v" -// synopsys translate_on -`include "ptc_defines.v" - -module ptc_top( - // WISHBONE Interface - wb_clk_i, wb_rst_i, wb_cyc_i, wb_adr_i, wb_dat_i, wb_sel_i, wb_we_i, wb_stb_i, - wb_dat_o, wb_ack_o, wb_err_o, wb_inta_o, - - // External PTC Interface - gate_clk_pad_i, capt_pad_i, pwm_pad_o, oen_padoen_o -); - -parameter dw = 32; -parameter aw = `PTC_ADDRHH+1; -parameter cw = `PTC_CW; - -// -// WISHBONE Interface -// -input wb_clk_i; // Clock -input wb_rst_i; // Reset -input wb_cyc_i; // cycle valid input -input [aw-1:0] wb_adr_i; // address bus inputs -input [dw-1:0] wb_dat_i; // input data bus -input [3:0] wb_sel_i; // byte select inputs -input wb_we_i; // indicates write transfer -input wb_stb_i; // strobe input -output [dw-1:0] wb_dat_o; // output data bus -output wb_ack_o; // normal termination -output wb_err_o; // termination w/ error -output wb_inta_o; // Interrupt request output - -// -// External PTC Interface -// -input gate_clk_pad_i; // EClk/Gate input -input capt_pad_i; // Capture input -output pwm_pad_o; // PWM output -output oen_padoen_o; // PWM output driver enable - -`ifdef PTC_IMPLEMENTED - -// -// PTC Main Counter Register (or no register) -// -`ifdef PTC_RPTC_CNTR -reg [cw-1:0] rptc_cntr; // RPTC_CNTR register -`else -wire [cw-1:0] rptc_cntr; // No RPTC_CNTR register -`endif - -// -// PTC HI Reference/Capture Register (or no register) -// -`ifdef PTC_RPTC_HRC -reg [cw-1:0] rptc_hrc; // RPTC_HRC register -`else -wire [cw-1:0] rptc_hrc; // No RPTC_HRC register -`endif - -// -// PTC LO Reference/Capture Register (or no register) -// -`ifdef PTC_RPTC_LRC -reg [cw-1:0] rptc_lrc; // RPTC_LRC register -`else -wire [cw-1:0] rptc_lrc; // No RPTC_LRC register -`endif - -// -// PTC Control Register (or no register) -// -`ifdef PTC_RPTC_CTRL -reg [8:0] rptc_ctrl; // RPTC_CTRL register -`else -wire [8:0] rptc_ctrl; // No RPTC_CTRL register -`endif - -// -// Internal wires & regs -// -wire rptc_cntr_sel; // RPTC_CNTR select -wire rptc_hrc_sel; // RPTC_HRC select -wire rptc_lrc_sel; // RPTC_LRC select -wire rptc_ctrl_sel; // RPTC_CTRL select -wire hrc_match; // RPTC_HRC matches RPTC_CNTR -wire lrc_match; // RPTC_LRC matches RPTC_CNTR -wire restart; // Restart counter when asserted -wire stop; // Stop counter when asserted -wire cntr_clk; // Counter clock -wire cntr_rst; // Counter reset -wire hrc_clk; // RPTC_HRC clock -wire lrc_clk; // RPTC_LRC clock -wire eclk_gate; // ptc_ecgt xored by RPTC_CTRL[NEC] -wire gate; // Gate function of ptc_ecgt -wire pwm_rst; // Reset of a PWM output -reg [dw-1:0] wb_dat_o; // Data out -reg pwm_pad_o; // PWM output -reg int; // Interrupt reg -wire int_match; // Interrupt match -wire full_decoding; // Full address decoding qualification - -// -// All WISHBONE transfer terminations are successful except when: -// a) full address decoding is enabled and address doesn't match -// any of the PTC registers -// b) sel_i evaluation is enabled and one of the sel_i inputs is zero -// -assign wb_ack_o = wb_cyc_i & wb_stb_i & !wb_err_o; -`ifdef PTC_FULL_DECODE -`ifdef PTC_STRICT_32BIT_ACCESS -assign wb_err_o = wb_cyc_i & wb_stb_i & (!full_decoding | (wb_sel_i != 4'b1111)); -`else -assign wb_err_o = wb_cyc_i & wb_stb_i & !full_decoding; -`endif -`else -`ifdef PTC_STRICT_32BIT_ACCESS -assign wb_err_o = wb_cyc_i & wb_stb_i & (wb_sel_i != 4'b1111); -`else -assign wb_err_o = 1'b0; -`endif -`endif - -// -// Counter clock is selected by RPTC_CTRL[ECLK]. When it is set, -// external clock is used. -// -assign cntr_clk = rptc_ctrl[`PTC_RPTC_CTRL_ECLK] ? eclk_gate : wb_clk_i; - -// -// Counter reset -// -assign cntr_rst = wb_rst_i; - -// -// HRC clock is selected by RPTC_CTRL[CAPTE]. When it is set, -// ptc_capt is used as a clock. -// -assign hrc_clk = rptc_ctrl[`PTC_RPTC_CTRL_CAPTE] ? capt_pad_i : wb_clk_i; - -// -// LRC clock is selected by RPTC_CTRL[CAPTE]. When it is set, -// inverted ptc_capt is used as a clock. -// -assign lrc_clk = rptc_ctrl[`PTC_RPTC_CTRL_CAPTE] ? ~capt_pad_i : wb_clk_i; - -// -// PWM output driver enable is inverted RPTC_CTRL[OE] -// -assign oen_padoen_o = ~rptc_ctrl[`PTC_RPTC_CTRL_OE]; - -// -// Use RPTC_CTRL[NEC] -// -assign eclk_gate = gate_clk_pad_i ^ rptc_ctrl[`PTC_RPTC_CTRL_NEC]; - -// -// Gate function is active when RPTC_CTRL[ECLK] is cleared -// -assign gate = eclk_gate & ~rptc_ctrl[`PTC_RPTC_CTRL_ECLK]; - -// -// Full address decoder -// -`ifdef PTC_FULL_DECODE -assign full_decoding = (wb_adr_i[`PTC_ADDRHH:`PTC_ADDRHL] == {`PTC_ADDRHH-`PTC_ADDRHL+1{1'b0}}) & - (wb_adr_i[`PTC_ADDRLH:`PTC_ADDRLL] == {`PTC_ADDRLH-`PTC_ADDRLL+1{1'b0}}); -`else -assign full_decoding = 1'b1; -`endif - -// -// PTC registers address decoder -// -assign rptc_cntr_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`PTC_OFS_BITS] == `PTC_RPTC_CNTR) & full_decoding; -assign rptc_hrc_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`PTC_OFS_BITS] == `PTC_RPTC_HRC) & full_decoding; -assign rptc_lrc_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`PTC_OFS_BITS] == `PTC_RPTC_LRC) & full_decoding; -assign rptc_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`PTC_OFS_BITS] == `PTC_RPTC_CTRL) & full_decoding; - -// -// Write to RPTC_CTRL or update of RPTC_CTRL[INT] bit -// -`ifdef PTC_RPTC_CTRL -always @(posedge wb_clk_i or posedge wb_rst_i) - if (wb_rst_i) - rptc_ctrl <= #1 9'b0; - else if (rptc_ctrl_sel && wb_we_i) - rptc_ctrl <= #1 wb_dat_i[8:0]; - else if (rptc_ctrl[`PTC_RPTC_CTRL_INTE]) - rptc_ctrl[`PTC_RPTC_CTRL_INT] <= #1 rptc_ctrl[`PTC_RPTC_CTRL_INT] | int; -`else -assign rptc_ctrl = `PTC_DEF_RPTC_CTRL; -`endif - -// -// Write to RPTC_HRC -// -`ifdef PTC_RPTC_HRC -always @(posedge hrc_clk or posedge wb_rst_i) - if (wb_rst_i) - rptc_hrc <= #1 {cw{1'b0}}; - else if (rptc_hrc_sel && wb_we_i) - rptc_hrc <= #1 wb_dat_i[cw-1:0]; - else if (rptc_ctrl[`PTC_RPTC_CTRL_CAPTE]) - rptc_hrc <= #1 rptc_cntr; -`else -assign rptc_hrc = `DEF_RPTC_HRC; -`endif - -// -// Write to RPTC_LRC -// -`ifdef PTC_RPTC_LRC -always @(posedge lrc_clk or posedge wb_rst_i) - if (wb_rst_i) - rptc_lrc <= #1 {cw{1'b0}}; - else if (rptc_lrc_sel && wb_we_i) - rptc_lrc <= #1 wb_dat_i[cw-1:0]; - else if (rptc_ctrl[`PTC_RPTC_CTRL_CAPTE]) - rptc_lrc <= #1 rptc_cntr; -`else -assign rptc_lrc = `DEF_RPTC_LRC; -`endif - -// -// Write to or increment of RPTC_CNTR -// -`ifdef PTC_RPTC_CNTR -always @(posedge cntr_clk or posedge cntr_rst) - if (cntr_rst) - rptc_cntr <= #1 {cw{1'b0}}; - else if (rptc_cntr_sel && wb_we_i) - rptc_cntr <= #1 wb_dat_i[cw-1:0]; - else if (restart) - rptc_cntr <= #1 {cw{1'b0}}; - else if (!stop && rptc_ctrl[`PTC_RPTC_CTRL_EN] && !gate) - rptc_cntr <= #1 rptc_cntr + 1; -`else -assign rptc_cntr = `DEF_RPTC_CNTR; -`endif - -// -// Read PTC registers -// -always @(wb_adr_i or rptc_hrc or rptc_lrc or rptc_ctrl or rptc_cntr) - case (wb_adr_i[`PTC_OFS_BITS]) // synopsys full_case parallel_case -`ifdef PTC_READREGS - `PTC_RPTC_HRC: wb_dat_o[dw-1:0] = {{dw-cw{1'b0}}, rptc_hrc}; - `PTC_RPTC_LRC: wb_dat_o[dw-1:0] = {{dw-cw{1'b0}}, rptc_lrc}; - `PTC_RPTC_CTRL: wb_dat_o[dw-1:0] = {{dw-9{1'b0}}, rptc_ctrl}; -`endif - default: wb_dat_o[dw-1:0] = {{dw-cw{1'b0}}, rptc_cntr}; - endcase - -// -// A match when RPTC_HRC is equal to RPTC_CNTR -// -assign hrc_match = rptc_ctrl[`PTC_RPTC_CTRL_EN] & (rptc_cntr == rptc_hrc); - -// -// A match when RPTC_LRC is equal to RPTC_CNTR -// -assign lrc_match = rptc_ctrl[`PTC_RPTC_CTRL_EN] & (rptc_cntr == rptc_lrc); - -// -// Restart counter when lrc_match asserted and RPTC_CTRL[SINGLE] cleared -// or when RPTC_CTRL[CNTRRST] is set -// -assign restart = lrc_match & ~rptc_ctrl[`PTC_RPTC_CTRL_SINGLE] - | rptc_ctrl[`PTC_RPTC_CTRL_CNTRRST]; - -// -// Stop counter when lrc_match and RPTC_CTRL[SINGLE] both asserted -// -assign stop = lrc_match & rptc_ctrl[`PTC_RPTC_CTRL_SINGLE]; - -// -// PWM reset when lrc_match or system reset -// -assign pwm_rst = lrc_match | wb_rst_i; - -// -// PWM output -// -always @(posedge wb_clk_i) // posedge pwm_rst or posedge hrc_match !!! Damjan - if (pwm_rst) - pwm_pad_o <= #1 1'b0; - else if (hrc_match) - pwm_pad_o <= #1 1'b1; - -// -// Generate an interrupt request -// -assign int_match = (lrc_match | hrc_match) & rptc_ctrl[`PTC_RPTC_CTRL_INTE]; - -// Register interrupt request -always @(posedge wb_rst_i or posedge wb_clk_i) // posedge int_match (instead of wb_rst_i) - if (wb_rst_i) - int <= #1 1'b0; - else if (int_match) - int <= #1 1'b1; - else - int <= #1 1'b0; - -// -// Alias -// -assign wb_inta_o = rptc_ctrl[`PTC_RPTC_CTRL_INT]; - -`else - -// -// When PTC is not implemented, drive all outputs as would when RPTC_CTRL -// is cleared and WISHBONE transfers complete with errors -// -assign wb_inta_o = 1'b0; -assign wb_ack_o = 1'b0; -assign wb_err_o = cyc_i & stb_i; -assign pwm_pad_o = 1'b0; -assign oen_padoen_o = 1'b1; - -// -// Read PTC registers -// -`ifdef PTC_READREGS -assign wb_dat_o = {dw{1'b0}}; -`endif - -`endif - -endmodule Index: ptc/trunk/rtl/verilog/ptc_top.v =================================================================== --- ptc/trunk/rtl/verilog/ptc_top.v (nonexistent) +++ ptc/trunk/rtl/verilog/ptc_top.v (revision 12) @@ -0,0 +1,394 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE PWM/Timer/Counter //// +//// //// +//// This file is part of the PTC project //// +//// http://www.opencores.org/cores/ptc/ //// +//// //// +//// Description //// +//// Implementation of PWM/Timer/Counter IP core according to //// +//// PTC IP core specification document. //// +//// //// +//// To Do: //// +//// Nothing //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.4 2001/09/18 18:48:29 lampret +// Changed top level ptc into ptc_top. Changed defines.v into ptc_defines.v. Reset of the counter is now synchronous. +// +// Revision 1.3 2001/08/21 23:23:50 lampret +// Changed directory structure, defines and port names. +// +// Revision 1.2 2001/07/17 00:18:10 lampret +// Added new parameters however RTL still has some issues related to hrc_match and int_match +// +// Revision 1.1 2001/06/05 07:45:36 lampret +// Added initial RTL and test benches. There are still some issues with these files. +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "ptc_defines.v" + +module ptc_top( + // WISHBONE Interface + wb_clk_i, wb_rst_i, wb_cyc_i, wb_adr_i, wb_dat_i, wb_sel_i, wb_we_i, wb_stb_i, + wb_dat_o, wb_ack_o, wb_err_o, wb_inta_o, + + // External PTC Interface + gate_clk_pad_i, capt_pad_i, pwm_pad_o, oen_padoen_o +); + +parameter dw = 32; +parameter aw = `PTC_ADDRHH+1; +parameter cw = `PTC_CW; + +// +// WISHBONE Interface +// +input wb_clk_i; // Clock +input wb_rst_i; // Reset +input wb_cyc_i; // cycle valid input +input [aw-1:0] wb_adr_i; // address bus inputs +input [dw-1:0] wb_dat_i; // input data bus +input [3:0] wb_sel_i; // byte select inputs +input wb_we_i; // indicates write transfer +input wb_stb_i; // strobe input +output [dw-1:0] wb_dat_o; // output data bus +output wb_ack_o; // normal termination +output wb_err_o; // termination w/ error +output wb_inta_o; // Interrupt request output + +// +// External PTC Interface +// +input gate_clk_pad_i; // EClk/Gate input +input capt_pad_i; // Capture input +output pwm_pad_o; // PWM output +output oen_padoen_o; // PWM output driver enable + +`ifdef PTC_IMPLEMENTED + +// +// PTC Main Counter Register (or no register) +// +`ifdef PTC_RPTC_CNTR +reg [cw-1:0] rptc_cntr; // RPTC_CNTR register +`else +wire [cw-1:0] rptc_cntr; // No RPTC_CNTR register +`endif + +// +// PTC HI Reference/Capture Register (or no register) +// +`ifdef PTC_RPTC_HRC +reg [cw-1:0] rptc_hrc; // RPTC_HRC register +`else +wire [cw-1:0] rptc_hrc; // No RPTC_HRC register +`endif + +// +// PTC LO Reference/Capture Register (or no register) +// +`ifdef PTC_RPTC_LRC +reg [cw-1:0] rptc_lrc; // RPTC_LRC register +`else +wire [cw-1:0] rptc_lrc; // No RPTC_LRC register +`endif + +// +// PTC Control Register (or no register) +// +`ifdef PTC_RPTC_CTRL +reg [8:0] rptc_ctrl; // RPTC_CTRL register +`else +wire [8:0] rptc_ctrl; // No RPTC_CTRL register +`endif + +// +// Internal wires & regs +// +wire rptc_cntr_sel; // RPTC_CNTR select +wire rptc_hrc_sel; // RPTC_HRC select +wire rptc_lrc_sel; // RPTC_LRC select +wire rptc_ctrl_sel; // RPTC_CTRL select +wire hrc_match; // RPTC_HRC matches RPTC_CNTR +wire lrc_match; // RPTC_LRC matches RPTC_CNTR +wire restart; // Restart counter when asserted +wire stop; // Stop counter when asserted +wire cntr_clk; // Counter clock +wire cntr_rst; // Counter reset +wire hrc_clk; // RPTC_HRC clock +wire lrc_clk; // RPTC_LRC clock +wire eclk_gate; // ptc_ecgt xored by RPTC_CTRL[NEC] +wire gate; // Gate function of ptc_ecgt +wire pwm_rst; // Reset of a PWM output +reg [dw-1:0] wb_dat_o; // Data out +reg pwm_pad_o; // PWM output +reg int; // Interrupt reg +wire int_match; // Interrupt match +wire full_decoding; // Full address decoding qualification + +// +// All WISHBONE transfer terminations are successful except when: +// a) full address decoding is enabled and address doesn't match +// any of the PTC registers +// b) sel_i evaluation is enabled and one of the sel_i inputs is zero +// +assign wb_ack_o = wb_cyc_i & wb_stb_i & !wb_err_o; +`ifdef PTC_FULL_DECODE +`ifdef PTC_STRICT_32BIT_ACCESS +assign wb_err_o = wb_cyc_i & wb_stb_i & (!full_decoding | (wb_sel_i != 4'b1111)); +`else +assign wb_err_o = wb_cyc_i & wb_stb_i & !full_decoding; +`endif +`else +`ifdef PTC_STRICT_32BIT_ACCESS +assign wb_err_o = wb_cyc_i & wb_stb_i & (wb_sel_i != 4'b1111); +`else +assign wb_err_o = 1'b0; +`endif +`endif + +// +// Counter clock is selected by RPTC_CTRL[ECLK]. When it is set, +// external clock is used. +// +assign cntr_clk = rptc_ctrl[`PTC_RPTC_CTRL_ECLK] ? eclk_gate : wb_clk_i; + +// +// Counter reset +// +assign cntr_rst = wb_rst_i; + +// +// HRC clock is selected by RPTC_CTRL[CAPTE]. When it is set, +// ptc_capt is used as a clock. +// +assign hrc_clk = rptc_ctrl[`PTC_RPTC_CTRL_CAPTE] ? capt_pad_i : wb_clk_i; + +// +// LRC clock is selected by RPTC_CTRL[CAPTE]. When it is set, +// inverted ptc_capt is used as a clock. +// +assign lrc_clk = rptc_ctrl[`PTC_RPTC_CTRL_CAPTE] ? ~capt_pad_i : wb_clk_i; + +// +// PWM output driver enable is inverted RPTC_CTRL[OE] +// +assign oen_padoen_o = ~rptc_ctrl[`PTC_RPTC_CTRL_OE]; + +// +// Use RPTC_CTRL[NEC] +// +assign eclk_gate = gate_clk_pad_i ^ rptc_ctrl[`PTC_RPTC_CTRL_NEC]; + +// +// Gate function is active when RPTC_CTRL[ECLK] is cleared +// +assign gate = eclk_gate & ~rptc_ctrl[`PTC_RPTC_CTRL_ECLK]; + +// +// Full address decoder +// +`ifdef PTC_FULL_DECODE +assign full_decoding = (wb_adr_i[`PTC_ADDRHH:`PTC_ADDRHL] == {`PTC_ADDRHH-`PTC_ADDRHL+1{1'b0}}) & + (wb_adr_i[`PTC_ADDRLH:`PTC_ADDRLL] == {`PTC_ADDRLH-`PTC_ADDRLL+1{1'b0}}); +`else +assign full_decoding = 1'b1; +`endif + +// +// PTC registers address decoder +// +assign rptc_cntr_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`PTC_OFS_BITS] == `PTC_RPTC_CNTR) & full_decoding; +assign rptc_hrc_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`PTC_OFS_BITS] == `PTC_RPTC_HRC) & full_decoding; +assign rptc_lrc_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`PTC_OFS_BITS] == `PTC_RPTC_LRC) & full_decoding; +assign rptc_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`PTC_OFS_BITS] == `PTC_RPTC_CTRL) & full_decoding; + +// +// Write to RPTC_CTRL or update of RPTC_CTRL[INT] bit +// +`ifdef PTC_RPTC_CTRL +always @(posedge wb_clk_i or posedge wb_rst_i) + if (wb_rst_i) + rptc_ctrl <= #1 9'b0; + else if (rptc_ctrl_sel && wb_we_i) + rptc_ctrl <= #1 wb_dat_i[8:0]; + else if (rptc_ctrl[`PTC_RPTC_CTRL_INTE]) + rptc_ctrl[`PTC_RPTC_CTRL_INT] <= #1 rptc_ctrl[`PTC_RPTC_CTRL_INT] | int; +`else +assign rptc_ctrl = `PTC_DEF_RPTC_CTRL; +`endif + +// +// Write to RPTC_HRC +// +`ifdef PTC_RPTC_HRC +always @(posedge hrc_clk or posedge wb_rst_i) + if (wb_rst_i) + rptc_hrc <= #1 {cw{1'b0}}; + else if (rptc_hrc_sel && wb_we_i) + rptc_hrc <= #1 wb_dat_i[cw-1:0]; + else if (rptc_ctrl[`PTC_RPTC_CTRL_CAPTE]) + rptc_hrc <= #1 rptc_cntr; +`else +assign rptc_hrc = `DEF_RPTC_HRC; +`endif + +// +// Write to RPTC_LRC +// +`ifdef PTC_RPTC_LRC +always @(posedge lrc_clk or posedge wb_rst_i) + if (wb_rst_i) + rptc_lrc <= #1 {cw{1'b0}}; + else if (rptc_lrc_sel && wb_we_i) + rptc_lrc <= #1 wb_dat_i[cw-1:0]; + else if (rptc_ctrl[`PTC_RPTC_CTRL_CAPTE]) + rptc_lrc <= #1 rptc_cntr; +`else +assign rptc_lrc = `DEF_RPTC_LRC; +`endif + +// +// Write to or increment of RPTC_CNTR +// +`ifdef PTC_RPTC_CNTR +always @(posedge cntr_clk or posedge cntr_rst) + if (cntr_rst) + rptc_cntr <= #1 {cw{1'b0}}; + else if (rptc_cntr_sel && wb_we_i) + rptc_cntr <= #1 wb_dat_i[cw-1:0]; + else if (restart) + rptc_cntr <= #1 {cw{1'b0}}; + else if (!stop && rptc_ctrl[`PTC_RPTC_CTRL_EN] && !gate) + rptc_cntr <= #1 rptc_cntr + 1; +`else +assign rptc_cntr = `DEF_RPTC_CNTR; +`endif + +// +// Read PTC registers +// +always @(wb_adr_i or rptc_hrc or rptc_lrc or rptc_ctrl or rptc_cntr) + case (wb_adr_i[`PTC_OFS_BITS]) // synopsys full_case parallel_case +`ifdef PTC_READREGS + `PTC_RPTC_HRC: wb_dat_o[dw-1:0] = {{dw-cw{1'b0}}, rptc_hrc}; + `PTC_RPTC_LRC: wb_dat_o[dw-1:0] = {{dw-cw{1'b0}}, rptc_lrc}; + `PTC_RPTC_CTRL: wb_dat_o[dw-1:0] = {{dw-9{1'b0}}, rptc_ctrl}; +`endif + default: wb_dat_o[dw-1:0] = {{dw-cw{1'b0}}, rptc_cntr}; + endcase + +// +// A match when RPTC_HRC is equal to RPTC_CNTR +// +assign hrc_match = rptc_ctrl[`PTC_RPTC_CTRL_EN] & (rptc_cntr == rptc_hrc); + +// +// A match when RPTC_LRC is equal to RPTC_CNTR +// +assign lrc_match = rptc_ctrl[`PTC_RPTC_CTRL_EN] & (rptc_cntr == rptc_lrc); + +// +// Restart counter when lrc_match asserted and RPTC_CTRL[SINGLE] cleared +// or when RPTC_CTRL[CNTRRST] is set +// +assign restart = lrc_match & ~rptc_ctrl[`PTC_RPTC_CTRL_SINGLE] + | rptc_ctrl[`PTC_RPTC_CTRL_CNTRRST]; + +// +// Stop counter when lrc_match and RPTC_CTRL[SINGLE] both asserted +// +assign stop = lrc_match & rptc_ctrl[`PTC_RPTC_CTRL_SINGLE]; + +// +// PWM reset when lrc_match or system reset +// +assign pwm_rst = lrc_match | wb_rst_i; + +// +// PWM output +// +always @(posedge wb_clk_i) // posedge pwm_rst or posedge hrc_match !!! Damjan + if (pwm_rst) + pwm_pad_o <= #1 1'b0; + else if (hrc_match) + pwm_pad_o <= #1 1'b1; + +// +// Generate an interrupt request +// +assign int_match = (lrc_match | hrc_match) & rptc_ctrl[`PTC_RPTC_CTRL_INTE]; + +// Register interrupt request +always @(posedge wb_rst_i or posedge wb_clk_i) // posedge int_match (instead of wb_rst_i) + if (wb_rst_i) + int <= #1 1'b0; + else if (int_match) + int <= #1 1'b1; + else + int <= #1 1'b0; + +// +// Alias +// +assign wb_inta_o = rptc_ctrl[`PTC_RPTC_CTRL_INT]; + +`else + +// +// When PTC is not implemented, drive all outputs as would when RPTC_CTRL +// is cleared and WISHBONE transfers complete with errors +// +assign wb_inta_o = 1'b0; +assign wb_ack_o = 1'b0; +assign wb_err_o = cyc_i & stb_i; +assign pwm_pad_o = 1'b0; +assign oen_padoen_o = 1'b1; + +// +// Read PTC registers +// +`ifdef PTC_READREGS +assign wb_dat_o = {dw{1'b0}}; +`endif + +`endif + +endmodule Index: ptc/trunk/rtl/verilog/ptc_defines.v =================================================================== --- ptc/trunk/rtl/verilog/ptc_defines.v (nonexistent) +++ ptc/trunk/rtl/verilog/ptc_defines.v (revision 12) @@ -0,0 +1,163 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE PWM/Timer/Counter Definitions //// +//// //// +//// This file is part of the PTC project //// +//// http://www.opencores.org/cores/ptc/ //// +//// //// +//// Description //// +//// PTC definitions. //// +//// //// +//// To Do: //// +//// Nothing //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.2 2001/08/21 23:23:50 lampret +// Changed directory structure, defines and port names. +// +// Revision 1.2 2001/07/17 00:18:08 lampret +// Added new parameters however RTL still has some issues related to hrc_match and int_match +// +// Revision 1.1 2001/06/05 07:45:36 lampret +// Added initial RTL and test benches. There are still some issues with these files. +// +// + +// +// Width of the PTC counter +// +// +`define PTC_CW 32 + +// +// Undefine this one if you don't want to remove PTC block from your design +// but you also don't need it. When it is undefined, all PTC ports still +// remain valid and the core can be synthesized however internally there is +// no PTC funationality. +// +// Defined by default (duhh !). +// +`define PTC_IMPLEMENTED + +// +// Undefine if you don't need to read PTC registers. +// When it is undefined all reads of PTC registers return zero. This +// is usually useful if you want really small area (for example when +// implemented in FPGA). +// +// To follow PTC IP core specification document this one must be defined. +// Also to successfully run the test bench it must be defined. By default +// it is defined. +// +`define PTC_READREGS + +// +// Full WISHBONE address decoding +// +// It is is undefined, partial WISHBONE address decoding is performed. +// Undefine it if you need to save some area. +// +// By default it is defined. +// +`define PTC_FULL_DECODE + +// +// Strict 32-bit WISHBONE access +// +// If this one is defined, all WISHBONE accesses must be 32-bit. If it is +// not defined, err_o is asserted whenever 8- or 16-bit access is made. +// Undefine it if you need to save some area. +// +// By default it is defined. +// +`define PTC_STRICT_32BIT_ACCESS + +// +// WISHBONE address bits used for full decoding of PTC registers. +// +`define PTC_ADDRHH 15 +`define PTC_ADDRHL 5 +`define PTC_ADDRLH 1 +`define PTC_ADDRLL 0 + +// +// Bits of WISHBONE address used for partial decoding of PTC registers. +// +// Default 4:2. +// +`define PTC_OFS_BITS `PTC_ADDRHL-1:`PTC_ADDRLH+1 + +// +// Addresses of PTC registers +// +// To comply with PTC IP core specification document they must go from +// address 0 to address 0xC in the following order: RPTC_CNTR, RPTC_HRC, +// RPTC_LRC and RPTC_CTRL +// +// If particular alarm/ctrl register is not needed, it's address definition +// can be omitted and the register will not be implemented. Instead a fixed +// default value will +// be used. +// +`define PTC_RPTC_CNTR 2'h0 // Address 0x0 +`define PTC_RPTC_HRC 2'h1 // Address 0x4 +`define PTC_RPTC_LRC 2'h2 // Address 0x8 +`define PTC_RPTC_CTRL 2'h3 // Address 0xc + +// +// Default values for unimplemented PTC registers +// +`define PTC_DEF_RPTC_CNTR `PTC_CW'b0 +`define PTC_DEF_RPTC_HRC `PTC_CW'b0 +`define PTC_DEF_RPTC_LRC `PTC_CW'b0 +`define PTC_DEF_RPTC_CTRL 9'h01 // RPTC_CTRL[EN] = 1 + +// +// RPTC_CTRL bits +// +// To comply with the PTC IP core specification document they must go from +// bit 0 to bit 8 in the following order: EN, ECLK, NEC, OE, SINGLE, INTE, +// INT, CNTRRST, CAPTE +// +`define PTC_RPTC_CTRL_EN 0 +`define PTC_RPTC_CTRL_ECLK 1 +`define PTC_RPTC_CTRL_NEC 2 +`define PTC_RPTC_CTRL_OE 3 +`define PTC_RPTC_CTRL_SINGLE 4 +`define PTC_RPTC_CTRL_INTE 5 +`define PTC_RPTC_CTRL_INT 6 +`define PTC_RPTC_CTRL_CNTRRST 7 +`define PTC_RPTC_CTRL_CAPTE 8 + Index: ptc/trunk/bench/verilog/tb_top.v =================================================================== --- ptc/trunk/bench/verilog/tb_top.v (nonexistent) +++ ptc/trunk/bench/verilog/tb_top.v (revision 12) @@ -0,0 +1,152 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// PTC Testbench Top //// +//// //// +//// This file is part of the PTC project //// +//// http://www.opencores.org/cores/ptc/ //// +//// //// +//// Description //// +//// Top level of testbench. It instantiates all blocks. //// +//// //// +//// To Do: //// +//// Nothing //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.2 2001/08/21 23:23:48 lampret +// Changed directory structure, defines and port names. +// +// Revision 1.1 2001/06/05 07:45:32 lampret +// Added initial RTL and test benches. There are still some issues with these files. +// +// + +`include "timescale.v" + +module tb_top; + +parameter aw = 32; +parameter dw = 32; + +// +// Interconnect wires +// +wire clk; // Clock +wire rst; // Reset +wire cyc; // Cycle valid +wire [aw-1:0] adr; // Address bus +wire [dw-1:0] dat_m; // Data bus from PTC to WBM +wire [3:0] sel; // Data selects +wire we; // Write enable +wire stb; // Strobe +wire [dw-1:0] dat_ptc;// Data bus from WBM to PTC +wire ack; // Successful cycle termination +wire err; // Failed cycle termination +wire ptc_ecgt;// External PTC clock/gate + +// +// Internal registers +// +reg ptc_capt;// Capture signal + +// +// Instantiation of Clock/Reset Generator +// +clkrst clkrst( + // Clock + .clk_o(clk), + // Reset + .rst_o(rst), + // External clock/gate + .ptc_ecgt(ptc_ecgt) +); + +// +// Instantiation of Master WISHBONE BFM +// +wb_master wb_master( + // WISHBONE Interface + .CLK_I(clk), + .RST_I(rst), + .CYC_O(cyc), + .ADR_O(adr), + .DAT_O(dat_ptc), + .SEL_O(sel), + .WE_O(we), + .STB_O(stb), + .DAT_I(dat_m), + .ACK_I(ack), + .ERR_I(err), + .RTY_I(0), + .TAG_I(4'b0) +); + +// +// Instantiation of PTC core +// +ptc_top ptc_top( + // WISHBONE Interface + .wb_clk_i(clk), + .wb_rst_i(rst), + .wb_cyc_i(cyc), + .wb_adr_i(adr[15:0]), + .wb_dat_i(dat_ptc), + .wb_sel_i(sel), + .wb_we_i(we), + .wb_stb_i(stb), + .wb_dat_o(dat_m), + .wb_ack_o(ack), + .wb_err_o(err), + .wb_inta_o(), + + // External PTC Interface + .gate_clk_pad_i(ptc_ecgt), + .capt_pad_i(ptc_capt), + .pwm_pad_o(), + .oen_padoen_o() +); + +initial ptc_capt = 0; + +// +// Task to set ptc_capt +// +task set_ptc_capt; +input bit; +begin + ptc_capt = bit; +end +endtask + +endmodule Index: ptc/trunk/bench/verilog/tb_tasks.v =================================================================== --- ptc/trunk/bench/verilog/tb_tasks.v (nonexistent) +++ ptc/trunk/bench/verilog/tb_tasks.v (revision 12) @@ -0,0 +1,968 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// PTC Testbench Tasks //// +//// //// +//// This file is part of the PTC project //// +//// http://www.opencores.org/cores/ptc/ //// +//// //// +//// Description //// +//// Testbench tasks. //// +//// //// +//// To Do: //// +//// Nothing //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.2 2001/08/21 23:23:48 lampret +// Changed directory structure, defines and port names. +// +// Revision 1.1 2001/06/05 07:45:32 lampret +// Added initial RTL and test benches. There are still some issues with these files. +// +// + +`include "timescale.v" +`include "ptc_defines.v" +`include "tb_defines.v" + +module tb_tasks; + +integer nr_failed; +integer ints_disabled; +integer ints_working; +integer capt_working; +integer monitor_ptc_pwm, pwm_l1, pwm_l2; + +// +// Count/report failed tests +// +task failed; +begin + $display("FAILED !!!"); + nr_failed = nr_failed + 1; +end +endtask + +// +// Set RPTC_CNTR register +// +task setcntr; +input [31:0] val; + +begin + #100 tb_top.wb_master.wr(`PTC_RPTC_CNTR<<2, val, 4'b1111); +end + +endtask + +// +// Set PTC_RPTC_HRC register +// +task sethrc; +input [31:0] val; + +begin + #100 tb_top.wb_master.wr(`PTC_RPTC_HRC<<2, val, 4'b1111); +end + +endtask + +// +// Set PTC_RPTC_LRC register +// +task setlrc; +input [31:0] val; + +begin + #100 tb_top.wb_master.wr(`PTC_RPTC_LRC<<2, val, 4'b1111); +end + +endtask + +// +// Set PTC_RPTC_CTRL register +// +task setctrl; +input [31:0] val; + +begin + #100 tb_top.wb_master.wr(`PTC_RPTC_CTRL<<2, val, 4'b1111); +end + +endtask + +// +// Display RPTC_CNTR register +// +task showcntr; + +reg [31:0] tmp; +begin + tb_top.wb_master.rd(`PTC_RPTC_CNTR<<2, tmp); + $write(" RPTC_CNTR: %h", tmp); +end + +endtask + +// +// Display RPTC_HRC register +// +task showhrc; + +reg [31:0] tmp; +begin + tb_top.wb_master.rd(`PTC_RPTC_HRC<<2, tmp); + $write(" RPTC_HRC: %h", tmp); +end + +endtask +// +// Display RPTC_LRC register +// +task showlrc; + +reg [31:0] tmp; +begin + tb_top.wb_master.rd(`PTC_RPTC_LRC<<2, tmp); + $write(" RPTC_LRC:%h", tmp); +end + +endtask +// +// Display RPTC_CTRL register +// +task showctrl; + +reg [31:0] tmp; +begin + tb_top.wb_master.rd(`PTC_RPTC_CTRL<<2, tmp); + $write(" RPTC_CTRL: %h", tmp); +end + +endtask + +// +// Compare parameter with PTC_RPTC_CNTR register +// +task comp_cntr; +input [31:0] val; +output ret; + +reg [31:0] tmp; +reg ret; +begin + tb_top.wb_master.rd(`PTC_RPTC_CNTR<<2, tmp); + + if (tmp == val) + ret = 1; + else + ret = 0; +end + +endtask + +// +// Compare parameter with PTC_RPTC_HRC register +// +task comp_hrc; +input [31:0] val; +output ret; + +reg [31:0] tmp; +reg ret; +begin + tb_top.wb_master.rd(`PTC_RPTC_HRC<<2, tmp); + + if (tmp == val) + ret = 1; + else + ret = 0; +end + +endtask + + +// +// Compare parameter with PTC_RPTC_LRC register +// +task comp_lrc; +input [31:0] val; +output ret; + +reg [31:0] tmp; +reg ret; +begin + tb_top.wb_master.rd(`PTC_RPTC_LRC<<2, tmp); + + if (tmp == val) + ret = 1; + else + ret = 0; +end + +endtask + +// +// Get PTC_RPTC_CNTR register +// +task getcntr; +output [31:0] tmp; + +begin + tb_top.wb_master.rd(`PTC_RPTC_CNTR<<2, tmp); +end + +endtask + +// +// Get PTC_RPTC_HRC register +// +task gethrc; +output [31:0] tmp; + +begin + tb_top.wb_master.rd(`PTC_RPTC_HRC<<2, tmp); +end + +endtask + +// +// Get PTC_RPTC_LRC register +// +task getlrc; +output [31:0] tmp; + +begin + tb_top.wb_master.rd(`PTC_RPTC_LRC<<2, tmp); +end + +endtask + +// +// Get PTC_RPTC_CTRL register +// +task getctrl; +output [31:0] tmp; + +begin + tb_top.wb_master.rd(`PTC_RPTC_CTRL<<2, tmp); +end + +endtask + +// +// Test operation of control bit PTC_RPTC_CTRL[ECLK] +// +task test_eclk; +integer l1, l2; +begin + $write(" Testing control bit RPTC_CTRL[ECLK] ..."); + + // + // Phase 1 + // + // PTC uses WISHBONE clock + // + + // Disable PTC, reset counter + setctrl(1 << `PTC_RPTC_CTRL_CNTRRST); + + // Set PTC_RPTC_HRC and PTC_RPTC_LRC to some high value + sethrc('hffffffff); + setlrc('hffffffff); + + // Enable PTC + setctrl(1 << `PTC_RPTC_CTRL_EN); + + // Wait for time to advance + #20000; + + // Get counter + getcntr(l1); + + // + // Phase 2 + // + // PTC uses external clock + // + + // Disable PTC, reset counter + setctrl(1 << `PTC_RPTC_CTRL_CNTRRST); + + // Enable PTC, use external clock + setctrl(1 << `PTC_RPTC_CTRL_EN | 1 << `PTC_RPTC_CTRL_ECLK); +`ifdef PTC_DEBUG + showctrl; + showcntr; +`endif + // Do 10000 external clock cyles + tb_top.clkrst.gen_ptc_ecgt(10000); + + // Get counter + getcntr(l2); + + // + // Phase 3 + // + // Compare counter from phase 1 and phase 2 + // + if (l2 - l1 == 7498) + $display(" OK"); + else + failed; +end +endtask + +// +// Test operation of control bit PTC_RPTC_CTRL[EN] +// +task test_en; +integer l1, l2; +begin + $write(" Testing control bit RPTC_CTRL[EN] ..."); + + // + // Phase 1 + // + // PTC does 1000 external clock cycles + // + + // Disable PTC, reset counter + setctrl(1 << `PTC_RPTC_CTRL_CNTRRST); + + // Enable PTC, use external clock + setctrl(1 << `PTC_RPTC_CTRL_EN | 1 << `PTC_RPTC_CTRL_ECLK); +`ifdef PTC_DEBUG + showctrl; + showcntr; +`endif + // Do 1000 external clock cycles + tb_top.clkrst.gen_ptc_ecgt(1000); + + // Get counter + getcntr(l1); + + // + // Phase 2 + // + // Disable PTC and run for another 1000 external clock cycles + // + + // Disable PTC, use external clock + setctrl(1 << `PTC_RPTC_CTRL_ECLK); +`ifdef PTC_DEBUG + showctrl; + showcntr; +`endif + // Do 1000 external clock cycles + tb_top.clkrst.gen_ptc_ecgt(1000); + + // Get counter + getcntr(l2); + + // + // Phase 3 + // + // Compare counter from phase 1 and phase 2. Should be the same. + // + if (l1 == l2 && l2 == 1000) + $display(" OK"); + else + failed; +end +endtask + +// +// Test operation of control bit PTC_RPTC_CTRL[NEC] +// +task test_nec; +integer l1, l2; +begin + $write(" Testing control bit RPTC_CTRL[NEC] ..."); + + // + // Phase 1 + // + // PTC does 1000 external clock cycles + // + + // Disable PTC, reset counter + setctrl(1 << `PTC_RPTC_CTRL_CNTRRST); + + // Enable PTC, use external clock + setctrl(1 << `PTC_RPTC_CTRL_EN | 1 << `PTC_RPTC_CTRL_ECLK); +`ifdef PTC_DEBUG + showctrl; + showcntr; +`endif + // Do 1000 external clock cycles + tb_top.clkrst.gen_ptc_ecgt(1000); + + // Get counter + getcntr(l1); + + // + // Phase 2 + // + // Enable PTC_RPTC_CTRL[NEC] and run for another 1000 external clock cycles + // + + // Enable PTC_RPTC_CTRL[NEC], use external clock + setctrl(1 << `PTC_RPTC_CTRL_EN | 1 << `PTC_RPTC_CTRL_ECLK | 1 << `PTC_RPTC_CTRL_NEC); +`ifdef PTC_DEBUG + showctrl; + showcntr; +`endif + // Do 1000 external clock cycles + tb_top.clkrst.gen_ptc_ecgt(1000); + + // Get counter + getcntr(l2); + + // + // Phase 3 + // + // Compare counter from phase 1 and phase 2. + // + if (l2 - l1 == 1001) + $display(" OK"); + else + failed; +end +endtask + +// +// Test operation of control bit PTC_RPTC_CTRL[CNTRRST] +// +task test_cntrrst; +integer l1, l2; +begin + $write(" Testing control bit RPTC_CTRL[CNTRRST] ..."); + + // + // Phase 1 + // + // Set counter and clear it + // + + // Disable PTC + setctrl(0); + + // Manually set counter + setcntr('d1234); +`ifdef PTC_DEBUG + showctrl; + showcntr; +`endif + + // Get counter + getcntr(l1); + + // Disable PTC, reset counter + setctrl(1 << `PTC_RPTC_CTRL_CNTRRST); + + // Get counter + getcntr(l2); + + // + // Phase 3 + // + // Counter l1 should be 1234 and counter l2 should be zero + // + if (l1 == 1234 && l2 == 0) + $display(" OK"); + else + failed; +end +endtask + +// +// Test operation of control bit PTC_RPTC_CTRL[OE] +// +task test_oe; +integer l1, l2; +begin + $write(" Testing control bit RPTC_CTRL[OE] ..."); + + // + // Phase 1 + // + // Clear PTC_RPTC_CTRL[OE] + // + + // Disable PTC, clear PTC_RPTC_CTRL[OE] + setctrl(0); + +`ifdef PTC_DEBUG + showctrl; +`endif + + // Get ptc_oen + l1 = tb_top.ptc_top.oen_padoen_o; + + // + // Phase 2 + // + // Set PTC_RPTC_CTRL[OE] + // + + // Disable PTC, set PTC_RPTC_CTRL[OE] + setctrl(1 << `PTC_RPTC_CTRL_OE); + +`ifdef PTC_DEBUG + showctrl; +`endif + + // Get ptc_oen + l2 = tb_top.ptc_top.oen_padoen_o; + + // + // Phase 3 + // + // l1 should be 1 and l2 should be zero + // + if (l1 && !l2) + $display(" OK"); + else + failed; +end +endtask + +// +// Test operation of control bit PTC_RPTC_CTRL[CAPTE] +// +task test_capte; +integer l1, l2; +begin + $write(" Testing control bit RPTC_CTRL[CAPTE] ..."); + + // + // Phase 1 + // + // Run counter off external clock and capture it into PTC_RPTC_HRC/LRC + // + + // Disable PTC, clear counter + setctrl(1 << `PTC_RPTC_CTRL_CNTRRST); + + // Set PTC_RPTC_HRC/LRC to some high value + sethrc('hffffffff); + setlrc('hffffffff); + + // Enable PTC, use external clock, enable PTC_RPTC_CTRL[CAPTE] + setctrl(1 << `PTC_RPTC_CTRL_EN | 1 << `PTC_RPTC_CTRL_ECLK | 1 << `PTC_RPTC_CTRL_CAPTE); + +`ifdef PTC_DEBUG + showctrl; +`endif + + // Do 1000 external clock cycles + tb_top.clkrst.gen_ptc_ecgt(1000); + + // Do posedge ptc_capt + tb_top.set_ptc_capt(1); + + // Get PTC_RPTC_HRC + gethrc(l1); + + // Do additional 1000 external clock cycles + tb_top.clkrst.gen_ptc_ecgt(1000); + + // Do posedge ptc_capt + tb_top.set_ptc_capt(0); + + // Get PTC_RPTC_LRC + getlrc(l2); + + // + // Phase 3 + // + // l1 should be 1000 and l2 should be 2000 + // + if (l1 == 1000 && l2 == 2000) begin + $display(" OK"); + capt_working = 1; + end else + failed; +end +endtask + +// +// Test operation of control bit PTC_RPTC_CTRL[SINGLE] +// +task test_single; +integer l1, l2; +begin + $write(" Testing control bit RPTC_CTRL[SINGLE] ..."); + + // + // Phase 1 + // + // Run counter off external clock with cleared PTC_RPTC_CTRL[SINGLE]. + // Counter should roll over when it reaches PTC_RPTC_LRC value. + // + + // Disable PTC, clear counter + setctrl(1 << `PTC_RPTC_CTRL_CNTRRST); + + // Set PTC_RPTC_HRC to some high value and PTC_RPTC_LRC to 1000 + sethrc('hffffffff); + setlrc('d1000); + + // Enable PTC, use external clock + setctrl(1 << `PTC_RPTC_CTRL_EN | 1 << `PTC_RPTC_CTRL_ECLK); +`ifdef PTC_DEBUG + showctrl; +`endif + + // Do 1501 external clock cycles + tb_top.clkrst.gen_ptc_ecgt(1501); + + // Get counter + getcntr(l1); + + // + // Phase 2 + // + // Run counter off external clock with PTC_RPTC_CTRL[SINGLE] set. + // Counter should stop when it reaches PTC_RPTC_LRC value. + // + + // Disable PTC, clear counter + setctrl(1 << `PTC_RPTC_CTRL_CNTRRST); + + // Set PTC_RPTC_HRC to some high value and PTC_RPTC_LRC to 1000 + sethrc('hffffffff); + setlrc('d1000); + + // Enable PTC, use external clock, set PTC_RPTC_CTRL[SINGLE] + setctrl(1 << `PTC_RPTC_CTRL_EN | 1 << `PTC_RPTC_CTRL_ECLK | 1 << `PTC_RPTC_CTRL_SINGLE); +`ifdef PTC_DEBUG + showctrl; +`endif + + // Do 1500 external clock cycles + tb_top.clkrst.gen_ptc_ecgt(1500); + + // Get counter + getcntr(l2); + + + // + // Phase 3 + // + // l1 should be 500 and l2 should be 1000 + // + if (l1 == 500 && l2 == 1000) + $display(" OK"); + else + failed; +end +endtask + +// +// Test operation of control bit PTC_RPTC_CTRL[INTE] and PTC_RPTC_CTRL[INT] +// +task test_ints; +integer l1, l2, l3; +begin + $write(" Testing control bit RPTC_CTRL[INTE] and PTC_RPTC_CTRL[INT]..."); + + // + // Phase 1 + // + // Run counter off external clock. + // Counter should generate an interrupt when it reaches PTC_RPTC_LRC value. + // + + // Disable PTC, clear counter + setctrl(1 << `PTC_RPTC_CTRL_CNTRRST); + + // Set PTC_RPTC_HRC to some high value and PTC_RPTC_LRC to 1000 + sethrc('hffffffff); + setlrc('d1000); + + // Disable detection of spurious interrupts + ints_disabled = 0; + + // Enable PTC, use external clock, set PTC_RPTC_CTRL[INTE] + setctrl(1 << `PTC_RPTC_CTRL_EN | 1 << `PTC_RPTC_CTRL_ECLK | 1 << `PTC_RPTC_CTRL_INTE); +`ifdef PTC_DEBUG + showctrl; +`endif + // Do 999 external clock cycles + tb_top.clkrst.gen_ptc_ecgt(999); + + // Sample interrupt request. It should be zero. + l1 = tb_top.ptc_top.wb_inta_o; + + // Do 4 additional external clock cycles + tb_top.clkrst.gen_ptc_ecgt(4); + + // Sample interrupt request. It should be one. + l2 = tb_top.ptc_top.wb_inta_o; + + // + // Phase 2 + // + // Mask interrupt. + // + + // Enable detection of spurious interrupts + ints_disabled = 1; + + // Mask interrupt + setctrl(1 << `PTC_RPTC_CTRL_EN | 1 << `PTC_RPTC_CTRL_ECLK); + + // Sample interrupt request. It should be again zero. + l3 = tb_top.ptc_top.wb_inta_o; + + // + // Phase 3 + // + // l1 should be zero, l2 should be one and l3 should be zero + // + if (!l1 && l2 && !l3) begin + $display(" OK"); + ints_working = ints_working + 1; + end else + failed; +end +endtask + +always @(posedge tb_top.ptc_top.gate_clk_pad_i) + if (monitor_ptc_pwm && !tb_top.ptc_top.pwm_pad_o) + pwm_l1 = pwm_l1 + 1; + +always @(posedge tb_top.ptc_top.gate_clk_pad_i) + if (monitor_ptc_pwm && tb_top.ptc_top.pwm_pad_o) + pwm_l2 = pwm_l2 + 1; + +// +// Test PWM mode +// +task test_pwm; +begin + $write(" Testing PWM mode ..."); + + // + // Phase 1 + // + // Run counter off external clock with PWM low for 10 clocks and + // PWM high for 20 clocks + // + + // Disable PTC, clear counter + setctrl(1 << `PTC_RPTC_CTRL_CNTRRST); + + // Set intervals 10 and 20 + // HRC must be set with number one less than low period + // because it takes one clock cycle to reset the counter + sethrc('d9); + setlrc('d29); + + // Enable PTC, use external clock + setctrl(1 << `PTC_RPTC_CTRL_EN | 1 << `PTC_RPTC_CTRL_ECLK); +`ifdef PTC_DEBUG + showctrl; +`endif + // Start monitoring ptc_pwm + monitor_ptc_pwm = 1; + + // Do 3000 external clock cycles + tb_top.clkrst.gen_ptc_ecgt(3000); + + // Stop monitoring ptc_pwm + monitor_ptc_pwm = 0; + + // + // Phase 2 + // + // l1 should be 1000 and l2 should be 2000 + // + if (pwm_l1 == 1000 && pwm_l2 == 2000) + $display(" OK"); + else + failed; +end +endtask + +// +// Test gate feature +// +task test_gate; +integer l1, l2, l3; +begin + $write(" Testing gate feature ..."); + + // + // Phase 1 + // + // Run counter off WB clock and in the middle assert gating + // + + // Disable PTC, clear counter + setctrl(1 << `PTC_RPTC_CTRL_CNTRRST); + + // Set PTC_RPTC_HRC/LRC to some high value + sethrc('hffffffff); + setlrc('hffffffff); + + // Enable PTC + setctrl(1 << `PTC_RPTC_CTRL_EN); +`ifdef PTC_DEBUG + showctrl; +`endif + + // Increment counter + #5000; + + // Get counter + getcntr(l1); + + // Increment counter + #5000; + + // Assert gate + tb_top.clkrst.gen_ptc_ecgt(-1); + + // Get counter + getcntr(l2); + + // Increment counter + #5000; + + // Get counter (should be the same as l2) + getcntr(l3); + + // + // Phase 2 + // + // l1 should be nonzero and l2 and l3 should be the same + // + if (l1 && l1 < l2 && l2 == l3) + $display(" OK"); + else + failed; +end +endtask + +// +// Test operation of control bit PTC_RPTC_CTRL[INTE] and PTC_RPTC_CTRL[INT] +// +task test_modes; +integer l1, l2, l3; +begin + + // Test PWM mode + test_pwm; + + $write(" Testing timer/counter mode ..."); + if (nr_failed == 0) + $display(" OK"); + else + failed; + + // Test gate feature + test_gate; + + $write(" Testing interrupt feature ..."); + if (ints_working == 1) + $display(" OK"); + else + failed; + + $write(" Testing capture feature ..."); + if (capt_working == 1) + $display(" OK"); + else + failed; + +end +endtask + +// +// Do continues check for interrupts +// +always @(posedge tb_top.ptc_top.wb_inta_o) + if (ints_disabled) begin + $display("Spurious interrupt detected. "); + failed; + ints_working = 9876; + $display; + end + +// +// Start of testbench test tasks +// +initial begin +`ifdef PTC_DUMP_VCD + $dumpfile("../out/tb_top.vcd"); + $dumpvars(0); +`endif + nr_failed = 0; + ints_disabled = 1; + ints_working = 0; + capt_working = 0; + monitor_ptc_pwm = 0; + pwm_l1 = 0; + pwm_l2 = 0; + $display; + $display("###"); + $display("### PTC IP Core Verification ###"); + $display("###"); + $display; + $display("I. Testing correct operation of RPTC_CTRL control bits"); + $display; + test_eclk; + test_oe; + test_cntrrst; + test_en; + test_nec; + test_capte; + test_single; + test_ints; + $display; + $display("II. Testing modes of operation ..."); + $display; + test_modes; + $display; + $display("###"); + $display("### FAILED TESTS: %d ###", nr_failed); + $display("###"); + $display; + $finish; +end + +endmodule Index: ptc/trunk/bench/verilog/clkrst.v =================================================================== --- ptc/trunk/bench/verilog/clkrst.v (nonexistent) +++ ptc/trunk/bench/verilog/clkrst.v (revision 12) @@ -0,0 +1,101 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Clock and Reset Generator //// +//// //// +//// This file is part of the PTC project //// +//// http://www.opencores.org/cores/ptc/ //// +//// //// +//// Description //// +//// Clock and reset generator. //// +//// //// +//// To Do: //// +//// Nothing //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1 2001/06/05 07:45:32 lampret +// Added initial RTL and test benches. There are still some issues with these files. +// +// + +`include "timescale.v" + +module clkrst(clk_o, rst_o, ptc_ecgt); + +// +// I/O ports +// +output clk_o; // Clock +output rst_o; // Reset +output ptc_ecgt; // (External) PTC clock/gate + +// +// Internal regs +// +reg clk_o; // Clock +reg rst_o; // Reset +reg ptc_ecgt; // PTC clock/gate + +initial begin + clk_o = 0; + rst_o = 1; + ptc_ecgt = 0; + #20; + rst_o = 0; +end + +// +// Clock +// +always #4 clk_o = ~clk_o; + +// +// PTC clock/gate generator +// +task gen_ptc_ecgt; +input [31:0] cycles; +integer i; +begin + if (cycles == -1) + ptc_ecgt = 1; + else + for (i = 2 * cycles; i; i = i - 1) begin + #4 ptc_ecgt = ~ptc_ecgt; + if (i % 20000 == 19999) + $write("."); + end +end +endtask + +endmodule Index: ptc/trunk/bench/verilog/tb_defines.v =================================================================== --- ptc/trunk/bench/verilog/tb_defines.v (nonexistent) +++ ptc/trunk/bench/verilog/tb_defines.v (revision 12) @@ -0,0 +1,61 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// PTC Testbench Definitions //// +//// //// +//// This file is part of the PTC project //// +//// http://www.opencores.org/cores/ptc/ //// +//// //// +//// Description //// +//// Testbench definitions that affect how testbench simulation //// +//// is performed. //// +//// //// +//// To Do: //// +//// Nothing //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1 2001/06/05 07:45:32 lampret +// Added initial RTL and test benches. There are still some issues with these files. +// +// + +// +// Run test bench with debug output +// +//`define DEBUG + +// +// Dump VCD +// +`define PTC_DUMP_VCD Index: ptc/trunk/bench/verilog/wb_master.v =================================================================== --- ptc/trunk/bench/verilog/wb_master.v (nonexistent) +++ ptc/trunk/bench/verilog/wb_master.v (revision 12) @@ -0,0 +1,306 @@ +`include "timescale.v" + +// -*- Mode: Verilog -*- +// Filename : wb_master.v +// Description : Wishbone Master Behavorial +// Author : Winefred Washington +// Created On : Thu Jan 11 21:18:41 2001 +// Last Modified By: . +// Last Modified On: . +// Update Count : 0 +// Status : Unknown, Use with caution! + +// Description Specification +// General Description: 8, 16, 32-bit WISHBONE Master +// Supported cycles: MASTER, READ/WRITE +// MASTER, BLOCK READ/WRITE +// MASTER, RMW +// Data port, size: 8, 16, 32-bit +// Data port, granularity 8-bit +// Data port, Max. operand size 32-bit +// Data transfer ordering: little endian +// Data transfer sequencing: undefined +// + +module wb_master(CLK_I, RST_I, TAG_I, TAG_O, + ACK_I, ADR_O, CYC_O, DAT_I, DAT_O, ERR_I, RTY_I, SEL_O, STB_O, WE_O); + + input CLK_I; + input RST_I; + input [3:0] TAG_I; + output [3:0] TAG_O; + input ACK_I; + output [31:0] ADR_O; + output CYC_O; + input [31:0] DAT_I; + output [31:0] DAT_O; + input ERR_I; + input RTY_I; + output [3:0] SEL_O; + output STB_O; + output WE_O; + + reg [31:0] ADR_O; + reg [3:0] SEL_O; + reg CYC_O; + reg STB_O; + reg WE_O; + reg [31:0] DAT_O; + + wire [15:0] mem_sizes; // determines the data width of an address range + reg [31:0] write_burst_buffer[0:7]; + reg [31:0] read_burst_buffer[0:7]; + + reg GO; + integer cycle_end; + integer address; + integer data; + integer selects; + integer write_flag; + + // + // mem_sizes determines the data widths of memory space + // The memory space is divided into eight regions. Each + // region is controlled by a two bit field. + // + // Bits + // 00 = 8 bit memory space + // 01 = 16 bit + // 10 = 32 bit + // 11 = 64 bit (not supported in this model + // + + assign mem_sizes = 16'b10_01_10_11_00_01_10_11; + + function [1:0] data_width; + input [31:0] adr; + begin + casex (adr[31:29]) + 3'b000: data_width = mem_sizes[15:14]; + 3'b001: data_width = mem_sizes[13:12]; + 3'b010: data_width = mem_sizes[11:10]; + 3'b011: data_width = mem_sizes[9:8]; + 3'b100: data_width = mem_sizes[7:6]; + 3'b101: data_width = mem_sizes[5:4]; + 3'b110: data_width = mem_sizes[3:2]; + 3'b111: data_width = mem_sizes[1:0]; + 3'bxxx: data_width = 2'bxx; + endcase // casex (adr[31:29]) + end + endfunction + + always @(posedge CLK_I or posedge RST_I) + begin + if (RST_I) + begin + GO = 1'b0; + end + end + + // read single + task rd; + input [31:0] adr; + output [31:0] result; + + begin + cycle_end = 1; + address = adr; + selects = 255; + write_flag = 0; + + GO <= 1; + @(posedge CLK_I); +// GO <= 0; + + // wait for cycle to start + while (~CYC_O) + @(posedge CLK_I); + + // wait for cycle to end + while (CYC_O) + @(posedge CLK_I); + + result = data; +// $display(" Reading %h from address %h", result, address); + + end + endtask // read + + task wr; + input [31:0] adr; + input [31:0] dat; + input [3:0] sel; + begin + cycle_end = 1; + address = adr; + selects = sel; + write_flag = 1; + data = dat; + + GO <= 1; + @(posedge CLK_I); +// GO <= 0; + + // wait for cycle to start + while (~CYC_O) + @(posedge CLK_I); + + // wait for cycle to end + while (CYC_O) + @(posedge CLK_I); +// $display(" Writing %h to address %h", data, address); + + end + endtask // wr + + // block read + task blkrd; + input [31:0] adr; + input end_flag; + output [31:0] result; + + begin + write_flag = 0; + cycle_end = end_flag; + address = adr; + GO <= 1; + @(posedge CLK_I); +// GO <= 0; + + while (~(ACK_I & STB_O)) + @(posedge CLK_I); + + result = data; + end + endtask // blkrd + + // block write + task blkwr; + input [31:0] adr; + input [31:0] dat; + input [3:0] sel; + input end_flag; + begin + write_flag = 1; + cycle_end = end_flag; + address = adr; + data = dat; + selects = sel; + GO <= 1; + @(posedge CLK_I); +// GO <= 0; + + while (~(ACK_I & STB_O)) + @(posedge CLK_I); + + end + endtask // blkwr + + // RMW + task rmw; + input [31:0] adr; + input [31:0] dat; + input [3:0] sel; + output [31:0] result; + + begin + // read phase + write_flag = 0; + cycle_end = 0; + address = adr; + GO <= 1; + @(posedge CLK_I); +// GO <= 0; + + while (~(ACK_I & STB_O)) + @(posedge CLK_I); + + result = data; + + // write phase + write_flag = 1; + address = adr; + selects = sel; + GO <= 1; + data <= dat; + cycle_end <= 1; + @(posedge CLK_I); +// GO <= 0; + + while (~(ACK_I & STB_O)) + @(posedge CLK_I); + + end + endtask // rmw + + always @(posedge CLK_I) + begin + if (RST_I) + ADR_O <= 32'h0000_0000; + else + ADR_O <= address; + end + + always @(posedge CLK_I) + begin + if (RST_I | ERR_I | RTY_I) + CYC_O <= 1'b0; + else if ((cycle_end == 1) & ACK_I) + CYC_O <= 1'b0; + else if (GO | CYC_O) begin + CYC_O <= 1'b1; + GO <= 1'b0; + end + end + + // stb control + always @(posedge CLK_I) + begin + if (RST_I | ERR_I | RTY_I) + STB_O <= 1'b0; + else if (STB_O & ACK_I) + STB_O <= 1'b0; + else if (GO | STB_O) + STB_O <= 1'b1; + end + + // selects & data + always @(posedge CLK_I) + begin + if (write_flag == 0) begin + SEL_O <= 4'b1111; + if (STB_O & ACK_I) + data <= DAT_I; + end + else begin + case (data_width(address)) + 2'b00: begin + SEL_O <= {3'b000, selects[0]}; + DAT_O <= {data[7:0], data[7:0], data[7:0], data[7:0]}; + end + 2'b01: begin + SEL_O <= {2'b00, selects[1:0]}; + DAT_O <= {data[15:0], data[15:0]}; + end + 2'b10: begin + SEL_O <= selects; + DAT_O <= data; + end + endcase + end + end + + always @(posedge CLK_I) + begin + if (RST_I) + WE_O <= 1'b0; + else if (GO) + WE_O <= write_flag; + end + +endmodule + + + + + Index: ptc/trunk/bench/verilog/timescale.v =================================================================== --- ptc/trunk/bench/verilog/timescale.v (nonexistent) +++ ptc/trunk/bench/verilog/timescale.v (revision 12) @@ -0,0 +1 @@ +`timescale 1ns/10ps Index: ptc/trunk/sim/rtl_sim/bin/sim.sh =================================================================== --- ptc/trunk/sim/rtl_sim/bin/sim.sh (nonexistent) +++ ptc/trunk/sim/rtl_sim/bin/sim.sh (revision 12) @@ -0,0 +1,125 @@ +#!/bin/bash + +# +# This script runs RTL and gate-level simulation using different simultion tools. +# Right now Cadence Verilog-XL and NCSim are supported. +# +# Author: Damjan Lampret +# + +# +# User definitions +# + +# Set simulation tool you are using (xl, ncsim, ncver) +SIMTOOL=ncsim + +# Set test bench top module(s) +TB_TOP="tb_tasks" + +# Set include directories +INCLUDE_DIRS="../../../rtl/verilog/ ../../../bench/verilog/" + +# Set test bench files +BENCH_FILES="../../../bench/verilog/*.v" + +# Set RTL source files +RTL_FILES="../../../rtl/verilog/*.v" + +# Set gate-level netlist files +GATE_FILES="../syn/out/final_ptc.v" + +# Set libraries (standard cell etc.) +LIB_FILES="/libs/Virtual_silicon/UMCL18U250D2_2.1/verilog_simulation_models/*.v" + +# Set parameters for simulation tool +if [ $SIMTOOL == xl ]; then + PARAM="+turbo+3 -q" + for i in $INCLUDE_DIRS; do + INCDIR=$INCDIR" +incdir+$i" + done +elif [ $SIMTOOL == ncver ]; then + NCVER_PARAM="" + for i in $INCLUDE_DIRS; do + INCDIR=$INCDIR" +incdir+$i" + done +elif [ $SIMTOOL == ncsim ]; then + NCPREP_PARAM="-UPDATE +overwrite" + NCSIM_PARAM="-MESSAGES -NOCOPYRIGHT" + for i in $INCLUDE_DIRS; do + INCDIR=$INCDIR" +incdir+$i" + done +else + echo "$SIMTOOL is unsupported simulation tool." + exit 0 +fi + +# +# Don't change anything below unless you know what you are doing +# + +# Run simulation in sim directory +cd ../sim + +# Run actual simulation + +# Cadence Verilog-XL +if [ $SIMTOOL == xl ]; then + + # RTL simulation + if [ "$1" == rtl ]; then + verilog $PARAM $INCDIR $BENCH_FILES $RTL_FILES + + # Gate-level simulation + elif [ "$1" == gate ]; then + verilog $PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES + + # Wrong parameter or no parameter + else + echo "Usage: $0 [rtl|gate]" + exit 0 + fi + +# Cadence Ncverilog +elif [ $SIMTOOL == ncver ]; then + + # RTL simulation + if [ "$1" == rtl ]; then + ncverilog $NCVER_PARAM $INCDIR $BENCH_FILES $RTL_FILES + cp ncverilog.log ../log + + # Gate-level simulation + elif [ "$1" == gate ]; then + ncverilog $NCVER_PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES + cp ncverilog.log ../log + + # Wrong parameter or no parameter + else + echo "Usage: $0 [rtl|gate]" + exit 0 + fi + +# Cadence Ncsim +elif [ $SIMTOOL == ncsim ]; then + + # RTL simulation + if [ "$1" == rtl ]; then + ncprep $NCPREP_PARAM $INCDIR $BENCH_FILES $RTL_FILES + ./RUN_NC + + # Gate-level simulation + elif [ "$1" == gate ]; then + ncprep $NCPREP_PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES + ./RUN_NC + + # Wrong parameter or no parameter + else + echo "Usage: $0 [rtl|gate]" + exit 0 + fi + +# Unsupported simulation tool +else + echo "$SIMTOOL is unsupported simulation tool." + exit 0; +fi

ptc/trunk/sim/rtl_sim/bin/sim.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: ptc/trunk/doc/src/ptc_spec.doc =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: ptc/trunk/doc/src/ptc_spec.doc =================================================================== --- ptc/trunk/doc/src/ptc_spec.doc (nonexistent) +++ ptc/trunk/doc/src/ptc_spec.doc (revision 12)

ptc/trunk/doc/src/ptc_spec.doc Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: ptc/trunk/doc/ptc_spec.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: ptc/trunk/doc/ptc_spec.pdf =================================================================== --- ptc/trunk/doc/ptc_spec.pdf (nonexistent) +++ ptc/trunk/doc/ptc_spec.pdf (revision 12)

ptc/trunk/doc/ptc_spec.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: ptc/trunk/syn/run/dodesign =================================================================== --- ptc/trunk/syn/run/dodesign (nonexistent) +++ ptc/trunk/syn/run/dodesign (revision 12) @@ -0,0 +1,5 @@ +#!/bin/sh -f + +# nohup dc_shell -f top.scr | tee ../logs/top.log +dc_shell -f top_ptc.scr > ../logs/top_ptc.log +mv command.log ../logs

ptc/trunk/syn/run/dodesign Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: ptc/trunk/syn/bin/cons_vs_umc18.inc =================================================================== --- ptc/trunk/syn/bin/cons_vs_umc18.inc (nonexistent) +++ ptc/trunk/syn/bin/cons_vs_umc18.inc (revision 12) @@ -0,0 +1,51 @@ +/* Constraints */ +CLK_UNCERTAINTY = 0.1 /* 100 ps */ +DFFPQ2_CKQ = 0.2 /* Clk to Q in technology time units */ +DFFPQ2_SETUP = 0.1 /* Setup time in technology time units */ + +/* Clocks constraints */ +create_clock CLK -period CLK_PERIOD +create_clock ECLK -period CLK_PERIOD +set_clock_skew all_clocks() -uncertainty CLK_UNCERTAINTY +set_dont_touch_network all_clocks() + +/* Reset constraints */ +set_driving_cell -none RST +set_drive 0 RST +set_dont_touch_network RST + +/* All inputs except reset and clock */ +all_inputs_wo_rst_clk = all_inputs() - CLK - RST + +/* Set output delays and load for output signals + * + * All outputs are assumed to go directly into + * external flip-flops for the purpose of this + * synthesis + */ +set_output_delay DFFPQ2_SETUP -clock CLK all_outputs() +set_load load_of(umcl18u250t2_typ/DFFPQ2/D) * 4 all_outputs() + +/* Input delay and driving cell of all inputs + * + * All these signals are assumed to come directly from + * flip-flops for the purpose of this synthesis + * + */ +set_input_delay DFFPQ2_CKQ -clock CLK all_inputs_wo_rst_clk +set_driving_cell -cell DFFPQ2 -pin Q all_inputs_wo_rst_clk + +/* Set design fanout */ +/* +set_max_fanout 10 TOPLEVEL +*/ + +/* Set area constraint */ +set_max_area MAX_AREA + +/* Optimize all near-critical paths to give extra slack for layout */ +c_range = CLK_PERIOD * 0.1 +group_path -critical_range c_range -name CLK -to CLK + +/* Operating conditions */ +set_operating_conditions TYPICAL Index: ptc/trunk/syn/bin/save_design.inc =================================================================== --- ptc/trunk/syn/bin/save_design.inc (nonexistent) +++ ptc/trunk/syn/bin/save_design.inc (revision 12) @@ -0,0 +1,5 @@ +/* Save current design using synopsys format */ +write -hierarchy -format db -output GATE_PATH + STAGE + _ + TOPLEVEL + .db + +/* Save current design using verilog format */ +write -hierarchy -format verilog -output GATE_PATH + STAGE + _ + TOPLEVEL + .v Index: ptc/trunk/syn/bin/tech_vs_umc18.inc =================================================================== --- ptc/trunk/syn/bin/tech_vs_umc18.inc (nonexistent) +++ ptc/trunk/syn/bin/tech_vs_umc18.inc (revision 12) @@ -0,0 +1,16 @@ +/* Set Virtual Silicon UMC 0.18u standard cell library */ + +search_path = {. /libs/Virtual_silicon/UMCL18U250D2_2.1/design_compiler/ } +snps = get_unix_variable("SYNOPSYS") +synthetic_library = { \ + snps + "/libraries/syn/dw01.sldb" \ + snps + "/libraries/syn/dw02.sldb" \ + snps + "/libraries/syn/dw03.sldb" \ + snps + "/libraries/syn/dw04.sldb" \ + snps + "/libraries/syn/dw05.sldb" \ + snps + "/libraries/syn/dw06.sldb" \ + snps + "/libraries/syn/dw07.sldb" } +target_library = { umcl18u250t2_typ.db } +link_library = target_library + synthetic_library +symbol_library = { umcl18u250t2.sdb } + Index: ptc/trunk/syn/bin/reports.inc =================================================================== --- ptc/trunk/syn/bin/reports.inc (nonexistent) +++ ptc/trunk/syn/bin/reports.inc (revision 12) @@ -0,0 +1,10 @@ +/* Basic reports */ +report_area > LOG_PATH + STAGE + _ + TOPLEVEL + _area.log +report_timing -nworst 10 > LOG_PATH + STAGE + _ + TOPLEVEL + _timing.log +report_hierarchy > LOG_PATH + STAGE + _ + TOPLEVEL + _hierarchy.log +report_resources > LOG_PATH + STAGE + _ + TOPLEVEL + _resources.log +report_constraint > LOG_PATH + STAGE + _ + TOPLEVEL + _constraint.log +/* +report_power > LOG_PATH + STAGE + _ + TOPLEVEL + _power.log +*/ + Index: ptc/trunk/syn/bin/select_tech.inc =================================================================== --- ptc/trunk/syn/bin/select_tech.inc (nonexistent) +++ ptc/trunk/syn/bin/select_tech.inc (revision 12) @@ -0,0 +1,5 @@ +/* Defaults */ + +TECH = vs_umc18 /* vs_umc18, art_umc18 */ +CLK_PERIOD = 5 /* 200 MHz */ +MAX_AREA = 0 /* Push hard */ Index: ptc/trunk/syn/bin/set_env.inc =================================================================== --- ptc/trunk/syn/bin/set_env.inc (nonexistent) +++ ptc/trunk/syn/bin/set_env.inc (revision 12) @@ -0,0 +1,18 @@ +/* Enable Verilog HDL preprocessor */ +hdlin_enable_vpp = true + +/* Set log path */ +LOG_PATH = "../log/" + +/* Set gate-level netlist path */ +GATE_PATH = "../out/" + +/* Set RAMS_PATH */ +RAMS_PATH = "../../../lib/" + +/* Set RTL source path */ +RTL_PATH = "../../rtl/verilog/" + +/* Optimize adders */ +synlib_model_map_effort = high +hlo_share_effort = medium Index: ptc/trunk/syn/bin/read_design.inc =================================================================== --- ptc/trunk/syn/bin/read_design.inc (nonexistent) +++ ptc/trunk/syn/bin/read_design.inc (revision 12) @@ -0,0 +1,11 @@ +/* Set search path for verilog include files */ +search_path = search_path + { RTL_PATH } + { GATE_PATH } + +/* Read verilog files of the PTC IP core */ +if (TOPLEVEL == "ptc") { + read -f verilog ptc.v +} else { + echo "Non-existing top level." + exit +} + Index: ptc/trunk/syn/bin/cons_art_umc18.inc =================================================================== --- ptc/trunk/syn/bin/cons_art_umc18.inc (nonexistent) +++ ptc/trunk/syn/bin/cons_art_umc18.inc (revision 12) @@ -0,0 +1,51 @@ +/* Constraints */ +CLK_UNCERTAINTY = 0.1 /* 100 ps */ +DFFHQX2_CKQ = 0.2 /* Clk to Q in technology time units */ +DFFHQX2_SETUP = 0.1 /* Setup time in technology time units */ + +/* Clocks constraints */ +create_clock CLK -period CLK_PERIOD +create_clock ECLK -period CLK_PERIOD +set_clock_skew all_clocks() -uncertainty CLK_UNCERTAINTY +set_dont_touch_network all_clocks() + +/* Reset constraints */ +set_driving_cell -none RST +set_drive 0 RST +set_dont_touch_network RST + +/* All inputs except reset and clock */ +all_inputs_wo_rst_clk = all_inputs() - CLK - RST + +/* Set output delays and load for output signals + * + * All outputs are assumed to go directly into + * external flip-flops for the purpose of this + * synthesis + */ +set_output_delay DFFHQX2_SETUP -clock CLK all_outputs() +set_load load_of(typical/DFFHQX2/D) * 1 all_outputs() + +/* Input delay and driving cell of all inputs + * + * All these signals are assumed to come directly from + * flip-flops for the purpose of this synthesis + * + */ +set_input_delay DFFHQX2_CKQ -clock CLK all_inputs_wo_rst_clk +set_driving_cell -cell DFFHQX2 -pin Q all_inputs_wo_rst_clk + +/* Set design fanout */ +/* +set_max_fanout 10 TOPLEVEL +*/ + +/* Set area constraint */ +set_max_area MAX_AREA + +/* Optimize all near-critical paths to give extra slack for layout */ +c_range = CLK_PERIOD * 0.05 +group_path -critical_range c_range -name CLK -to CLK + +/* Operating conditions */ +set_operating_conditions typical Index: ptc/trunk/syn/bin/tech_art_umc18.inc =================================================================== --- ptc/trunk/syn/bin/tech_art_umc18.inc (nonexistent) +++ ptc/trunk/syn/bin/tech_art_umc18.inc (revision 12) @@ -0,0 +1,17 @@ +/* Set Artisan Sage-X UMC 0.18u standard cell library */ + +search_path = {. /libs/Artisan/aci/sc-x/synopsys/ } + \ + { /libs/Artisan/aci/sc-x/symbols/synopsys/ } +snps = get_unix_variable("SYNOPSYS") +synthetic_library = { \ + snps + "/libraries/syn/dw01.sldb" \ + snps + "/libraries/syn/dw02.sldb" \ + snps + "/libraries/syn/dw03.sldb" \ + snps + "/libraries/syn/dw04.sldb" \ + snps + "/libraries/syn/dw05.sldb" \ + snps + "/libraries/syn/dw06.sldb" \ + snps + "/libraries/syn/dw07.sldb" } +target_library = { typical.db } +link_library = target_library + synthetic_library +symbol_library = { umc18.sdb } + Index: ptc/trunk/syn/bin/top_ptc.scr =================================================================== --- ptc/trunk/syn/bin/top_ptc.scr (nonexistent) +++ ptc/trunk/syn/bin/top_ptc.scr (revision 12) @@ -0,0 +1,65 @@ +/* + * User defines for synthesizing PTC IP core + * + */ +TOPLEVEL = ptc +include select_tech.inc +CLK = clk_i +ECLK = ptc_ecgt +RST = rst_i +CLK_PERIOD = 5 /* 200 MHz */ +MAX_AREA = 0 /* Push hard */ +DO_UNGROUP = yes /* yes, no */ +DO_VERIFY = yes /* yes, no */ + +/* Starting timestamp */ +sh date + +/* Set some basic variables related to environment */ +include set_env.inc +STAGE = final + +/* Load libraries */ +include tech_ + TECH + .inc + +/* Load HDL source files */ +include read_design.inc > LOG_PATH + read_design_ + TOPLEVEL + .log + +/* Set design top */ +current_design TOPLEVEL + +/* Link all blocks and uniquify them */ +link +uniquify +check_design > LOG_PATH + check_design_ + TOPLEVEL + .log + +/* Apply constraints */ +if (TECH == "vs_umc18") { + include cons_vs_umc18.inc +} else if (TECH == "art_umc18") { + include cons_art_umc18.inc +} else { + echo "Error: Unsupported technology" + exit +} + +/* Lets do basic synthesis */ +if (DO_UNGROUP == "yes") { + ungroup -all +} +compile -boundary_optimization -map_effort low + +/* Dump gate-level from incremental synthesis */ +include save_design.inc + +/* Generate reports for incremental synthesis */ +include reports.inc + +/* Verify design */ +if (DO_VERIFY == "yes") { + compile -no_map -verify > LOG_PATH + verify_ + TOPLEVEL + .log +} + +/* Finish */ +sh date +exit Index: ptc/trunk =================================================================== --- ptc/trunk (nonexistent) +++ ptc/trunk (revision 12)

ptc/trunk Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: ptc/web_uploads =================================================================== --- ptc/web_uploads (nonexistent) +++ ptc/web_uploads (revision 12)

ptc/web_uploads Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: ptc/branches =================================================================== --- ptc/branches (nonexistent) +++ ptc/branches (revision 12)

ptc/branches Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: ptc/tags/a/bench/verilog/clkrst.v =================================================================== --- ptc/tags/a/bench/verilog/clkrst.v (nonexistent) +++ ptc/tags/a/bench/verilog/clkrst.v (revision 12) @@ -0,0 +1,101 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Clock and Reset Generator //// +//// //// +//// This file is part of the PTC project //// +//// http://www.opencores.org/cores/ptc/ //// +//// //// +//// Description //// +//// Clock and reset generator. //// +//// //// +//// To Do: //// +//// Nothing //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1 2001/06/05 07:45:32 lampret +// Added initial RTL and test benches. There are still some issues with these files. +// +// + +`include "timescale.v" + +module clkrst(clk_o, rst_o, ptc_ecgt); + +// +// I/O ports +// +output clk_o; // Clock +output rst_o; // Reset +output ptc_ecgt; // (External) PTC clock/gate + +// +// Internal regs +// +reg clk_o; // Clock +reg rst_o; // Reset +reg ptc_ecgt; // PTC clock/gate + +initial begin + clk_o = 0; + rst_o = 1; + ptc_ecgt = 0; + #20; + rst_o = 0; +end + +// +// Clock +// +always #4 clk_o = ~clk_o; + +// +// PTC clock/gate generator +// +task gen_ptc_ecgt; +input [31:0] cycles; +integer i; +begin + if (cycles == -1) + ptc_ecgt = 1; + else + for (i = 2 * cycles; i; i = i - 1) begin + #4 ptc_ecgt = ~ptc_ecgt; + if (i % 20000 == 19999) + $write("."); + end +end +endtask + +endmodule Index: ptc/tags/a/bench/verilog/tb_defines.v =================================================================== --- ptc/tags/a/bench/verilog/tb_defines.v (nonexistent) +++ ptc/tags/a/bench/verilog/tb_defines.v (revision 12) @@ -0,0 +1,61 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// PTC Testbench Definitions //// +//// //// +//// This file is part of the PTC project //// +//// http://www.opencores.org/cores/ptc/ //// +//// //// +//// Description //// +//// Testbench definitions that affect how testbench simulation //// +//// is performed. //// +//// //// +//// To Do: //// +//// Nothing //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1 2001/06/05 07:45:32 lampret +// Added initial RTL and test benches. There are still some issues with these files. +// +// + +// +// Run test bench with debug output +// +//`define DEBUG + +// +// Dump VCD +// +`define PTC_DUMP_VCD Index: ptc/tags/a/bench/verilog/wb_master.v =================================================================== --- ptc/tags/a/bench/verilog/wb_master.v (nonexistent) +++ ptc/tags/a/bench/verilog/wb_master.v (revision 12) @@ -0,0 +1,306 @@ +`include "timescale.v" + +// -*- Mode: Verilog -*- +// Filename : wb_master.v +// Description : Wishbone Master Behavorial +// Author : Winefred Washington +// Created On : Thu Jan 11 21:18:41 2001 +// Last Modified By: . +// Last Modified On: . +// Update Count : 0 +// Status : Unknown, Use with caution! + +// Description Specification +// General Description: 8, 16, 32-bit WISHBONE Master +// Supported cycles: MASTER, READ/WRITE +// MASTER, BLOCK READ/WRITE +// MASTER, RMW +// Data port, size: 8, 16, 32-bit +// Data port, granularity 8-bit +// Data port, Max. operand size 32-bit +// Data transfer ordering: little endian +// Data transfer sequencing: undefined +// + +module wb_master(CLK_I, RST_I, TAG_I, TAG_O, + ACK_I, ADR_O, CYC_O, DAT_I, DAT_O, ERR_I, RTY_I, SEL_O, STB_O, WE_O); + + input CLK_I; + input RST_I; + input [3:0] TAG_I; + output [3:0] TAG_O; + input ACK_I; + output [31:0] ADR_O; + output CYC_O; + input [31:0] DAT_I; + output [31:0] DAT_O; + input ERR_I; + input RTY_I; + output [3:0] SEL_O; + output STB_O; + output WE_O; + + reg [31:0] ADR_O; + reg [3:0] SEL_O; + reg CYC_O; + reg STB_O; + reg WE_O; + reg [31:0] DAT_O; + + wire [15:0] mem_sizes; // determines the data width of an address range + reg [31:0] write_burst_buffer[0:7]; + reg [31:0] read_burst_buffer[0:7]; + + reg GO; + integer cycle_end; + integer address; + integer data; + integer selects; + integer write_flag; + + // + // mem_sizes determines the data widths of memory space + // The memory space is divided into eight regions. Each + // region is controlled by a two bit field. + // + // Bits + // 00 = 8 bit memory space + // 01 = 16 bit + // 10 = 32 bit + // 11 = 64 bit (not supported in this model + // + + assign mem_sizes = 16'b10_01_10_11_00_01_10_11; + + function [1:0] data_width; + input [31:0] adr; + begin + casex (adr[31:29]) + 3'b000: data_width = mem_sizes[15:14]; + 3'b001: data_width = mem_sizes[13:12]; + 3'b010: data_width = mem_sizes[11:10]; + 3'b011: data_width = mem_sizes[9:8]; + 3'b100: data_width = mem_sizes[7:6]; + 3'b101: data_width = mem_sizes[5:4]; + 3'b110: data_width = mem_sizes[3:2]; + 3'b111: data_width = mem_sizes[1:0]; + 3'bxxx: data_width = 2'bxx; + endcase // casex (adr[31:29]) + end + endfunction + + always @(posedge CLK_I or posedge RST_I) + begin + if (RST_I) + begin + GO = 1'b0; + end + end + + // read single + task rd; + input [31:0] adr; + output [31:0] result; + + begin + cycle_end = 1; + address = adr; + selects = 255; + write_flag = 0; + + GO <= 1; + @(posedge CLK_I); +// GO <= 0; + + // wait for cycle to start + while (~CYC_O) + @(posedge CLK_I); + + // wait for cycle to end + while (CYC_O) + @(posedge CLK_I); + + result = data; +// $display(" Reading %h from address %h", result, address); + + end + endtask // read + + task wr; + input [31:0] adr; + input [31:0] dat; + input [3:0] sel; + begin + cycle_end = 1; + address = adr; + selects = sel; + write_flag = 1; + data = dat; + + GO <= 1; + @(posedge CLK_I); +// GO <= 0; + + // wait for cycle to start + while (~CYC_O) + @(posedge CLK_I); + + // wait for cycle to end + while (CYC_O) + @(posedge CLK_I); +// $display(" Writing %h to address %h", data, address); + + end + endtask // wr + + // block read + task blkrd; + input [31:0] adr; + input end_flag; + output [31:0] result; + + begin + write_flag = 0; + cycle_end = end_flag; + address = adr; + GO <= 1; + @(posedge CLK_I); +// GO <= 0; + + while (~(ACK_I & STB_O)) + @(posedge CLK_I); + + result = data; + end + endtask // blkrd + + // block write + task blkwr; + input [31:0] adr; + input [31:0] dat; + input [3:0] sel; + input end_flag; + begin + write_flag = 1; + cycle_end = end_flag; + address = adr; + data = dat; + selects = sel; + GO <= 1; + @(posedge CLK_I); +// GO <= 0; + + while (~(ACK_I & STB_O)) + @(posedge CLK_I); + + end + endtask // blkwr + + // RMW + task rmw; + input [31:0] adr; + input [31:0] dat; + input [3:0] sel; + output [31:0] result; + + begin + // read phase + write_flag = 0; + cycle_end = 0; + address = adr; + GO <= 1; + @(posedge CLK_I); +// GO <= 0; + + while (~(ACK_I & STB_O)) + @(posedge CLK_I); + + result = data; + + // write phase + write_flag = 1; + address = adr; + selects = sel; + GO <= 1; + data <= dat; + cycle_end <= 1; + @(posedge CLK_I); +// GO <= 0; + + while (~(ACK_I & STB_O)) + @(posedge CLK_I); + + end + endtask // rmw + + always @(posedge CLK_I) + begin + if (RST_I) + ADR_O <= 32'h0000_0000; + else + ADR_O <= address; + end + + always @(posedge CLK_I) + begin + if (RST_I | ERR_I | RTY_I) + CYC_O <= 1'b0; + else if ((cycle_end == 1) & ACK_I) + CYC_O <= 1'b0; + else if (GO | CYC_O) begin + CYC_O <= 1'b1; + GO <= 1'b0; + end + end + + // stb control + always @(posedge CLK_I) + begin + if (RST_I | ERR_I | RTY_I) + STB_O <= 1'b0; + else if (STB_O & ACK_I) + STB_O <= 1'b0; + else if (GO | STB_O) + STB_O <= 1'b1; + end + + // selects & data + always @(posedge CLK_I) + begin + if (write_flag == 0) begin + SEL_O <= 4'b1111; + if (STB_O & ACK_I) + data <= DAT_I; + end + else begin + case (data_width(address)) + 2'b00: begin + SEL_O <= {3'b000, selects[0]}; + DAT_O <= {data[7:0], data[7:0], data[7:0], data[7:0]}; + end + 2'b01: begin + SEL_O <= {2'b00, selects[1:0]}; + DAT_O <= {data[15:0], data[15:0]}; + end + 2'b10: begin + SEL_O <= selects; + DAT_O <= data; + end + endcase + end + end + + always @(posedge CLK_I) + begin + if (RST_I) + WE_O <= 1'b0; + else if (GO) + WE_O <= write_flag; + end + +endmodule + + + + + Index: ptc/tags/a/bench/verilog/timescale.v =================================================================== --- ptc/tags/a/bench/verilog/timescale.v (nonexistent) +++ ptc/tags/a/bench/verilog/timescale.v (revision 12) @@ -0,0 +1 @@ +`timescale 1ns/10ps Index: ptc/tags/a/bench/verilog/tb_top.v =================================================================== --- ptc/tags/a/bench/verilog/tb_top.v (nonexistent) +++ ptc/tags/a/bench/verilog/tb_top.v (revision 12) @@ -0,0 +1,149 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// PTC Testbench Top //// +//// //// +//// This file is part of the PTC project //// +//// http://www.opencores.org/cores/ptc/ //// +//// //// +//// Description //// +//// Top level of testbench. It instantiates all blocks. //// +//// //// +//// To Do: //// +//// Nothing //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1 2001/06/05 07:45:32 lampret +// Added initial RTL and test benches. There are still some issues with these files. +// +// + +`include "timescale.v" + +module tb_top; + +parameter aw = 32; +parameter dw = 32; + +// +// Interconnect wires +// +wire clk; // Clock +wire rst; // Reset +wire cyc; // Cycle valid +wire [aw-1:0] adr; // Address bus +wire [dw-1:0] dat_m; // Data bus from PTC to WBM +wire [3:0] sel; // Data selects +wire we; // Write enable +wire stb; // Strobe +wire [dw-1:0] dat_ptc;// Data bus from WBM to PTC +wire ack; // Successful cycle termination +wire err; // Failed cycle termination +wire ptc_ecgt;// External PTC clock/gate + +// +// Internal registers +// +reg ptc_capt;// Capture signal + +// +// Instantiation of Clock/Reset Generator +// +clkrst clkrst( + // Clock + .clk_o(clk), + // Reset + .rst_o(rst), + // External clock/gate + .ptc_ecgt(ptc_ecgt) +); + +// +// Instantiation of Master WISHBONE BFM +// +wb_master wb_master( + // WISHBONE Interface + .CLK_I(clk), + .RST_I(rst), + .CYC_O(cyc), + .ADR_O(adr), + .DAT_O(dat_ptc), + .SEL_O(sel), + .WE_O(we), + .STB_O(stb), + .DAT_I(dat_m), + .ACK_I(ack), + .ERR_I(err), + .RTY_I(0), + .TAG_I(4'b0) +); + +// +// Instantiation of PTC core +// +ptc ptc( + // WISHBONE Interface + .wb_clk_i(clk), + .wb_rst_i(rst), + .wb_cyc_i(cyc), + .wb_adr_i(adr[15:0]), + .wb_dat_i(dat_ptc), + .wb_sel_i(sel), + .wb_we_i(we), + .wb_stb_i(stb), + .wb_dat_o(dat_m), + .wb_ack_o(ack), + .wb_err_o(err), + .wb_inta_o(), + + // External PTC Interface + .gate_clk_pad_i(ptc_ecgt), + .capt_pad_i(ptc_capt), + .pwm_pad_o(), + .oen_padoen_o() +); + +initial ptc_capt = 0; + +// +// Task to set ptc_capt +// +task set_ptc_capt; +input bit; +begin + ptc_capt = bit; +end +endtask + +endmodule Index: ptc/tags/a/bench/verilog/tb_tasks.v =================================================================== --- ptc/tags/a/bench/verilog/tb_tasks.v (nonexistent) +++ ptc/tags/a/bench/verilog/tb_tasks.v (revision 12) @@ -0,0 +1,964 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// PTC Testbench Tasks //// +//// //// +//// This file is part of the PTC project //// +//// http://www.opencores.org/cores/ptc/ //// +//// //// +//// Description //// +//// Testbench tasks. //// +//// //// +//// To Do: //// +//// Nothing //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1 2001/06/05 07:45:32 lampret +// Added initial RTL and test benches. There are still some issues with these files. +// +// + +`include "timescale.v" +`include "defines.v" +`include "tb_defines.v" + +module tb_tasks; + +integer nr_failed; +integer ints_disabled; +integer ints_working; +integer capt_working; +integer monitor_ptc_pwm, pwm_l1, pwm_l2; + +// +// Count/report failed tests +// +task failed; +begin + $display("FAILED !!!"); + nr_failed = nr_failed + 1; +end +endtask + +// +// Set RPTC_CNTR register +// +task setcntr; +input [31:0] val; + +begin + #100 tb_top.wb_master.wr(`PTC_RPTC_CNTR<<2, val, 4'b1111); +end + +endtask + +// +// Set PTC_RPTC_HRC register +// +task sethrc; +input [31:0] val; + +begin + #100 tb_top.wb_master.wr(`PTC_RPTC_HRC<<2, val, 4'b1111); +end + +endtask + +// +// Set PTC_RPTC_LRC register +// +task setlrc; +input [31:0] val; + +begin + #100 tb_top.wb_master.wr(`PTC_RPTC_LRC<<2, val, 4'b1111); +end + +endtask + +// +// Set PTC_RPTC_CTRL register +// +task setctrl; +input [31:0] val; + +begin + #100 tb_top.wb_master.wr(`PTC_RPTC_CTRL<<2, val, 4'b1111); +end + +endtask + +// +// Display RPTC_CNTR register +// +task showcntr; + +reg [31:0] tmp; +begin + tb_top.wb_master.rd(`PTC_RPTC_CNTR<<2, tmp); + $write(" RPTC_CNTR: %h", tmp); +end + +endtask + +// +// Display RPTC_HRC register +// +task showhrc; + +reg [31:0] tmp; +begin + tb_top.wb_master.rd(`PTC_RPTC_HRC<<2, tmp); + $write(" RPTC_HRC: %h", tmp); +end + +endtask +// +// Display RPTC_LRC register +// +task showlrc; + +reg [31:0] tmp; +begin + tb_top.wb_master.rd(`PTC_RPTC_LRC<<2, tmp); + $write(" RPTC_LRC:%h", tmp); +end + +endtask +// +// Display RPTC_CTRL register +// +task showctrl; + +reg [31:0] tmp; +begin + tb_top.wb_master.rd(`PTC_RPTC_CTRL<<2, tmp); + $write(" RPTC_CTRL: %h", tmp); +end + +endtask + +// +// Compare parameter with PTC_RPTC_CNTR register +// +task comp_cntr; +input [31:0] val; +output ret; + +reg [31:0] tmp; +reg ret; +begin + tb_top.wb_master.rd(`PTC_RPTC_CNTR<<2, tmp); + + if (tmp == val) + ret = 1; + else + ret = 0; +end + +endtask + +// +// Compare parameter with PTC_RPTC_HRC register +// +task comp_hrc; +input [31:0] val; +output ret; + +reg [31:0] tmp; +reg ret; +begin + tb_top.wb_master.rd(`PTC_RPTC_HRC<<2, tmp); + + if (tmp == val) + ret = 1; + else + ret = 0; +end + +endtask + + +// +// Compare parameter with PTC_RPTC_LRC register +// +task comp_lrc; +input [31:0] val; +output ret; + +reg [31:0] tmp; +reg ret; +begin + tb_top.wb_master.rd(`PTC_RPTC_LRC<<2, tmp); + + if (tmp == val) + ret = 1; + else + ret = 0; +end + +endtask + +// +// Get PTC_RPTC_CNTR register +// +task getcntr; +output [31:0] tmp; + +begin + tb_top.wb_master.rd(`PTC_RPTC_CNTR<<2, tmp); +end + +endtask + +// +// Get PTC_RPTC_HRC register +// +task gethrc; +output [31:0] tmp; + +begin + tb_top.wb_master.rd(`PTC_RPTC_HRC<<2, tmp); +end + +endtask + +// +// Get PTC_RPTC_LRC register +// +task getlrc; +output [31:0] tmp; + +begin + tb_top.wb_master.rd(`PTC_RPTC_LRC<<2, tmp); +end + +endtask + +// +// Get PTC_RPTC_CTRL register +// +task getctrl; +output [31:0] tmp; + +begin + tb_top.wb_master.rd(`PTC_RPTC_CTRL<<2, tmp); +end + +endtask + +// +// Test operation of control bit PTC_RPTC_CTRL[ECLK] +// +task test_eclk; +integer l1, l2; +begin + $write(" Testing control bit RPTC_CTRL[ECLK] ..."); + + // + // Phase 1 + // + // PTC uses WISHBONE clock + // + + // Disable PTC, reset counter + setctrl(1 << `PTC_RPTC_CTRL_CNTRRST); + + // Set PTC_RPTC_HRC and PTC_RPTC_LRC to some high value + sethrc('hffffffff); + setlrc('hffffffff); + + // Enable PTC + setctrl(1 << `PTC_RPTC_CTRL_EN); + + // Wait for time to advance + #20000; + + // Get counter + getcntr(l1); + + // + // Phase 2 + // + // PTC uses external clock + // + + // Disable PTC, reset counter + setctrl(1 << `PTC_RPTC_CTRL_CNTRRST); + + // Enable PTC, use external clock + setctrl(1 << `PTC_RPTC_CTRL_EN | 1 << `PTC_RPTC_CTRL_ECLK); +`ifdef PTC_DEBUG + showctrl; + showcntr; +`endif + // Do 10000 external clock cyles + tb_top.clkrst.gen_ptc_ecgt(10000); + + // Get counter + getcntr(l2); + + // + // Phase 3 + // + // Compare counter from phase 1 and phase 2 + // + if (l2 - l1 == 7498) + $display(" OK"); + else + failed; +end +endtask + +// +// Test operation of control bit PTC_RPTC_CTRL[EN] +// +task test_en; +integer l1, l2; +begin + $write(" Testing control bit RPTC_CTRL[EN] ..."); + + // + // Phase 1 + // + // PTC does 1000 external clock cycles + // + + // Disable PTC, reset counter + setctrl(1 << `PTC_RPTC_CTRL_CNTRRST); + + // Enable PTC, use external clock + setctrl(1 << `PTC_RPTC_CTRL_EN | 1 << `PTC_RPTC_CTRL_ECLK); +`ifdef PTC_DEBUG + showctrl; + showcntr; +`endif + // Do 1000 external clock cycles + tb_top.clkrst.gen_ptc_ecgt(1000); + + // Get counter + getcntr(l1); + + // + // Phase 2 + // + // Disable PTC and run for another 1000 external clock cycles + // + + // Disable PTC, use external clock + setctrl(1 << `PTC_RPTC_CTRL_ECLK); +`ifdef PTC_DEBUG + showctrl; + showcntr; +`endif + // Do 1000 external clock cycles + tb_top.clkrst.gen_ptc_ecgt(1000); + + // Get counter + getcntr(l2); + + // + // Phase 3 + // + // Compare counter from phase 1 and phase 2. Should be the same. + // + if (l1 == l2 && l2 == 1000) + $display(" OK"); + else + failed; +end +endtask + +// +// Test operation of control bit PTC_RPTC_CTRL[NEC] +// +task test_nec; +integer l1, l2; +begin + $write(" Testing control bit RPTC_CTRL[NEC] ..."); + + // + // Phase 1 + // + // PTC does 1000 external clock cycles + // + + // Disable PTC, reset counter + setctrl(1 << `PTC_RPTC_CTRL_CNTRRST); + + // Enable PTC, use external clock + setctrl(1 << `PTC_RPTC_CTRL_EN | 1 << `PTC_RPTC_CTRL_ECLK); +`ifdef PTC_DEBUG + showctrl; + showcntr; +`endif + // Do 1000 external clock cycles + tb_top.clkrst.gen_ptc_ecgt(1000); + + // Get counter + getcntr(l1); + + // + // Phase 2 + // + // Enable PTC_RPTC_CTRL[NEC] and run for another 1000 external clock cycles + // + + // Enable PTC_RPTC_CTRL[NEC], use external clock + setctrl(1 << `PTC_RPTC_CTRL_EN | 1 << `PTC_RPTC_CTRL_ECLK | 1 << `PTC_RPTC_CTRL_NEC); +`ifdef PTC_DEBUG + showctrl; + showcntr; +`endif + // Do 1000 external clock cycles + tb_top.clkrst.gen_ptc_ecgt(1000); + + // Get counter + getcntr(l2); + + // + // Phase 3 + // + // Compare counter from phase 1 and phase 2. + // + if (l2 - l1 == 1001) + $display(" OK"); + else + failed; +end +endtask + +// +// Test operation of control bit PTC_RPTC_CTRL[CNTRRST] +// +task test_cntrrst; +integer l1, l2; +begin + $write(" Testing control bit RPTC_CTRL[CNTRRST] ..."); + + // + // Phase 1 + // + // Set counter and clear it + // + + // Disable PTC + setctrl(0); + + // Manually set counter + setcntr('d1234); +`ifdef PTC_DEBUG + showctrl; + showcntr; +`endif + + // Get counter + getcntr(l1); + + // Disable PTC, reset counter + setctrl(1 << `PTC_RPTC_CTRL_CNTRRST); + + // Get counter + getcntr(l2); + + // + // Phase 3 + // + // Counter l1 should be 1234 and counter l2 should be zero + // + if (l1 == 1234 && l2 == 0) + $display(" OK"); + else + failed; +end +endtask + +// +// Test operation of control bit PTC_RPTC_CTRL[OE] +// +task test_oe; +integer l1, l2; +begin + $write(" Testing control bit RPTC_CTRL[OE] ..."); + + // + // Phase 1 + // + // Clear PTC_RPTC_CTRL[OE] + // + + // Disable PTC, clear PTC_RPTC_CTRL[OE] + setctrl(0); + +`ifdef PTC_DEBUG + showctrl; +`endif + + // Get ptc_oen + l1 = tb_top.ptc.oen_padoen_o; + + // + // Phase 2 + // + // Set PTC_RPTC_CTRL[OE] + // + + // Disable PTC, set PTC_RPTC_CTRL[OE] + setctrl(1 << `PTC_RPTC_CTRL_OE); + +`ifdef PTC_DEBUG + showctrl; +`endif + + // Get ptc_oen + l2 = tb_top.ptc.oen_padoen_o; + + // + // Phase 3 + // + // l1 should be 1 and l2 should be zero + // + if (l1 && !l2) + $display(" OK"); + else + failed; +end +endtask + +// +// Test operation of control bit PTC_RPTC_CTRL[CAPTE] +// +task test_capte; +integer l1, l2; +begin + $write(" Testing control bit RPTC_CTRL[CAPTE] ..."); + + // + // Phase 1 + // + // Run counter off external clock and capture it into PTC_RPTC_HRC/LRC + // + + // Disable PTC, clear counter + setctrl(1 << `PTC_RPTC_CTRL_CNTRRST); + + // Set PTC_RPTC_HRC/LRC to some high value + sethrc('hffffffff); + setlrc('hffffffff); + + // Enable PTC, use external clock, enable PTC_RPTC_CTRL[CAPTE] + setctrl(1 << `PTC_RPTC_CTRL_EN | 1 << `PTC_RPTC_CTRL_ECLK | 1 << `PTC_RPTC_CTRL_CAPTE); + +`ifdef PTC_DEBUG + showctrl; +`endif + + // Do 1000 external clock cycles + tb_top.clkrst.gen_ptc_ecgt(1000); + + // Do posedge ptc_capt + tb_top.set_ptc_capt(1); + + // Get PTC_RPTC_HRC + gethrc(l1); + + // Do additional 1000 external clock cycles + tb_top.clkrst.gen_ptc_ecgt(1000); + + // Do posedge ptc_capt + tb_top.set_ptc_capt(0); + + // Get PTC_RPTC_LRC + getlrc(l2); + + // + // Phase 3 + // + // l1 should be 1000 and l2 should be 2000 + // + if (l1 == 1000 && l2 == 2000) begin + $display(" OK"); + capt_working = 1; + end else + failed; +end +endtask + +// +// Test operation of control bit PTC_RPTC_CTRL[SINGLE] +// +task test_single; +integer l1, l2; +begin + $write(" Testing control bit RPTC_CTRL[SINGLE] ..."); + + // + // Phase 1 + // + // Run counter off external clock with cleared PTC_RPTC_CTRL[SINGLE]. + // Counter should roll over when it reaches PTC_RPTC_LRC value. + // + + // Disable PTC, clear counter + setctrl(1 << `PTC_RPTC_CTRL_CNTRRST); + + // Set PTC_RPTC_HRC to some high value and PTC_RPTC_LRC to 1000 + sethrc('hffffffff); + setlrc('d1000); + + // Enable PTC, use external clock + setctrl(1 << `PTC_RPTC_CTRL_EN | 1 << `PTC_RPTC_CTRL_ECLK); +`ifdef PTC_DEBUG + showctrl; +`endif + + // Do 1500 external clock cycles + tb_top.clkrst.gen_ptc_ecgt(1500); + + // Get counter + getcntr(l1); + + // + // Phase 2 + // + // Run counter off external clock with PTC_RPTC_CTRL[SINGLE] set. + // Counter should stop when it reaches PTC_RPTC_LRC value. + // + + // Disable PTC, clear counter + setctrl(1 << `PTC_RPTC_CTRL_CNTRRST); + + // Set PTC_RPTC_HRC to some high value and PTC_RPTC_LRC to 1000 + sethrc('hffffffff); + setlrc('d1000); + + // Enable PTC, use external clock, set PTC_RPTC_CTRL[SINGLE] + setctrl(1 << `PTC_RPTC_CTRL_EN | 1 << `PTC_RPTC_CTRL_ECLK | 1 << `PTC_RPTC_CTRL_SINGLE); +`ifdef PTC_DEBUG + showctrl; +`endif + + // Do 1500 external clock cycles + tb_top.clkrst.gen_ptc_ecgt(1500); + + // Get counter + getcntr(l2); + + + // + // Phase 3 + // + // l1 should be 500 and l2 should be 1000 + // + if (l1 == 500 && l2 == 1000) + $display(" OK"); + else + failed; +end +endtask + +// +// Test operation of control bit PTC_RPTC_CTRL[INTE] and PTC_RPTC_CTRL[INT] +// +task test_ints; +integer l1, l2, l3; +begin + $write(" Testing control bit RPTC_CTRL[INTE] and PTC_RPTC_CTRL[INT]..."); + + // + // Phase 1 + // + // Run counter off external clock. + // Counter should generate an interrupt when it reaches PTC_RPTC_LRC value. + // + + // Disable PTC, clear counter + setctrl(1 << `PTC_RPTC_CTRL_CNTRRST); + + // Set PTC_RPTC_HRC to some high value and PTC_RPTC_LRC to 1000 + sethrc('hffffffff); + setlrc('d1000); + + // Disable detection of spurious interrupts + ints_disabled = 0; + + // Enable PTC, use external clock, set PTC_RPTC_CTRL[INTE] + setctrl(1 << `PTC_RPTC_CTRL_EN | 1 << `PTC_RPTC_CTRL_ECLK | 1 << `PTC_RPTC_CTRL_INTE); +`ifdef PTC_DEBUG + showctrl; +`endif + + // Do 999 external clock cycles + tb_top.clkrst.gen_ptc_ecgt(999); + + // Sample interrupt request. It should be zero. + l1 = tb_top.ptc.wb_inta_o; + + // Do 1 additional external clock cycles + tb_top.clkrst.gen_ptc_ecgt(10); + + // Sample interrupt request. It should be one. + l2 = tb_top.ptc.wb_inta_o; + + // + // Phase 2 + // + // Mask interrupt. + // + + // Enable detection of spurious interrupts + ints_disabled = 1; + + // Mask interrupt + setctrl(1 << `PTC_RPTC_CTRL_EN | 1 << `PTC_RPTC_CTRL_ECLK); + + // Sample interrupt request. It should be again zero. + l3 = tb_top.ptc.wb_inta_o; + + // + // Phase 3 + // + // l1 should be zero, l2 should be one and l3 should be zero + // + if (!l1 && l2 && !l3) begin + $display(" OK"); + ints_working = ints_working + 1; + end else + failed; +end +endtask + +always @(posedge tb_top.ptc.gate_clk_pad_i) + if (monitor_ptc_pwm && !tb_top.ptc.pwm_pad_o) + pwm_l1 = pwm_l1 + 1; + +always @(posedge tb_top.ptc.gate_clk_pad_i) + if (monitor_ptc_pwm && tb_top.ptc.pwm_pad_o) + pwm_l2 = pwm_l2 + 1; + +// +// Test PWM mode +// +task test_pwm; +begin + $write(" Testing PWM mode ..."); + + // + // Phase 1 + // + // Run counter off external clock with PWM low for 10 clocks and + // PWM high for 20 clocks + // + + // Disable PTC, clear counter + setctrl(1 << `PTC_RPTC_CTRL_CNTRRST); + + // Set intervals 10 and 20 + sethrc('d10); + setlrc('d30); + + // Enable PTC, use external clock + setctrl(1 << `PTC_RPTC_CTRL_EN | 1 << `PTC_RPTC_CTRL_ECLK); +`ifdef PTC_DEBUG + showctrl; +`endif + // Start monitoring ptc_pwm + monitor_ptc_pwm = 1; + + // Do 3000 external clock cycles + tb_top.clkrst.gen_ptc_ecgt(3000); + + // Stop monitoring ptc_pwm + monitor_ptc_pwm = 0; + + // + // Phase 2 + // + // l1 should be 1000 and l2 should be 2000 + // + if (pwm_l1 == 1000 && pwm_l2 == 2000) + $display(" OK"); + else + failed; +end +endtask + +// +// Test gate feature +// +task test_gate; +integer l1, l2, l3; +begin + $write(" Testing gate feature ..."); + + // + // Phase 1 + // + // Run counter off WB clock and in the middle assert gating + // + + // Disable PTC, clear counter + setctrl(1 << `PTC_RPTC_CTRL_CNTRRST); + + // Set PTC_RPTC_HRC/LRC to some high value + sethrc('hffffffff); + setlrc('hffffffff); + + // Enable PTC + setctrl(1 << `PTC_RPTC_CTRL_EN); +`ifdef PTC_DEBUG + showctrl; +`endif + + // Increment counter + #5000; + + // Get counter + getcntr(l1); + + // Increment counter + #5000; + + // Assert gate + tb_top.clkrst.gen_ptc_ecgt(-1); + + // Get counter + getcntr(l2); + + // Increment counter + #5000; + + // Get counter (should be the same as l2) + getcntr(l3); + + // + // Phase 2 + // + // l1 should be nonzero and l2 and l3 should be the same + // + if (l1 && l1 < l2 && l2 == l3) + $display(" OK"); + else + failed; +end +endtask + +// +// Test operation of control bit PTC_RPTC_CTRL[INTE] and PTC_RPTC_CTRL[INT] +// +task test_modes; +integer l1, l2, l3; +begin + + // Test PWM mode + test_pwm; + + $write(" Testing timer/counter mode ..."); + if (nr_failed == 0) + $display(" OK"); + else + failed; + + // Test gate feature + test_gate; + + $write(" Testing interrupt feature ..."); + if (ints_working == 1) + $display(" OK"); + else + failed; + + $write(" Testing capture feature ..."); + if (capt_working == 1) + $display(" OK"); + else + failed; + +end +endtask + +// +// Do continues check for interrupts +// +always @(posedge tb_top.ptc.wb_inta_o) + if (ints_disabled) begin + $display("Spurious interrupt detected. "); + failed; + ints_working = 9876; + $display; + end + +// +// Start of testbench test tasks +// +initial begin +`ifdef PTC_DUMP_VCD + $dumpfile("../sim/tb_top.vcd"); + $dumpvars(0); +`endif + nr_failed = 0; + ints_disabled = 1; + ints_working = 0; + capt_working = 0; + monitor_ptc_pwm = 0; + pwm_l1 = 0; + pwm_l2 = 0; + $display; + $display("###"); + $display("### PTC IP Core Verification ###"); + $display("###"); + $display; + $display("I. Testing correct operation of RPTC_CTRL control bits"); + $display; + test_eclk; + test_oe; + test_cntrrst; + test_en; + test_nec; + test_capte; + test_single; + test_ints; + $display; + $display("II. Testing modes of operation ..."); + $display; + test_modes; + $display; + $display("###"); + $display("### FAILED TESTS: %d ###", nr_failed); + $display("###"); + $display; + $finish; +end + +endmodule Index: ptc/tags/a/sim/rtl_sim/run/ncverilog.log =================================================================== --- ptc/tags/a/sim/rtl_sim/run/ncverilog.log (nonexistent) +++ ptc/tags/a/sim/rtl_sim/run/ncverilog.log (revision 12) @@ -0,0 +1,122 @@ +ncverilog: v3.20.(p1): (c) Copyright 1995 - 2000 Cadence Design Systems, Inc. +ncverilog: v3.20.(p1): Started on Aug 22, 2001 at 01:58:37 +ncverilog + +incdir+../../../rtl/verilog/ + +incdir+../../../bench/verilog/ + ../../../bench/verilog/clkrst.v + ../../../bench/verilog/tb_defines.v + ../../../bench/verilog/tb_tasks.v + ../../../bench/verilog/tb_top.v + ../../../bench/verilog/timescale.v + ../../../bench/verilog/wb_master.v + ../../../rtl/verilog/defines.v + ../../../rtl/verilog/ptc.v + +file: ../../../bench/verilog/clkrst.v + module worklib.clkrst:v (up-to-date) + errors: 0, warnings: 0 +file: ../../../bench/verilog/tb_defines.v +file: ../../../bench/verilog/tb_tasks.v + module worklib.tb_tasks:v + errors: 0, warnings: 0 +file: ../../../bench/verilog/tb_top.v + module worklib.tb_top:v (up-to-date) + errors: 0, warnings: 0 +file: ../../../bench/verilog/timescale.v +file: ../../../bench/verilog/wb_master.v + module worklib.wb_master:v (up-to-date) + errors: 0, warnings: 0 +file: ../../../rtl/verilog/defines.v +file: ../../../rtl/verilog/ptc.v + module worklib.ptc:v (up-to-date) + errors: 0, warnings: 0 + Caching library 'worklib' ....... Done + Elaborating the design hierarchy: +wb_master wb_master( + | +ncelab: *W,CUVWSP (/projects/Temp/damjan/ptc/bench/verilog/tb_top.v,95|18): Too few module port connections. + .RTY_I(0), + | +ncelab: *W,CUVMPW (/projects/Temp/damjan/ptc/bench/verilog/tb_top.v,108|8): port sizes differ in port connection. + Building instance overlay tables: .................... + `PTC_RPTC_HRC: wb_dat_o[dw-1:0] <= {{dw-cw{1'b0}}, rptc_hrc}; + | +ncelab: *W,NEGMCV (/projects/Temp/damjan/ptc/rtl/verilog/ptc.v,303|41): zero or negative multiple concatenation multiplier (0). + `PTC_RPTC_LRC: wb_dat_o[dw-1:0] <= {{dw-cw{1'b0}}, rptc_lrc}; + | +ncelab: *W,NEGMCV (/projects/Temp/damjan/ptc/rtl/verilog/ptc.v,304|41): zero or negative multiple concatenation multiplier (0). + default: wb_dat_o[dw-1:0] <= {{dw-cw{1'b0}}, rptc_cntr}; + | +ncelab: *W,NEGMCV (/projects/Temp/damjan/ptc/rtl/verilog/ptc.v,307|35): zero or negative multiple concatenation multiplier (0). + Done + Generating native compiled code: + worklib.clkrst:v <0x4a5775d7> + streams: 3, words: 351 + worklib.ptc:v <0x445302e9> + streams: 43, words: 4150 + worklib.tb_tasks:v <0x7534da37> + streams: 31, words: 2955 + worklib.tb_top:v <0x6bcb5cb6> + streams: 4, words: 150 + worklib.wb_master:v <0x122b0123> + streams: 38, words: 3464 + Loading native compiled code: .................... Done + Building instance specific data structures. + Design hierarchy summary: + Instances Unique + Modules: 5 5 + Registers: 97 97 + Scalar wires: 30 - + Expanded wires: 32 1 + Vectored wires: 5 - + Always blocks: 17 17 + Initial blocks: 3 3 + Cont. assignments: 16 22 + Pseudo assignments: 2 36 + Simulation timescale: 10ps + Writing initial simulation snapshot: worklib.tb_tasks:v +Loading snapshot worklib.tb_tasks:v .................... Done +ncsim> source /software/cadence/tools/inca/files/ncsimrc +ncsim> run + +Warning! some objects excluded from $dumpvars due to access restrictions, use +access+r on comandline for access to all objects + File: /projects/Temp/damjan/ptc/bench/verilog/tb_tasks.v, line = 928, pos = 9 + Scope: tb_tasks + Time: 0 FS + 0 + + +### +### PTC IP Core Verification ### +### + +I. Testing correct operation of RPTC_CTRL control bits + + Testing control bit RPTC_CTRL[ECLK] ... +Warning! Unable to open VCD file ../sim/tb_top.vcd (check file permissions) + Time: 0 FS + 2 + +. OK + Testing control bit RPTC_CTRL[OE] ... OK + Testing control bit RPTC_CTRL[CNTRRST] ... OK + Testing control bit RPTC_CTRL[EN] ... OK + Testing control bit RPTC_CTRL[NEC] ... OK + Testing control bit RPTC_CTRL[CAPTE] ... OK + Testing control bit RPTC_CTRL[SINGLE] ... OK + Testing control bit RPTC_CTRL[INTE] and PTC_RPTC_CTRL[INT]... OK + +II. Testing modes of operation ... + + Testing PWM mode ...FAILED !!! + Testing timer/counter mode ...FAILED !!! + Testing gate feature ... OK + Testing interrupt feature ... OK + Testing capture feature ... OK + +### +### FAILED TESTS: 2 ### +### + +Simulation complete via $finish(1) at time 224476 NS + 1 +/projects/Temp/damjan/ptc/bench/verilog/tb_tasks.v:961 $finish; +ncsim> exit +ncverilog: v3.20.(p1): Exiting on Aug 22, 2001 at 01:58:38 (total: 00:00:01) Index: ptc/tags/a/sim/rtl_sim/bin/sim.sh =================================================================== --- ptc/tags/a/sim/rtl_sim/bin/sim.sh (nonexistent) +++ ptc/tags/a/sim/rtl_sim/bin/sim.sh (revision 12) @@ -0,0 +1,125 @@ +#!/bin/bash + +# +# This script runs RTL and gate-level simulation using different simultion tools. +# Right now Cadence Verilog-XL and NCSim are supported. +# +# Author: Damjan Lampret +# + +# +# User definitions +# + +# Set simulation tool you are using (xl, ncsim, ncver) +SIMTOOL=ncver + +# Set test bench top module(s) +TB_TOP="tb_tasks" + +# Set include directories +INCLUDE_DIRS="../../../rtl/verilog/ ../../../bench/verilog/" + +# Set test bench files +BENCH_FILES="../../../bench/verilog/*.v" + +# Set RTL source files +RTL_FILES="../../../rtl/verilog/*.v" + +# Set gate-level netlist files +GATE_FILES="../syn/out/final_ptc.v" + +# Set libraries (standard cell etc.) +LIB_FILES="/libs/Virtual_silicon/UMCL18U250D2_2.1/verilog_simulation_models/*.v" + +# Set parameters for simulation tool +if [ $SIMTOOL == xl ]; then + PARAM="+turbo+3 -q" + for i in $INCLUDE_DIRS; do + INCDIR=$INCDIR" +incdir+$i" + done +elif [ $SIMTOOL == ncver ]; then + NCVER_PARAM="" + for i in $INCLUDE_DIRS; do + INCDIR=$INCDIR" +incdir+$i" + done +elif [ $SIMTOOL == ncsim ]; then + NCPREP_PARAM="-UPDATE +overwrite" + NCSIM_PARAM="-MESSAGES -NOCOPYRIGHT" + for i in $INCLUDE_DIRS; do + INCDIR=$INCDIR" +incdir+$i" + done +else + echo "$SIMTOOL is unsupported simulation tool." + exit 0 +fi + +# +# Don't change anything below unless you know what you are doing +# + +# Run simulation in sim directory +cd ../sim + +# Run actual simulation + +# Cadence Verilog-XL +if [ $SIMTOOL == xl ]; then + + # RTL simulation + if [ "$1" == rtl ]; then + verilog $PARAM $INCDIR $BENCH_FILES $RTL_FILES + + # Gate-level simulation + elif [ "$1" == gate ]; then + verilog $PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES + + # Wrong parameter or no parameter + else + echo "Usage: $0 [rtl|gate]" + exit 0 + fi + +# Cadence Ncverilog +elif [ $SIMTOOL == ncver ]; then + + # RTL simulation + if [ "$1" == rtl ]; then + ncverilog $NCVER_PARAM $INCDIR $BENCH_FILES $RTL_FILES + cp ncverilog.log ../log + + # Gate-level simulation + elif [ "$1" == gate ]; then + ncverilog $NCVER_PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES + cp ncverilog.log ../log + + # Wrong parameter or no parameter + else + echo "Usage: $0 [rtl|gate]" + exit 0 + fi + +# Cadence Ncsim +elif [ $SIMTOOL == ncsim ]; then + + # RTL simulation + if [ "$1" == rtl ]; then + ncprep $NCPREP_PARAM $INCDIR $BENCH_FILES $RTL_FILES + ./RUN_NC + + # Gate-level simulation + elif [ "$1" == gate ]; then + ncprep $NCPREP_PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES + ./RUN_NC + + # Wrong parameter or no parameter + else + echo "Usage: $0 [rtl|gate]" + exit 0 + fi + +# Unsupported simulation tool +else + echo "$SIMTOOL is unsupported simulation tool." + exit 0; +fi

ptc/tags/a/sim/rtl_sim/bin/sim.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: ptc/tags/a/doc/src/ptc_spec.doc =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: ptc/tags/a/doc/src/ptc_spec.doc =================================================================== --- ptc/tags/a/doc/src/ptc_spec.doc (nonexistent) +++ ptc/tags/a/doc/src/ptc_spec.doc (revision 12)

ptc/tags/a/doc/src/ptc_spec.doc Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: ptc/tags/a/doc/ptc_spec.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: ptc/tags/a/doc/ptc_spec.pdf =================================================================== --- ptc/tags/a/doc/ptc_spec.pdf (nonexistent) +++ ptc/tags/a/doc/ptc_spec.pdf (revision 12)

ptc/tags/a/doc/ptc_spec.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: ptc/tags/a/syn/run/dodesign =================================================================== --- ptc/tags/a/syn/run/dodesign (nonexistent) +++ ptc/tags/a/syn/run/dodesign (revision 12) @@ -0,0 +1,5 @@ +#!/bin/sh -f + +# nohup dc_shell -f top.scr | tee ../logs/top.log +dc_shell -f top_ptc.scr > ../logs/top_ptc.log +mv command.log ../logs

ptc/tags/a/syn/run/dodesign Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: ptc/tags/a/syn/bin/cons_vs_umc18.inc =================================================================== --- ptc/tags/a/syn/bin/cons_vs_umc18.inc (nonexistent) +++ ptc/tags/a/syn/bin/cons_vs_umc18.inc (revision 12) @@ -0,0 +1,51 @@ +/* Constraints */ +CLK_UNCERTAINTY = 0.1 /* 100 ps */ +DFFPQ2_CKQ = 0.2 /* Clk to Q in technology time units */ +DFFPQ2_SETUP = 0.1 /* Setup time in technology time units */ + +/* Clocks constraints */ +create_clock CLK -period CLK_PERIOD +create_clock ECLK -period CLK_PERIOD +set_clock_skew all_clocks() -uncertainty CLK_UNCERTAINTY +set_dont_touch_network all_clocks() + +/* Reset constraints */ +set_driving_cell -none RST +set_drive 0 RST +set_dont_touch_network RST + +/* All inputs except reset and clock */ +all_inputs_wo_rst_clk = all_inputs() - CLK - RST + +/* Set output delays and load for output signals + * + * All outputs are assumed to go directly into + * external flip-flops for the purpose of this + * synthesis + */ +set_output_delay DFFPQ2_SETUP -clock CLK all_outputs() +set_load load_of(umcl18u250t2_typ/DFFPQ2/D) * 4 all_outputs() + +/* Input delay and driving cell of all inputs + * + * All these signals are assumed to come directly from + * flip-flops for the purpose of this synthesis + * + */ +set_input_delay DFFPQ2_CKQ -clock CLK all_inputs_wo_rst_clk +set_driving_cell -cell DFFPQ2 -pin Q all_inputs_wo_rst_clk + +/* Set design fanout */ +/* +set_max_fanout 10 TOPLEVEL +*/ + +/* Set area constraint */ +set_max_area MAX_AREA + +/* Optimize all near-critical paths to give extra slack for layout */ +c_range = CLK_PERIOD * 0.1 +group_path -critical_range c_range -name CLK -to CLK + +/* Operating conditions */ +set_operating_conditions TYPICAL Index: ptc/tags/a/syn/bin/save_design.inc =================================================================== --- ptc/tags/a/syn/bin/save_design.inc (nonexistent) +++ ptc/tags/a/syn/bin/save_design.inc (revision 12) @@ -0,0 +1,5 @@ +/* Save current design using synopsys format */ +write -hierarchy -format db -output GATE_PATH + STAGE + _ + TOPLEVEL + .db + +/* Save current design using verilog format */ +write -hierarchy -format verilog -output GATE_PATH + STAGE + _ + TOPLEVEL + .v Index: ptc/tags/a/syn/bin/tech_vs_umc18.inc =================================================================== --- ptc/tags/a/syn/bin/tech_vs_umc18.inc (nonexistent) +++ ptc/tags/a/syn/bin/tech_vs_umc18.inc (revision 12) @@ -0,0 +1,16 @@ +/* Set Virtual Silicon UMC 0.18u standard cell library */ + +search_path = {. /libs/Virtual_silicon/UMCL18U250D2_2.1/design_compiler/ } +snps = get_unix_variable("SYNOPSYS") +synthetic_library = { \ + snps + "/libraries/syn/dw01.sldb" \ + snps + "/libraries/syn/dw02.sldb" \ + snps + "/libraries/syn/dw03.sldb" \ + snps + "/libraries/syn/dw04.sldb" \ + snps + "/libraries/syn/dw05.sldb" \ + snps + "/libraries/syn/dw06.sldb" \ + snps + "/libraries/syn/dw07.sldb" } +target_library = { umcl18u250t2_typ.db } +link_library = target_library + synthetic_library +symbol_library = { umcl18u250t2.sdb } + Index: ptc/tags/a/syn/bin/reports.inc =================================================================== --- ptc/tags/a/syn/bin/reports.inc (nonexistent) +++ ptc/tags/a/syn/bin/reports.inc (revision 12) @@ -0,0 +1,10 @@ +/* Basic reports */ +report_area > LOG_PATH + STAGE + _ + TOPLEVEL + _area.log +report_timing -nworst 10 > LOG_PATH + STAGE + _ + TOPLEVEL + _timing.log +report_hierarchy > LOG_PATH + STAGE + _ + TOPLEVEL + _hierarchy.log +report_resources > LOG_PATH + STAGE + _ + TOPLEVEL + _resources.log +report_constraint > LOG_PATH + STAGE + _ + TOPLEVEL + _constraint.log +/* +report_power > LOG_PATH + STAGE + _ + TOPLEVEL + _power.log +*/ + Index: ptc/tags/a/syn/bin/select_tech.inc =================================================================== --- ptc/tags/a/syn/bin/select_tech.inc (nonexistent) +++ ptc/tags/a/syn/bin/select_tech.inc (revision 12) @@ -0,0 +1,5 @@ +/* Defaults */ + +TECH = vs_umc18 /* vs_umc18, art_umc18 */ +CLK_PERIOD = 5 /* 200 MHz */ +MAX_AREA = 0 /* Push hard */ Index: ptc/tags/a/syn/bin/set_env.inc =================================================================== --- ptc/tags/a/syn/bin/set_env.inc (nonexistent) +++ ptc/tags/a/syn/bin/set_env.inc (revision 12) @@ -0,0 +1,18 @@ +/* Enable Verilog HDL preprocessor */ +hdlin_enable_vpp = true + +/* Set log path */ +LOG_PATH = "../log/" + +/* Set gate-level netlist path */ +GATE_PATH = "../out/" + +/* Set RAMS_PATH */ +RAMS_PATH = "../../../lib/" + +/* Set RTL source path */ +RTL_PATH = "../../rtl/verilog/" + +/* Optimize adders */ +synlib_model_map_effort = high +hlo_share_effort = medium Index: ptc/tags/a/syn/bin/read_design.inc =================================================================== --- ptc/tags/a/syn/bin/read_design.inc (nonexistent) +++ ptc/tags/a/syn/bin/read_design.inc (revision 12) @@ -0,0 +1,11 @@ +/* Set search path for verilog include files */ +search_path = search_path + { RTL_PATH } + { GATE_PATH } + +/* Read verilog files of the PTC IP core */ +if (TOPLEVEL == "ptc") { + read -f verilog ptc.v +} else { + echo "Non-existing top level." + exit +} + Index: ptc/tags/a/syn/bin/cons_art_umc18.inc =================================================================== --- ptc/tags/a/syn/bin/cons_art_umc18.inc (nonexistent) +++ ptc/tags/a/syn/bin/cons_art_umc18.inc (revision 12) @@ -0,0 +1,51 @@ +/* Constraints */ +CLK_UNCERTAINTY = 0.1 /* 100 ps */ +DFFHQX2_CKQ = 0.2 /* Clk to Q in technology time units */ +DFFHQX2_SETUP = 0.1 /* Setup time in technology time units */ + +/* Clocks constraints */ +create_clock CLK -period CLK_PERIOD +create_clock ECLK -period CLK_PERIOD +set_clock_skew all_clocks() -uncertainty CLK_UNCERTAINTY +set_dont_touch_network all_clocks() + +/* Reset constraints */ +set_driving_cell -none RST +set_drive 0 RST +set_dont_touch_network RST + +/* All inputs except reset and clock */ +all_inputs_wo_rst_clk = all_inputs() - CLK - RST + +/* Set output delays and load for output signals + * + * All outputs are assumed to go directly into + * external flip-flops for the purpose of this + * synthesis + */ +set_output_delay DFFHQX2_SETUP -clock CLK all_outputs() +set_load load_of(typical/DFFHQX2/D) * 1 all_outputs() + +/* Input delay and driving cell of all inputs + * + * All these signals are assumed to come directly from + * flip-flops for the purpose of this synthesis + * + */ +set_input_delay DFFHQX2_CKQ -clock CLK all_inputs_wo_rst_clk +set_driving_cell -cell DFFHQX2 -pin Q all_inputs_wo_rst_clk + +/* Set design fanout */ +/* +set_max_fanout 10 TOPLEVEL +*/ + +/* Set area constraint */ +set_max_area MAX_AREA + +/* Optimize all near-critical paths to give extra slack for layout */ +c_range = CLK_PERIOD * 0.05 +group_path -critical_range c_range -name CLK -to CLK + +/* Operating conditions */ +set_operating_conditions typical Index: ptc/tags/a/syn/bin/tech_art_umc18.inc =================================================================== --- ptc/tags/a/syn/bin/tech_art_umc18.inc (nonexistent) +++ ptc/tags/a/syn/bin/tech_art_umc18.inc (revision 12) @@ -0,0 +1,17 @@ +/* Set Artisan Sage-X UMC 0.18u standard cell library */ + +search_path = {. /libs/Artisan/aci/sc-x/synopsys/ } + \ + { /libs/Artisan/aci/sc-x/symbols/synopsys/ } +snps = get_unix_variable("SYNOPSYS") +synthetic_library = { \ + snps + "/libraries/syn/dw01.sldb" \ + snps + "/libraries/syn/dw02.sldb" \ + snps + "/libraries/syn/dw03.sldb" \ + snps + "/libraries/syn/dw04.sldb" \ + snps + "/libraries/syn/dw05.sldb" \ + snps + "/libraries/syn/dw06.sldb" \ + snps + "/libraries/syn/dw07.sldb" } +target_library = { typical.db } +link_library = target_library + synthetic_library +symbol_library = { umc18.sdb } + Index: ptc/tags/a/syn/bin/top_ptc.scr =================================================================== --- ptc/tags/a/syn/bin/top_ptc.scr (nonexistent) +++ ptc/tags/a/syn/bin/top_ptc.scr (revision 12) @@ -0,0 +1,65 @@ +/* + * User defines for synthesizing PTC IP core + * + */ +TOPLEVEL = ptc +include select_tech.inc +CLK = clk_i +ECLK = ptc_ecgt +RST = rst_i +CLK_PERIOD = 5 /* 200 MHz */ +MAX_AREA = 0 /* Push hard */ +DO_UNGROUP = yes /* yes, no */ +DO_VERIFY = yes /* yes, no */ + +/* Starting timestamp */ +sh date + +/* Set some basic variables related to environment */ +include set_env.inc +STAGE = final + +/* Load libraries */ +include tech_ + TECH + .inc + +/* Load HDL source files */ +include read_design.inc > LOG_PATH + read_design_ + TOPLEVEL + .log + +/* Set design top */ +current_design TOPLEVEL + +/* Link all blocks and uniquify them */ +link +uniquify +check_design > LOG_PATH + check_design_ + TOPLEVEL + .log + +/* Apply constraints */ +if (TECH == "vs_umc18") { + include cons_vs_umc18.inc +} else if (TECH == "art_umc18") { + include cons_art_umc18.inc +} else { + echo "Error: Unsupported technology" + exit +} + +/* Lets do basic synthesis */ +if (DO_UNGROUP == "yes") { + ungroup -all +} +compile -boundary_optimization -map_effort low + +/* Dump gate-level from incremental synthesis */ +include save_design.inc + +/* Generate reports for incremental synthesis */ +include reports.inc + +/* Verify design */ +if (DO_VERIFY == "yes") { + compile -no_map -verify > LOG_PATH + verify_ + TOPLEVEL + .log +} + +/* Finish */ +sh date +exit Index: ptc/tags =================================================================== --- ptc/tags (nonexistent) +++ ptc/tags (revision 12)

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