OpenCores

/trunk/doc/ultimate_crc.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

trunk/doc/ultimate_crc.pdf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/doc/copying.txt =================================================================== --- trunk/doc/copying.txt (revision 11) +++ trunk/doc/copying.txt (nonexistent) @@ -1,340 +0,0 @@ - GNU GENERAL PUBLIC LICENSE - Version 2, June 1991 - - Copyright (C) 1989, 1991 Free Software Foundation, Inc. - 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - Everyone is permitted to copy and distribute verbatim copies - of this license document, but changing it is not allowed. - - Preamble - - The licenses for most software are designed to take away your -freedom to share and change it. By contrast, the GNU General Public -License is intended to guarantee your freedom to share and change free -software--to make sure the software is free for all its users. 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Index: trunk/doc/src/ultimate_crc.doc =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/src/ultimate_crc.doc =================================================================== --- trunk/doc/src/ultimate_crc.doc (revision 11) +++ trunk/doc/src/ultimate_crc.doc (nonexistent)

trunk/doc/src/ultimate_crc.doc Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/bench/vhdl/wb_tb_pack.txt =================================================================== --- trunk/bench/vhdl/wb_tb_pack.txt (revision 11) +++ trunk/bench/vhdl/wb_tb_pack.txt (nonexistent) @@ -1,2 +0,0 @@ -wb_tb_pack.vhd is reused from the spdif project. Fetch the latest revision of -this file from there. \ No newline at end of file Index: trunk/bench/vhdl/tb_crc.vhd =================================================================== --- trunk/bench/vhdl/tb_crc.vhd (revision 11) +++ trunk/bench/vhdl/tb_crc.vhd (nonexistent) @@ -1,304 +0,0 @@ ----------------------------------------------------------------------- ----- ---- ----- Ultimate CRC. ---- ----- ---- ----- This file is part of the ultimate CRC projectt ---- ----- http://www.opencores.org/cores/ultimate_crc/ ---- ----- ---- ----- Description ---- ----- Test bench for ultimate crc. ---- ----- ---- ----- ---- ----- To Do: ---- ----- - ---- ----- ---- ----- Author(s): ---- ----- - Geir Drange, gedra@opencores.org ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2005 Authors and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.0 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU General Public License for more details.---- ----- ---- ----- You should have received a copy of the GNU General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.gnu.org/licenses/gpl.txt ---- ----- ---- ----------------------------------------------------------------------- --- --- CVS Revision History --- --- $Log: not supported by cvs2svn $ --- Revision 1.1 2005/05/09 16:07:45 gedra --- test bench. --- --- --- - -library ieee; -use ieee.std_logic_1164.all; -use work.ucrc_pkg.all; -use work.wb_tb_pack.all; - -entity tb_crc is - -end tb_crc; - -architecture behav of tb_crc is - - -- Polynomial under testing - constant POLYNOMIAL : std_logic_vector(15 downto 0) := - "0001000000100001"; -- x^16 + x^12 + x^5 + 1; - -- Initialization value - constant INIT_VALUE : std_logic_vector(15 downto 0) := "1111111111111111"; - -- Data width for the parallel implementation - constant DATA_WIDTH : integer := 8; - -- Number of bits - constant CODE_LENGTH : integer := 64 / DATA_WIDTH; - constant EXPECTED_CRC : std_logic_vector(POLYNOMIAL'length - 1 downto 0) := - "0110100100110101"; -- this must be updated if any parameter is changed! - signal clk, rst, d_o, d_v, flush, clken, pd_in : std_logic; - signal lsfr_reg : std_logic_vector(31 downto 0); - signal cnt : integer range 0 to CODE_LENGTH*DATA_WIDTH+10; - signal zero, match_s, match_p, chk_in, clken3 : std_logic; - signal data, par_in : std_logic_vector(DATA_WIDTH - 1 downto 0); - signal crc_s, crc_sc, crc_p : std_logic_vector(POLYNOMIAL'length - 1 downto 0); - signal pcnt : integer range 0 to DATA_WIDTH - 1; - signal one, check, par_clken, clken2, match_p2 : std_logic; - signal crc_p2 : std_logic_vector(31 downto 0); - signal data3 : std_logic_vector(159 downto 0); - -begin - - zero <= '0'; - one <= '1'; - - ---------------------------------------------------------------------------- - -- LFSR generates random bits as input to the CRC generators - ---------------------------------------------------------------------------- - LSFR : process (clk, rst) - begin - if rst = '1' then - lsfr_reg <= (others => '1'); - elsif rising_edge(clk) then - lsfr_reg(0) <= lsfr_reg(31) xor lsfr_reg(6) xor lsfr_reg(4) - xor lsfr_reg(2) xor lsfr_reg(1) xor lsfr_reg(0); - lsfr_reg(31 downto 1) <= lsfr_reg(30 downto 0); - end if; - end process; - - ---------------------------------------------------------------------------- - -- Serial to parallel data register, used to feed the parallel implementation - ---------------------------------------------------------------------------- - pd_in <= chk_in; -- Data plus CRC - par_in(DATA_WIDTH - 1) <= pd_in; - S2P : process (clk, rst) - begin - if rst = '1' then - par_in(DATA_WIDTH - 2 downto 0) <= (others => '0'); - par_clken <= '0'; - pcnt <= 0; - elsif rising_edge(clk) then - if clken = '1' then - par_in(DATA_WIDTH - 2) <= pd_in; - par_in(DATA_WIDTH - 3 downto 0) <= par_in(DATA_WIDTH - 2 downto 1); - if pcnt < DATA_WIDTH - 1 then - pcnt <= pcnt + 1; - else - pcnt <= 0; - end if; - if pcnt = DATA_WIDTH - 2 then - par_clken <= '1'; - else - par_clken <= '0'; - end if; - else - par_clken <= '0'; - end if; - end if; - end process; - - ---------------------------------------------------------------------------- - -- Bit counter and CRC control. Generates clken and flush signals for the - -- serial generator. - ---------------------------------------------------------------------------- - BCNT : process (clk, rst) - begin - if rst = '1' then - cnt <= 0; - flush <= '0'; - clken <= '0'; - elsif rising_edge(clk) then - if cnt < CODE_LENGTH*DATA_WIDTH+10 then - cnt <= cnt + 1; - end if; - if cnt >= DATA_WIDTH and cnt < CODE_LENGTH*DATA_WIDTH then - clken <= '1'; - else - clken <= '0'; - end if; - if (cnt >= CODE_LENGTH*DATA_WIDTH - POLYNOMIAL'length) and - (cnt < CODE_LENGTH*DATA_WIDTH) then - flush <= '1'; - else - flush <= '0'; - end if; - end if; - end process; - - ---------------------------------------------------------------------------- - -- Serial CRC generator. CRC is flushed out after the data block - ---------------------------------------------------------------------------- - SGEN : ucrc_ser - generic map ( - POLYNOMIAL => POLYNOMIAL, - INIT_VALUE => INIT_VALUE, - SYNC_RESET => 1) - port map ( - clk_i => clk, - rst_i => rst, - clken_i => clken, - data_i => lsfr_reg(0), - flush_i => flush, - match_o => open, - crc_o => crc_s); - - ---------------------------------------------------------------------------- - -- Serial CRC checker. Takes input from the serial generator, incl. CRC - ---------------------------------------------------------------------------- - chk_in <= lsfr_reg(0) when flush = '0' else crc_s(POLYNOMIAL'length - 1); - SCHK : ucrc_ser - generic map ( - POLYNOMIAL => POLYNOMIAL, - INIT_VALUE => INIT_VALUE, - SYNC_RESET => 1) - port map ( - clk_i => clk, - rst_i => rst, - clken_i => clken, - data_i => chk_in, - flush_i => zero, - match_o => match_s, - crc_o => crc_sc); - - ---------------------------------------------------------------------------- - -- Parallel CRC generator/checker. Takes input from the serial generator, - -- including the CRC - ---------------------------------------------------------------------------- - PGEN : ucrc_par - generic map ( - POLYNOMIAL => POLYNOMIAL, - INIT_VALUE => INIT_VALUE, - DATA_WIDTH => DATA_WIDTH, - SYNC_RESET => 1) - port map ( - clk_i => clk, - rst_i => rst, - clken_i => par_clken, - data_i => par_in, - match_o => match_p, - crc_o => crc_p); - - ---------------------------------------------------------------------------- - -- 128bit wide CRC generator - ---------------------------------------------------------------------------- - iucrc_par : ucrc_par - generic map ( - POLYNOMIAL => x"00018bb7", - INIT_VALUE => x"00000000", - DATA_WIDTH => 128, - SYNC_RESET => 1) - port map ( - clk_i => clk, - rst_i => rst, - clken_i => clken2, - data_i => (others => '1'), - match_o => open, - crc_o => crc_p2); - - ---------------------------------------------------------------------------- - -- 160bit wide CRC checker - ---------------------------------------------------------------------------- - iucrc_par2 : ucrc_par - generic map ( - POLYNOMIAL => x"00018bb7", - INIT_VALUE => x"00000000", - DATA_WIDTH => 160, - SYNC_RESET => 1) - port map ( - clk_i => clk, - rst_i => rst, - clken_i => clken3, - data_i => data3, - match_o => match_p2, - crc_o => open); - - data3(127 downto 0) <= (others => '1'); - lCpy : for i in 0 to 31 generate -- CRC must be MSB first! - data3(128 + i) <= crc_p2(31 - i); - end generate lCpy; - - ---------------------------------------------------------------------------- - -- Main test process - ---------------------------------------------------------------------------- - MAIN : process - begin - clken2 <= '0'; - clken3 <= '0'; - message("Simulation starts with a reset."); - rst <= '1'; - wait for 18 ns; - rst <= '0'; - wait_for_event("Wait for flushing of serial CRC generator", 1 ms, flush); - wait for 2 ns; - vector_check("CRC of serial generator", EXPECTED_CRC, crc_s); - vector_check("CRC of parallel generator", EXPECTED_CRC, crc_p); - wait_for_event("Wait for flush to finish", 500 ns, flush); - wait for 2 ns; - signal_check("Serial CRC match signal", '1', match_s); - signal_check("Parallel CRC match signal", '1', match_p); - message("Check 128bit crc:"); - wait until rising_edge(clk); - clken2 <= '1'; - wait until rising_edge(clk); - clken2 <= '0'; - wait until rising_edge(clk); - clken3 <= '1'; - wait until rising_edge(clk); - clken3 <= '0'; - signal_check("Parallel 128bit CRC check", '1', match_p2); - sim_report(""); - wait for 100 ns; - report "End of simulation! (ignore this failure)" - severity failure; - wait; - end process; - - ---------------------------------------------------------------------------- - -- Clock - ---------------------------------------------------------------------------- - CLOCK : process - begin - clk <= '0'; - wait for 5 ns; - clk <= '1'; - wait for 5 ns; - end process; - -end behav; - Index: trunk/rtl/vhdl/ucrc_pkg.vhd =================================================================== --- trunk/rtl/vhdl/ucrc_pkg.vhd (revision 11) +++ trunk/rtl/vhdl/ucrc_pkg.vhd (nonexistent) @@ -1,88 +0,0 @@ ----------------------------------------------------------------------- ----- ---- ----- Ultimate CRC. ---- ----- ---- ----- This file is part of the ultimate CRC projectt ---- ----- http://www.opencores.org/cores/ultimate_crc/ ---- ----- ---- ----- Description ---- ----- Ultimate CRC component declarations. ---- ----- ---- ----- ---- ----- To Do: ---- ----- - ---- ----- ---- ----- Author(s): ---- ----- - Geir Drange, gedra@opencores.org ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2005 Authors and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.0 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU General Public License for more details.---- ----- ---- ----- You should have received a copy of the GNU General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.gnu.org/licenses/gpl.txt ---- ----- ---- ----------------------------------------------------------------------- --- --- CVS Revision History --- --- $Log: not supported by cvs2svn $ --- Revision 1.1 2005/05/09 15:56:14 gedra --- Component declarations --- --- --- - -library ieee; -use ieee.std_logic_1164.all; - -package ucrc_pkg is - - component ucrc_ser - generic ( - POLYNOMIAL : std_logic_vector; -- 4 to 32 bits - INIT_VALUE : std_logic_vector; - SYNC_RESET : integer range 0 to 1); -- use synchronous reset - port ( - clk_i : in std_logic; -- clock - rst_i : in std_logic; -- init CRC - clken_i : in std_logic; -- clock enable - data_i : in std_logic; -- data input - flush_i : in std_logic; -- flush crc - match_o : out std_logic; -- CRC match flag - crc_o : out std_logic_vector(POLYNOMIAL'length - 1 downto 0)); -- CRC output - end component; - - component ucrc_par - generic ( - POLYNOMIAL : std_logic_vector; - INIT_VALUE : std_logic_vector; - DATA_WIDTH : integer range 2 to 256; - SYNC_RESET : integer range 0 to 1); -- use synchronous reset - port ( - clk_i : in std_logic; -- clock - rst_i : in std_logic; -- init CRC - clken_i : in std_logic; -- clock enable - data_i : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- data input - match_o : out std_logic; -- CRC match flag - crc_o : out std_logic_vector(POLYNOMIAL'length - 1 downto 0)); -- CRC output - end component; - -end ucrc_pkg; Index: trunk/rtl/vhdl/ucrc_par.vhd =================================================================== --- trunk/rtl/vhdl/ucrc_par.vhd (revision 11) +++ trunk/rtl/vhdl/ucrc_par.vhd (nonexistent) @@ -1,176 +0,0 @@ ----------------------------------------------------------------------- ----- ---- ----- Ultimate CRC. ---- ----- ---- ----- This file is part of the ultimate CRC projectt ---- ----- http://www.opencores.org/cores/ultimate_crc/ ---- ----- ---- ----- Description ---- ----- CRC generator/checker, parallel implementation. ---- ----- ---- ----- ---- ----- To Do: ---- ----- - ---- ----- ---- ----- Author(s): ---- ----- - Geir Drange, gedra@opencores.org ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2005 Authors and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.0 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU General Public License for more details.---- ----- ---- ----- You should have received a copy of the GNU General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.gnu.org/licenses/gpl.txt ---- ----- ---- ----------------------------------------------------------------------- --- --- CVS Revision History --- --- $Log: not supported by cvs2svn $ --- Revision 1.1 2005/05/09 15:58:38 gedra --- Parallel implementation --- --- --- - -library ieee; -use ieee.std_logic_1164.all; - -entity ucrc_par is - generic ( - POLYNOMIAL : std_logic_vector; - INIT_VALUE : std_logic_vector; - DATA_WIDTH : integer range 2 to 256; - SYNC_RESET : integer range 0 to 1); -- use sync./async reset - port ( - clk_i : in std_logic; -- clock - rst_i : in std_logic; -- init CRC - clken_i : in std_logic; -- clock enable - data_i : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- data input - match_o : out std_logic; -- CRC match flag - crc_o : out std_logic_vector(POLYNOMIAL'length - 1 downto 0)); -- CRC output -end ucrc_par; - -architecture rtl of ucrc_par is - - constant msb : integer := POLYNOMIAL'length - 1; - constant init_msb : integer := INIT_VALUE'length - 1; - constant p : std_logic_vector(msb downto 0) := POLYNOMIAL; - constant dw : integer := DATA_WIDTH; - constant pw : integer := POLYNOMIAL'length; - type fb_array is array (dw downto 1) of std_logic_vector(msb downto 0); - type dmsb_array is array (dw downto 1) of std_logic_vector(msb downto 1); - signal crca : fb_array; - signal da, ma : dmsb_array; - signal crc, zero : std_logic_vector(msb downto 0); - signal arst, srst : std_logic; - -begin - --- Parameter checking: Invalid generics will abort simulation/synthesis - PCHK1 : if msb /= init_msb generate - process - begin - report "POLYNOMIAL and INIT_VALUE vectors must be equal length!" - severity failure; - wait; - end process; - end generate PCHK1; - - PCHK2 : if (msb < 3) or (msb > 31) generate - process - begin - report "POLYNOMIAL must be of order 4 to 32!" - severity failure; - wait; - end process; - end generate PCHK2; - - PCHK3 : if p(0) /= '1' generate -- LSB must be 1 - process - begin - report "POLYNOMIAL must have lsb set to 1!" - severity failure; - wait; - end process; - end generate PCHK3; - --- Generate vector of each data bit - CA : for i in 1 to dw generate -- data bits - DAT : for j in 1 to msb generate - da(i)(j) <= data_i(i - 1); - end generate DAT; - end generate CA; - --- Generate vector of each CRC MSB - MS0 : for i in 1 to msb generate - ma(1)(i) <= crc(msb); - end generate MS0; - MSP : for i in 2 to dw generate - MSU : for j in 1 to msb generate - ma(i)(j) <= crca(i - 1)(msb); - end generate MSU; - end generate MSP; - --- Generate feedback matrix - crca(1)(0) <= da(1)(1) xor crc(msb); - crca(1)(msb downto 1) <= crc(msb - 1 downto 0) xor ((da(1) xor ma(1)) and p(msb downto 1)); - FB : for i in 2 to dw generate - crca(i)(0) <= da(i)(1) xor crca(i - 1)(msb); - crca(i)(msb downto 1) <= crca(i - 1)(msb - 1 downto 0) xor - ((da(i) xor ma(i)) and p(msb downto 1)); - end generate FB; - --- Reset signal - SR : if SYNC_RESET = 1 generate - srst <= rst_i; - arst <= '0'; - end generate SR; - AR : if SYNC_RESET = 0 generate - srst <= '0'; - arst <= rst_i; - end generate AR; - --- CRC process - crc_o <= crc; - zero <= (others => '0'); - - CRCP : process (clk_i, arst) - begin - if arst = '1' then -- async. reset - crc <= INIT_VALUE; - match_o <= '0'; - elsif rising_edge(clk_i) then - if srst = '1' then -- sync. reset - crc <= INIT_VALUE; - match_o <= '0'; - elsif clken_i = '1' then - crc <= crca(dw); - if crca(dw) = zero then - match_o <= '1'; - else - match_o <= '0'; - end if; - end if; - end if; - end process; - -end rtl; - Index: trunk/rtl/vhdl/ucrc_ser.vhd =================================================================== --- trunk/rtl/vhdl/ucrc_ser.vhd (revision 11) +++ trunk/rtl/vhdl/ucrc_ser.vhd (nonexistent) @@ -1,168 +0,0 @@ ----------------------------------------------------------------------- ----- ---- ----- Ultimate CRC. ---- ----- ---- ----- This file is part of the ultimate CRC projectt ---- ----- http://www.opencores.org/cores/ultimate_crc/ ---- ----- ---- ----- Description ---- ----- CRC generator/checker, serial implementation. ---- ----- ---- ----- ---- ----- To Do: ---- ----- - ---- ----- ---- ----- Author(s): ---- ----- - Geir Drange, gedra@opencores.org ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2005 Authors and OPENCORES.ORG ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.0 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU General Public License for more details.---- ----- ---- ----- You should have received a copy of the GNU General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.gnu.org/licenses/gpl.txt ---- ----- ---- ----------------------------------------------------------------------- --- --- CVS Revision History --- --- $Log: not supported by cvs2svn $ --- Revision 1.2 2005/05/09 19:26:58 gedra --- Moved match signal into clock enable --- --- Revision 1.1 2005/05/07 12:47:47 gedra --- Serial implementation. --- --- --- - -library ieee; -use ieee.std_logic_1164.all; - -entity ucrc_ser is - generic ( - POLYNOMIAL : std_logic_vector; - INIT_VALUE : std_logic_vector; - SYNC_RESET : integer range 0 to 1 := 0); -- use synchronous reset - port ( - clk_i : in std_logic; -- clock - rst_i : in std_logic; -- init CRC - clken_i : in std_logic; -- clock enable - data_i : in std_logic; -- data input - flush_i : in std_logic; -- flush crc - match_o : out std_logic; -- CRC match flag - crc_o : out std_logic_vector(POLYNOMIAL'length - 1 downto 0)); -- CRC output -end ucrc_ser; - -architecture rtl of ucrc_ser is - - constant msb : integer := POLYNOMIAL'length - 1; - constant init_msb : integer := INIT_VALUE'length - 1; - constant p : std_logic_vector(msb downto 0) := POLYNOMIAL; - signal din, crc_msb : std_logic_vector(msb downto 1); - signal crc, zero, fb : std_logic_vector(msb downto 0); - signal arst, srst : std_logic; - -begin - --- Parameter checking: Invalid generics will abort simulation/synthesis - PCHK : if msb /= init_msb generate - process - begin - report "POLYNOMIAL and INIT_VALUE vectors must be equal length!" - severity failure; - wait; - end process; - end generate PCHK; - - PCHK2 : if (msb < 3) or (msb > 31) generate - process - begin - report "POLYNOMIAL must be of order 4 to 32!" - severity failure; - wait; - end process; - end generate PCHK2; - - PCHK3 : if p(0) /= '1' generate -- LSB must be 1 - process - begin - report "POLYNOMIAL must have lsb set to 1!" - severity failure; - wait; - end process; - end generate PCHK3; - - zero <= (others => '0'); - crc_o <= crc; - --- Create vectors of data input and MSB of CRC - DI : for i in 1 to msb generate - din(i) <= data_i; - crc_msb(i) <= crc(msb); - end generate DI; - --- Feedback signals - fb(0) <= data_i xor crc(msb); - fb(msb downto 1) <= crc(msb-1 downto 0) xor ((din xor crc_msb) and p(msb downto 1)); - --- Reset signal - SR : if SYNC_RESET = 1 generate - srst <= rst_i; - arst <= '0'; - end generate SR; - AR : if SYNC_RESET = 0 generate - srst <= '0'; - arst <= rst_i; - end generate AR; - --- CRC process - CRCP : process (clk_i, arst) - begin - if arst = '1' then -- async. reset - crc <= INIT_VALUE; - match_o <= '0'; - elsif rising_edge(clk_i) then - if srst = '1' then -- sync. reset - crc <= INIT_VALUE; - match_o <= '0'; - else - if clken_i = '1' then - -- CRC generation - if flush_i = '1' then - crc(0) <= '0'; - crc(msb downto 1) <= crc(msb - 1 downto 0); - else - crc <= fb; - end if; - -- CRC match checker (if data plus CRC is clocked in without errors, - -- the CRC register ends up with all zeroes) - if fb = zero then - match_o <= '1'; - else - match_o <= '0'; - end if; - end if; - end if; - end if; - end process; - -end rtl; - Index: ultimate_crc/trunk/bench/vhdl/tb_crc.vhd =================================================================== --- ultimate_crc/trunk/bench/vhdl/tb_crc.vhd (nonexistent) +++ ultimate_crc/trunk/bench/vhdl/tb_crc.vhd (revision 12) @@ -0,0 +1,304 @@ +---------------------------------------------------------------------- +---- ---- +---- Ultimate CRC. ---- +---- ---- +---- This file is part of the ultimate CRC projectt ---- +---- http://www.opencores.org/cores/ultimate_crc/ ---- +---- ---- +---- Description ---- +---- Test bench for ultimate crc. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Geir Drange, gedra@opencores.org ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2005 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.0 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU General Public License for more details.---- +---- ---- +---- You should have received a copy of the GNU General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/gpl.txt ---- +---- ---- +---------------------------------------------------------------------- +-- +-- CVS Revision History +-- +-- $Log: not supported by cvs2svn $ +-- Revision 1.1 2005/05/09 16:07:45 gedra +-- test bench. +-- +-- +-- + +library ieee; +use ieee.std_logic_1164.all; +use work.ucrc_pkg.all; +use work.wb_tb_pack.all; + +entity tb_crc is + +end tb_crc; + +architecture behav of tb_crc is + + -- Polynomial under testing + constant POLYNOMIAL : std_logic_vector(15 downto 0) := + "0001000000100001"; -- x^16 + x^12 + x^5 + 1; + -- Initialization value + constant INIT_VALUE : std_logic_vector(15 downto 0) := "1111111111111111"; + -- Data width for the parallel implementation + constant DATA_WIDTH : integer := 8; + -- Number of bits + constant CODE_LENGTH : integer := 64 / DATA_WIDTH; + constant EXPECTED_CRC : std_logic_vector(POLYNOMIAL'length - 1 downto 0) := + "0110100100110101"; -- this must be updated if any parameter is changed! + signal clk, rst, d_o, d_v, flush, clken, pd_in : std_logic; + signal lsfr_reg : std_logic_vector(31 downto 0); + signal cnt : integer range 0 to CODE_LENGTH*DATA_WIDTH+10; + signal zero, match_s, match_p, chk_in, clken3 : std_logic; + signal data, par_in : std_logic_vector(DATA_WIDTH - 1 downto 0); + signal crc_s, crc_sc, crc_p : std_logic_vector(POLYNOMIAL'length - 1 downto 0); + signal pcnt : integer range 0 to DATA_WIDTH - 1; + signal one, check, par_clken, clken2, match_p2 : std_logic; + signal crc_p2 : std_logic_vector(31 downto 0); + signal data3 : std_logic_vector(159 downto 0); + +begin + + zero <= '0'; + one <= '1'; + + ---------------------------------------------------------------------------- + -- LFSR generates random bits as input to the CRC generators + ---------------------------------------------------------------------------- + LSFR : process (clk, rst) + begin + if rst = '1' then + lsfr_reg <= (others => '1'); + elsif rising_edge(clk) then + lsfr_reg(0) <= lsfr_reg(31) xor lsfr_reg(6) xor lsfr_reg(4) + xor lsfr_reg(2) xor lsfr_reg(1) xor lsfr_reg(0); + lsfr_reg(31 downto 1) <= lsfr_reg(30 downto 0); + end if; + end process; + + ---------------------------------------------------------------------------- + -- Serial to parallel data register, used to feed the parallel implementation + ---------------------------------------------------------------------------- + pd_in <= chk_in; -- Data plus CRC + par_in(DATA_WIDTH - 1) <= pd_in; + S2P : process (clk, rst) + begin + if rst = '1' then + par_in(DATA_WIDTH - 2 downto 0) <= (others => '0'); + par_clken <= '0'; + pcnt <= 0; + elsif rising_edge(clk) then + if clken = '1' then + par_in(DATA_WIDTH - 2) <= pd_in; + par_in(DATA_WIDTH - 3 downto 0) <= par_in(DATA_WIDTH - 2 downto 1); + if pcnt < DATA_WIDTH - 1 then + pcnt <= pcnt + 1; + else + pcnt <= 0; + end if; + if pcnt = DATA_WIDTH - 2 then + par_clken <= '1'; + else + par_clken <= '0'; + end if; + else + par_clken <= '0'; + end if; + end if; + end process; + + ---------------------------------------------------------------------------- + -- Bit counter and CRC control. Generates clken and flush signals for the + -- serial generator. + ---------------------------------------------------------------------------- + BCNT : process (clk, rst) + begin + if rst = '1' then + cnt <= 0; + flush <= '0'; + clken <= '0'; + elsif rising_edge(clk) then + if cnt < CODE_LENGTH*DATA_WIDTH+10 then + cnt <= cnt + 1; + end if; + if cnt >= DATA_WIDTH and cnt < CODE_LENGTH*DATA_WIDTH then + clken <= '1'; + else + clken <= '0'; + end if; + if (cnt >= CODE_LENGTH*DATA_WIDTH - POLYNOMIAL'length) and + (cnt < CODE_LENGTH*DATA_WIDTH) then + flush <= '1'; + else + flush <= '0'; + end if; + end if; + end process; + + ---------------------------------------------------------------------------- + -- Serial CRC generator. CRC is flushed out after the data block + ---------------------------------------------------------------------------- + SGEN : ucrc_ser + generic map ( + POLYNOMIAL => POLYNOMIAL, + INIT_VALUE => INIT_VALUE, + SYNC_RESET => 1) + port map ( + clk_i => clk, + rst_i => rst, + clken_i => clken, + data_i => lsfr_reg(0), + flush_i => flush, + match_o => open, + crc_o => crc_s); + + ---------------------------------------------------------------------------- + -- Serial CRC checker. Takes input from the serial generator, incl. CRC + ---------------------------------------------------------------------------- + chk_in <= lsfr_reg(0) when flush = '0' else crc_s(POLYNOMIAL'length - 1); + SCHK : ucrc_ser + generic map ( + POLYNOMIAL => POLYNOMIAL, + INIT_VALUE => INIT_VALUE, + SYNC_RESET => 1) + port map ( + clk_i => clk, + rst_i => rst, + clken_i => clken, + data_i => chk_in, + flush_i => zero, + match_o => match_s, + crc_o => crc_sc); + + ---------------------------------------------------------------------------- + -- Parallel CRC generator/checker. Takes input from the serial generator, + -- including the CRC + ---------------------------------------------------------------------------- + PGEN : ucrc_par + generic map ( + POLYNOMIAL => POLYNOMIAL, + INIT_VALUE => INIT_VALUE, + DATA_WIDTH => DATA_WIDTH, + SYNC_RESET => 1) + port map ( + clk_i => clk, + rst_i => rst, + clken_i => par_clken, + data_i => par_in, + match_o => match_p, + crc_o => crc_p); + + ---------------------------------------------------------------------------- + -- 128bit wide CRC generator + ---------------------------------------------------------------------------- + iucrc_par : ucrc_par + generic map ( + POLYNOMIAL => x"00018bb7", + INIT_VALUE => x"00000000", + DATA_WIDTH => 128, + SYNC_RESET => 1) + port map ( + clk_i => clk, + rst_i => rst, + clken_i => clken2, + data_i => (others => '1'), + match_o => open, + crc_o => crc_p2); + + ---------------------------------------------------------------------------- + -- 160bit wide CRC checker + ---------------------------------------------------------------------------- + iucrc_par2 : ucrc_par + generic map ( + POLYNOMIAL => x"00018bb7", + INIT_VALUE => x"00000000", + DATA_WIDTH => 160, + SYNC_RESET => 1) + port map ( + clk_i => clk, + rst_i => rst, + clken_i => clken3, + data_i => data3, + match_o => match_p2, + crc_o => open); + + data3(127 downto 0) <= (others => '1'); + lCpy : for i in 0 to 31 generate -- CRC must be MSB first! + data3(128 + i) <= crc_p2(31 - i); + end generate lCpy; + + ---------------------------------------------------------------------------- + -- Main test process + ---------------------------------------------------------------------------- + MAIN : process + begin + clken2 <= '0'; + clken3 <= '0'; + message("Simulation starts with a reset."); + rst <= '1'; + wait for 18 ns; + rst <= '0'; + wait_for_event("Wait for flushing of serial CRC generator", 1 ms, flush); + wait for 2 ns; + vector_check("CRC of serial generator", EXPECTED_CRC, crc_s); + vector_check("CRC of parallel generator", EXPECTED_CRC, crc_p); + wait_for_event("Wait for flush to finish", 500 ns, flush); + wait for 2 ns; + signal_check("Serial CRC match signal", '1', match_s); + signal_check("Parallel CRC match signal", '1', match_p); + message("Check 128bit crc:"); + wait until rising_edge(clk); + clken2 <= '1'; + wait until rising_edge(clk); + clken2 <= '0'; + wait until rising_edge(clk); + clken3 <= '1'; + wait until rising_edge(clk); + clken3 <= '0'; + signal_check("Parallel 128bit CRC check", '1', match_p2); + sim_report(""); + wait for 100 ns; + report "End of simulation! (ignore this failure)" + severity failure; + wait; + end process; + + ---------------------------------------------------------------------------- + -- Clock + ---------------------------------------------------------------------------- + CLOCK : process + begin + clk <= '0'; + wait for 5 ns; + clk <= '1'; + wait for 5 ns; + end process; + +end behav; + Index: ultimate_crc/trunk/bench/vhdl/wb_tb_pack.txt =================================================================== --- ultimate_crc/trunk/bench/vhdl/wb_tb_pack.txt (nonexistent) +++ ultimate_crc/trunk/bench/vhdl/wb_tb_pack.txt (revision 12) @@ -0,0 +1,2 @@ +wb_tb_pack.vhd is reused from the spdif project. Fetch the latest revision of +this file from there. \ No newline at end of file Index: ultimate_crc/trunk/rtl/vhdl/ucrc_ser.vhd =================================================================== --- ultimate_crc/trunk/rtl/vhdl/ucrc_ser.vhd (nonexistent) +++ ultimate_crc/trunk/rtl/vhdl/ucrc_ser.vhd (revision 12) @@ -0,0 +1,168 @@ +---------------------------------------------------------------------- +---- ---- +---- Ultimate CRC. ---- +---- ---- +---- This file is part of the ultimate CRC projectt ---- +---- http://www.opencores.org/cores/ultimate_crc/ ---- +---- ---- +---- Description ---- +---- CRC generator/checker, serial implementation. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Geir Drange, gedra@opencores.org ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2005 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.0 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU General Public License for more details.---- +---- ---- +---- You should have received a copy of the GNU General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/gpl.txt ---- +---- ---- +---------------------------------------------------------------------- +-- +-- CVS Revision History +-- +-- $Log: not supported by cvs2svn $ +-- Revision 1.2 2005/05/09 19:26:58 gedra +-- Moved match signal into clock enable +-- +-- Revision 1.1 2005/05/07 12:47:47 gedra +-- Serial implementation. +-- +-- +-- + +library ieee; +use ieee.std_logic_1164.all; + +entity ucrc_ser is + generic ( + POLYNOMIAL : std_logic_vector; + INIT_VALUE : std_logic_vector; + SYNC_RESET : integer range 0 to 1 := 0); -- use synchronous reset + port ( + clk_i : in std_logic; -- clock + rst_i : in std_logic; -- init CRC + clken_i : in std_logic; -- clock enable + data_i : in std_logic; -- data input + flush_i : in std_logic; -- flush crc + match_o : out std_logic; -- CRC match flag + crc_o : out std_logic_vector(POLYNOMIAL'length - 1 downto 0)); -- CRC output +end ucrc_ser; + +architecture rtl of ucrc_ser is + + constant msb : integer := POLYNOMIAL'length - 1; + constant init_msb : integer := INIT_VALUE'length - 1; + constant p : std_logic_vector(msb downto 0) := POLYNOMIAL; + signal din, crc_msb : std_logic_vector(msb downto 1); + signal crc, zero, fb : std_logic_vector(msb downto 0); + signal arst, srst : std_logic; + +begin + +-- Parameter checking: Invalid generics will abort simulation/synthesis + PCHK : if msb /= init_msb generate + process + begin + report "POLYNOMIAL and INIT_VALUE vectors must be equal length!" + severity failure; + wait; + end process; + end generate PCHK; + + PCHK2 : if (msb < 3) or (msb > 31) generate + process + begin + report "POLYNOMIAL must be of order 4 to 32!" + severity failure; + wait; + end process; + end generate PCHK2; + + PCHK3 : if p(0) /= '1' generate -- LSB must be 1 + process + begin + report "POLYNOMIAL must have lsb set to 1!" + severity failure; + wait; + end process; + end generate PCHK3; + + zero <= (others => '0'); + crc_o <= crc; + +-- Create vectors of data input and MSB of CRC + DI : for i in 1 to msb generate + din(i) <= data_i; + crc_msb(i) <= crc(msb); + end generate DI; + +-- Feedback signals + fb(0) <= data_i xor crc(msb); + fb(msb downto 1) <= crc(msb-1 downto 0) xor ((din xor crc_msb) and p(msb downto 1)); + +-- Reset signal + SR : if SYNC_RESET = 1 generate + srst <= rst_i; + arst <= '0'; + end generate SR; + AR : if SYNC_RESET = 0 generate + srst <= '0'; + arst <= rst_i; + end generate AR; + +-- CRC process + CRCP : process (clk_i, arst) + begin + if arst = '1' then -- async. reset + crc <= INIT_VALUE; + match_o <= '0'; + elsif rising_edge(clk_i) then + if srst = '1' then -- sync. reset + crc <= INIT_VALUE; + match_o <= '0'; + else + if clken_i = '1' then + -- CRC generation + if flush_i = '1' then + crc(0) <= '0'; + crc(msb downto 1) <= crc(msb - 1 downto 0); + else + crc <= fb; + end if; + -- CRC match checker (if data plus CRC is clocked in without errors, + -- the CRC register ends up with all zeroes) + if fb = zero then + match_o <= '1'; + else + match_o <= '0'; + end if; + end if; + end if; + end if; + end process; + +end rtl; + Index: ultimate_crc/trunk/rtl/vhdl/ucrc_pkg.vhd =================================================================== --- ultimate_crc/trunk/rtl/vhdl/ucrc_pkg.vhd (nonexistent) +++ ultimate_crc/trunk/rtl/vhdl/ucrc_pkg.vhd (revision 12) @@ -0,0 +1,88 @@ +---------------------------------------------------------------------- +---- ---- +---- Ultimate CRC. ---- +---- ---- +---- This file is part of the ultimate CRC projectt ---- +---- http://www.opencores.org/cores/ultimate_crc/ ---- +---- ---- +---- Description ---- +---- Ultimate CRC component declarations. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Geir Drange, gedra@opencores.org ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2005 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.0 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU General Public License for more details.---- +---- ---- +---- You should have received a copy of the GNU General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/gpl.txt ---- +---- ---- +---------------------------------------------------------------------- +-- +-- CVS Revision History +-- +-- $Log: not supported by cvs2svn $ +-- Revision 1.1 2005/05/09 15:56:14 gedra +-- Component declarations +-- +-- +-- + +library ieee; +use ieee.std_logic_1164.all; + +package ucrc_pkg is + + component ucrc_ser + generic ( + POLYNOMIAL : std_logic_vector; -- 4 to 32 bits + INIT_VALUE : std_logic_vector; + SYNC_RESET : integer range 0 to 1); -- use synchronous reset + port ( + clk_i : in std_logic; -- clock + rst_i : in std_logic; -- init CRC + clken_i : in std_logic; -- clock enable + data_i : in std_logic; -- data input + flush_i : in std_logic; -- flush crc + match_o : out std_logic; -- CRC match flag + crc_o : out std_logic_vector(POLYNOMIAL'length - 1 downto 0)); -- CRC output + end component; + + component ucrc_par + generic ( + POLYNOMIAL : std_logic_vector; + INIT_VALUE : std_logic_vector; + DATA_WIDTH : integer range 2 to 256; + SYNC_RESET : integer range 0 to 1); -- use synchronous reset + port ( + clk_i : in std_logic; -- clock + rst_i : in std_logic; -- init CRC + clken_i : in std_logic; -- clock enable + data_i : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- data input + match_o : out std_logic; -- CRC match flag + crc_o : out std_logic_vector(POLYNOMIAL'length - 1 downto 0)); -- CRC output + end component; + +end ucrc_pkg; Index: ultimate_crc/trunk/rtl/vhdl/ucrc_par.vhd =================================================================== --- ultimate_crc/trunk/rtl/vhdl/ucrc_par.vhd (nonexistent) +++ ultimate_crc/trunk/rtl/vhdl/ucrc_par.vhd (revision 12) @@ -0,0 +1,176 @@ +---------------------------------------------------------------------- +---- ---- +---- Ultimate CRC. ---- +---- ---- +---- This file is part of the ultimate CRC projectt ---- +---- http://www.opencores.org/cores/ultimate_crc/ ---- +---- ---- +---- Description ---- +---- CRC generator/checker, parallel implementation. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Geir Drange, gedra@opencores.org ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2005 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.0 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU General Public License for more details.---- +---- ---- +---- You should have received a copy of the GNU General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/gpl.txt ---- +---- ---- +---------------------------------------------------------------------- +-- +-- CVS Revision History +-- +-- $Log: not supported by cvs2svn $ +-- Revision 1.1 2005/05/09 15:58:38 gedra +-- Parallel implementation +-- +-- +-- + +library ieee; +use ieee.std_logic_1164.all; + +entity ucrc_par is + generic ( + POLYNOMIAL : std_logic_vector; + INIT_VALUE : std_logic_vector; + DATA_WIDTH : integer range 2 to 256; + SYNC_RESET : integer range 0 to 1); -- use sync./async reset + port ( + clk_i : in std_logic; -- clock + rst_i : in std_logic; -- init CRC + clken_i : in std_logic; -- clock enable + data_i : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- data input + match_o : out std_logic; -- CRC match flag + crc_o : out std_logic_vector(POLYNOMIAL'length - 1 downto 0)); -- CRC output +end ucrc_par; + +architecture rtl of ucrc_par is + + constant msb : integer := POLYNOMIAL'length - 1; + constant init_msb : integer := INIT_VALUE'length - 1; + constant p : std_logic_vector(msb downto 0) := POLYNOMIAL; + constant dw : integer := DATA_WIDTH; + constant pw : integer := POLYNOMIAL'length; + type fb_array is array (dw downto 1) of std_logic_vector(msb downto 0); + type dmsb_array is array (dw downto 1) of std_logic_vector(msb downto 1); + signal crca : fb_array; + signal da, ma : dmsb_array; + signal crc, zero : std_logic_vector(msb downto 0); + signal arst, srst : std_logic; + +begin + +-- Parameter checking: Invalid generics will abort simulation/synthesis + PCHK1 : if msb /= init_msb generate + process + begin + report "POLYNOMIAL and INIT_VALUE vectors must be equal length!" + severity failure; + wait; + end process; + end generate PCHK1; + + PCHK2 : if (msb < 3) or (msb > 31) generate + process + begin + report "POLYNOMIAL must be of order 4 to 32!" + severity failure; + wait; + end process; + end generate PCHK2; + + PCHK3 : if p(0) /= '1' generate -- LSB must be 1 + process + begin + report "POLYNOMIAL must have lsb set to 1!" + severity failure; + wait; + end process; + end generate PCHK3; + +-- Generate vector of each data bit + CA : for i in 1 to dw generate -- data bits + DAT : for j in 1 to msb generate + da(i)(j) <= data_i(i - 1); + end generate DAT; + end generate CA; + +-- Generate vector of each CRC MSB + MS0 : for i in 1 to msb generate + ma(1)(i) <= crc(msb); + end generate MS0; + MSP : for i in 2 to dw generate + MSU : for j in 1 to msb generate + ma(i)(j) <= crca(i - 1)(msb); + end generate MSU; + end generate MSP; + +-- Generate feedback matrix + crca(1)(0) <= da(1)(1) xor crc(msb); + crca(1)(msb downto 1) <= crc(msb - 1 downto 0) xor ((da(1) xor ma(1)) and p(msb downto 1)); + FB : for i in 2 to dw generate + crca(i)(0) <= da(i)(1) xor crca(i - 1)(msb); + crca(i)(msb downto 1) <= crca(i - 1)(msb - 1 downto 0) xor + ((da(i) xor ma(i)) and p(msb downto 1)); + end generate FB; + +-- Reset signal + SR : if SYNC_RESET = 1 generate + srst <= rst_i; + arst <= '0'; + end generate SR; + AR : if SYNC_RESET = 0 generate + srst <= '0'; + arst <= rst_i; + end generate AR; + +-- CRC process + crc_o <= crc; + zero <= (others => '0'); + + CRCP : process (clk_i, arst) + begin + if arst = '1' then -- async. reset + crc <= INIT_VALUE; + match_o <= '0'; + elsif rising_edge(clk_i) then + if srst = '1' then -- sync. reset + crc <= INIT_VALUE; + match_o <= '0'; + elsif clken_i = '1' then + crc <= crca(dw); + if crca(dw) = zero then + match_o <= '1'; + else + match_o <= '0'; + end if; + end if; + end if; + end process; + +end rtl; + Index: ultimate_crc/trunk/doc/ultimate_crc.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: ultimate_crc/trunk/doc/ultimate_crc.pdf =================================================================== --- ultimate_crc/trunk/doc/ultimate_crc.pdf (nonexistent) +++ ultimate_crc/trunk/doc/ultimate_crc.pdf (revision 12)

ultimate_crc/trunk/doc/ultimate_crc.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: ultimate_crc/trunk/doc/src/ultimate_crc.doc =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: ultimate_crc/trunk/doc/src/ultimate_crc.doc =================================================================== --- ultimate_crc/trunk/doc/src/ultimate_crc.doc (nonexistent) +++ ultimate_crc/trunk/doc/src/ultimate_crc.doc (revision 12)

ultimate_crc/trunk/doc/src/ultimate_crc.doc Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: ultimate_crc/trunk/doc/copying.txt =================================================================== --- ultimate_crc/trunk/doc/copying.txt (nonexistent) +++ ultimate_crc/trunk/doc/copying.txt (revision 12) @@ -0,0 +1,340 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc. + 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. By contrast, the GNU General Public +License is intended to guarantee your freedom to share and change free +software--to make sure the software is free for all its users. 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For software which is copyrighted by the Free +Software Foundation, write to the Free Software Foundation; we sometimes +make exceptions for this. Our decision will be guided by the two goals +of preserving the free status of all derivatives of our free software and +of promoting the sharing and reuse of software generally. + + NO WARRANTY + + 11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY +FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN +OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES +PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED +OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS +TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE +PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, +REPAIR OR CORRECTION. + + 12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING +WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR +REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, +INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING +OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED +TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY +YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER +PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. + + END OF TERMS AND CONDITIONS + + How to Apply These Terms to Your New Programs + + If you develop a new program, and you want it to be of the greatest +possible use to the public, the best way to achieve this is to make it +free software which everyone can redistribute and change under these terms. + + To do so, attach the following notices to the program. It is safest +to attach them to the start of each source file to most effectively +convey the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + + Copyright (C) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) year name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + , 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Library General +Public License instead of this License. Index: ultimate_crc/trunk =================================================================== --- ultimate_crc/trunk (nonexistent) +++ ultimate_crc/trunk (revision 12)

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ultimate_crc/web_uploads Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: ultimate_crc/branches =================================================================== --- ultimate_crc/branches (nonexistent) +++ ultimate_crc/branches (revision 12)

ultimate_crc/branches Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: ultimate_crc/tags =================================================================== --- ultimate_crc/tags (nonexistent) +++ ultimate_crc/tags (revision 12)

ultimate_crc/tags Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ##

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