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URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

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Rev 12 → Rev 13

/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/src/NoC/ni.v
28,7 → 28,7
must be updated by cpu in the first word of the packet
3-status register: provide information about the current status of the router
status_reg = {all_vcs_full,any_vc_has_data,rd_no_pck_err,rd_ovr_size_err,rd_done,wr_done};
status_reg = {ni_isr,all_vcs_full,any_vc_has_data,rd_no_pck_err,rd_ovr_size_err,rd_done,wr_done};
RD/WR registers ={pck_size_next,memory_ptr_next}
Info: monemi@fkegraduate.utm.my
104,9 → 104,12
output m_we_o,
 
input [W_DATA_WIDTH-1 : 0] m_dat_i,
input m_ack_i
input m_ack_i,
//intruupt interface
output irq
);
`LOG2
178,6 → 181,7
assign s_ack_o_next = s_chipselect & (~s_ack_o);
assign m_cti_o = (m_stb_o) ? ((last_rw)? 3'b111 : 3'b010) : 3'b000;
reg ni_isr,ni_isr_next;
reg [NUMBER_OF_STATUS-1 : 0] ps,ns;
246,6 → 250,8
wire [VC_NUM_PER_PORT-1 :0] full_vc;
wire [VC_NUM_PER_PORT-1 :0] cand_wr_vc;
assign irq = ni_isr;
assign all_vcs_full = & full_vc;
assign cand_wr_vc_full = | ( full_vc & cand_wr_vc);
279,7 → 285,7
//status register
assign status_reg = {all_vcs_full,any_vc_has_data,rd_no_pck_err,rd_ovr_size_err,rd_done,wr_done};
assign status_reg = {ni_isr,all_vcs_full,any_vc_has_data,rd_no_pck_err,rd_ovr_size_err,rd_done,wr_done};
assign s_readdata = status_reg;
assign prog_mode_en_next = flit_in_hdr_flg & (flit_in [`FLIT_IN_WR_RAM_LOC]== 1'b1);
326,6 → 332,7
//hdr_write <= 1'b0;
m_ack_i_delayed <= 1'b0;
s_ack_o <= 1'b0;
ni_isr <= 1'b0;
end else begin //if reset
ps <= ns;
347,6 → 354,7
//hdr_write <= hdr_write_next;
m_ack_i_delayed <= m_ack_i;
s_ack_o <= s_ack_o_next;
ni_isr <= ni_isr_next;
end//els reset
end//always
532,8 → 540,16
end
//isr_register handeling
always @(*) begin
ni_isr_next = ni_isr;
if(any_vc_has_data) ni_isr_next = 1'b1;
if(s_chipselect & s_write & (s_address == SLAVE_STATUS_ADDR) & s_writedata[`NI_ISR_LOC]) ni_isr_next = 1'b0;
end
 
 
fifo_buffer #(
.VC_NUM_PER_PORT (VC_NUM_PER_PORT),
.FLIT_WIDTH (FLIT_WIDTH ),
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/src/IP_core/aeMB_IP.v
57,7 → 57,7
parameter TIMER_INT_NUM =1,
 
//int_ctrl parameters
parameter INT_CTRL_INT_NUM = (EXT_INT_EN*EXT_INT_NUM) + (TIMER_EN * TIMER_INT_NUM),
parameter INT_CTRL_INT_NUM =3, //ext_int,timer,ni
parameter INT_CTRL_ADDR_WIDTH =3,
//gpio parameters
180,9 → 180,9
 
 
wire sys_int_i,timer_irq;
wire [EXT_INT_NUM-1 : 0 ] ext_int_o;
//intrrupts signals
wire sys_int_i,timer_irq,ni_irq,ext_int_irq;
wire [INT_CTRL_INT_NUM-1 : 0 ] int_ctrl_in;
wire [SLAVE_ADDR_ARRAY_WIDTH-1 : 0 ] bus_slave_adr_o;
453,7 → 453,8
.m_cyc_o (master_cyc_o [NOC_M_ID]) ,
.m_we_o (master_wre_o [NOC_M_ID]) ,
.m_dat_i (master_dat_i [NOC_M_ID]) ,
.m_ack_i (master_ack_i [NOC_M_ID])
.m_ack_i (master_ack_i [NOC_M_ID]) ,
.irq (ni_irq)
);
 
assign master_adr_o [NOC_M_ID] [ADDR_WIDTH-1 : AEMB_RAM_WIDTH_IN_WORD] = {ADDR_WIDTH-AEMB_RAM_WIDTH_IN_WORD{1'b0}};
462,6 → 463,7
assign flit_out ={FLIT_WIDTH{1'bX}};
assign flit_out_wr = 1'bX;
assign credit_out ={VC_NUM_PER_PORT{1'bX}};
assign ni_irq = 1'b0;
end
if(EXT_INT_EN) begin : ext_in_gen
472,27 → 474,26
.ADDR_WIDTH (EXT_INT_ADDR_WIDTH)
)the_ext_int
(
.clk (clk),
.reset (reset),
.sa_dat_i (slave_dat_i [EXT_INT_ID][EXT_INT_NUM-1 :0]) ,
.sa_sel_i (slave_sel_i [EXT_INT_ID]),
.sa_addr_i (slave_addr_i [EXT_INT_ID][EXT_INT_ADDR_WIDTH-1 :0]) ,
.sa_stb_i (slave_stb_i [EXT_INT_ID]) ,
.sa_we_i (slave_we_i [EXT_INT_ID]) ,
.sa_dat_o (slave_dat_o [EXT_INT_ID][EXT_INT_NUM-1 :0]) ,
.sa_ack_o (slave_ack_o [EXT_INT_ID]) ,
.ext_int_i (ext_int_i),
.ext_int_o (ext_int_o)//output to the interrupt controller
.clk (clk),
.reset (reset),
.sa_dat_i (slave_dat_i [EXT_INT_ID][EXT_INT_NUM-1 :0]) ,
.sa_sel_i (slave_sel_i [EXT_INT_ID]),
.sa_addr_i (slave_addr_i [EXT_INT_ID][EXT_INT_ADDR_WIDTH-1 :0]) ,
.sa_stb_i (slave_stb_i [EXT_INT_ID]) ,
.sa_we_i (slave_we_i [EXT_INT_ID]) ,
.sa_dat_o (slave_dat_o [EXT_INT_ID][EXT_INT_NUM-1 :0]) ,
.sa_ack_o (slave_ack_o [EXT_INT_ID]) ,
.ext_int_i (ext_int_i),
.ext_int_o (ext_int_irq)//output to the interrupt controller
);
);
assign slave_dat_o [EXT_INT_ID][DATA_WIDTH-1 :EXT_INT_NUM] = {(DATA_WIDTH-EXT_INT_NUM){1'b0}};
assign slave_dat_o [EXT_INT_ID][DATA_WIDTH-1 :EXT_INT_NUM] = {(DATA_WIDTH-EXT_INT_NUM){1'b0}};
end else begin // EXT_INT_EN
assign ext_int_irq = 1'b0;
end
end // EXT_INT_EN
if(TIMER_EN) begin :timer_gen
// wire timer_irq;
513,13 → 514,18
.irq (timer_irq)
);
end //TIMER_EN
end else begin //TIMER_EN
assign timer_irq = 1'b0;
end
if(INT_CTRL_EN) begin : int_ctrl_gen
int_ctrl #(
.INT_NUM (INT_CTRL_INT_NUM),
.DATA_WIDTH (DATA_WIDTH),
.ADDR_WIDTH (INT_CTRL_ADDR_WIDTH)
.NOC_EN (NOC_EN),
.EXT_INT_EN (EXT_INT_EN),
.TIMER_EN (TIMER_EN),
.INT_NUM (INT_CTRL_INT_NUM),
.DATA_WIDTH (DATA_WIDTH),
.ADDR_WIDTH (INT_CTRL_ADDR_WIDTH)
)
int_ctrl_gen
(
536,11 → 542,8
.int_i (int_ctrl_in),
.int_o (sys_int_i)
);
if(EXT_INT_EN && TIMER_EN) assign int_ctrl_in = {timer_irq,ext_int_o};
else if(EXT_INT_EN) assign int_ctrl_in = ext_int_o;
else assign int_ctrl_in = timer_irq;
assign int_ctrl_in = {ext_int_irq,timer_irq,ni_irq};
end //INT_CTRL_EN
else begin
assign sys_int_i= 1'b0;
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/src/IP_core/int_ctrl.v
1,8 → 1,11
module int_ctrl #(
parameter INT_NUM = 4,
parameter NOC_EN = 0,
parameter EXT_INT_EN = 1,
parameter TIMER_EN = 1,
parameter INT_NUM = 32,
parameter DATA_WIDTH = 32,
parameter SEL_WIDTH = 4,
parameter ADDR_WIDTH = 3
parameter ADDR_WIDTH = 3
 
 
)
28,7 → 31,8
localparam [ADDR_WIDTH-1 : 0] IAR_REG_ADDR = 2;
localparam [ADDR_WIDTH-1 : 0] IPR_REG_ADDR = 3;
localparam LD_ZERO = (INT_NUM >2 )? INT_NUM-2 : 0;
localparam DATA_BUS_MASK = (EXT_INT_EN <<2) + (TIMER_EN << 1)+ NOC_EN ;
//internal register
reg [INT_NUM-1 : 0] ipr,ier,iar;
reg [INT_NUM-1 : 0] ipr_next,ier_next,iar_next;
35,12 → 39,15
reg [INT_NUM-1 : 0] read,read_next;
reg [1:0] mer,mer_next;
wire [INT_NUM-1:0] sa_dat_i_masked, int_i_masked;
assign sa_dat_i_masked = sa_dat_i & DATA_BUS_MASK;
assign int_i_masked = int_i & DATA_BUS_MASK;
always@(*) begin
mer_next = mer;
ier_next = ier;
iar_next = iar & ~int_i;
ipr_next = (ipr | int_i) & ier;
iar_next = iar & ~ int_i_masked;
ipr_next = (ipr | int_i_masked) & ier;
read_next = read;
if(sa_stb_i )
47,17 → 54,17
if(sa_we_i ) begin
case(sa_addr_i)
MER_REG_ADDR: mer_next = sa_dat_i[1:0];
IER_REG_ADDR: ier_next = sa_dat_i[INT_NUM-1 : 0];
IER_REG_ADDR: ier_next = sa_dat_i_masked[INT_NUM-1 : 0];
IAR_REG_ADDR: begin
iar_next = iar | sa_dat_i[INT_NUM-1 : 0];//set iar by writting 1
ipr_next = ipr & ~sa_dat_i[INT_NUM-1 : 0];//reset ipr by writting 1
iar_next = iar | sa_dat_i_masked[INT_NUM-1 : 0];//set iar by writting 1
ipr_next = ipr & ~sa_dat_i_masked[INT_NUM-1 : 0];//reset ipr by writting 1
end
default: ipr_next = ipr | int_i;
default: ipr_next = ipr | int_i_masked;
endcase
end//we
else begin
case(sa_addr_i)
MER_REG_ADDR: read_next = mer;
MER_REG_ADDR: read_next = {{LD_ZERO{1'b0}},mer};
IER_REG_ADDR: read_next = ier;
IAR_REG_ADDR: read_next = iar;
IPR_REG_ADDR: read_next = ipr;
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/src/IP_core/ext_int.v
17,7 → 17,7
output reg sa_ack_o,
//interrupt ports
input [EXT_INT_NUM-1 : 0] ext_int_i,
output [EXT_INT_NUM-1 : 0] ext_int_o //output to the interrupt controller
output ext_int_o //output to the interrupt controller
);
 
93,7 → 93,7
assign sa_dat_o = read;
assign ext_int_o= isr;
assign ext_int_o = |isr;
endmodule
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/src/define.v
205,6 → 205,8
`define NI_RD_OVR_ERR_LOC 2
`define NI_RD_NPCK_ERR_LOC 3
`define NI_HAS_PCK_LOC 4
`define NI_ALL_VCS_FULL_LOC 5
`define NI_ISR_LOC 6
`define NI_PTR_WIDTH 19
`define NI_PCK_SIZE_WIDTH 13
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/compile/system.h
23,8 → 23,8
#define GPIO_READ_REG 8
 
#define GPIO_TYPE_LOC_START (GPIO_ADDR_REG_WIDTH + GPIO_ADDR_PORT_WIDTH)
#define GPIO_PORT_LOC_START (GPIO_ADDR_REG_WIDTH+2)
#define GPIO_TYPE_LOC_START (GPIO_ADDR_REG_WIDTH + GPIO_ADDR_PORT_WIDTH)
#define GPIO_PORT_LOC_START (GPIO_ADDR_REG_WIDTH+2)
 
#define GPIO_IO_BASE (GPIO_BASE + (GPIO_IO_TYPE_NUM << GPIO_TYPE_LOC_START))
42,11 → 42,11
#define gpio_o_wr(port_num,val) gpio_o_wr_reg(port_num)=val
 
//EXT_INT
#define EXT_INT_GER (*((volatile unsigned int *) (EXT_INT_BASE )))
#define EXT_INT_IER_RISE (*((volatile unsigned int *) (EXT_INT_BASE+4 )))
#define EXT_INT_IER_FALL (*((volatile unsigned int *) (EXT_INT_BASE+8 )))
#define EXT_INT_ISR (*((volatile unsigned int *) (EXT_INT_BASE+12 )))
#define EXT_INT_RD (*((volatile unsigned int *) (EXT_INT_BASE+16 )))
#define EXT_INT_GER (*((volatile unsigned int *) (EXT_INT_BASE )))
#define EXT_INT_IER_RISE (*((volatile unsigned int *) (EXT_INT_BASE+4 )))
#define EXT_INT_IER_FALL (*((volatile unsigned int *) (EXT_INT_BASE+8 )))
#define EXT_INT_ISR (*((volatile unsigned int *) (EXT_INT_BASE+12 )))
#define EXT_INT_RD (*((volatile unsigned int *) (EXT_INT_BASE+16 )))
53,7 → 53,7
 
//TIMER
#define TCSR0 (*((volatile unsigned int *) (TIMER_BASE )))
#define TCSR0 (*((volatile unsigned int *) (TIMER_BASE )))
/*
//timer control register
65,50 → 65,56
1 : int_enble_on_cmp_value
0 : timer enable
*/
#define TLR0 (*((volatile unsigned int *) (TIMER_BASE+4 )))
#define TCMP0 (*((volatile unsigned int *) (TIMER_BASE+8 )))
#define TLR0 (*((volatile unsigned int *) (TIMER_BASE+4 )))
#define TCMP0 (*((volatile unsigned int *) (TIMER_BASE+8 )))
#define TIMER_EN 1
#define TIMER_INT_EN 2
#define TIMER_RST_ON_CMP 4
#define TIMER_EN (1 << 0)
#define TIMER_INT_EN (1 << 1)
#define TIMER_RST_ON_CMP (1 << 2)
 
//INT CONTROLLER
 
#define INTC_MER (*((volatile unsigned int *) (INT_CTRL_BASE )))
#define INTC_IER (*((volatile unsigned int *) (INT_CTRL_BASE+4 )))
#define INTC_IAR (*((volatile unsigned int *) (INT_CTRL_BASE+8 )))
#define INTC_IPR (*((volatile unsigned int *) (INT_CTRL_BASE+12 )))
 
#define INTC_MER (*((volatile unsigned int *) (INT_CTRL_BASE )))
#define INTC_IER (*((volatile unsigned int *) (INT_CTRL_BASE+4 )))
#define INTC_IAR (*((volatile unsigned int *) (INT_CTRL_BASE+8 )))
#define INTC_IPR (*((volatile unsigned int *) (INT_CTRL_BASE+12 )))
#define NI_INT (1 << 0)
#define TIMER_INT (1 << 1)
#define EXT_INT (1 << 2)
//SHARED RAM
#define RAM_X 2
#define RAM_Y 2
#define RAM_ADDR core_addr(RAM_X, RAM_Y)
#define RAM_X 2
#define RAM_Y 2
#define RAM_ADDR core_addr(RAM_X, RAM_Y)
 
 
//NOC
#define X_Y_ADDR_WIDTH_IN_HDR 4
#define NI_PTR_WIDTH 19
#define NI_PCK_SIZE_WIDTH 13
#define NIC_WR_DONE_LOC 1<<0
#define NIC_RD_DONE_LOC 1<<1
#define NIC_RD_OVR_ERR_LOC 1<<2
#define NIC_RD_NPCK_ERR_LOC 1<<3
#define NIC_HAS_PCK_LOC 1<<4
#define X_Y_ADDR_WIDTH_IN_HDR 4
#define NI_PTR_WIDTH 19
#define NI_PCK_SIZE_WIDTH 13
 
#define NIC_RD (*((volatile unsigned int *) (NOC_BASE )))
#define NIC_WR (*((volatile unsigned int *) (NOC_BASE+4)))
#define NIC_ST (*((volatile unsigned int *) (NOC_BASE+8)))
#define NIC_WR_DONE_LOC (1<<0)
#define NIC_RD_DONE_LOC (1<<1)
#define NIC_RD_OVR_ERR_LOC (1<<2)
#define NIC_RD_NPCK_ERR_LOC (1<<3)
#define NIC_HAS_PCK_LOC (1<<4)
#define NIC_ISR (1<<5)
 
#define NIC_RD (*((volatile unsigned int *) (NOC_BASE )))
#define NIC_WR (*((volatile unsigned int *) (NOC_BASE+4)))
#define NIC_ST (*((volatile unsigned int *) (NOC_BASE+8)))
 
 
#define core_addr(DES_X, DES_Y) ((DES_X << X_Y_ADDR_WIDTH_IN_HDR) + DES_Y)<<(32-3-(2*X_Y_ADDR_WIDTH_IN_HDR))
#define core_addr(DES_X, DES_Y) ((DES_X << X_Y_ADDR_WIDTH_IN_HDR) + DES_Y)<<(32-3-(2*X_Y_ADDR_WIDTH_IN_HDR))
#define wait_for_sending_pck() while (!(NIC_ST & NIC_WR_DONE_LOC))
#define wait_for_sending_pck() while (!(NIC_ST & NIC_WR_DONE_LOC))
#define wait_for_reading_pck() while (!(NIC_ST & NIC_RD_DONE_LOC))
 
#define wait_for_getting_pck() while (!(NIC_ST & NIC_HAS_PCK_LOC))
#define wait_for_getting_pck() while (!(NIC_ST & NIC_HAS_PCK_LOC))
 
/*****************************************
void send_pck (unsigned int * pck_buffer, unsigned int data_size);
122,6 → 128,8
inline void send_pck (unsigned int des_x,unsigned int des_y,unsigned int * pck_buffer, unsigned int data_size, unsigned int flags){
pck_buffer [0] = core_addr(des_x, des_y) | flags ;
NIC_WR = (unsigned int) (& pck_buffer [0]) + (data_size<<NI_PTR_WIDTH);
wait_for_sending_pck();
 
}
 
/*******************************************
131,6 → 139,7
********************************************/
inline void save_pck (unsigned int * pck_buffer, unsigned int buffer_size){
NIC_RD = (unsigned int) (& pck_buffer [0]) + (buffer_size<<NI_PTR_WIDTH);
wait_for_reading_pck();
}
 
145,7 → 154,6
unsigned int ack_buff[3];
buffer[1] = start_address;
send_pck (RAM_X,RAM_Y,buffer,size+1,0x3); //send write request packet
wait_for_sending_pck();
wait_for_getting_pck(); //wait for ack paket from sdram
save_pck (ack_buff,3);
}
160,7 → 168,7
void write_on_ram_no_ack(unsigned int * buffer, unsigned int start_address,unsigned int size){
buffer[1] = start_address;
send_pck (RAM_X,RAM_Y,buffer,size+1,0x1); //send write request packet
wait_for_sending_pck();
}
 
/**************************
176,7 → 184,6
buffer[1] = start_address;
buffer[2] = size;
send_pck (RAM_X,RAM_Y,buffer,2,0x00);
wait_for_sending_pck();
wait_for_getting_pck();
save_pck (buffer,size+1);
}
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu00_00.c
4,20 → 4,18
#include "system.h"
 
 
#define EXT_INT_EN 1
#define TIMER_EN 1
#define EXT_INT_NUM 3
 
#define TIMER_INT (1<<(EXT_INT_NUM*EXT_INT_EN))
 
#define EXT_INT_1 (1<<0)
#define EXT_INT_2 (1<<1)
#define EXT_INT_3 (1<<2)
 
#define EXT_INT_ALL (EXT_INT_1 | EXT_INT_2 | EXT_INT_3) // ((1<<EXT_INT_NUM)-1)
 
 
const unsigned int seven_seg_tab [16] = {0x3F,0x06,0x5B,0x4F,0x66,0x6D,0x7D,0x07,0x7F,0x6F,0x77,0x7C,0x39,0x5E, 0x79,0x71};
 
void delay(unsigned int);
void ni_ISR ( void );
void timer_ISR( void );
void ext_int_ISR( void );
 
39,12 → 37,13
void myISR( void ) __attribute__ ((interrupt_handler));
 
 
unsigned int i;
unsigned int i=0;
 
void myISR( void )
{
if( INTC_IPR & NI_INT ) ni_ISR();
if( INTC_IPR & TIMER_INT ) timer_ISR();
if( INTC_IPR & EXT_INT_ALL ) ext_int_ISR();
if( INTC_IPR & EXT_INT) ext_int_ISR();
INTC_IAR = INTC_IPR; // Acknowledge Interrupts
}
 
62,15 → 61,26
void ext_int_ISR( void )
{
// Do Stuff Here
if(INTC_IPR & EXT_INT_1) i=0xDEADBEAF;
if(INTC_IPR & EXT_INT_2) i=0x12345678;
if(INTC_IPR & EXT_INT_3) i=0xAAAAAAAA;
if(EXT_INT_ISR & EXT_INT_1) i=0xDEADBEAF;
if(EXT_INT_ISR & EXT_INT_2) i=0x12345678;
if(EXT_INT_ISR & EXT_INT_3) i=0xAAAAAAAA;
EXT_INT_ISR = EXT_INT_ISR;
// Clear any pending button interrupts
}
 
unsigned int ni_buffer [32];
 
void ni_ISR( void )
{
// Do Stuff Here
save_pck (ni_buffer, 32);
i += 0x11111111;
NIC_ST = NIC_ST;
// Clear any pending button interrupts
}
 
 
int main()
{
unsigned int j,hex_val;
79,14 → 89,14
EXT_INT_IER_RISE=EXT_INT_ALL;
EXT_INT_GER =0x3;
EXT_INT_IER_RISE = EXT_INT_1 | EXT_INT_2 | EXT_INT_3;
EXT_INT_GER = 0x3;
 
TCMP0 = 50000000;
TCSR0 = ( TIMER_EN | TIMER_INT_EN | TIMER_RST_ON_CMP);
 
INTC_IER=EXT_INT_ALL|TIMER_INT;
INTC_MER=0x3;
INTC_IER= EXT_INT | TIMER_INT | NI_INT;
INTC_MER= 0x3;
 
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu00_01.c
25,7 → 25,7
while(1){
for (i=1;i<BUFFER_SIZE;i++) buffer [i] = i;
send_pck (DES_X,DES_Y,buffer,2,0x00);
wait_for_sending_pck();
 
}
 
/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk/noc_based_mpsoc/sw/mpsoc_code/cpu01_00.c
6,15 → 6,37
void delay(unsigned int);
 
 
unsigned int buffer [32];
 
 
 
 
 
 
int main()
{
int i;
for (i=1;i<32;i++) buffer [i] = i;
for (i=1;i<32;i++) {
delay(5000000);
send_pck (0,0,buffer,30,0x00);
wait_for_sending_pck();
delay(50000000);
send_pck (0,0,buffer,31,0x00);
wait_for_sending_pck();
}
while(1)
{
gpio_o_wr(0,1);
delay(50000);
delay(500000);
 
gpio_o_wr(0,0);
delay(50000);
delay(500000);
}//while
return 0;
}

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